Junior Responsibilities / Accomplishments

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AMIQ Consulting is looking for Verification Engineers with all levels of expertise in functional hardware verification domain.

As
a member of the AMIQ consulting team, the Verification Engineer must be able to carry out independent tasks with little
supervision and collaborate closely with both customers and other team members. This position requires dealing with
customers located abroad. On-site visits of various durations will be needed. The person in this position must enjoy being part
of a young, creative and open-minded team and working in multi-cultural environments as the client sites are. Passion,
initiative and the ability to wear many hats are highly appreciated.
Junior Responsibilities / Accomplishments
o Learn the functional verification domain specific knowledge
o Find and implement solutions for exercises
o Run simulations and debug issues found along the way and do the root cause analysis
o Contribute to project's infrastructure if needed (scripts, make-files, etc)
o Document code and write help according to trainer's requirements
o Consult with team members and/or trainer on solutions and issue handling
Junior Required Skills and Qualifications
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Junior Desired:
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Good background in digital circuits or hardware design


Practical experience(6+ months) with OOP (eg Java, C++)
Familiar with a digital circuit simulator (modelsim, ncsim, virsim)
Familiar with Linux and Shell scripting
Proactive and good problem solver
Fast learner; ability to quickly come up to speed on new technology concepts
Strong interpersonal and communication skills
Good English communication skills (both in written and verbal)
Availability to work abroad for various periods of time
Bachelor degree in Electronics/Telecommunications, Computer Science, Mathematics
Experience with Verilog or VHDL
Personal software/hardware projects

Senior Responsibilities / Accomplishments


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Understand the specification of the device under verification and develop the verification plan
Report DUV specification issues to customer
Develop and debug the verification environment, complying with customer's required methodology
Run and debug simulations or regressions until verification goals are achieved
Debug RTL issues and report them to customer
Perform environment maintenance activities
Contribute to the project's infrastructure if needed (scripts, make-files, etc)
Document code and write Help documents according to customer's requirements
Consult with team members and/or customer on solutions and issue handling
Participate in reviews and pro-actively contribute to the verification project
Report progress to customer's management or responsible persons

Senior Required Skills and Qualifications


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Solid experience (5+ years) with one or more of the SystemVerilog, e, Vera or SystemC languages and the associated
methodologies OVM/UVM, eRM and VMM
Programming experience with C/C++ or Java
Experience with eVC/UVCs development
Excellent knowledge of the functional verification tool chain (simulators, linters, regression managers etc)
Excellent knowledge of functional verification flow and support tools (issue tracking, source control, release process)
Proficiency in Linux and Shell scripting
Demonstrated success in previous projects
Ability to prioritize, schedule and meet deadlines
Proactive and good problem solver, having the capability to cope with incomplete specifications
Strong sense of accountability and follow through
Strong interpersonal and communication skills
Good English communication skills (both in written and verbal)
Availability to work abroad for short periods of time
Bachelor degree in Electronics/Telecommunications, Computer Science, Mathematics

Senior Desired:
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Design experience with Verilog or VHDL, or FPGA prototyping

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Practical knowledge in developing SystemC or Matlab models


Experience with TLM/TBA modeling
SW Design Patterns knowledge

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