An 11.

1Gbps Analog PRML Receiver for EDC of

up to 400km-Reach WDM Fiber-Optic Links
Salam Elahmadi, Matthias Bussmann, Jomo Dalius Baranauskas, Denis Zelenin
Edwards, Kelvin Tran, Lloyd F. Linder, Christopher Pacific MicroCHIP Corp.
Gill, Harry Tan, Devin "g Los Angeles, CA
Menara Networks Inc., Dallas, TX dalius@pacificmicrochip.com

Abstract—A dispersion tolerant receiver for fiber-optic links, A 5-tap discrete time FIR filter provides for further
in 0.18µm SiGe BiCMOS, implements a Class-2 Partial equalization and is responsible for sampling of the signal in
Response Maximum Likelihood (PRML) equalization a time interleaved fashion subsequently splitting the data
entirely in the analog domain. Post-FEC error free operation stream into two channels (A and B). This is essential for
is achieved with data received from over 400km of
reducing of the effective data rate necessary to relax timing
uncompensated single mode fiber (SMF). The receiver
complies with XFI Jitter specifications for Telecom (SO7ET requirements for further signal processing. The Viterbi
OC-192 and G.709 “OTU-2”). decoder consists of an Add-Compare-Select (ACS)
function and a Survival Sequence Register (SSR). A 2:1
I. INTRODUCTION MUX assembles the error corrected data back into a single
bit steam and ships it out through a 50Ω terminated buffer.
Chromatic and polarization mode dispersion in optical The Clock Recovery (CR) block provides the timing for the
fiber causes inter-symbol interference and subsequently FIR, ACS and SSR as well as the synchronization of the
leads to errors at the receiving end of the channel. Optical other on-chip functions.
dispersion compensation requires inconvenient and
expensive compensation modules commonly placed at
80km intervals. Electrical Dispersion Compensation (EDC)
provides for a simple low cost solution by replacing
expensive optics with inexpensive electronics. Recently,
maximum likelihood sequence estimation (MLSE)
techniques have evolved as the preferred approach for
high-performance EDC in 10Gb/s fiber-optic systems [1-2].
Previously reported EDC receivers employ an analog front
end including a VGA and an ADC followed by a DSP. The
reported solutions are either based on a dual-chip solution
or are entirely implemented on a single chip using an
advanced CMOS process. They utilize a narrow sliding
window for their digital implementation of the Viterbi
Decoder resulting in suboptimal performance. In this paper,
we present a single-chip small form factor (2.5mm x Figure 1. Analog PRML receiver IC architecture.
2.5mm die) solution, in which the MLSE decoding function
is implemented entirely in the analog domain on a mature The Automatic Gain Control (AGC) loop involving the
0.18µm SiGe process. Our approach augments the MLSE VGA, Peak Detectors (PD) and an AGC logic block is
with partial-response equalization. This kind of multi-stage responsible for coarse tuning of the CTF output signal
equalization results in a reduced-complexity, superior- swing. When the CR enters the phase locked mode, the
performance solution compared with the MLSE-only AGC control logic switches to the “fine” loop through the
approach. Some aspects and blocks of the IC were PD2 maintaining the signal swing at the FIR (Ch A) output
previously reported [3-6]. This presentation aims to show equal to REF2. The VGA gain in the AGC loop is
the entire receiver architecture as well as to describe blocks controlled by a 7-bit DAC. An automatic offset correction
and functions not covered in previous publications. feature is employed for canceling out of the offset
introduced in the VGA and the CTF. An offset control
II. ARCHITECTURE overriding option is implemented in order to provide for
The simplified block diagram of the IC is shown in Fig. external offset control. For example, it allows the Forward
1. The dispersion impaired optical data signal from the Error Correction (FEC) processor to optimize the offset
fiber is converted to the electrical domain by a based on the minimum bit error rate. PTAT and Band-Gap
transimpedance amplifier (TIA) and is fed to the 50Ω bias currents referenced to internal as well as external
terminated variable-gain amplifier (VGA) for amplitude resistors are generated for various analog functions. High-
normalization and then enters a Continuous Time Filter speed as well as DC test functions are implemented in
(CTF) to undergo normalization of the frequency response. order to make possible probing of the signals along the data

978-1-4244-4353-6/09/$25.00 ©2009 IEEE

path as well as DC bias voltages and also temperature in accommodate the incoming data rates ranging from
three different on-chip locations. 9.953Gb/s to 11.1Gb/s. Additional 4-bit cut-off frequency
tuning capability is built-in for the compensation of the
A. VGA/AGC impact on the cut-off frequency of the component
A linear VGA (Fig. 2) is implemented as a part of a parameter variation over process corners. The CTF group
dual loop AGC normalizing the signal amplitude at the FIR delay was measured to be flat to +/- 10ps up to 1.2 times
input (coarse loop) and at the FIR output (fine loop). The the BW. THD was measured to be below -40dBc at
gain (from -8dB to +4dB) is controlled by a current from a 500MHz frequency.
7-bit DAC. Thermometer coding is used in the DAC in Bi-Quad Bi-Quad
order to ensure monotonic transfer characteristic for
avoiding of the AGC loop malfunction. The DAC is
controlled by the AGC logic block which functions V2I
I2V
according to a special algorithm. The gain control loops are IN OUT
working one at a time. The coarse loop lock is achieved
first. It ensures that a 900mVpp swing data signal enters the
FIR. Once the CR achieves a lock condition, the coarse
loop is switched off transferring the control to the fine loop
for continued monitoring and fine adjustment of the data
Figure 3. Continuous Time Filter (CTF) block diagram
signal swing at the output of the FIR. The fine loop is also
responsible for the accommodation of any deviations of the
signal level at the output of TIA during the operation of the C. FIR
IC. The automatic offset control block cancels out any The 5-tap sampled-time analog programmable finite
offset in the signal chain along VGA and the CTF. A Gm-C impulse response (FIR) filter operates along with the CTF
based loop filter instead of an RC filter is used for setting in order to match the combined response of the optical
the low frequency response of the automatic offset control, channel and the CTF-FIR to a predefined target – class-2
since the implementation of the Gm cell requires much less partial response (PR) polynomial (1+D)2. The interleaved
on-chip area compared to Mega-Ohms of resistance FIR is clocked at 5GHz, taking 1 sample per bit of the
necessary for the low cut-off frequency. Moreover, Gm in incoming signal. The linearity and SNDR is 40dBc and
contrast to R can be set virtually independent on process 35dBc, respectively, for the entire VGA-CTF-FIR signal
corners. This is achieved by deriving the Gm cell bias chain. The FIR outputs correspond to the 5-level partial
current using an external resistor. Temperature dependence response target. A newly developed track-and-hold (T/H)
is eliminated by using PTAT bias current. 100Hz low architecture in Fig. 4 achieves >50dBc linearity and >45dB
frequency cut-off is achieved. The offset control voltage on feed-through suppression from a single +3.3V supply by
the capacitor is converted to current by another Gm cell using a switched diode isolation stage in addition to the
which is subsequently inserted into the VGA output standard switched emitter follower T/H architecture. A
termination point. This ensures the offset control loop buffer amplifier adds further isolation and restores the gain
bandwidth independence on the VGA gain. The automatic to unity in order to overcome the losses in the T/H core.
offset control can be disabled for external digital control of The performance of the T/H is critical since any errors or
the offset through the 7-bit DAC. imperfections introduced in the T/Hs are accumulated
along the signal chain. A differential peak-to-peak signal
swing of about 900mV has been shown to be the optimum
for SNDR purposes by trading off noise degradation and
signal distortion. A detailed description of the FIR filter has
been presented in [6].

VCC
Ib1
Ib2 RDN R R RDP Ia2
Ia1
VB VA
Q3N Q3P

VON VN VP VOP
DN Q2N Q2P DP

Figure 2. Simplified VGA schematics Cff_P

B. CTF Cff_N

Fig. 3 shows a block diagram of the 4th order Gm-C low- VinP Q1 VinN
Q2
pass CTF. It consists of two bi-Quads, the input voltage-to- Chold
2R
Chold

current converter and the output current-to-voltage

QT QH QH QT
converter. A three bi-Quad version of the filter (6th order)
has previously been described in detail [4]. This CTF CLK Isw
Isw Is1a Is1 Is2 CLK Is2a
features 230mW – significantly lower power compared to “hold” “track”

the reported 6th Order CTF. The CTF cut-off frequency can
be tuned from 1.5 to 3.5 GHz with 4-bit granularity through Figure 4. Improved switched emitter follower circuit
a digital serial interface. The tuning range is sufficient to
D. Clock Recovery SNR and low bit error rates. The performance of the ACS
The clock recovery (CR) uses a decision-directed block is determined by the accuracy of the internal metric
algorithm approach shown in Fig. 5. Initially, a traditional update calculation and the accuracy of the equalization in
PLL, with a Phase-Frequency Detector (PFD), has been the CTF/FIR front-end to match the optimum 5-level target.
used to lock the frequency of the Voltage-Controlled A 2x4-channel digital output of the ACS bus connects to
Oscillator (VCO) to the incoming data rate. Once the SSR (Fig. 7) channels: interleave A and B. The SSR
frequency lock is achieved, the control of the VCO is block chooses the final survivor based on a majority vote
transferred to a Decision-Directed Phase Detector (DDPD) calculation at the end of the SSR chain. The interleaved
phase alignment loop which is using the incoming data channels are finally combined in a 2:1 MUX circuit and fed
stream as reference. The DDPD loop minimizes the into an XFI compliant output buffer. All SSR clocking is
Minimum-Mean-Square-Error (MMSE) between the implemented at half-rate. As a result, the residual offset
incoming data and the ideal (1 + D)2 PR2 polynomial. The and/or duty cycle distortion in the clock signal driving the
transition from frequency acquisition mode to phase output 2:1 MUX can cause even-odd bit duty cycle
alignment mode is automatically controlled by a finite- distortion. Special care was taken to mitigate this effect by
state-machine – the Lock-Detect (LD). Once the LD has providing careful offset compensation for clock driver
been initialized with a reset, the LD will automatically circuitry.
control the dual-loop CR. The CR loop drives the FIR and
the Viterbi decoder clock inputs maintaining an optimal
sampling phase. A detailed description of the CR has been
provided in [5].

∑ ∑
Figure 6. Viterbi Decoder ACS block diagram
∑

Figure 5. Clock Recovery block functional diagram. Figure 7. Viterbi Decoder SSR block.

E. Viterbi Decoder F. Test Points

The interleaved discrete-time analog ACS architecture The high complexity of this analog receiver makes it
employs a 4-state MLSE engine to process the PR2, 5-level difficult to assess the operation of the functional blocks and
signals from the FIR (Fig. 6). The ACS is optimized for an to identify potential problems in the circuits. High-speed
(1+D)2 PR target that is obtained by applying the frequency Test Point (TP) circuits are introduced for probing the
equalization on the original binary sequence. The two 5- signals. The use of TP makes it possible to pick up the high
level equalized input signals from the FIR channels A and speed data signals at the critical points along the signal path
B are retimed in two track and hold circuits and distributed with minimal loading of the precision-analog circuits and
to the ACS core slices as well as to unity gain linear output minimal perturbation of the layout integrity (Fig. 8).
buffers connecting to the phase detector block in the CR.
Each slice contains an interleaved version of the metric
update circuitry, the metric track-and-hold and additional
support circuits. The challenge of the non-windowed non-
unrolled-loop branch/path metric calculation is the
constraint of the extremely short cycle time of under 100ps.
From a system point of view, the ACS metrics update
equations are uniquely arranged to allow the circuit
implementation to achieve the maximum circuit symmetry
paired with the maximum SNR at the digital decision
circuits. This is vital for achieving the high equivalent input Figure 8. High speed test point implementation
 Figure 9. Measured eyes for 400km SMF link: at the receiver input (a), FIR output (b), IC output (c)

A high-speed signal is picked up by a probe that has a outstanding performance of this PRML receiver has been
driving capability to transmit the signal to the periphery of achieved with a 1-sample/bit, 4-state MLSE [3]. This EDC
the block (≤ 50µm). A line driver picks up the signal from receiver shifts optical transmission issues from the optical
the probe and transmits it over larger distance (≤ 1mm). An domain to a low cost IC solution. To the best of our
analog MUX selects one out of up to 7 high speed signals knowledge this is the first reported analog implementation
coming from the line drivers and ships them to the output of the PRML algorithm for a 10Gb/s+ fiber-optic receiver.
through a 50Ω terminated linear buffer. The DC voltages of
the critical biasing points, the voltage drop on ground plane
and power supply as well as voltages corresponding to the
on-chip temperature are routed out through an integrated
DC test point. Since the DC test point is bi-directional it
also provides the capability of adding or subtracting of
currents to/from a specific point in the circuit.
III. IC IMPLEMENTATION
A Jazz Semiconductor 0.18µm SiGe process is used for
the IC implementation. The die size is 2.5mm x 2.5mm
with the VGA occupying 0.15mm2, CTF 0.17mm2, FIR
0.21mm2, CR 0.68mm2, ACS 0.55mm2, SSR 0.14mm2. The
test chip is wire-bonded in a custom ceramic BGA package
and consumes 4.5W from 3.3V, 1.8V and -1.2V supplies.
IV. TEST RESULTS
To assess the performance of the PRML EDC receiver
IC, a 10.71Gb/s 231-1 PRBS NRZ data is launched onto an
Figure 10. EDC die photo
uncompensated 5x80km-span SMF fiber link. A standard
Mach-Zehnder modulator is used. The light source is a Table I. Comparison with state-of-the-art solutions
1550nm wavelength laser, and the link consists of four Reference 7umber Samples ADC Performance
Erbium-doped fiber amplifiers spaced at 80km. An optical of states per bit required (reach)
band-pass filter precedes a standard linear PIN-TIA [7] 4 2 Yes 120km
receiver. A bit-error rate tester was used to detect errors [8] 4 2 Yes 160km
[2] 8 1 Yes 300km
and generate the NRZ data signal. Fig. 9 depicts the Our work 4 1 No 400km
received eye after a transmission distance of 400km (a), the
equalized eye at the FIR output (b) and the recovered clock REFERENCES
and data eye at the IC output (c). As can be seen, the [1] T. Kupfer, et al., “Measurement of the performance of 16-states
received eye is totally closed. The PR2 equalization has MLSE Digital Equalizer with different optical modulation formats,”
produced the expected (1+D)2, 5-level eye (with residual PDP13, OFC"FOEC 2008.
miss-equalization) which is then applied to the 4-state [2] R. Griffin, et al., “Combination of InP MZM transmitter and
MLSE for NRZ data recovery. The required back-to-back monolithic CMOS 8-state MLSE receiver for dispersion tolerant 10
Gb/s transmission,” OthO2, OFC"FOEC 2008.
OSNR is 16 dB and approximately 25dB at 400km (i.e.,
[3] S. Elahmadi, et al., “A monolithic one-sample / bit partial-response
6800ps/nm). The required OSNR increases at a slope of maximum likelihood SiGe receiver for electronic dispersion
less than 1.5dB/80-km-span (or 1.5dB/1360ps/nm) for the compensation of 10.7Gb/s fiber channel”, OFC/"FOEC 2009.
first 3 spans. Over the last two spans, the slope increases to [4] D. Baranauskas, et al., “A 6th Order 1.6 to 3.2GHz Tunable Low-
about 2.5dB/span. Pass Linear Phase gm-C Filter for Fiber Optic Adaptive EDC
Receivers” IEEE RFIC Symp. June 2009.
V. CONCLUSIONS [5] J. Edwards, et al., “A 12.5Gbps Analog Timing Recovery System
The PRML receiver presented here is capable of post- for PRML Optical Receivers”, IEEE RFIC Symp. June 2009.
FEC error-free recovery of up to 11.1Gb/s data transmitted [6] K. Tran, et al., “A 50dB Dynamic Range 11.3GSPS, Programmable
FIR Equalizer in 0.18um SiGe BiCMOS Technology for High
over 400km of uncompensated SMF fiber. In contrast to Speed EDC Applications”, IEEE RFIC Symp. June 2009
existing MLSE receivers that fully rely on a digital Viterbi
[7] Hyeon-Min Bae, et al., “An MLSE Receiver for Electronic
decoder, our architecture is entirely analog. The realized Dispersion Compensation of OC-192 Fiber Links” JSSC, vol. 41,
reach of this receiver exceeds that of any reported EDC no. 11, pp. 2541-2554, "ov. 2006.
receiver employing standard NRZ transmission and direct [8] A. Faebert et al., “Performance of a 10.7 Gb/s receiver with digital
detection (non-coherent, IM-DD) means (Table I). The equalizer using MLSE”, ECOC’04, paper Th4.1.5.