RFIC Symposium CDR
RFIC Symposium CDR
RFIC Symposium CDR
978-1-4244-3376-6/978-1-4244-3378-0/09/$25.00 © 2009 IEEE 535 2009 IEEE Radio Frequency Integrated Circuits Symposium
together by a differential transconductor (Gm) which ek = y *k − yk (1)
drives the loop filter and VCO.
∞
MSE = E{ek2 } = ∫ ek2 PDF ( yk )dyk
(2)
AGC
−∞
DAC
Offset
7-Bit
7-Bit
DAC
Correction
GmC
dek2 ⎡d ⎤ (3)
CTF
VGA Line-In NRZ = −2ek (nk ) ⎢ y (t )⎥
dnk ⎣ dt ⎦ t =kT + nk
Continuous
Time PRS
∑ k ( n ) x (n − i)
i
+
MSE (2) is found by setting the derivative with respect to
i=0 fs/2 ∑
FIR output @ time +
the sampling time of (2) to zero and setting the timing
n ∑ Linear V2I
T/H
yk-1(B) - ek-1(B)
- Converter jitter to zero. The minimum occurs when the product of
yk(B) +
sgn{ek-1(A)}
Multi Band
LC-VCO
Test the amplitude error for sample k and the slope of the
Clock
Reference PFD
Charge VCM sample at time k is equal to zero. So, if the phase of the
Pump
Clock
loop_sel VCO is modulated with (4)
Lock-Detection
Digital Controller VCO
N-Bit Control & ZONE
0 1
zk = ek × ( y k +1 − y k −1 ), (4)
Status Signals
III. MMSE BASED TIMING RECOVERY The interleave topology of the fully differential DDPD
is shown in Fig. 3. The sample under measurement (yn) is
Sample at time kT + (nk + Tj) sent to two track and hold based current mode logic
CTF
y(t) yk(nk)
Timing (CML) processing paths. One path computes the
Slope
y*k(nk) error
Calculation amplitude error (partial response target error), the other
5-Tap FIR Filter detector
Ideal PRS determines the instantaneous slope of the sample whose
Generator
ek(nk) target error is being computed in the opposite interleave
Myk = yk+1 – yk-1
Hlf(s)
zk(nk)
536
dB linear amplifier which drives the analog input of a
saturated multiplier. The digital input to the multiplier is I =G ×(Φ +Φ )
Gm m Ae Be
537
JDSU ONT-506 TESTER JDSU ONT-506 TESTER
(c) (d)
538
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