VLSI Fabrication Process PDF
VLSI Fabrication Process PDF
VLSI Fabrication Process PDF
Om prakash
5th sem ASCT, Bhopal
omprakashsony@gmail.com
Abstract
VLSI stands for "Very Large Scale
Integration". This is the field which
involves packing more and more logic
devices into smaller and smaller areas.
Thanks to VLSI, circuits that would have
taken boardfuls of space can now be put
into a small space few millimeters across!
This has opened up a big opportunity to do
things that were not possible before. VLSI
circuits are everywhere ... your computer,
your car, your brand new state-of-the-art
digital camera, the cell-phones, and what
have you.We must have a working
knowledge of chip fabrication to create
effective designs and in order to optimize
the circuits with respect to various
manufacturing parameters. Also, the
circuit designer must have a clear
understanding of the roles of various
masks used in the fabrication process, and
how the masks are used to define various
features of the devices on-chip.
Introduction
An Integrated Circuit (IC) is an electronic
network fabricated in a single piece of a
semiconductor material.
The semiconductor surface is subjected to
various processing steps in which
impurities and other materials are added
with specific geometrical patterns
The fabrication steps are sequenced to
form three dimensional regions that act as
a transistors and interconnects that form
the network.
Manisha Kumari
5 sem ASCT, Bhopal
Manisha2686@gmail.com
th
Why VLSI ?
1. Greater Functionality
Its results in average energy savings of
35% to 70% with an average speedup of 3
to 7 times.
2. Embedded Characteristics
After fabrication many applications could
share commodity economics for the
production of a single IC and the same IC
could be used to solve different problems
at different points in time.
3. Lower System Cost
By eliminating the ASIC design lower
system cost on a low-volume product is
achieved. For higher-volume products, the
production cost of fixed hardware is
actually very much lower.
History
The final step in the development process,
starting in the 1980s and continuing
through the present, was "very large-scale
integration" (VLSI). The development
started with hundreds of thousands of
transistors in the early 1980s, and
continues
beyond
several
billion
transistors as of 2007.
There was no single breakthrough that
allowed this increase in complexity,
though
many
factors
helped.
Manufacturing moved to smaller rules and
2. Wafer processing
3.Lithography
Lithography: process used to transfer
patterns to each layer of the IC
Lithography sequence steps:
Designer:Drawing the layer patterns on
a layout editor
Silicon Foundry:Masks generation from
the layer patterns in the design data base
Printing: transfer the mask pattern to the
wafer surface
Process the wafer to physically pattern
each layer of the IC.
(a).Photo resist application:
the surface to be patterned is
spin-coated with a light-sensitive
organic polymer called photoresist
(b)Printing (exposure):
the mask pattern is developed on the
photoresist, with UV light exposure
7.Silicon deposition
Films of silicon can be added on the
surface of a wafer
Epitaxy: growthof a single-crystal
semiconductor film on a crystalline
substate
Polysilicon: polycrystalline film with a
granular structure obtained through
depositionof silicon on an amorphous
material
MOSFET gates
8.Metallization
Metallization: deposition of metal layers
by evaporation
interconnections
9.Testing
Test that chip operates
Design errors
Manufacturing errors
A single dust particle or wafer defect kills
a die
Yields from 90% to < 10%
Depends on die size, maturity of process
Test each part before shipping to customer
10.Assembly and packaging
Tapeout final layout
Fabrication
6, 8, 12 wafers
Optimized for throughput, not latency (10
weeks!)
Cut into individual dice
Packaging
Bond gold wires from die I/O pads to
package
Limitations
Placement Issues
Advantages
Less power
because each of the devices consumes only
a tiny amount of power. In a switching
circuit most of the power is consumed
switching the charge on the capacitors that
connect the switches to each other. In a
large IC the components are so small and
close together that that capacitance is
much smaller, and thus less power.
Less testing.
If you built the same circuit out of discrete
ICs and other components, each IC has to
be tested (before you use it) for the many
different ways it could be used in different
applications. for 10000 ICs this is a lot of
testing. In a VLSI the components are
dedicated to a single use. Further, most are
located in the middle of the VLSI and
there is no access to them for testing. All
you can test is the function the entire
circuit
was
designed
for.
Reliability.
Over time, we have found that the
reliability of an IC is a function of how
many connections it has to the outside
Routing Issues
Existing components has to be connected
to the components newly reconfigured.
The ports must be available to interface
new components. The same ports must
have also been used under the
old configuration. To accomplish this
orientation of the components should be in
a workable fashion.
Timing Issues
Newly configured hardware must meet the
timing requirement for the efficient
operation of the circuit. Longer wires
between components may affect the
timing. Optimal speed should be attainable
after dynamically reconfiguring the device.
Over timing or under timing the new
added design may yield erroneous result.
Consistency Issues
Static or dynamic reconfiguration of the
device should not degrade computational
Conclusion
The demand for low power VLSI digital
circuits in the growing area of
portable communications and computing
systems will continue to increase in
the future. Cost and life cycle of these
products will depend not only on low
power synthesis techniques but also on
new DFT methods targeting power
minimization during test application. This
is because the traditional DFT
methods are not suitable for testing low
power VLSI circuits since they reduce
the reliability and manufacturing yield.
References
en.wikipedia.org/wiki/VLSI_Technology
www.ieee.org
www.epfl.ch
Principles of CMOS VLSI Design
Neil
H.E.Weste
Kamran Eshraghian