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1502-Advanced VHDL Verification Datasheet

This document describes an advanced 5-day VHDL testbench and verification workshop taught by Jim Lewis. The workshop teaches advanced VHDL coding styles and methodologies for improving design verification productivity and testbench development. Students will learn how to create a system-level, transaction-based, self-checking test environment in VHDL. The workshop covers topics such as constrained random testing, functional coverage, and advanced randomization and is split evenly between lectures and hands-on labs.

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186 views1 page

1502-Advanced VHDL Verification Datasheet

This document describes an advanced 5-day VHDL testbench and verification workshop taught by Jim Lewis. The workshop teaches advanced VHDL coding styles and methodologies for improving design verification productivity and testbench development. Students will learn how to create a system-level, transaction-based, self-checking test environment in VHDL. The workshop covers topics such as constrained random testing, functional coverage, and advanced randomization and is split evenly between lectures and hands-on labs.

Uploaded by

Sam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced VHDL Testbenches & Verication

with Jim Lewis of SynthWorks

Introduction
Developed and delivered in person by VHDL specialist Jim Lewis,
this 5-day instructor led workshop will teach the latest verication
methodologies for FPGA and ASIC design. Jim is a founding
member of the Open Source VHDL Verication Methodology
(OSVVM) and he will instruct you on how to create a VHDL
testbench environment that is competitive with other advanced
verication methodologies, such as those based on SystemVerilog
and 'e'.

Requirements
Suitable for device (PLD/FPGA/ASIC) designers who are looking to
improve their verication eciency and eectiveness. Delegates
should have a good working knowledge of digital circuits and prior
exposure to VHDL through work or a previous course.

Agenda
Day 1, Module TB1
Testbench Overview
Basic Testbenches
Overview
Transactions & Sub-programs
This course will teach you advanced VHDL coding styles,
Modelling for Verication
techniques and methodologies. These approaches will ensure that
VHDL IO
you become more productive at both design verication generally
and specically in regards to testbench development. Your existing
Day 2, Module TB2
investment in VHDL is leveraged and core topics such as data
Lab Review: Testing with sub-programs
structures, randomisation and coverage are explored in depth.
Transaction-based Models (BFM)
Elements of a Transaction-based BFM Part 1
The course starts with simple testbenches, progressively increasData Structures for Verication
ing the level of abstraction and contains numerous examples that
can be used as templates to accelerate your own test and
Day 3, Module TB3
testbench development. The nal result is a system-level, transacLab Review: UartTx BFM
tion-based, self-checking test environment.
Creating Tests
Constrained Random Testing
This methodology uses the natural concurrency that is built into
Functional Coverage
VHDL. Certain processes and models are used to create separate
threads of execution for items that naturally run independently.
Day 4, Module TB4
When modelling state machines with this approach they can
Execution & Timing
either be modelled concurrently, like RTL code, or sequentially like
Congurations & Simulation
software and OO approaches. To synchronise the separate
Management
processes, we use a synchronisation primitive from a "library"
Advanced Coverage
contained in our open source utility package. Unlike other
Advanced Randomisation
verication languages, the structure of the testbench is created
with structural code similar to RTL, all in VHDL.
Day 5, Module TB5
Lab Review: Scoreboards,
Objectives
Randomisation & Coverage
- Improve design verication and testbench productivity
Modelling RAM
- Learn how to create a transaction-based, system-level,
Test Plans
self-checking test environment
Transaction-based BFM Part 2
- Implement interface functionality with either a sub-program
or bus functional model (aka transaction-level model or TLM)
Approach & Labs
- Use sub-programs to abstract interface actions (CpuRead,
This hands-on, how-to course is taught by an experienced vericaCpuWrite, UartSend)
tion engineer with specialist VHDL knowledge and expertise. We
- Write directed, algorithmic, constrained random, coverage
believe that student and instructor interaction is key to a successdriven random tests or a mixture of them
ful learning environment, therefore places on the course are
- Write a test plan that maximises reuse from RTL to core to
limited.
system-level tests
- Reuse SynthWorks' packages for constrained random testing, The course is split roughly 50/50 lecture and labs, so plenty of
functional coverage, memories, scoreboards and interfaces
opportunity to reinforce the theory. Each delegate will be provid- Model interface behaviour with proper timing
ed with access to a laptop, Aldec Riviera-PRO and all the neces- Model analogue values and periodic waveforms
sary resources required.
- Use VHDL's le read and write capabilities eectively

CONTACT

www.rsteda.com
FirstEDA +44 (1295) 201250 or adam.wilson@rsteda.com
Eastlands II, London Road, BASINGSTOKE, RG21 4AW, UK

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