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VLSI START

The document outlines a 12-week study plan for VLSI Design and Verification, assuming a commitment of 2-3 hours per day. It covers foundational topics in digital design, Verilog, SystemVerilog, and UVM, along with practical projects and resources for each week. The plan concludes with guidance on resume preparation, interview practice, and suggestions for further learning and projects after the initial 12 weeks.

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3 views7 pages

VLSI START

The document outlines a 12-week study plan for VLSI Design and Verification, assuming a commitment of 2-3 hours per day. It covers foundational topics in digital design, Verilog, SystemVerilog, and UVM, along with practical projects and resources for each week. The plan concludes with guidance on resume preparation, interview practice, and suggestions for further learning and projects after the initial 12 weeks.

Uploaded by

abhijitkarale55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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12-Week VLSI Design & Verification Study Plan

Assumptions:

• You can dedicate 2–3 hours per day, 6 days/week.

• You are comfortable with basic digital electronics, logic gates, and basic programming.

Month 1: Core Foundations (RTL Design + Digital + HDL)

Week 1: Digital Design Fundamentals Refresher

• Combinational logic (MUX, DEC, ALU, Encoders/Decoders)

• Sequential logic (Flip-flops, Registers, Counters)

• Timing diagrams, setup/hold, clocking

• FSM design (Mealy/Moore)

Resources:

• Book: Digital Design by Morris Mano

• Neso Academy / Gate Smashers YouTube

Week 2: Verilog HDL – Basics

• Verilog data types, operators

• module, wire, reg, assign

• Gate-level, dataflow, behavioral modeling

• Procedural blocks (always, initial)


• if, case, for, while, repeat

Practice:

• Simulate MUX, Encoder, Flip-flop using Verilog

Resources:

• Book: Verilog HDL by Samir Palnitkar

• EDA Playground (Online simulator)

Week 3: Verilog – Testbenches & Simulation

• Writing basic testbenches

• $display, $monitor, $finish

• Delay modeling (#, @, posedge, negedge)

• Vectors, concatenation, parameters

Mini Project: Design + simulate 4-bit ALU and testbench

Tools: ModelSim, EDA Playground

Month 2: RTL Design to Verification Transition

Week 4: Advanced Verilog + RTL Design Practices

• Blocking vs non-blocking

• FSM in Verilog

• Synthesis guidelines (inferring latches, flops, memory)


• Coding style for clean RTL

Project: 8-bit shift register, FSM-based vending machine

Resources: Clifford Wolf’s Yosys (for synthesis)

Week 5: Introduction to FPGA & Synthesis

• FPGA vs ASIC

• Xilinx Vivado basics

• RTL synthesis process

• Timing analysis (setup/hold violations)

• Verilog constraints (clock constraints)

Lab: Simulate + synthesize FSM on Vivado

Tools: Vivado WebPack, Basys3/Nexys A7 (if board available)

Week 6: SystemVerilog Basics for Verification

• logic, bit, int, enum, typedef

• always_ff, always_comb, always_latch

• interface, modport, package

• Testbench constructs

Practice: Rewriting earlier Verilog testbenches in SystemVerilog

Resources: SystemVerilog for Verification by Chris Spear


Month 3: Verification + UVM + Projects

Week 7: Introduction to Verification Concepts

• Simulation vs Emulation vs Formal

• Directed vs Constrained-Random Testing

• Self-checking testbenches

• Scoreboards, monitors, coverage

Resources: Verification Academy (free courses)

Week 8: SystemVerilog OOP Concepts

• Classes, objects, constructors

• Inheritance, polymorphism

• Mailboxes, semaphores

• Dynamic arrays, queues

Practice: Create packet generator class, mailbox-based communication

Week 9: UVM Foundations

• UVM testbench structure

• Components: driver, monitor, agent, environment, scoreboard

• Factory & Configuration DB


Mini Project: Basic UVM testbench for a 4-bit counter

Resources: UVM Cookbook (Verification Academy)

Week 10: Assertions & Functional Coverage

• Introduction to SystemVerilog Assertions (SVA)

• Immediate vs concurrent assertions

• Functional Coverage concepts

• Covergroup, coverpoint, bins

Add coverage & assertions to UVM project

Week 11: Industry-Level Projects

• Choose 1 RTL Design + Verification project:

o UART, SPI, I2C

o FIFO Controller

o AXI-lite slave

Design RTL + UVM Testbench + Coverage

Week 12: Resume, GitHub & Interview Prep

• Prepare resume with RTL + Verification project

• Document GitHub projects


• Practice common RTL/Verification questions:

o Verilog/SystemVerilog syntax

o FSM design, coverage, assertions

o UVM architecture

Mock Interview Topics:

• Blocking vs non-blocking

• Scoreboard vs Monitor

• Coverage hole handling

• Clock-domain crossing

Suggested Tools to Learn (Free/Student Versions)

• EDA Playground – Free Verilog/SV simulator

• ModelSim or Questa – Simulation

• Vivado WebPack – RTL Synthesis and FPGA

• GTKWave – Waveform viewer

• Verilator + Yosys – Open-source simulation + synthesis

What Next After 3 Months?

In the next 3 months, you can:

• Build multiple UVM projects with AXI, AHB


• Learn Formal Verification (optional)

• Dive into Scripting (Python/TCL for automation)

• Prepare for company-specific test patterns (Synopsys, Cadence, Intel, etc.)

• Do internships or contribute to open RTL repos

Would you like a Google Sheets planner or Notion template for this 12-week plan?

Tools

ChatGPT can make mistakes. Check important info. See

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