Journal of Communication and Computer 8 (2011) 313-317

A Comparative Study & Performance Analysis of SRAM

Cells with Symmetric & Asymmetric Configuration
Sandeep Dhariwal1, Sushma1, Vipin Gupta2, Ritu Vijay3 and Vijay Lamba 1
1. Electronics & Communication Department, Kurukshetra University, Kaithal 136027, India
2. Electronics & Communication Department, R.P.I.I.T., Karnal, India
3. Department of Electronics, Banasthali University, Rajasthan 304022, India
Received: September 17, 2010 / Accepted: November 26, 2010 / Published: April 30, 2011.
Abstract: This paper discusses 6T, 5T & 4T memory cells asymmetric configuration. Six transistor (6T) SRAM Cells are the main
choice for todays cache applications. The static noise margin of 6T SRAM cell is highest in all memory cells, so the stability is highest
in this cell. Simulation is carried out using tSPICE 7.1v with process technology of 0.18 m. Delay of the 6T cell is 1ns and leakage
power dissipation in stand by mode is 1.5610-10 watts. Next memory cell in static memory cells is 5-transistor single-bit line memory
cell. Due to reduced threshold voltage in coming technologies, leakage power is increasing fast. An asymmetric configuration has been
implemented to reduce this leakage power. 6T SRAM cell is the best asymmetric configuration used as caches.
Key words: Asymmetric SRAM (ASRAM), tSPICE, bitline, wordline, delay.

1. Introduction
Excessive power dissipation increases temperature
and with every 10oC increase in operating temperature,
approximately doubles a components failure rate [1].
So, the low power design is a growing class of personal
computing devices, such as portable electronics and
communication devices. These devices and systems
require high speed, complex functionalities and real
time processing capabilities [2]. Due to these problems,
circuit designers are realizing the importance of
limiting power consumption at all levels of the design.
Scaling of CMOS devices has provided remarkable
improvement in performance of electronic circuits in
the past few years [3]. They can work at a much
reduced threshold as compared to before CMOS
Ritu Vijay, Ph.D., professor, research fields: VLSI design,
DSP. E-mail: rituvijay1975@yahoo.co.in.
Vijay Lamba, Ph.D., professor, research fields: VLSI design,
nano antenna, nano mosfets, nanotechnology.
Corresponding author: Sandeep. Dhariwal, post graduate
student, research fields: low power digital VLSI design, CNTs.
E-mail: dhariwal.vlsi@gmail.com.

threshold voltages. But this scaling causes leakage in

the circuit. Leakage power consumption [4] is another
concern with SRAMs. Conventional 6T SRAM cells
are the main choice for todays cache applications.
Next, a simple 5T SRAM cell is presented. Further, an
intermediate bitline precharge voltage combined with a
different 5T cell sizing allows correct write operation
without requiring any additional cell nodes [5]. The 5T
cell has only one access transistor M5 and a single
bitline BL.
Next 4T SRAM cell configuration reduces the
SRAM cell size by approximately one third [6].
Although conventional 6-T SRAMs [7] is easily
embedded in logic LSIs owing to its compatibility with
the CMOS logic process, they are not economical to be
included in practical systems due to the large cell chip
area [8]. The loadless design of the 4-T SRAMs
requires special process to reduce the threshold voltage
of pMOS in order to increase the supply current. In this
paper, a special configuration is used to lower the
leakage power that is responsible for the power

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A Comparative Study & Performance Analysis of SRAM Cells with Symmetric & Asymmetric
Configuration

dissipation in the memories cells. Name of that

configuration is asymmetric configuration. Since the
MOSFET sub-threshold leakage current increases
exponentially with a reduced threshold voltage,
leakage power dissipation has grown to be a significant
fraction of overall chip power dissipation in modern
deep sub-micrometer (0.18 m) processes [9].
One can reduce leakage by using higher VTH
transistors, but unfortunately using an all-high-VTH
transistor cell degrades performance by an
unacceptable margin [10]. Asymmetric SRAM cells
reduce leakage while maintaining high performance
based on the following approach: select a preferred
state and weaken only those transistors necessary to
drastically reduce leakage when the cell is in that state.

2. Review of Asymmetric Cells

The main source of leakage current is the
sub-threshold leakage through a MOS device channel.
Even though a transistor is logically turned off, there is
a non zero leakage current through the channel at the
microscopic level. This current is known as the
sub-threshold leakage because it occurs when the gate
voltage is below its threshold voltage.
Leakage current is given as follows in Eq. (1):
q

I subth = A e nkT

(VGS Vt )

(1 e

qV DS
kT

(1)

It can be seen directly from the equation that the

sub-threshold leakage current is less if Vt is more and
vice versa. Therefore asymmetric configuration deals
with dual threshold voltage in each SRAM cell.
2.1 6T ASRAM Cell
Structure of the cell is identical to the 6T symmetric
SRAM cell. The difference lies in the dual threshold
voltages of the PMOS and NMOS transistors. Fig. 1
shows the high threshold voltage (High Vth) when
transistors are in off state and responsible for the
leakage in the cell. Suppose the voltage node Vout1 is
storing logic 0 and Vout2 has logic1. So, the
transistors P1, N2 are in off state and given high Vth.
Due to charge sharing at the node Vout1, the N3
transistor will also acquire the logic 0 and will be

Fig. 1 6T ASRAM Cell.

given high Vth. Leakage is reduced by giving high

threshold voltage to the selected transistors. Due to this
asymmetric Vth for on and off transistors, the
SRAM cell is called as asymmetric SRAM cell or
simply ASRAM.
2.1.1 Read Operation
In the read operation, the off transistors are
responsible for the leakage. As the Vout1 node is storing
logic0, the P1 transistor is off and the N1 transistor
is on. And on the other side vout2 stores logic 1, the
P2 transistor is on and N2 transistor is off. The
access transistor N3 is also responsible for leakage,
through charge sharing concept this transistor acquires
logic 0 substantially. Hence all NMOS transistors i.e.
N3, N2 and PMOS transistor P1 are given high
threshold voltages.
2.1.2 Write Operation
The write operation is identical to the section II.
Every time we have to check that the off transistor
will be given high Vth and no change in threshold
voltages of on transistors.
2.2 5T ASRAM Cell
Circuit is identical to the 5T SRAM cell. Only one bit
line is responsible to read from the cell and to write into
the cell. Vout1 node is storing logic 0 and Vout2 node is
storing logic 1. Therefore transistors P1 and N2 are
off and given high Vth. The transistor N3 also
experiences a logic 0 value with the charge sharing
concept. And it is also made high Vth transistor as
shown in Fig. 2. The circuit is asymmetric in value of
threshold voltages applied across PMOS NMOS
transistors and called as 5T ASRAM.
2.2.1 Read Operation

A Comparative Study & Performance Analysis of SRAM Cells with Symmetric & Asymmetric
Configuration

Fig. 2 5T ASRAM Cell.

The read operation is identical to 6T cell. The bit line

is precharged to VPC and the complementary outputs
are obtained at the nodes Vout1 and Vout2. A sense
am-plifier is used to speedup the reading process and
two cells can share the same sense amplifier as the
accessing is through one transistor i.e. N3.
2.2.2 Write Operation
The write operation is identical to above, however
there is low power consumption during writing logic
0 in the cell. The static noise margin of the cell is very
low as compare to 6T and 5T cell.
2.3 4T ASRAM Cell
The PMOS are always set to the high voltage i.e. to
VDD. And therefore only NMOS transistors are selected
to obtain high threshold voltage. From Fig. 3, it is
confirmed that Vout1 node is at logic 0 and Vout2 node
is at logic 1. Correspondingly, the N1 transistor is set
at high threshold voltage. At the output node Vout1,
logic 0 is stored; therefore the transistor N1 will be
set with high threshold voltage. All other transistors are
set with their previous threshold voltages.
2.3.1 Read Operation
The read operation is identical to the 4T SRAM Cell,
take initial conditions across both the bit lines bit and
bit_bar VCC/2 = 0.9 V. By taking initial conditions,
bit lines are precharged. Word line is set high by
applying a negative clock pulse. At the nodes Vout1 and
Vout2, complementary outputs are obtained. Now, the
cell is ready for write operation.
2.3.2 Write Operation
The word line is set to high logic. If we want to write
logic 1 at the node Vout1, then charged the bit_bar at

315

Fig. 3 4T ASRAM Cell.

high logic and correspondingly, bit line bit is given

ground. We get logic 1 at the output node Vout1 and
logic 0 at the node Vout2. If a logic 0 is to be written
at the node Vout1, then bit line bit_bar is held at
ground and bit is charged to VCC.

3. Results and Comparative Analysis

All memory cells are simulated using t-SPICE 7.1v.
In this section, comparison based results are presented
in following tables. These results have been obtained
from simulation of 6T, 5T & 4T memory cells in
symmetric and asymmetric configurations.
3.1 Power Dissipation of All Symmetric Cells
6T SRAM cell shows the overall least power
dissipation among all cells (Table 1). If area of chip is
to be kept small at the cost of power dissipation, then
5T and 4T SRAM cells are next choice.
Main memory communicates with the processor
through cache memory. Frequently utilized data are
stored in cache memory. Most of the time, cache
memory is in read/write mode. Therefore it is required
that cell configuration used in the cache memory
should have small chip area, small delay and very low
power dissipation.
3.2 Power Dissipation of Asymmetric Cells
In Asymmetric configuration of cells, 6T ASRAM
cell is best to use in cache memories. If chip area is to
be kept very small, then 5T ASRAM cells and 4T
ASRAM cells are preferred. Power dissipation of 5T
ASRAM cell is less than 4T ASRAM cell, but chip area

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A Comparative Study & Performance Analysis of SRAM Cells with Symmetric & Asymmetric
Configuration

Table 1 Power dissipation (watts) in symmetric cells.

Operation
Standby
Writing
Reading

6T SRAM

5T SRAM

4T SRAM

-10

-10

-10

1.5610
6.0610-11
3.8810-06

3.4210
4.0210-07
3.2810-07

7.7910
5.4210-08
1.4910-07

of 4T cell is smaller than 5T cell (Table 2).

In comparison of symmetric and asymmetric
configurations of SRAM cells, 6T and 5T cells show
significant reduction in the standby leakage. So, we
conclude that 6T asymmetric SRAM cell is the best
configuration for fast cache memories. Along with
power dissipation, delay is the second most important
performance factor to the system on chip design. Next
this factor has been given with the comparison of
SRAM cells.
3.3 Delay in Symmetric Cells
6T, 5T and 4T SRAM cells are faster than DRAM
cells. For cache memories, low power dissipation and
high speed are two main factors (Table 3). Though, we
can compromise on speed for reduced power
dissipation in devices like portable battery operated
electronics things , e.g., Laptops, cellphones, etc.
6T and 5T SRAM cells are best for cache memories.
But the stability of data is more in 6T SRAM cell.
3.4 Delay in Asymmetric Cells
In Asymmetric cell Configurations, 6T SRAM cell is
fastest and has small access delay. Although 4T
ASRAM cell shows least delay in Table 4, this cell has
large power dissipation in all operations. Therefore 6T
cell is suitable in high speed caches.
It has been concluded from both configurations
(symmetric and asymmetric) that 6T ASRAM cell has
least power dissipation and delay among all cells. So,
6T ASRAM cell is best among all cells to be used in
cache memories.

Table 2 Power dissipation (watts) of asymmetric cells.

Operation
Standby
Writing
Reading

-11

9.2910
5.8510-11
510-07

5T ASRAM

4T ASRAM

-11

7.7910-10
8.0910-08
1.2210-07

5T SRAM
5 ns
5 ns

4T SRAM
20 ns
120 ns

5.6510
8.1510-10
1.9610-07

Table 3 Delay in symmetric cells.

Operation
Writing
Reading

6T SRAM
1 ns
40 ns

Table 4 Delay in asymmetric cells.

Operation
Writing
Reading

6T ASRAM
1 ns
5 ns

5T ASRAM
10 ns
10 ns

4T ASRAM
100 ns
200 ns

SRAM cell, i.e. 1.56 10-10 watts. Second

performance factor is delay. Delay in write operation is
least in 6T SRAM cell, i.e. 1 ns. However 5T SRAM
cell shows overall minimum delay in both the operation,
read and write equal to 5 ns. After 6T cell, 5T SRAM
memory cell is preferred. Results obtained from
simulation of all asymmetric memory cells suggest that
6T ASRAM cell shows overall least power dissipation.
6T ASRAM cell shows least power dissipation in all
the three operations, e.g., standby, write and read
operation. In asymmetric configuration, leakage power
is reduced to 9.29 10-11 watts. Delay in write
operation is least in 6T SRAM cell, i.e.1 ns. However
read operation delay is greater than write operation
delay. Read operation delay of 6T ASRAM cell is 5 ns.
Comparative analysis of SRAMs in symmetric and
asymmetric configuration indicates that 6T SRAM cell
and 6T ASRAM cell are best in their categories.
Further, 6T ASRAM cell, i.e. asymmetric
configuration is more suitable as compare to symmetric
configuration of 6T SRAM cell.

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4. Conclusions
Simulation of memory cells has been performed in
TSPICE (7.1v). The leakage power is minimum in 6T

6T ASRAM

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