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    Tessent Scan (Dftadvisor) : Why The Clock Inputs On Some D Flop Flops Are Assigned Uo Faults?

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    Umesh Parashar
    The document discusses why faults on clock inputs of D flip-flops are considered unobservable. It explains that a fault on a clock line cannot be detected unless it affects the output of the flip-flop. The tool classifies certain faults as "detected by implication" if it can determine the clock must have functioned properly based on observing the data inputs and outputs. It provides examples of faults that may be classified as detected by implication after running an analysis command.

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    Tessent Scan (Dftadvisor) : Why The Clock Inputs On Some D Flop Flops Are Assigned Uo Faults?

    Uploaded by

    Umesh Parashar
    64 views3 pages
    The document discusses why faults on clock inputs of D flip-flops are considered unobservable. It explains that a fault on a clock line cannot be detected unless it affects the output of the flip-flop. The tool classifies certain faults as "detected by implication" if it can determine the clock must have functioned properly based on observing the data inputs and outputs. It provides examples of faults that may be classified as detected by implication after running an analysis command.

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    clock UO faults

    Original Title

    clock_UO

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    The document discusses why faults on clock inputs of D flip-flops are considered unobservable. It explains that a fault on a clock line cannot be detected unless it affects the output of the flip-flop. The tool classifies certain faults as "detected by implication" if it can determine the clock must have functioned properly based on observing the data inputs and outputs. It provides examples of faults that may be classified as detected by implication after running an analysis command.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    64 views3 pages

    Tessent Scan (Dftadvisor) : Why The Clock Inputs On Some D Flop Flops Are Assigned Uo Faults?

    Uploaded by

    Umesh Parashar
    The document discusses why faults on clock inputs of D flip-flops are considered unobservable. It explains that a fault on a clock line cannot be detected unless it affects the output of the flip-flop. The tool classifies certain faults as "detected by implication" if it can determine the clock must have functioned properly based on observing the data inputs and outputs. It provides examples of faults that may be classified as detected by implication after running an analysis command.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    You are on page 1of 3

    6/13/2016

    MentorGraphicsSupportNet:Portal

    SUPPORTFOR

    TessentScan(DFTAdvisor)
    TECHNOTE MG22705,05Nov2005

    WhytheclockinputsonsomeDflopflopsareassignedUOfaults?
    SYMPTOMS

    TECHNOTEID

    Whyisthisfaultsonclockinputsconsideredunobservable
    UO?

    MG22705

    TECHNOTETYPE

    WhenfaulttestingadesigntheclockinputsonsomeD
    flopflopsis
    assignedUOfaults.Howtoimprovethecoverageon
    thesesites?

    Solution
    UPDATED

    05Nov2005
    PRODUCTS

    TessentFastScan
    FlexTest
    TessentTestKompress
    ENVIRONMENT

    FlexTest
    updateimplicationdetection
    DetectbyImplicationDIFaults
    FastScan

    Solution
    ThedetectabilityoffaultsonclocklinesofDflipflops.
    Todetectafaultonaclocklineoneneedstohavesomewayof
    observingtheclocksaffectontheflipflop.Thisisdonewiththe
    Dinput.ForexamplestartwiththesimplecaseofaDflopwithjust
    aDinput,Qoutputandaclockinput.AssumingthattheDinput
    canbefullycontrolledtoa1or0.Inagoodmachinesimulation
    a0isplacedontheDinputandtheclockispulsed.Thestateof
    theflopisinitiallyXandtheeffectoftheclockcausestheoutput
    tobecome0.ThisgivesusaX0transitionontheoutput.Thesame
    istruefora1ontheinput,theoutputisaX1transition.The
    faultymachinewillmakeneithertransitionbecausetheclockwillbe
    tiedtoether0or1.Whensimulatedthiswillnoteffecttheoutput.
    TherewillonlybeXXoutput.ATPGwillonlycreateatestwhenit
    canmakethegood(notstuck)valueknown,andalsomakethefaulty
    valueknown,anddifferentfrom,theexpectedvalue.
    https://supportnet.mentor.com/portal?do=reference.technote&id=MG22705&lang=en&prod=C104S119G239P10205

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    Thisisthemainpartoftheproblem,Atiedclocklinecan't
    propagatethedatatotheoutput.Thuswithnochangeontheoutputs,
    theclocklinecan'tbeobserved.Thefaultclass
    detectedbyimplicationinfersthattheclockisnotstuckwhenitcan
    bedeterminedthattheDinputcanbeobservedforstuckat1and0.
    Anotherwaytosaythisis,becausethedatahaspropagatedfromthe
    Dtotheoutputtheclockmusthavecausedthedatatobelatched
    intotheflop.Becausetheclockoperateswithanedgebothstuckat
    fortheclockhavebeendetectedbyimplication.
    Whentherearesetsand/orresetssignalsthentheproblemof
    detectingafaultontheclockismoredifficult.Iftheresetorset
    canbeactivated(MentorDFTprimitivesetsandresetsareactiveHI)
    thenitcan'tbedeterminediftheclockchangedthestateofthe
    outputoriftheset/resetwasresponsibleforthestatechange.So,
    onlyifthesedonotexist,oraretiedinactive(to0attheprimitive
    level),canadetectbyimplicationbesafelymadeontheclock.
    Becausescanpatternscanbereordered,withanypatternbeing
    repositionedasthefirstoneapplied,itisnotpossibletocarry
    knownstatevaluescreatedinapatternintothenextpattern's
    initialstate.Avalidpatternwouldhavetoclockin,thenobserve,
    bothvaluescomingoutofastateelementtoproveithadbeenclocked.
    However,whenastateelementmustbeclockedtochangestate,itis
    possiblethatthefaultsdetectedimplythattheclockmustnotbe
    stuck.Thecommand
    "UPDateIMplicationDetections"performsananalysisonthe
    undetectedandpossiblydetectedfaultstoseeiftheycanbe
    classifiedasdetectedbyimplication.Byinvocationdefault,the
    tooldoesnotdothisanalysis,andonlyanalyzesscanpathassociated
    faultsforthedetectedbyimplicationclassification.Thesearestuck
    faultsonthescanpaththatwouldbedetectedbythefirstshiftoutof
    anypattern(thechaintestpattern,orthefirstscanpattern)thathas
    bothvalues(0and1)asexpectedoutputs.Thisdoesnotincludeclock,
    set,orresetlinefaults,butdoesincludeDandQlinefaults.The
    toolcanalsoclassifythefollowingfaultsasdetectedbyimplication
    iftheuserissuesthe"UpdateImplicationDetections"command:
    1)Astuckat1faultonthesetinputlineofatransparent
    latch,scanlatch,scanDflipflop,shadow,copy,or
    sequentialcellwhenthetooldetectsthestuckat1fault
    ontheoutput.Thesetinputstuckat1willbedeclared
    detectedbyimplication(DI).Thisisbecauseifitweresa1,
    theQwouldalwaysbesetto1,andcouldnoteverbecome
    valid0,butdetectingthesa1ontheQoutputmeansthat
    aQ=0outputwasobserved.Ifthispassesonthetester,
    thenthatimpliesthatthesetcannotbesa1.
    2)Astuckat1faultontheresetinputlineofatransparent
    latch,scanlatch,scanDflipflop,shadow,copy,or
    sequentialcellwhenthetooldetectsthestuckat0fault
    ontheoutput.Theresetinputstuckat1willbedeclared
    DI,forreasonssimilarto1)above.
    https://supportnet.mentor.com/portal?do=reference.technote&id=MG22705&lang=en&prod=C104S119G239P10205

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    3)Astuckat0faultonaclockinputlineofatransparent
    latch,scanlatch,scanflipflop,shadow,copy,or
    sequentialcellwhenthetooldetectsboththestuckat0
    andstuckat1faultsfortheassociateddataline.The
    clockinputstuckat0maybedeclaredDI,ifnoother
    inputthantheclockcancausethememoryelementtochange
    state.
    4)Astuckat0faultonadatainputlineofatransparent
    latch,scanlatch,scanDflipflop,shadow,copyor
    sequentialcellwhenthetooldetectsthestuckat0fault
    onthatmemoryelement'sQoutput,andnootherportscan
    causethestate(Qoutput)tobecome1.
    5)Astuckat1faultonadatainputlineofatransparent
    latch,scanlatch,scanDflipflop,shadow,copy,or
    sequentialcellwhenthetooldetectsthestuckat1fault
    onthatmemoryelement'sQoutput,andnootherportscan
    causethestate(Qoutput)tobecome1.
    WhatthiscomesdowntoisthatFastScan&Flextesttakecare
    toavoiddeclaringfalseoroptimisticdetections.Ourtools
    willnotcreditforfaultswithoutclearjustification.
    RelatedtothisTechNote
    MG4646ATPGUntestable(AU)faultsonlatchclock/enableinputs(TLAs)

    https://supportnet.mentor.com/portal?do=reference.technote&id=MG22705&lang=en&prod=C104S119G239P10205

    3/3

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