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Synchronous Up Counter VHDL

This document contains VHDL code for a 4-bit synchronous up counter and down counter. Both counters use a clock input C and reset input S to increment or decrement an internal signal tmp on each rising edge of the clock. If reset is asserted, tmp is set to either 0000 or 1111 for up and down counting respectively. The current value of tmp is output on port Q.

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sindhura
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261 views1 page

Synchronous Up Counter VHDL

This document contains VHDL code for a 4-bit synchronous up counter and down counter. Both counters use a clock input C and reset input S to increment or decrement an internal signal tmp on each rising edge of the clock. If reset is asserted, tmp is set to either 0000 or 1111 for up and down counting respectively. The current value of tmp is output on port Q.

Uploaded by

sindhura
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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synchronous up counter vhdl:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= "0000";
else
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;

synchronous down counter vhdl:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= "1111";
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;

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