Application Note 149

January 2015

Modeling and Loop Compensation Design of

Switching Mode Power Supplies
Henry J. Zhang

Introduction Identifying The Problem

Todays electronic systems are becoming more and more A well-designed switching mode power supply (SMPS)
complex, with an increasing number of power rails and must be quiet, both electrically and acoustically. An under-
supplies. To achieve optimum power solution density, compensated system may result in unstable operations.
reliability and cost, often system designers need to design Typical symptoms of an unstable power supply include:
their own power solutions, instead of just using commer- audible noise from the magnetic components or ceramic
cial power supply bricks. Designing and optimizing high capacitors, jittering in the switching waveforms, oscillation
performance switching mode power supplies is becoming of output voltage, overheating of power FETs and so on.
a more frequent and challenging task.
However, there are many reasons that can cause undesir-
Power supply loop compensation design is usually able oscillation other than loop stability. Unfortunately, they
viewed as a difficult task, especially for inexperienced all look the same on the oscilloscope to the inexperienced
supply designers. Practical compensation design typically supply designer. Even for experienced engineers, some-
involves numerous iterations on the value adjustment times identifying the reason that causes the instability can
of the compensation components. This is not only time be difficult. Figure 1 shows typical output and switching
consuming, but is also inaccurate in a complicated node waveforms of an unstable buck supply. Adjusting
system whose supply bandwidth and stability margin the loop compensation may or may not fix the unstable
can be affected by several factors. This application note supply because sometimes the oscillation is caused by
explains the basic concepts and methods of small signal other factors such as PCB noise. If you do not have a list
modeling of switching mode power supplies and their loop of possibilities in your mind, uncovering the underlying
compensation design. The buck step-down converter is cause of noisy operation can be very time-consuming
used as the typical example, but the concepts can be applied and frustrating.
to other topologies. A user-friendly LTpowerCADTM design L, LT, LTC, LTM, Linear Technology, the Linear logo and LTspice are registered trademarks
tool is also introduced to ease the design and optimization. and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.

VO
50mV/DIV

VSW VSW
10V/DIV 10V/DIV

AN149 F01
2.0s/DIV 200ns/DIV

Figure 1. Typical Output Voltage and Switching Node Waveforms of an Unstable Buck Converter

an149f

AN149-1
Application Note 149
VIN

CINB CINC

VOUT

MTOP1 IL
TG
RT1 CFF1
VSW L1 DCR VOUT
VFB SW VOUT
RB1 CFLT1 MBOT1 RS1 COC COB
BG
RP1
LTC3851
LTC3833
RTH1 LTC3866
ITH ETC.
CTH1
CTHP1

SENSE+
CS1
FREQ SENSE
AN149 F02
RFREQ
GND

Figure 2. A Typical Buck Step-Down Converter

(LTC3851, LTC3833, LTC3866, etc.)

For switching mode power converters, such as an LTC3851 An over-compensated system is usually stable, however,
or LTC3833 current-mode buck supply shown in Figure2, with low bandwidth and slow transient response. Such
a fast way to determine whether the unstable operation is design requires excessive output capacitance to meet the
caused by the loop compensation is to place a large, 0.1F, transient regulation requirement, increasing the overall
capacitor on the feedback error amplifier output pin (ITH) supply cost and size. Figure 3 shows typical output volt-
to IC ground. (Or this capacitor can be placed between age and inductor current waveforms of a buck converter
the amplifier output pin and feedback pin for a voltage during a load step up/down transient. Figure 3a is for a
mode supply.) This 0.1F capacitor is usually considered stable but low bandwidth (BW) over-compensated system,
large enough to bring down the loop bandwidth to low where there is large amount of VOUT undershoot/over-
frequency, therefore ensuring voltage loop stability. If the shoot during transient. Figure 3b is for a high bandwidth
supply becomes stable with this capacitor, the problem under-compensated system, which has much less VOUT
can likely be solved with loop compensation. undershoot/overshoot but the waveforms are not stable
in steady state. Figure 3c shows the load transient of a
well-designed supply with a fast and stable loop.

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AN149-2
 Application Note 149
18 18
14
IOUT IOUT
10
6
(A)

(A)
2 IL
IL
2
6 15
1.80 1.80
1.75 1.75
1.70 1.70
1.65 VOUT 1.65 VOUT
1.60 1.60
1.55
(V)

1.55

(V)
1.50 1.50
1.45 1.45
1.40 1.40
1.35 1.35
1.30 1.30
348 400 416 432 448 464 480 385 399 413 427 441 455
TIME (s) TIME (s)
AN149 F03a
AN149 F03b

a) Lower Bandwidth and Stable b) Higher Bandwidth but Unstable

18
15
12 IOUT
9
6
(A)

3
0 IL
3
6
9
1.80

1.64
VOUT
1.56
(V)

1.48

1.40

1.32
385 399 413 427 441 455
TIME (s)
AN149 F03c

c) Optimum Design with Fast and Stable Loop

Figure 3. Typical Load Transient Responses of a) An Over-Compensated System;
b) An Under-Compensated System; c) Optimum Design with a Fast and Stable Loop

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AN149-3
Application Note 149
Small Signal Modeling of Pwm Converter diode D can be replaced by a synchronous FET, which is
Power Stage still a passive switch. The active terminal a is the active
switch terminal. The passive terminal p is the passive
A switching mode power supply (SMPS), such as the buck
switch terminal. In a converter, the terminals a and p are
step-down converter in Figure 4, usually has two operating
always connected to a voltage source, such as VIN and
modes, depending on the on/off state of its main control
ground in the buck converter. The common terminal c
switch. Therefore, the supply is a time-variant, nonlinear
is connected to a current source, which is the inductor in
system. To analyze and design the compensation with
the buck converter.
conventional linear control methods, an averaged, small
signal linear model is developed by applying linearization To change the time-variant SMPS into a time-invariant
techniques on the SMPS circuit around its steady state system, the 3-terminal PWM cell average modeling method
operating point. can be applied by changing the active switch Q to an aver-
aged current source and the passive switch (diode) D to an
Modeling Step 1: Changing to a Time-Invariant averaged voltage source. The averaged switch Q current
System by Averaging over TS equals d iL and the averaged switch D voltage equals
All the SMPS power topologies, including buck, boost or dvap, as shown in Figure 5. The averaging is applied
buck/boost converters, have a typical 3-terminal PWM over a switching period TS. Since the current and voltage
switching cell, which includes an active control switch Q sources are the products of two variables, the system is
and passive switch (diode) D. To improve efficiency, the still a nonlinear system.
Q1
SW L VO

iL

+ +
PWM CELL VIN +
iL
CO
Q1
s SW L VO Q1 ON
g iL

+ + a) L Charging Mode (Q1 On)

VIN +
D1 CO
Q1 OFF
SW L VO

iL

DUTY + +
VIN +
D1 iL CO

AN149 F04

b) L Discharging Mode (Q1 Off)

Figure 4. A Buck Step-Down DC/DC Converter and Its Two Operating Modes within One Switching Period TS

PWM CELL AVERAGE MODEL

d Q d iL
iSW iL
a c a c
+ +
VD
Vap AVERAGING + d Vap
D
(TREAT d AS A VARIABLE)


d: DUTY CYCLE
p p AN149 F05

Figure 5. Modeling Step 1: Changing 3-Terminal PWM Switching Cell to Averaged Current and Voltage Sources
an149f

AN149-4
 Application Note 149
Modeling Step 2: Linear Small Signal AC Modeling By applying this two-step modeling technique to a buck
The next step is to expand the product of variables to get converter, as shown in Figure 8, the buck converter power
the linear AC small signal model. For example, a variable stage can be modeled as simple voltage source, d VIN,
followed by an L/C 2nd-order filter network.
x=X+ x , where X is the DC steady state operating point
and x is the AC small signal variation around X. Therefore, Based on the linear circuit in Figure 8, since the control
the product of two variables xy can be rewritten as: signal is the duty cycle d and the output signal is vOUT,
the buck converter can be described by the duty-to-output
x y = ( x + X ) ( y + Y ) = x Y + X y + X Y + x y transfer function Gdv(s) in the frequency domain:
SMALL SIGNAL AC DC(OP) IGNORE
s
Figure 6. Expand the Product of Two Variables for Linear VIN 1+
Small Signal AC Part and DC Operating Point v o sz _ ESR
Gdv (s) = = (1)
Figure 6 shows that the linear small signal AC part can be d s s2
1+ + 2
separated from the DC operating point (OP) part. And the o Q o

product of two AC small signal variations ( x y ) can be
ignored, since it is an even smaller value variable. Follow- where,
ing this concept, the averaged PWM switching cell can be 1
rewritten as shown in Figure 7. sz _ ESR = 2f z _ ESR = (2)
rC C
AVERAGE MODEL
d iL d iL = d IL + D iL + D IL
r
a c a c
1 1+ L
o = 2f wo = R 1 (3)
L C r L C
+
d Vap +
1+ C
R
AN149 F07
p p
d vap = d Vap + D v ap + D Vap 1 1
Q= (4)
Figure 7. Modeling Step 2: AC Small Signal Modeling o L rL R
+ C rc +
by Expanding the Products of Variables rL + R rL + R

PWM CELL SMALL (AC) SIGNAL MODEL

Q1 d IL + D !L
a c L VO c L VO
a

iL iL
+ +
VIN + DUTY VIN + +
D1 CO CO

p d Vap + D ! ap p

1. AVERAGE Vap = VIN

2. KEEP SMALL AC SIGNAL !IN = 0

c L VO
ASSUMING VIN IS CONSTANT: a
d VIN + D ! in = d VIN iL
+
+ CO

d VIN
p
AN149 F08

Figure 8. Changing a Buck Converter into an Averaged, AC Small Signal Linear Circuit
an149f

AN149-5
Application Note 149
Function Gdv(s) shows that the buck converter power-stage Small Signal Model of the Boost Step-Up Converter
is a 2nd-order system with two poles and one zero in the Using the same 3-terminal PWM switching cell average
frequency domain. The zero sZ_ESR is generated by the small signal modeling method, the boost step-up converter
output capacitor C and its ESR rC. The resonant double
can be modeled too. Figure 10 shows how to model and
poles O are generated by the output filter inductor L and
convert the boost converter to its linear AC small signal
capacitor C.
model circuit.
Since the poles and zero frequencies are functions of the
output capacitor and its ESR, the bode plots of function VIN L SW D VO
c p
Gdv(s) varies with different choices of supply output ca-
iL
pacitor, as shown in Figure 9. The small signal behavior d ESR LOAD
Q
of the buck converter power stage highly depends on the + R
CO
choice of output capacitors. If the supply has small output a

capacitance or very low-ESR output capacitors, the ESR

zero frequency can be much higher than the resonant pole 1. AVERAGING
frequency. The power stage phase delay can be close to
180 degrees. As a result, it can be difficult to compensate VIN L d
vO
the loop when the negative voltage feedback loop is closed.

+

iL
d iL ESR
40 R
+
fo fz_C_ESR
CO

20
DOUBLE POLES
180 2. SMALL AC SIGNAL
GAIN (GdV)

0 ESR ZERO
+90 L d VO + D

+

L
20 ESR
d IL + L D
R
+
CO
p
-40
1103 1104 1105 1106
AN149 F10
100
FREQUENCY (Hz)

30 Figure 10. AC Small Signal Modeling Circuit of a Boost

fo fz_C_ESR Step-Up Converter
0
The boost power stage transfer function Gdv(s) can be
30 derived in Equation (5). It is also a 2nd-order system
PHASE (GdV)

60
with L/C resonance. Different from the buck converter,
the boost converter has a right-half-plane zero (RHPZ) in
90 addition to the COUT ESR zero. The RHPZ causes increased
80
gain but reduced (negative) phase. Equation 6 also shows
120
30
that the RHPZ varies with duty cycle and load resistance.
180 Since the duty-cycle is a function of VIN, the boost power
100 1103 1104 1105 1106
FREQUENCY (Hz) stage transfer function Gdv(s) varies with VIN and load
current. At low VIN and heavy load IOUT_MAX, the RHPZ is
AN149 F09

REF-DESIGN: COUT 3 X 470F

TANTALUM CAP. ESR rC = 30m at its lowest frequency and causes significant phase lag.
IN SYSTEM: COUT 2 X 220F
POLYMER CAP. ESR rC = 12m
This makes it difficult to design a high-bandwidth boost
converter. As a general design rule, to ensure loop stabil-
Figure 9. COUT Capacitor Variation Causes Significant ity, people design the boost converter bandwidth at less
Power Stage Gdv(s) Phase Variation.
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AN149-6
 Application Note 149
than 1/10 of its lowest RHPZ frequency. Several other Close The Feedback Loop with Voltage Mode
topologies, such as the positive-to-negative buck/boost, Control
flyback (isolated buck/boost), SEPIC and CUK converters, The output voltage can be regulated by a closed feedback
all have an undesirable RHPZ and cannot be designed for loop system. For example in Figure 12, when the output
high bandwidth, fast transient solutions. voltage VOUT increases, the feedback voltage VFB increases
v and the output of the negative feedback error amplifier
Gdv ( s ) = o
(5) decreases, so the duty cycle d decreases. As a result,
d
VOUT is pulled back to make VFB = VREF. The compensa-
VIN L tion network of the error op amp can be a Type I, Type II
1 s R (1 D) (1+ s rc C) or TypeIII feedback amplifier network. There is only one
=
(1 D) 2
control loop to regulate the VOUT. This control scheme is
L LC referred to as voltage mode control. Linear Technologys
1+ s + s2
R (1 D) (1 D)2
2
LTC3861 and LTC3882 are typical voltage mode buck
controllers.
fRHPZ =
( 1 D) RLOAD (6)
2
L
2 L + RAMP

70
D
ESR VO VC
PWM
+ R
VIN R2
50 CO LOAD

30 DT S
GAIN (dB)

TS
VFB
D
10 RAMP
COMP D = k VC

R1
+
10 VC +
VIN(MIN), IO(MAX)
COMPARATOR
VIN(MAX), IO(MIN) RHPZ
-30 VREF
100 1103 1104 1105 1106
fnn (Hz) FEEDBACK CONTROL
L
200
RAMP
+
124 D
ESR VO VC
PWM
+ R
VIN R2
48 CO LOAD
PHASE ()

DT S
28
TS
VFB
D
RAMP
104 COMP D = k VC AN149 F12

R1
+ Figure 12. Voltage Mode Buck Converter Diagram with
180 VC
Closed Voltage Feedback Loop
+
100 1103 1104 1105 COMPARATOR
1106
fnn (Hz)
AN149 F11b VREF

FEEDBACK
Figure 11. Boost Converter Power Stage SmallCONTROL
Signal
Duty-To-VO Transfer Function Varies with VIN and Load

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AN149-7
Application Note 149
To optimize a voltage mode PWM converter, as shown in Where
Figure 13, a complicated Type III compensation network 1
is usually needed to design a fast loop with sufficient 1 = ,
phase margin. As shown in Equation 7 and Figure 14, R1 (C1 + C3 )
this compensation network has 3 poles and 2 zeros in the 1 1
frequency domain: the low frequency integration pole (1/s) Z1 = , Z2 = ,
provides high DC gain to minimize DC regulation error, R2C1 C2 (R1 + R3 )
the double-zeros are placed around the system resonant 1 1
frequency f0 to compensate the 180 phase delay caused P1 = , P2 =
R3C2 C1C3
by power stage L and C, the 1st high frequency pole is R 2
placed to cancel COUT ESR zero at fESR, and the 2nd high C1 + C3

frequency pole is placed after the desired bandwidth fC to
HIGH DC GAIN
attenuate switching noise in the feedback loop. The TypeIII
TV
compensation is quite complicated, since it requires six 1
3-POLE & 2-ZERO COMPENSATOR A(s) IS NEEDED.

R/C values. It is a time consuming task to find the optimum Gdv

1
+1
0
1
combination of these values. Vi 1 SLOPE @ fC A(s)
n 2
fC
A(s) 0 f0 fESR f
C3
2
1 = 20dB/DECADE fSW
Zi Zf 1
C1
R2 HF NOISE REJECTION
C2
R3
AN149 F14

vO
R1 Figure 14. Type III Compensation A(s) Provides 3 Poles
vC and 2 Zeros to Achieve Optimum Total Loop Gain TV(s)
+
To simplify and automate the switching mode supply
design, the LTpowerCAD design tool has been developed.
VREF
This tool makes loop compensation design a much simpler
AN149 F13
task. LTpowerCAD is a free-download design tool available
at www.linear.com/LTpowerCAD. It helps users to select a
Figure 13. A Type III Feedback Compensation Network
for a Voltage Mode Converter
power solution, design power stage components, and op-
timize supply efficiency and loop compensation. As shown
v c
=
(
1 1+ s
Z1
1+ s )(
Z2 ) in the Figure 15 example, for a given Linear Technology
voltage mode controller such as the LTC3861, its loop
( )( )
(7)
v o s 1+ s 1+ s parameters are modeled in the design tool. For a given
P1 P2 power stage, users can place the pole and zero locations
(frequencies), then follow the program guide to put in
real R/C values and check the overall loop gain and load
transient performance in real time. After that, the design
can also be exported to an LTspice simulation circuit for
a real time simulation.

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AN149-8
 Application Note 149

(a) LTpowerCAD Power Stage Design Page

(b) LTpowerCAD Loop Compensation and Load Transient Design Page

Figure 15. LTpowerCAD Design Tool Eases the Type III Loop Design for Voltage Mode Converters
(Free-download from www.linear.com/LTpowerCAD)
an149f

AN149-9
Application Note 149
Adding a Current Loop for Current Mode Control ERROR OP AMP
SLOPE COMP OUTPUT
The single loop voltage mode control has some limitations.
It requires a fairly complicated Type III compensation
~IOUT
network. The loop performance can vary significantly with
output capacitor parameters and parasitics, especially the INDUCTOR
CURRENT
capacitor ESR and PCB trace impedance. A reliable supply SIGNAL
also requires fast overcurrent protection, which requires a
fast current sensing method and fast protection compara- TOP FET
GATE SIGNAL
tor. For high current solutions which require paralleling
of many phases, an additional current sharing network/ AN149 F17

loop is required. Figure 17. Peak Current Mode Control Signal Waveforms
Adding an inner current sensing path and feedback loop 20
fWP fz_C_ESR
to the voltage-mode converter makes it a current mode- 10
controlled converter. Figures 16 and 17 show the typical
LF POLE
peak current-mode buck converter and how it works. The 0

GAIN GCV (dB)

internal clock turns on the topside control FET. After that, 10
as soon as the sensed peak inductor current signal reaches
the amplifier ITH pin voltage VC, the top FET is turned 20
ESR ZERO
off. Conceptually, the current loop makes the inductor a
-30
controlled current source. Therefore, the power stage with
closed current loop becomes a 1st-order system, instead -40
1103 1104 1105 1106
of a 2nd-order system with L/C resonance. As a result,
100
FREQUENCY (Hz)
the phase lag caused by the power stage poles decreases
0
from 180 degrees to about 90 degrees. Less phase delay fWP fz_C_ESR
20
makes it much easier to compensate the outer voltage loop.
This also makes the power supply less sensitive to output 40

capacitor or inductance variation, as shown in Figure 18. 60

PHASE GCV ()

100
L RSENSE
120
+ >90
+ 140
D KI rC VO VO
PWM 160
+ VIN R
C
180
100 1103 1104 1105 1106
FREQUENCY (Hz)
NEW POWER STAGE GCV(s) AN149 F18

D IL FEEDBACK REF-DESIGN: COUT 3 X 470F

R2 C2
TANTALUM CAP. ESR rC = 30m
KREF(s) IN SYSTEM: COUT 2 X 220F
POLYMER CAP. ESR rC = 12m

+
FB
COMPARATOR A(s)
Igm
vFB Figure 18. New Power Stage Transfer Function GCV(s)
V ITH with Closed Current Loop

C gm R1 C1
+
RTH
CTHP
RO
ERROR The inductor current signal can be sensed directly with an
0P-AMP
CTH
VREF
additional RSENSE, or indirectly via the inductor winding
DCR or FET RDS(ON). All provide several other important
COMPENSATION NETWORK
LTC385x
AN149 F16
benefits from current mode control. As shown in Figure
Figure 16. Block Diagram of Current-Mode Converter with 17, since the inductor current is sensed and limited by the
an Inner Current Loop and Outer Voltage Feedback Loop amplifier output voltage in a cycle-by-cycle fashion, the
an149f

AN149-10
 Application Note 149
system has a more accurate and faster current limit under Modeling New Power Stage with Closed
overload or inductor current saturation. The inrush inductor Current Loop
current is also tightly controlled during power-up or input Figure 19 shows a simplified 1st order model of the buck
voltage transients. When multiple converters/phases are converter power stage with inner current loop by just treat-
paralleled, with current mode control, it is very easy to ing the inductor as a current source controlled by amplifier
share current among supplies by tying the amplifier ITH ITH pin voltage C. A similar method can be used for other
pins together to implement a reliable PolyPhase design. topologies with inductor current mode control. How good
Typical current mode controllers include Linear Technol-
is this simple model? Figure 20 shows the comparison of
ogys LTC3851A, LTC3833 and LTC3855, etc.
transfer function GCV(s) = vOUT/vC between the 1st order
model and a more complicated but accurate model. It is
Peak vs. Valley Current Mode Control Methods
for a current mode buck converter running at 500kHz
The current mode control method shown in Figures 16 and switching frequency. In this example, the 1st order model
17 is peak inductor current mode control. The converter is accurate up to 10kHz, ~1/50 of the switching frequency
operates with a fixed switching frequency fSW, making it fSW. After that, the phase plot of the 1st order model is no
easy for clock synchronization and phase interleaving, longer accurate. So this simplified model is only good for
especially for paralleled converters. However, if the load a design with low bandwidth.
step-up transient occurs just after the control FET gate
is turned off, the converter has to wait the FET off-time VITH = (ki RSENSE ) IL = k VC IL
TOFF until the next clock cycle to respond to the transient. +
This TOFF delay is usually not a problem, but it matters GAIN: kVC rC VO VO
for a really fast transient system. Besides, the control R
C
FET minimum on-time (TON_min) cannot be really small
since the current comparator needs noise blanking time to
INDUCTOR ~ CURRENT SOURCE
avoid false triggering. This limits the maximum switching SINGLE POLE

frequency fSW for high VIN/VOUT step-down ratio applica-

tions. In addition, peak current mode control also requires KREF(s) R2 C2
certain slope compensation to keep the current loop stable
FB
when the duty-cycle is over 50%. This is not a problem
for Linear Technologys controllers which usually have Igm
R1 C1
vFB
built-in adaptive slope compensation to ensure current VC ITH
gm

loop stability over the full duty-cycle range. The LTC3851A RTH RO
+

and LTC3855 are typical peak current mode controllers. CTHP

ERROR
0P-AMP
CTH
VREF
Valley current mode controllers generate a controlled FET
on-time and wait till the inductor valley current reaches its COMPENSATION NETWORK
LTC385x
valley limit (VITH) to turn on the control FET again. Therefore, AN149 F19

the supply can respond to load step-up transients during Figure 19. A Simple, 1st Order Model for a Current
the control FET TOFF. Besides, since the on-time is fixed, Mode Buck Converter
the control FET TON_min can be smaller than with peak
current mode control to allow higher fSW for high step-
down ratio applications. Valley current mode control also
does not need additional slope compensation for current
loop stability. However, since the switching period TS is
allowed to vary, the switching node waveform may look
more jittery on the scope with valley current mode con-
trol. The LTC3833 and LTC3838 are typical valley current
mode controllers.
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AN149-11
Application Note 149
20 specifications/performances of the power supply. The
1ST ORDER MODEL outer voltage loop gain T(s)=GCV(s)A(s)KREF(s) is
0.782
therefore determined by the voltage feedback stage Kref(s)
and compensation stage A(s). The designs of these two
stages will largely decide the supply stability and transient
GAIN (dB)

21.56
response.
VO(s)
42.34 POWER STAGE WITH CURRENT LOOP
ACCURATE MODEL GCV(s)

63.13
100 1103 1104 1105 1106
FREQUENCY (Hz) vITH(s) FEEDBACK
POWER SUPPLY DIVIDER
LOOP GAIN KREF(s)
0 T(s) = GCV KREF A(s)

vFB(s)
20

+
ITH COMPENSATOR VREF
40 (INTERNAL)
A(s)
PHASE ()

AN149 F21

60
Figure 21. Control Block Diagram for Feedback Loop Design
80
In general, the performance of the closed voltage loop T(s)
110 is evaluated by two important values: the loop bandwidth
and the loop stability margin. The loop bandwidth is quanti-
120
100 1103 1104 1105 1106 fied by the crossover frequency fC, at which the loop gain
FREQUENCY (Hz)
AN149 F20 T(s) equals one (0dB). The loop stability margin is typically
Figure 20. GCV(s) Comparison Between the 1st Order quantified by the phase margin or gain margin. The loop
Model and Accurate Model for a Current Mode Buck phase margin m is defined as the difference between
the overall T(s) phase delay and 180 at the crossover
In fact, it is quite complicated to develop an accurate small
frequency. A 45-degree or 60-degree minimum phase
signal model for current mode converters for the full fre-
margin is usually needed to ensure stability. For current
quency range. R. Ridleys current mode model [3] is the
mode control, to attenuate switching noise in the current
most popular one used by the power supply industry for
loop, the loop gain margin is defined as the attenuation
both peak current mode and valley current mode controls.
at fSW. In general, a minimum 8dB attenuation (8dB
Most recently, Jian Li developed a more intuitive circuit
loop gain) at fSW is desired.
model [4] for current mode control, which can also be used
for other current mode control methods. To make it easy, Select Desired Voltage-Loop Crossover Frequency fC
the LTpowerCAD design tool implements these accurate
models, so even an inexperienced user can easily design Higher bandwidth helps obtain fast transient response.
a current mode power supply, without much knowledge However, increasing the bandwidth usually reduces the
of Ridley or Jian Lis models. stability margin and makes the control loop more sensitive
to switching noise. An optimum design usually achieves a
good trade-off between the bandwidth (transient response)
Loop Compensation Design of a Current Mode
and stability margin. In fact, current mode control also
Converter
introduces a pair of double-poles n by the sampling effect
In Figures 16 and 21, the power stage Gcv(s) with closed of the current signal at 1/2fSW [3]. These double poles
current loop is determined by the selection of power introduce an undesirable phase delay around fSW. In
stage components, which are mainly decided by the DC general, to obtain sufficient phase margin and PCB noise

an149f

AN149-12
 Application Note 149
attenuation, the crossover frequency is selected to be where:
less than 1/101/6 of the phase switching frequency fSW. 1
f z _ ref = (12)
f 2 R2 C2
fC SW (8)
6
and
Design of the Feedback Divider Network Kref(s) with 1 1
R1, R2, C1 and C2 fp _ ref = (13)
KREF 2 R2 (C1 + C2 )

In Figure 16, the DC gain KREF of Kref(s) is the ratio be-
tween the internal reference voltage VREF and the desired fCENTER = f z _ ref fp _ ref (14)
DC output voltage Vo. Resistors R1 and R2 are used to
set the desired output DC voltage. 1 1
= = fC
2 R2 KREF C2 (C1 + C2 )
KREF R2
R1 =
1 KREF (9)
C2 1
Gain HF(dB) = 20 log (15)
where C1 + C2 KREF

VREF 0
KREF =
Vo (10)
5
The optional capacitor C2 can be added to improve the
dynamic response of the feedback loop. Conceptually,
GAIN (dB)

GAIN
at high frequency, C2 provides a low impedance 10

feed-forward path for the output voltage AC signal and

therefore, speeds up transient responses. But C2 may also 15
bring undesirable switching noise into the control loop.
Therefore, an optional C1 filter capacitor may be added to
20
attenuate the switching noise. As shown in Equation 11, 100 1103 1104 1105 1106
FREQUENCY (Hz)
the overall resistor divider transfer function KREF(s) with AN149 F22a

C1 and C2 has one zero and one pole. Figure 22 shows 40

the bode plot of KREF(s). By designing fz_ref < fp_ref, C1
and C2 together with R1 and R2 introduce a phase boost 30
in a frequency band centered at fCENTER, which is given in
equation (14). If fCENTER is placed at the targeted crossover 20 fC
PHASE ()

frequency fC, Kref(s) provides phase lead to the voltage PHASE

loop and increases the phase margin. On the other hand, 10

Figure22 also shows that C1 and C2 increase the divider

gain at high frequency. This is undesirable because a gain 0

increase at high frequency makes the control loop more

10
sensitive to switching noise. The increase in high-frequency 100 1103 1104 1105 1106
gain by C1 and C2 is given by Equation 15. FREQUENCY (Hz)
AN149 F22b

s Figure 22. Transfer Function Bode Plot of Resistor

1+ Divider Gain KREF(s)
FB 2 f z _ ref
KREF ( s ) = = KREF (11)
o s
1+
2 fp _ ref

an149f

AN149-13
Application Note 149
For a given C1 and C2, the increased phase REF from the From the control block diagram in Fig.21, the voltage loop
divider network can be calculated by Equation 16. Further, regulation error can be quantified by:
the maximum possible phase boost for a given output Error VREF VFB 1
voltage is given by Equation 17, for C2 >> C1. As shown, = = (19)
the maximum phase boost REF_max is determined by Vo VREF A(s) GCV (s) S= j2f

the divider ratio KREF = VREF/VO. Since VREF is fixed for a
given controller, higher phase boost can be achieved with Therefore, to minimize the DC regulation error, a large
higher output voltage VO. DC gain of A(s) is very desirable. To maximize the DC
gain of A(s), a capacitor Cth is first placed at the amplifier
C1 1 output ITH pin to form an integrator. In this case, the A(s)
REF = 2 tg1 90 (16)
C1 + C2 KREF transfer gain is:

ith ( s ) gm 1
1 A (s) = = (20)
REF = 2 tg1 FB ( s ) Cth s
KREF 90 (17)

Figure 23 shows the schematic diagram of A(s) and its
The selections of REF, C1 and C2 are a trade-off between Bode plot. As shown, capacitor Cth creates an integration
desired phase boost and undesired high frequency gain term in A(s) with an infinitely high DC gain. Unfortunately,
increase. The overall loop gain needs to be checked later in addition to the original 180 degrees of negative feed-
for optimized values. back, Cth adds another 90 degrees phase lag. Including
the 90 degree phase of the 1st-order system power stage
Design Type II Compensation Network of Voltage- GCV(s), the total voltage loop phase is close to 360 de-
Loop ITH Error Amplifier grees at the crossover frequency fC and the loop is close
The ITH compensation A(s) is most critical to the loop to being unstable.
compensation design because it determines the DC gain, In reality, the output impedance of the current source gm
crossover frequency (bandwidth) and the phase/gain amplifier is not an infinite value. In Figure 24, Ro is the
margins of the supply voltage loop. For a current source internal output resistance of the gm amplifier ITH pin.
output, gm transconductance-type amplifier, its transfer Linear Technology controllers Ro is usually high, in the
function A(s) is given by Equation 18: 500k 1M range. Therefore, the single capacitor A(s)
ith ( s ) transfer function becomes Equation (21). It has a low
A (s) = = gm Zith (s) (18) frequency pole fpo determined by RO Cth. So the DC gain
FB ( s )
of A(s) is actually gm RO. As shown in Figure 24, A(s)
where, gm is the gain of the transconductance error ampli- still has 90 degree phase lag at the expected crossover
fier. Zith(s) is the impedance of the compensation network frequency fC_exp.
at the amplifier output ITH pin. ith ( s ) 1
A (s) = = gm Ro (21)
FB ( s ) 1+ s spo

where,
1
spo = (22)
Ro Cth

an149f

AN149-14
 Application Note 149
90
80
70
fC
60
STEP 1
50

GAIN (dB)
40
30
20
COMPENSATOR GAIN A(s)
10
igm FB
ITH ITH vFB 0
VITH FB 10
+
gm 0

Cth VREF
90
45
ZITH(s)

PHASE ()
90

135

180
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
AN149 F23

Figure 23. Step 1: Simple Capacitor Compensation Network A(s) and Its Bode Plot

90
DC GAIN gm RO
80
70
fC
60
50
GAIN (dB)

40
30
20
COMPENSATOR GAIN A(s)
10
igm FB SPO LF POLE
ITH ITH vFB 0
INTRODUCED BY RO

VITH FB 10
+
gm 0
RO

Cth VREF
90
45
ZITH(s)
PHASE ()

90

135

180
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
AN149 F24

Figure 24. One-Pole A(s) That Includes gm Amplifier Output Impedance RO

an149f

AN149-15
Application Note 149
To increase the phase at fC, a resistor Rth is added in series Unfortunately, there is a penalty of adding the zero sthzthe
with Cth to create a zero, as shown in Equation 23 and gain of A(s) is significantly increased at high frequency
Figure 25. The zero contributes up to +90 degree phase beyond fC. So the switching noise is more likely to come
lead. As shown in Figure 25, if the zero sthz is placed be- into the control loop with less A(s) attenuation at the
fore the crossover frequency fC, A(s)s phase at fC can be switching frequency. To compensate this gain increase and
significantly increased. As a result, it increases the phase attenuate PCB noise, it is necessary to add another small
margin of the voltage loop. ceramic capacitor Cthp from the ITH pin to IC signal ground,
as shown in Figure 26. Typically, choose Cthp<<Cth. In
ith ( s ) 1+ s s the PCB layout, filter capacitor Cthp should be placed as
A (s) = = gm Ro thz (23)
FB ( s ) s
1+ s close to the ITH pin as possible. By adding Cthp, the final
po compensation transfer function A(s) is given in Equation25
and Equation26 and its Bode plot is shown in Figure26.
where, Cthp introduces a high-frequency pole sthp, which should
1 be located between the crossover frequency fC and the
sthz = (24)
Rth Cth switching frequency fS. Cthp reduces A(s) gain at fS, but

90
80
70
fC
60
50
GAIN (dB)

STEP 2 40 fs

30
20
COMPENSATOR GAIN A(s)
10
igm FB
ITH ITH vFB 0 STHZ BOOSTS
PHASE MARGIN

VITH FB 10
+
gm 0
Rth RO

Cth VREF
90
45
ZITH(s)
PHASE ()

90

135

180
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
AN149 F25

Figure 25 Step 2: Adding RTH Zero to Boost Phase One-Pole, One-Zero Compensation A(s)

an149f

AN149-16
 Application Note 149
90
80
70
fC
60
50 fs

GAIN (dB)
STEP 3 40
30
20
COMPENSATOR GAIN A(s)
10
igm FB HF POLE
ITH ITH vFB 0
VITH FB 10
+
gm 0
Rth Cthp RO

Cth VREF

45
ZITH(s)

PHASE ()
90
90

135

180
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
AN149 F24

Figure 26. Step 3: Adding High Frequency Decoupling Cthp - Two-Pole, One-Zero Compensation A(S)

may also decrease the phase at fC. The location of sthp This two-pole, one-zero compensation network on the
is a trade-off between the phase margin and supply PCB amplifier ITH pin is also called a Type II compensation
noise immunity. network. In summary, there are two capacitors CTH and
CTHP, and one resistor RTH. This R/C network together
s
1+ with the amplifier output resistance Ro, generates a typical
ith ( s ) sthz transfer function shown in Figure 27, with one zero at fz1
A (s) = = gm Ro (25)
FB ( s ) s s and two poles at fpo and fp2.
1+
s s 1+
po thp 1
CTH Ro
where, GAIN
1 1
1 1 RTH CTH R C
TH THP
sthp = if Cthp << Cth (26)
Cth Cthp Rth Cthp
Rth
Cth + Cthp gm RTH

fpo fz1 fC fp2 FREQUENCYAN149 F27
Since the current mode power stage is a quasi-single-pole
system, the two-pole and one-zero compensation network Figure 27. Conceptual Plot of Type II Compensation
Network Transfer Function
in Figure 26 is generally sufficient to provide the needed
phase margin.

an149f

AN149-17
Application Note 149
Compensation R/C Values vs. Load Step Transient 2) RTHs effects on load step transient. Figure 29 shows
Response that the RTH affects the location of zero fz1 and pole fp2.
More importantly, a larger RTH increases the A(s) gain
The previous section explained the frequency domain
between fz1 and fp2. As a result, a larger RTH directly
behavior of the Type II compensation network. In a closed-
increases the supply bandwidth fc and reduces the VOUT
loop supply design, one important performance parameter
undershoot/overshoot at load transient. However, if RTH
is the supplys output voltage undershoot (or overshoot)
is too large, the supply bandwidth fc can be too high
during a load step-up (or load step-down) transient, which
with insufficient phase margin.
is usually directly impacted by loop compensation design.
fz1 fp2
1) CTHs effects on a load step transient. The CTH affects GAIN
1 1
the location of low frequency pole fpo and zero fz1. As RTH CTH RTH CTHP
shown in Figure 28, a smaller CTH can increase the low-

to-mid frequency gain of transfer function A(s). As a

result, it can reduce the load transient response settling gm RTH

time without much impact on the VOUT undershoot (or FREQUENCY

a)
overshoot) amplitude. On the other hand, a smaller CTH
means higher fz1 frequency. This may reduce the phase 10

boost by fz1 at the targeted crossover frequency fC. 0

fpo
10
1
AC VO(T) (mV)

CTH Ro
GAIN fz1 20
RTH
1
RTH CTH 30

40 RTH = 37k
gm RTH RTH = 23k
RTH = 17k
50
FREQUENCY 10 0 10 20 30 40 50 60 70
a) TIME (s)
AN149 F29
10 b)
0 Figure 29. RTHs Effects on Transfer Function and Load Transient

10 3) CTHPs effects on load step transient. Figure 30 shows

AC VO(T) (mV)

CTH
that CTHP affects the location of pole fp2. CTHP is used
20
as a decoupling capacitor to reduce switching noise on
30 the ITH pin to minimize switching jitter. If the supply
bandwidth fc > fp2, CTHP does not impact load transient
CTH = 620pF
40
CTH = 1100pF response much. If CTHP is overdesigned so that fp2 is
50
CTH = 2200pF close to fc, it can reduce the bandwidth and phase margin,
10 0 10 20 30 40 50 60 70 resulting in increased transient undershoot/overshoot.
TIME (s)
AN149 F28

b)

Figure 28. CTHs Effects on Transfer Function and Load Transient

an149f

AN149-18
 Application Note 149
Design a Current Mode Supply With the
GAIN
fp2 LTpowerCAD Design Tool
1

RTH CTHP With the LTpowerCAD design tool, users can easily design
and optimize loop compensation and load transient per-
gm RTH formance of Linear Technologys current mode supplies.
FREQUENCY Many Linear products have been accurately modeled with
a) their loop parameters. First, users need to design the power
10 stage, in which they need to design the current sensing
network and ensure a sufficient AC sensing signal to the
0
IC. After that, on the loop design page, they can adjust
10 the loop compensation R/C values by simply moving the
AC VO(T) (mV)

CTHP sliding bars and observing the overall loop bandwidth,

20
phase margin and corresponding load transient perfor-
30
mance. For a buck converter, users usually need to design
a bandwidth below 1/6 fSW, have at least 45 degrees (or 60
40 CTHP = 0pF
CTHP = 47pF
degrees) of phase margin and have at least 8dB total loop
50
CTHP = 120pF gain attenuation at fSW. For a boost converter, because
10 0 10 20 30 40 50 60 70 of the right-half-plane zero (RHPZ), users need to design
TIME (s)
AN149 F30 the supply bandwidth below 1/10 of the worst case RHPZ
b)
frequency. The LTpowerCAD design file can be exported to
Figure 30. CTHPs Effects on Transfer Function and Load Transient LTspice for real-time simulation to check detailed supply
dynamic performance, such as load transient, power-up/
down, overcurrent protection, etc.

R-DIVIDER
C1, C2

TYPE II
RTH/CTH/CTHP

AN149 F31

Figure 31. LTpowerCAD Design Tool Eases Loop Compensation Design and Transient Optimization

an149f

AN149-19
Application Note 149
Measure the Supply Loop Gain POWER SUPPLY

VOUT+
The LTpowerCAD and LTspice programs are not intended DC/DC CHANNEL 2
VIN VOUT
to replace final bench loop gain measurement of the real POWER STAGE

power supply. It is always necessary to make a measure- 50 OUTPUT

ment before releasing the design for final production. VOS+

CHANNEL 1
Though the models of power supplies are theoretically LTC38XX VOS
CONTROLLER
correct, they cannot take full account of circuit parasitics
and component nonlinearity, such as the ESR variations of AN149 F32

output capacitors, the nonlinearity of inductors and capaci- Figure 32. Test Setup of the Power Supply Loop
tors, etc. Also, circuit PCB noise and limited measurement Gain Measurement
accuracy may also cause measurement errors. Thats why, 70
sometimes, the theoretical model and measurement can 60
diverge considerably. If this happens, a load transient test 50
can be used to further confirm the loop stability. 40

Figure 32 shows the typical supply loop gain measurement

GAIN (dB)
30
fC fS
setup of a nonisolated power supply using a frequency 20

analyzer system. To measure the loop gain, a 50 to 10

100 resistor is inserted into the voltage feedback loop 0

and a 50mV isolated AC signal is applied on this resistor. 10 CALCULATED

MEASURED
Channel 2 is connected to the output voltage and Channel1 20
100 1103 1104 1105 1106
is connected to the other side of this resistor. The loop
gain is calculated as Ch2/Ch1 by the frequency analyzer 180

system. Figure 33 shows the measured and LTpowerCAD 160

calculated loop Bode plot of a typical LTC3851A current 140

CRITICAL
mode supply. They have good matching in the critical 120 FREQUENCY RANGE
frequency range from 1kHz to 100kHz.
PHASE ()

100

80

60

40

20

0
100 1103 1104 1105 1106
FREQUENCY (Hz)
AN149 F33

Figure 33. Measured and LTpowerCAD

Modeled Loop Gain of a Current Mode Buck
Converter

an149f

AN149-20
 Application Note 149
Other Reasons That Cause Instability There are some important considerations for PCB
layout [6]. In general, Kelvin sensing is usually required
Operating Conditions: with a pair of closely routed current sensing traces back
If the supply switching or output voltage waveform looks to SENSE+ and SENSE pins. If a PCB via is used in the
unstable or jittery on the oscilloscope, first, users need to SENSE net, make sure this via does not contact other VOUT
make sure the supply is operated in a steady state condition, planes. The filter capacitor across SENSE+ and SENSE
without load or input voltage transients. For very small should be placed as close to the IC pins as possible with
or very large duty cycle applications, if pulse-skipping a direct trace connection. Sometimes, filter resistors are
operation happens, check whether the minimum on-time needed and these resistors must be close to the IC too.
or off-time limitation has been reached. For supplies that
Control Chip Component Placement and Layout:
require an external synchronization signal, make sure
the signal is clean and within the linear range given by Placement and layout of components around the control IC
controller data sheet. Sometimes it is also necessary to are also critical [6]. All the ceramic decoupling capacitors
adjust the phase-locked-loop (PLL) filter network. should be close to their pins, if possible. It is especially
important for the ITH pin capacitor Cthp to be as close
Current Sensing Signal and Noise: to the ITH and IC signal ground pins as possible. The
To minimize the sensing resistor power loss, in a current control IC should have a separate signal ground (SGND)
mode supply, the maximum current sensing voltage is island from the power supply power ground (PGND). The
typically very low. For example, LTC3851A may have switching nodes, such as SW, BOOST, TG and BG, should
50mV maximum sensing voltage. It is possible for PCB be kept away from sensitive small signal nodes, such as
noise to disturb the current sensing loop and cause an current sensing, feedback and ITH compensation traces.
unstable switching behavior. To debug whether the prob-
lem is indeed a loop compensation problem, a large 0.1F Summary
capacitor can be placed from ITH pin to IC ground. If the
Loop compensation design is often viewed as a challenging
supply is still unstable with this capacitor, the next step task for switching mode power supplies. For applications
is to review the design. In general, the inductor and cur- with fast transient requirements, it is very important to de-
rent sensing network should be designed to have at least sign the supply with high bandwidth and sufficient stability
10mV to 15mV peak-to-peak AC inductor current signal margin. This is typically a time consuming process. This
on the IC current sensing pin. Besides, the current sensing article explains the key concepts to help system engineers
traces can be rerouted with a pair of twisted jumper wires understand this task. The LTpowerCAD design tool can
to check if it solves the problem. be used to make supply loop design and optimization a
much simpler task.

an149f

AN149-21
Application Note 149
References [4] J. Li, Current-Mode Control: Modeling and its Digital
Application, Ph.D. Dissertation, Virginia Tech, Apr.
[1] J. Seago, Opti-Loop Architecture Reduces Output
2009.
Capacitance and Improves Transient Response,
Application Note 76, Linear Technology Corp., May [5] LTpowerCAD TM design tool and user guide at
1999. www.linear.com/LTpowerCAD.
[2] V. Vorperian, Simplified Analysis of PWM Convert- [6] H. Zhang, PCB Layout Considerations for Non-Isolated
ers Using the Model of the PWM Switch: Parts I and Switching Power Supplies, AN136, www.linear.com.
II, IEEE Transactions on Aerospace and Electronic
[7] H. Zhang, Basic Concepts of Linear Regulator and
Systems, Mar. 1990, Vol. 26, No.2.
Switching Mode Power Supplies, AN140,
[3] R. B. Ridley, An Accurate and Practical Small- www.linear.com.
Signal Model for Current-Mode Control,
www.ridleyengineering.com.

an149f

Linear Technology Corporation LT 0315 PRINTED IN USA

AN149-22 1630 McCarthy Blvd., Milpitas, CA 95035-7417

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