1989 Cmos Bicmos Data Book

Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741
How To Use This Book
This book has been organized by product type, beginning A Numeric Device Index is included after the Table of
with Product Information. The products then follow, be- Contents that identifies products by numeric order, rather
ginning with SRAMs, then PROMs, EPLDs, LOGIC than by device type. To further help you in identifying
(FIFO products are included in this section), RISC, Mod- parts, a Product Line Cross Reference is in the Product
ules, and ECL. A section containing military information Information section. It can be used to find the Cypress part
is next, followed by the BridgeMOSTM product family, the number that is comparable to another manufacturer's part
Cypress programming board, QuickPro, and Cypress' pro- number.
grammable logic design tool, the PLD ToolKit. Within
each section, data sheets are arranged in order of part num-
ber. Quality and Reliability aspects follow next, then Ap-
plication Briefs, and finally Thermal Data and Packages.
Published February 1, 1989
BridgeMOSTM is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation, 1989. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey
or imply any license under patent or other rights. "Cypress Semiconductor does not authorize its products for use as critical components in life support
systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypresi
Semiconductor against all damages."
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS a
QUICKPRO
PLDTOOLKIT HI
QUALITY AND
RELIABILITY

APPLICATION BRIEFS
PACKAGES

,.
~ Table of Contents
~~~DUaoR================================================================
General Product Information Page Number
Cypress Semiconductor Background ....................................................................... 1-1
Cypress Process Technology .............................................................................. 1-2
Product Selection Guide ................................................................................. 1-3
Ordering Information .................................................................................... 1-6
Product Line Cross Reference ............................................................................. 1-8
Static RAMs (Random Access Memory)

Device Number Description
CY2147 4096 x 1 Static RAM ...................................................... 2-1
CY2148 1024 x 4 Static RAM ...................................................... 2-6
CY21L48 1024 x 4 Static RAM, Low Power ............................................ 2-6
CY2149 1024 x 4 Static RAM ...................................................... 2-6
CY6116 2048 x 8 Static RAM ..................................................... 2-12
CY6117 2048 x 8 Static RAM ..................................................... 2-12
CY6116A 2048 x 8 Static RAM ..................................................... 2-19
CY6117A 2048 x 8 Static RAM ..................................................... 2-19
CY7C122 256 x 4 Static RAM Separate I/O .......................................... 2-26
CY7C123 256 x 4 Static RAM Separate 110 .......................................... 2-33
CY7C128 2048 x 8 Static RAM ..................................................... 2-40
CY7C128A 2048 x 8 Static RAM ..................................................... 2-47
CY7C130 1024 x 8 Dual Port Static RAM ............................................ 2-54
CY7C147 4096 x 1 Static RAM ..................................................... 2-76
CY7C148 1024 x 4 Static RAM ..................................................... 2-83
CY7C149 1024 x 4 Static RAM ..................................................... 2-83
CY7C150 1024 x 4 Static RAM Separate 110 .......................................... 2-90
CY7C157 16,384 x 16 Static Cache RAM ............................................... 2-98
CY7C161-1O 16,384 x 4 Static RAM Separate I/O ......................................... 2-104
CY7C161-20 16,384 x 4 Static RAM Separatel/O ......................................... 2-110
CY7C162-20 16,384 x 4 Static RAM Separate I/O ......................................... 2-110
CY7C164-1O 16,384x4StaticRAM .................................................... 2-117
CY7C166-1O 16,384 x 4 Static RAM .................................................... 2-117
CY7C164-20 16,384 x 4 Static RAM .................................................... 2-123
CY7C166-20 16,384 x 4 Static RAM with Output Enable ................................... 2-123
CY7C167 16,384 x 1 Static RAM .................................................... 2-131
CY7C167A 16,384 x 1 Static RAM .................................................... 2-138
CY7C168 4096 x 4 Static RAM .................................................... 2-145
CY7C169 4096 x 4 Static RAM .................................................... 2-145
CY7C168A 4096 x 4 Static RAM .................................................... 2-152
CY7C169A 4096 x 4 Static RAM .................................................... 2-152
CY7C170 4096 x 4 Static RAM with Output Enable ................................... 2-159
CY7C170A 4096 x 4 Static RAM with Output Enable ................................... 2-165
CY7C171 4096 x 4 Static RAM Separate I/O ............................ -. ............ 2-171
CY7CI72 4096 x 4 Static RAM Separate I/O ......................................... 2-171
CY7C171A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
CY7CI72A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
CY7C183 2 x 4096 x 16 Cache RAM ................................................ 2-185
ICY7C184 2 x 4096 x 16 Cache RAM ................................................ 2-185
CY7C185-12 8192 x 8 Static RAM .................................................... 2-193
I
CY7C186-12 8192 x 8 Static RAM .................................................... 2-193
CY7C185-20 8192 x 8 Static RAM .................................................... 2-199
I ICY7C186-20 8192 x 8 Static RAM .................................................... 2-199
CY7C187 65,536 x 1 Static RAM .................................................... 2-207
~ Table of Contents (Continued)
~~~~U~R================================================================
Static RAMs (Random Access Memory) (Continued)
Device Number Description Page Number
CY7C189 16 x 4 Static RAM .................................................... 2-215
CY7C190 16 x 4 Static RAM .................................................... 2-215
CY7C191 65,536 x 4 Static RAM Separate I/O ......................................... 2-222
CY7C192 65,536 x 4 Static RAM Separate 110 ......................................... 2-222
CY7C194 65,536 x 4 Static RAM ..................................................... 2-228
CY7C196 65,536 x 4 Static RAM with Output Enable ......................... ~ ......... 2-228
CY7C197 262,144 x 1 Static RAM ................................................. ; .. 2-234
CY7C198 32,768 x 8 Static RAM .................................................... 2-240
CY7C199 32,768 x 8 Static RAM .................................................... 2-240
CY74S189 16 x 4 Static RAM .................................................... 2-246
CY27LS03 16 x 4 Static RAM ................................................. ~ .. 2-246
CY27S03 16 x 4 Static RAM .................................................... 2-246
CY27S07 16 x 4 Static RAM .................................................... 2-246
CY93422A 256 x 4 Static RAM Separate 110 ......................................... 2-252
CY93L422A 256 x 4 Static RAM Separate 110 ......................................... 2-252
CY93422 256 x 4 Static RAM Separate I/O ......................................... 2-252
CY93L422 256 x 4 Static RAM Separate 110 ......................................... 2-252
CYM1420 128K x 8 Static RAM Module ............................................. 2-259
CYM1422 128K x: 8 Static RAM Module ............................................. 2-271
CYM1461 S12K x 8 Static RAM Module ............................................. 2-282
CYMI611 16K x 16 Static RAM Module ............................................. 2-293
CYM1623 64K x 16 Static RAM Module.; ........................................... 2-312
CYM1626 64Kx 16 Static RAM Module ............................................. 2-318
CYM1804 lK x 32 Static RAM Module Separate I/O .................................. 2-330,
CYM1822 16K x 32 Static RAM Module Separate I/O .................................. 2-337,
CYM1830 64K x 32 Static RAM Module ............................................. 2-343,
CYM1832 64K x 32 Static RAM Module ............................................. 2-355'
PROMs (Programmable Read Only Memory)

Introduction to PROMs .................................................................................. 3-1
CY7C225 512 x 8 Registered PROM .................................................. 3-4
CY7C235 1024 x 8 Registered PROM ................................................. 3-15
CY7C245 2048 x 8 Reprogrammable Registered PROM .................................. 3-26
CY7C245A 2048 x 8 Reprogrammable Registered PROM .................................. 3-38
CY7C251 16,384 x 8 Reprogrammable Power Switched PROM ............................. 3-50
CY7C254 16,384 x 8 Reprogrammable PROM ........................................... 3-50
CY7C261 8192 x 8 Reprogrammable Power Switched PROM ............................. 3-60
CY7C263 8192 x 8 Reprogrammable PROM ........................................... 3-60
CY7C265 64K Registered PROM ................................................. 3-71
CY7C266 8192 x 8 Reprogrammable EPROM .......................................... 3-81'
CY7C268 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-86
CY7C269 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-86 I

CY7C274 32,768 x 8 Reprogrammable PROM ........................................... 3-991 ,
CY7C277 32,768 x 8 Reprogrammable Registered PROM ................................. 3-107
CY7C281 1024 x 8 PROM ......................................................... 3-118
CY7C282 1024 x 8 PROM ......................................................... 3-118
CY7C285 65,536 x 8 Reprogrammable Fast Column Access PROM ......................... 3-127
~FESS Table of Contents (Continued)
~~~O~UcrOR==================================================================
PROMs (Programmable Read Only Memory) (Continued)
CY7C291 2048 x 8 Reprogrammable PROM .......................................... 3-129
CY7C292 2048 x 8 PROM ......................................................... 3-129
CY7C291A 2048 x 8 Reprogrammable PROM .......................................... 3-138
PROM Programming Information ....................................................................... 3-147
EPLDs (Eraseable Programmable Logic Devices)

Introduction to EPLDs .................................................................................. 4-1
PAL C 20 Series 16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL Device ................... .4-7
PLD C 18G8 CMOS Generic 20 Pin Programmable Logic Device ............................. .4-26
PLD C 20G lOB CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-33
PLD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20RA 10 Reprogrammable Asynchronous CMOS Programmable Logic Device ................ 4-52
PAL C 22VlOB Reprogrammable CMOS PAL Device .......................................... 4-61
PAL C 22VlO Reprogrammable CMOS PAL Device ......................................... .4-61
CY7C330 Synchronous State Machine .................................................. 4-80
CY7C331 Asynchronous Registered EPLD ............................................. .4-91
CY7C332 Combinatorial Registered EPLD ............................................ .4-103
CY7C340 EPLD Family Multiple Array Matrix High Density EPLDs .................................. .4-112
CY7C361 Ultra High Speed State Machine ............................................. 4-123
PLD Programming Information ......................................................................... 4-129
LOGIC
CY2901C CMOS 4-Bit Slice ............................................................ 5-1
CY2909A CMOS Microprogram Sequencer ............................................... 5-9
CY2910A CMOS Microprogram Controller .............................................. 5-14
CY3341 64 x 4 FIFO Serial Memory .................................................. 5-19
CY7C401 Cascadeable 64 x 4 FIFO .................................................... 5-24
CY7C403 Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-24
CY7C408A Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-34
CY7C409A Cascadeable 64 x 9 FIFO .................................................... 5-34
CY7C420 Cascadeable 512 x 9 FIFO ................................................... 5-48
:::;Y7C424 Cascadeable 1024 x 9 FIFO .................................................. 5-48
:::;Y7C51O 16 x 16 Multiplier Accumulator ............................................... 5-60
::;Y7C516 16 x 16 Multiplier ........................................................... 5-72
::;Y7C517 16 x 16 Multiplier ........................................................... 5-72
::;Y7C901 CMOS 4-Bit Slice ........................................................... 5-84
::;Y7C909 Microprogram Sequencer .................................................... 5-99
::;Y7C911 Microprogram Sequencer .................................................... 5-99
::;Y7C91O Microprogram Controller ................................................... 5-110
::;Y7C9101 CMOS 16-Bit Slice ......................................................... 5-121
::;Y7C9115 CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
)AL is a registered trademark of Monolithic Memories Inc.
~ Table of Contents (Continued)
~ ~~~~UcrOR================================================================~
RISC Page Number
Introduction to RISC .................................................................................... 6~ 1
CY7C601 32-Bit RISC Integer Unit ..................................................... 6-6
CY7C602 Floating-Point Unit ......................................................... 6-12
CY7C604 Cache Controller and Memory Management Unit ................................ 6-13
CY7C605 Multiprocessor Cache Controller and Memory Management Unit ................... 6-17
CY7C608 Floating-Point Controller .................................................... 6-18
CY7C609 Floating-Point Processor ..................................................... 6-23
Modules
Custom Module Capabilities .............................................................................. 7-1 .
ECL
CYIOE301 Combinatorial ECL 16P8 PLD ................................................. 8-1
CY100E301 Combinatorial ECL 16P8 PLD ................................................. 8-1
CYIOE302 Combinatorial ECL 16P4 PLD ................................................. 8-6
CYl00E302 Combinatorial ECL 16P4 PLD ................................................. 8-6
CYIOE422 256 x 4 ECL Static RAM .................................................... 8-11
CYl00E422 256 x 4 ECL Static RAM .................................................... 8-11
CYI0E474 1024 x 4 ECL Static RAM ................................................... 8-16
CY100E474 1024 x 4 ECL Static RAM ................................................... 8-16
Military Information
Military Overview ....................................................................................... 9-1.
Military Product Selection Guide .......................................................................... 9-2
Military Ordering Information ............................................................................ 9-5
BridgeMOS
BridgeMOS Overview .................................................................................. 10-1
CY8C150 BridgeMOS 1024 x 4 Static RAM Separate I/O .................................. 10-1
CY8C245 BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
CY8C291 BridgeMOS Reprogrammable 2048 x 8 PROM .................................. 10-1
CY8C901 BridgeMOS 4-Bit Slice .................................................. : .... 10-1
CY8C909 BridgeMOS Microprogram Sequencer .......................................... 10-1
QuickPro
CY3000 Combined PROM, PLD, and EPROM Programmer .............................. 11-],
PLD ToolKit
CY3101 Programmable Logic Design Tool ............................................. 12-]
Quality and Reliability

Quality, Reliability and Process Flows ..................................................................... 13-1
Application Briefs
RAM Input and Output Characteristics .................................................................... 14-1
Power Characteristics of Cypress Products ................................................................. 14-l
Pin-Out Compatibility Considerations of SRAMs and PROMs ................................................ 14-1!
Packages
Thermal Management and Component Reliability ........................................................... 15-"
Package Diagrams ..................................................................................... 15-1
~ Numeric Device Index
~~~~UcrOR==================================================================
IOE301 Combinatorial ECL 16P8 PLD ................................................. 8-1
IOE302 Combinatorial ECL 16P4 PLD ................................................. 8-6
IOE422 256 x 4 ECL Static RAM ................................................. 8-11
IOE474 1024 x 4 ECL Static RAM ...................................... , .......... 8-16
100E301 Combinatorial ECL 16P8 PLD ................................................. 8-1
100E302 Combinatorial ECL 16P4 PLD ................................................. 8-6
100E422 256 x 4 ECL Static RAM ................................................. 8-11
100E474 1024 x 4 ECL Static RAM ................................................. 8-16
2147 4096 x 1 Static RAM ...................................................... 2-1
2148 1024 x 4 Static RAM ...................................................... 2-6
21L48 1024 x 4 Static RAM, Low Power ............................................ 2-6
2149 1024 x 4 Static RAM ...................................................... 2-6
21L49 1024 x 4 Static RAM, Low Power ............................................ 2-6
27LS03 16 x 4 Static RAM .................................................... 2-246
27S03 16 x 4 Static RAM .................................................... 2-246
27S07 16 x 4 Static RAM .................................................... 2-246
2901C CMOS 4-Bit Slice ............................................................ 5-1
2909A CMOS Microprogram Sequencer ............................................... 5-9
2910A CMOS Microprogram Controller .............................................. 5-14
2911A CMOS Microprogram Sequencer ............................................... 5-9
3000 Combined PROM, PLD, and EPROM Programmer .............................. 11-1
3101 Programmable Logic Design Tool ............................................. 12-1
3341 64 x 4 FIFO Serial Memory .............................................. 5-19
5116 2048 x 8 Static RAM ..................................................... 2-12
5116A 2048 x 8 Static RAM ..................................................... 2-19
5117 2048 x 8 Static RAM ..................................................... 2-12
5117A 2048 x 8 Static RAM ..................................................... 2-19
74S189 16 x 4 Static RAM .................................................... 2-246
7C122 256 x 4 Static RAM Separate I/O .......................................... 2-26
'C123 256 x 4 Static RAM Separate I/O .......................................... 2-33
'C128 2048 x 8 Static RAM ..................................................... 2-40
'C128A 2048 x 8 Static RAM ..................................................... 2-47
'C130 1024 x 8 Dual Port Static RAM ............................................ 2-54
C136 2048 x 8 Dual Port Static RAM ............................................ 2-65
C147 4096 x 1 Static RAM ..................................................... 2-76
C148 1024 x 4 Static RAM ..................................................... 2-83
C149 1024 x 4 Static RAM ..................................................... 2-83
C150 1024 x 4 Static RAM Separate I/O .......................................... 2-90
C157 16,384 x 16 Static Cache RAM ............................................... 2-98
C161-1O 16,384 x 4 Static RAM Separate I/O ......................................... 2-104
C161-20 16,384 x 4 Static RAM Separate I/O ......................................... 2-110
C162-1O 16,384 x 4 Static RAM Separate I/O ......................................... 2-104
C162-20 16,384 x 4 Static RAM Separate I/O ......................................... 2-110
C164-1O 16,384 x 4 Static RAM .................................................... 2-117
C164-20 16,384 x 4 Static RAM .................................................... 2-123
C166-1O 16,384 x 4 Static RAM .......... ; ......................................... 2-117
2166-20 16,384 x 4 Static RAM .................................................... 2-123
2167 16,384 x 1 Static RAM .................................................... 2-131
2167A 16,384 x 1 Static RAM .................................................... 2-138
2168 4096 x 4 Static RAM .................................................... 2-145
:168A 4096 x 4 Static RAM .................................................... 2-152
:169 4096 x 4 Static RAM .................................................... 2-145
:169A 4096x4StaticRAM .................................................... 2-152
:170 4096 x 4 Static RAM with Output Enable ................................... 2-159
:170A 4096 x 4 Static RAM with Output Enable ................................... 2-165
~ Numeric Device Index (Continued)
~~~UcrOR==================================================================
7CI71 4096 x 4 Static RAM Separate I/O ......................................... 2-171
7CI71A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
7CI72 4096 x 4 Static RAM Separate I/O ......................................... 2-171
7CI72A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
7C183 2 x 4096 x 16 Cache RAM ................................................ 2-185
7C184 2 x 4096 x 16 Cache RAM ................................................ 2-185
7C185-12 8192 x 8 Static RAM .................................................... 2-193
7C185-20 8192 x 8 Static RAM .................................................... 2-199
7C186-12 8192 x 8 Static RAM .................................................... 2-193
7C186-20 8192 x 8 Static RAM .................................................... 2-199
7C187 65,536 x 1 Static RAM .................................................... 2-207
7C189 16 x 4 Static RAM ............ " ...................................... 2-215
7C190 16 x 4 Static RAM .................................................... 2-215
7C191 65,536 x 4 Static RAM Separate I/O ......................................... 2-222
7C192 65,536 x 4 Static RAM Separate I/O ......................................... 2-222
7C194 65,536 x 4 Static RAM .................................................... 2-228
7C196 65,536 x 4 Static RAM with Output Enable ................................... 2-228
7C197 262,144 x 1 Static RAM .................................................... 2-234
7C198 32,768 x 8 Static RAM .................................................... 2-240
7C199 32,768 x 8 Static RAM .................................................... 2-24C
7C225 512 x 8 Registered PROM ................................................. 3-4
7C235 1024 x 8 Registered PROM ................................................ 3-1:
7C245 2048 x 8 Reprogrammable Registered PROM ................................ . 3-2t
7C245A 2048 x 8 Reprogrammable Registered PROM ................................. 3-3f
7C251 16,384 x 8 Reprogrammable Power Switched PROM ............................ 3-5(
7C254 16,384 x 8 Reprogrammable PROM .......................................... 3-5(
7C261 8192 x 8 Reprogrammable Power Switched PROM ............................ 3-6(
7C263 8192 x 8 Reprogrammable PROM .......................................... 3-6(
7C264 8192 x 8 Reprogrammable PROM .......................................... 3-6(
7C265 64K Registered PROM ................................................ 3-7'
7C266 8192 x 8 Reprogrammable EPROM ......................................... 3-8'
7C268 8192 x 8 Reprogrammable Registered Diagnostic PROM ....................... 3-8i
7C269 8192 x 8 Reprogrammable Registered Diagnostic PROM ....................... 3-81
7C271 32,768 x 8 Reprogrammable Power Switched PROM ............................ 3-9 1
7C274 32,768 x 8 Reprogrammable PROM .......................................... 3-91
7C277 32,768 x 8 Reprogrammable Registered PROM ................................ 3-10
7C281 1024 x 8 PROM ................. ; ...................................... 3-11
7C282 1024 x 8 PROM ........................................................ 3-11
7C285 65,536 x 8 Reprogrammable Fast Column Access PROM .......... " ............ 3-12
7C289 65,536 x 8 Reprogrammable Fast Column Access PROM ........................ 3-12
7C291 2048 x 8 Reprogrammable PROM ......................................... 3-12
7C291A 2048 x 8 Reprogrammable PROM ......................................... 3-13
7C292 2048 x 8 PROM ........................................................ 3-12
7C330 Synchronous State Machine Reprogrammable PLD ................... '............ 4-~
7C331 Asynchronous Registered EPLD .............................................. 4-~
7C332 Combinatorial Registered EPLD ............................................. 4-1 ~
7C340 EPLD Family Multiple Array Matrix High Density EPLDs .................................. .4-1 J II
7C361 Ultra High Speed State Machine ............................................. 4-1; ,I
7C401 Cascadeable 64 x 4 FIFO .................................................... 5-; l

7C402 Cascadeable 64 x 5 FIFO .................................................... 5-'11
7C403 Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-: II
7C404 Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-:,

7C408A Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-;
7C409A Cascadeable 64 x 9 FIFO .................................................... 5-. "
~ Numeric Device Index (Continued)
~~~~ucr~==================================================================
7C420 Cascadeable 512 x 9 FIFO ................................................... 5-48
7C421 Cascadeable 512 x 9 FIFO ................................................... 5-48
7C424 Cascadeable 1024 x 9 FIFO .................................................. 5-48
7C51O 16 x 16 Multiplier Accumulator ............................................... 5-60
7C516 16x 16 Multiplier ........................................................... 5-72
7C517 16x 16 Multiplier ........................................................... 5-72
7C601 32-Bit RISC Integer Unit ..................................................... 6-6
7C602 Floating Point Unit ......................................................... 6-12
7C604 Cache Controller and Memory Management Unit ................................ 6-13
7C605 Multiprocessor Cache Controller and Memory Management Unit ................... 6-17
7C608 Floating-Point Controller .................................................... 6-18
7C609 Floating-Point Processor ..................................................... 6-23
7C901 CMOS Four-Bit Slice ........................................................ 5-84
7C909 Microprogram Sequencer .................................................... 5-99
7C91O Microprogram Controller ........................................ " ......... 5-110
7C911 Microprogram Sequencer .................................................... 5-99
7C9101 CMOS 16-Bit Slice ......................................................... 5-121
7C9115 CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
8C150 BridgeMOS 1024 x 4 Static RAM Separate 110 .................................. 10-1
8C245 BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
8C291 BridgeMOS Reprogrammable 2048 x 8 PROM .................................. 10-1
8C901 BridgeMOS Four-Bit Slice ................................................... 10-1
8C909 BridgeMOS Microprogram Sequencer .......................................... 10-1
8C911 BridgeMOS Microprogram Sequencer .......................................... 10-1
93422 256 x 4 Static RAM Separate I/O ............................................ 2-252
93422A 256 x 4 Static RAM Separate I/O ............................................ 2-252
93L422 256 x 4 Static RAM Separate I/O ............................................ 2-252
93L422A 256 x 4 Static RAM Separate I/O ............................................ 2-252
M1420 128K x 8 Static RAM Module ............................................... 2-259
M1421 128K x 8 Static RAM Module '" ............................................ 2-265
\11422 128K x 8 Static RAM Module ............................................... 2-271
\11460 512K x 8 Static RAM Module ....................................... , ....... 2-277
\11610 16K x 16 Static RAM Module .................................... , .......... 2-287
1;11620 64K x 16 Static RAM Module ............................................... 2-299
1011623 64Kx16StaticRAMModuie ............................................... 2-312
1011626 64K x 16 Static RAM Module ............................................... 2-318
1011641 256K x 16 Static RAM Module .............................................. 2-324
.11804 lK x 32 Static RAM Module Separate I/O ..................................... 2-330
.11821 16K x 32 Static RAM Module ............................................... 2-331
r11822 16K x 32 Static RAM Module Separate I/O .................................... 2-337
r11830 64K x 32 Static RAM Module ............................................... 2-343
r11831 64K x 32 Static RAM Module ............................................... 2-349
,11832 64K x 32 Static RAM Module ............................................... 2-355
'AL C 20 Series Reprogrammable CMOS PAL Device ........................................... 4-7
16L8 ............................................................................................... 4-7
16R4 .... , .......................................................................................... 4-7
16R6 ............................................................................................... 4-7
16R8 ............................................................................................... 4-7
'AL C 22VlO Reprogrammable CMOS PAL Device ......................................... .4-61
'AL C 22VlOB Reprogrammable CMOS PAL Device ......................................... .4-61
'LD C 18G8 CMOS Generic 20 Pin Programmable Logic Device .............................. 4-26
'LD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
'LD C 20G lOB CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
LD C 20RAlO Reprogrammable Asynchronous CMOS Programmable Logic Device ................ 4-52
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO

PLDTOOLKIT III
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
-
PACKAGES
~ Section Contents
~~~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
General Product Information Page Number
Cypress Semiconductor Background ....................................................................... 1-1
Cypress Process Technology .............................................................................. 1-2
Product Selection Guide ................................................................................. 1-3
Ordering Information .................................................................................... 1-6
Product Line Cross Reference ............................................................................. 1-8
~~~================================================================~
Cypress Semiconductor Background
Cypress Semiconductor was founded in April 1983 with
the stated goal of serving the high performance semicon-
the PLD ToolKit software are updated via floppy disk,
thereby allowing quick support of all Cypress programma-
II
ductor market. This market is served by producing the ble products.
highest performance integrated circuits using state-of-the- Logic products include circuits such as 4-bit and 16-bit
art processes and circuit design. Cypress is a complete slices, 16 x 16 multipliers, and 16-bit microprogrammable
semiconductor manufacturer, performing its own process ALUs, as well as a family of FIFOs that range from 64 x 4
development, circuit design, wafer fabrication, assembly, to 2048 x 9. FIFOs provide the interface between digital
and test. The company went public in May 1986 and was information paths of widely varying speeds. This allows the
listed on the New York Stock Exchange in October 1988. information source to operate at its own intrinsic speed
The initial semiconductor process, a CMOS process em- while the results may be processed or distributed at a speed
ploying 1.2 micron geometries, was introduced in Mar~h commensurate with need.
1984. This process is used in the manufacturing of StatIc Until 1988, all Cypress products were TTL I/O comp~ti
RAMs and Logic circuits. In the third quarter of 1984, a ble. In 1989, Cypress will introduce ECL products havmg
1.2 micron CMOS EPROM process was introduced for the access times (propagation delays) of less than 3 ns in either
production of programmable products. At the time of in- of the popular I/O configurations, lOOK or lOK/lO~!f.
troduction, these processes were the most advanced pro- ECL RAMs include 256 x 4 and lK x 4 RAM famIlIes
duction processes in the industry. Following the 1.2 micron with balanced read/write cycles. The ECL PLDs are com-
processes, a 0.8 micron CMOS SRAM process was i~ple binatorial16P8 and 16P4 devices that can be programmed
mented in the first quarter of 1986, and a 0.8 mIcron on QuickPro and other commercially available program-
EPROM process in the third quarter of 1987. ming tools. Both the RAMs and PLDs are offered in low
In keeping with the strategy of serving the high perform- power versions, reducing operating power by 30 to 40 per-
ance markets with state-of-the-art integrated circuits, Cy- cent, while achieving 5 ns access time (RAM) and 6 ns tpD
press will introduce two new processes in 1989. Th~se ~ill (PLD).
be a bipolar submicron process, targeted for ECL CIrCUIts, The module family consists of both standard and custom
and a BiCMOS process to be used for most types of TTL modules incorporating circuits from the other six product
and ECL circuits. families. This capability provides a fast, low risk solution
The circuit design technology used by Cypress is also state- for designs requiring the ultimate in system performance
of-the-art. This design technology, along with advanced and density. Several module configurations are available
process technology, allows Cypress to introduce the fastest, depending on height and board real estate constraints.
highest performance circuits in the industry. Cypress' Modules include Single-In-Line, Dual-In-Line, Dual Sin-
products fall into seven families: high speed Static RAMs, gle-In-Line, Vertical Dual-In-Line, Quad-In-Line, and
PROMS, Erasable Programmable Logic Devices, Logic, (Staggered) Zig-Zag-In-Line packages.
RISC microprocessors, ECL, and module products. Mem- Cypress' CY7C600 family of RISC microprocessor prod-
bers of the Static RAM family include devices in densities ucts provides state-of-the-art high performance computing
of 64 bits to 256K bits, and performance from 7 ns to for applications ranging from UNIX-based business com-
35 ns. The various organizations, 16 x 4, 256 x 4 through puters and workstations to embedded controls. Based on
256K x 1, 32K x 8, and 64K x 4, provide optimal solutions the SPARCTM RISC architecture, the family provides a
for applications such as large mainframes, high-speed con- complete solution with Integer Unit (IU), Floating-Point
trollers, communications, and graphics display. Unit (FPU), Cache Control and Memory Management
Cypress' programmable products consist of high speed Unit (CMU) and Cache RAMs (CRAMs). The family is
CMOS PROMs and Erasable Programmable Logic Devic- functionally partitioned to provide a range of features, per-
!s (EPLDs), both employing an EPROM programming el- formance, and price to suit each type of application.
!ment. Like the high speed Static RAM family, these prod- Situated in California's Silicon Valley (San Jose) and
lCts are the natural choice to replace older devices because Round Rock (Austin), Texas, Cypress houses R&D, de-
:hey provide superior performance at one half of the po~er sign, wafer fabrication, assembly, and administration. The
:onsumption. PROM densities range from 4K to 256K bIts facilities are designed to the most demanding technical and
n byte wide organization. EPLD products range from 20- environmental specifications in the industry. At the Texas
)ins to 68-pins with performance as fast as 12 ns. To sup- facility, the entire wafer fabrication area is specified to be a
)ort new programmable products, Cypress introduced the Class 1 environment. This means that the ambient air has
~uickProTM programming system (CY3000) for PLDs and
less than 1 particle of greater than 0.2 microns in diameter
~ROMs, and the PLD ToolKit for PLDs. QuickPro is a per cubic foot of air. Other environmental considerations
Ilevelopment tool which includes a singl~~ IBM PC@ com- are carefully insured: temperature is controlled to a 0.2
, latible add-on board, and a software utIlIty program. The degree Fahrenheit tolerance; filtered air is completely ex-
)LD ToolKit is a software design tool that assembles and changed more than 10 times each minute throughout the
imulates logic functions, generates JEDEC files, and re- fab; and critical equipment is situated on isolated slabs to
jerse assembles to create source files. Both QuickPro and minimize vibration.
BM PC is a registered trademark of International Business Corporation.

luickPro is a trademark of Cypress Semiconductor Corporation.
PARCTM is a trademark of Sun MicroSystems, Inc.
1-1
~~ =====================================================================
Cypress Semiconductor Background (Continued)
Attention to assembly is equally as critical. Cypress assem- power consumption for any device. This improves reliabili-
bles and tests 55 packages in the United States at its San ty by allowing the device to operate at a lower die tempera-
Jose, California, plant. Assembly is completed in a clean ture. Now higher levels of integration are possible without
room until the silicon die is sealed in a package. Lead trading performance for power. For instance, devices may
frames are handled in carriers or cassettes through the en- now be delivered in plastic packages, without any impact
tire operation. Automated robots remove and replace parts on reliability.
into cassettes. Using sophisticated automated equipment, While addressing the performance issues of CMOS tech-
parts are assembled and tested in less than five days. The nology, Cypress has not ignored the quality and reliability
Cypress assembly line is the most flexible, automated line aspects of technology development. Rather, the traditional
in the United States. failure mechanisms of electrostatic discharge (ESD) and
The Cypress motto has always been "only the best-the latchup have been addressed and solved through process
best facilities, the best equipment, the best employees ... and design technology innovation.
all striving to make the best CMOS, BiCMOS and bipolar ESD-induced failure has been a generic problem for many
products." high performance MOS and bipolar products. Although in
its earliest years MOS technology experienced oxide reli-
Cypress Process Technology ability failures, this problem has largely been eliminated
In the last decade, there has been a tremendous need for through improved oxide growth techniques and a better
high performance semiconductor products manufactured understanding of the ESD problem. The effort to adequate-
with a balance of SPEED, RELIABILITY, and POWER. ly protect against ESD failures is perturbed by circuit de-
Cypress Semiconductor has overcome the classically held lays associated with ESD protection circuits. Focusing on
perceptions that CMOS is a moderate performance tech- these constraints, Cypress has developed ESD protection
nology. circuitry specific to 1.2 and 0.8 micron CMOS process
technology. Cypress products are designed to withstand
Cypress initially introduced a 1.2 micron "N" well tech- voltage and energy levels in excess of 2001 volts and
nology with double layer poly, and a single layer metal. 0.4 milli-joules, more than twice the energy level specified
The process employs lightly doped extensions of the heavi- by MIL STD 883C.
ly doped source and drain regions for both "N" and "P"
channel transistors for significant improvement in gate de- Latchup, a traditional problem with CMOS technologies,
lays. Further improvements in performance, through the has been eliminated through the use of substrate bias gen-
use of substrate bias techniques, have added the benefit of eration techniques, the elimination of the "P" MOS pull-
eliminating the input and output latchup characteristics as- ups in the output drivers, the use of guardring structures,
sociated with the older CMOS technologies. and care in the physical layout of the products.
Cypress pushed process development to new limits in the Cypress has also developed additional process innovations
area of PROMs (Programmable Read Only Memory) and and enhancements: the use of multi-layer metal intercon-
EPLDs (Eraseable Programmable Logic Devices). Both nections, advanced metal deposition techniques, silicides,
PROMs and EPLDs have existed since the early 1970s in a exclusive use of plasma for etching and ashing process
bipolar process which employed various fuse technologies steps, and 100% stepper technology with the world's most
and was the only viable high speed non-volatile process advanced equipment.
available. Cypress PROMs and EPLDs use EPROM tech- A wholly owned subsidiary of Cypress, Aspen Semicon
nology, which has also been in use in MOS (Metal Oxide ductor, has developed both advanced Bipolar and BiCMOS
Silicon) also since the early 1970s. EPROM technology has technologies augmenting the capabilities of the Cypres~
traditionally emphasized density advantages, while forsak- CMOS processes. Both the new Bipolar and BiCMOS tech
ing performance. Through improved technology, Cypress nologies are based on the Cypress 0.8 micron CMOS pro-
has produced the first high performance CMOS PROMs cess for enhanced manufacturability. Like CMOS, thes(
and EPLDs, replacing their bipolar counterparts. processes are scalable to take advantage of finer line lithog
To maintain our leadership position in CMOS Technology, raphy. Where speed is critical, Cypress BiCMOS allowl
Cypress has introduced a sub-micron technology into pro- increased transistor performance. It also allows reduce(
duction. This process reduces the drawn channel length power in the non-speed critical sections of the design t(
from the current 1.2 microns to 0.8 microns. This sub-mi- optimize the speed/power balance. The Bipolar an(
cron breakthrough makes Cypress' CMOS one of the most BiCMOS processes make possible memories and logic op
advanced production processes in the world. erating up to 400 MHz.' The drive to maintain proces1j
technology leadership has not stopped with the 0.8 micrOl
To further enhance the technology from the reliability di- devices. Cypress is developing fine line geometries beyon\
rection, improvements have been incorporated in the pro- this to insure technology leadership in the next decade. I
cess and design, minimizing electrostatic discharge and in-
put signal clipping problems. Cypress technologies have been carefully designed, creatin;
products that are "only the best" in high speed, excelleri
Finally, although not a requirement in the high perform- reliability, and low power.
ance arena, CMOS technology substantially reduces the
1-2
Sn
SRAMs 64
64
64
64
64
Organization
16 x 4-Inverting
16 x 4-Non-Inverting
16 x 4-Inverting
16 x 4-Inverting
16 x 4-Non-Inverting
Product Selection Guide
~ ~~NDUcrOR=======================================================================
Size Pins
16
16
16
16
16
Part Number
CY7CI89
CY7CI90
CY74S189
CY27S03A
CY27S07A
Speed (ns)
tAA = 15,25
tAA = 15, 25
tAA =35
tAA =25,35
tAA =25,35
IcdIso/IcCDR
(mA @ns)
55 @ 25
55 @ 25
90@ 35
90@25
90@25
Packages
D,L,P
D,L,P
D,P
D,L,P
D,L,P
..
64 16 x 4-Inv. Low Power 16 CY27LS03M tAA =65 38 @ 65 D,L
IK 256x4 22 CY7CI22 tAA = 15,25,35 60@25 D,L,P,S
IK 256x4 24S CY7CI23 tAA =7,9,12 120@7 D,L,P, V
IK 256x4 22 CY9122/91L22 tAA = 25, 35, 45 120@ 25 D,P
IK 256x4 22 CY93422A193L422A tAA = 35, 45,60 80@45 D,P,L
4K 4096 x I-CS Power Down 18 CY7CI47 tAA = 25, 35, 45 80/10 @ 35 D,L,P,S
4K 4096 x I-CS Power Down 18 CY2147/21L47 tAA = 35, 45, 55 125/25 @35 D,P
4K 1024 x 4-CS Power Down 18 CY7CI48 tAA = 25,35,45 80/10 @ 35 D,L,P,S
4K 1024 x 4-CS Power Down 18 CY2 14812 IL48 tAA = 35, 45, 55 120/20@35 D,P,S
4K 1024 x 4 18 CY7CI49 tAA = 25, 35, 45 80@35 D,L,P,S
4K 1024 x 4 18 CY2149/21L49 tAA = 35, 45, 55 120 @ 35 D,P
4K 1024 x 4-Separate I/O, Reset 24S CY7CI50 tAA = 12, 15,25,35 90@ 12 D,L,P,S
8K 1024 x 8-Dual Port 48 CY7C130 tAA = 25, 35, 45, 55 170 @ 25 D,L,P
8K 1024 x 8-Dual Port (Slave) 48 CY7CI40 tAA = 25, 35,45, 55 170 @ 25 D,L,P
8K 1024 x 8-Dual Port 52 CY7C13 I tAA = 25, 35, 45, 55 170 @25 L,J
8K 1024 x 8-Dual Port 52 CY7CI41 tAA = 25, 35, 45, 55 170 @ 25 L,J
16K 2048 x 8-CS Power Down 24S CY7CI28 tAA = 35, 45, 55 90/20 @ 55 D,L,P,V
16K 2048 x 8-CS Power Down 24 CY7CI28A 90/20 @ 55
tAA = 20, 25, 35, 45, 55 D,L,P, V
16K 2048 x 8-CS Power Down 24 CY6116 tAA = 35, 45, 55 120/20@ 45 D,L
16K 2048 x 8-CS Power Down 24 CY6116A 80/20 @ 55
tAA = 20, 25, 35, 45, 55 D,L
16K 2048 x 8-CS Power Down 32S CY6117 tAA = 35, 45, 55 130/20@ 55 L
16K 2048 x 8-CS Power Down 32S CY6117A lOO/20@ 55
tAA = 20, 25, 35, 45, 55 L
16K 16384 x I-CS Power Down 20 CY7CI67 tAA = 25, 35, 45 50/15 @25 D,L,P,V
16K 16384 x l-CS Power Down 20 CY7C167A tAA = 20, 25, 35, 45 50/15 @45 D,L,P,V
16K 4096 x 4-CS Power Down 20 CY7C168 tAA = 25, 35, 45 90/15 @ 25 D,L,P,V
16K 4096 x 4-CS Power Down 20 CY7C168A tAA = 20, 25, 35, 45 70/15 @45 D,L,P,V
16K 4096 x4 20 CY7C169 tAA = 25, 35, 40 90@25 D,L,P, V
16K 4096x4 20 CY7C169A tAA = 20, 25, 35, 40 70@45 D,L,P,V
16K 4096 x 4-0utput Enable 22S CY7C170 tAA = 25, 35, 45 90@45 D,L,P,V
16K 4096 x 4-Output Enable 20 CY7C170A tAA = 20, 25, 35, 45 90@45 D,L,P, V
16K 4096 x 4-Separate 1/0 24S CY7C171 tAA = 20,25,35,45 90/15 @ 25 D,L,P,V
16K 4096 x 4-Separate 1/0 24S CY7C171A tAA = 20, 25, 35, 45 90@45 D,L,P,V
16K 4096 x 4-Separate I/O 24S CY7C172 tAA = 20, 25, 35, 45 90/15 @25 D,L,P, V
16K 4096 x 4-Separate 1/0 24S CY7C172A tAA = 20,25,35,45 90@45 D,L,P,V
16K 2048 x 8-Dual Port 48 CY7C132 tAA = 25, 35, 45, 55 170@ 25 D,L,P
16K 2048 x 8-Dual Port (Slave) 48 CY7C142 tAA = 25, 35,45, 55 170@25 D,L,P
64K 2048 x 8 52 CY7CI36 tAA = 25,35,45,55 170@ 25 L,J
64K 2048 x 8 52 CY7C146 tAA = 25, 35, 45, 55 170@ 25 L,J
64K 8192 x 8 28 CY7C185-12 tAA=12,15 115/50 @ 15 D,L,P,V
64K 8192x 8 28 CY7C186-12 tAA = 12, 15 115150 @ 15 D,L,P, V
64K 8192 x 8-CS Power Down 28S CY7C185-20 tAA = 20, 25, 35, 45 100/20 @ 25 D,L,P,V
64K 8192 x 8-CS Power Down 28 CY7C186-20 tAA = 20, 25, 35, 45 100/20 @25 D,P
64K 16384 x 4 22 CY7C164-1O tAA = 10, 12, 15 115150 @ 15 D,L,P,V
64K 16384 x 4-CS Power Down 22S CY7C164-20 tAA = 20, 25, 35, 45 70/20@ 25 D,L,P, V
64K 16384 x 4 24 CY7C166-1O tAA = 10, 12, 15 115150 @ 15 D,L,P,V
64K 16384 x 4-0utput Enable 24S CY7C166-20 tAA = 20, 25, 35,45 70/20@ 25 D,L,P,V
64K 16384 x 4 28 CY7C161-10 tAA = 10,12,15 115150@ 15 D,L,P, V
64K 16384 x 4 28 CY7C162-1O tAA = 10, 12, 15 115150 @ 15 D,L,P,V
64K 16384 x 4-Separate I/O 28S CY7C161-20 tAA = 20, 25, 35,45 70/20 @ 25 D,L,P, V
64K 16384 x 4-Separate I/O 28S CY7C162-20 tAA = 20, 25, 35, 45 70/20@ 25 D,L,P,V
64K 65536 x l-CS Power Down 22S CY7C187 tAA = 20, 25, 35, 45 70/20 @ 25 D,L,P,V
128K 8192 x 16---Addresses Latched except A-12 52 CY7C183 tAA = 25, 35, 45 220@ 25 D,J,L
128K 8192 x 16---Addresses Latched 52 CY7C184 tAA = 25, 35, 45 220@ 25 D,J,L
256K 16384 x 16 52 CY7C157 tAA =20,24 TBD J,L
256K 32768 x 8-CS Power Down 28 CY7C198 tAA = 35, 45, 55 110/20@ 35 D,P
256K 32768 x 8-CS Power Down 28S CY7C199 tAA = 35, 45, 55 110/20@ 35 D,L,P, V
256K 65536 x 4-CS Power Down 24S CY7C194 tAA = 25, 35, 45 80/20 @25 D,L,P,V
256K 65536 x 4-CS Power Down With OE 28S CY7C196 tAA = 25, 35,45 80/20 @ 25 D,L,P,V
256K 65536 x 4-Separate 1/0 28S CY7C191 tAA = 25, 35, 45 80/20 @ 25 D,L,P, V
256K 65536 x 4-Separate 1/0 28S CY7CI92 tAA = 25, 35, 45 80/20 @25 D,L,P,V
256K 262144 x 1-CS Power Down 24S CY7C197 tAA = 25, 35, 45 70/20 @ 25 D,L,P,V
otes: Package Code:
Ie above specifications are for the commercial temperature range ofO"C to B = PLASTIC PIN GRID R = WINDOWED PGA
1C. ARRAY S=SOIC
iIitary temperature range (- 55C to + 125C) product processed to MIL- D = CERDIP T = WINDOWED CERPAK
~D-883 Revision C is also available. Speed and power selections may vary F = FLATPAK V = SOJ
)m those above. G = PIN GRID ARRAY W = WINDOWED CERDIP
)mmercial grade product is available in plastic, CERDIP, or LCe. Military H = WINDOWED X = DICE
ade product is available in CERDIP or LCC. PLCC, SOJ, and SOIC HERMETIC LCC HD = HERMETIC DIP
ckages are available on some products. J = PLCC HV = HERMETIC VERTICAL
I power supplies are Vcc = 5V 10%. K = CERPAK DIP
S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for L = LCC PF = PLASTIC FLAT SIP
-pin 300 mil. P = PLASTIC PS = PLASTIC SIP
K and T packages are special order only. Q = WINDOWED LCC PZ = PLASTIC ZIP
1-3
~ Product Selection Guide (Continued)
~~~NDUaoR =====================================================================
Size Organization Pins Part Nurnber Speed (ns) IccIIsslICCDR Packages
(rnA@ns)
PROMs 4K 512 x 8-Registered 24S CY7C225 tSAICO = 25/12, 30/15 90 D,L,P
8K 1024 x 8-Registered 24S CY7C235 tSAICO = 25/12, 30/15 90 D,L,P
8K 1024 x 8 24S CY7C281 tAA =30,45 90 D,L,P
8K 1024 x 8 24 CY7C282 tAA =30,45 90 D,L,P
16K 2048 x 8-Registered 24S CY7C245/L tSAICO = 25/12,35/15 100,60 D, L, P, Q, W, S
16K 2048 x 8-Registered 24S CY7C245A/L tSAlCO= 18/12 6O@ 35 D, L, P, Q, W, S
16K 2048 x 8 24S CY7C291/L tAA =35,50 90,60 D, L, P, Q, W, S
16K 2048 x 8 24S CY7C291A/L tAA = 25, 30, 35, 50 60@35 D,L,P,Q, W,S
16K 2048 x 8 24 CY7C2921L tAA=35,50 90,60 D,P
16K 2048 x 8-CS Power Down 24S CY7C293A/L tAA = 25, 30, 35, 50 60/15 @ 35 D, L, P, Q, W, S
64K 8192 x 8-CS Power Down 24S CY7C261 tAA = 35, 40, 45, 55 100/30 D,L,P,Q, W,S
64K 8192 x 8 24S CY7C263 tAA = 35, 40, 45, 55 100 D,L,P,Q, W,S
64K 8192 x 8 24 CY7C264 tAA = 35, 40, 45, 55 100 D,P
64K 8192 x 8-Registered 28S CY7C265 tSAICO = 40/20 80 D,L,P,Q, W,S
64K 8192 x 8 28 CY7C266 tAA=55 80115 D,L,P,Q,W
64K 8192 x 8-Registered, Diagnostic 28S CY7C269 tSAICO = 40/20, 50/25 100 D,L,P,Q, W,S
64K 8192 x 8-Registered, Diagnostic 32 CY7C268 tSAICO = 40/20, 50/25 100 D,L,Q,W
128K 16384 x 8-CS Power Down 28S CY7C251 tAA = 45, 55, 65 100/30 D, L, P, Q, W, S
128K 16384 x 8 28 CY7C254 tAA = 45, 55, 65 100 D,P
256K 32768 x 8-CS Power Down 28S CY7C271 tAA = 45, 55, 65 100/30 D, L,P,Q, W,S
256K 32768 x 8 28 CY7C274 tAA=45 120/30 D,L,P,Q,W
256K 32768 x 8-Registered 28S CY7C277 tSAICO = 40/20 120/30 D,L,P,Q,W
256K 32768 x 8-Address Latch 28S CY7C279 tAA=45 120 D,L,P,Q,W
512K 65536 x 8-FCA 28S CY7C285 tAAICAA = 65/30 180 D,L,P,Q,W
512K 65536 x 8-CE Power Down 28 CY7C286 tAA =65 120/40 D,L,P,Q,W
512K 65536 x 8-Registered 28S CY7C287 tSAICO = 55/20 180 D,L,P,Q, W
512K 65536 x 8-FCA 32S CY7C289 tAAICA = 75/30 180 D,L,P,Q,W
PLDs PALC20 16L8 20 PALCI6L8/L tpD=20 70,45 D,L,P,Q, V, W
PALC20 16R8 20 PALCI6R8/L ts/co= 15/12 70,45 D, L, P,Q, V, W
PALC20 16R6 20 PALCI6R6/L tPD/S/CO = 20/20/15 70,45 D,L,P,Q, V, W
PALC20 16R4 20 PALCI6R4/L tPD/S/CO = 20/20/15 70,45 D,L,P,Q, V, W
PLDC20 18G8-Generic 20 PLDC18G8 tPD/S/CO = 12112110 90 D,L,P,Q, V, W
PLDC24 22VIO-Macro Cell 24S PALC22VI0/L tPD/S/CO = 25/15/15 90,55 D, L, P,Q, W,J
PLDC24 22VIO-Macro Cell 24S PALC22VI0B tpD/S/CO= 15/10/10 90 D,L, P,Q, W,J
PLDC24 20GlO-Generic 24S PLDC20GI0 tpD/S/CO= 25/15/15 55 D,L,P,Q, W,J
PLDC24 20G lO-Generic 24S PLDC20G1OB tpD/S/CO= 15/12110 70 D, L, P, Q, W, J
PLDC24 20RA 100Asynchronous 24S PLDC20RAI0 tPD/S/CO = 20/10/20 80 D, L, P, Q, W, J
PLDC28 7C330-State Machine 28S CY7C330 fMAX, tIS, tco = 66 MHz/3 ns/12 ns 130 D, L, P,Q, W,J
PLDC28 7C331-Asynchronous 28S CY7C331 tpD/S/CO= 20/12/20 120 D, L, P, Q, W, J
PLDC28 7C332-Combinatorial 28S CY7C332 tpD= 20 ns 120 D, L, P, Q, W, J
PLDC28 7C361-State Machine 28S CY7C361 fMAX/tS/tco = 125 MHz/2 ns/12 ns 140 D, L, P, Q, W, J
MAXC28 7C344-32-Macro Cell 28S CY7C344 tPD/S/CO = TBD Icc=TBD D, L, P, Q, W, J
MAXC40 7C343-64-Macro Cell 40/44 CY7C343 tPD/S/co=TBD Icc=TBD D,L,P, W,J, H
MAXC40 7C345-128-Macro Cell 40/44 CY7C345 tpD/S/CO = TBD Icc=TBD D, L,P, W,J,H
MAXC68 7C342-128-Macro Cell 68 CY7C342 tPD/S/CO = TBD Icc = TBD L,J,G,H,R
FlFOs 256 64 x 4-Cascadeable 16 CY3341 1.2,2MHz 45 D,P
256 64 x 4-Cascadeable 16 CY7C401 5, 10, 15,25 MHz 75 D,L,P,V
256 64 x 4-Cascadeable/OE 16 CY7C403 10, 15,25 MHz 75 D,L,P,V
320 64 x 5-Cascadeable 18 CY7C402 5,10,15,25 MHz 75 D,L,P,V
320 64 x 5-Cascadeable/OE 18 CY7C404 10, 15, 25 MHz 75 D,L,P,V
512 64 x 8-Cascadeable/OE 28S CY7C408A 15,25,35 MHz 120 D,L,P,V
576 64 x 9-Cascadeable 28S CY7C409A 15,25, 35 MHz 120 D,L,P,V
4608 512 x 9-Cascadeable 28 CY7C420 30,40,65 ns 100 D,P
4608 512 x 9-Cascadeable 28S CY7C421 30,40,65 ns 100 D,J,L,P, V
9216 1024 x 9-Cascadeable 28 CY7C424 30,40,65ns 100 D,P
9216 1024 x 9-Cascadeable 28S CY7C425 30,40,65 ns 100 D,J,L,P
18432 2048 x 9-Cascadeable 28 CY7C428 30,40,65 ns 100 D,P
18432 2048 x 9-Cascadeable 28S CY7C429 30,40,65 ns 100 D,J, L,P, V
Notes: Package Code:
The above specifications are for the commercial temperature range ofOC to B = PLASTIC PIN GRID R = WINDOWED PGA
70C. ARRAY S = SOIC
Military temperature range ( - 55C to + 125C) product processed to MIL- D = CERDIP T = WINDOWED CERPAK
STD-883 Revision C is also available. Speed and power selections may vary F = FLATPAK V =
SOJ
from those above. G = PIN GRID ARRAY W =
WINDOWED CERDIP
Commercial grade product is available in plastic, CERDIP, or LCC. Military H = WINDOWED X =
DICE
grade product is available in CERDIP or LCC. PLCC, SOJ, and SOIC HERMETIC LCC HD =
HERMETIC DIP
packages are available on some products. J = PLCC HV =
HERMETIC VERTICAL
All power supplies are Vcc = 5V 10%. K = CERPAK DIP
22S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for L = LCC PF = PLASTIC FLAT SIP
28-pin 300 mil. P = PLASTIC PS = PLASTIC SIP
F, K and T packages are special order only. Q = WINDOWED LCC PZ = PLASTIC ZIP
1-4
~ Product Selection Guide (Continued)
~~~NDUcrOR =======================================================================
LOGIC
Size Organization
2901--4 Bit Slice

2901--4 Bit Slice
4 x 2901-16 Bit Slice
29116---16 Bit Controller
29116---16 Bit Controller
29117 -16 Bit Controller
2909-Sequencer
40
40
64
52
52
68
28
Pins Part Number
CY7C901
CY2901
CY7C9101
CY7C9115
CY7C9116
CY7C9117
CY7C909
Speed (ns)
tCLK=23,31
C
tCLK=30, 40
tCLK = 35, 45, 53, 79, 100
tCLK = 35,45,53,79, 100
tCLK = 35,45,53,79, 100
tCLK=30, 40
IcclIsB/IcCDR
70
140
60
145
145
145
55
(mA@ns)
D,P
]
Packages
D,L,P,J
D,L,P,]
D,L,G,]
L,G, J
D,L,P,J

2911-Sequencer 20 CY7C911 tCLK=30, 40 55 D,L,P,J
2909-Sequencer 28 CY2909 A 70 D,P
2911-Sequencer 20 CY2911 A 70 D,P
2910-Controller (17 Word Stack) 40 CY7C91O tCLK = 40, 50,93 100 D,L,P,]
2910-Controller (9 Word Stack) 40 CY2910 A 170 D,L,P,J
16 x 16---Multiplier 64 CY7C516 tMC = 38, 45, 55, 75 lOO@ 10 MHz D,L,P,G,J
16 x 16---Multiplier 64 CY7C517 tMC = 38, 45, 55, 75 loo@ 10 MHz D, L, P, G,J
16 x 16---Multiplier/ Accumulator 64 CY7C51O tMC = 45, 55, 65, 75 loo@ 10 MHz D,L,P,G,J
RISC IV SPARC 32 Bit Integer Unit 208 CY7C601 tCYC = 40, 33, 25 MHz 650 G,B
FPC Floating-Point Controller 281 CY7C608 tCYC = 33, 25 MHz 600 G
FPP Floating-Point Processor 208 CY7C609 tcyc=33, 25 MHz 600 G
FPU Floating-Point Unit 299/144 CY7C602 tCYC = 40, 33, 25 MHz 650 G,K
(Controller & Processor)
CMU Cache Controlled Memory 207/196 CY7C604 tCYC = 40, 33, 25 MHz 650 G,K
Management Unit
CMU-MP Cache Controller and Multiprocessing 207/196 CY7C605 tCYC = 40, 33, 25 MHz 650 G,K
Memory Management Unit
Modules 32K lKx32-SRAM 56 CYM1804 tAA = 15, 17 720 @ 15 PZ
256K 16K x 16---SRAM (JEDEC) 40 CYM1610 tAA = 25, 35, 45, 50 330@ 25 HD
256K 16K x 16---SRAM 36 CYMl611 tAA = 25, 30, 35, 45 330 @ 25 HV
512K 16K x 32-SRAM 64 CYM1821 tAA = 25, 35, 45 720 @ 25 PZ
512K 16K x 32-SRAM Separate I/O 88 CYM1822 tAA = 25, 30, 35, 45 720 @ 25 HV
1M 128K x 8-SRAM (JEDEC) 32 CYM1420 tAA =45,55 210 @ 45 HD
1M 128K x 8-SRAM (JEDEC) 32 CYM1421 tAA =70,85 120@ 70 HD
1M 128K x 8-SRAM 30 CYM1422 tAA = 35, 45, 55 220 @ 35 PF,PS
1M 64K x 16---SRAM (JEDEC) 40 CYM1620 tAA =45,55 34O@ 45 HD
1M 64K x 16---SRAM 40 CYM1621 tAA = 25,30,35,45 1250@ 25 HD
1M 64K x 16---SRAM 40 CYM1622 tAA = 35, 45, 55 4oo@ 35 HV
1M 64K x 16---SRAM (JEDEC) 40 CYM1623 tAA = 70, 85, 100 24O@ 70 HD
1M 64K x 16---SRAM 40 CYM1626 tAA = 30, 35, 45 34O@ 30 PF,PS
2M 64K x 32-SRAM 60 CYM1830 tAA = 35, 45, 55 550@ 45 HD
2M 64K x 32-SRAM 64 CYM1831 tAA = 30, 35, 45 670@ 30 PZ
2M 64K x 32-SRAM 64 CYM1832 tAA = 35, 45, 55 980@ 35 PZ
4M 512K x 8-SRAM 36 CYMI460 tAA = 45, 55, 70 450@ 45 PF,PS
4M 512K x 8-SRAM 36 CYM1461 tAA = 70, 85, 100 120@ 70 PF,PS
4M 256K x 16---SRAM 48 CYM1641 tAA = 35, 45, 55 1760 @ 35 HD
ECL lK 256K x 4--lOK/lO KH 24 CYlOE422 tAA =3,5 205 D,L
SRAMs lK 256K x 4--1OK/1O KH 24 CYlOE422L tAA=5,7 150 D,L
lK 256K x 4--1ooK 24 CYl00E422 tAA =3,5 200 D,L
lK 256K x 4--1OOK 24 CYlooE422L tAA=5,7 150 D,L
4K 1024K x 4--lOK/I0 KH 24 CYlOE474 tAA =3,5 275 D,L
4K 1024K x 4--lOK/lO KH 24 CYlOE474L tAA =5,7 190 D,L
4K 1024K x 4--1ooK 24 CYlooE474 tAA =3,5 275 D,L
4K 1024K x 4--1ooK 24 CYl00E474L tAA=5,7 190 D,L
ECL 32 x64 16P8-lOKH 24 CYlOE301 tAA=3,4 240 D,L
PLDs 32x 64 16P8-lOKH 24 CYI0E301L tAA=6 150 D,P,L,J
32 x64 16P8-1ooK 24 CYlooE301 tAA =3,4 240 D,L
32x 64 16P8-1OOK 24 CYlooE301L tAA=6 150 D,P,L,J
32 x 32 16P4--lOKH 24 CYlOE302 tAA =2,5,4 220 D,L
32x 32 16P4--lOKH 24 CYlOE302L tAA=6 150 D,P,L,J
32 x 32 16P4--1ooK 24 CYl00E302 tAA =2,5,4 220 D,L
32 x 32 16P4--1ooK 24 CYlOOE302L tAA=6 150 D,P,L,J
lotes: Package Code:
'he above specifications are for the commercial temperature range ofOC to B = PLASTIC PIN GRID R = WINDOWED PGA
Doe. ARRAY S=SOIC
liIitary temperature range ( - 55C to + 125C) product processed to MIL- D = CERDIP T = WINDOWED CERPAK
TD-883 Revision C is also available. Speed and power selections may vary F = FLATPAK V = SOJ
'om those above. G = PIN GRID ARRAY W = WINDOWED CERDIP
'ommercial grade product is available in plastic, CERDIP, or LCe. Military H = WINDOWED X = DICE
rade product is available in CERDIP or LCe. PLCC, SOJ, and SOIC HERMETIC LCC HD = HERMETIC DIP
~ckages are available on some products. J = PLCC HV = HERMETIC VERTICAL
II power supplies are VCC = 5V 10%. K = CERPAK DIP
~S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for
L= LCC PF = PLASTIC FLAT SIP
~-pin 300 mil. P = PLASTIC PS = PLASTIC SIP
, K and T packages are special order only. Q = WINDOWED LCC PZ = PLASTIC ZIP
1-5
Ordering Information
Specific ordering codes are indicated in the detailed data sheets. In general, the codes for all products
(except modules) follow the format below:
PAL Be PLD
PREFIX DEVICE SUFFIX FAMILY
'PAL C' 16R8 -25 P C PAL 20
PAL C 16R8 L-35 P C LOW POWER PAL 20
PAL C 22V10 -25 W C PAL 24 VARIABLE PRODUCT TERMS
PLD C 20G10 -25 W C GENERIC PLD 24
CY 7C330 -33 P C PLD SYNCHRONOUS STATE MACHINE
CY 10E302 -2.5 D C 10K ECL PLD
CY 100E302 -2.5 D C 100K ECL PLD
RAM, PROM, FIFO, JJ.P ,ECL

PREFIX DEVICE SUFFIX FAMILY
r-cY" 7C128 1-45 D MB ' 1 SRAM
CY 7C245 L-35 P C PROM
CY 7C404 -25 DMB FIFO
CY 7C901 -23 P C JJ.P
CY 10E415 -3 DC 10K ECL SRAM
CY 100E415 -3 F C 100K ECL SRAM
IL PROC~SING
B = HI REL MIL STD 883 C
FOR MILITARY PRODUCT
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCT
TEMPERATURE RANGE
C = COMMERCIAL (OOC TO 70 0 C)
M=MILITARY(-55 0 C TO +1250 C)
PACKAGE
D = CERDIP
F = FLATPAK
G = PIN GRID ARRAY (PGA)
J = PLCC
K = CERPAK (GLASS SEALED FLAT PACKAGE)
L = LEADLESS CHIP CARRIER
P = PLASTIC
Q = WINDOWED LEADLESS CHIP CARRIER
S = SOIC (GULL WING)
T = WINDOWED CERPAK
V = SOIC (J LEAD)
W= WINDOWED CERDIP
X = DICE (WAFFLE PACK)
~--- SPEED (ns or MHz)

L..-_ _ _ _ L = LOW POWER OPTION
A, B, C = REVISION LEVEL
0018-1
i.e. CY7C128-35PC, PALC16R8L-25PC

Cypress FSCM # 65786
1-6
Ordering Information (Continued) II
The codes for module products follow the format below:
PREFIX DEVICE SUFFIX
r---1
CYM 1001 H 0-120 M B
IL PROCESSING
B = MILITARY STANDARD 883
= STANDARD
TEMPERATURE RANGE
C = OOC TO 70C
I = -40C TO 85C
M = -55C TO 125C
" ' - - - SPEED
- - - - CONFIGURATION
0= DUAL-IN-LiNE
G = PIN GRID ARRAY
Q = QUAD-IN-LiNE
S = SINGLE-IN-LiNE
V = VERTICAL DIP
Z = ZIGZAG-IN-LiNE
' - - - - - - TYPE
H = HERMETIC
P = PLASTIC
0018-2
Cypress FSCM # 65786
1-7
~ Product Line Cross Reference
~~~NDUcroR =====================================================================
CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS
2l4735C 7Cl4735C 29llAM 7C911-40M 7Cl50-25C 7Cl50l5C 7C25l65M 7C25155M
2l47-45C 2l4735C 334l2C 7C40l5C+ 7Cl50-35C 7Cl5025C 7C25365M 7C25355M
2147-45C 7Cl4745C 334l2M 7C40llOM 7Cl50-35M 7Cl5025M 7C254-45C 7C254-45C
2l47-45M + 7Cl47-45M + 3341C 33412C 7C16735C 7C16725C 7C25455C 7C254-45C
2l4755C 2l4745C 334lM 334l2M 7Cl6745M 7Cl6735M+ 7C25465C 7C254-55C
2l4755M 2l4745M 54Sl89M 27S03M 7Cl6835C 7Cl6825C 7C254-65M 7C25455M

2l4835C 2lL4835C 611635C 611635C 7Cl6845M 7Cl6835M+ 7C26l35C 7C26135C
214835C 7C14835C 611645C 611635C 7C16935C 7C16925C 7C26145C 7C26l35C
214835M 7C14835M 611645M 6116-45M 7C16940M 7C16935M+ 7C26145M 7C26l-45M
2148-45C 214835C 611655C 611645C 7C170-35C 7C17025C 7C26155C 7C261-45C
214845C 21L4845C 611655M 611645M 7C170-45C 7C17035C 7C26155M 7C261-45M
214845M 214835M 74S189C 27S03C 7C17045M 7C170-35M 7C26335C 7C26335C

2148-45M+ 7C148-45M + 7Cl2225C 7C12215C+ 7C17135C 7C17l25C 7C263-45C 7C26335C
214855C 214845C 7Cl2235C 7C12225C 7C17l35M 7C17l35M 7C263-45M 7C26345M
214855C 21L4855C 7C122-35M 7C12225M 7C171-45M 7C17l35M + 7C26355C 7C263-45C
214855M 214845M 7C12312C 7C1237C 7C17235C 7C17225C 7C26355M 7C263-45M
214935C 21L4935C 7C12835C 7C12825C 7C17245M 7C17235M+ 7C26435C 7C26435C
214935C 7C14935C 7C12835M 7C12835M 7C186L45M 7C18645M 7C264-45C 7C26435C

214935M 7C14935M 7C128-45C 7C12835C 7C18925C 7C189l5C+ 7C264-45M 7C264-45M
214945C 21L4945C 7C128-45M 7C12835M + 7C190-25C 7C190-15C+ 7C264-55C 7C264-45C
214945M 214935M 7C12855C 7C12845C+ 7C191-45M 7C19l35M 7C264-55M 7C26445M
214945M 7C14945M 7C12855M 7Cl28-45M + 7C192-45M 7Cl9235M 7C26850C 7C2684OC+
214955C 2149-45C 7C\30-45C 7C\3035C 7C194-35C 7C194-25C 7C26860C 7C2685OC
2l4955C 21L4955C 7C\3Q.45M 7C13045M 7C19445C 7C194-35C+ 7C26860M 7C26850M+

2l4955M 214945M 7C\3055C 7C13045C 7C19445M 7C19435M 7C26950C 7C269-4OC+
21L4835C 7Cl4835C 7C13055M 7C13045M 7C19635C 7C19625C 7C26960C 7C2695OC
2lL48-45C 21L4835C 7C\3145C 7C13135C 7C19635M 7C19635M 7C26960M 7C26950M+
2lL4845C 7C14845C 7C\3145M 7C13145M 7C19645C 7C19635C+ 7C281-45C 7C2813OC
2lL4855C 21L4845C 7C\3155C 7C13145C 7C19735C 7C19725C 7C28245C 7C2823OC+
21L4935C 7C14925C 7C\3155M 7C13145M 7Cl9745C 7C19735C+ 7C28245M 7C28245M

21L4945C 21L4935C 7C13235C 7C13235C 7C19745M 7C19735M 7C29135C 7C29125C+
21L4945C 7Cl4945C 7C13245C 7C13235C 7C19845C 7C19835C 7C29135M 7C29135M
21L4955C 21L4945C 7C13255C 7C13245C 7C19855C 7C19845C+ 7C29150C 7C29135C
27S03AC 7C18925C 7C13255M 7C13245M 7C19855M 7C19845M 7C29150M 7C29135M
27S03AM 7C18925M 7C13635C 7C13635C 7C199-45C 7C19935C 7C291A35C 7C291AL35C
27S03C 27S03AC 7C13645C 7C13635C 7C19955C 7C19945C+ 7C291A35M 7C291 A30M

27S03C 74S189C 7C13655C 7C13645C 7C19955M 7C19945M 7C291A50C 7C291AL5OC
27S03M 27S03AM 7C13655M 7C13645M 7C22530C 7C22525C 7C29lA50M 7C291A35M
27S03M 54S189M 7Cl4035C 7Cl4025C 7C22530M 7C22525M 7C291AL35C 7C291A25C +
27S07AC 7C19025C 7Cl40-45C 7Cl4035C 7C22540C 7C2253OC 7C291AL5OC 7C291AL35C
27S07AM 7C19025M 7Cl4055C 7Cl4045C 7C225-40M 7C22535M 7C291L35C 7C29135C+
27S07C 27S07AC 7C14135C 7C14125C 7C23540C 7C2353OC 7C291L50C 7C291L-35C

27S07M 27S07AM 7C14145C 7C14135C 7C24535C 7C24525C 7C29235C 7C29225C+
27S07M 7C190-25M 7C14155C 7C14145C 7C24545C 7C24535C 7C29250C 7C29235C
2901CC 7C90131C 7C14735C 7C14725C+ 7C24545M 7C24535M 7C292L35C 7C29235C+
2901CM 7C90132M 7C14735M+ 7C14735M+ 7C245A25C 7C245A18C 7C292L5OC 7C292L-35C
2909AC 7C90940C 7C14745C 7C14735C 7C245A35C 7C245AL35C 7C293A35C 7C293AL-35C
2909AM 7C90940M 7C14825C 7C14825C 7C245A35M 7C245A25M 7C293A35M 7C293A30M I

2910AC 7C9105OC 7C14835C 7C148-25C+ 7C245AL35C 7C245A25C + 7C293A50C 7C293AL5OC
2910AM 7C91051M 7C148-45C 7C14835C 7C245L35C 7C24535C+ 7C293A50M 7C293A35M
2910C 2910AC 7C14935C 7C14925C+ 7C245L45C 7C245L35C 7C293AL35C 7C293A2OC +
29 10M 29 lOAM 7C14945C 7C14935C 7C25155C 7C25145C 7C293AL5OC 7C293AL-35C
2911AC 7C9114OC 7C14945M 7C14935M 7C25165C 7C25155C 7C4011OC 7C40115C
Note: Unless otherwise noted, product meets all performance specs and is within 10 mA on Icc and 5 mA on ISB ;
+ = meets all performance specs but may not meet Icc or ISB ;
* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;
- = functionally equivalent
1-8
~ Product Line Cross Reference (Continued)
~~~~U~R================================================================~
CYPRESS
7C401-IOM
7C401-5C
7C402-1OC
7C402-IOM
7C402-5C
CYPRESS
7C401-15M
7C401-1OC
7C402-15C
7C402-15M
7C402-IOC
CYPRESS
7C517-45C
7C517-55C
7C517-55M
7C517-75C
7C517-75M
CYPRESS
7C517-3SC
7C517-45C
7C517-42M
7C517-55C
7C517-55M
CYPRESS
PALC16RS-35C
PALC16RS-40M
PALC16RSL-35C
PALC22VIO-35C
PALC22VIO-40M
CYPRESS
PALC16RS-25C
PALC16RS-30M
PALC 16RSL-25C
PALC22VIO-25C
PALC22V1 0-30M
AMD
216S-45M
216S-55C
216S-55M
216S-7OC
216S-70M
CYPRESS
7C16S-45M
7C16S-45C
7C16S-45M
7C16S-45C
7C16S-45M

7C403-1OC 7C403-15C 7C901-31C 7C901-23C+ PALC22VIOL-25C PALC22VIO-25C 2169-40C 7C169-40C
7C403-IOM 7C403-15M 7C901-32M 7C901-27M PALC22VIOL-35C PALC22VIOL-25C 21 69-50C 7C169-40C
7C403-15C 7C403-25C 7C909-40C 7C909-30C PLDC20GI0-35C PLDC2OGI0-25C 2169-50M 7C169-40M
7C403-15M 7C403-25M 7C909-40M 7C909-30M PLDC20G IO-40M PLDC20GlO-30M 2169-70C 7C169-40C
7C404-1OC 7C404-15C 7C91O-5OC 7C91O-40C 2169-70M 7C169-40M
7C404-IOM 7C404-15M 7C91O-51M 7C910-46M AMD CYPRESS 21L47-45C 7C147-45C
7C404-15C 7C404-25C 7C910-93C 7C91O-50C PREFIX:Am PREFIX:CY 21L47-55C 7C147-45C

7C404-15M 7C404-25M 7C91O-99M 7C91O-51M PREFIX:SN PREFIX:CY 21L47-70C 7C147-45C
7C40S-15C 7C40S-25C 7C9101-40C 7C9101-3OC SUFFIX:B SUFFIX:B 21L4S-45C 21L4S-45C
7C40S-15M 7C40S-25M 7C9101-45M 7C9101-35M SUFFIX:D SUFFIX:D 21L4S-55C 21L4S-55C
7C40S-25C 7C40S-35C 7C911-40C 7C911-30C SUFFIX:F SUFFIX:F 21L4S-7OC 21L4S-55C
7C409-15C 7C409-25C 7C911-40M 7C911-30M SUFFIX:L SUFFIX:L 21L49-45C 21L49-45C
7C409-15M 7C409-25M 9122-25C 7C122-15C SUFFIX:P SUFFIX:P 21L49-55C 21L49-55C

7C409-25C 7C409-35C 9122-25C 91L22-25C 2l30-100C 7C130-55C 21L49-70C 21L49-55C
7C420-40C 7C420-30C 9122-35C 9122-25C 2l30-12OC 7C130-55C 27C191-25C 7C292A-25C
7C420-40M 7C420-30M 9122-35C 91L22-35C 2130-70C 7C130-55C 27C191-35C 7C291A-25C +
7C420-65C 7C420-40C 9122-45C 93L422C 2147-35C 2147-35C 27C191-35C 7C291A-35C
7C420-65M 7C420-40M 91L22-25C 7C122-25C 2147-45C 2147-45C. 27C191-35C 7C292A-35C
7C421-4OC 7C421-3OC 91L22-35C 7C122-35C 2147-45M 2147-45M 27C191-35C 7C292AL-35C

7C421-40M 7C421-30M 91L22-45C 93L422AC 2147-55C 2147-55C 27C191-35M 7C292A-30M
7C421-65C 7C421-40C 93422AC 7C122-35C 2147-55M 214755M 27C191-45M 7C291A-45M
7C421-65M 7C421-40M 93422AC 9122-35C 2147-70C 2147-55C 27C291-25C 7C291A-25C
7C424-4OC 7C424-30C 93422AM 7C122-35M 2147-70M 2147-55M 27C291-35C 7C291AL-35C
7C424-40M 7C424-30M 93422C 93L422AC 214S-35C 214S-35C 27C291-45M 7C291A-35M
7C424-65C 7C424-40C 93422M 93422AM 214S-35M 214S-35M 27C291A-30M 7C291A-30M

7C424-65M 7C424-40M 93422M 93L422AM 214S-45C 214S-45C 27LS03C 27LS03C
7C425-4OC 7C425-3OC 93L422AC 7C122-35C 214S-45M 214S-45M 27LS03M 27LS03M+
7C425-40M 7C425-30M 93L422AC 91L22-45C 214S-55C 214S-55C 27LS07C 27S07C+
7C425-65C 7C425-40C 93L422AM 7C122-35M 214S-55M 214S-55M 27LS191C 7C292-35C
7C425-65M 7C425-40M 93L422C 93L422AC 214S-70C 214S-55C 27LS291C 7C291-35C
7C42S-40C 7C42S-30C 93L422M 93L422AM 214S-70M 214S-55M 27LS291M 7C291-35M

7C42S-40M 7C42S-30M PALC16LS-25C PALC16LSL-25C 2149-35C 2149-35C 27PSlS1AC 7C2S2-45C
7C42S-65C 7C428-4OC PALC16LS-30M PALC16L8-20M 2149-45C 2149-45C 27PS181AM 7C282-45M+
7C42S-65M 7C428-40M PALC16LS-35C PALC16LS-25C 2149-45M 2149-45M 27PSlS1C 7C2S2-45C
7C429-4OC 7C429-3OC PALC16L8-40M PALC16LS-30M 2149-55C 2149-55C 27PS181M 7C2S2-45M+
7C429-40M 7C429-30M PALC16LSL-35C PALC16LSL-25C 2149-55M 2149-55M 27PS191AC 7C292-50C
7C429-65C 7C429-40C PALC16R4-25C PALC16R4L-25C 2149-7OC 2149-55C 27PS191AM 7C292-50M+

7C429-65M 7C429-40M PALC16R4-30M PALC16R4-20M 2149-70M 2149-55M 27PS191C 7C292-50C
7C510-55C 7C510-45C PALC16R4-35C PALC16R4-25C 2167-35C 7C167-35C 27PS191M 7C292-50M+
7C51O-65C 7C51O-55C PALC16R4-40M PALC16R4-30M 2167-35M 7C167-35M 27PS2S1AC 7C2S1-45C
7C510-65M 7C51O-55M PALC16R4L-35C PALC16R4L-25C 2167-45C 7C167-45C 27PS28 lAM 7C2S1-45M+
7C51O-75C 7C51O65C PALC1 6R6-25C PALC16R6L-25C 2167-45M 7C167-45M 27PS2S1C 7C2S1-45C
.: 7C51O-75M 7C51O-65M PALC16R6-30M PALC16R6-20M 2167-55C 7C167-45C 27PS2S1M 7C2S1-45M+

7C516-45C 7C516-3SC PALC16R6-35C PALC16R6-25C 2167-55M 7C167-45M 27PS291AC 7C291-50C
7C516-55C 7C516-45C PALC1 6R6-40M PALC16R6-30M 2167-70C 7C167-45C 27PS29 lAM 7C291-50M+
7C516-55M 7C51642M PALC16R6L-35C PALC1 6R6L-25C 2167-70M 7C167-45M 27PS291C 7C291-5OC
7C516-75C 7C516-55C PALC16RS-25C PALC16R8L-25C 216S-35C 7C16S-35C 27PS291M 7C291-50M+
7C516-75M 7C516-55M PALC16RS-30M PALC1 6RS-20M 216S-45C 7C16S-45C 27S03AC 27S03AC
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
1-9
~~~UcrOR=====================================================================
AMD CYPRESS AMD CYPRESS AMD CYPRESS AMD CYPRESS
27S03AM 27S03AM 290lBC 2901CC 29L51OM 7C51O-75M 99C165-55C 7C166-45C+
27S03C 27S03C 290lBM 2901CM 29L516C 7C516-75C 99C165-55M 7C166-45M+
27S03M 27S03M 2901CC 2901CC 29L516M 7C516-75M 99C165-70C 7C166-45C+
27S07AC 27S07AC 2901CM 2901CM 29L517C 7CS17-7SC 99C16S-70M 7C166-45M+
27S07AM 27S07AM 2909AC 2909AC 29L517M 7CS17-7SM 99C641-2SC 7C187-2SC
27S07C 27S07C 2909AM 2909AM 3341C 3341C 99C641-3SC 7C187-3SC

27S07M 27S07M 2909C 2909AC 3341M 3341M 99C641-4SC 7C187-45C
27S181AC 7C282-3OC 2909M 2909M S4S189M S4S189M 99C641-4SM 7C187-4SM
27S181AM 7C282-4SM 2910-1C 2910C 74S189C 74S189C 99C641-SSC 7C187-4SC
27S181C 7C282-4SC 2910-1M 2910M 9122-2SC 9122-2SC 99C641-SSM 7C187-4SM
27S181M 7C282-4SM 2910AC 2910AC 9122-35C 9122-35C 99C641-70C 7C187-45C
27S191AC 7C292-3SC 2910AM 2910AM 9122-3SM 7C122-3SM 99C641-70M 7C187-4SM

27S191AM 7C292-S0M 2910C 2910C 9128-100c 6116-SSC 99C68-3SC 7C168-3SC
27S191C 7C292-SOC 2910M 2910M 9128-120M 6116-S5M 99C68-4SC 7C168-4SC*
27S191M 7C292-S0M 29116AC 7C9116AC 912S-lSOC 6116-S5C 99C6S-4SM 7C16S-4SM*
27S191SAC 7C292A-2OC 29116AM 7C9116AM 912S-1S0M 6116-SSM 99C6S-S5C 7C168-45C*
27S2SAC 7C22S-3OC 29116C 7C9116AC 912S-200C 6116-5SC 99C68-SSM 7C16S-4SM*
27S2SAM 7C225-3SM 29116M 7C9116AM 9128-200M 6116-S5M 99C68-70C 7C168-4SC*

27S2SC 7C22S-4OC 29117C 7C9117AC 9128-70C 6116-SSC 99C6S-70M 7C16S-4SM*
27S2SM 7C22S-40M 29117M 7C9117AM 9128-90M 6116-SSM 99C8SH-3SC 7C186-3SC
27S25SAC 7C22S-25C 2911AC 2911AC 9150-20C 7C150-1SC 99C88H-4SC 7C186-45C
27S2SSAM 7C225-3SM 2911AM 29 11 AM 9150-25C 7C150-25C 99CS8H-45M 7C1S6-45M
27S2S1AC 7C281-30C 2911C 2911AC 9150-25M 7C150-25M 99CS8H-55C 7C1S6-55C
27S2S1AM 7C281-45M 2911M 2911M 9150-35C 7C150-35C 99C88H-55M 7C1S6-55M

27S2S1C 7C281-45C 29510C 7C510-75C 9150-35M 7C150-35M 99C88H-70C 7C1S6-55C
27S2S1M 7C281-45M 29510M 7C510-75M 9150-45C 7C150-35C 99CS8H-70M 7C1S6-55M
27S291AC 7C291-35C 2951<iAM 7C516-55M 9150-45M 7C150-35M 99CL68-35C 7C168-35C
27S291AM 7C291-50M 29516C 7C516-55C 91L22-35C 91L22-35C 99CL6S-45C 7C16S-45C*
27S291C 7C291-5OC 29516M 7C516-55M 91L22-35M 7C122-35M 99CL6S-45M 7C168-45M*
27S291M 7C291-50M 29517AC 7CS17-3SC 91L22-45C 91L22-45C 99CL68-55C 7C168-45C*

27S291SAC 7C291A-25C 29517C 7C517-55C 91L22-45M 7C122-35M 99CL68-55M 7C16S-45M*
27S291SAM 7C291A-30M 29517M 7C517-55M 91L22-6OC 7C122-35C+ 99CL68-70C 7C168-45C*
27S35AC 7C235-3OC 29701C 27S07C 91L50-25C 7C150-25C 99CL68-70M 7C168-45M*
27S35AM 7C235-40M 29701M 27S07M 91L50-35C 7C150-35C PAL16LSA-4C PALC16L8L-35C
27S35C 7C235-40C 29703C 27S03C 91L50-45C 7C150-35C PAL16L8A-4M PALC16L8-40M
27S35M 7C235-40M 29703M 27S03M 93422AC 93422AC PAL16LSAC PALC16LS-25C

27S45AC 7C245-35C 29C01-1C 7C901-23C+ 93422AM 93422AM PAL16LSALC PALC16L8-25C I
27S45AM 7C245-45M 29COIBA 7C901-32M 93422C 93422C PAL16L8ALM PALC16L8-30M I
27S45C 7C245-45C 29COlBC 7C901-31C 93422M 93422M PAL 16L8AM PALC16LS-30M

27S45M 7C245-45M 29COIC 7C901-31C 93L422AC 93L422AC PAL16LSBM PALC16LS-20M
27S45SAC 7C245-25C 29COICC 7C901-31C 93L422AM 93L422AM PAL16LSC PALC16LS-35C
27S45SAM 7C245A-25M - 29CIO-IC 7C91O-4OC 93L422C 93L422C PAL16L8LC PALC16LS-35C

27S49A-45C 7C264-45C 29CI0IC 7C9101-4OC 93L422M 93L422M PAL16LSLM PALC16LS-40M
27S49AC 7C264-45C 29ClOIM 7C9101-35M 99Cl64-35C 7Cl64-35C+ PAL16LSM PALC16L8-40M
27S49AM 7C264-55M 29ClOABA 7C910-51M 99Cl64-45C 7C164-45C+ PAL16LSQC PALC16LSL-35C I
27S49C 7C264-55C 29CIQAC 7C910-5OC 99Cl64-45M 7Cl64-45M+ PAL16LSQM PALC16L8-40M
27S49M 7C264-5SM 29CIOAC 7C91O-93C 99Cl64-55C 7Cl64-45C+ PAL16R4A-4C PALC16R4L-35C
27S51C 7C254-55C 29C116C 7C9116AC 99C164-55M 7Cl64-45M + PAL16R4A-4M PALC16R4-40M

27S5lM 7C254-65M 29C116M 7C9116AM 99Cl64-70C 7Cl64-45C+ PAL16R4ALC PALC16R4-25C
2S41AC 3341C 29C117C 7C9117AC 99Cl64-70M 7Cl64-45M PAL16R4ALM PALC16R4-30M
2841AM 3341M 29L116AC 7C9116AC 99C165-35C 7C166-35C+ PAL16R4AM PALC16R4-30M
2S41C 3341C 29L116AM 7C9116AM 99C165-45C 7C166-45C+ PAL16R4BM PALC16R4-20M
2S41M 3341M 29L51OC 7C51O-75C 99C165-45M 7C166-45M+ PAL16R4C PALC16R4-35C
Note: Unless otherwise noted, product meets aU performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
+ = meets all performance spec~ but may not meet Icc or ISB ;
1-10
~~~UcrOR=====================================================================
AMD
PAL 16R4LC
PAL 16R4LM
PAL16R4M
PAL16R4QC
PAL16R4QM
CYPRESS
PALCI6R4-35C
PALCI6R4-40M
PALCI6R4-40M
PALCI6R4L35C
PALCI6R440M
DENSEPAK
102725C
102725C
102735C
102735C
102745C
CYPRESS
1621HD25C
1621HD25C
1621HD3OC
1621HD35C
1621HD45C
FAIRCHILD
100E4225
100E4225
100E4227
100E4227
100E474-7
CYPRESS
100E4225C
1OE4225C
100E4227C
1OE4227C
100E474-7C
FAIRCHILD
93U22AC
93U22AM
93U22C
93U22M
93Z451AC
CYPRESS
93U22AC
93U22AM
93U22C
93U22M
7C28230C

PAL16R6A4C PALCI6R6L35C 102755C 1621HD55C 100E4747 1OE4747C 93Z451AM 7C28245M
PAL16R6A4M PALCI6R640M 16X1725C 1611HV25C 1600c45 7C18745C 93Z451C 7C2823OC
PAL16R6AC PALCI6R625C 16X1725C 1611HV25C 16OOC55 7C18745C 93Z451M 7C28245M
PAL 16R6ALC PALCI6R625C 16X1735C 1611HV35C 1600C70 7C18745C 93Z51lC 7C29235C
PAL16R6ALM PALCI6R630M 16X1735C 1611HV35C 1600M55 7C18745M 93Z51lM 7C29250M
PAL16R6AM PALCI6R630M 16X1745C 1611HV45C 1600M70 7C18745M 93Z565AC 7C264-45C
PAL16R6BM PALCI6R620M 16X17-45C 1611HV45C 1601C55 7C18745C 93Z565AM 7C26455M

PAL16R6C PALCI6R635C 16X1755C 1611HV55C 162OC35 7CI6435C+ 93Z565C 7C26455C
PAL16R6LC PALCI6R635C 41288100c 1421HD85C 1620M35 7CI6435M 93Z565M 7C264-55M
PAL16R6LM PALCI6R6-40M 41288100c 1421HD100C 1620M45 7CI6445M 93Z61lC 7C29225C
PAL16R6M PALCI6R640M 4128870C 1421HD70C 1621C25 7CI6425C+ 93Z611M 7C291A30M
PAL16R6QC PALCI6R6L35C 4128885C 1421HD85C 1622C25 7CI6625C+ 93Z665C 7C26435C
PAL16R6QM PALCI6R640M 4128885C 1421HD85C 1622C35 7CI6635C+ 93Z665M 7C26445M

PAL16R8A4C PALCI6R8L35 643245C 1830HD-45C 1622M35 7C16635M 93Z667C 7C26335C
PAL16R8A-4M PALCI6R8-40M 643255C 1830HD55C 1622M45 7C16645M 93Z667M 7C26145M
PAL16R8AC PALCI6R825C 643255C 1830HD55C 16L8A PALCI6L820M
PAL16R8ALC PALCI6R825C 8M624100C 1623HD85C 16L8A PALCI6L825C FUJITSU CYPRESS
PAL16R8ALM PALCI6R830M 8M62485C 1623HD100C 16P8A PALCI6L820M PREFIX:MB PREFIX:CY
PAL16R8AM PALCI6R830M 8M65635C 161OHD35C 16P8A PALCI6L825C- PREFIX:MBM PREFIX:CY

PAL16R8BM PALCI6R820M 8M6567OC 161OHD70C 16R4A PALCI6R420M SUFFIX:F SUFFIX:F
PAL16R8C PALCI6R835C 16R4A PALCI6R425C SUFFIX:M SUFFIX:P
PAL16R8LC PALCI6R835C EDI CYPRESS 16R6A PALCI6R620M SUFFIX:Z SUFFIX:D
PAL16R8LM PALCI6R840M PREFIX:ED PREFIX:CYM 16R6A PALCI6R625C 100422A5C 100E4225C
PAL16R8M PALCI6R840M 816H16C25 1611HV25C 16R8A PALCI6R820M 100422A7C 100E4227C
PAL16R8QC PALCI6R8L35 816H16C35 1611HV35C 16R8A PALCI6R825C 100422AC 100E4227C

PAL16R8QM PALCI6R840M 816H16C-45 1611HV45C 16RP4A PALCI6R420M 100474A3C 100E4743C
PAL22VIOAC PALC22VIO25C 8M8128C100 1421HD85C 16RP4A PALCI6R425C 100474A5C 100E4745C
PAL22VIOAM PALC22VIO30M 8M8128C70 1421HD70C 16RP6A PALCI6R620M 100474A7C 100E4747C
PAL22VIOC PALC22VIO35C H816HI6C25CC 1611HV25C 16RP6A PALCI6R625C 100474AC 100E4747C
PAL22VlOM PALC22V1 O-4OM H816HI6C35CC 1611HV35C 16RP8A PALCI6R820M 10422A5C 1OE4225C
H816HI6C-45CC 1611HV45C 16RP8A PALCI6R825C 10422A7C IOE4227C

ANALOGDEV CYPRESS H816HI6C55CC 1611HV45C 3341AC 3341C 10422AC 1OE4227C
PREFIX:ADSP PREFIX:CY I8MI664ClOOCC 1623HDlOOC 3341C 3341C 10474A3C 1OE4743C
SUFFIX:883B SUFFIX:B I8MI664C6OCC 1623HD55C 54F189 7CI8925M- 10474A5C 1OE4745C
SUFFIX:D SUFFIX:D I8MI664C7OCC 1623HD70C 54F219 7CI9025M- 10474A7C 1OE4747C
SUFFIX:E SUFFIX:L IBM 1664C85CC 1623HD85C 54F413 7C40115M 10474AC 1OE4747C
SUFFIX:F SUFFIX:F I8M8128C6OCC 1420HD55C 54S189M 54S189M 2147H35 214735C

SUFFIX:G SUFFIX:G I8M8128C70CC 1421HD70C 74AC 10 1040 7C51O.45C 2147H45 214745C
10 lOA 7C51O65C+ I8M8128C80CC 1421HD70C 74F189 7CI8925C- 2147H55 214755C
IOIOJ 7C51O75C+ I8M8128C90CC 1421HD85C 74F219 7CI9025C- 2147H70 214755C
10 10K 7C51O75C+ 74F413 7C40115C 214855L 21U855C
10 lOS 7C51O75M + FAIRCHILD CYPRESS 74LS189 27LS03C 214870L 21U855C
.101OT 7C51O75M + PREFIX:F PREFIX:CY 74S189 74S189C 214945 2149-45C

7C90127M 7C90132M SUFFIX:D SUFFIX:D 93422AC 93422AC 214955L 21U955C
7C90132M 2901CM SUFFIX:F SUFFIX:F 93422AM 93422AM 214970L 21U955C
SUFFIX:L SUFFIX:L 93422C 93422C 7132E 7C28245C
DENSEPAK CYPRESS SUFFIX:P SUFFIX:P 93422M 93422M 7132ESK 7C28145C
PREFIX:DPS PREFIX:CYM SUFFIX:QB SUFFIX:B 93475C 214945C 7132EW 7C282-45M
lote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
1-11
~ ProductLine Cross Reference (Continued)
~~~UaoR==================================================================
FUJITSU CYPRESS HARRIS CYPRESS HITACHI CYPRESS HITACHI CYPRESS
7132H 7C282-45C PREFIX:HM PREFIX:CY PREFIX:HM PREFIX:CY 6168HL55 7CI68-45C'
7132HSK 7C281-45C PREFIX:HPL PREFIX:CY PREFIX:HN PREFIX:CY 6168HL70 7CI6845C'
7132Y 7C2823OC SUFFIX:8 SUFFIX:B SUFFIX:CG SUFFIX:L 6264-10 7CI8655C+
7132YSK 7C2813OC PREFIX: 1 SUFFIX:D SUFFIX:G SUFFIX:D 6264-12 7CI8655C+
7138E 7C2925OC PREFIX:9 SUFFIX:F SUFFIX:P SUFFIX:P 626415 7CI8655C+
7138ESK 7C2915OC PREFIX:4 SUFFIX:L l00422C lOOE4227C 626735 7CI6735C+

7138EW 7C29250M PREFIX:3 SUFFIX:P l00474-1OC lOOE4747C 626745 7C167-45C
7138H 7C29235C 16LC85 PALCI6L8L35C l004748C lOOE474-7C 626825 7C16825C
7138HSK 7C29135C 16LC88 PALCI6L8-40M l00474C lOOE474-7C 626835 7C16835C
7138Y 7C29235C 16LC89 PALCI6L84OM I0422C 1OE4227C 628745 7C187-45C
7138YSK 7C29135C 16RC45 PALCI6R4L35C 10474toC lOOE4747C 628755 7C187-45C
7144E 7C264-55C 16RC48 PALCI6R4-4OM 104748C 10E4747C 628770 7C187-45C

7144EW 7C264-55M 16RC49 PALCI6R4-4OM 10474C lOOE4747C 628835 7CI6435C
7144H 7C26455C 16RC65 PALCI6R6L35C 25089 7C28245C 628845 7CI6445C
7144Y 7C264-45C 16RC68 PALCI6R64OM 25089S 7C28245C 628855 7CI64-45C
7226RA20 7C2253OC 16RC69 PALCI6R64OM 25169S 7C29250C 6716 7C12825C
7226RA25 7C2253OC 16RC85 PALCI6R8L35C 4847 214755C 678730 7C18725C
7232RA20 7C2353OC 16RC88 PALCI6R84OM 48472 214745C 678825 7CI6425C

7232RA25 7C2353OC 16RC89 PALCI6R84OM 48473 214755C 678830 7CI6425C
7238RA20 7C24525C 6761612 7C29150M 6116ALS12 611655C*
7238RA25 7C24535C 6761615 7C2915OC 6116ALS15 611655C' INMOS CYPRESS
812810 7C12855C 676161A2 7C29150M 6116ALS20 611655C* PREFIX:IMS PREFIX:CY
812815 7C12855C 6-76161A5 7C29150C 6116AS12 611655C+ SUFFIX:B SUFFIX:B
816770W 7C167-45M 676161B5 7C29135C 6116AS15 611655C+ SUFFIX:P SUFFIX:P

8167A55 7C16745C 676815 7C28145C 6116AS20 611655C+ SUFFIX:S SUFFIX:D
8167A70 7C16745C 67681A5 7C28145C 6147 7CI4745C* SUFFIX:W SUFFIX:L
816855 7C16845C 651625 6116-55C' 61473 7CI4745C* 120325 7CI4725C+
816870 7C16845C 651628 611655M* 6147H35 7CI4735C+ 120335 7CI4735C+
816870W 7C168-45M 651629 611655M* 6147H45 7CI4745C+ 120345 7CI47-45C+
817155 7C187-45 65162B5 611655C* 6147H55 7CI4745C+ 1203M35 7CI4735M+

817170 7C18745C 65162B8 611655M* 6147HL35 7CI4735C* 1203M45 7CI4745M+
81C6735 7C16735C 65162B9 6116-55M* 6147HL45 7CI4745C* 122325 7C14825C
81C6745 7C167-45C 65162C8 611655M* 6147HL55 7CI4755C* 122335 7C14835C
81C6755W 7C167-45M 65162C9 611655M* 6148 7C14845C 122345 7C14845C
81C68-45 7C168-45C 65162S5 611655C* 6148H35 21L4835C 1223M35 7CI4825M+
81C6855W 7C168-45M + 65162S9 611655M* 6148H45 7CI4845C+ 1223M45 7CI4845M+

81C71-45 7C187-45C 652628 7CI67-45M* 6148H55 7CI4845C+ 140035 7C16735C
81C7155 7C18745C 652629 7CI6745M* 6148HL35 21L4835C' 140045 7C16745C
81C7425 7CI6425C 65262B8 7CI6745M* 6148HL45 7CI4845C' 140055 7C16745C
81C74-35 7CI6435C+ 65262B9 7CI67-45M* 6148HL55 7CI4845C* 14OOM45 7C16745M
81C74-45 7CI64-45C 65262C9 7CI67-45M* 6148L 7CI4845C* 14OOM55 7C16745M
81C7525 7C16625C 65262S9 7CI6745M* 61676 7CI6745C+ 14OOM70 7C16745M

81C7535 7C16635C 761612 7C29250M 61678 7CI6745C+ 140325 7C16725C
81C7845 7C186-45C 76161A2 7C29250M 6167H55 7C167-45C 140335 7CI6735C+
81C7855 7C18655C 76161A5 7C29250C 6167H70 7C16745C 140345 7CI6745C+
81C81-45 7C197-45C 76161B5 7C29235C 6167HL55 7CI6745C* 140355 7CI6745C+
81C8155 7C19745C 766412 7C264-55M 6167HL70 7CI6745C* 1403LM35 7CI6735M*
81C84-45 7C194-45C 766415 7C26455C 6167L6 7CI6745C* 1403M35 7CI6735M+

81C84-55 7C194-45C 76641A5 7C26445C 6167L8 7CI6745C* 1403M45 7CI6745M+
81C8655 7CI92-45C+ 76812 7C282-45M 6168H45 7CI6845C+ 1403M55 7CI6745M+
81C8670 7CI92-45C+ 76815 7C282-45C 6168H55 7CI6845C+ 1403M70 7CI6745M+
8464Lloo 7CI8555C+ 7681A5 7C28245C 6168H70 7CI6845C+ 142045 7C16835C
84641-70 7CI8545C+ 6168HL-45 7CI68-45C* 142055 7C16845C i
1-12
~
INMOS
1420M55
1420M70
1421C-40
142325
Product Line Cross Reference (Continued)
~~~U~R==================================================================
CYPRESS
7C168-45M+
7C16845M
7C169-4OC
7C16825C+
INMOS
180045
18ooM35
18ooM-45
182025
CYPRESS
7C19745C
7C19735M
7C19745M
7C19425C
IDT
6116LA70TB
6116LA90
6116LA90B
6116LA9OT
CYPRESS
7C12855M*
611655C*
611655M*
7C12855C*
IDT
6167SA25
6167SA35
6167SA35B
6167SA45
CYPRESS
7C16725C+
7C16735C+
7C16735M+
7C167-45C+
..
142335 7C16835C+ 182035 7C19435C 6116LA90TB 7C12855M* 6167SA45B 7CI6745M+
1423-40 7CI68-45C+ 1820-45 7C19445C 6116S120B 611655M + 6167SA55 7CI67-45C+

1423M35 7CI6835M* 6116S150B 611655M + 6167SA55B 7CI6745M+
1423M-45 7CI6845M* IDT CYPRESS 6116S55 611655C+ 6167SA70B 7CI6745M+
1423M55 7CI68-45M* PREFIX:IDT PREFIX:CY 6116S55B 611655M+ 6168LlooB 7CI68-45M*
143330 7C12825C+ PREFIX:IDT PREFIX:CYM 6116S70 611655C+ 6168145 7CI6845C*
143335 7CI2835C+ SUFFIX:B SUFFIX:B 6116S70B 611655M + 6168L55 7CI68-45C*
143345 7C128-45C+ SUFFIX:D SUFFIX:D 6116S90 611655C+ 6168L55B 7CI6845M*

143355 7CI2855C+ SUFFIX:F SUFFIX:F 6116S90B 611655M+ 6168170 7CI6845C
1433M35 7C12835M+ SUFFIX:L SUFFIX:L 6116SA120B 611655M+ 6168L70B 7CI6845M*
1433M-45 7C128-45M + SUFFIX:P SUFFIX:P 6116SA120TB 7CI2855M+ 6168L85 7CI6845C*
1433M55 7CI2855M+ 39C01CB 7C90132M+ 6116SA35 611635C+ 6168L85B 7CI68-45M*
1600-35 7C18735C 39C01CC 2901CC+ 6116SA35B 611645M+ 6168LA25 7CI6825C
160045 7C18745C 39C01CM 2901CM+ 6116SA35T 7CI2835C+ 6168LA35 7CI6835C*

1600-55 7C187-45C 39COIDB 7C90127M+ 6116SA35TB 7CI2835M+ 6168LA35B 7CI6835M*
1600-70 7C187-45C 39COIDC 7C90123C+ 6116SA45 6116-45C+ 6168LA45 7CI6845C*
1600M-45 7C187-45M + 39C09A 7C909-40C+ 6116SA45B 611645M + 6168LA45B 7CI6845M*
1600M55 7C187-45M + 39C09AB 7C90940M+ 6116SA45T 7CI2845C+ 6168LA55 7CI6845C*
1600M70 7C187-45M + 39ClOB 7C91O50C- 6116SA45TB 7CI28-45M+ 6168LA55B 7CI6845M*
160 1LM45 7C187-45M + 39ClOBB 7C91O51M 6116SA55 611655C+ 6168LA70B 7CI6845M*

1601LM55 7CI87-45M+ 39C11A 7C91140C+ 6116SA55B 611655M + 6168S1ooB 7CI6845M+
1601LM70 7CI87-45M+ 39CllAB 7C91140M+ 6116SA55T 7CI2855C+ 6168S45 7CI6845C+
1620-35 7CI6435C 49C401 7C9101-40C- 6116SA55TB 7CI2855M+ 6168S55 7CI6845C+
1620-45 7CI64-45C+ 49C401 7C910145M - 6116SA70 611655C+ 6168S55B 7CI6845M+
162055 7CI64-45C+ 6116Ll20B 611655M* 6116SA70B 611655M + 6168S70 7C16845C
1620-70 7CI6445C+ 6116Ll50B 611655M* 6116SA70T 7CI2855C+ 6168S70B 7C16845M

1620M-45 7CI64-45M 6116L55 611655C* 6116SA70TB 7CI2855M+ 6168S85 7C16845C
1620M55 7CI64-45M 6116L55B 611655M* 6116SA90 611655C+ 6168S85B 7C16845M
I 1620M.70 7CI64-45M 6116L70 611655C* 6116SA90B 611655M+ 6168SA25 7CI6825C+
1624-35 7CI6635C+ 6116L70B 611655M* 6116SA90T 7CI2855C+ 6168SA35 7CI6835C+
1624-45 7CI66-45C+ 6116L90 611655C* 6116SA9OTB 7CI2855M+ 6168SA35B 7CI6835M+
1624-55 7CI66-45C+ 6116L90B 611655M* 6167LlooB 7CI6745M* 6168SA45 7CI68-45C+

1624-70 7C16645C+ 6116LA120B 611655M* 6167L55B 7CI6745M* 6168SA45B 7CI6845M+
1624M45 7C166-45M 6116LA12OTB 7C12855M* 6167170B 7CI67-45M* 6168SA55 7CI68-45C+
1624M55 7C166-45M 6116LA35 611635C* 6167L85B 7CI6745M* 6168SA55B 7CI6845M+
1624M70 7C166-45M 6116LA35B 611645M* 6167LA25 7CI6725C* 6168SA70B 7CI6845M+
162525 7Cl64-25C 6116LA35T 7CI2835C* 6167LA35 7CI6735C* 7130Lloo 7C13055C*
162535 7CI6435C 6116LA35TB 7C12835M* 6167LA35B 7CI6735M* 7130LlooB 7C13055M

1625M35 7CI64-45M 6116LA45 611645C 6167LA45 7CI6745C* 7130Ll20B 7C13055M
1625M-45 7CI6445M 6116LA45B 611645M* 6167LA45B 7CI6745M* 7130L55 7C13055C*
1630-45 7C18645C+ 6116LA45T 7CI2845C 6167LA55 7CI6745C 7130L70 7C13055C*
163055 7CI8655C+ 6116LA45TB 7CI2845M* 6167LA55B 7CI6745M* 7130L90 7C13055C*
163070 7CI8655C+ 6116LA55 611655C 6167LA70B 7CI6745M* 7130S1OO 7C13055C
1630LM70 7C18655M 6116LA55B 611655M* 6167S1ooB 7C16745M 7130S1ooB 7C13055M

1630M-45 7C18645M 6116LA55T 7CI2855C 6167S45 7C16745C 7130S120B 7C13055M
1630M55 7CI8655M+ 6116LA55TB 7CI2855M* 6167S55 7C16745C 7130S55 7C13055C
1630M70 7C18655M 6116LA70 611655C* 6167S55B 7C16745M 7130S70 7C13055C
1800-30 7C19725C 6116LA70B 611655M* 6167S70B 7C16745M 7130S90 7C13055C
180035 7C19735C 6116LA70T 7CI2855C 6167S85B 7C16745M 7132Lloo 7C13255C*
rote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
'" = meets all performance specs except 2V data retention-may not meet Icc or ISB ;
1-13
~~~NDUcrOR================================================================~~
IDT CYPRESS lOT CYPRESS lOT CYPRESS lOT CYPRESS
7132L100B 7C13255M" 716821100B 7C172-45M" 71981855B 7C161-45M 72028A120B 7C424-65M
7132L120B 7C13255M" 71682U5 7C17245C" 71981870 7C161-45C 72028A35 7C424-3OC
7132L55 7C13255C" 71682L55 7C17245C" 71981870B 7C16145M 72028A4OB 7C424-40M
7132L70 7C13255C" 71682L55B 7C17245M" 71981885B 7C16145M 72028A50 7C424-4OC
7132L70B 7C13255M" 71682L70 7C172-45C' 71982835 7C16235C 72028A50B 7C424-40M
7132L90 7C13255C 71682L70B 7CI7245M 71982835B 7C16235M 72028A65 7C424-65C

7132L90B 7C13255M" 71682L85B 7C17245M 71982845 7C162-45C 72028A65B 7C424-65M
71328100 7C13255C+ 71682LA25 7C17225C" 71982845B 7C16245M 72028A80 7C42465C
71328100B 7C13255M + 71682LA35 7C17235C" 71982855 7C162-45C 72028A80B 7C42465M
71328120B 7C13255M + 71682LA35B 7C17235M* 71982855B 7C162-45M 7210-120B 7C510-75M +
7132855 7C13255C+ 71682LA45 7C17245C 71982870 7C162-45C 7210-200B 7C51075M+
7132870 7C13255C+ 71682LA45B 7C172-45M" 71982870B 7C16245M 721055B 7C51O55M

7132870B 7C13255M+ 71682LA55 7C17245C 71982885B 7C162-45M 721065B 7C51O65M
7132890 7C13255C+ 71682LA55B 7CI7245M" 7198835 7C16635C 721075B 7C51075M
7132890B 7C13255M + 716828100B 7C17245M+ 7198835B 7C16635M 7210-85B 7C51075M
7164835 7C18635C 71682845 7C17245C+ 7198845 7C166-45C 72lOL-45 7C51045C+
7164845 7C18645C 71682855 7C17245C+ 7198845B 7C16645M 72lOL100 7C510-75C+
7164845B 7C18645M 71682855B 7C17245M+ 7198855 7C16645C 72101165 7C510-75C+

7164855 7C18655C 71682870 7C17245C+ 7198855B 7C16645M 7210L55 7C51055C+
7164855B 7C18655M 71682870B 7C172-45M + 7198870 7C16645C 7210L65 7C510-65C+
7164870 7C18655C 71682885B 7C17245M+ 7198870B 7C16645M 7210L75 7C51075C+
7164S70B 7C18655M 716828A25 7C17225C+ 7198885B 7C16645M 72161120B 7C51675M+
7164885B 7C18655M 716828A35 7C17235C+ 7201LA120 7C42065C+ 72161140 7C51675C+
716811100B 7CI7145M* 716828A35B 7C17235M + 720 1LA 120B 7C42065M+ 72161185B 7C51675M+
71681U5 7C171-45C" 716828A45 7C17245C+ 7201LA35 7C4203OC+ 7216L55 7C51655C+
71681L55 7C171-45C" 716828A45B 7C17245M+ 7201LA4OB 7C4204OM+ 7216L55B 7C51655M
71681L55B 7C171-45M" 716828A55 7C17245C+ 7201LA50 7C4204OC+ 7216L65 7C51665C+
71681L70 7CI7145C" 716828A55B 7C17245M+ 7201LA50B 7C4204OM+ 7216L65B 7C51665M
71681L70B 7CI71-45M" 7187830 7C18725C 720 1LA65 7C42065C+ 7216L75 7C51675C+
71681L85B 7C17145M" 7187835 7C18735C 7201LA65B 7C420-65M + 7216L75B 7C51675M

71681LA25 7C17125C" 7187835B 7C18735M 7201LA80 7C42065C+ 7216L90 7C516-75C+
71681LA35 7C17135C 7187845 7C18745C 720 1LA80B 7C4206SM+ 7216L90B 7C51675M+
71681LA35B 7C17135M" 7187845B 7C187-45M 72018A120 7C42065C 7217L120B 7C51775M+
71681LA45 7C17145C" 7187855 7C18745C 720 18A120B 7C42065M 72171140 7C51775C+
71681LA45B 7CI7145M 7187855B 7C187-45M 72018A35 7C42030C 72171185B 7C51775M+
71681LA55 7C171-45C" 7187870 7C18745C 72018A4OB 7C4204OM 7217U5 7C51745C+

71681LA55B 7C17145M* 7187870B 7C18745M 72018A50 7C4204OC 7217L55 7C51755C+
71681LA70B 7CI7145M" 7187885 7C18745C 72018A50B 7C420-40M 7217L55B 7C51755M
716818100B 7CI7145M+ 7187885B 7C187-45M 720 18A65 7C42065C 7217L65 7C51765C+
71681845 7CI71-45C+ 7188830 7CI6425C 72018A65B 7C42065M 7217L65B 7C51765M
71681855 7C171-45C+ 7188835 7CI6435C 720 18A80 7C42065C 7217L75 7C51775C+
71681855B 7C17145M+ 7188S45 7CI6445C 72018A80B 7C42065M 7217L75B 7C51775M

71681870 7CI7145C+ 7188S45B 7C16445M 7202LA120 7C42465C+ 7217L90 7C51775C+
71681870B 7CI7145M+ 7188855 7CI6445C 7202LA120B 7C42465M+ 7217L90B 7C51775M+
71681885B 7CI71-45M+ 7188855B 7CI64-45M 7202LA35 7C42430C+ 7M4016835C 164lHD35C
716818A25 7CI7125C+ 7188870 7CI64-45C 7202LA-40B 7C4244OM+ 7M4016S45C 164lHD45C
716818A35 7CI7135C+ 7188870B 7CI64-45M 7202LA50 7C4244OC+ 7M4016855C 164lHD55C
716818A35B 7C17135M + 7188885B 7CI64-45M 7202LA50B 7C424-40M+ 7M4017S4OC 1830HD35C

716818A45 7C17145C+ 71981835 7C16135C 7202LA65 7C42465C+ 7M4017845C 1830HD45C
716818A45B 7C17145M+ 71981835B 7C16135M 7202LA65B 7C424-65M + 7M4017850C 1830HD45C
716818A55 7CI7145C+ 71981845 7C16145C 7202LA80 7C42465C+ 7M4017850CB 1830HD-45MB
716818A55B 7CI71-45M+ 71981845B 7C161-45M 7202LA80B 7C42465M+ 7M4017855C 1830HD55C
716818A70B 7C17145M+ 71981855 7C16145C 72028A120 7C42465C 7M4017860C 1830HD55C
+ = meets all performance specs but may not meet IcC or ISB ;
'" = meets all performance specs except 2V data retention-may not meet Icc or ISB ;
1-14
_n~NDucrOR ====================================================================
IDT
7M4017S60CB
7M4017S70C
7M4017S70CB
7M624S30C
7M624S35C
CYPRESS
1S30HD-55MB
1S30HD-55C
1S30HD-55MB
162lHD-30C
162lHD-35C
IDT
SMP624S40S
SMP624S45S
SMP624S50S
SMP624S60S
SMPS24S40S
CYPRESS
1626PS-35C
1626PS-45C
1626PS-45C
1626PS-45C
1422PS-35C
LATTICE
16K4-25
16K4-35
16K4-35M
16K4-45
16K4-45M
CYPRESS
7C16S-25C
7C16S-35C
7C16S-35M
7C16S-45C
7C16S-45M
LATTICE
64E4-45
64E4-55
64K1-35
64K1-45
64K1-45M
CYPRESS
7C166-45C
7C166-45C
7C1S7-35C
7C1S7-45C
7C1S7-45M

7M624S35CB 162lHD-35MB SMPS24S45S 1422PS-45C 16KS-35 7C12S-35C+ 64K1-55 7C1S7-45C
7M624S45C 1621HD-45C SMPS24S50S 1422PS-45C 16KS-55 7C12S-45C+ 64K1-55M 7C1S7-45M
7M624S45CB 162lHD-45MB SMPS24S60S 1422PS-55C 16VS-25 PALC16LS-25C 64K4-35 7C164-35C
7M624S55C 162lHD-45C SMPS24S70S 1422PS-55C 16VS-25 PALC16R4-25C 64K4-45 7C164-45C
7M624S55CB 162lHD-45MB 16VS-25 PALC16R6-25C 64K4-45M 7C164-45M
7M624S65C 162lHD-45C INTEL CYPRESS 16VS-25 PALC16RS-25C 64K4-55 7C164-45C
7M624S65CB 162lHD-45MB PREFIX:D SUFFIX:D 16VS-25L PALC16LS-25C 64K4-55M 7C164-45M

7MC4005S25CV 161lHV-25C PREFIX:L SUFFIX:L 16VS-25L PALC16R4-25C 64KS-35 7C1S6-35C
7MC4005S30CV 161lHV-30C PREFIX:P SUFFIX:P 16VS-25L PALC16R6-25C 64KS-45 7C1S6-45C
7MC4005S35CV 161lHV-35C SUFFIX:!B SUFFIX:B 16VS-25L PALC16RS-25C 64KS-45 7C264-45C
7MC4005S45CV 1611HV-45C 2147H 2147-55C 16VS-25Q PALC16LSL-25C 64KS-45M 7C1S6-45M
7MC4005S55CV 161lHV-45C 2147H-1 2147-35C 16VS-25Q PALC16R4L-25 64KS-55 7C1S6-55C
7MC4032S25CV 1S22HV-25C 2147H-2 2147-45C 16VS-25Q PALC16R6L-25 64KS-55 7C264-55C

7MC4032S30CV 1S22HV-30C 2147H-3 2147-55C 16VS-25Q PALC16RSL-25 64KS-55M 7C1S6-45M
7MC4032S40CV 1S22HV-35C 2147HL 7C147-45C 16VS-30 PALC16LS-30M 64KS-70 7C264-55C
7MC4032S50CV 1S22HV-45C 214SH 214S-55C 16VS-30 PALC16R4-30M 11010-45 7C51O-45C+
7MP400S1100S 1461PS-100C 214SH-2 214S-45C 16VS-30 PALC16R6-30M 11010-65 7C51O-65C+
7MP400SLS5S 1461PS-S5C 2148H-3 214S-55C 16VS-30 PALC16RS-30M LIOIO-65B 7C510-65M +
7MP400SS45S 1460PS-45C 214SHL 21US-55C 16VS-30L PALC16LS-30M 11010-90 7C51O-75C+

7MP400SS55S 1460PS-55C 214SHL-3 21L4S-55C 16VS-30L PALC16R4-30M 11 01O-90B 7C51O-75M+
7MP400SS70S 1460PS-70C 2149H 2149-55C 16VS-30L PALC16R6-30M
SM624S45C 1620HD-45C 2149H-1 2149-35C 16VS-30L PALC16RS-30M MICRON CYPRESS
SM624S50C 1620HD-45C 2149H-2 2149-45C 16VS-3OQ PALC16LS-30M PREFIX:MT PREFIX:CY
SM624S50CB 1620HD-45MB 2149H-3 2149-55C 16VS-3OQ PALC16R4-30M 5C1601-2OC 7C167A-20C
SM624S60C 1620HD-55C 2149HL 21U9-55C 16VS-3OQ PALC16R6-30M 5C1601-25C 7C167A-25C

SM624S60CB 1620HD-55MB 51C66-25 7C167-25C- 16VS-3OQ PALC16RS,30M 5C1601-25M 7C167A-25M
SM624S7OC 1620HD-55C 51C66-30 7C167-25C- 16VS-35 PALC16LS-35C 5C1601-35C 7C167A-35C
SM624S70CB 1620HD-55MB 51C66-35 7C167-25C- 16VS-35 PALC16R4-35C 5C1601-35M 7C167A-35M
SM656S40C 161OHD-35C 51C66-35L 7C167-25C- 16VS-35 PALC16R6-35C 5C1601-45C 7C167A-45C
SM656S50C 161OHD-50C 51C67-30 7C167-25C+ 16VS-35 PALC16RS-35C 5C1601-45M 7C167A-45M
SM656S6OCB 161OHD-50MB 51C67-35 7C167-35C+ 16VS-35L PALC16LS-35C 5C1604-20C 7C16SA-20C

SM656S70C 161OHD-50C 51C67-35L 7C167-35C+ 16VS-35L PALC16R4-35C 5C1604-25C 7C16SA-25C
SM656S70CB 161OHD-50MB 51C6S-30 7C16S-25C+ l6VS-35L PALC16R6-35C 5CI604-25M 7C16SA-25M
SMS241100C 142lHD-S5C 51C6S-35 7C16S-35C+ 16VS-35L PALC16RS-35C 5C1604-35C 7C16SA-35C
SMS24LlOON 142lHD-S5C M2147H-3 7C169-40M 16VS-35Q PALC16LSL-35C 5C1604-35M 7C16SA-35M
SMS24L85C 142lHD-S5C M214SH 214S-55M 16VS-35Q PALC16R4L-35C 5C1604-45C 7C16SA-45C
SMS24LS5N 142lHD-S5C M2149H 2149-55M 16VS-35Q PALC16R6L-35C 5C1604-45M 7C16SA-45M

SMS24S45C 1420HD-45C M2149H-2 2149-45M 16VS-35Q PALC16RSL-35C 5C1605-2OC 7C170A-20C
SMS24S45N 1420HD-45C M2149H-3 2149-55M 20VS-25 PLDC20G 1O-25C 5C1605-25C 7C170A-25C
SMS24S50C 1420HD-45C 20VS-25L PLDC20G 1O-25C 5C1605-25M 7C170A-25M
SMS24S50CB 1420HD-45MB LATTICE CYPRESS 20VS-25Q PLDC20G 1O-25C 5C1605-35C 7C170A-35C
SMS24S50N 1420HD-45C PREFIX:EE PREFIX:CY 20VS-35 PLDC20G 1O-30M 5C1605-35M 7C170A-35M
SMS24S60C 1420HD-55C PREFIX:GAL PREFIX:CY 20VS-35 PLDC20G 10-35C 5C1605-45C 7C170A-45C

SMS24S60CB 1420HD-55MB PREFIX:SR PREFIX:CY 20VS-35L PLDC20G 1O-30M 5C1605-45M 7C170A-45M
8MS24S60N 1420HD-55C SUFFIX:B SUFFIX:B 20VS-35L PLDC20G 1O-35C 5C1606-20C 7C171A-20C
SMS24S70C 142lHD-70C SUFFIX:D SUFFIX:D 20VS-35Q PLDC20G 1O-30M 5C1606-25C 7Cl7lA-25C
I SMS24S70CB 1420HD-55MB SUFFIX:L SUFFIX:L 20VS-35Q PLDC20G 1O-35C 5C1606-25M 7Cl7lA-25M
SMS24S70N 142lHD-70C SUFFIX:P SUFFIX:P 64E4-35 7C166-35C 5C1606-35C 7C171A-35C
rote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
1-15
~~~NDUcrOR========================================================~~==~==~
MICRON CYPRESS MICRON CYPRESS MMI CYPRESS MMI CYPRESS
5C160635M 7C171A35M 5C640725C 7C16225C 53812 7C28245M C57401 7C401lOM
5C1606-45C 7C171A45C 5C640725M 7C16225M 5381S1 7C281-45M C57401A 7C401lOM
5C1606-45M 7C171 A45M 5C640735C 7C16235C 5381S2 7C281-45M C57402 7C40210M
5C16072OC 7C172A2OC 5C640735M 7C16235M 53RA1681AS 7C24535M- C57402A 7C40210M
5C160725C 7C172A25C 5C6407-45C 7C162-45C 53RA1681S 7C24545M- C67401A 7C40115C
5C160725M 7C172A25M 5C640745M 7C162-45M 53RA481AS 7C22535M C67401B 7C40325C

5C160735C 7C172A35C 5C64082OC 7C1852OC 53RA481S 7C225-40M C67402 7C402lOC
5C160735M 7C172A35M 5C640825C 7C18525C 53RS1681AS 7C24535M- C67402A 7C40215C
5C160745C 7C172A45C 5C640825M 7C18525M 53RS1681S 7C245-45M- C67402B 7C404-25C
5C160745M 7C172A45M 5C640835C 7C18535C 53RS881AS 7C235-40M- C67L401 7C4015C
5C16082OC 7C128A2OC 5C640835M 7C18535M 53RS881S 7C235-40M - C67L401D 7C40l15C
5Cl60825C 7C128A25C 5C640845C 7C18545C 53S1681 7C29250M C67L402D 7C402l5C

5Cl60825M 7C128A25M 5C6408-45M 7C18545M 53S1681AS 7C29135M PAL12L1OC PLDC20G 10-35C
5C160835C 7C128A35C 5C640855C 7C12855C 53Sl681S 7C29150M PAL12L10M PLDC2OG10-40M
5C160835M 7C128A35M 5C640855M 7C18555M 53S881 7C282-45M PAL14L8C PLDC20G 1O35C
5C1608-45C 7C128A45C 53S881A 7C282-45M PAL14L8M PLDC20G 1O4OM
5C160845M 7C128A45M MITSUBISHI CYPRESS 53S881AS 7C28145M PAL16L6C PLDC20G 1035C
5C160855C 7C128A55C PREFIX:M5M PREFIX:CY 53S881S 7C281-45M PAL16L6M PLDC20G 10-40M

5C160855M 7C128A55M SUFFIX:AP SUFFIX:L 57401 7C40110M PAL16L8A2C PALC16L835C
5C256125C 7C19725C SUFFIX:FP SUFFIX:F 57401A 7C40 1 10M PAL16L8A2M PALC16L8-40M
5C256l35C 7C19735C SUFFIX:K SUFFIX:D 57402 7C40210M PAL16L8A4C PALC16L8L35C
5C256135M 7C19735M SUFFIX:P SUFFIX:P 57402A 7C40210M PAL 16L8A-4M PALC16L84OM
5C256145C 7C197-45C 21C67P35 7C16735C 63811 7C282-45C PAL16L8AC PALC16L825C
5C2561-45M 7C197-45M 21C67P45 7C16745C 63812 7C282-45C PAL16L8AM PALC16L830M

5C640120C 7C1872OC 21C67P55 7C16745C 6381S1 7C281-45C PAL16L8B2C PALC16L825C
5C640125C 7C18725C 21C68P35 7C16835C 6381S2 7C28145C PAL 16L8B2M PALC16L830M
5C640125M 7C18725M 21C68P45 7C168-45C 63RA1681AS 7C24535C- PAL16L8B.4C PALC16L81-35C
5C640135C 7C18735C 21C68P55 7C168-45C 63RA1681S 7C24535C- PAL16L8B-4M PALC16L8-40M
5C640135M 7C18735M 5165L1oo 7C18655C+ 63RA481AS 7C22525C PAL16L8BM PALC16L820M
5C640145C 7C18745C 5165L120 7C18655C+ 63RA481S 7C2253OC PAL16L8C PALC16L835C

5C640145M 7C18745M 51651-70 7C18655C+ 63RS1681AS 7C24535C- PAL 16L8D-4C PALC16L8L25C
5C64042OC 7C1642OC 5165p1oo 7C18655C+ 63RS1681S 7C24535C- PAL16L8D-4M PALC16L830M
5C640425C 7C164-25C 5165P120 7C18655C+ 63RS881AS 7C23530C- PAL16L8M PALC16L8-40M
5C640425M 7C16425M 5165P70 7C18655C+ 63RS881S 7C2353OC- PAL16R4A2C PALC16R435C I
5C640435C 7C16435C 5178p45 7C18645C+ 63S1681 7C2925OC PAL16R4A2M PALC16R4-4OM
5C640435M 7C16435M 5178p55 7C18655C+ 63S1681A 7C29235C PAL16R4A4C PALC16R41-35C

5C640445C 7C164-45C 5187p25 7C18725C 63S1681AS 7C29135C PAL16R4A4M PALC16R4-4OM
5C640445M 7Cl6445M 5187p35 7C18735C 63S1681S 7C29150C PAL16R4AC PALC16R425C
5C64052OC 7C16620C 5187p45 7C18745C 63S881 7C28145C PAL16R4AM PALC16R4-30M
5C640525C 7C16625C 5187p55 7C187-45C 63S881 7C28245C PAL16R4B2C PALC16R4-25C
5C640525M 7C16625M 5188p25 7C164-25C 63S881A 7C28130C PAL16R4B2M PALC16R430M
5C640535C 7C16635C 5188p35 7C16435C 63S881A 7C2823OC PAL16R4B-4C PALC16R41-35C

5C640535M 7C16635M 5188p45 7C16445C 67401 7C4011OC PAL16R4B-4M PALC16R44OM
5C640545C 7C16645C 5188p55 7C16445C 67401A 7C40l15C PAL16R4BM PALC16R4-20M
5C640545M 7C16645M 6740lB 7C40325C PAL16R4C PALC16R4-35C
5C64062OC 7C1612OC MMI CYPRESS 67401D 7C40325C PAL16R4D4C PALC16R4L25C
5C6406-25C 7C16125C SUFFIX:883B SUFFIX:B 67402 7C4021OC PAL16R4M PALC16R44OM
5C640625M 7C16125M SUFFIX:F SUFFIX:F 67402A 7C40215C PAL16R6A2C PALC16R6-35C

5C640635C 7C16135C SUFFIX:] SUFFIX:D 67402B 7C40225C PAL16R6A2M PALC16R6-40M
5C640635M 7C16135M SUFFIX:L SUFFIX:L 67402D 7C404-25C PAL16R6A-4C PALC16R6L35C
5C6406-45C 7C16145C SUFFIX:N SUFFIX:P 67411 7C40325C PAL16R6A-4M PALC16R64OM
5C640645M 7C16145M SUFFIX:SHRP SUFFIX:B 67412 7C40225C PAL16R6AC PALC16R625C
5C64072OC 7C16220C 53811 7C282-45M 67L402 7C4021OC PAL16R6AM PALC16R630M
I
Note: Unless otherwIse noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
1-16
~~~OOUcrOR=====================================================================
MMI
PALl6R6B2C
PALl6R6B2M
PALl6R6B-4C
PALl6R6B-4M
PALl6R6BM
CYPRESS
PALCI6R625C
PALCI6R630M
PALCI6R6L35C
PALCI6R640M
PALCI6R620M
MMI
PAL20R8M
PALC22VlO/A
PLElOP8C
PLElOP8C
PLE10P8M
CYPRESS
PLDC20G lO40M
PALC22VI0-35C
7C2813OC
7C2823OC
7C28145M
MOTOROLA
201845
2167H35
2167H-45
2167H55
614755
CYPRESS
7C128-45C
7C16735C
7C167-45C
7C167-45C
7CI47-45C*
NATIONAL
PREFIX:NMC
SUFFIX:]
SUFFIX:N
1004221OC
1004225C
CYPRESS
PREFIX:CY
SUFFIX:D
SUFFIX:P
100E4227C
100E4225C

PALl6R6C PALCI6R635C PLElOP8M 7C282-45M 614770 7CI47-45C 100422A7C 100E4227C
PALl6R6D4C PALCI6R6L25C PLElOR8C 7C2353OC- 6164-45 7C18645C l00422AC 100E4227C
PALl6R6M PALCI6R6-40M PLElOR8M 7C23540M- 6164-55 7C18655C 100474A1OC l00E4747C
PALl6R8A2C PALCI6R835C PLE11P8C 7C29135C 6164-70 7C18655C 100474A8C 100E474-7C
PALl6R8A2M PALCI6R840M PLEIIP8M 7C29135M 616835 7CI6835C+ lO422lOC 1OE4227C
PALl6R8A4C PALCI6R8L35C PLE11RA8C 7C24535C- 616845 7CI68-45C+ 104225C 1OE4225C
PALl6R8A-4M PALCI6R8-40M PLE11RA8M 7C24535M- 616855 7CI68-45C+ 10422A7C 1OE4227C

PALl6R8AC PALCI6R825C PLE11RS8C 7C24535C- 616870 7CI6845C+ 10422AC 10E4227C
PALl6R8AM PALCI6R830M PLEI1RS8M 7C24535M - 61U755 7CI47-45C* 10474AlOC 1OE474-7C
PALl6R8B2C PALCI6R825C PLE9R8C 7C22530C 61U770 7CI47-45C* 10474A8C 1OE474-7C
PALl6R8B2M PALCI6R830M PLE9R8M 7C22535M 61L64-45 7C186-45C 12LlOC PLDC2OGlO35C
PAL 16R8B-4C PALCI6R8L35C 61L6455 7C18655C 14L8C PLDC20G 1O35C
PALl6R8B-4M PALCI6R8-40M MOSAIC CYPRESS 61L64-70 7C18655C 14L8M PLDC20GlO-40M

PALl6R8BM PALCI6R820M PREFIX:MS PREFIX:CYM 626825 7C16825C 16L6C PLDC20G 1O35C
PALl6R8C PALCI6R835C 8128SC100 1420HD85C 626835 7C16835C 16L6M PLDC20G lO40M
PAL 16R8D4C PALCI6R8L25C 8128SCl00 142IHD85C 626925 7C16925C 18UC PLDC20G 1035C
PALl6R8M PALCI6R8-40M 8128SC-45 1420HD45C 626935 7C16935C 18L4M PLDC20G lO40M
PALl8UC PLDC20G 1O35C 8128SC55 1420HD55C 627025 7C17025C 20L2M PLDC20GlO-40M
PALl8UM PLDC2OGIO-40M 8128SC70 1420HD7OC 627035 7C17035C 2147H 214755C

PAL20LlOAC PLDC2OG1035C 8128SC70 142IHD7OC 627045 7C17045C 2147H 214755M
PAL20LlOAM PLDC20G 1030M 628725 7C18725C 2147H1 214735C
PAL20LlOC PLDC20GlO35C MOSTEK CYPRESS 628735 7C18735C 2147H2 214745C
PAL20LlOM PLDC20G 10040M PREFIX:ET PREFIX:CY 6287-45 7C187-45C 2147H3 214755C
PAL20L2C PLDC20G 1O35C PREFIX:MK PREFIX:CY 628825C 7CI64-25C 2147H3 214755M
PAL20L2M PLDC20G lO40M PREFIX:TS PREFIX:CY 628835C 7CI6435C 2147H3L 7C147-45C

PAL20L8A2C PLDC20G 10-35C SUFFIX:N SUFFIX:P 628835M 7CI6435M 2148H 214855C
PAL20L8A2M PLDC20G IO-40M SUFFIX:P SUFFIX:D 628845M 7CI6445M 2148H2 214845C
PAL20L8AC PLDC20G 1O25C 4IH6725 7CI6725C+ 629025C 7C16625C 2148H3 214855C
PAL20L8AM PLDC20G 1O30M 4IH6735 7C16735+ 629035C 7C16635C 2148H3L 21U855C
PAL20L8C PLDC20G 10-35C 4IH6825 7CI6825C+ 629035M 7C16635M 2148HL 21U855C
PAL20L8M PLDC20G lO40M 4IH6835 7CI6835C+ 6290-45C 7C16645C 2901AIC 7C90131C

PAL20R4A2C PLDC20G 1O35C 4IH6925 7C16925 629045M 7C16645M 2901AIM 7C90132M
PAL20R4A2M PLDC20GlO-40M 4IH6935 7C16935C 62L8725 7C18725C 290 1A2C 7C90131C
PAL20R4AC PLDC2OGlO25C 41L6725 7CI6725C- 62L8735 7CI87~35C+ 290 1A2M 7C90132M
PAL20R4AM PLDC20G 1O30M 41L6735 7CI6735- 7681 7C28245C 2901AC 7C90131C
PAL20R4C PLDC20G 1O35C 41L6745 7CI6735- 7681A 7C282-45C 2901AM- 7C90132M
PAL20R4M PLDC20GlO40M 93422 93422C 2909AC 2909AC

PAL20R6A2C PLDC20GlO35C MOTOROLA CYPRESS 93422 93422M 2909AM 2909M
PAL20R6A2M PLDC20G lO-40M PREFIX:MCM PREFIX:CY 93422A 93422AC 2911AC 2911AC
PAL20R6AC PLDC20G 1O25C SUFFIX:P SUFFIX:P 93422A 93422AM 2911AM 2911M
PAL20R6AM PLDC20G 1O30M SUFFIX:S SUFFIX:D 93U22 93U22C 54S189 54S189M
PAL20R6C PLDC20G 1O35C SUFFIX:Z SUFFIX:L 93U22 93U22M 54S189A 7C18925M
PAL20R6M PLDC20G lO-40M 104221OC 1OE4227C 93U22A 93U22AC 74S189 74S189C

PAL20R8A2C PLDC20G 1O35C 142345 7CI6845C+ 93L422A 93U22AM 74S189A 27S03AC
PAL20R8A2M PLDC2OGIO40M 2016H45 6116-45C 75S07 7C19025M
PAL20R8AC PLDC20G 1O25C 2016H55 611655C NATIONAL CYPRESS 75S07A 27S07AM
PAL20R8AM PLDC20G 1O30M 2016H70 611655C PREFIX:DM PREFIX:CY 77LS181 7C28245M
PAL20R8C PLDC20G 1O35C 201835 7C12835C PREFIX:IDM PREFIX:CY 77S181 7C28245M
I
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on IcC and 5 rnA on ISB;
= meets all performance specs except 2V data retention-may not meet Icc or ISB ;
1-17
~~~~================================================================
NATIONAL CYPRESS NATIONAL CYPRESS NATIONAL CYPRESS NEC CYPRESS
77S181A 7C282-45M PALl6L8A2M PALC16L8-40M PAL20L8M PLDC20G l0-40M 4291 7C2925OC
77S191 7C29250M PALl6L8AC PALC16L825C PAL20R4AC PLDC20G 10-25C 4292 7C2925OC
77S191A 7C29250M PALl6L8AM PALC16L830M PAL20R4AM PLDC20G lO30M 4293 7C29235C
77S191B 7C29250M PALl6L8B2C PALC16L825C PAL20R4BC PLDC20G lO25C 4311-45 7C167-45C
77S281 7C281-45M PALl6L8B2M PALC16L830M PAL20R4BM PLDC20G 10-30M 431155 7C167-45C
77S281A 7C28145M PALl6L8B4C PALC16L8L35C PAL20R4C PLDC2OGlO35C 4361-40 7C18735C

77S291 7C29150M PALl6L8B4M PALC16L8-40M PAL20R4M PLDC20G lO-40M 4361-45 7C187-45C
77S291A 7C29150M PALl6L8BM PALC16L820M PAL20R6AC PLDC20G 10-25C 436155 7C18745C
77S291B 7C29150M PALl6L8C PALC16L835C PAL20R6AM PLDC20G lO30M 436170 7C18745C
77S401 7C401lOM PALl6L8M PALC16L8-40M PAL20R6BC PLDC20G 10-25C 4362-45 7Cl64-45C
77S401A 7C40110M PALl6R4A2C PALC16R4-35C PAL20R6BM PLDC2OG10-30M 436255 7Cl64-45C
77S402 7C402lOM PALl6R4A2M PALC16R440M PAL20R6C PLDC20G lO35C 436270 7Cl6445C

77S402A 7C402lOM PALl6R4AC PALC16R425C PAL20R6M PLDC20G lO-40M 436345 7C166-45C
77SR181 7C23540M PALl6R4AM PALC16R430M PAL20R8AC PLDC20G 10-25C 436355 7C166-45C
77SR25 7C225-40M PALl6R4B2C PALC16R4-25C PAL20R8AM PLDC20G 10-30M 436370 7C16645C
77SR25B 7C225-40M PALl6R4B2M PALCI 6R4-30M PAL20R8BC PLDC20G 1025C
77SR476 7C225-40M- PALl6R4B4C PALC16R4L35C PAL20R8BM PLDC20G 1030M RAYTHEON CYPRESS
77SR476B 7C22540M- PALl6R4B4M PALC16R4-40M PAL20R8C PLDC20G 10-35C PREFIX:R PREFIX:CY

85S07 27S07C PALl6R4BM PALC16R4-20M PAL20R8M PLDC20G 1O-40M SUFFIX:B SUFFIX:B
85S07A 27S07AC PALl6R4C PALC16R435C SUFFIX:D SUFFIX:D
85S07A 7C128-45C+ PALl6R4M PALC16R4-40M NEC CYPRESS SUFFIX:F SUFFIX:F
87LS181 7C282-45C PAL16R6A2C PALC16R635C PREFIX:uPD PREFIX:CY SUFFIX:L SUFFIX:L
87S181 7C282-45C PALl6R6A2M PALC16R640M SUFFIX:C SUFFIX:P SUFFIX:S SUFFIX:S
87S191 7C2925OC PALl6R6AC PALC16R625C SUFFIX:D SUFFIX:D 29631AC 7C28245C

87S191A 7C29235C PALl6R6AM PALC16R6-30M SUFFIX:K SUFFIX:L 29631AM 7C28245M
87S191B 7C29235C PALl6R6B2C PALC16R6-25C SUFFIX:L SUFFIX:F 29631ASC 7C28145C
87S281 7C281-45C PALl6R6B2M PALCI 6R630M l00422lOC lOOE4227C 2963lASM 7C281-45M
87S281A 7C281-45C PALl6R6B4C PALC16R6L35C 1004225C 100E4225C 29631C 7C28245C
87S291 7C2915OC PALl6R6B4M PALC16R6-40M 1004227C 100E4227C 29631M 7C28245M
87S291A 7C29135C PALl6R6BM PALCI6R6-20M 100474lOC IOOE474-7C 29631SC 7C28145C

87S291B 7C29135C PALl6R6C PALC16R635C 100474-3C IOOE474-3C 29631SM 7C281-45M
87S401 7C40IIOC PALl6R6M PALCI6R6-40M 1004744.5C IOOE4743C 29633AC 7C28245C+
87S40IA 7C40I15C PAL I6R8A2C PALCI6R835C l004746C lOOE4745C 29633AM 7C28245M+
87S402 7C4021OC PALl6R8A2M PALCI6R840M l004748C lOOE4747C 29633ASC 7C28145C+
87S402A 7C40215C PALl6R8AC PALC16R825C lO422lOC lOE4227C 29633ASM 7C28145M+
87SR181 7C2353OC PALl6R8AM PALC16R830M 104225C lOE4225C 29633C 7C28245C+

87SR25 7C225-4OC PALl6R8B2C PALC16R825C 104227C lOE4227C 29633M 7C28245M+
87SR25B 7C2253OC PALl6R8B2M PALC16R830M 10474-lOC lOE4747C 29633SC 7C28145C+
87SR476 7C225-4OC- PAL16R8B4C PALC16R8L35C 10474-3C lOE4743C 29633SM 7C281-45M +
87SR476B 7C2253OC- PALl6R8B4M PALC16R840M 104744.5C lOE4743C 29681AC 7C29250C
PALlOO16P4-2.5 100E3022.5C PALl6R8BM PALC16R820M 104746C 10E474-5C 29681AM 7C29250M
PALlOO16P4-4C 100E302-4C PALl6R8C PALC16R835C 10474-8C 10E4747C 29681ASC 7C2915OC

PAL10016P4-6C 100E3026C PALl6R8M PALC16R840M 21472 214755C 29681ASM 7C29150M
PALlOO16P83C 100E3013C PAL20LlOB2C PLDC20G lO25C 21473 214755C 29681C 7C29250C
PALlOO16P8-4C 100E301-4C PAL20LlOB2M PLDC20G 10-30M 2147A25 7C14725C 29681M 7C29250M
PALl(X)16P86C 100E3016C PAL20LlOC PLDC20G 10-35C 2147A35 214735C 29681SC 7C29150C
PALlO16P4-2.5C lOE3022.5C PAL20LlOM PLDC20G 1040M 2147A-45 214745C 29681SM 7C29150M
PALl016P4-4C lOE302-4C PAL20L2C PLDC2OGlO35C 2149 214955C 29683AC 7C2925OC+

PALl016P4-6C 10E3026C PAL20L8AC PLDC20G 10-25C 21491 2149-45C 29683AM 7C29250M+
PALlO16P83C lOE3013C PAL20L8AM PLDC20G lO30M 21492 214935C 29683ASC 7C29150C+
PALlO16P8-4C lOE301-4C PAL20L8BC PLDC20G 1025C 21672 7C16745C 29683ASM 7C29150M+
PALlO16P86C lOE3016C PAL20L8BM PLDC20G lO30M 21673 7C16745C 29683C 7C2925OC+
PALl6L8A2C PALC16L835C PAL20L8C PLDC20G lO35C 429 7C2925OC 29683M 7C29250M+
Note: Unless otherwise noted, product meets all performance specs and IS wlthm 10 rnA on Icc and 5 rnA on ISB ;
= meets all performance specs except 2V data retention-may not meet Icc or ISB ;
1-18
~~~ucr~==================================================================
RAYTHEON CYPRESS TI CYPRESS TI CYPRESS TOSHIBA CYPRESS
29683SC 7C291-5OC+ PREFIX:TBP PREFIX:CY HCT9510E 7C51O-75C+ PREFlX:P SUFFIX:P
29683SM 7C291-50M+ PREFIX:TIB PREFIX:CY HCT9510E-1O 7C51O-75C+ PREFIX:TMM PREFIX:CY
29VP864DB 7C264-55M SUFFIX:F SUFFIX:F HCT9510M 7C510-75M + SUFFIX:D SUFFIX:D
29VP864SB 7C263-55M SUFFIX:J SUFFIX:L PALl6L8-20M PALCI6L8-20M 2015A-1O 7CI28-55C+
29VS864SB 7C261-55M SUFFIX:N SUFFIX:D PALl6L8-25C PALCI6L8-25C 2015A-12 7CI28-55C+
39VP864D 7C264-55C l0016P8-3C l00E301-3C PALl6L8-30M PALCI6L8-30M 2015A-15 7CI28-55C+

39VP864S 7C263-55C l0016P8-4C l00E301-4C PALl6L8A-2C PALCI6L8-35C 2015A-90 7CI28-55C+
39VS864S 7C261-S5C l0016P8-6C l00E301-6C PAL 16L8A-2M PALCI6L8-40M 2018-25 7C128-25C
1OH16P8-3C 1OE301-3C PALl6L8AC PALCI6L8-25C 2018-35 7C128-35C
SIGNETICS CYPRESS 1OHI6P8-4C 1OE301-4C PALl6L8AM PALCI6L8-30M 2018-45 7C128-45C
PREFIX:N PREFIX:CY 10H16P8-6C 1OE301-6C PALl6R4-20M PALCI6R4-20M 2018-55 7CI28-55C+
PREFIX:S PREFIX:CY 22V1OAC PALC22V1O-25C PALl6R4-25C PALCI6R4-25C 2068-25 7C168-25C

SUFFIX:883B SUFFIX:B 22V1OAM PALC22VI0-30M PALl6R4-30M PALCI6R4-30M 2068-35 7C168-35C
SUFFIX:F SUFFIX:D 27C291-3 7C291L-35C+ PALl6R4A-2C PALCI6R4-25C 2068-45 7C168-45C
SUFFIX:G SUFFIX:L 27C291-30 7C291L-35C+ PAL 16R4A-2M PALCI6R4-40M 2068-55 7C168-45C
SUFFIX:N SUFFIX:P 27C291-S 7C291L-5OC + PALl6R4AC PALCI6R4-25C 2069-35 7C169-35C
SUFFlX:R SUFFIX:F 27C291-50 7C291L-50C + PALl6R4AM PALCI6R4-30M 2078-35 7C170-35C
l00422BC l00E422-7C 27C292-3 7C292L-35C + PAL 16R6-20M PALCI6R6-20M 2078-45 7C170-45C

l00422CC l00E422-7C 27C292-35 7C292L-35C + PALI6R6-25C PALCI6R6-25C 2078-55 7C170-45C
l00474AC l00E474-7C 27C292-5 7C292L-5OC + PALl6R6-30M PALCI6R6-30M 2088-35 7C186-35C
10422BC 1OE422-7C 27C292-50 7C292L-50C + PALl6R6A-2C PALCI6R6-25C 2088-45 7C186-45C
10422CC 1OE422-7C 28L166W 7C292-5OC PALl6R6A-2M PALCI6R6-40M 2088-55 7C186-55C
10474AC 1OE474-7C 28L86AMW 7C282-45M PALl6R6AC PALCI6R6-25C 315 2147-55C
N74S189 74S189C 28L86AW 7C282-45C PALl6R6AM PALCI6R6-30M 315-1 2147-55C

N82HS641 7C264-55C 28S166W 7C292-50C PALl6R8-20M PALCI6R8-20M 55416-35 7CI64-35C
N82HS641A 7C264-45C 28S86AMW 7C282-45M PALl6R8-25C PALCI6R8-25C 55416-45 7CI64-45C
N82HS641B 7C264-35C 28S86AW 7C282-4SC PALl6R8-30M PALCI6R8-30M SS417-2S 7C166-2SC
N82LS181 7C282-4SC 38Ll6S-35C 7C291-35C PALl6R8A-2C PALCI6R8-2SC 55417-35 7C166-35C
N82S181 7C282-45C 38Ll6S-4SC 7C291-35C PALl6R8A-2M PALCI6R8-40M SS417-45 7C166-45C
N82S181A 7C282-45C 38Ll66-35 7C292-35C PALl6R8AC PALCI6R8-25C 5561-45 7CI87-45C+

N82S181B 7C282-4SC 38Ll66-45 7C292-35C PALl6R8AM PALCI6R8-30M 5561-55 7CI87-45C+
N82S191A-3 7C291-5OC 38L8S-45C 7C281-45C PAL20L1OA-2C PLDC20G 1O-25C 5561-70 7CI87-45C+
N82S191A-6 7C292-5OC 38R165-18C 7C245-25C PAL20L1OA-2M PLDC20G 1O-30M 5562-35 7C187-35C
N82S191B-3 7C291-35C 38R16S-25C 7C245-35C PAL20LlOAC PLDC20G 10-35C 5562-45 7C187-45C
N82S191B-6 7C292-35C 38R85-15C 7C235-30C PAL20LlOAM PLDC20G 1O-30M 5562-55 7C187-45C
N82S191-3 7C291-5OC 38S165-25C 7C291A-2SC PAL20L8A-2C PLDC20GlO-25C

N82S191-6 7C292-5OC 38S165-3SC 7C291-35C PAL20L8A-2M PLDC20G 1O-30M TRW CYPRESS
S54S189 54S189M 38S85-3OC 7C281-30C PAL20L8AC PLDC20G10-25C MPY016HA 7C516-75M
S82HS641 7C264-55M 54HC189 7C189-25M PAL20L8AM PLDC20G 1O-30M MPY016HC 7C516-75C
S82LS181 7C282-45M 54HCT189 7C189-25M PAL20R4A-2C PLDC2OG1O-25C MPY016KA 7C516-75M
: S82S181 7C282-45M 54LS189A 27LS03M PAL20R4A-2M PLDC20G1O-30M MPY016KC 7C516-75C
S82S181A 7C282-45M 54LS219A 7CI90-25M+ PAL20R4AC PLDC20G 10-25C TDC 10 10A 7C51O-75M
S82S191A-3 7C291-50M 54S189A 54S189M PAL20R4AM PLDC20GlO-30M TDC1010C 7CS10-75C
S82S191A-6 7C292-50M 7489 7C189-2SC PAL20R6A-2C PLDC20G 1O-25C TMC2010A 7CS1O-75M +
S82S191B-3 7C291-S0M 74ACT29116 7C9116AC PAL20R6A-2M PLDC20G 1O-30M TMC2010C 7C51O-7SC+
S82S191B-6 7C292-S0M 74ACT29116-1 7C9116AC PAL20R6AC PLDC20G 1O-25C TMC2110A 7C51O-75M
S82S191-3 7C291-50M 74HC189 7C189-25C PAL20R6AM PLDC20G 1O-30M TMC2110C 7C51O-75C
I
I
S82S191-6 7C292-50M 74HC219 7C190-25C PAL20R8A-2C PLDC20G 1O-25C TMC216HA 7C516-75M
74HCT189 7C189-25C PAL20R8A-2M PLDC20G 10-30M TMC216HC 7C516-75C+
TI CYPRESS 74LS189A 27LS03C PAL20R8AC PLDC20G 1O-25C
PREFIX:JBP PREFIX:CY 74LS219A 27S07C+ PAL20R8AM PLDC2OG10-30M VTI CYPRESS
PREFIX:PAL SUFFIX:P 74S189A 74S189C 2OC18-25 7CI28-25C+
PREFIX:SN PREFIX:CY 74S189B 7C189-25C 20C18-35 7CI28-35C+
I Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;
+= meets all performance specs but may not meet Icc or ISB ;
1-19
~~~U~================================================================
VTI CYPRESS WSI CYPRESS WEITEK CYPRESS
20C1925 7C12825C 57C19155 7C2925OC 2517C 7C51775C
2OC1935 7C12835C 57C19155M 7C29250M 2517M 7C51775M+
2OC6825 7CI6825C+ 57C19170 7C2925OC
2OC6835 7CI6835C+ 57C19170M 7C29250M
2OC6925 7C16925C 57C291-40 7C29135C
2OC6935 7C16935C 57C29155 7C2915OC

2OC6945 7C169-45C 57C29155M 7C29150M
2OC7825 7C170-25C+ 57C29170 7C2915OC
2OC7835 7C170-35C+ 57C29170M 7C29150M
2OC78-45 7CI70-45C+ 57C4955 7C26455C+
2OC7925 7C17025C 57C4955M 7C264-55M
2OC7935 7C170-35C 57C4970 7C264-55C+

2OC79-45 7C170-45C 57C4970M 7C264-55M
2OC9835 7CI8535C+ 57C499Q 7C26455C+
20C98-45 7CI85-45C+ 57C4990M 7C264-55M
2OC9935 7C18535C 59016C 7C9101-4OC
2OC99-45 7C185-45C 59016C 7C9101-45M
2130-1OC 7C130-55C 5901C 2901CC+

2130-12C 7C130-55C 5901M 2901CM+
2130-15C 7C130-55C 5910AC 7C910-40C
713255 7CI3255C 5910AM 7C910-46M
713270 7CI3255C 59516 7C516-45C
7132A35 7C13235C 59517 7C517-45C
7132A-45 7CI32-45C
714255 7C14255C WEITEK CYPRESS
714270 7C14255C 1010AC 7C510-75C
7142A35 7C14235C 1010AM 7C510-75M
7142A-45 7C142-45C 1010BC 7C510-75C
7C12215 7C12215C 1010BM 7C510-75M
7C12225 7C12225C 1010C 7C510-75C

7C12235 7C12235C 10 10M 7C510-75M
VL2010-65 7C510-65C 1516AC 7C51675C
VL2010-70 7C51O65C 1516AM 7C51675M
VL201090 7C510-75C 1516BC 7C51655C
VT64KS4-35 7CI64-35C 1516BM 7C51675M
VT64KS4-45 7CI64-45C 1516C 7C51675C

VT64KS4-55 7CI64-45C 1516M 7C51675M
VT65KS4-35 7C16635C 20lOAC 7C51O55C
VT65KS4-45 7C166-45C 20 lOAM 7C51075M
VT65KS4-55 7C166-45C 2010BC 7C510-45C
2010BM 7C510-55M
WSI CYPRESS 2010C 7C510-75C I
PREFIX:WS PREFIX:CY 2010DC 7C510-55C

SUFFIX:C PREFIX:CY 20lODM 7C51075M
I
SUFFIX:D PREFIX:CY 20 10M 7C510-75M + I
SUFFIX:M SUFFIX:P 2516AC 7C51655C
I
SUFFIX:P PREFIX:CY 2516AM 7C516-75M i
29C01C 7C90131C 2516C 7C51675C I

57C128F70 7C25155C 2516DC 7C516-45C
I
57C128F70M 7C25155M+ 2516DM 7C516-55M
57C128F90 7C25155C 2516M 7C516-75M+
57C128F90M 7C25155M+ 2517AC 7C51755C
57C191-40 7C29235C 2517AM 7C51775M
Note: Unless otherwise noted, product meets all performance specs and is within 10 mA on Icc and 5 mA on ISB ;
1-20
PRODUCT~~~~~~~~~~~~
e;,r INFORMATION
STATIC RAMS ~~~~~~~~~~~
PROMS~:~~~~~
PLD TOOLKIT :~~~~~~::RII
QUALITY AND ~==:==:==:==:==:~==:~.

RELIABILITY
APPLICATION BRIEFS
PACKAGES 3,.
~ Section Contents
~~~ooucr~================================================================
Static RAMs (Random Access Memory)
CY2147 4096 x 1 Static RAM ...................................................... 2-1
CY2148 1024 x 4 Static RAM ...................................................... 2-6
CY2149 1024 x 4 Static RAM ...................................................... 2-6
CY6116 2048 x 8 Static RAM ..................................................... 2-12
CY6117 2048 x 8 Static RAM .......................................... , .......... 2-12
CY6116A 2048 x 8 Static RAM ..................................................... 2-19
CY6117A 2048 x 8 Static RAM ..................................................... 2-19
CY7C128 2048 x 8 Static RAM ..................................................... 2-40
CY7C128A 2048 x 8 Static RAM ..................................................... 2-47
CY7C147 4096 x 1 Static RAM ..................................................... 2-76
CY7C148 1024 x 4 Static RAM ..................................................... 2-83
CY7C149 1024 x 4 Static RAM ..................................................... 2-83
CY7C157 16,384 x 16 Static Cache RAM ............................ , .................. 2-98
CY7C164-1O 16,384 x 4 Static RAM .................................. , ................. 2-117
CY7C166-1O 16,384 x 4 Static RAM .................................................... 2-117
CY7C164-20 16,384x4StaticRAM .................................................... 2-123
CY7C166-20 16,384 x 4 Static RAM with Output Enable ................................... 2-123
CY7C167 16,384 x 1 Static RAM .................................................... 2-131
CY7C167A 16,384 x 1 Static RAM .......................................... , ......... 2-138
CY7C168 4096 x 4 Static RAM .................................................... 2-145
CY7C169 4096 x 4 Static RAM .................................. , ....... , ......... 2-145
CY7C168A 4096 x 4 Static RAM .................................................... 2-152
CY7C169A 4096 x 4 Static RAM .................................................... 2-152
:::;Y7C170 4096 x 4 Static RAM with Output Enable ................................... 2-159
2Y7C170A 4096 x 4 Static RAM with Output Enable ................................... 2-165
2Y7C171 4096 x 4 Static RAM Separate I/O ......................................... 2-171
2Y7C172 4096 x 4 Static RAM Separate I/O ......................................... 2-171
:Y7C171A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
::;Y7C172A 4096 x 4 Static RAM Separate I/O ......................................... 2-178
::;Y7C183 2 x 4096 x 16 Cache RAM ...................... , ....... , ....... , ......... 2-185
:Y7C184 2 x 4096 x 16 Cache RAM .............. , ................................. 2-185
:;Y7C185-12 8192 x 8 Static RAM .................................................... 2-193
:;Y7C186-12 8192 x 8 Static RAM .................................. , ....... , ......... 2-193
:;Y7C185-20 8192 x 8 Static RAM .................................................... 2-199
:;Y7C186-20 8192 x 8 Static RAM .......................... , ............... , ......... 2-199
:;Y7C187 65,536 x 1 Static RAM .................................................... 2-207
:;Y7C189 16 x 4 Static RAM .................................................... 2-215
~Y7C190 16 x 4 Static RAM .................................................... 2-215
~Y7C191 65,536 x 4 Static RAM Separate I/O ......................................... 2-222
~Y7C192 65,536 x 4 Static RAM Separate I/O ......................................... 2-222
~Y7C194 65,536 x 4 Static RAM .................................................... 2-228
:;Y7C196 65,536 x 4 Static RAM with Output Enable ................................... 2-228
~ Section Contents (Continued)
~~~~UaoR================================================================
Static RAMs (Random Access Memory) (Continued)
CY7C197 262,144 x 1 Static RAM .................................................... 2-234
CY7C198 32,768 x 8 Static RAM .................................................... 2-240
CY7C199 32,768 x 8 Static RAM .. '" ..... " ..................................... " .2-240
CY74S189 16 x 4 Static RAM .................................................... 2-246
CY27LS03 16 x 4 Static RAM .. " ................................................ 2-246
CY27S03 16 x 4 Static RAM .................................................... 2-246
CY27S07 16 x 4 Static RAM .................................................... 2-246
CY93422A 256 x 4 Static RAM Separate I/O ......................................... 2-252
CY93L422A 256 x 4 Static RAM Separate I/O ......................................... 2-252
CY93422 256 x 4 Static RAM Separate I/O ......................................... 2-252
CY93L422 256 x 4 Static RAM Separate I/O ......................................... 2-252
CYM1461 512K x 8 Static RAM Module ... '" ....................................... 2-282
CYM1641 256K x 16 Static RAM Module .................................. " ...... " .2-324
CYMI804 lK x 32 Static RAM Module Separate I/O ............................... " .2-330
CYM1821 16K x 32 Static RAM Module ................................. '" ......... 2-331
CYM1822 16K x 32 Static RAM Module Separate I/O .................................. 2-337
CYM1830 64K x 32 Static RAM Module ... " ..................................... " .2-343
CY2147
CYPRESS
SEMICONDUCTOR 4096 x 1 Static R/W RAM
Features Functional Description
Automatic power-down when The CY2147 is a high performance Reading the device is accomplished by
deselected CMOS static RAM organized as taking the chip enable (CE) LOW,
4096 x 1 bit. Easy memory expansion is while write enable (WE) remains
CMOS for optimum
speed/power provided by an active LOW chip en- HIGH. Under these conditions the
able (CE) and three-state drivers. The contents of the memory location speci-
High speed CY2147 has an automatic power-down fied on the address pins will appear on
-35 ns feature, reducing the power consump- the data output (DO) pin.
Low active power tion by 80% when deselected. The output pin stays in high impedance
- 690 mW (commercial) Writing to the device is accomplished state when chip enable (CE) is HIGH
- 770 mW (military) when the chip enable (CE) and write or write enable (WE) is LOW.
Low standby power enable (WE) inputs are both LOW.
-140 mW Data on the input pin (DI) is written
into the memory location specified on
TTL compatible inputs and the address pins (Ao through All).
outputs
Capable of withstanding greater
than 2000V electrostatic
discharge
Logic Block Diagram Pin Configuration

,...---------c ...- - - - - 0 1 Ao Vee
Al A6
A2 A7
A3 As
A4 Ag
As AlO
DO All
WE 01
I---+----f >---- DO
GND EE
0013-2
WE
0013-1
Selection Guide (For higher performance and lower power refer to CY7C147 data sheet.)
2147-35 2147-45 2147-55
Maximum Access Time (ns) 35 45 55
Maximum Operating Commercial 125 125 125
Current (rnA) Military 140 140
Maximum Standby Commercial 25 25 25
2-1
~ CY2147
~~~U~R==================================================================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ......... " ...... " .. >2OO1V
Ambient Temperature with (Per MIL-STD-883 Method 3015)
Power Applied .................... - 55C to + 125C LatchupCurrent .......................... > 200 mA
Supply Voltage to Ground Potential
(Pin 18 to Pin 9) ...... " ............. -0.5V to +7.0V Operating Range
DC Voltage Applied to Outputs Ambient
in High Z State ...................... - 0.5V to + 7.0V Range Vee
Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial QOC to +70C 5V 1O%
Output Current into Outputs (Low) ............. 20 mA Military[S] - 55C to + 125C 5V 1O%
Electrical Characteristics Over Operating Range[4]

Parameters Description Test Conditions Min. Max. Units
VOH Output HIGH Voltage Vee = Min.,loH = -4.0mA 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 12.0 rnA 0.4 V
VIH Input HIGH Voltage 2.0 Vee V
VIL Input LOW Voltage -3.0 0.8 V
IIX Input Load Current GND::;: VI::;: Vee -10 +10 ,..,A
GND::;: Vo::;: Vee
loz Output Leakage Current -50 +50 ,..,A
Output Disabled
Output Short Circuit
los Vee = Max., VOUT = GND -350 rnA
Current [1]
Vee Operating Supply Vee = Max. Commercial 125
lee rnA
Current lOUT = OmA Military 140
Automatic CE[2] Max. Vee, Commercial 25
ISB rnA
Power Down Current CE ~ VIH Military 2S
Capacitance [3]
Parameters Description Test Conditions Max. Units
CIN Input Capacitance TA = 2SC,f= 1 MHz 5
pF
Output Capacitance Vee = 5.0V 6
COUT
Notes:
1. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may
2. A pull-up resistor to Vee on the CE input is required to keep the affect these parameters.
device deselected during Vee power-up, otherwise ISB will exceed 4. See the last page of this specification for Group A subgroup testing
values given. information.
5. TA is the "instant on" case temperature.
AC Test Loads and Waveforms

R13291! R1329H
5Vo-------~~~ 5Vo-------~~_,
OUTPUT 0 - - - - -......-------4 OUTPUT 0-----.....- - - -....... INPUT PULSES
R2 R2 3.0 V -------:::i:-:~--~'-
5 pF
'NCLUO'NGI30 pF 202Sl 202 n
JIG AND ,NCLUD,Nl
SCOPE JIG AND GND-----""r-
SCOPE ~
0013-3 0013-4
Figure la Figure Ib Figure 2
Equivalent to:
THEVENIN EQUIVALENT
125Sl
OUTPUT~1.90V
0013-5
2-2
~ CY2147
~~~UcrOR =====================================================================
Switching Characteristics Over Operating Range[4, 6]
2147-35 2147-45 2147-55
Parameters Description Units
Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 35 45 55 ns
tAA Address to Data Valid 35 45 55 ns
tOHA Data Hold from Address Change 5 5 5 ns
tACE CE LOW to Data Valid 35 45 55 ns
tLZCE CE LOW to Low Z[S] 5 5 5 ns
tHZCE CE HIGH to High Z[7, S] 30 30 30 ns
tpu CE LOW to Power Up 0 0 0 ns
tpo CE HIGH to Power Down 20 20 20 ns
WRITE CYCLE[9]
twc Write Cycle Time 35 45 55 ns
tscE CE LOW to Write End 35 45 45 ns
tAW Address Set-up to Write End 35 45 45 ns
tHA Address Hold from Write End 0 0 10 ns
tSA Address Set-up to Write Start 0 0 0 ns
tpwE WE Pulse Width 20 25 25 ns
tso Data Set-up to Write End 20 25 25 ns
tHO Data Hold from Write End 10 10 10 ns
tLZWE WE HIGH to Low Z[S] 0 0 0 ns
tHZWE WE LOW to High Z[7, S] 0 20 0 25 0 25 ns
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing 9. The internal write time of the memory is defined by the overlap of
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CE LOW and WE LOW. Both signals must be LOW to initiate a
loading of the specified lor/loH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
7. tHZCE and tHzwE are tested with CL = 5 pF as in Figure lb. Tran- data input setup and hold timing should be referenced to the rising
sition is measured 500 m V from steady state voltage. edge of the signal that terminates the write.
S. At any given temperature and voltage condition, tHZ is less than tLZ 10. WE is HIGH for read cycle.
for all devices. 11. Device is continuously selected, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
Switching Waveforms
Read Cycle No.1 (Notes 10, 11)
""r,:=------------t ------------1.j .
'OO"~~--tAA_-"
DATA OUT
~HA~
PREVIOUS DATA VALlO

Rc
-*-
________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _D_AT_A_V_A_L_ID______________
0013-6

tRC
Jr- ....,'"
tACE
DATA OUT
t
LZCE
HIGH IMPEDANCE
:-1 II I I IL
DATA VALID
_tHZCE1
,
HIGH
IMPEDANCE
1
I~~~~~
~'~
I---tpu -tPD
VCC _ _ _ _ _
SUPPLY 50% 50%
CURRENT _ 158
0013-7
2-3
~ CY2147
~~~NDUcroR ==================================================================
Switching Waveforms (Continued)
Write Cycle No.1 (WE Controlled) (Note 9)
J------------.wc-------------i
ADDRESS
DATA IN
DATA OUT DATA UNDEFINED
0013-8
Write Cycle No.2 (CE Controlled) (Note 9)
J-------------~c-----------~
ADDRESS
.$0----+0>-
DATA IN DATA-IN VALID
tHZWE~
--------------~
DATA OUT DATA UNDEFINED J)------------------ HIGH IMPEDANCE
0013-9
Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
Speed Package Operating
(ns) Ordering Code
Type Range
35 CY2147-35 PC P3 Commercial
CY2147-35 DC D4
CY2147-45 DC D4
CY2147-45 DMB D4 Military
CY2147-55 DC D4
CY2147-55 DMB D4 Military
2-4
~ CY2147
~~~~UcrOR==============================================================
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vm
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB 1,2,3
Switching Characteristics
Parameters Subgroups
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAw 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #: 38-00023-B
2-5
CY2148/CY21L48
CY2149/CY21L49
CYPRESS
SEMICONDUCTOR 1024 X 4 Static R/W RAM
Automated power-down when The CY2148 and CY2149 are high per- select (CS) and write enable (WE) in-
deselected (2148) formance CMOS static RAMs orga- puts are both LOW, data on the four
nized as 1024 x 4 bits. Easy memory data input/output pins (1/00 through
CMOS for optimum speed/
power expansion is provided by an active 1/03) is written into the memory loca-
LOW chip select (CS) input, and three- tion addressed by the address present
Low power state outputs. The CY2148 and on the address pins (Ao through A9)'
- 660 mW (commercial) CY2149 are identical except that the
- 770 mW (military) Reading the device is accomplished by
CY2148 includes an automatic (CS) selecting the device, (CS) active LOW,
5 volt power supply 10% power-down feature. The CY2148 re- while (WE) remains inactive or HIGH.
tolerance both commercial and mains in a low power mode as long as Under these conditions, the contents of
military the device remains unselected, i.e. (CS) the location addressed by the informa-
is HIGH, thus reducing the average tion on address pins (Ao through A9) is
TIL compatible inputs and power requirements of the device. The
outputs present on the four data input/output
chip select (CS) of the CY2149 does pins (1/00 through 1/03).
not affect the power dissipation of the
device. The input/output pins (1/00 through
1/03) remain in a high impedance state
An active LOW write enable signal unless the chip is selected, and write
(WE) controls the writing/reading op- enable (WE) is high.
eration of the memory. When the chip
STORAGE MATRIX A6 vee

A5 A7
A4 As
A3 Ag
Ao 1/00
A, I/O,
A2 1/02
CS 1/03
GND WE
Vss
cs---..&.....--.. 0015-2
DATA BUFFERS
WE------..
Vcc_
Vss- 1/00 1/01 1/0 3
0015-1
Selection Guide (For Higher Performance and Lower Power Refer to CY7C148/9 Data Sheet)
2148/9-35 21L48/9-35 2148/9-45 21L48/9-45 2148/9-55 21L48/9-55
Maximum Access Time (ns) 35 35 45 45 55 55
Maximum Operating I Commercial 140 120 140 120 140 120
Current (rnA) 1 Military 140 140
2-6
CY2148/CY21L48
fill .
Maximum Ratings
~UcrOR==================================================================
CY2149/CY21L49
Storage Temperature ............... - 65C to + 150C DC Input Voltage ................... - 3.0V to + 7.0V
Ambient Temperature with
Power Applied .................... - 55C to + 125C
Output Current into Outputs (Low) ............. 20 rnA
Operating Range EI
(Pin 18 to Pin 9) ..................... -0.5V to + 7.0V Range
Ambient
Temperature Vee
DC Voltage Applied to Outputs
in High Z State ....... , .............. -0.5V to + 7.0V Commercial OCto + 70C 5V 10%
Military [11] - 55C to + 125C 5V + 10%
21L48/9 2148/9
Parameters Description T~st Conditions Units
Min. Max. Min. Max.
IOH Output HIGH Current VOH = 2.4V Vee = 4.5V -4 -4 rnA
TA = 70C 8 8
IOL Output LOW Current VOL = O.4V rnA
TA = 125C 8
VIH Input HIGH Voltage 2.0 6.0 2.0 6.0 V
VIL Input LOW Voltage -3.0 0.8 -3.0 0.8 V
IIX Input Load Current Vss ~ VI ~ Vee -10 10 -10 10 p,A
Output Leakage GND ~ Vo ~ Vee -50 -50
loz Current Output Disabled TA= - 55C to + 125C 50 50 p,A
CI Input Capacitance[13] 5 5
Test Frequency = 1.0 MHz pF
Input/Output TA = 25C,AllPinsatOV, Vee = 5V 7
CliO Capacitancd 13] 7
Vee Operating Max. Vee, CS ~ VIL TA = OC to + 70C 120 140
Icc rnA
Supply Current Output Open TA = - 55C to + 125C 140
Automatic CS Max. Vee, 2148 TA = OCto +70C 20 30 rnA
ISB Power Down Current CS;;:: VIH only TA = -55Cto + 125C 30
Peak Power-On Max. Vee, 2148 TA = OCto + 70C 30 50
Ipo CS;;:: VIH[3] rnA
Current only TA = - 55C to + 125C 50
Output Short GND ~ Vo ~ Vee[lO] TA = OCto +70C 275 275
lOS rnA
Circuit Current TA = - 55C to + 125C +350
Notes:
1. Test conditions assume signal transition times of 10 ns or less, timing 6. At any given temperature and voltage condition, tHZ is less than tLZ
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output for all devices. Transition is measured 500 mV from steady state
loading of the specified IorJIOH and 30 pF load capacitance. Output voltage with specified loading in Figure 1h.
timing reference is 1.5V. 7. WE is HIGH for read cycle.
2. The internal write time of the memory is defined by the overlap of 8. Device is continuously selected, CS = VIL.
es LOW and WE LOW. Both signals must be LOW to initiate a 9. Address valid prior to or coincident with es transition LOW.
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising 10. For test purposes, not more than one output at a time should be
edge of the signal that terminates the write. shorted. Short circuit test duration should not exceed 30 seconds.
3. A pull up resistor to Vee on the es input is required to keep the 11. T A is the "instant on" case temperature.
device deselected during Vee power up. Otherwise current will ex- 12. See the last page of this specification for Group A subgroup testing
ceed values given (eY2148 only). information.
4. Chip deselected greater than 55 ns prior to selection. 13. Tested initially and after any design or process changes that may
5. ehip deselected less than 55 ns prior to selection. affect these parameters.

Rl48Hl Rl48Hl
ALL INPUT PULSES
5Vo----JV'\,..,......, 5VO----""',..,........,
OUTPUTo---.----i OUTPUT 0--_---.... 3.0 V - - - - - ) - - - - -...
30 pF R2 5 pF R2
I
_
INCLUDING
JIG AND _
- SCOPE -
255n
I INCLUDING
_JIG AND
- SCOPE
_
-
255n
GND
10 ns 10 ns
0015-3 0015-5
Equivalent to:
THEVINEN EQUIVALENT
167!l
OUTPUT O---~VI'llo"I'110.----O 1.73V 0015-4
2-7
CY2148/CY21L48
(in
. CY2149/CY21L49
~ucr~==================================================================
Switching Characteristics [12]
2148/9-35 2148/9-45 2148/9-55
Min. Max. Min. Max. Min. Max. I
READ CYCLE
Address Valid to Address Do Not
tRC 35 45 55 ns
Care Time (Read Cycle Time)
Address Valid to Data Out
tAA 35 45 55 ns
Valid Delay (Address Access Time)
tAcSl[4] Chip Select LOW to Data Out Valid 35 45 55
ns
tACS2[S] (CY2148 only) 45 55 65
Chip Select LOW to Data Out Valid
tACS 15 20 25 ns
(CY2149 only)
Chip Select LOW to 2148 10 10 10
tLZ[6] ns
Data Out On 2149 5 5 5
Chip Select HIGH to Data
tHZ[6] 0 20 0 20 0 20 ns
Out Off
Address Unknown to Data Out
tOH 0 5 5 ns
Unknown Time
Chip Select HIGH to
tpo 2148 30 30 30 ns
Power-Down Delay
Chip Select LOW to
tpu 2148 0 0 0 ns
Power-Up Delay
WRITE CYCLE
twc 35 45 55 ns
Care (Write Cycle Time)
twp[2]
Write Enable LOW to
30 35 40 ns
Write Enable HIGH
tWR Address Hold from Write End 5 5 5 ns
Write Enable LOW to Output
twz[6] 0 10 0 15 0 20 ns
in High Z
tow Data in Valid to Write Enable HIGH 20 20 20 ns
tOH Data Hold Time 0 0 0 ns
Address Valid to Write
tAS 0 0 0 ns
Enable LOW
Chip Select LOW to Write
tcW[2] 30 40 50 ns
Enable HIGH
Write Enable High to Output
tow [6] 0 0 0 ns
in Low Z
tAW Address Valid to End of Write 30 35 50 ns
Switching Waveforms
~~~------------------------tRc------------------------~1~
ADDRE~_~~ :- ~ -_~ ~:_~-_-H~-_=~-_=_t=A_A=~-.-.,~,=======================-~-~~~~~~------------_-_-~

DATA OUT
______
PREVIOUS DATA VALID ~
,
__________
DATA VALID
0015-6
2-8
CY2148/CY21L48
fin~~NDUaoR =======================================================================
CY2149/CY21L49
Read Cycle No.2 (Notes 7,9)
~-------------------------tRe--------------------------_
~----------tAes----------~
tLZ---j
HIGH
HIGH IMPEDANCE IiP'R""'i~_IW"h,...--------------+--
DATA VALID
IMPEDANCE
DATAOUT .....-~---------(
tpu1 t
po
--! ICC
Vee
CUS~~~~~ _____ 50"1.. 50%~ 158
0015-9
Write Cycle No.1 (WE Controlled)
~---------------------------twe-------------------------~
ADDRESS
I--------------------tew ----------------------1
~----------------------tAw----------------------+W---
~--------tAS ---------~ ~-------twp-----~~
14---'------tow --------"--
DATA 1/0 DATA-IN VALID
twz~
DATA 1/0 .....---------DA-T-A-U-N-D-E-FI-NE-D------- )).--....;.;.;.;;.;..;..;.;.;;.;..;;,;;;;.;;.;.;.;.--~,,_ _ _ _ _ __
0015-8
Write Cycle No.2 (CS Controlled)
~--------------------------twe--------------------~
DATAIIO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ *t= -D:A-'NVAUD

!:==twz----l
DATA 1/0 DATA UNDEFINED ,>-_________
--\) ....;...;.;;.;;_______
HIGH IMPEDANCE
0015-7
Note: IfeS goes HIGH simultaneously with WE HIGH, the output remains in a HIGH impedance state.
2-9
~~~u~================================================================
CY2148/CY21L48
. . CY2149/CY21L49
Ordering Code
(ns) Type Range
35 CY214S-35 PC P3 Commercial
CY2149-35 PC
CY214S-35 DC D4
CY2149-35 DC
CY21L4S-35 PC P3 Commercial
CY21U9-35 PC
CY21US-35 DC D4
CY21L49-35 DC
CY2149-45 PC
CY214S-45 DC D4
CY2149-45 DC
CY214S-45 DMB D4 Military
CY2149-45 DMB
CY21U9-45 PC
CY21 L4S-45 DC D4
CY21L49-45 DC
CY2149-55 PC
CY214S-55 DC D4
CY2149-55 DC
CY214S-55 DMB D4 Military
CY2149-55 DMB
CY21U9-55 PC
CY21US-55 DC D4
CY21L49-55 DC
2-10
CY2148/CY21L48
5Jl ; CYPRESS CY2149/CY21L49
S~ICO~UcrOR================================================================
DC Characteristics
IOH 1,2,3
IOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB[1] 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tACSl[1] 7,8,9,10,11
tAcS2[1] 7,8,9,10,11
tACS[2] 7,8,9,10,11
tOH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
twp 7,8,9,10,11
tWR 7,8,9,10,11
tDW 7,8,9,10,11
tDH 7,8,9,10,11
tAS 7,8,9,10,11
tAW 7,8,9,10,11
\lotes:
. CY2148 only.
',. CY2149 only.
)ocument #: 38-00024-B
2-11
CY6116
CY6117
CYPRESS
Automatic power-down when The CY6116 and CY6117 are high per- tion addressed by the address present
deselected formance CMOS static RAMs orga- on the address pins (Ao through AlO).
nized as 2048 words by 8 bits. Easy Reading the devices is accomplished by
CMOS for optimum
speed/power memory expansion is provided by an selecting the device and enabling the
active LOW chip enable (CE), and ac- outputs, CE and OE active LOW,
High speed-35 ns tive LOW output enable (00) and while (WE) remains inactive or HIGH.
Low active power three-state drivers. The CY6116 and Under these conditions, the contents of
- 660 mW CY6117 have an automatic power- the location addressed by the informa-
down feature, reducing the power con- tion on address pins is present on the
Low standby power sumption by 83% when deselected. eight data input/output pins.
-110 mW
An active LOW write enable signal The input/output pins remain in a high
TTL compatible inputs and (WE) controls the writing/reading op- impedance state unless the chip is se-
outputs eration of the memory. When the chip lected, outputs are enabled, and write
Capable of withstanding greater enable (CE) and write enable (WE) in- enable (WE) is HIGH.
than 2001V electrostatic puts are both LOW, data on the eight The CY6116 and CY6117 utilize a die
discharge data input/output pins (1/00 through coat to ensure alpha immunity.
1/07) is written into the memory loca-
Logic Block Diagram
1/00
1/0,
1/0 2
1/0 3
1/04
1/0 5
1/0 6
CE ---._-<1
WE-t--1I~L
1/07
DE -I-+--<Ir--,
0087-1
Selection Guide
CY6116-35 CY6116-45 CY6116-55
CY6117-35 CY6117-45 CY6117-55
Current (rnA) Military 130 130 130
Current (rnA) Military 20 20 20
2-12
CY6116
&Ii~~~crOR===================================================================== CY6117
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... > 2001V
Power Applied .................... - 55C to
+ 125C
(Per MIL-STD-883 Method 3015)
Latch-up Current .......................... > 200 rnA til
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V Operating Range
Range Vee
in High Z State ...................... - 0.5V to + 7.0V Temperature
DC Input Voltage ................... - 3.OV to + 7.0V Commercial OOCto +700C 5V 1O%
Output Current into Outputs (Low) ............. 20 rnA MiIitary[4] - 55C to + 12SoC SV 10%

CY6116
Parameters Description Test Conditions CY6117 Units
Min. Max.
VOH Output HIGH Voltage Vee = Min.,loH = -4.0 rnA 2.4 V
VOL Output LOW Voltage Vee = Min.,loL = 8.0 rnA 0.4 V
IIX Input Load Current GND::;: VI::;: Vee -10 10 /-t A
Output Leakage GND::;: VI::;: Vee
loz 10 /-t A
Current Output Disabled
Output Short
los Circuit Current[l] Vee = Max., VOUT = GND -300 rnA
Vee Operating Vee = Max. Commercial 120

lee Supply Current rnA
lOUT = OmA Military 130
Automatic CE Max. Vee, Commercial 20
ISB Power Down Current rnA
CE:2 VIH Military 20
Capacitance [2]
CIN Input Capacitance TA = 2SoC, f = 1 MHz 5
pF
COUT Output Capacitance Vee = S.OV 7
Notes:
1. Not more than 1 output should be shorted at one time. Duration of 3. See the last page of this specification for Group A subgroup testing
the short circuit should not exceed 30 seconds. information.
2. Tested initially and after any design or process changes that may 4. TA is the "instant on" case temperature.
affect these parameters.

Rl481!1 Rl 481!1 ALL INPUT PULSES
5V~------~~~_ 5V o--------V\l\o-...., 3.0 V -----:~~---.oIJL
OUTPUT o---~---", OUTPUT 0 - - -......- - -..
GNO
30pF R2 5 pF R2
I
_
-
INCLUDING
JIGAND _
SCOPE -
255!1
0087-4
I INCLUDING
_JIG AND
- SCOPE
_
-
255!1
0087-5 Figure 2
0087-6
Figure la Figure Ib
Equivalent to:
THEVENIN EQUIVALENT
16m
OUTPUT O--~tt1""'.Ir.---o 1.73V 0087-7
2-13
CY6116
(in . CY6117
~NDUcrOR==~~~~~~~~~~~~~~~~~~~~~~======~======~==~~
CY611635 CY611645 CY611655
Parameters Description CY611735 CY611745 CY611755 Units
READ CYCLE
tDOE OE LOW to Data Valid 15 20 25 ns
tLZOE OE LOW to Low Z 0 0 0 ns
tHZOE OE HIGH to High Z[7] 15 15 20 ns
tLZCE CE LOW to Low Z[8] 5 5 5 ns
tHZCE CE HIGH to High Z[7, 8] 15 20 20 ns
tpD CE HIGH to Power Down 20 25 25 ns
WRITE CYCLE[9]

tSCE CE LOW to Write End 30 40 40 ns
tSD Data Set-up to Write End 15 20 25 ns
tHD Data Hold from Write End 0 0 0 ns
tHzWE WE LOW to High Z 15 15 20 ns
tLZWE WE HIGH to Low Z 0 0 0 ns
Notes:
5. Data 1/0 Pins enter high-impedance state, as shown, when OE is 9. The internal write time of the memory is defined by the overlap of
held LOW during write. CE LOW and WE LOW. Both signals must be LOW to initiate a
6. Test conditions assume signal transition times of 5 ns or less, timing write and either signal can terminate a write by going HIGH. The
reference levels of 1.5V, input pulse levels of 0 to3.0V and output data input setup and hold timing should be referenced to the rising
loading of the specified 10VlOH and 30 pF load capacitance. edge of the signal that terminates the write.
7. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure to. WE is HIGH for read cycle.
1h. Transition is measured 500 mV from steady state voltage. 11. Device is continuously selected. OE, CE = VIL.
8. At any given temperature and voltage condition, tHZCE is less than 12. Address valid prior to or coincident with CE transition LOW.
tLZCE for any given device.
Switching Waveforms
-----,J;~~-------------------------tRc--------------------------~1~
DAADTDARoEUSST _
__-_{ "'I!_:~ :~__:~~to~H~A~~~~~tA~A-L0-.
PREVIOUS DATA VALID
,-----.-.-.-'.-_~~~~~~~~~~~~~~~~~~~~~~~~~*_~~~~~~~~~~~~~~~~~
~ ' DATA VALID
0087-8
214
CY6116
fin .
~~UcrOR==================================================================
CY6117
til
tRC
).- ..,l
\ J
tACE
~ ....
~
{
~"'~
tOOE
f--tHZCE-
I4---tLZOEi
HIGH
IMPEDANCE
1/
.r- \. \. \. \.
HIGH IMPEDANCE 1/ / / / ,
DATA OUT DATA VALID
/
J
tLZCE
1\
i---tpo
I-----tpu
--1 ICC
VCC
SUPPL
CURRENT
Y ______
-
50%
=~'SB
0087-9
Write Cycle No.1 (WE Controlled) (Notes 5, 9)

~-----------------------------~C----------------------------~
ADDRESS
I + - - - - - - - - - - - - - - tSCE ----------------------1
_-,,"_.. 1
1+------------------------tAW---------------------~~---
l4---------tSA-------------.I ~-------t~E------~~
WE --------------------~~- ~-------------------
14--'--------tso ------+-_
tHZWE~
DATA lID ----------D-A-T-A-U-N-D-EF-,-N-ED-------- )o---.;..;.;.;;.;.;.;.;.;.;.;;.;;.;.;;.~--~
------ 0087-10
Write Cycle No.2 (CE Controlled) (Notes 5, 9)

I+-----------------------------twc------~--------------------~
ADDRESS
- .....-----~tSCE - - - - - - - + l
I+--+--------------tso-------.ll--
DATA IN DATA-ioN VALID
tHZWE-----!
------------------~ HIGH IMPEDANCE

DATA 110 DATA UNDEFINED J~----------------------
0087-11
Note: IrCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-15
CY6116
fin .
~NDUcroR =====================================================================
CY6117
Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.2 120
1.2 L ~ <
!
1.0
... 100
IV
~ ..,a:z
III
1.0 .:P
0.8
V U 0.8
.!:/
..,
Q
a:
~
..,uu
80
~
0.6
V N
::;
0.6
a:
60
~
Vee" 5.0 V
'::Ea:" 0.4
~
0
en
... 40
TA = 25"C
'"
0.4 0 Vee =5.0V
z VIN -5.0V ~
0.2 0.2 ...

IL
20
"
Isa Isa ~
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('CI OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT

1.4 1.6 ,------"T'"""-------, 140
1.3
1.4 ~----+--------t
<
!
...
120
/
I" --
" " ..,a:z 100
:!-
0
w
1.2 :1-
~ 1.2 ~----+----_,,~--t a: 80 / Vee = 5.0 V
TA = 25'C
N
::; 1.1
~
.............
N
::;
~
u
:.:
I
~
TA =25'C
'o"
~ 1.0 ~----~~------t z 60
2;
iii
L
-
II:
0
z
1.0
~ z ... 40
0.9 0.8 ""'""'~---+--------t ...~

~ /
0 20
0.8 0.6 ' - - - - - - " " ' - - - - - -.......

V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('CI OUTPUT VOLTAGE (VI
TYPICAL POWERON CURRENT TYPICAL ACCESS TIME CHANGE NORMALIZED Icc

vs. SUPPLY VOLTAGE vs. OUTPUT LOADING vs. CYCLE TIME
3.0 30.0 1.4
I
"..- Vee =5.0V
2.5 25.0 1.3 -TA = 25'C
E 2.0 ! 20.0 L (J
.!:/
..,
1.2
VIN =0.5 V
/
0 Q
W
N
:::; 1.5 "
: 15.0
N
::::i 1.1
2;
a:
:;.., /11' 'a:"
::E
1.0 1.0
i Q 10.0 0
z ~
/ / TA = 25'C
Vee =4.50 V ~
-
~
0.5 5.0 0.9
~
0.0
0.0 1.0 2.0
",/
3.0 4.0 5.0
0.0 V
o 200 400 600 800 1000
0.8
o
~
10 20 30 40
SUPPL Y VOLTAGE (VI CAPACITANCE (pFI CYCLE FREQUENCY (MHzI
0067-12
2-16
CY6116
5r~ CY6117
Pin Configurations

A7 Vee .... 0 0 0 ~oo co .... (.)
(.)
< z z z > z z > 00 01
.... I/)
A6 As
4 3 211 1 1132 31 30 3
As Ag
AS 5 29 AS A3 WE
A4 WE
A5 6 28 Ag A2 OE
A3 DE A10
A4 7 27 NC NC
A2 A,o
8 26 WE NC CY6116 NC
A, CE A3
Al 21 NC
Ao 1/0 7 A2 9 CY6117 25 DE
Ao CE
1/00 1/06 Al 10 24 A10
1/1 I/O s
1/0, 1/0 5
AO 11 23 CE
1/02 1/04
NC 12 22 1/7 NI'lC .... IOCO ....
GND 1/03
1/0 13 21 I/Os ~~~~~~~
0087-2 14 15 16 17 18 19 20 0087-3
0087-14
Speed Package Operating Speed Package Operating
Ordering Code Ordering Code
(ns) Type Range (ns) Type Range
35 CY6116-35PC Pll Commercial 35 CY6117-35LMB L55 Military
CY6116-35DC D12 45 CY6117-45LMB L55 Military
CY6116-35LC L64 55 CY6117-55LMB L55 Military
CY6116-35DMB D12 Military
CY6116-35LMB L64
45 CY6116-45PC Pll Commercial
CY6116-45DC D12
CY6116-45LC L64
CY6116-45LMB L64
55 CY6116-55PC Pll Commercial
CY6116-55DC D12
CY6116-55LC L64
CY6116-55LMB L64
2-17
CY6116
WA . . CYPRESS CY6117
S~~U~R==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #: 38-00055-C
2-18
CY6116A
CY6117A
CYPRESS
Features
Automatic power-down when
Functional Description
The CY6116A and CY6117A are high tion addressed by the address present
til
deselected performance CMOS static RAMs orga- on the address pins (Ao through AlO).
nized as 2048 words by 8 bits. Easy Reading the device is accomplished by
CMOS for optimum
speed/power memory expansion is provided by an selecting the device and enabling the
active LOW chip enable (CE), and ac- outputs, CE and OE active LOW,
High speed-20 ns tive LOW output enable (OE) and while (WE) remains inactive or HIGH.
Low active power three-state drivers. The CY6116A and Under these conditions, the contents of
- 550 mW CY6117A have an automatic power- the location addressed by the informa-
down feature, reducing the power con- tion on address pins is present on the
Low standby power sumption by 83% when deselected. eight data input/output pins.
-110 mW
An active LOW write enable signal The input/output pins remain in a high
TTL compatible inputs and (WE) controls the writing/reading op- impedance state unless the chip is se-
outputs eration of the memory. When the chip lected, outputs are enabled, and write
Capable of withstanding greater enable (CE) and write enable (WE) in- enable (WE) is HIGH.
than 2001V electrostatic puts are both LOW, data on the eight The CY6116A and CY6117A utilize a
discharge data input/output pins (1/00 through die coat to ensure alpha immunity.
Logic Block Diagram
>-t+t~f-t+-I/Oo
>-t+t~f+-- 1/0,
>-~---I/05
> - + + - - - - 1 /0 6
CE---._-<I
WE--~
OE-t-i-<:r-""",
0167-1
Selection Guide
CY6116A20 CY6116A25 CY6116A35 CY6116A-45 CY6116A-55
CY6117A-20 CY6117A-25 CY6117A-35 CY6117A-45 CY6117A-55
Maximum Access Time (ns) 20 25 35 45 55
Maximum Operating Commercial 100 100 100 100 80
Current (mA) Military 125 100 100 100
Maximum Standby Commercial 40/20 20 20 20 20
2-19
~ CY6116A
.r.~NDUcroR CY6117A
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... ). 2001V
Power Applied .................... - 55C to + 125C Latch-up Current .......................... > 200 mA
Supply Voltage to Ground Potential Operating Range
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
DC Voltage Applied to Outputs Range Ambient
Temperature Vee
in High Z State ...................... - O. 5V to + 7.0V
Commercial OCto + 70C 5V 10%
DC Input Voltage ................... - 3.0V to + 7.0V
Military [4] - 55C to + 125C SV 1O%
Output Current into Outputs (Low) ............. 20 mA
CY6116A-20 CY6116A-25, 35, 45 CY6116A-55
Parameters Description Test Conditions CY6117A-20 CY6117A-25, 35, 45 CY6117A-55 Units
VOH Output HIGH Voltage Vee = Min., IOH = -4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee V
VIL Input LOW Voltage[4A] -0.5 0.8 -0.5 0.8 -0.5 0.8 V
IIX Input Load Current GND ~ VI ~ Vee -10 10 -10 10 -10 10 p.A
Output Leakage GND ~ VI ~ Vee -10 +10 -10 -10
loz Current Output Disabled +10 +10 p.A
Output Short
lOS Circuit Current[l] Vee = Max., VOUT = GND -300 -300 -300 mA
Coml. 100 100 80

Vee Operating Vee = Max.
Ice Supply Current lOUT = OmA Mil.~
35,45
125
100
100
mA
Max. Vee, Coml. 40 20 20

Automatic CE CEI ~ VIH, 25 40
ISBI Power Down Current I--- mA
Min. Duty Mil. 20
Cycle = 100% 35,45 20
Automatic CE CEI ~ Vee - 0.3V,
ISB2 mA
Power Down Current VIN ~ Vee - 0.3V
orVIN ~ 0.3V Mil. 20 20
*35 ns and 55 ns only
Capacitance [2]
CIN Input Capacitance TA = 25C, f = 1 MHz 5
Vee = 5.0V pF
COUT Output Capacitance 7
Notes:
affect these parameters. 4A. VIL min. = - 3.0V for pulse durations less than 30 ns.
Rl481fl Rl481n ALL INPUT PULSES
5VO---~N'tI-~ 5V
~
3.0 V
-=dt
OUTPUT C>--......- - - . . . . OUTPUT
I
30pF
INCLUDING
_ JIGAND _
R2
265fl I 5 pF
INCLUDING
_JIG AND _
R2
255fl
GND
- SCOPE - 0167-5 - SCOPE - 0167-6 0167-' .

Equivalent to: THEVENIN EQUIVALENT
16m
OUTPUT O--~'I'\""''''.----O 1.73V 0167-8
2-20
CY6116A
fm .
~NDUcrOR =====================================================================
CY6117A
Switching Characteristics Over Operating Rangd4, 6]

CY6116A20 CY6116A25 CY6116A35 CY6116A45 CY6116A55
til
Parameters Description CY6117A20 CY6117A25 CY6117A35 CY6117A45 CY6117A55 Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 20 25 35 45 55 ns
tAA Address to Data Valid 20 25 35 45 55 ns
tOHA Data Hold from Address Change 5 5 5 5 5 ns
tACE CE LOW to Data Valid 20 25 35 45 55 ns
tDOE OE LOW to Data Valid 10 12 15 20 25 ns
tLZOE OE LOW to Low Z 3 3 3 3 3 ns
tHZOE OE HIGH to High Z[7] 8 10 12 15 20 ns
tLZCE CE LOW to Low Z[S] 5 5 5 5 5 ns
tHzCE CE HIGH to High Z[7, S] 8 10 15 15 20 ns
tpu CE LOW to Power Up 0 0 0 0 0 ns
tpD CE HIGH to Power Down 20 20 20 25 25 ns
WRITE CYCLE[9]
twc Write Cycle Time 20 20 25 40 50 ns
tSCE CE LOW to Write End 15 20 25 30 40 ns
tAw Address Set-up to Write End 15 20 25 30 40 ns
tHA Address Hold from Write End 0 0 0 0 0 ns
tSA Address Set-up to Write Start 0 0 0 0 0 ns
tPWE WE Pulse Width 15 15 20 20 25 ns
tSD Data Set-up to Write End 10 10 15 15 25 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tHZWE WE LOW to High Z 7 7 10 15 20 ns
tLZWE WE HIGH to Low Z 5 5 5 5 5 ns
Notes:
5. Data I/O Pins enter high-impedance state, as shown, when OE is 9. The internal write time ofthe memory is defined by the overlap of
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output data input setup and hold timing should be referenced to the rising
loading of the specified Ior/IOH and 30 pF load capacitance. edge of the signal that terminates the write.
7. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure 10. WE is HIGH for read cycle.
1h. Transition is measured 500 mV from steady state voltage. 11. Device is continuously selected. OE, CE = VIL.
S. At any given temperature and voltage condition, tHzCE is less than 12. Address valid prior to or coincident with CE transition LOW.
Switching Waveforms
ADOR ... ~~...-_

---i
-_- _- _ -
~"'
_-
---+I
_tRC--====~~* __
DATA OUT PREVIOUS DATA VALID DATA VALID
0167-9
2-21
CY6116A
WA .
~NDUcroR =====================================================================
crM~

tRC
)t -,l
j
tAce
)~
I---tLZOEi
tooe f '~":j
f+-tHzce-
HIGH
DATA OUT
HIGH IMPEDANCE 1/ / / / , ~
DATA VALID , IMPEDANCE
!---tpu
tLZce "t '" '" '" '" ~ ~tPD
Vcc ]
SUPPLY _ _ _ _ _ _ ~ 50%
CURRENT -
0167-10

~------------------------~---~c----------------------------~
ADORESS
.....-.1_ _ 1~------------------- tSCE ----------------------+1
~-----------------------tAW----------------------~~---
-----------tSA----------~ ~--~--t~E------~
--------------------~~-
\+--'--------tso --------~14_
_____________________ ~tH~ZW~E~
DATA 110 DATA UNDEFINED >)o---.. . -.. . . . .~--~'-------

0167-11

~-------------------------'--twc--------------------------~
-t-------------tscE ------------.1
--~--------------~ I,----~-------------
~-I---------------tso-------+l\4-
DATA-IN VALID
tHZWE~
DATA 110 ---------O-A-TA-U-ND-E-F-IN-E-D---- ___________ H..;IG;.;.H..;I..;M..;PE;.;;D;.;.A..;N,;,CE;;..._ _ _ _ __
0167-12
2-22
CY6116A
(fA~~UaoR==================================================================
. CY6117A

1.4 1.2 120
1.2 ./ 1.0 ~ <

! 100
~
IV I-
~ 1.0 j ~
] ./ U 0.8 a:
a: 80
~
1: :::l
c 0.8 cw u
w
N
::; ./ N 0.6 w
u 60
'" '"
0.6 ::; a: Vee = 5.0 V
0( 0(
S
:::l TA =25C
S
IZ:
0.4 IZ: 0.4 ~ 40
0 0 Vee "'5.0 V I-
z z VIN5.0V :::l
~
0.2 0.2 I- 20
'"
IS8 IS8 :::l
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0

1.4 1.6 140
~
1.3 < 120
1.41-----+----------1 ! ~V
I- 100
Z
:1
:1
c
w
1.2
~
N
1.2 1-____+-___~C-.--1
w
a:
a:
:::l
80
/ Vee =5.0V
TA = 25'C
N
::; 1.1 ""- ::; U V
"'
c( :>'
0(
TA =25'C z 60
~
IZ: ~ ~
o
1.0 1-----,."--------1 iii
/
0
z
1.0
0.9
r------ t--- z
0.8 ~~---+--------1
I-
:::l
~
I-
:::l
40
/
0 20
0.8
4.0 4.5 5.0 5.5 6.0
0.6 ......- - - -......- - - - -......
V
-55 25 125 0.0 1.0 2.0 3.0 4.0
TYPICAL POWER-ON CURRENT TYPICAL ACCESS TIME CHANGE NORMALIZED Icc

3.0 30.0 1..4
I
~ Vee = 5.0V
2.5 25.0 1.3 r--TA = 25'C
E
cw
2.0 ! 20.0
/ 1:
cw
...
1.2
VIN =0.5 V
N
::; 1.5

;: 15.0
/ N
::; 1.1
c(
S
IZ:
~ /11' 0(
S
a:
i 1.0 ~ 10.0 0 1.0
~/
z ~
/ TA = 25'C
Vee =4.50 V ~
-V
0.5 5.0 0.9
~
0.0
0.0 1.0 2.0 3.0 4.0 5.0
0.0 V
o 200 400 600 800 1000
0.8 ~
o 10 20 30 40
SUPPLY VOLTAGE (VI CAPACITANCE (pFI CYCLE FREQUENCY (MHz!
0167-13
2-23
CY6116A
WA .
~U~================================================================
CY6117A
Pin Configurations
.... 0 o 0 80 0 0
Vee 0( Z Z Z > Z Z
..... IIlCD .... OOClOl
0(0(0(0(>0(0(
As
4 3 21 1 132 31 30
A5 At 1 1 3 2 111282726
AS 5 29 AS A3 '-'
25 WE
~ WE
DE AS 6 28 Ag A2 OE
A3
A4 7 27 NC NC Al0
A2 A'0
NC 6116A NC
A, Ci A3 8 26 WE
A1 21 NC
Au 1/0 7 A2 9 CY6117A 25 OE
AO CE
1/0, A1 10 24 A 10
1/1 I/Os
II0s 11 23 CE
AO
1/02 1/0. o .....
NC 12 22 1/7 N It) III CD ....
GND 1/0 3
1/0 13 21 I/Os ~~(5~~~~
0167-2 14 15 16 17 18 19 20 0167-4
.....
z 0z
It) III
o- 0
NO
:::::':::::,e> ~~~
0167-3
20 CY6116A-20PC Pll Commercial 25 CY6117A-25LMB L55 Military
CY6116A-200C 012 35 CY6117A-35LMB L55 Military
25 CY6116A-25PC Pll Commercial 45 CY6117A-45LMB L55 Military
CY6116A-250C 012 55 CY6117A-55LMB L55 Military
CY6116A-25LC L64
CY6116A-250MB 012 Military
CY6116A-25LMB L64
35 CY6116A-35PC Pll Commercial
CY6116A-350C 012
CY6116A-35LC L64
CY6116A-35LMB L64
CY6116A-450C 012
CY6116A-45LC L64
CY6116A-45LMB L64
CY6116A-550C 012
CY6116A-55LC L64
CY6116A-55LMB L64
2-24
CY6116A
(;n~~~UODR==============================================================
CY6117A
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tAcE 7,8,9,10,11
tOOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAw 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
Document #: 38-00105
2-25
CY7C122
CYPRESS
256 x 4 static RAM for control The CY7C122 is a high performance operation insures minimum write re-
store in high speed computers CMOS static RAM organized as 256 covery times by eliminating the "write
words x 4 bits. Easy memory expansion recovery glitch."
CMOS for optimum
speed/power is provided by an active LOW chip se- Reading is performed with the chip se-
lect one (CSl) input, an active HIGH lect one (CSl) input LOW, the chip se-
High speed chip select two (CS2) input, and three-
- 15 ns (commercial) lect two input (CS2) and write enable
state outputs. (WE) inputs HIGH, and the output en-
- 25 ns (military)
An active LOW write enable input able input (OE) LOW. The information
Low power (WE) controls the writing/reading op- stored in the addressed word is read
- 330 mW (commercial) eration of the memory. When the chip out on the four non-inverting outputs
- 495 mW (military) select one (CSl) and write enable (WE) 00 to 03.
Separate inputs and outputs inputs are LOW and the chip select The outputs of the memory go to an
two (CS2) input is HIGH, the informa- active high impedance state whenever
5 volt power supply 10% tion on the four data inputs Do to D3 is
tolerance both commercial and chip select one (CSl) is HIGH, chip se-
written into the addressed memory lect two (CS2) is LOW, output enable
military word and the output circuitry is pre- (OE) is HIGH, or during the writing
Capable of withstanding greater conditioned so that the correct data is operation when write enable (WE) is
than 2000V static discharge present at the outputs when the write LOW.
cycle is complete. This preconditioning
TTL compatible inputs and
outputs
Logic Block Diagram Pin Configurations
02
01
0003-2
N.., U U
oc( oc( Z Z >~
A4
WE
CS 1
OE
CS 2
03
Do 03
o _ .... N C'I
oeoco 0003-10
Selection Guide
7C122-15 7C122-25 7C122-35
Commercial 15 25 35
Maximum Access Time (ns)
Military NA 25 35
Commercial 90 60 60
Maximum Operating Current (rnA)
Military NA 90 90
2-26
~ CY7C122
~~~UcrOR =====================================================================
Maximum Ratings
Storage Temperature ............... -65C to
Pin 22 to Pin 8) ..................... -0.5V to
in High Z State ...................... -0.5V to
+ 150C
+ 125C
+ 7.0V
+ 7.0V
Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 3015)
Latchup Current .......................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
OCto + 70C
Vee
5V 1O%

Output Current, into Outputs (Low) ............. 20 mA
Military [5] - 55C to + 125C 5V 1O%
Logic Table
Inputs
Outputs Mode
OE CSt CS2 WE Do-D3
X H X X X HighZ Not Selected
X X L X X HighZ Not Selected
L L H H X 00-03 Read Stored Data
X L H L L HighZ Write "0"
X L H L H HighZ Write "I"
H L H H X HighZ Output Disabled
Notes: H = HIGH Voltage L = LOW Voltage x = Don't Care
High Z = High Impedance
Electrical Characteristics Over the Operating Range[4]

7C122-2S
7C122-1S
Parameters Description Test Conditions 7C122-3S Units
Min. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min., IOH = - 5.2 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.1 VCC 2.1 VCC V
IIX Input Load Current GND:::;: Vl:::;: Vcc 10 10 p,A
Input Diode Clamp
VCD Note 2 Note 2 V
Voltage
VOL:::;: VOUT:::;: VOH
loz Output Current (High-Z)
Output Disabled
-10 +10 -10 +10 p,A
Output Short Circuit Vcc = Max., Commercial -70 -70 mA

los Current (Note 1) VOUT = GND Military -80 -80 mA
Power Supply Vcc = Max., Commercial 90 60 mA
IcC Current lOUT = OmA Military NA 90 mA
Capacitance [3]
pF
COUT Output Capacitance VCC = 5.0V 7
Notes:
1. For test purposes, not more than one output at a time should be 3. Tested initially and after any design or process changes that may
shorted. Short circuit test duration should not exceed 30 seconds. affect these parameters.
2. The CMOS process does not provide a clamp diode. However, the 4. See the last page of this specification for Group A subgroup testing
CY7C122 is insensitive to -3V dc input levels and -5V undershoot information.
pulses ofless than 10 ns (measured at 50% point). 5. TA is the "instant on" case temperature.
2-27
~ CY7C122
~~~NDUcrOR ;====================================================================
Switching Characteristics Over the Operating Ra;ge[6, 7]
Test CY7C122-15 CY7C122-25 CY7C122-35
Parameters Description Conditions Units
READ CYCLE
tACS Chip Select Time 8 15 25 ns
tZRCS Chip Select to High-Z Note 8 12 20 30 ns
tAOS Output Enable Time 8 15 25 ns
tZROS Output Enable to High-Z Note 8 12 20 30 ns
tAA Address Access Time 15 25 35 ns
WRITE CYCLE
tzws Write Disable to High-Z Note 8 12 20 30 ns
tWR Write Recovery Time 12 20 25 ns
tw Write Pulse Width Note 6 11 15 25 ns
tWSD Data Setup Time Prior to Write 0 5 5 ns
tWHD Data Hold Time After Write 2 5 5 ns
tWSA Address Setup Time Note 6 0 5 10 ns
tWHA Address Hold Time 4 5 5 ns
twSCS Chip Select Setup Time 0 5 5 ns
tWHCS Chip Select Hold Time 2 5 5 ns
Notes:
6. tw measured at tWSA = min.; tWSA measured at tw = min. 8. Transition is measured at steady state HIGH level - 500 mV or
7. Test conditions assume signal transition times of 5 ns or less for the steady state LOW level + 500 mVon the output from 1.5V level on
- 15 product and 10 ns orless for the - 25 and - 35 product. Timing the input with load shown in Figure 1h.
reference levels of 1.5V and output loading of the specified IorJIOH
and 30 pF load capacitance as in Figure 1Q.
BitMap
Address Designators
Address Address Pin
Name Function Number
Ao AXO 4
Al AXl 3
A2 AX2 2
A3 AX3 1
A4 AX4 21
As AYO 5
A6 AYl 6
A7 AY2 7
0003-3
2-28
~ CY7C122
~~~NDUcrOR =======================================================================
5VTl
OUTPUT
r ':"
u:T1
r
Rl 47051
30 pF
AC Test Loads
R2
22451
OUTP
5
Rl 47051
5 pF R2
~ ~.n
3.0 V-----.i~----~
GND
Input Pulses
Figure 2
0003-5
0003-4
Figure la Figure Ib
152.11
OUTPUT O--~I/<"...
I/<Ir-.---<0 1.62 V
0003-6
Read Mode
Ao-A7
ADDRESS
tAA
I
-'~
, \.
'~ }'f.
1- .....-tZROS
tAOS ,NOTE6
DATA '-
OUTPUTS
Iffffff" DATA VALID
0 0-03
\.\.\.\.\.\.\.\.\. 1-
LNOTE6
tACS !--tZRCS_
0003-7
Write Mode
twe
AO-A7
ADDRESS -elf- -It
~1-CS2
CHIP SELECT
---
-H-
tWSA I---
- tWHA
~~
I--
0 0- 0 3
---
-H-
tWSCS I--
- twHCS
~~
I--
-
DATA IN
twso tw twHO I--

W -'0- ..,~
WRITE ENABLE
0 0-0 3
DATA OUTPUTS
LOADlb
" NOTE 6 I--twR
~-----~--(
------------------------~~NOTE6
tzws
} 1-
0003-8
(All above measurements referenced to 1.5V unless otherwise stated.)
Note:
Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed in various applications as long as the worst case
limits are not violated.
2-29
~ CY7C122
~~~NDUcrOR =====================================================================
NORMALIZED Icc NORMALIZED Icc OUTPUT SOURCE CURRENT
1.2.------r----,----,----, 1.4.------..--------, 60
~
! 50 ~
'"
1.0 ~ Vee = 5.0 V
1.2
1l 1l ~ TA = 25C
cc 40
~
@ cc
N
fil
N
::l
(,J
::::; 0.8 ::::; w 30
<l <l (,J
'"
:E :E cc
cc cc ::l
0 0 0 20
z z (i)
0.6 ~
VIN = 5.0 V Vee =5.5V

~
~ 10 "'-"
~
::l
TA = 25C VIN =5.0V 0
0.4 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)

1.6 1.4 150
1.4
~ 125 ~ -
~V
!
~
:! :! ~ 100
C
w
N
::::;

1.2
~ ...............
fil
N
::::;
.
cc
cc
::l
(,J
~
75
I
/
z
- I
:E 1.0 :t
cc ~ a: iii 50
0 0
z
/
~
z
0.8 ~
~ Vee =5.0V_
::l 25
0.6
4.0 4.5
I
5.0
TA j25C
5.5 6.0
0.6
-55 25
Vee = 5.0V
125
0
V 1.0 2.0 3.0
TA =rOC
4.0 5.0
SUPPL Y VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VO LT AGE (V)
ACCESS TIME CHANGE NORMALIZED Icc

vs. OUTPUT LOADING vs. FREQUENCY
1.4
1.3 l/
!

1l
cw 1.2
//
V'
N
:! :J

~
w
~
a: 1. 1
c 0
z /
1.0 /
0
0 10 20 30 40 50 60 70
CAPACITANCE (pF) FREQUENCY (MHz)

0003-9
2-30
~PRFSS CY7C122
~~~~O~UcrOR==================================================================
Ordering Code
(ns) Type Range
15 CY7C122-15PC
CY7C122-15DC
P7
D8
Commercial
Commercial
til
25 CY7C122-25PC P7 Commercial
CY7C122-25DC D8 Commercial
CY7C122-25LC L53 Commercial
CY7CI22-25DMB D8 Military
CY7CI22-35LMB L53 Military
2-31
~ CY7C122
~~~U~R================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
. VIL Max. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tACS 7,8,9,10,11
tAOS 7,8,9,10,11
tAA 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tWR 7,8,9,10,11
tw 7,8,9,10,11
tWSD 7,8,9,10,11
tWHD 7,8,9,10,11
tWSA 7,8,9,10,11
tWHA 7,8,9,10,11
tWSCS 7,8,9,10,11
tWHCS 7,8,9,10,11
Document #: 38-0002S-B
2-32
PRELIMINARY CY7C123
CYPRESS
256 x 4 static RAM for control The CY7C123 is a high performance covery times by eliminating the "write
store in high speed computers CMOS static RAM organized as 256 recovery glitch."
CMOS for optimum words x 4 bits. Easy memory expansion Reading is performed with the chip se-
speed/power is provided by an active LOW chip select one (CSt) input LOW, the chip se-
lect one (CSt) input, an active HIGH lect two input (CS2) and write enable
High speed chip select two (CS2) input, and three-
- 7 ns (commercial) (WE) inputs HIGH, and the output en-
state outputs. able input (OE) LOW. The information
- 10 ns (military)
An active LOW write enable input stored in the addressed word is read
Low power (WE) controls the writing/reading op- out on the four non-inverting outputs
- 660 mW (commercial) eration of the memory. When the chip 00 to 03.
- 825 mW (military) select one (CSt) and write enable (WE) The outputs of the memory go to an
Separate inputs and outputs inputs are LOW and the chip select active high impedance state whenever
two (CS2) input is HIGH, the informa- chip select one (CSt) is HIGH, chip se-
5 volt power supply 10% tion on the four data inputs Do to D3 is
tolerance both commercial and lect two (CS2) is LOW, output enable
written into the addressed memory (OE) is HIGH, or during the writing
military word and the output circuitry is pre- operation when write enable (WE) is
TTL compatible inputs and conditioned so that the write data is LOW.
outputs present at the outputs when the write
cycle is complete. This preconditioning A die coat is used to insure alpha im-
24 pin operation insures minimum write re- munity.
300 MIL package

A2 Vee
A3 AI
A4 Ao
As WE
As ~1
A7 or
Vss Vee
DO CS2
01 03
00 O2
1 3
Vss 2
0088-2
u
.. ,." N >0 -
3 2 ~2423
As 4 22 Ao
As 5 21 WE
A7 20 CS 1
COLUMN Vss 19 OE
As DECODER DO 8 18 Vee
01 9 17 CS 2
0088-1 0 10 03
0' :VJ: ' 0

N,." N
00
0088-3
Selection Guide
7C1237 7C1239 7C12310 7C12312 7C12315
Maximum Access Time (ns) Commercial 7 9 NA 12 NA
Military NA NA 10 12 15
Maximum Operating Current (mA) Commercial 120 120 NA 120 NA
Military NA NA 150 150 150
2-33
~ PRELIMINARY CY7C123
~~~U~================================================================
Maximum Ratings
Storage Temperature ............... - 6SoC to + IS0C Output Current, into Outputs (Low) ............. 20 rnA
Ambient Temperature with Latchup Current .......................... > 200 rnA
Power Applied .................... - SSoC to + 12SoC
Operating Range
Pins 24 & 18 to Pins 7 & 12 ........... -O.SV to + 7.0V Range
Ambient
Vee
Temperature
in High Z State ...................... - O.SV to + 7.0V Commercial OCto + 70C SV 1O%
DC Input Voltage ................... - 3.0V to + 7.0V Military [2] - SsoC to + 12SoC SV 1O%
Logic Table
Inputs
Outputs Mode
OE CSt CS2 WE Do-D3
X H X X X HighZ Not Selected
X X L X X HighZ Not Selected
L L H H X 00-03 Read Stored Data
X L H L L HighZ Write "0"
X L H L H HighZ Write "I"
H L H H X HighZ Output Disabled
Notes:H = HIGH Voltage L = LOW Voltage x= Don't eare
High Z = High Impedance

7C1237 7C12310
7C12312
Parameters Description Test Conditions 7C1239 7C12315 Units
VOH Output HIGH Voltage Vee = Min., IOH = -S.2mA 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 V
VIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 V
IIX Input Load Current Vss::;: VI::;: Vee -10 10 -10 10 -10 10 /-LA
Output Current VSS ::;: VOUT ::;: Vee
loz -10 + 10 -10 + 10 -10 +10 /-LA
(HighZ) Output Disabled
lee
Power Supply Vee = Max., l Commercial 120 NA 120 rnA
Current lOUT = OmA I Military NA ISO ISO rnA
Capacitance [1]
pF
CoUT Output Capacitance Vee = S.OV 7
Notes:
I. Tested initially and after any design or process changes that may 3. See the last page ofthis specification for Group A subgroup testing
affect these parameters. information.
234
~~~NDUcrOR ====================================================================
Switching Characteristics Over the Operating Ranger3]
Test 7C123-7 7C123-9 7C123-10 7C123-12 7C123-15
Conditions Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tAA Address Access Time 7 9 10 12 15 ns
tACS Chip Select Time 7 8 8 8 10 ns
tDOE Output Enable Time 7 8 8 8 10 ns
tHZCS Chip Select to Output Hi-Z Notes 4,5 5 6 6 6.5 8 ns
tHZOE Output Enable to Out Hi-Z Note 4 5 6 6 6.5 8 ns
tLZCS Chip Select to Out Low-Z Notes 4,5 2 2 2 2 2 ns
tLzOE Output Enable to Out Low-Z Note 4 2 2 2 2 2 ns
WRITE CYCLE
tHZWE Write Enable to Hi-Z 5.5 6 6 7 8 ns
tLZWE Write Enable to Low-Z 2 2 2 2 2 ns
tPWE Write Pulse Width 5 6.5 7 8 11 ns
tSD Data Setup to End of Write 5 6 7 8 11 ns
tHD Data Hold Time After Write 1 1 1 1 1 ns
tSA Add Setup to Start of Write 0.5 1 1 2 2 ns
tHA Address Hold Time 1.5 1.5 2 2 2 ns
tscs CS Active Low to End of Write 5 6.5 7 8 11 ns
tAW Add Setup to End of Write 5.5 7.5 8 10 13 ns
Notes:
4. Transition is measured at steady state HIGH level - 500 mV or 5. At any given temperature and voltage condition, tHZCS is less than
steady state LOW level + 500 mV on the output from 1.5V level on tLZCS for any given device.
the input with load shown in Figure 1h.
2-35
~~~~u~==================================================================
AC Test Loads Input Pulses
5V~R1470!l
Rl 470!l 3.0V-----J1~----oL
5V
TI
OUTPUT OUTPUT
r ':"
GND
20pF R2 5PF R2
224!l
1 - --
224!l
Figure 2
0088-5
0088-4
Figure la Figure Ib
15251
OUTPUT O--....J,IJ</'IJ
..Ioo.- -....0 1.62 V
0088-6
Read Mode
~,,~----------------tRC------------~
ADDRESS ---_____ .J),c~-----t

_____~-----------------,~~--------
AA -------..:,
______________
CsdCS2 ---------"\X --',~ _______ : ~:-------.J,
X '
: - tAcs - , _ tHZCS --:
t LZCS : - - - ; : : '
-------------~~ : I ,
~tooE.-I " ,
tLZOE---,.J, ' - , ,
, ,-tHZOE~
,
~~----------------~(~.(~~------~----~)~:------
0088-11
Write Mode
II .. I
twc
~, ~
_ _ _ _J
ADDRESS
tAW -I" tHA-:
"
,I. tscs
",
Cs 1/CS 2 _______ ~-----J
,j.
X X
,
tSA ,'.
, t pWE - :
I,
DATA
IN
-----------~
_____________ J
- tHZWE '-;
X
'.
,
" ,
,
tso
,
II" t HO -';
t LZWE
,
X
OUT ________________________
DATA ----------------~ ) <m 0088-12
(All above measurements referenced to 1.SV unless otherwise stated.)
Note:
2-36
~~~NDUcrOR =====================================================================
til
1.4 1.2 90
/ ~ ~
1.2
I~V .'"
1.0
~
! 75
"
"'" "
I- Vee = 5.0V
~ 1.0 3 TA = 25C
0
0
.!i
0.8 V U 0.8
.!i
0
a:
a:
=>
60
w
N
:J 0.6
<[
:;;
V w
N
:J
<[
0.6
c..l
w
c..l
a:
::J
45
:;; 0.4 0 30
a: 0.4 a: en
"'~
0 0 Vee; 5.0 V
z z VIN = 5.0V
l-
0.2 0.2 r----ISB i?to- 15

ISB =>
'"
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIEl'lIT TEMPERATURE (OC) OUTPUT VOLTAGE (VI

1.4 1.6 , . . . . - - - - - . . , . . . - - - - - -...... 360
1.3
1.4 I-----+-_____ ~
~ 300 ~ -
1~
!
~ " 1.2 "
~
to-
~ 240
~
,/
0
w
1.2 t-----+------;>"""--i a:
N N a:
:J 1.1 :::i =>
c..l 180
<[ ~ <[
:;;
a: ~
TA25C
~ 1.0 I--------,~~----~ '"z j
-
0 1.0 o iii 120
z """-.. z
/
I-
;:)
CI.
0.9 0.8 ~"c...---+_-------I I- Vee = 5.0 V_
;:) 60
TA = 25"C
0.8
4.0 4.5 5.0 5.5 6.0
0.6
-55
~ _ _ _ _..L..__ _ _ _ _
25
~
125
0
o /
o 1.0 2.0 3.0 4.0
I
5.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOL TAGE (V)

3.0 1.1 r------,r----~---_
TA ; 25C Vee = 5.0 V

2.5 Vee = 4.5 V TA = 25'C
VIN = 0.5 V
j 2.0 20~-4---+--'~-~-~
<.>
<.> 1.0 t----i-----+--__=_'
0 o
W w
N
:J 1.5 ~"
<[
N
:J
<[
:;; I-
....
:;;
a: w
0
z
1.0 o ~ 0.9 t----tl------+---~
/ z
-
0.5
,/ 0.8 L -_ _---''--_ _- - '_ _ _- - '
0.0
0.0 1.0 2.0 3.0 4.0 5.0 200 400 600 800 1000 10 20 40
SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz)
0088-13
2-37
~~~UaoR================================================================
Ordering Code
(os) Type Range
7 CY7CI23-7PC P13A Commercial
CY7CI23-7DC D14
CY7CI23-7LC L53
9 CY7CI23-9PC P13A Commercial
CY7CI23-9DC D14
CY7CI23-9LC L53
lO CY7CI23-lODMB D14 Military
CY7CI23-lOLMB L53
CY7CI23-10KMB K73
12 CY7C123-12PC P13A Commercial
CY7C123-12DC D14
CY7C123-12LC L53
CY7CI23-12LMB L53
CY7CI23-12KMB K73
15 CY7CI23-15DMB D14 Military
CY7C 123-15LMB L53
CY7CI23-15KMB K73
2-38
~ PRELIMINAR Y CY7C123
~~~~UaDR==============================================================
DC Characteristics
Parameters
VOH
VOL
VIR
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tACS 7,8,9,10,11
tOOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tpwE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
tSA 7,8,9,10,11
tHA 7,8,9,10,11
tscs 7,8,9,10,11
tAw 7,8,9,10,11
Document #: 38-00060-D
2-39
CY7C128
CYPRESS
Automatic power-down when The CY7C128 is a high performance tion addressed by the address present
deselected CMOS static RAM organized as 2048 on the address pins (Ao through AlO).
words by 8 bits. Easy memory expan- Reading the device is accomplished by
CMOS for optimum
speed/power sion is provided by an active LOW chip selecting the device and enabling the
enable (CE), and active LOW output outputs, CE and OE active LOW,
High speed-35 ns enable (OE) and three-state drivers. while (WE) remains inactive or HIGH.
Low active power The CY7Cl28 has an automatic power- Under these conditions, the contents of
- 660 mW (commercial) down feature, reducing the power con- the location addressed by the informa-
- 825 mW (military) sumption by 83% when deselected. tion on address pins is present on the
An active LOW write enable signal eight data input/output pins.
Low standby power
-110 mW (WE) controls the writing/reading op- The input/output pins remain in a high
eration of the memory. When the chip impedance state unless the chip is se-
SOJ package enable (CE) and write enable (WE) in- lected, outputs are enabled, and write
TTL compatible inputs and puts are both LOW, data on the eight enable (WE) is HIGH.
outputs data input/output pins (1/00 through The 7Cl28 utilizes a die coat to ensure
1/07) is written into the memory loca- alpha immunity.
discharge

A7
A6 As
1/00
OE
I/O,
Au
1/02 1/0 0
1/03
0036-2
1/04
0
~~~-?~
1/0 5
A4 4 Ag
1/06 A3 WE
CE - - -------
WE
A2 or
A, 7 A,o
1/07
O'E-........-nr--, Ao 8 CE
1/0 9 1/7
1/1 1/6
0036-1 NO It) ..... II')
~~~~~
0036-3
Selection Guide
7C128-35 7C128-4S 7C128-55
Current (mA) Military 130 100
2-40
~ CY7C128
~~~NDUcrOR =====================================================================
Maximum Ratings
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... > 200 1V
Latch-up Current .......................... > 200 rnA til
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Operating Range
Range Vee
in High Z State ...................... -0.5V to + 7.0V Temperature
Commercial OC to +700C 5V 10%
DC Input Voltage ................... -3.0Vto +7.0V

7C128
Parameters Description Test Conditions Units
Min. Max.
VOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 8.0 rnA 0.4 V
hx Input Load Current GND:::;; VI:::;; Vee -10 10 p,A
Output Leakage GND:::;; VI:::;; Vee -40
Ioz 40 p,A
Output Short
loS Vee = Max., VOUT = GND -300 rnA
Circuit Current[l]
Vee Operating Vee = Max. Commercial -25, -35, -45 120 rnA
lee
Supply Current lOUT = OmA Commercial-55 90 rnA
Military-35 150 rnA
Military-45 130 rnA
Military -55 100 rnA
Automatic CE Max. Vee, Commercial 20
ISB rnA
Power Down Current CE 2: VIH Military * 20
Capacitance [2]
I Parameters Description Test Conditions Max. Units
CIN Input Capacitance T A = 25C, f = 1 MHz 5
Vee = 5.0V pF
Notes:
2. Tested initially and after any design or process changes that may 4. T A is the "instant on" case temperature.

R148W R148W ALL INPUT PULSES
5V~------~~~_ 5V o-------V'/\o--, 3.0V----~~~_-~
OUTPUT~----.--------t OUTPUT 0 - - -....- - -..
R2 GND
30pF R2 5 pF
I_
INCLUDING
JIGAND _
- SCOPE -
255n
0036-4
I ,NCLUD,NG
_JIG AND
- SCOPE
_
-
255n
0036-5 Figure 2
0036-6
Figure la Figure Ib
~uivalent to:
THEVENIN EQUIVALENT
16m
OUTPUT O---~"~;ir'.--~O 1.73V 0036-13
2-41
~ CY7C128
~~~U~==================================================================
7C128-35 7C12845 7C12855
READ CYCLE
tLZCE CE LOW to Low Z[S] 5 5 5 ns
tHZCE CE HIGH to High Z[7, S] 15 20 20 ns
WRITE CYCLE[9]

tpWE WE Pulse Width 20 20 25 ns
tHZWE WE LOW to High Z[7] 15 15 20 ns
Notes:
5. Data I/O Pins enter high-impedance state, as shown, when OE is 9. The internal write time of the memory is defined by the overlap of
loading of the specified lor/IOH and 30 pF load capacitance. edge of the signal that terminates the write.
7. tHZOE, tHzCE and tHZWE are specified with CL = 5 pF as in Figure 10. WE is HIGH for read cycle.
1b. Transition is measured 500 mV from steady state voltage. 11. Device is continuously selected. OE, CE = VIL.
Switching Waveforms
Read Cycle No. I (Notes 10, 11)
-----,J;~~-------------------------tRc---------------------------1~.
ADDRE~~~_~~~~~~~~~H~A~~~~t~A~A-~-'-----------'-f-l~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
DATA OUT
_______
PREVIOUS DATA VALID ~ DATA VALID
__
2-42
~ CY7C128
~~~~UcrOR =====================================================================
Read Cycle No.2 (Notes to, 12)
tRC
J t ]1{
tACE
),
{
'"'0':3
tOOE
r+--tLZOEi f--tHZCE~
HIGH
IMPEDANCE
HIGH IMPEDANCE II I , I I If
DATA OUT DATA VALID
.~~~~, ~ /
J
tLZCE
f---tpu !----tpo
---j ICC
Vcc
SUPPLY _ _ _ _ _ _ 50"10
CURRENT _ =lc-ISB
0036-8

~-----------------------------twc----------------------------~
ADDRESS
~---------------- tSCE ---------------------...,..j

....,...~~1
~-----------------------tAw---------------------~4+---
r-------tSA-------------..l ~------t~E-------~
r---'------tso-------'"-
tHZWE~
DATA 110 ----------D-A-T-A-U-N-D-EF-IN-E-D------- ),.-------...;..----f
------ 0036-9

~---------------------------twc----------------------------~
-+---------tSCE - - - - - - - - t
~-----t~E-------_t
I---+---------------tso------I+-
DATA-IN VALID
tHZWE~
------------------~ HIGH IMPEDANCE
DATA 110 DATA UNDEFINED ,>-----------------------0036-10
Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-43
~ CY7C128
~~~NDUcrOR =======================================================================
1.4 1.2 120
1.2 L 1.0
~ ~
! 100
~
IV ID ~
~ 1.0 '" Z
w
2
0
cj
0.8
V U
2
0
0.8 a:
a:
::l
u
80
~
w
N
'/ w
N 0.6 w
u 60
~
:IE
a: 0.4
0.6 :::i

~
a: 0.4
Vee =5.0 V
a:
::l
0
en 40
I' Vee = 5.0 V
TA = 25"C
'"
0 0 ~
Z z VIN =5.0V
~
0.2 0.2 ~ 20
"
Iss Iss ::l
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE rC) OUTPUT VOLT AGE (V)

1.4 1.6 140
",
1.3 ~ 120
1.4 t-----+--------4 ! ",
~
100
/
Z
" ~
~
faN
1.2
....
S 1.2 r------+----~L--f
w
a:
a: 80
/ Vee =5.0 V
TA = 25C
:::.i 1.1
.............
N
:;

::l
U
~
60
V
"
:IE
a: ~
TA = 25C ~
o
1.0 t------:~~-----t Z
en
/
0
z
1.0
0.9
r---- t--- z
0.8 1-7~---+_------t
~
~
~
::l
40
/
0 20
0.8 0.6 '--_ _ _ _-'--_ _ _ _ _.....J if

4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPL Y VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)
TYPICAL POWERON CURRENT TYPICAL ACCESS TIME CHANGE NORMALIZED IcC

3.0 30.0 1.4
I
~ Vee = 5.0V
2.5 25.0 1.3 ~TA = 25C
j
0
2.0 ] 20.0
/ 2
CJ
1.2
VIN = 0.5 V
W
N
:::i 1.5

;( 15.0
/ w

0
N
:::i 1.1
c(
~
a: ~ /v :IE
a:
i 1.0 ~ 10.0 0 1.0
z
/ ~
/ ~
TA = 25C
Vee =4.50 V
~
-
0.5 5.0 0.9
~ ~
0.0
0.0 1.0 2.0 3.0 4.0 5.0
0.0
o
V 200 400 600 800 1000
0.8
~
o 10 20 30 40
0036-11
2-44
~ CY7C128
~~~~U~R==================================================================
Ordering Code
(ns) Type Range
CY7C128-35VC V13
CY7C128-35DC D14
CY7C128-35LC L53
CY7CI28-35KMB K73 Military
CY7C128-45VC V13
CY7C128-45DC D14
CY7C128-45LC L53
CY7CI28-45LMB L53
CY7CI28-45KMB K73
CY7C 128-55VC V13
CY7C128-55DC D14
CY7C128-55LC L53
CY7C128-55DMB D14 Military
CY7CI28-55LMB L53
CY7C 128-55KMB K73
2-45
~ CY7C128
~~~UcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
IcC 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tOOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
2-46
CY7C128A
CYPRESS
Features
Automatic power.down when
The CY7C128A is a high performance tion addressed by the address present
fI
deselected CMOS static RAM organized as 2048 on the address pins (Ao through AlO).
CMOS for optimum words by 8 bits. Easy memory expan- Reading the device is accomplished by
speed/power sion is provided by an active LOW chip selecting the device and enabling the
enable (CE), and active LOW output outputs, CE and OE active LOW,
High speed-20 ns enable (OE) and three-state drivers. while (WE) remains inactive or HIGH.
Low active power The CY7C128A has an automatic pow- Under these conditions, the contents of
- 440 mW (commercial) er-down feature, reducing the power the location addressed by the informa-
- 550 mW (military) consumption by 83% when deselected. tion on address pins is present on the
Low standby power An active LOW write enable signal eight data input/output pins.
-110 mW (WE) controls the writing/reading op- The input/output pins remain in a high
SOJ package eration of the memory. When the chip impedance state unless the chip is se-
TTL compatible inputs and enable (CE) and write enable (WE) in- lected, outputs are enabled, and write
outputs puts are both LOW, data on the eight enable (WE) is HIGH.
data input/output pins (1/00 through The 7C128A utilizes a die coat to en-
Capable of withstanding greater 1/07) is written into the memory loca-
than 2001 V electrostatic sure alpha immunity.
discharge
VI" of 2.2V

Vee
As
As
WE
1/0 0 OE
-1/01
110 2
1/0 3
0164-2
1/04
>8 co
U) (0 "
1/0 5
A4 Ag
1/0 6 A3 WE
CE A2 Of
We Al A10
1/07 Ao B CE
OE 1/0 9 1/7
1/1 1/6
A3 A2 Al Ao
<'to .., .... It)
0164-1
~i3~~~
0164-3
Selection Guide
7C128A20 7C128A25 7C128A35 7C128A45 7C128A55
Maximum Standby Commercial 40/20 20 20 20 20
2-47
~ CY7C128A
~~~U~================================================================
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage. '" . '" .......... '" >2oo1V
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Range Vee
in High Z State ...................... -0.5Vto +7.0V Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to +70C 5V 10%
Military [4] - 55C to + 125C 5V 10%

7C128A-20 7C128A-25, 35, 45 7C128A-55
VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 2.4 V
VIR Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee V
IIX Input Load Current GND S VI S Vee -10 10 -10 10 -10 10 IJ-A
Output Leakage GND S VI S Vee -10 -10 +10 -10 +10
loz +10 IJ-A
Output Short -300 -300 -300 rnA
los Circuit Current[ll Vee = Max., VOUT = GND
Coml. 100 100 80
Ice Supply Current lOUT = OmA Mil.~
35,45
125
100
100 rnA

Automatic CE CEI ~ VIR, 25 40
Mil. -
ISBI rnA
Power Down Current Min. Duty 20
Cycle ~ 100% 35,45 20
Automatic CE CEI ~ Vee - 0.3V, rnA
ISB2 Power Down Current VIN ~ Vee - 0.3V
orVIN S 0.3V Mil. 20 20
Capacitance [2]
Vee = 5.0V pF
Notes:
1. Not more than I output should be shorted at one time. Duration of 3. See the last page ofthis specification for Group A subgroup testing
RI481n RI481n ALL INPUT PULSES
5 v o------'\N+o--. 5V 0-----"""---.
OUTPUT 0 - -.....- - - - - . OUTPUT C>---.---... .,V~
30 pF R2
5pF ~~n GND lr1'1o90"10
I
_
INCLUDING
JIGAND _
- SCOPE -
255n
0164-4
I INCLUDING
_JIGAND
- SCOPE
_
- 0164-5
5ns \.---
0164-6
Equivalent to; THEVENIN EQUIVALENT
167S1
OUTPUT O--~'\t"'''''''\'''---O 1.73 v 0164-12
2-48
~ CY7C128A
~~~NDUcrOR ~===================================================================
7C128A-20 7C128A-25 7C128A-35 7C128A-45 7C128A-55
READ CYCLE
tRC Read Cycle Time

Min.
20
Max. Min.
25
Max. Min.
35
Max. Min.
45
Max. Min.
55
Max.
ns
til
tACE CE LOW to Data Valid 20 25 35 45 55 ns
tLZCE CE LOW to Low Z[8] 5 5 5 5 5 ns
tHZCE CE HIGH to High Z[7, 8] 8 10 15 15 20 ns
tpu CE LOW to Power Up 0 0 0 0 0 ns

tpD CE HIGH to Power Down 20 20 20 25 25 ns
WRITE CYCLE[9]
tAW Address Set-up to Write End 15 20 25 30 40 ns
tHZWE WE LOW to High Z[7] 7 7 10 15 20 ns

Notes:
5. Data I/O Pins enter high-impedance state, as shown, when OE is 9. The internal write time of the memory is defined by the overlap of
loading ofthe specified IorJ10H and 30 pF load capacitance. edge of the signal that terminates the write.
7. tHzoE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure 10. WE is HIGH for read cycle.
1b. Transition is measured 500 mV from steady state voltage. 11. Device is continuously selected. OE, CE = VIL.
Switching Waveforms
~t::~~-------------------------tRc----------------------------1~
ADDRESS-1
DATA OUT
_ _ _ _... I_;:~ : _-~ _-~ to~H~A~ ~ ~tA~A-~-.,- - - .-:,~~~~~~~~~~~~~~~~~~~~~~~~~~*_=================
PREVIOUS DATA VALID ~ DATA VALID
0164-7
2-49
~ CY7C128A
~~~U~================================================================
Read Cycle No.2 (Notes to, 12)
tRC
)t-
\.
-,'f-
J
tACE
~\:
tOOE
{
I+--tLZOEi
~'~:j
-tHZCE-
HIGH
HIGH IMPEDANCE If , , f , ~
IMPEDANCE
DATA OUT DATA VALID
"I\' \. \. \. \. I\. /
J
tLZCE
I---tpu I+--tpo
----j ICC
VCC
SUPPL Y ______ 50%
CURRENT _ =t-ISB
0164-8

~-----------------------------twc----------------------------~
ADDRESS
~-----------------------tAW----------------------~~___
1+----------tSA----------~
t+---:-----tso-------+-
DATA IN DATA-IN VA-LID
tHZWE~
DATA 1/0 ----------D-A-TA-U-N-DE-F-IN-E-D-------- >~----------oo(
------- 0164-9

~----------------------------~C----------------------------~
-t+------------- tSCE - - - - - - - + 1
t+-----------t~E------+I
~-+--------------tso--~------+i14_
DATA-IN VALID
tHZWE~
------------------~ HIGH IMPEDANCE
DATA 1/0 DATA UNDEFINED. J~----------------------0164-1C
Note: lfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-50
~ CY7C128A
~~~aoR================================================================

1.4 1.2 120
1.2
./ 1.0
~ <
! 100
le~
~
I-
~ 1.0 ~ Z
1&1
U
.!: / U 0.8
.!:
a:
a: 80
"
j
0 0.8 0 u
1&1
N
./ 1&1
N 0.6 1&1
u 60
~~
~ 0.6 ~ a: Vee = 5.0 V
C[ C[ j TA = 25C
~ ~
a:
0 0.4
a: 0.4 Sl 40
'"
0 Vee a5.0V I-
Z z VIN =5.0V j
0-
0.2 0.2 I- 20
'"
ISB 'SB j
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPL Y VOLTAGE (VI AMBIENT TEMPERATURE ('CI OUTPUT VOLTAGE (VI

SUPPLY VOLTAGE
VS. vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.6 140
.",
< 120
)~
1.3
1.4 ~----+------___4 !
I-
'" ~'" ffia:
100
~
0
1&1
1.2
S
N
1.2 t-----+----~......_i a:
j
80 / Vee =5.0V
TA = 2S'C
N
~ 1.1
"'" ............. ~
C[
u
~ 60
I
C[
TA =25'C ~ 1.0 ~----,...::....-----___4 z
~
a: ............. o iii
/
-
0 1.0 I- 40
z ~ Z j
0.9 0.8 .....,."c...---+------___4 0-

I-
0
j
20
/
0.8 0.6 L..._ _ _ _L..._ _ _ _ _.,j V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0

SUPPLY VOLTAGE
VS. vs. OUTPUT LOADING vs. CYCLE TIME
3.0 30.0 1.4
I
2.5 25.0
.,.-- Vee =5.0V
1.3 - T A = 25'C
E
0
2.0 ! 20.0 / .!:
0
c.>
1.2
VIN =0.5 V
1&1
N
~ 1.5 ;''"" 15.0
/ 1&1
N
~ 1.1
C[
~
a:
I-
...J
1&1
/11' C[
~
a:
1.0 o 10.0 1.0
i 0
z ~
/ ~
/ TA = 25'C
vee =4.50 V ~
0.5 5.0 0.9
~
0.0
..-V 0.0 V 0.8
~
0.0 1.0 2.0 3.0 4.0 5.0 o 200 400 600 800 1000 o 10 20 30 40
SUPPLY VOLTAGE (VI CAPACITANCE (pFI CYCLE FREQUENCY (MHz)
0164-11
2-51
~ CY7C128A
~~~~UcrOR==================================================================
Ordering Code
(ns) Type Range
20 CY7C128A-20PC P13 Commercial
CY7C128A-20VC V13
CY7C128A-20DC D14
CY7C128A-20LC L53
CY7C128A-25VC V13
CY7C128A-25DC D14
CY7C128A-25LC L53
CY7C128A-25DMB D14 Military
CY7C128A-25LMB L53
CY7C128A-35VC V13
CY7C128A-35DC D14
CY7C128A-35LC L53
CY7C128A-35LMB L53
CY7C128A-35KMB K73
CY7C128A-45VC V13
CY7C128A-45DC D14
CY7C128A-45LC L53
CY7C128A-45LMB L53
CY7C128A-45KMB K73
CY7C128A-55VC V13
CY7C128A-55DC D14
CY7C128A-55LC L53
CY7C128A-55LMB L53
CY7C128A-55KMB K73
2-52
~ CY7C128A
~~~UcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tOOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
2-53
CY7C130/CY7C131
CY7C140/CY7C141
CYPRESS
SEMICONDUCTOR 1024 X 8 Dual Port
Static RAM
0.8 micron CMOS for optimum The CY7C130/CY7C140/CY7C131/ (WE), and Output Enable (OE). Two
speed/power CY7C141 are high speed CMOS lK x flags are provided on each port, BUSY
Automatic power-down 8 Dual Port Static RAMS. Two ports and INT. BUSY signals that the port is
are provided permitting independent trying to access the same location cur-
TTL compatible access to any location in memory. The rently being accessed by the other port.
Capable of withstanding greater CY7C130/CY7C131 can be utilized as INT is an interrupt flag indicating that
than 2001V electrostatic either a stand-alone 8-bit Dual Port data has been placed in a unique loca-
discharge Static RAM or as a MASTER Dual tion by the other port. An automatic
Fully asynchronous operation Port RAM in conjunction with the power down feature is controlled inde-
Master CY7C130/CY7C131 CY7Cl40/CY7C141 SLAVE Dual pendently on each port by the Chip En-
easily expands data bus width to Port device in systems requiring 16-bit able (CE) pin.
16 or more bits using SLAVE or greater word widths. It is the solu- The CY7C130/CY7C140 are available
CY7CI40/CY7CI41 tion to applications requiring shared or in both 48-pin DIP and 48-pin LCC.
buffered data such as cache memory The CY7C131/CY7C141 are available
BUSY output flag on CY7C130/ for DSP, Bit-Slice, or multiprocessor
CY7C131; BUSY input on in both 52-pin LCC and PLCC.
designs.
CY7CI40/CY7CI41 A die coat is used to insure alpha im-
Each port has independent control munity.
INT flag for port to port pins; Chip Enable (CE), Write Enable
communication

CEl
R!Wl
BU~l 3
DEL or.. INTl
OEl
~~==:43hl r;~===~:: Aol 6
I/OOl ---+M:::-H":=::'..... '-+I-=-=H"::::II-6:-f--- I/OSR
I/0 7l ----L.::.:..H....:..:.....J" VL..::..::J-L:::J-.....- - I/07R
BUSYl(l) - -......- - _..... '----~~--+ BUSYR(l)
...~l ---+:-+r-::::-::-l
Aol---+:...t...:::::::...J
0114-1
Notes:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pullup resistor. 0114-2
CY7Cl40/CY7C141 (Slave): BUSY is input. DIP
2. Open drain outputs: pullup resistor required. Top View
Selection Guide
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Shaded area contains preliminary information.
2-54
CY7C130/CY7C131
fiA .
~NDUcrOR
Maximum Ratings
=====================================================================
CY7C140/CY7C141
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... > 2001 V
Power Applied .................... - 55C to + 125C Latch-up Current .......................... > 200 rnA
Range Vee
in High Z State .................. , ... -0.5V to + 7.0V Temperature
DC Input Voltage ................... - 3.5V to + 7.0V Commercial OC to + 70C SV 10%
Output Current into Outputs (Low) ............. 20 rnA Military [6) - SSoC to + 12SoC SV 10%
Parameters Description Test Conditions
CE = VIL
Vee Operating
ICC Outputs Open
Supply Current
f = fMAX
Standby Current CEL and CER ;;:: VIH
ISBl Both Ports, TTL Inputs f= fMAX
CEL or CER ;;:: VIH
Standby Current
ISB2 Active Port Outputs Open
One Port, TTL Inputs
f=
Both Ports CEL and CER
Standby Current ;;:: Vee - 0.2V
ISB3
Both Ports, CMOS Inputs VIN;;:: Vee - 0.2Vor
VIN S 0.2V, f = 0
One Port CEL or CER

;;:: Vee - 0.2V
Standby Current
ISB4
One Port, CMOS Inputs
VIN ;;:: Vee - 0.2V or VIN S 0.2V f-----....,
Active Ports Outputs Open
f = fMAX

Capacitance [4]
Parameters Description Test Condtions Max. Units
pF
Notes:
3. Duration of the short circuit should not exceed 30 seconds. 6. T A is the "instant on" case temperature.
4. Tested initially and after any design or process changes that may 7. See the last page of this specification for Group A subgroup testing
affect these parameters. information.
5. BUSY and !NT pins only.
2-55
CY7C130/CY7C131
fin .
~~UcrOR==============================================================~~
CY7C140/CY7C141
5V
R1893n R1893n
_~280.n
5Vo-------~~~ 5Vo-------~~~
OUTPUT O-----_----~ OUTPUT 0----_----.......

BUSY
OR
R2 5 pF jjiff
'NCLUD'NGI30 pF 347n
JIG AND
SCOPE
'NCLUD,Nl
JIG AND
SCOPE -=
I 30P
F'
0114-5 0114-4
Figure 1 Figure 2 Figure 3. BUSY Output Load

(CY7C130/CY7C131 Only)
250n ALL INPUT PULSES
OUTPUT O~--.-J,\N o 1.40V
0114-7
3.0V----~~--"""'i..
GND
0114-6
Figure 4

2-56
CY7C130/CY7C131
5A~NDUcroR =====================================================================
.
Switching Characteristics Over Operating Range[7, 9] (Continued)

CY7C140/CY7C141
------------r-----------~----------.----.

CY7C140/CY7C141 Only
Notes:
8. Data I/O pins enter high impedance state, as shown when OE is held 13. WE is HIGH for read cycle.
LOW during write. 14. Device is continuously selected OE, CE = VIL.
9. Test conditions assume signal transition times of 5 ns or less, timing 15. Address valid prior to or coincident with CE transition LOW.
reference levels of 1.5V, input pulse levels ofOV to 3.0V and output 16. A write operation on Port A, where Port A has priority, leaves the
loading of the specified lor/loH and 30 pF load capacitance. data on Port B's outputs undisturbed until one access time after one
10. tHzOE, tHZCE, and tHZWE are specified with CL = 5 pF in Figure 2. of the following:
Transition is measured 500 m V from steady state voltage. A. BUSY on Port B goes HIGH.
11. At any given temperature and voltage condition, tHZCE is less than B. Port B's address toggled.
C. CE for Port B is toggled.
12. The internal write time ofthe memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a D. WE for Port B is toggled.
write and either signal can terminate a write by going HIGH. The 17. These parameters are measured from the input signal changing, until
data input setup and hold timing should be referenced to the rising the output pin goes to a high impedance state.
edge of the signal that terminates the write. 18. For master/slave combinations twc = tpwE + tBLA.
Switching Waveforms
iRead Cycle No.1 (Notes l3, 14)
*_
Either Port Address Access
~
---------------------------tRC----------------------------:1~.
_RE"~._ _ _
_____~__HA_____tA__
______-_----- A_~.'
DATA OUT _ PREVIOUS DATA VALID DATA VALID
------------------------------------- 0114-8
2-57
CY7C130/CY7C131
(inS~~aDR==============================================================
. CYPRFSS CY7C140/CY7C141

Either Port CE/OE Access
~ f
t ACE I--tHZCE -
~~ I t HZOE
tooE
I-tLZOE -
- tLzcE -
..,r-f 111111111, III
DATA OUT DATA VALID
- tpu r\.""""" """"\.\.\.\. -tpo

~
ICC _ _ _ _ _ _..1
ISB 1 1- 0114-9
Timing Waveform of Read with BUSY (Note 13)

ADDRESS R ADDRESS MATCH
~ J
(.
ADDRESS L ADDRESS MATCH
~
BUSYL
'\-tBOO --
~CvAUO
JI\..-
toDD
twoo
0114-10
Write Cycle No.1 (Notes 8, 12)

Either Port
twc
~
''f.
,,
ADDRESS
,I tSCE
\ ,\; j"-/77 [7///
tAW tHA-
i--- tSA ----j tpWE
~-~-~
L
tHO I
tso 1
.L DATA VALID ){
L//~ ~ \, \
T HIGH IMPEDANCE
DOUT I I I I I I
0114-12
2-58
CY7C130/CY7C131
fin CYPRESS
s~~u~==========================================================~~
CY7C140/CY7C141

Either Port
twc
ADDRESS j~
tSCE
J
tHA-
-
\.\.\ \.\.\.'k "-/ / / /L
tAW
I--- t S A 4 tpWE
\.\. k- f-
tHO
I-tso
~ DATA VALID X
~tHZWE--j ! - - tLZWE -
~ -y -y '\.'\.'\.~.~ ~~ '\. '\..~ HIGH IMPEDANCE L
DATAOUT -, ~ I " I -#- ~~
I
" " 0114-13
Busy Timing Diagram No.1 (CE Arbitration)

CEL Valid First:
=:::)(
ADDRESS
LAND R
ADDRESS MATCH
X
CE L
CER
tpsh
BUSYR
~LC=1. t"HCj
0114-14
CER Valid First:

=:::)(
ADDRESS
LAND R
ADDRESS MATCH
X
CER
CE L t'PSh
BUSYL
"LC---=il t"HCj
0114-15
2-59
CY7C130/CY7C131
WA . .
~~UcrOR==================================================================
CY7C140/CY7C141
Busy Timing Diagram No.2 (Address Arbitration)

Left Address Valid First:
t Rc OR twc
ADDRESS L ADDRESS MATCH ADDRESS MISMATCH
ADDRESS R
t BLA , t
BHAJ
BUSYR
0114-16
Right Address Valid First:

t RC OR twc
ADDRESS R ADDRESS MATCH ADDRESS MISMATCH
ADDRESSL
t BLA , t
BHAJ
BUSYL
0114-17
Busy Timing Diagram No.3

Write with BUSY (Slave: CY7C140/CY7C141) (Note 19):
-,t~-------------tpWE----------~--~~ ________
BU:: -t_t_WB__~
___________ r= Iw~ ~ 0114-11
2-60
CY7C130/CY7C131
fiA cy CY7C140/CY7C141
S~~UcrOR=====================================================================
Interrupt Timing Diagrams
Left Side Sets INTR:
~---------twc--------~
ADDRL ----'I~ ____ ____________

~ ~~~ ________ __J
0114-18
Right Side Clears INTR:
________________________________-JI
INTR
0114-19
Right Side Sets INTV

~----------twc--------~
ADDRR ____JI~~____________________~~~-------------J~-------
0114-20
Left Side Clears INTV
________________________________-JI
INTL
0114-21
2-61
CY7C130/CY7C131
5n~UcrOR =====================================================================
. CY7C140/CY7C141

1.4 1.2 120
1.2
/ 1.0
~ ;(
!
...z 100
~
Icy
11 1.0 ~ w
U
!t /" U 0.8 II:
II:
80
"
.!t ::::l
0.8 cw
@ U
N
::::;
ct
0.6 V N
::::;
0.6 w
u
II:
60
,,~ Vee = 5.0 V
~
II:
0.4
'"
:E
II: 0.4
=5.0 V
::::l
0
en
...::::l 40
TA = 25'C
'" "
0 0 Vee
Z z VIN =5.0 V
0.2 Isa
0.2 '---Isa ...::::l
~
20
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPL Y VOLTAGE (V~ AMBIENT TEMPERATURE ('C~ OUTPUT VOLTAGE (V)

1.4 1.6 140
;( 120 ./"
1.3
1.4 t - - - - - t - - - - - - - 1 ! //
... 100
~ ~ Vee = 5.0 V
~
~
1.2
....
S
N
1.2 1------I-----"7"-~ II:
II:
::::l
80
/ TA = 25'C
N
::::; 1.1
.............
::::; U
V
'" I"-......
TA = 25'C
'o"
~ 1.0 I-------::::l~----__I
~
Z
60
:E
II: in
...::::l /
-
1.0
0
z r---. Z 40
0.9 0.8 1-::;;,otil=----t-------1 ...::::l

~
0 20
/
0.8 0.6 ......- - - -......- - - - -..
V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V~ AMBIENT TEMPERATURE ('C~ OUTPUT VOLTAGE (V)

3.0 30.0 1.25 r---......,----,..---..,
~ Vee = 5.0 V
2.5 25.0 TA = 25'C
j 2.0 ] 20.0
L .!t
c.J
VIN = 0.5 V
1.0t----t----+--~::It
~
N
/ aN
::::;
~
1.5 ;; 15.0 ;'
:E
II:
~
1.0
~C 10.0
/ ioz 0.75 t----i.,."----+---~
TA =25'C
/ /V Vee =4.50 V
0.5
0.0
0.0 1.0 2.0
SUPPLY VOLTAGE
-- V
3.0 4.0
(V~
5.0
5.0
0.0 V
a 200 400
CAPACITANCE
600
(pF~
800 1000
0.501~0---~20:----30'---......
CYCLE FREQUENCY
40
(MHz~
0114-23
2-62
CY7C130/CY7C131
fin .
~~UcrOR =====================================================================
Pin Configurations
CY7C140/CY7C141
....ol~ a:11llil::1~
z _ ::>~I'" 0" ~
....0....0 -J ..10 O!
01'"0 ol!z 0 ><>1' '" ::>I!z
'" Q) ' " Q) _ z0
ol"'l!z r'::>~I'"
...J...J ..JV)I "'I~
....o tll"'~::>I!zI'"
-J 0::1 (I) Q: 0::
All
A2l
8
9
7 6 5 4 3 2 111525150494847
'-' 46
45 All 7
~ - -
-<O_CIla::::U>Ua::::aII_O
6 5 4 3 2111484746454443
'-' 42
------- AOR
A3l 10 44 A2l 8 41 A1R
A4l 11 43 A3l 9 40 A2R
ASl 12 42 A4l 10 39 A3R
ASl 13 41 ASl 11 38 A4R
A7L 14 40 ASl 12 37 A5R
ASl 15 39 A7l 13 36 ASR
A9l 16 38 ASl 14 35 A7R
I/OOl 17 374 A9l 15 34 ASR
I/Oll 18 364 I/OOL 16 33 A9R
1/0 2l I 19 354 1/0 1L 17 32 1/0 7R
1/03l 20 34 1/0 2L 18 31 I/OSR
21 2223242526 27282930313233 1920 2122 232425~~!8~::0 j
..J ..J ...J ...J...JO .a::: Q: Ill:: Q:; a::: ac:
~g~~~5~~~~g~
0114-3 0114-22
52-Pin LCC/PLCC 48-Pin LCC
Top View Top View
Military Military
45 Commercial 45 Commercial
Military Military
Military Military
aded area contains preliminary information.

2-63
CY7C130/CY7C131
fm CYPRESS CY7C140/CY7C141
S~IOO~UcrOR========================================~==================~~
DC Characteristics
Parameters Subgroups Parameters Subgroups
VOH 1,2,3 ISB4 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
lOS 1,2,3
Icc 1,2,3
ISBI 1,2,3
ISB2 1,2,3
ISB3 1,2,3
READ CYCLE BUSY /INTERRUPT
7,8,9,10,11 TIMING (Continued)
tAA
7,8,9,10,11 tOINR 7,8,9,10,11
tOHA
7,8,9,10,11 tEINR 7,8,9,10,11
tACE
tINR 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE BUSY TIMING
tWB[t] 7,8,9,10,11
tSCE 7,8,9,10,11
7,8,9,10,11 tWH 7,8,9,10,11
tAw
7,8,9,10,11 tBDD 7,8,9,10,11
tHA
7,8,9,10,11 tDDD 7,8,9,10,11
tSA
7,8,9,10,11 tWDD 7,8,9,10,11
tpWE
tSD 7,8,9,10,11
tHD 7,8,9,10,11
BUSY/INTERRUPT
TIMING
tBLA 7,8,9,10,11
tBHA 7,8,9,10,11
tBLC 7,8,9,10,11
tBHC 7,8,9,10,11
tps 7,8,9,10,11
tWINS 7,8,9,10,11
tEINS 7,8,9,10,11
tINS 7,8,9,10,11
Note:
1. CY7Cl40 only.
2-64
CY7C132/CY7C136
CY7C142/CY7C146
2048 X 8 Dual Port

Static RAM
0.8 micron CMOS for optimum The CY7C 132/CY7C142/CY7C 136/ flags are provided on each port. In ad-
speed/power CY7C146 are high speed CMOS 2K x dition, an interrupt flag (INT) is pro-
Automatic power-down 8 Dual Port Static RAMs. Two ports vided on each port of the 52-pin LCC
are provided permitting independent or PLCC versions. BUSY signals that
TTL compatible access to any location in memory. The the port is trying to access the same
Capable of withstanding greater CY7C132/CY7C136 can be utilized as location currently being accessed by
than 2001 V electrostatic either a stand-alone 8-Bit Dual Port the other port. On the LCC/PLCC
discharge RAM or as a MASTER Dual Port versions, INT is an interrupt flag indi-
Fully asynchronous operation RAM in conjunction with the cating that data has been placed in a
CY7C142/CY7C146 SLAVE Dual unique location by the other port.
MASTER CY7C132/CY7C136 Port device in systems requiring 16-Bit
easily expands databus width to An automatic power-down feature is
or greater word widths. It is the solu- controlled independently on each port
16 or more bits using SLAVE
CY7C142/CY7C146 tion to applications requiring shared or by the Chip Enable (CE) pin.
buffered data such as cache memory
BUSY output flag on CY7C132/ for DSP, bit-slice or multiprocessor de- The CY7C132/CY7C142 are available
CY7C136; BUSY input on signs. in both 48-pin DIP and 48-pin LCe.
CY7C142/CY7C146 The CY7C136/CY7C146 are available
Each port has independent control in both 52-pin LCC and 52-pin PLCC.
INT flag for port to port pins; Chip Enable (CE), Write Enable
communication (LCC/PLCC A die coat is used to insure alpha im-
(WE), and Output Enable (OE). BUSY munity.
versions)

R/Wl ---1_-a-, eEL 1 Vee
crl ~----~ R/Wl eER
BUSYl R/WR
OEl OER A10l BUSYR
A10 l ----f;l::::::;-l .---+:-1--- A10R Orl A10R
A7l ----I''+--> .......t''+---A7R 43 OrR
I/OOl ---+~-=:-l-f=~1+-' L-+I-==l-f=~I--- I/0 9R AOR
A1R
I/0 7l ---4":='J-t......::...:........J L..::"':"""'.J-l":='.J--'+--- I/0 7R A2R
BUSYl (1) +--------' r--~'----, '-------1---+ BUSYR(1)
ASl ---+:-+1"--:::::-1 r:::::::-,..,+--- ASR

Acl ---+"-+L":=:.:..:..J L..::::':":"j.-.;+--_AOR
Notes: 0106-1 GND
1. CY7C132/CY7C136 (MASTER): BUSY is open drain output and requires pullup resistor.
CY7C142/CY7C146 (SLAVE): BUSY is input. DIP 0106-2
2. Open drain outputs: pullup resistor required. Top View
Selection Guide
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
ihaded area contains preliminary information.
2-65
CY7C132/CY7C136
(;n~U~==================================================================
. CY7C142/CY7C146
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage .......... , .... , ... " >2001V
Ambient Temperature with (per MIL-STD-883 Method 3015)
(Pin 48 to Pin 24) .................... -O.SV to + 7.0V
Range Vee
in High Z State ...................... - O. SV to + 7.0V Temperature
DC Input Voltage ................... - 3.SV to + 7.0V Commercial OC to +70C 5V 1O%
Output Current into Outputs (Low) ............. 20 rnA Military [7] -55C to + 125C 5V 1O%
Output Short [3]

lOS
Circuit Current
Vee Operating
Icc
Supply Current
Standby Current
ISBl
Both Ports, TTL Inputs
CELor CER ~ VIH

Standby Current
ISB2 Active Port Outputs Open rnA
One Port, TTL Inputs
f = fMAX
Both Ports CEL and CER
Standby Current ~ Vee - O.2V
ISB3 rnA
Both Ports, CMOS Inputs VIN ~ Vee - 0.2Vor
VIN ::;: 0.2V, f = 0 Military 15 15
One Port CEL or CER

~ Vee - 0.2V 85 70
Standby Current VIN ~ Vee - 0.2Vor rnA
ISB4
One Port, CMOS Inputs VIN::;: 0.2V
Active Ports Outputs Open Military 105 85
f = fMAX
Capacitance [4]
pF
CoUT
Notes:
3. Duration of the short circuit should not exceed 30 seconds. 6. BUSY and INT pins only.
affect these parameters. 8. See the last page of this specification for Group A subgroup testing
5. LCC version only. information.
2-66
CY7C132/CY7C136
(;Jl
. CY7C142/CY7C146
~~UcrOR =====================================================================
R18930 R18930 5V
5Vo-------~~~ 5Vo-------~AA~
OUTPUT o-----~---.............
R2
OUTPUT 0 - - - -.....- - - - 4
5pF R2
_~280.n
BUSY
3470 OR
'NCLUD'NGI30 pF 3470
JIG AND 'NCLUD'Nl INT
JIG AND
SCOPE
SCOPE -= I 30P
F"
0106-4 0106-5
Figure 1 Figure 2 0106-6
Figure 3. BUSY Output Load
(CY7C132/CY7C136 Only)
2500 ALL INPUT PULSES
OUTPUT O~-~'\N\Ir---"""O 1.40V
0106-8 3.0 V - - - - - ...- - - -...
GND -....:.::.:~
5 ns 5 ns
0106-7
Figure 4
Switching Characteristics Over Operating Range [8, 10]
haded area contains preliminary information.

2-67
CY7C132/CY7C136
5n .
~NDUcrOR=====================================================================
Switching Characteristics Over Operating Range [8, 10] (Continued)
CY7C142/CY7C146
------------r-----------~----------._--_.

'CY7CI42/CY7CI46 Only
Notes:
9. Data I/O pins enter high-impedance state, as shown, when OR is 14. WE is HIGH for read cyele.
held LOW during write. 15. Device is continuously selected. OE, CE = VIL.
10. Test conditions assume signal transition times of 5 ns or less, timing 16. Address valid prior to or coincident with CE transition LOW.
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output 17. A write operation on Port A, where Port A has priority, leaves the
loading of the specified Ior/IOH and 30 pF load capacitance. data on Port B's outputs undisturbed until one access time after one
11. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure of the following:
2. Transition is measured 500 m V from steady state voltage. A. BUSY on Port B goes HIGH.
12. At any given temperature and voltage condition, tHZCE is less than B. Port B's address toggled.
C. CE for Port B is toggled.
13. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a D. WE for Port B is toggled.
write and either signal can terminate a write by going HIGH. The 18. These parameters are measured from the input signal changing, until
data input setup and hold timing should be referenced to the rising the output pin goes to a high impedance state.
edge of the signal that terminates the write. 19. For master/slave combinations twc = tpwE + tBLA'
Switching Waveforms
Either Port-Address Access
~t:~~---------------------------tRC----------------------------~:1~
ADDRE~_~~I_;~-_~ - ~ -_=~t_O-_H-A~ ~ ~ ~__A--_.-!------------.-,----------------------------~------------------

DATA OUT
______
PREVIOUS DATA VALID DATA VALID
--------------------------------------- 0106-
2-68
CY7C132/CY7C136
(;Jl CYPRESS
SEMICONDUCTOR ================================================================
CY7C142/CY7C146

Either Port-CE/OE Access
, }"-
\
. , t ACE I--tHZCE -
OE
\ )
tOOE t HZOE
- t LzoE -
- tLZCE -
.J
-1-/////1///////'
DATA OUT
- tpu ~'""""",,"
DATA VALID
---tpo
..,
ICC _ _ _ _ _ _,.,)
IS8 1- 0106-10
Read Cycle No.3 (Note 14)

READ with BUSY
ADDRESS R ADDRESS MATCH ~
"'~
ADDRESS L X ADDRESS MATCH
~
-f-
t BOO -
-
DOUTL
twoo
tO~~
-
)rVALID
0106-11

Either Port
twc
ADDRESS
"
tSCE
~{ '-/ / / //77
\ tAW t HA -
_tSA-==:L t pWE -
~,~ f-
tHO I
tso I
7:
3- DATA VALID )I(
DOUT -"I
///~
I I I I I Z
HIGH IMPEDANCE
r" " 0106-13
2-69
CY7C132/CY7C136
fin . CYPRESS
s~~O~UcrOR==================================================================
CY7C142/CY7C146

Either Port
ADDRESS
twc
) --
tSCE tHA-
\.\.\ \.\.\.\. J/// //

tAW
- tSA--=-1 tpWE
'I
\.\. tHO
I-tso
:r
~
DATA VALID
f+- t HZWE --j ! - - tLZWE -

HIGH IMPEDANCE
DATAOUT " ""
III
~ ~
--, --, " " " " " "
III 111-77
~ ~
.,
,,~ 1 1
" " 0106-14
BUSY Timing Diagram No.1 (CE Arbitration)

CEL Valid First:
ADDRESS
LAND R
=:x ADDRESS MATCH
X
CEL
t..S
CE R
BUSYR
b 1BLC=---t t.'HCj
0106-15
CER Valid First:

ADDRESS
LAND R
=:x ADDRESS MATCH
X
CER
CE L t.PSb BL
BUSYL
I C=1 tl.HCj
0106-16
2-70
CY7C132/CY7C136
5n~~~UcrOR==================================================================
CY7C142/CY7C146
BUSY Timing Diagram No.2 (Address Arbitration)

LEFT Address Valid First:
1----tRc OR twc----J
ADDRESS L _ _...."I'-_ _~_A_D_DR_E_S_S_M_A_TC_H""'I'Io..._A_D_DR_E_S_S_M_IS_M_AT_C_H_" '-_ _ _ _ __
_________
ADDRESSR _ _ _ _ _ _-JI'-_ _ _ _ _
tB_~~, tBHAJ___________
-+___________J
BUSYR
---- 0106-17
BUSY Timing Diagram No.2

RIGHT Address Valid First:
1----tRc OR twc---+l
ADDRESS R _ _ _ I"-_ _ _ _ _ _ _ _JI'....._A_D_DR_E_S_S_M_IS_M_AT_C_H_" '-_ _ _ _ __
______ __
ADDRESSL _ _ _ _ _-J'I'-_ _ _ _ _ _
BUSY L
~ tB_~~, tBHAJ___________
-+___________-'
---- 0106-18
BUSY Timing Diagram No.3

WRITE with BUSY (SLAVE: CY7C142/CY7C146) (Note 20):
-,t~-------tpwE-----~-~
WE I-- 'we -I' r== ====1----

'WH
BUSY~~____________________-J~
0106-12
2-71
. CY7C132/CY7C136
(;n . CYPRFSS .
S~I~U~================================================================
CY7C142/CY7C146

Interrupt Timing Diagram (Note 5)
LEFf Side Sets INTR:
~---------~c--------~
ADDRESS L __ ~rl~ ____ ~ ________ ~ __ ~~~ ________- J
INTR
0106-19
RIGHT Side Clears INTR:
INTR
--------------------------------~
0106-20
RIGHT Side Sets INTV
ADDRESS R ____ rl~ ____ ~ ________ ~--~~~----------J
0106-21
LEFf Side Clears INTV
INTL
--------------------------------~
0106-22
2-72
CY7C132/CY7C136
5n ~~NDUcrOR ==================================================================~
CY7C142/CY7C146

1.4 1.2 120
./ ~
.E
CD
'".:;
1.2
1.0
leV CD
'"oj
1.0
~
~
~
100
V 0.8 II:
a: 80
'"
.!: .!: ~
0.8 0 u
S
N
~
<t 0.6 V w
N
~
ct
0.6 w
u
II:
~
60
~ Vee = 5.0 V
TA = 25~C
~ ~
II: II: 0.4 ~ 40
'"
0 0.4 0 Vee = 5.0 V ~
Z Z VIN = 5.0 V
~
0.2 0.2 1--156 ~ 20
'"
158 ~
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPl V VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)

1.4 1.6 _----'T"""-----....., 140

/V """
1.3 120
1.4 I------+------~ .E
~
<l <l 100
~ Vee = 5.0 V
:!
filN
1.2 :!
@ 1.2 I------+----.....,.,c..~ II:
II: 80
/ TA = 25~C
~ 1.1
~
N
::;
~
u /
<t ............. TA = 25'C
<{
~ 1.0 I-----~~----~
:..:
Z
60
~
II:
0
z
1.0
..............
I---r---
o
z
<ii
~ 40 1
0.9
0.8 h " L . . - - - + - - - - - - - I
~
~
~
20
7
0.8 0.6 L-_ _ _ _...L.._ _ _ _ _.....I
0
V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPl V VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)

3.0 30.0 1.25.._---r------,.,-----,
2.5 25.0
.,-- Vee = 5.0 V
TA = 25C
g 2.0 ] 20.0
/ u
u
VIN = 0.5 V
filN
;:j 1.5 :t
<l
<l
15.0
/ @
N
::i
ct
~
a: 8o /1/ ct
~
II:
1.0 10.0 oZ
51
/ 5.0
)7 TA : 25C
Vee = 4.50 V
0.5
0.0
0.0 1.0 2.0
SUPPl Y VOLT AG E (V)
---V 3.0 4.0 5.0
0.0 V
o 200 400 600
CAPACITANCE (pF)
800 1000
0.50 L-_ _ _L-_ _.....J'--_ _--I
10 20 30
CYCLE FREQUENCY (MHz)
40
0106-25
2-73
CY7C132/CY7C136
fin~~NDUcroR=====================================================================
Pin Configurations
CY7C142/CY7C146
7 6 5 4 3 2 1525150494847
J11iI' ~r=' 1~1..t
~~ ~ gl.3'I~~
o<m",u>u",m<o
'"
'T~ ~1.3'
AIL 8 46
6 5 4 3 2LU484746454443
A2L 9 45
AIL 7 42 "'oR
A3L 10 44
A2L 8 41 AIR
A4L 11 43
A3L 9 40 A2R
A5L 12 42
A4L 10 39 A3R
A6L 13 41
A5L 11 38 A4R
A7L 14 40
A6L 12 37 AsR
ASL 15 39
A7L 13 36 ASR
A9L 16 38
ASL 14 35 A7R
I/OOL 17 37
AgL 15 34 ASR
I/OIL 18 36
I/OOL 16 33 A9R
I/0 2L 19 35
I/OIL 17 32 I/0 7R
I/0 3L 20 34
21222324252627282930313233
1/0 2L 18 31 I/0 6R
192021222324252627282930
52-Pin LCC/PLCC 0106-23 0106-24

48-Pin LCC
Top View Top View
Military Military
Military Military
Military Military

2-74
CY7C132/CY7C136
(ijiS~~UaoR================================================================
CYPRESS CY7C142/CY7C146
DC Characteristics
Parameters
VOH
VOL
VIR
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
Parameters
ISB4
Subgroups
1,2,3

IIX 1,2,3
IOZ 1,2,3
los 1,2,3
Icc 1,2,3
ISBI 1,2,3
ISB2 1,2,3
ISB3 1,2,3
READ CYCLE BUSY/INTERRUPT
7,8,9,10,11 TIMING (Continued)
tAA
7,8,9,10,11 tOINR 7,8,9,10,11
tOHA
tEINR 7,8,9,10,11
tACE 7,8,9,10,11
tlNR 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE BUSY TIMING
7,8,9,10,11
tWB[I] 7,8,9,10,11
tSCE
tWH 7,8,9,10,11
tAW 7,8,9,10,11
7,8,9,10,11 tBDD 7,8,9,10,11
tHA
tDDD 7,8,9,10,11
tSA 7,8,9,10,11
tWDD 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
BUSY/INTERRUPT
TIMING
tBLA 7,8,9,10,11
tBHA 7,8,9,10,11
tBLC 7,8,9,10,11
tBHC 7,8,9,10,11
tps 7,8,9,10,11
tWINS 7,8,9,10,11
tEINS 7,8,9,10,11
tINS 7,8,9,10,11
~ote:
I. CY7Cl42 only.
2-75
CY7C147
CYPRESS
Automatic power-down when The CY7C147 is a high performance Reading the device is accomplished by
deselected CMOS static RAM organized as 4096 taking the chip enable (CE) LOW,
words by 1 bit. Easy memory expan- while write enable (WE) remains
CMOS for optimum
speed/power sion is provided by an active LOW chip HIGH. Under these conditions the
enable (CE) and three-state drivers. contents of the memory location speci-
High speed-2s ns The CY7C147 has an automatic pow- fied on the address pins will appear on
Low active power er-down feature, reducing the power the data output (DO) pin.
- 440 mW (commercial) consumption by 80% when deselected. The output pin stays in high impedance
- 60S mW (military) Writing to the device is accomplished state when chip enable (CE) is HIGH
Low standby power when the chip enable (CE) and write or write enable (WE) is LOW.
-ssmW enable (WE) inputs are both LOW.
Data on the input pin (01) is written
TTL compatible inputs and into the memory location specified on
outputs the address pins (An through All).
Capable of withstanding
greater than 2000V
electrostatic discharge
r---------c~----Ol Ao Vee
Al A6
A2 A7
A3 A8
A4 Ae
As A1D
DO A11
WE 01
J---+---1 > - - - - 0 0
GNO CE
0019-2
u
,....o(,)u)
><
A2 A7
A3 4 A8
A4 A9
A5 A 10
DO 7 All
0019-1
I~ ~ I~ is
0019-3
Selection Guide
7C147-25 7C147-35 7C147-45
Maximum Access Commercial 25 35 45
Time (ns)
Military 35 45
Current (rnA)
Military 110 110
Current (rnA)
Military 10 10
2-76
~ CY7C147
~~~NDUcroR ==================================================================~
Maximum Ratings
+ 125C
Latchup Current .......................... > 200 rnA
Operating Range
II
(Pin 18 to Pin 9) ..................... -0.5V to + 7.0V
Range Vee
in High Z State ...................... - O.5V to + 7.0V Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OOCto +700C 5V 10%
Output Current into Outputs (Low) ............. 20 rnA Military [3] - 55C to + 125C 5V 10%
7C14725 7CI4735,45
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min. IOH = -4.0mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min. IOL = 12.0mA 0.4 0.4 V
VIH Input High Voltage 2.0 6.0 2.0 6.0 V
VIL Input Low Voltage -3.0 0.8 -3.0 0.8 V
IIX Input Load Current GND S VI S Vee -10 +10 -10 +10 p,A
Output Leakage GND s Vo s Vee -50 -50
Ioz +50 +50 p,A
Output Short [I]
los Vee = Max. VOUT = GND -350 -350 mA
Circuit Current
Vee Operating Vee = Max. Commercial 90 80
Icc mA
Supply Current lOUT = OmA Military 110
Automatic CE[2] Max. Vee, Commercial 15 10
ISBI mA
Power Down Current CE ~ VIH Military 10
Capacitance [5]
pF
COUT
Notes:
1. Duration of the short circuit should not exceed 30 seconds. 3. TA is the "instant on" case temperature.
2. A pull-up resistor to Vee on the eE input is required to keep the 4. See the last page of this specification for Group A subgroup testing
device deselected during Vee power-up, otherwise ISB will exceed information.
values given. 5. Tested initially and after any design or process changes that may

R1329!l R1 329.n
5V o------IV..,...,.--. 5VO-------~vv~~
ALL INPUT PULSES
OUTPUT 0----_------.... OUTPUT 0-----__-----.. 3.0V----t~~--"'"
INCLUDING
JIG AND
SCOPE
I 30 pF
R2
202.n
,NCLUD'Nl
JIG AND
5 pF R2
202.n
GND
,,5 ns
0019-6
SCOPE -= 0019-4
Figure 2
Figure la Figure Ib
125.n
OUTPUT O--_JlVV\.,..--_Ol.90 V 0019-5
2-77
~ CY7C147
~~~NDUcroR =====================================================================
Switching Characteristics Over Operating Range[6]
7C14725 7C14735 7C14745
READ CYCLE
toHA Data Hold from Address Change 3 5 5 ns
tACE CS Low to Data Valid 25 35 45 ns
tLZCE CE LOW to Low Z[S) 5 5 5 ns
tHZCE CEHIGH to High Z[7, S) 20 30 30 ns
tPD CE HIGH to Power Down 20 20 20 ns
WRITE CYCLE[9)

tAW Address Setup to Write End 25 35 45 ns
tPWE WE Pulse Width 15 20 25 ns
tHZWE WE LOW to High Z[7, S] 15 20 25 ns
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing 9. The internal write time ofthe memory is defined by the overlap of
loading of the specified IorJIoH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
7. tHZCE and tHZWE are tested with CL = 5 pF as in Figure lb. data input setup and hold timing should be referenced to the rising
Transition is measured 500 mV from steady state voltage. edge of the signal that terminates the write.
S. At any given temperature and voltage condition, tHZ is less than tLZ 10. WE is HIGH for read cycle.
for all devices. 11. Device is continuously selected, CE = VIL.
Switching Waveforms
ADDRESS ----;.~t-----_-=-tRC-==*_
DATA OUT
--{""-o----tOHA
0019-7
2-78
~ CY7C147
~~~NDUcroR =====================================================================
~t
tACE
tRC
.
-,'{-
J
fI
tLZCE~ _tHZCE~1 HIGH
IMPEDANCE
HIGH IMPEDANCE II I I I I ,
DATA OUT DATA VALID
1
J
-tpu
I" " " '- '- ,...--tpo
VCC _ _ _ _ _ _
SUPPLY
CURRENT -
60%
t'"
60%
ISB
0019-8
~----------------------------twc---------------------------~
ADDRESS
1-------------------- tSCE ------------------------1
t-----------------------tAW----------------------~t---
f+---------tSA-----+i f+-----t~E----~
14--;-----tso--------+l-
tHZWE~
DATA OUT ---------D-A-T-A-U-N-D-EF-IN-E-D------- ))0-----------<"'_______
0019-9
~-----------------------~C---------------------------~
_+------------- tSCE---------~
f+-------t~E---------~
I--+---------tso--------+-
DATA-IN VALID
tHZWE--j
-------------..;...---~ HIGH IMPEDANCE
DATA OUT DATA UNDEFINED , ..- - - - - - - - - - - - - - - - - - - - - -
0019-10
2-79
~ CY7C147
~~~NDUcroR =====================================================================
vs SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.2
~ ~ lee ~ 100
1.2
y 1.0 !
~
~
0
J:!
1.0
,/
~
c.i 0.8
J:!
~ .... I-
Z
w
a:
80
~~
a:
c 0.8 0 ::::I
w
N '/ w
N 0.6
CJ
w
60
:J 0.6
<I:
::E VIN = 5 V
:J
<I:
::E
CJ
a:
::::I 40
"'\, Vee = 5.0V
TA = 25C
a: TA = 25C a: 0.4 0
'"'"
0 0.4 0 Vee =5.0 V en
z z VIN = 5.0 V I-
0.2 0.2 ~ 20
I-
IS8 IS8 ::::I
0
0.0 0.0 0
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPL Y VOLTAGE (V) AMBIENT TEMPERATURE rC) OUTPUT VOLTAGE (V)

, ---
1.4 1 . 6 . - - - - - - T " " " - - - - -..... 160
~ 140
~
1.3
1.4 t-----+-------I !
I- 120
s-"
cw
1.2
ow 1.2 t-----+-----,."c;....-I
Z
w
a: 100 /
N
:J 1.1
N
:J
a:
::::I
CJ 80
V
<I:
::E
a: 1.0 ~
TA = 25C <I:
~
oz
1.0 r-----::;;01~-----~ z
en
~
60 I ~~c= =2~~~ V -
0
z ...............
r---
I-
::::I
ll- 40 L
0.9
0.8 r-----r------~ l-
::::I
0 20 /
0.8 0.6 ~----.......- - - - - - ' o
If
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPL Y VO LTAGE (V) AMBIENT TEMPERATURE ('C) OUTPUT VOLTAGE (V)

vs. SUPPLY VOLTAGE (7Cl48) vs. OUTPUT LOADING vs. CYCLE TIME
3.0 30.0 1.4
.,-
II
Vee = 5.0V
2.5 25.0 1.3 f---TA = 25C
g I / VIN = 0.5 V
cw
2.0 TA = 25C - ' - - - -
lK n es
PULL-UP
! 20.0 .Ii
t.l
1.2
N
:J 1.5
RESISTOR TO Vee
1" 150 / 0
w
N
:::i 1.1
<I:
/'t' <I:
---
::E I-
a: ..J ::E
IS8 W a:
1.0
~ o 10.0 0
z
1.0
~
0.5
/ 5.0 1
V TA = 25C
Vee = 4.5 V
0.9 ./
~ /' ./'
V"
0.0
0.0 1.0 2.0 ----
SUPPLY VOLTAGE (V)
3.0 4.0 5.0
0.0
o 200 400 600
CAPACITANCE (pF)
800 1000
0.8
o 10 20
30 40 50
0019-11
2-80
~ CY7C147
~~~NDUcroR =====================================================================
Ordering Information Address Designators
Speed Package Operating Address Address Pin
Ordering Code
(ns) Type Range Name Function Number
25 CY7C147-25PC P3 Commercial Ao Xo 1
Al XI 2
A2 X2 3
CY7C147-35DC D4 Commercial A3 X3 4
CY7C147-35LC L50 Commercial A4 Yo 5
CY7CI47-35LMB L50 Military As YI 6
A6 X4 17
CY7C147-45DC D4 Commercial A7 Xs 16
CY7C147-45LC L50 Commercial 15
As Y2
CY7C147-45LMB L50 Military A9 Y3 14
AIO Y4 13
All Ys 12
BitMap
ROW 0
ROW 63
0019-12
2-81
~ CY7C147
~Jr;~u~==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
Icc 1,2,3
ISBl 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
toHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tscE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #; 3800030B
282
CY7C148
CY7C149
CYPRESS
Features
deselected (7CI48)
CMOS for optimum
speed/power
25 ns access time
The CY7C148 and CY7C149 are high
performance CMOS static RAMs orga-
nized as 1024 x 4 bits. Easy memory
expansion is provided by an active
LOW chip select (CS) input, and three-
state outputs. The CY7C148 and
select (CS) and write enable (WE) in-
puts are both LOW, data on the four
data input/output pins (1/00 through
tion addressed by the address present
on the address pins (Ao through A9).

Low active power CY7C149 are identical except that the Reading the device is accomplished by
- 440 mW (commercial) CY7C148 includes an automatic (CS) selecting the device, (CS) active LOW,
- 605 mW (military) power-down feature. The CY7C148 re- while (WE) remains inactive or HIGH.
mains in a low power mode as long as Under these conditions, the contents of
Low standby power (7CI48) the device remains unselected, i.e. (CS)
- 82.5 mW (25 ns version) the location addressed by the informa-
is HIGH, thus reducing the average tion on address pins (Ao through A9) is
- 55 mW (all others) power requirements of the device. The present on the four data input/output
5 volt power supply 10% chip select (CS) of the CY7C149 does pins (1/00 through 1/03).
tolerance both commercial and not affect the power dissipation of the
military device. The input/output pins (1/00 through
1/03) remain in a high impedance state
TTL compatible inputs and An active LOW write enable signal unless the chip is selected, and write
outputs (WE) controls the writing/reading op- enable (WE) is high.
eration of the memory. When the chip

Vee
A7
As
Ag
1/00
1/01
A2 1/02
cs 1/03
Ag 1/00 WE
As
0001-2
A7 1/01
A6
As 1/02
A4
1/03
cs
WE
0001-1 0001-3
Selection Guide
7Cl48-25 7C148-35 7Cl48-45 7C149-25 7C149-35 7C149-45
Maximum Access Time (ns) 25 35 45 25 35 45
Maximum Operating Commercial 90 80 80 90 80 80
Current (rnA) Military 110 110 110 110
2-83
CY7C148
fin
Maximum Ratings
~~NDUcrOR=====================================================================
CY7C149
Storage Temperature ............... -65C to + 150C Static Discharge Voltage
Ambient Temperature with (Per MIL-STD-883 Method 3015) ............. >2OO1V
Power Applied .................... - 55C to + 125C Latchup Current. . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
(Pin 18 to Pin 9) ..................... -O.SV to + 7.0V Operating Range
Range Vee
in High Z State ............... " ..... -O.SV to + 7.0V Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to + 70C 5V 1O%
Output Current into Outputs (Low) ............. 20 rnA Military[11] - 55C to + 125C 5V 1O%

7Cl48/9-25 7Cl48/9-35, 45
Min. Max. Min. Max.
IOH Output High Current VOH = 2.4V Vee = 4.5V -4 -4 mA
IOL Output Low Current VOL = O.4V 8 8 mA
VIH Input High Voltage 2.0 6.0 2.0 6.0 V
VIL Input Low Voltage -3.0 0.8 -3.0 0.8 V
IIX Input Load Current GND ~ VI ~ Vec -10 10 -10 10 p.A
IOZ Output Leakage Current GND ~ Vo ~ Vec Output Disabled -50 50 -50 50 p.A
CI Input Capacitance[13] 5 5
Test Frequency = 1.0 MHz pF
Input/Output T A = 25C, All Pins at OV, V CC = 5V
CliO 7 7
Capacitance[13]
V CC Operating Max. VCC, CS ~ VIL Commercial 90 80
Icc rnA
Supply Current Output Open Military 110
Automatic CS Max. Vcc, 7C148 Commercial 15 10 rnA
ISB Power Down Current CS:C: VIH only Military 10
Peak Power-On Max. Vcc, 7C148 Commercial 15 10 rnA
Ipo CS:C: VIH[3]
Current only Military 10
Output Short GND ~ Vo ~ Commercial 275 275
loS mA
Circuit Current VcdlO] Military 350
Notes:
1. Test conditions assume signal transition times of 10 ns or less, timing 6. At any given temperature and voltage condition, tHZ is less than tLZ
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output for all devices. Transition is measured 500 mV from steady state
loading of the specified IOLlIoH and 30 pF load capacitance. Output voltage with specified loading in Figure 1b.
timing reference is 1.5V. 7. WE is high for read cycle.
2. The internal write time of the memory is defined by the overlap of 8. Device is continuously selected, CS = VIL.
CS low and WE low. Both signals must be low to initiate a write and 9. Address valid prior to or coincident with CS transition low.
either signal can terminate a write by going high. The data input
setup and hold timing should be referenced to the rising edge of the 10. For test purposes, not more than one output at a time should be
signal that terminates the write. shorted. Short circuit test duration should not exceed 30 seconds.
3. A pull up resistor to Vee on the CS input is required to keep the 11. T A is the "instant on" case temperature.
device deselected during Vee power up. Otherwise current will ex- 12. See the last page of this specification for Group A subgroup testing
ceed values given (CY7C148 only). information.
4. Chip deselected greater than 25 ns prior to selection. 13. Tested initially and after any design or process changes that may
S. Chip deselected less than 25 ns prior to selection. affect these parameters.
Rl481Sl Rl481n
5V 0----"""'''''"''-. 5 v Q----"""'\__..... ALL INPUT PULSES
OUTPUT 0 - - - 1 - - -.... OUTPUT 0---1---'" 3.0 V ------:~~----!l
30 pF R2 5pF R2
I INCLUDING
_JIG AND _
- SCOPE -
26SSl
I INCLUDING
-::-~~~~D -::-
255Sl
GND
~10n8 ~10n8
0001-4 0001-5
Figure la Figure Ib
Equivalent To: Figure 2
THEVENIN EQUIVALENT
1670
OUTPUT O~--~""'''''''\:~--O 1.73 v 0001-12
2-84
CY7C148
fin ~~NDUcrOR =======================================================================
CY7C149

7Cl48/925 7Cl48/935 7Cl48/945
READ CYCLE
tRC 25 35 45 ns
Care Time (Read Cycle Time)
Address Valid to Data Out
tAA 25 35 45 ns
Valid Delay (Address Access Time)
tACS! Chip Select Low to Data Out Valid 25[4] 35 45
ns
tACS2 (CY7C148 only) 30[5] 35 45
Chip Select Low to Data Out Valid
tACS 15 15 20 ns
(CY7C149 only)
tLZ[6] Chip Select Low to 7C148 8 10 10

ns
Data Out On 7C149 5 5 5
tHZ[6] Chip Select High to Data

0 15 0 20 0 20 ns
Out OtT
Address Unknown to Data Out
tOH 0 0 5 ns
Unknown Time
Chip Select High to
tpo 7C148 20 30 30 ns
Power-Down Delay
Chip Select Low to
tpu 7C148 0 0 0 ns
Power-Up Delay
WRITE CYCLE
twc 25 35 45 ns
Care (Write Cycle Time)
twp[2] Write Enable Low to

20 30 35 ns
Write Enable High
tWR Address Hold from Write End 5 5 5 ns
twz[6] Write Enable to Output

0 8 0 10 0 15 ns
in HighZ
tow Data in Valid to Write Enable High 12 20 20 ns
tOH Data Hold Time 0 0 0 ns
Address Valid to Write
tAS 0 0 0 ns
Enable Low
tcW[2] Chip Select Low to Write

20 30 40 ns
Enable High
tow[6] Write Enable High to Output

0 0 0 ns
in Low Z
tAW Address Valid to End of Write 20 30 35 ns
Switching Waveforms
Read Cycle No.1 (Notes 7,8)
~~-------------------------tRc------------------------~1.
~~~_~
___'~=~:~~:~~:~t_O~H~~~~~~-t_A:A=-~-.-I-----.-!-------------~-------
-------------------------------------- 0001-6
2-85
, CY7Cl48
(;A~NDUcroR =====================================================================
. CY7C149

tRC
~
t -;'1-
tACS
tLZ:l
~'"'~ HIGH
DATA OUT
HIGH IMPEDANCE If , , , 7 II
1
\.\.\.\.\.1\
i---tpu I---tPD
--j ICC
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT _
. 50%
SOO:~ISB
0001-7

~-----------------------------twc---------------------------~
ADDRESS
~---------------------t~--------------------~
~-----------------------tAW--~------------------~~---
1+---------tAS --------o.l I+--------twp - - - - - - - . - I
1+-~-------tDW------~~
DATA 1/0 DATA-IN VALID
DATA 1/0 ----------D-A-T-A-U-ND-E-F-IN-E-D-------

twz~
>)O--------------~~ ______
0001-8
Write Cycle No.2 (CS Controlled)

~---------------------------twc----------------------------
1+--------twP - - - - - - - . - I
DATA 1/0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ *L~.~NVALID ,', ~"l-----------

~ HIGH IMPEDANCE
DATA 1/0 _ _ _ _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _ _..J
0001-9
Note: IfCS goes high simultaneously with WE high, the output remains in a high impedance state.
2-86
CY7C148
5J1 .
~~UaoR==~~~~~~~~~========================~======~============
CY7C149
11
Ii
::
0
w
1.4
1.2
1.0
0.8
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
V
.,V
~
./
'"
II>
0
::
0
w
1.2
1.0
0.8
0.6
~
vs. AMBIENT TEMPERATURE
~
lee <
..
~
~
ex:
ex:
:J
(J
100
80
60
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
" r'\.

"
N N w
:::; 0.6 :::; (J Vee = 5.0 V
ex: TA = 25C
:E VIN = 5 V
:E :J 40
I\.
0.4 0(I)
'" '"
ex: 0.4
TA = 25C ex: Vee = 5.0 V
0 0
z z VIN = 5.0 V ~
:J
0.2 0. 20
0.2 ~
ISB ISB :J
0
0.0 0.0
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0

1.4 1.6 140
1.3 <
..
120
1.4 .......----1f-----~
~
~
c f\. ; z~w 100
:! 1.2
ex: V'
"
0
w
fil 1.2 I-----~f--_~-~ ex:
:J 80
/
N
:::;

1.1
N
:::;
io
(J
~ /
~
TA ~ 25C z 60
:E 1.0 .......- - - - - " , j ) ' - - - - - - - 4 Vee =5.0 V
ex:
0 1.0
iii
~ J TA = 25C
z
0.9
~
r-- z
0.8 ....~---1f-------4
:J
0.
~
:J
0
40
20
-7
0.6 L...._ _ _ _ _ _ _ _---'
[7
0.8 ~
o
4.0 4.5 5.0 5.6 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE rc) OUTPUT VOLTAGE (V)

vs. SUPPLY VOLTAGE (7Cl48) vs. OUTPUT LOADING vs. ACCESS TIME
3.0 30.0 1.4
j
2.5
2.0
I
TA = 25C L . . - -
n
]: 20.0
25.0
/ --- ~
1.3
1.2
f\.
"
lK I:S PULL-UP
filN 0
:::;

1.5
RESISTOR TO Vee
~" 15.0 I/'
/ w
N
:::;

1.1
.......... r--
:IE
ex:
1.0
ISB 8 / :E
ex:
1.0
i o 10.0
i
/ ~V
TA = 25C
Vee = 4.5 V
0.5 5.0 0.9
0.0
0.0 1.0 2.0 --- V
3.0 4.0 5.0
0.0 V
o 200 400 600 800 1000
0.8
10 20 30 40 50 60
SUPPLY VOLTAGE (V) CAPACITANCE (pF) tAA (nl)
0001-10
2-87
~
CY7C148
. CY7C149
~~========================~~~~~~~~~~~~~~~~~~~~
Ordering Information Address Designators
Speed Package Operating Address Address Pin
Ordering Code
(ns) Type Range Name Function Number
25 CY7C148-25PC P3 Commercial Ao Yo 5
CY7C 149-25PC 6
Al YI
CY7C148-250C 04 7
A2 Y2
CY7C149-250C
A3 Y3 4
CY7C148-25LC L50
CY7C149-25LC A4 Xo 3
35 CY7C148-35PC P3 Commercial As X3 2
CY7C149-35PC A6 X2 1
CY7C148-350C 04 A7 Xs 17
CY7C149-350C
As X4 16
CY7C 148-35LC L50
A9 Xl 15
CY7C149-35LC
CY7C148-350MB 04 Military BitMap
CY7C149-350MB
CY7CI48-35LMB L50
CY7CI49-35LMB
CY7C149-45PC
CY7C148-450C 04
CY7C149-450C
CY7C148-45LC L50
CY7C149-45LC
CY7C148-450MB 04 , Military
CY7C149-450MB
CY7C148-45LMB L50
CY7CI49-45LMB
0001-11
2-88
CY7C148
5'n~~~UaoR================================================================
.'
CY7C149

DC Characteristics
Parameters
IOH
Subgroups
1,2,3
fI
IOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
IcC 1,2,3
ISB[l] 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tACSl[l] 7,8,9,10,11
tACS2[1] 7,8,9,10,11
tACS[2] 7,8,9,10,11
toH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
twp 7,8,9,10,11
tWR 7,8,9,10,11
tDW 7,8,9,10,11
tDH 7,8,9,10,11
tAS 7,8,9,10,11
tAW 7,8,9,10,11
Notes:
1. 7C148 only.
2. 7C149 only.
2-89
CY7C150
CYPRESS
Memory reset function The CY7C150 is a high performance eration of the memory. When the chip
CMOS static RAM designed for use in select (CS) and write enable (WE) in-
1024 x 4 static RAM for control
store in high speed computers cache memory, high speed graphics, puts are LOW, the information on the
and data aquisition applications. Orga- four data inputs Do to D3 is written
CMOS for optimum nized as 1024 words x 4 bits, the entire into the addressed memory location
speed/power memory can be reset to zero in two and the output circuitry is precondi-
High speed memory cycles. tioned so that the write data is present
- 12 ns (commercial) Separate I/O paths eliminate the need at the outputs when the write cycle is
- 15 ns (military) to multiplex data in and data out, pro- completed.
viding for simpler board layout and Read~ is performed with the chip se-
Low power
- 495 mW (commercial) faster system performance. Outputs are lect (CS) input LOW, and the write en-
- 550 mW (military) tri-stated during write, reset, deselect, able (WE) input HIGH, and the output
or when output enable (OE) is held enable input (OE) LOW. The informa-
Separate inputs and outputs HIGH, allowing for easy memory ex- tion stored in the addressed word is
5 volt power supply 10% pansion. read out on the four non-inverting out-
tolerance both commercial and Reset is initiated by selecting the device puts 00 to 03.
military (CS = LOW) and pulsing the reset The outputs of the memory go to an
Capable of withstanding greater (RS) input LOW. Within two memory active high impedance state whenever
than 2001V static discharge cycles all bits are internally cleared to chip select (CS) is HIGH, Reset (RS) is
zero. Since chip select must be LOW LOW, output enable (OE) is HIGH, or
TIL compatible inputs and during the writing operation when
for the device to be reset, a global reset
outputs
signal can be employed, with only se- Write Enable (WE) is LOW.
lected devices being cleared at any giv- A die coat is used to ensure alpha im-
en time. munity.
An active LOW write enable input
(WE) controls the writing/reading op-

RS "1'1")0
0
o N
-o(-o(z>-o(
es
A3 Vee
DE A, A4 A2
Ao As AI
WE Rs AS Ao
Cs A7 RS
00 Ne As cs
Ao Ag WE Ag WE
At
1 Do DE Do Of
A2
D, D3 01 03
A3
A4 2 00 D2
O2
0
As
03 1 03
-00 N ttl
oz
(!)
zoo GND 2
0028-13
0028-2
0028-1
Selection Guide
7C15012 7C15015 7C15025 7C15035
Commercial 12 15 25 35
Military 15 25 35
Military 100 100 100
2-90
~ CY7C150
~~~~UcrOR =======================================================================
Maximum Ratings
+ 125C Latch-up Current .......................... > 200 rnA fJI
(Pin 24 to Pin 12) .................... - 0.5V to + 7.0V Operating Range
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OCto + 70C 5V 10%
Output Current into Outputs (Low) ............. 20 rnA Military [3] - 55C to + 125C 5V 1O%

7CI50-12, 15,25, 35
Min. Max.
VOL Output LOW Voltage Vee = Min.,loL = 12.0 rnA 0.4 V
VIR Input High Voltage 2.0 Vee V
VIL Input Low Voltage -3.0 0.8 V
IIX Input Load Current GND::;; VI::;; Vee -10 +10 p,A
Output Leakage GND::;; Vo::;; Vee
loz -50 +50 p,A
los Output Short[l] Vee = Max., VOUT = GND -300 rnA
lee
Vee Operating Vee = Max. I Commercial 90
rnA
lOUT = OmA
Supply Current
I Military * 100
*-15, -25 and -35 only
Capacitance [2]
CIN Input Capacitance TA = 25C, f = 1 MHz, Vee = 5.0V 5 pF
COUT Output Capacitance TA = 25C, f = 1 MHz, Vee = 5.0V 7 pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration of 3. TA is the "instant on" case temperature.
the short circuit should not exceed 30 seconds. 4. See the last page of this specification for Group A subgroup testing
2. Tested initially and after any design or process changes that may information.

R1329 n Rl 329 n
5Vo---------~~~ 5Vo---------~~~
3.0 V ----ir.~--- ......
OUTPUT 0-----....- - - - - - 1 OUTPUT 0-----__- - -...
GND----..,.
R2 . 5 pF R2 ,.;;3n8 ,.;;3n8
'NCLUD'NGI 30 pF 20HZ 202n
JIG AND ,NCLUD,Nl 0028-5
SCOPE JIG AND
SCOPE ":" Figure 2. All Input Pulses
0028-3
Figure la Figure Ib
Equivalent To:
THEVENIN EQUIVALENT
12sn
OUTPUT O---.JO,'VV\Ir---_O 1.90 V
0028-4
2-91
~ CY7C150
~~~UcrOR =====================================================================
7C150-12 7C15015 7C15025 7C15035
Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 12 15 25 35 ns
tAA Address to Data Valid 12 15 25 35 ns
tOHA Output Hold from Address Change 2 2 2 2 ns
tACS CS LOW to Data Valid 10 12 15 20 ns
tLZCS CS LOW to Low Z[7] 0 0 0 0 ns
tHZCS CS HIGH to High Z[6, 7] 8 0 11 0 20 0 25 ns
tDOE OE LOW to Data Valid 8 10 15 20 ns
tLZOE OE LOW to Low Z[7] 0 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 0 8 0 9 0 20 0 25 ns
WRITE CYCLE[8]
twc Write Cycle Time 12 15 25 35 ns
tscs CS LOW to Write End 8 11 15 20 ns
tAW Address Set-up to Write End 10 13 20 30 ns
tHA Address Hold from Write End 2 2 5 5 ns
tSA Address Set-up to Write Start 2 2 5 5 ns
tPWE WE Pulse Width 8 11 15 20 ns
tSD Data Set-up to Write End 8 11 15 20 ns
tHD Data Hold from Write End 2 2 5 5 ns
tLZWE WE HIGH to Low Z[7], 0 0 0 0 ns
tHZWE WE LOW to High Z[6, 7] 0 8 0 12 0 20 0 25 ns
RESET CYCLE
tRRC Reset Cycle Time 24 30 50 70 ns
tSAR Address Valid to Beginning of Reset 0 0 0 0 ns
tSWER Write Enable HIGH to Beginning of Reset 0 0 0 0 ns
tSCSR Chip Select LOW to Beginning of Reset 0 0 0 0 ns
tpRS Reset Pulse Width 12 15 20 30 ns
tHCSR Chip Select Hold after End of Reset 0 0 0 0 ns
tHWER Write Enable Hold after End of Reset 12 15 30 40 ns
tHAR Address Hold after End of Reset 12 15 30 40 ns
tLZRS Reset HIGH to Output in Low Z[7] 0 0 0 0 ns
tHZRS Reset LOW to Output in High Z[6, 7] 0 8 0 12 0 20 0 25 ns
Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CS LOW and WE LOW. Both signals must be LOW to initiate a
loading of the specified IoIlIoH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
6. tHZCS, tHZOE, tHZR and tHZWE are tested with CL = 5 pF as in data input setup and hold timing should be referenced to the rising
Figure 1h. Transition is measured 500 mV from steady state volt- edge of the signal that terminates the write.
age. 9. WE is HIGH for read cycle.
7. At any given temperature and voltage condition, tHZ is less than tLZ 10. Device is continuously selected, CS and OE = VIL.
for any given device. II. Address valid prior to or coincident with CS transition LOW.
2-92
~ CY7C150
~~~NDUcrOR=====================================================================
Switching Waveforms
-----,J;~~--------------------------tRc--------------------~----~1~
til
ADDRE~_~~I_:~--~~~~~~~~-~~H~A~~~~~tA~A~-_.-!-----------_-!---------------------------~------------------
DATA OUT
______
------------------------------------------- 0028-6
tRC
J -,'l
t J
tACS
~~
tOOE
{
I--tLZOEi 'Hro':3
-tHZCS-
HIGH
IMPEDANCE
HIGH IMPEDANCE II I I I I ",
DATA OUT DATA VALID
lucS -I'" \. \. \. \. ~ f
0028-8
~-----------------------------~C----------------------------~
J--------------------- tscs -----------------------1
~-----------------------tAW------------------------~---
1+--------tSA-------------.{ ~-------tME--------~
~-:-----tso---- .....-
tHZWE---+j tLZWE---j
DATA OUT
-------------------------------------~
DATA UNDEFINED
HIGH IMPEDANCE It'-------------
________
J).----...;...;;,;.;.....;....~..;...---~\'".
0028-9
2-93
~ CY7C150
~~~~UcrOR================================================================~
Write Cycle No.2 (CS Controlled) (Note 8)
~----------------------------~c----------------------------~
ADDRESS
1 4 - - - - - tSA - - - - - + - - - - - - - - t5C5------..-I
~------------------------tAW----------------------~~-
~-------tME------------~
WE
~_+---------------tSD----------t....-
tHZWE~
------------------~ HIGH IMPEDANCE
DATA 1/0 DATA UNDEFINED , .....- - - - - - - - - - - - - - - - - - - - - - -
0026-10
Note: IfCS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
Reset Cycle
1+1"------- t RRC --------1'1

ADDRESS::::::::::::::::>.<r---------------------------------------)(::::::::::::::
t-------t HwER - - - - ' "
1-...........................- .
01-04~~~~~~~~~~~~~t-----1mr.r----~
(DATA OUTPUT) 1. HIGH 1'-_ _ _ _ _ _ _ _ _ _ _ _ __
IMPEDANCE OUTPUT VALID ZERO
0028-11
Note: Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
2-94
~ CY7C150
~~~UcrOR=====================================================================

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE
til
vs OUTPUT VOLTAGE
1.4 1.2 60
1.2
/ 1.0
~ ;t
! 50 ~
I~V
~
"
ID I- Vee = 5.0 V
jl 1.0
III
~ TA = 25C
~ V Y 0.8 a: 40
'" '""
.:d a:
0.8 :::I
~ ~ 0.6
V
(.)
N N w 30
(.)
~ ~ a:
< 0.6 < :::I
::!i ::!i 0.4 0 20
a: 0.4 a: en
0 0 Vee ~5.0 V I-
Z z VIN =5.0V
0.2 1--158 irI- 10
~
0.2
'"
158 :::I
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)

1.4 1.6 .....- - - - , - - - - - - - . , 150
'----
1.3 ;t 125 ~
~V
1.4 ~-----t-------i
!
'"
:! 1.2 '"
:!
I-
~ 100
0
w
N
~ 1.1 .....
~
N
~
1.2 ~-----t----_;;;JJ"c;...---; a:
a:
:::I
(.) 75 L
j "
< ........... TA ~ 25C
c:( :.0:
~ ~ 1.0 ~----,...~-------;
~ Z
a:
-
1.0 o iii 50
0
z r---.... z
0.8 h , . c . . . . - - - - t - - - - - - - i
I-
ir
I- 1 Vee = 5.0 v_
0.9 :::I 25
0.8
4.0 4.5 5.0 5.5 6.0
0.6 L-_ _ _ _
-55
~
25
_ _ _ _ _.......
125
0
V 1.0 2.0 3.0
TA = rOC
4.0 5.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (VI

3.0 30~-~-~--~-~--" 1.1,..------,r-------,---.....,
TA =25C Vee = 5.0 V

2.5 Vee z 4.5 V TA = 25C
VIN z 0.5 V
E 2.0 ! 20r--~-~--,~-~----;
0
~
W
N
::i 1.5 c:(
<
~ ~
a: ~ 10~-~~-+--~-~-~
1.0
i
0.5 L
0.0 -" V 200 400 600 800 1000
0.8 L.-_ _---II..-_ _---I_ _ _
10
~
0.0 1.0 2.0 3.0 4.0 5.0 20 30 40

SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREOUENCY (MHz)
0028-14
2-95
~ CY7C150
~~~~UaoR==================================================================
Truth Table Ordering Information
Inputs Speed Package Operating
Outputs Mode Ordering Code
(ns) Type Range
CS WE OE RS
H X X X HighZ Not Selected 12 CY7C150-12PC P13A Commercial
L H X L HighZ Reset CY7C150-12DC D14
L L X H HighZ Write CY7C150-12LC L54
L H L H Read CY7C150-128C S13
00-0 3
L X H H HighZ Output Disable 15 CY7C150-15PC P13A Commercial
CY7C150-15DC Dl4
CY7C150-15LC L54
CY7C150-158C 813
CY7CI50-15LMB L54
CY7C150-25DC D14
CY7C150-25LC L54
CY7C150-258C S13
CY7CI50-25LMB L54
CY7C150-35DC D14
CY7C150-35LC L54
CY7C150-358C S13
CY7CI50-35LMB L54
BitMap Address Designators

Address Address Pin
Ao Xo 21
Al Xl 22
A2 X2 23
A3 X3 1
A4 X4 2
o As Xs 3
1
.
2
3 At;
A7
Yo
YI
4
5
As Y2 6
.
60
61
A9 Y3 7
62
63
0028-15
2-96
~ CY7C150
~~~~UcrOR==============================================================
DC Characteristics
Parameters
VOH
VOL
VIH
VIL Max.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACS 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tscs 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
RESET CYCLE
tRRC 7,8,9,10,11
tSAR 7,8,9,10,11
tSWER 7,8,9,10,11
tSCSR 7,8,9,10,11
tpRS 7,8,9,10,11
tHCSR 7,8,9,10,11
tHWER 7,8,9,10,11
tHAR 7,8,9,10,11
2-97
PRELIMINARY CY7C157
CYPRESS
SEMICONDUCTOR 16,384 X 16 Static Cache RAM
Address and WE registers The CY7C157 is a high performance order to meet the hold time require-
CMOS static RAM organized as ments of the microprocessor.
power 16,384 x 16 bits. It is intended specifi- To write the device correctly, OE must
cally for use as a high speed cache be taken HIGH. If the falling edge of
High speed-20 ns memory device with the CY7C600 CLOCK samples either or both of
Data In and Data Out latches SPARCTM family of devices. The WEo or WEt LOW, a self timed byte
CY7C157 employs common I/O archi- write mechanism is triggered. Data is
TTL compatible inputs and tecture, and a self timed byte-write
outputs written from the data-in latch into the
mechanism. memory array at the corresponding ad-
Self-timed write Reading the device is accomplished by dress.
Capable of withstanding greater taking WE HIGH, and OE LOW. On Note that the OE signal must be HIGH
than 2001 V electrostatic the rising edge of CLOCK, addresses for a proper write as the WEo and WEl
discharge Ao-A13 are loaded into the input reg- signals do not tristate the outputs.
isters. A memory access occurs, and
Common I/O data is held after a read cycle beyond A die coat insures alpha immunity.
the next rising edge of CLOCK in
SPARCTM is a trademark of Sun Microsystems, Inc.
Logic Block Diagram
ARRAY 0 ARRAY 1
WEo ------+Q 8096 x 16 8096 x 16
WE, _-------lkll
CLOCK ._-----4~------__1
~"------------------1-~
0153-1
2-98
~~~~NDUcroR =====================================================================
Selection Guide
7C157-20 7C157-24 7C157-33
Maximum Clock to Commercial 20 24 33
Output (ns)
Maximum Output Enable to

Military
Commercial 8
24
10
33
15
tI
Output Time (ns) Military 10 15
Commercial 250 250 250
Maximum Current (rnA)
Military 300 300
Maximum Ratings
Supply Voltage to Ground Potential .... -0.5V to + 7.0V Operating Range
in High Z State ...................... -0.5V to + 7.0V Range
Ambient
Vee
Temperature
Commercial OC to + 70C 5V 1O%
Output Current into Outputs (LOW) ............ 50 rnA
Military - 55C to + 125C 5V 1O%
Electrical Characteristics Over Operating Range

7C157-20 7C157-24 7C157-33
VOR Output HIGH Voltage Vee = Min, lOR = -4.0mA 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min, IOL = 8.0 rnA 0.4 0.4 0.4 V
IIX Input Load Current GND < VI < Vee -10 +10 -10 + 10 -10 +10 ILA
Ioz Output Leakage Current GND < Vo < Vee, Output Disabled -50 +50 -50 +50 -50 +50 ILA
los Vee = Max, VOUT = GND -350 -350 -350 rnA
Current (1]
lee
Vee Operating Vee = Max. ICommercial 250 250 250
rnA
Supply Current lOUT = OmA IMilitary 300 300
Capacitance [2]
pF
COUT Output Capacitance Vee = 5.0V[3] 8
Notes:
1. Not more than 1 output should be shorted at one time. Duration of 2. Tested initially and after any design or process changes that may
the short circuit should not exceed 30 seconds. affect these parameters.
2-99
~~~~UaoR==================================================================
RI481n R1481n All Input Pulses
0----"""''''''''. . . 6V O----'V'W'Ir--,
5V
OUTPUT 0--....---.. OUTPUT 0--_----4 3.0V ----:.P!o~--~l..
:Sf!
r 100 pf
INCLUDING
_ JIGAND _
- SCOPE -
0153-3
r 6PF
INCLUDING
_JIG AND
- SCOPE
_
-
:Sn
0153-4
GND
0153-5
Figure 2
Figure la Figure Ib
167Sl
OUTPUT O----'~~ ....""'.---O 1.73 V
0153-6
Switching Characteristics Over Operating Range [4, 5]

7C157-20[6] 7C157-24[6] 7C157-33
READ CYCLE[7, 8]
tcHCH Clock Cycle Time 25 30 40 ns

tCHQV Clock HIGH to Output Valid 20 24 33 ns
tCHQX Output Data Hold 5 5 5 ns
tGLQV DE LOW to Output Valid 8 10 15 ns
tGHQZ OE HIGH to Output Tristate 8 10 15 ns
tGHCH DE HIGH to Next Clock HIGH 7 7 7 ns
tAVCH Address Setup 2 2 3 ns
tCHAX Address Hold 6 6 6 ns
WRITE CYCLE[9]
tGHQZ OE HIGH to Output Tristate[to] 8 10 15 ns
taHcH DE HIGH to Next Clock HIGH 7 7 7 ns
tDVCL Data in Setup to Clock 6 6 7 ns
tCLDX Data in Hold from Clock 2 2 2 ns
tWLCL WEx LOW to Clock LOw[t2, 13] 4 4 6 ns
tCLWH Clock LOW to WEX HIGH[12, 13] 3 3 3 ns
tAVCH Address Setup 2 2 3 ns
tCHAX Address Hold 6 6 6 ns
Notes:
4. See the last page of this specification for Group A subgroup testing 10. tGHQZ is specified with CL = 5 pF as in Figure lb. Transition is
information. measured 500 mV from steady state voltage.
5. Test conditions assume signal transition times of 3 ns or less, timing 11. Self Timed Write is triggered on falling edge of either WEo or WEt.
reference levels of 1.SV, input pulse levels of 0 to 3.0V and output 12. X = 0 or 1 for low byte and high byte, respectively.
loading ofthe specified IorJ10H and 100 pF load capacitance. 13. Self Timed Write is triggered on falling edge of registered WEo or
6. Surface mount package only. WEt signals.
7. WE is HIGH for read cycle.
8. OE is selected (LOW).
9. OE must be high for data-in to propagate to latch.
2-100
~~~U~~============================================================
Switching Waveforms
Read Cycle
CLOCK
ADDRESS ADD(N+ 1)
a(N+ 1)
0153-7
Write Cycle
CLOCK
------'1
0153-8
2-101
~~~NDUcrOR ==================================================================~
Pin Timing Cross Reference Pin Configuration
Timing
Pin Name Description
Reference
Clock C Clock Inputs 6 5 4 3 2 ~52 51504948 47
Ao . 46 A13
Ao-A13 A Address Inputs
Vsso 9 45 Vsso
1/00-1/015 (Input) D Data Inputs 1/00 44 1/15
1/00-1/015 (Output) Q Data Outputs 1/1 43 1/14
1/2 42 1/13
\VEo, WEt. WEx W Write Enable 1/03 41 1/12
OE G Output Enable Vsso 40 Vsso
1/0 4 39 1/11
38 1/10
1/5
I/Og
1/6 17 37
1/8
1/7 36
Vsso
Vsso 35 Vsso
Vsso 34
21222324252627282930313233
C,) 0
Z 110.1
~
0
U
0110.1
U 0
-
VI
-
VI
- ~
VI....I
0
U ul
0 -
loI
u~
C,)
Z
U U VI VI VIC,)
> U
0153-2
PLCC
Top View
Truth Table
Inputs
Outputs
OE WEo (.! CLOCK) WEt (.! CLOCK)
X X X HighZ
H H H HighZ
L H H 1/00- 1/015
H L H 1/0 0- 1/ 0 7
H H L 1/08-11015
H L L 1/0 0- 1/015
Notes:
14. Data In latch is transparent when clock i HIGH.
15. Data In latch is closed when clock J, LOW.
Ordering Code
(ns) Type Range
20 CY7ClS7-20LC L69 Commercial
CY7ClS7-20JC J69
24 CY7C157-24LC L69
CY7C157-24JC J69
CY7C157-24LMB L69 Military
33 CY7C157-33LC L69 Commercial
CY7C157-33JC J69
2-102
~~~NDUaoR ================================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
tI
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
READ CYCLE
tCHCH 7,8,9,10,11
tCHQV 7,8,9,10,11
tGHQZ 7,8,9,10,11
tCHQX 7,8,9,10,11
tGHQV 7,8,9,10,11
WRITE CYCLE
tCHcH 7,8,9,10,11
tDvCL 7,8,9,10,11
tAVCH 7,8,9,10,11
tCHAX 7,8,9,10,11
tCLDX 7,8,9,10,11
tDVWL 7,8,9,10,11
tWLDX 7,8,9,10,11
2-103
CY7C161
ADVANCED INFORMATION CY7C162
CYPRESS
SEMICONDUCTOR 16,384 X 4 Static RAM
Separate I/O
Automatic power-down when The CY7C161 and CY7C162 are high (10 through 13) is written into the mem-
deselected performance CMOS static RAMs orga- ory location specified on the address
Transparent Write (7C161) nized as 16,384 x 4 bits with separate pins (Ao through A13)'
I/O. These RAMs are developed by Reading the device is accomplished by
CMOS for optimum speed/ Aspen Semiconductor Corporation, a
power taking the chip enables (CE1. CE2)
subsidiary of Cypress Semiconductor. LOW, while write enable (WE) re-
High speed Easy memory expansion is provided by mains HIGH. Under these conditions
-10 ns tAA active LOW chip enables (CEI, CE2) the contents of the memory location
Low active power and three-state drivers. They have an specified on the address pins will ap-
- 525 mW at 40 MHz automatic power-down feature, reduc- pear on the four data output pins.
ing the power consumption by 75%
Low standby power when deselected. The output pins stay in high impedance
-150 mW state when write enable (WE) is LOW
TTL compatible inputs and Writing to the device is acco'!!!plished (7C162 only), or one of the chip en-
outputs when the chip enable (CEI, CE2) and ables (CEI, CE2) are HIGH.
write enable (WE) inputs are both
Capable of withstanding greater LOW. Data on the four input pins
discharge
12
Vee
13
A6 A4 u ....
...N.,r <,0 >().(
A7 A3
Ao
As
A9
A2
Al
A3 4 3' 2lTI is 2726 A12
A4 5 25 All
Al A 10 Ao
A2 AS 24 Al0
All 13 A6 23 A9
A3
A4 A12 A7 8 22 13
A5 As 9 21 C 12
A8 10 10 20 0 3
A7 03 11 11 19 02
11 01
ct 12 18C 01
eEl 00 1 \.. 1314151617
DE WE
GND CE2
I~ ~1l:!I~g
CE I
CE2 0152-3
0152-2
WE
Of
0152-1
Selection Guide
7C161-10 7C161-12 7C161-15
7C16210 7C16212 7C16215
Maximum 0serating Commercial 125 120 115
Current(mA Military 150 135
2-104
CY7C161
5A~~~~UcrOR======================================================================= ADVANCED INFORMATION CY7C162
Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... > 2001 V
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs Range Vee
Temperature
in High Z State ...................... -0.5V to + 7.0V
InputVoltage[14] .................... -3.0Vto +7.0V Commercial OC to + 70C 5V 1O%
Electrical Characteristics Over Operating Rangef4]

7C161-10 7C161-12 7C161-15
Parameters Description Test Conditions 7C162-10 7C162-12 7C162-15 Units
VOH Output HIGH Voltage Vee = Min., IOH = -4.0mA 2.4 2.4 2.4 V
VIL Input LOW Voltage [I 4] -0.5 0.8 -0.5 0.8 -0.5 0.8 V
IIX Input Load Current GND::::;: VI::::;: Vee -10 +10 -10 +10 -10 +10 /-LA
Output Leakage GND : : ;: Vo : : ;: Vee,
Ioz -10 +10 -10 +10 -10 +10 /-LA
Current Output Dsbld.
los Vee = Max., VOUT = GND -350 -350 -350 rnA
Current[I]
Automatic CE Vee = Max. Commercial 105 105 105

lee} Power Down Current lOUT = OmA rnA
f= 40 MHz Military 130 130
Vee Operating Vee = Max. Commercial 125 120 115

Iee2 Supply Current lOUT = OmA rnA
f = fmax. Military 150 135
Automatic CE Max. Vee, CE;;:>: VIH Commercial 30 30 30
ISB rnA
Power Down Current Min. Duty Cycle = 100% Military 50 50
Capacitance [2]
Parameters Description Test Conditions Max.!13] Units
Notes:
1. Not more than} output should be shorted at one time. Duration of 3. TA is the "instant on" case temperature.
Z. Tested initially and after any design or process changes that may information.
~C Test Loads and Waveforms

R148Hl. Rl 481.n. 3.0V----_lP----""""-
5V O---,""",I'v-~ 5V o---JV\I'v---,
OUTPUT 0--4----.. OUTPUT 0---1-----+ GND
~;5.n.
R2
CL 5 pF
255.n.
I-= INCLUDING
JIG AND
SCOPE -= I-= INCLUDING
JIG AND
SCOPE 0152-4
Figure 2
0152-5
Figure la Figure lb
~quivalent to: THEVENIN EQUIVALENT
1671l
OUTPUT o--~~v.-".~-~O 1.73 V 0152-6
2-105
CY7C161
5'n~NDUcroR =====================================================================
. ADVANCED INFORMATION CY7C162
Switching Characteristics Over Operating Range[4, 5, 12]

7C16110 7C16112 7C16115
Parameters Description 7C16210 7C16212 7C16215 Units
READ CYCLE
tOHA Output Hold from Address Change 2 3 3 ns
tDoE OE LOW to Data Valid 8 10 10 ns
tLZOE OE LOW to LOW Z 2 3 2 ns
tHZOE OE HIGH to HIGH Z 6 8 8 ns
WRITE CYCLE[S]
tLzwE WE HIGH to Low Z[7] (7CI62) 3 5 5 ns
tHZWE WE LOW to High Z[6, 7] (7CI62) 5 7 7 ns
tAWE WE LOW to Data Valid (7CI61) 10 12 15 ns
tADV Data Valid to Output Valid (7CI61) 10 12 15 ns
Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CEt. CE2 LOW and WE LOW. Both signals must be LOW to initi-
loading of the specified IorlIOH and CL = 30 pF load capacitance ate a write and either signal can terminate a write by going HIGH.
for 15 ns tAA devices and CL = 20 pF load capacitance for 10 ns and The data input setup and hold timing should be referenced to the
12 ns tAA devices. rising edge of the signal that terminates the write.
6. tHzCE and tHzWE are specified with CL = 5 pF as in Figure lb. 9. WE is HIGH for read cycle.
Transition is measured 500 mV from steady state voltage. 10. Device is continuously selected, CEt. CE2 = VIL.
7. At any given temperature and voltage condition, tHz is less than tLZ 11. Address valid prior to or coincident with CEt. CE2 transition LOW.
for any given device. 12. Both CEl and CE2 are represented by CE in the Switching Charac-
teristics and Waveforms.
13. For all packages except cerdip (D22) which has maximums of CIN
= 10 pF, CoUT = 12 pF.
14. VIL (min.) = - 3.0V for pulse width < 20 ns.
Switching Waveforms[12]
Read Cycle No. 1[9, 10]
~t:=====r------------------------tRC------------------------~~~
~D",~~_",", _ _ _ _
OATAOUT PREVIOUS OATA VALlO OATAVALIO
0152-
2106
CY7C161
5A~~NDUcroR ======================================================================= ADVANCED INFORMATION CY7C162
Switching Waveforms[t2] (Continued)

Read Cycle[9, 11]
tRC
jk- ,'f..
I\.
tACE
~~
I---tLZOEi
tOOE L '"'"':3
~tHZCE-
HIGH
HIGH IMPEDANCE If J f f L f IMPEDANCE
DATA OUT DATA VALID
.\\. \. \. \.
1 tLZCE \. f
==t='~
!---tpu ~tpo
VceY _ _ _ _ _
SUPPL 50',(, 50%
CURRENT _ ISB
0152-8
Write Cycle No.1 (WE Controlled)[8]

twc
ADDRESS - -it-
tSCE ,
\\ .\ \\: /111 IIIIIIIII
tAW t HA -
tSA 'I I - - - tpWE -
\:\ \r
tso .1 tHO
I
DATA IN -] DATA-IN VALID ~
!--tHZWE -=! ~tLZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
(7C162)
I-- t AOV
II
'"
DATA OUT
(7C161)
DATA UNDEFINED :::t
J~ DATA VALID __
0152-9
Write Cycle No.2 (CE Controlled)[8]
--
twc
ADDRESS -it- -it-
tSA t scE -
\: "l
tAW - tHA -
~tpWE-
\\ ,\\ \ \ \ \ \ \ \ \ \ \ \ \ \ \-'~ "If-/ / / / / / / / / / / / I
I:: f ----tso - ~tHO

DATA IN ~ DATA-IN VALID ~.
DATA OUT
I - t HZWE ---:1 HIGH IMPEDANCE
DATA UNDEFINED
(7C162)
-------D-A-TA-U-N-D-EF-IN-E-D---------~I--DA-T-A-V-AL-ID----
-tAW -
DATA OUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _X~
(7C161) ________
0152-10
Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C162 only).
2-107
CY7C161
5A
Truth Tables
~DUcrOR~~~~~~~~~~~~~~~~~~==============================
CY7C161 CY7C162
CEI C E 2 WE OE Output Input Mode CEI CE2 WE OE Output Input Mode
H X X X HighZ X Deselect Power Down H X X X HighZ X Deselect Power Down
X H X X HighZ X Deselect Power Down X H X X HighZ X Deselect Power Down
L L H L Data Out X. Read L L H L Data Out X Read
L L L X HighZ Data In Write L L L L Data In Data In Write
L L H H HighZ X Deselect L L L H HighZ Data In Write
L L H H HighZ X Deselect
Ordering Code (ns) Ordering Code
(ns) Type Range Type Range
10 CY7CI61-lOVC V21 Commercial 10 CY7CI62-lOVC V21 Commercial
CY7C161-10LC L54 CY7CI62-lOLC L54
12 CY7C161-12PC P21 Commercial 12 CY7C162-12PC P21 Commercial
CY7C161-12VC V21 CY7C162-12VC V21
CY7C161-12DC D22 CY7C162-12DC D22
CY7C161-12LC L54 CY7C162-12LC L54
CY7CI61-12DMB D22 Military CY7CI62-12DMB D22 Military
CY7CI61-12LMB L54 CY7C 162-12LMB L54
CY7C161-15VC V21 CY7C162-15VC V21
CY7C161-15DC D22 CY7C162-15DC D22
CY7C161-15LC L54 CY7C162-15LC L54
CY7CI61-15LMB L54 CY7CI62-15LMB L54
2-108
CY7C161
(in~~UaDR==============================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
fI
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tooE 7,8,9,10,11
WRITE CYCLE
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
tAWE[ll 7,8,9,10,11
tAOV[ll 7,8,9,10,11
Note:
1. 7C161 only.
Document #: 38-A-00014
2-109
CY7C161
CY7C162
CYPRESS
SEMICONDUCTOR 16,384 X 4 Static R/W RAM
Separate I/O
Features
Automatic powerdown when Capable of withstanding greater LOW. Data on the four input pins (10
deselected than 2001V electrostatic through 13) is written into the memory
Transparent Write (7C161) discharge location specified on the address pins
(Ao through Al3).
CMOS for optimum speed/ Functional Description Reading the device is accomplished by
power
The CY7C161 and CY7C162 are high taking the chip enables (CB1, CE2)
High speed performance CMOS static RAMs orga- LOW, while write enable (WE) re-
- 20 ns tAA nized as 16,384 x 4 bits with separate mains HIGH. Under these conditions
Low active power I/O. Easy memory expansion is pro- the contents of the memory location
-275 mW vided by active LOW chip enables specified on the address pins will ap-
(CB1, CE2) and three-state drivers. pear on the four data output pins.
Low standby power They have an automatic power-down
-110 mW The output pins stay in high impedance
feature, reducing the power consump-
state when write enable (WE) is LOW
TTL compatible inputs and tion by 60% when deselected.
(7C162 only), or one of the chip en-
outputs Writing to the device is accomplished ables (CEl> CE2) are HIGH.
when the chip enable (eEl, CE2) and
A die coat is used to insure alpha im-
write enable (WE) inputs are both
munity.
12
As 28 Vee
13 A6 27 A4 <.> '"
26
<'~~><.>~
A3
A8 25 A2 3 2 1 2827
A3 4 26 A12
00 Ag 24 AI
Ao A4 25 A11
AI A,o 23 Ao As 24 A,o
A2 0, 22
A" 13 A6 7 23 Ag
A3
A'2 21 12 A7 22 13
A4
2 20 03 As 21 12
As
A6 10 10 20 03
10 19 2
A7 11 11 19 2
03 I, 11 18 0,
CE, 12 18 0,
CE, 12 17 00 1314151617
OE 13 16 WE
GND 14 15 eE2
~,
eE2 0062-3
0062-2
WE
OE
._----------
0062-1
Selection Guide
7C16120 7C16125 7C161-35 7C16145
7C16220 7C16225 7C16235 7C16245
Maximum Access Time (ns) 20 25 35 45
Maximum oserating Commercial 80 70 70 50
Current (mA Military 80 70 70
Maximum Standby Commercial 40/20 20/20 20/20 20/20
Current (mA) Military 40/20 20/20 20/20
2-110
CY7C161
Wn .
Maximum Ratings
~NDUaoR ============================~~~~~~~~~~~~~~==~~==~===
CY7C162
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... > 200 1V 2
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Ambient
Temperature
in High Z State ...................... - 0.5V to + 7.0V
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OOCto + 70C 5V 10%
Output Current into Outputs (Low) ............. 20 mA Military [3] - 55C to + 125C 5V 1O%

7C161-20 7C161-25,35 7C161-45
Parameters Description Test Conditions 7C162-20 7C162.25, 35 7C16245 Units
IIX Input Load Current GND S VI S Vee -10 +10 -10 +10 -10 +10 }LA
Output Leakage GND S Vo s Vee, -10
loz +10 -10 +10 -10 +10 }LA
Current Output Dsbld.
los Current[!] Vee = Max., VOUT = GND -350 -350 -350 mA
Coml. 80 70 50
lee Supply Current lOUT = OmA 80 mA
Mil. I--- 70
Ws-
35 70
Coml. 40 20 20
Automatic CE Max. Vee, CE z VIH
ISBI Power Down Current Min. Duty Cycle = 100% Mil. 40 mA
I--- 20
Ws-
35 20
Automatic CE CE z Vee - 0.3V
ISB2 mA
Power Down Current VIN z Vee -0.3Vor
VIN s 0.3V Mil. 20 20
Capacitance [2]
Notes:
1. Not more than I output should be shorted at one time. Duration of 3. T A is the "instant on" case temperature.

RI481Sl R1481Sl
3.DV----~.....- - _ i . .
5 v o---~\h-..., 5v 0-----',..,..--.
OUTPUT 0--......- - 4 OUTPUT 0--_._--.--..

GND
30 pF R2 5 pF R2
I_~~g~~~N~
- SCOPE -
255n
I INCLUOING
_JIG AND
- SCOPE
_
-
25sn
0062-4 Figure 2
0062-6
Figure 18 Figure Ib
! Equivalent to: TlrnVENIN EQUIVALENT
16711
OUTPUT 0 - -.....',..',..- - 0 1.73 V 0062-5
2111
CY7C161
5A~UcroR =====================================================================
. . CY7C162
Switching Characteristics Over Operating Range[4, S, 12]

7C16120 7C16125 7C16135 7C16145
Parameters Description 7C16220 7C16225 7C16235 7C16245 Units
READ CYCLE
tACE CE LOW to Data Valid 20 25 35 45 ns
tLZCE CE LOW to Low Z[7] 5 5 5 5 ns
tHzcE CE HIGH to High Z[6, 7] 8 10 15 15 ns
tLzOE OE LOW to LOW Z 3 3 3 3 ns
tHZOE OE HIGH to HIGH Z 8 10 12 15 ns
tpu CE LOW to Power Up 0 0 0 0 ns
tpD CE HIGH to Power Down 20 20 20 25 ns
WRITE CYCLE[8]
tSCE CE LOW to Write End 15 20 25 30 ns
tLZWE WE HIGH to Low Z[7] (7CI62) 5 5 5 5 ns
tHZWE WE LOW to High Z[6, 7] (7CI62) 7 7 10 15 ns
tAWE WE LOW to Data Valid (7CI61) 20 25 30 35 ns
tADV Data Valid to Output Valid (7CI61) 20 20 30 35 ns
Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CEt. eE2 LOW and WE LOW. Both signals must be LOW to initi-
loading of the specified Ior/IOH and 30 pF load capacitance. ate a write and either signal can terminate a write by going HIGH.
6. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb. The data input setup and hold timing should be referenced to the
Transition is measured 500 mV from steady state voltage. rising edge of the signal that terminates the write.
7. At any given temperature and voltage condition, tHZ is less than tLZ 9. WE is HIGH for read cycle.
for any given device. 10. Device is continuously selected, CEl, CE2 = VIL.
11. Address valid prior to or coincident with CEl, CE2 transition LOW.
12. Both eEl and CE2 are represented by CE in the Switching Charac-
teristics and Waveforms.
Switching Waveforms[12]
___
Read Cycle No.1 (Notes 9, to)
ADD"," __.~
1- -=-=-~to-H_A-=-=tA-A "_:,-~~~~~~~*
==*
-,-----.
.
DATA OUT PREVIOUS DATA VALID
------.....-- --.....--...................................--
..........
DATA VALID
0062-7
2-112
CY7C161
5A .'
~NDUcrOR =====================================================================
CY7C162
Switching Waveforms [12] (Continued)

Read Cycle (Notes 9, 11)
tRC
~r-
1\
..,~
J
tACE
~~
t+----tLZOEi
tOOE L "'' :3 I+-tHZCE-
HIGH
IMPEDANCE
HIGH IMPEDANCE 1/ / / / / I
DATA OUT DATA VALID
1
/
tLZCE
1'" '" '" '" '" \.
~'"
t---tpu f---tpo
VCC _ _ _ _ _
SUPPLY 50% 50%
CURRENT _ IS8
0062-8

,
ADDRESS -- -It-
twc
t
tSCE ,
\\ \\\: ~I / / / V/ / /11 I II
tAW t HA -
tSA ~tpWE-
'I
~\\:' f-
tSD .1 tHO
DATA IN DATA-IN VALID ~
1- tHZWE.=j - - tLZWE
DATA OUT HIGH IMPEDANCE

DATA UNDEFINED 11
(7C162)
""
~I.....__________
-tAOV-
(7C161)
DATA OUT _ _ _ _ _ _ _ _ UNDEFINED
DATA _______ -..-jX DATA VALID _
0062-9

twc ,
ADDRESS -- -It-
tSA 'I t scE -
. tAW
\:
_ tpwE -
, -tHA-
\\ .\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ /////////////
I:: - t s o -:::::l tHO
DATA IN ~ DATA-IN VALID ~
DATA OUT
- t HZWE --:-1 HIGH IMPEDANCE
DATA UNDEFINED
(7C162) 11
-------D-AT-A-U-N-D-EF-IN-E-D---------~I--DA-T-A-V-AL-ID----
- tAwE -
DATA OUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J~~_ _ _ _ _ __
(7C161)
0062-10
Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C162 only).
2-113
CY7C161
(in~UaoR==================================================================
.. CY7C162

1.4 1.2 120
1.2 L 1.0
~ Ci
! 100
~
leV ....z
~ 1.0 ~ w
~
<.i
/' U 0.8 cz: 80
~
.!:! IZ:
0.8 ::l
S S
N
:; 0.6 /' N
::;
0.6
U
w
u 60
~
:I:
It

::E 0.4
IZ:
::l
0
40
~ Vee = 5.0 V
TA = 25'C
0.4 cz: <I)
"
0 0 Vee =5.0V ....
Z Z VIN =5.0V
0.2 ISB
0.2 I----ISB ....~ 20
"
::l
0
0.0 0.0
4.0
o
4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OCI OUTPUT VOLT AGE (V)

1.4 1.6 r-------r-------, 140
"
1.3
"
:l
1.4 I-----+------~ !
Ci
....
120
100
./V --
:l 1.2 ~
w
N
0
~
S
N
1.2 1-----+-----7'~_I IZ:
IZ: 80
/ Vee = 5.0 V
TA = 25'C
::;

1.1
..............
:::; ::l
U I
::E
..............
TA = 25C
~ 1.0 I-------:~::....-----~ '"z 60
0
cz:
z
1.0
r--- r---- ~
iii
....
~
40 /
0.9 0.8...."..,,:;....---+--------1 ....
::l
0 20
/
0.8
4.0 4.5 5.0 5.5 6.0
0.6 '--_ _ _ _.L...._ _ _ _ _
-55 25
~
125
V
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OCI OUTPUT VOLT AGE (VI

3.0 30.0 1.25
2.5 25.0 ~ Vee = 5.0 V

TA = 25'C
j 2.0 ] 20.0
/ 2
VIN = 0.5 V
filN
,/
0
::; 1.5 ""
;; 15.0
W
N
:::;

::E
cz:
~
1.0
@
o 10.0
/ ::E
a:
0
0.5 / 5.0
~
/ TA =25'C
Vee = 4.50 V
z
0.0
.-..V 0.0 / 0.50
0.0 1.0 2.0 3.0 4.0 5.0 o 200 400 600 800 1000 10 20 30 40
SUPPLY VOLTAGE (VI CAPACITANCE (pF) CYCLE FREQUENCY (MHz)
0062-12
2-114
CY7C161
5A~~UcrOR==================================================================
.
CY7C162

Ordering Code (ns) Ordering Code
CY7C161-20VC V21 CY7C162-20VC V21
CY7C161-20DC D22 CY7C 162-20DC D22
CY7C161-20LC L54 CY7C162-20LC L54
CY7C161-25VC V21 CY7C162-25VC V21
CY7C161-25DC D22 CY7C162-25DC D22
CY7C161-25LC L54 CY7C162-25LC L54
CY7C161-25DMB D22 Military CY7C162-25DMB D22 Military
CY7C161-25LMB L54 CY7C 162-25LMB L54
35 CY7C161-35PC P21 Commercial CY7C162-25KMB K74
CY7C161-35VC V21 35 CY7C162-35PC P21 Commercial
CY7C161-35DC D22 CY7C162-35VC V21
CY7C161-35LC L54 CY7C162-35DC D22
CY7C161-35DMB D22 Military CY7C162-35LC L54
CY7C161-35LMB L54 CY7C162-35DMB D22 Military
45 CY7C161-45PC P21 Commercial CY7C162-35LMB L54
CY7C161-45VC V21 CY7C162-35KMB K74
CY7C161-45DC D22 45 CY7C162-45PC P21 Commercial
CY7C161-45LC L54 CY7C162-45VC V21
CY7C161-45DMB D22 Military CY7C162-45DC D22
CY7C161-45LMB L54 CY7C162-45LC L54
CY7C 162-45LMB L54
BitMap CY7C162-45KMB K74
Address Designators
Address Address Pin
A5 X3 1
A6 X4 2
A7 X5 3
A8 X6 4
A9 X7 5
AlO YO 6
All Yl 7
A12 Y5 8
A13 Y4 9
AO Y3 23
Al Y2 24
A2 XO 25
A3 Xl 26
A4 X2 27
0062-13
2-115
CY7C161
fijis~~O~UcrOR========================================================~======
. CYPRF.SS CY7C162
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VlH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
lOS 1,2,3
IcC 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
tAWE[ll 7,8,9,10,11
tADV[ll 7,8,9,10,11
Note:
1. 7C161 only.
2-116
CY7C164
CYPRESS
SEMICONDUCTOR 16,384 X 4 Static RAM
Automatic power-down when The CY7C164 and CY7C166 are high for the 7CI66). Data on the four in-
deselected performance CMOS static RAMs orga- put/output pins (1/00 through 1/03) is
Output Enable (OE) Feature nized as 16,384 x 4 bits. These RAMs written into the memory location speci-
(7CI66) are developed by Aspen Semiconductor fied on the address pins (Ao through
Corporation, a subsidiary of Cypress A13)
CMOS for optimum speed/ Semiconductor. Easy memory expan-
power Reading the device is accomplished by
High speed
sion is provided by an active LOW chip
enable (CE) and three-state drivers.
taking chip enable (CE) LOW (and ern
LOW for 7CI66), while write enable
-10 ns tAA The CY7C166 has an active low output (WE) remains HIGH. Under these
Low active power enable (OE) feature. Both devices have conditions the contents of the memory
- 525 mW at 40 MHz an automatic power-down feature, re- location specified on the address pins
ducing the power consumption by 60% will appear on the four data I/O pins.
Low standby power when deselected.
-150 mW The I/O pins stay in high impedance
TTL compatible inputs and Writing to the device is accomplished state when chip enable (CE) is HIGH,
outputs when the chip enable (CE) and write or write enable (WE) is LOW (or out-
enable (WE) inputs are both LOW put enable (OE) is HIGH for 7CI66).
Capable of withstanding greater (and the output enable (OE) is LOW
than 2001 V electrostatic
discharge
Logic Block Diagram DIP Pin Configurations

AS Vee Vee As Vee
AS A. A. As A.
A3 A3 A3
A2 Aa
A, Ag
A,o A,O AO
An An
A,
A2
A3 0150-2
1/2
A.
As
As
A7
I/O, LCC Pin Configurations
Aa
1/0
3 20
3 2l!l282~6 NC
A7 A3 As
CE Aa 19 A2 A7 5 25 A.
Ag 1a A, Aa 6 24 A3
A,o 17 Ao Ag 23 A2
An 16 1/3 A,o 22 A,
WE A'2 15 1/2 An 9 21 Ao
_.----(OE)
(7C 166 ONLY) Au 1. I/O, A'2 10 20 1/3
10111213 AU 11 19 1/02
0150-1 Cl: 12 18 I/O,
Itl ~I~~ 1314151617
0150-5 I~ ~ lil~~
0150-6
Selection Guide
7CI64-10 7CI64-12 7CI64-15
7C166-10 7CI66-12 7C166-15
I

2-117
CY7C164
5n .
~UCTOR =====================================================================
Maximum Ratings
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... >2001V
in High Z State ...... " ..... '" ...... -0.5V to + 7.0V Range
Temperature Vee
Input Voltage[t4] .................... -3.0V to + 7.0V Commercial OC to +70C 5V 1O%
Output Current into Outputs (Low) ............. 20 mA Military [3] - 55C to + 125C 5V 10%
7CI64-10 7CI64-12 7CIM-IS
Parameters Description Test Conditions 7C166-10 7C166-12 7C166IS Units
VIL Input LOW Voltage[l4] -0.5 0.8 -0.5 0.8 -0.5 0.8 V
IIX Input Load Current GND::;; VI::;; Vee -10 +10 -10 +10 -10 +10 IJ-A
Output Leakage GND ::;; Vo ::;; Vee, -10 -10
loz + 10 + 10 -10 +10 IJ-A
los CurrentU] Vee = Max., VOUT = GND -350 -350 -350 rnA

leel Supply Current lOUT = OmA rnA
f = 40 MHz Military 130 130

lee2 Supply Current lOUT = OmA rnA
f = fmax. Military 150 135
Automatic CE[2] Max. Vee, CE 2 VIH Commercial 30 30 30
ISB rnA
Capacitance [5]
Parameters Description Test Conditions Max,[15] Units
CIN Input Capacitance TA = 25C, f = 1 MHz, 5
Vee = 5.0V pF
Notes:
2. A pull-up resistor to Vee on the CE input is required to keep the information.
device deselected during Vee power-up, otherwise ISB will exceed 5. Tested initially and after any design or process changes that may
values given. affect these parameters.

R1481.11. Rl 481.0. 3.0V----j~---i..
5V O---.J../Ijl\r---, 5Vo----Alt.fY-......
OUTPUT o--+----t OUTPUT O--+---~
GND
R2 R2
I-= ~CLUDING
255.0. 5Pf 255.0.
JIG AND
SCOPE
I-= INCLUDING
JIG AND
SCOPE 0150-7
Figure 2
0150-8
Figure 1a Figure 1b
OUTPUT 0---'\.,... ."".--0

16m
1.73 V 0150-9
2-118
CY7C164
5A~~UcrOR=====================================================================
Switching Characteristics Over Operating Range[4, 61

7CI64-10 7CI64-12 7CI64-15
Parameters Description 7C166-10 7C166-12 7C166-15 Units
READ CYCLE

Output Hold from Address
tOHA 2 3 3 ns
Change
tDOE OE LOW to Data Valid 7C166 8 10 10 ns
tLZOE OE LOW to LOW Z 7C166 2 2 3 ns
tHZOE OE HIGH to HIGH Z 7C166 8 9 8 ns
tLzCE CE LOW to Low Z[s] 2 3 3 ns
tHZCE CE HIGH to High Z[7, s] 6 8 8 ns

WRITE CYCLE[9]


tHZWE WE LOW to High Z[7, S] 0 5 0 7 0 7 ns

Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing 10. WE is HIGH for read cycle.
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output 11. Device is continuously selected, CE = VIL. (7CI66: OE = VIL
loading of the specified lorJIOH and CL = 30 pF load capacitance also.)
for 15 ns tAA devices and CL = 20 pF load capacitance for 10 and 12. Address valid prior to or coincident with CE transition low.
12 ns tAA devices.
13. 7C166 only: Data I/O will be high impedanceifOE = VIR.
7. tHzCE and tHzwE are specified with CL = 5 pF as in Figure 1h.
Transition is measured 500 mV from steady state voltage. 14. VIL (min.) = - 3.0V for pulse width < 20 ns.
S. At any given temperature and voltage condition, tHZCE is less than 15. For all packages except cerdip (DlO, D14) which has maximums of
tLZCE for any given device. These parameters are guaranteed and not CIN = 10 pF, COUT = 12 pF.
100% tested.
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
2-119
CY7C164
Wn .
~~U~R==================================================================
Switching Waveforms
*_
Read Cycle No. l.(Notes 10, 11)
=l
~--------------------------tRc--------------------------~1.
ADDRESS _ _ _ _
DATA OUT _
______ ~~~.:_.:_.:__-_- ~_H_A
__
PREVIOUS DATA VALID
V
____t_AA_ _ .'
DATA VALID
----------------------------------------------- 0150-10

tRC
j~ -l-
tACE
Oe
(7C166)
~~ -I
tOOE 'l-
I---tLZOEi ~'M:J
f.-tHZCE-
HIGH
DATA OUT
HIGH IMPEDANCE
----1' '- X,
1/ 7 , , ,
VCC
SUPPL
CURRENT
Y ________
_
!--tpu
J tLZCE
50%
'-
!--tpo
0150-11

~--------------------------twc------------------------~
)4---------- tscE---------------------+l
1+------- - - - - - - - t A w --------------------<~
i+-----tSA ~------tME-------
14-~---- tso--------+I-oo-
tHZWE~
DATA I/O - - - - - - - - - D A - T - A - U - N - D E - F - I N - E - D - - - - - - - )~--...;.;.;.;;;.;..;;;;;.,;;,;;.;.~;;....-~'-_ _ _ _ __
0150-12
2-120
CY7C164
(;Ii~NDUcroR =====================================================================

~----------------------~C----------------------~
t+----- tSA -------r--- tSCE------
----tPWE ----------~
~-+-----------tSD------t--
tHZWE---1
--------------~ HIGH IMPEDANCE

DATA 1/0 DATA UNDEFINED J~-----------------
0150-13
Note: IreE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
7C164 Truth Table 7C166 Truth Table

CE WE Input/Outputs Mode CE WE OE Inputs/Outputs Mode
H X HighZ Deselect Power Down H X X HighZ Deselect Power Down
L H Data Out Read L H L Data Out Read
L L Data In Write L L X Data In Write
L H H HighZ Deselect
lO CY7CI64-lOVC V13 Commercial lO CY7CI66-lOVC V13 Commercial
CY7CI64-lOLC L52 CY7CI66-lOLC L54
CY7C164-12VC V13 CY7C166-12VC V13
CY7C164-12DC DlO CY7C166-12DC D14
CY7C164-12LC L52 CY7C166-12LC L54
CY7CI64-12DMB DlO Military CY7CI66-12DMB D14 Military
CY7C164-15VC V13 CY7C166-15VC V13
CY7C164-15DC DlO CY7C166-15DC D14
CY7C164-15LC L52 CY7C166-15LC L54
CY7CI64-15DMB DlO Military CY7C166-15DMB D14 Military
2-121
CY7Cl64
WA~ucr~==============================================================
.

DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tDOE[l] 7,8,9,10,11
WRITE CYCLE
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Note:
1. 7C166 only.
Document #: 38-A-OOOI5
2-122
CY7C164
CY7C166
CYPRESS
Automatic power-down when The CY7C164 and CY7C166 are high is written into the memory location
deselected performance CMOS static RAMs orga- specified on the address pins (Ao
Output Enable (OE) Feature nized as 16,384 x 4 bits. Easy memory through A13).
(7CI66) expansion is provided by an active Reading the device is accomplished by
LOW chip enable (CE) and three-state taking chip enable (CE) LOW (and OE
CMOS for optimum speed/ drivers. The CY7C166 has an active
power LOW for 7CI66), while write enable
low output enable (OE) feature. Both (WE) remains HIGH. Under these
High speed devices have an automatic power-down conditions the contents of the memory
- 20 ns tAA feature, reducing the power consump- location specified on the address pins
Low active power tion by 60% when deselected. will appear on the four data I/O pins.
-440mW Writing to the device is accomplished The I/O pins stay in high impedance
Low standby power when the chip enable (CE) and write state when chip enable (CE) is HIGH,
-110 mW enable (WE) inputs are both LOW or write enable (WE) is LOW (or out-
TTL compatible inputs and (and the output enable (OE) is LOW
for the 7CI66). Data on the four
put enable (om
is HIGH for 7CI66).
outputs A die coat is used to insure alpha im-
input/output pins (1/00 through 1/03) munity.
discharge
Logic Block Diagram DIP Pin Configurations
A6
A7
AS A2 AS
As AI As
A12
AI 1/3
A2 0056-2
A3 0056-16 0056-3
1/2
A4
A5
A6
LCC Pin Configurations
1/1
A7
As
1/0
2 ~2221 43 i@2S27
AS 26 NC
A7 3 20 A3
A7 5 25 A4
AS 4 19 A2
As 24 A3
CE A9 18 AI
A9 23 A2
AID 17 AD
AID 22 AI
All 7 16 1/3 All 9 21 Ao
A12 8 15 1/2 20
A12 10 1/3
WE
__,p---(OE) A13 9 14 1/1 11 19
A13 1/2
10111213 CE 12 IS
(7C166 ONLY) 1/1
1314151617
0056-1 It: ~I~ if 0056-4 I~ ~ ~I~ g 0056-5
Selection Guide
7Cl64-20 7Cl64-2S 7Cl64-3S 7Cl64-4S
7C166-20 7C166-2S 7C166-3S 7C166-4S
Maximum Operating Commercial 80 70 70 50
Current (mA) Military 80 70 70
2-123
CY7C164
Wn~UcroR =====================================================================
.
Maximum Ratings
. CY7C166
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... >2001V
Power Applied .................... - 55C to + 125C Latch-up Current. ......................... > 200 rnA
in High Z State ...................... -0.5V to + 7.0V Range Vee
Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OCto +70C 5V 1O%
7C164-20 7CI64-25, 35 7CI64-45
Parameters ' Description Test Conditions 7C166-20 7CI66-25, 35 7C166-45 Units
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 2.4 2.4 V
VIL Input LOW Voltage[SA] -3.0 0.8 -3.0 0.8 -3.0 0.8 V
IIX Input Load Current GND::;: VI::;: Vee -10 +10 -10 +10 -10 +10 p,A
Output Leakage GND ::;: Vo ::;: Vee, -10 -10
loz +10 +10 -10 +10 p,A
los Current[l] Vee = Max., VOUT = GND -350 -350 -350 rnA
Cornl. 80 70 50
~ - 80
Icc Supply Current lOUT = OmA Mil. rnA
70
35 70
Automatic CE[2] Coml. 40 20 20
Max. Vee, CE 2 VIR
~
ISBl Power Down Current Min. Duty Cycle = 100% Mil. 40 rnA
r--- 20
35 20
Automatic CE[2] CE 2 Vee - 0.3V
ISB2 Power Down Current rnA
VIN 2 Vee -0.3Vor
VIN::;: 0.3V Mil. 20 20
Capacitance [5]
Vee = 5.0V pF
Notes:
2. A pull-up resistor to Vee on the eE input is required to keep the S. Tested initially and after any design or process changes that may
device deselected during Vee power-up, otherwise ISB will exceed affect these parameters.
values given. SA. VIL min. = - 3.0V for pulse durations less than 30 ns.
3. T A is the "instant on" case temperature.

Rl481U R1481!l
5v o---~f'r-..., 5v O----JV'.,.,....-,
OUTPUT C > - - _ - - - i OUTPUT 0--_---+
30 pF R2 5 pF R2
I INCLUDING
_JIGAND _
- SCOPE -
265H
I-:-~6~~~D
INCLUDING
-=-
255U
0056-6
0056-7

16711
OUTPUT o~--'\~",.I\.o.---<O 1.73 v 0056-8
2-124
CY7C164
fin .
~NDUcroR =====================================================================
CY7C166

7Cl64-20 7C164-25 7Cl64-35 7Cl64-45
Parameters Description 7C166-20 7C166-25 7C166-35 7C166-45 Units
READ CYCLE
Output Hold from Address
tOHA 5 5 5 5 os
Change
tACE CE LOW to Data Valid 20 25 35 45 os
tDOE OE LOW to Data Valid 7CI66 10 12 15 20 os
tLZOE OE LOW to LOW Z 7C166 3 3 3 3 ns
tHZOE OE HIGH to HIGH Z 7C166 8 10 12 15 os
tLZCE CE LOW to Low Z[S] 5 5 5 5 ns
tHZCE CE HIGH to High Z[7, S] 8 10 15 15 os
tPD CE HIGH to Power Dowo 20 20 20 25 os
WRITE CYCLE[9]
twc Write Cycle Time 20 20 >. 25 40 os

tSCE CE LOW to Write Eod 15 20 25 30 os
tAW Address Set-up to Write Eod 15 20 25 30 os
tHA Address Hold from Write Eod 0 0 0 0 os
tSA Address Set-up to Write Start 0 0 0 0 os
tpwE WE Pulse Width 15 15 20 20 os
tSD Data Set-up to Write Eod 10 10 15 15 os
tHD Data Hold from Write Eod 0 0 0 0 os
tLZWE WE HIGH to Low Z[S] 5 5 5 5 os
tHZWE WE LOW to High Z[7, S] 7 7 10 15 os
Notes:
loading of the specified IorJIOH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
7. tHZCE and tHZWE are specified with CL = 5 pF as in Figure lb. data input setup and hold timing should be referenced to the rising
S. At any given temperature and voltage condition, tHzCE is less than 10. WE is HIGH for read cycle.
tLZCE for any given device. These parameters are guaranteed and not 11. Device is continuously selected, CE = VIL. (7CI66: OE = VIL
100% tested. also.)
12. Address valid prior to or coincident with CE transition low.
13. 7C166 only: Data I/O will be high impedance ifOE = VIH.
Switching Waveforms
0056-9
2-125
CY7C164
fiii~NDUcrOR =====================================================================
. CY7C166

tRC
J t -l-
tACE
BE
(7CI66)
~~ I-
~
"'~:3
i+---tDOE
-tHzcE-
-tLZOEi
HIGH
HIGH IMPEDANCE II I I I I II' IMPEDANCE
DATA OUT DATA VALID
---1'" .~ _\. ...\. '" I\.
J lLZCE J
I--tpu -tPD
VCC _ _ _ _ _
SUPPLY 50%
CURRENT _
0056-10
~----------------------------~C--------------------------~
1------------------ tscE------------------------i
~----------------------tAW----------------------~~--
14------tSA--------,.j 14------tPWE-------,.j
~-'--------tSD ----------.jo.-
tHZWE :::::::j
DATA 1/0 ---------D-A-T-A-U-ND-E-F-IN-E-D------- )0----------"'\.______
0056-11
I---------------------------~C--------------------------~
1-------- tSA -----.j4-- - - - - I S C E - - - . "----
. ---tPWE -----------l
~_t_------------tSD------~f__
tHZWE-----l
------------------~ HIGH IMPEDANCE

DATA I/O 'DATA UNDEFINED ~).---------------------
0056-12
2-126
CY7C164
(;A~~NDUcrOR ======================================================================= CY7C166

1.4 1.2 120
1.2
./ 1.0
~
! 100
~
lev I-
'" 1.0 '"
<II
ffiII:
~ V ~
0.8 80
~
II:
;:)
0 0.8
fil \,)
IU
N
/'" N 0.6 IU
\,) 60
"" '"
~ 0.6 ~ II: Vee = 5.0 V
<{ <{ ;:)
:! TA = 25>C
:IE 0.4 0
40
II: II: (I)
0 0.4 0 Vee =5.0 V I-
2 2 VIN =5.0 V ;:)
0-
0.2 0.2 I---IS8 I- 20
Iss
'"
;:)
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ('CI OUTPUT VOLTAGE (V)

1.4 1.6 140
1.3
1.4 ~----+-------4

!
120
~
./'
I- /
'" ffi
100
Vee =5.0 V
$ 1.2
fil
$
fil
N
1.2 ~----+-----7""'-~ II:
II: 80
/ TA = 25'C
N
~ 1.1
" ::;
;:)
\,)
I
"' ---....t---
<{
z'"
<{
TA = 25'C 60
:IE
II:
0 1.0 ~ ~
oz
1.0 I------:~'------_I
iii
/
I- 40
2
itI-
0.9 0.8 t-::.~---+-------1 ;:)
0 20
/
0.8
4.0 4.5 5.0 5.5 6.0
0.6 L-_ _ _ _.L...._ _ _ _ _ ~ V
-55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE I'CI OUTPUT VOLTAGE (VI

--
3.0 30.0 1.25 r----......,,....----r---....,
2.5
Vee ~ 5.0 V
25.0 TA 25'C
E 2.0 ] 20.0
/ 2 1.01---__
VIN = 0.5 V
f----4---...,..
fil
N
~
<{
1.5

~ 15.0 ,r
/ fil
N
::;
:IE ~
II:
~
1.0
@
o 10.0 / ~ 0.75t------ii::;oo'E:---4------i
0.5 /' 5.0

// TA = 25'C
Vee = 4.50 V
V /
0.0
0.0 1.0 2.0 ---
SUPPL Y VOLTAGE (VI
3.0 4.0 5.0
0.0
o 200 400 600
CAPACITANCE (pFI
800 1000
0.501':0---~2~0---.....
30----40
..
CYCLE FREQUENCY (MHzl
0056-14
2-127
CY7C164
(;n~~ucr~==================================================================
. CY7C166

CE WE Input/Outputs Mode CE WE OE Inputs/Outputs Mode
H X HighZ Deselect Power Down H X X HighZ Deselect Power Down
L H Data Out Read L H L Data Out Read
L L Data In Write L L X Data In Write
CY7C164-20VC V13 CY7C166-20VC V13
CY7C164-20DC D10 CY7C166-20DC D14
CY7C164-20LC L52 CY7C166-20LC L54
CY7C164-25VC V13 CY7C166-25VC V13
CY7C164-25DC D10 CY7C166-25DC D14
CY7C164-25LC L52 CY7C166-25LC L54
CY7C164-25DMB 010 Military CY7CI66-25DMB D14 Military
CY7CI64-25LMB L52 CY7C166-25LMB L54
CY7C164-25KMB K73 CY7CI66-25KMB K73
CY7C164-35VC V13 CY7C166-35VC V13
CY7C164-35DC D10 CY7C166-35DC D14
CY7C164-35LC L52 CY7C166-35LC L54
CY7C164-35DMB 010 Military CY7CI66-35DMB D14 Military
45 CY7C1 64-45PC P9 Commercial 45 CY7C166-45PC P13 Commercial
CY7C164-45VC V13 CY7C166-45VC V13
CY7C164-45DC D10 CY7C166-45DC 014
CY7CI64-45LC L52 CY7C166-45LC L54
CY7C164-45DMB DI0 Military CY7CI66-45DMB D14 Military
CY7C164-45LMB L52 CY7CI66-45LMB L54
2-128
CY7C164
~RF.SS CY7C166
.nlCONDUcrOR
II
2-129
.. CY7C164
5'11 . CYPRESS CY7C166
~OO~U~R================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
ICC 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tOOE[1] 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tso 7,8,9,10,11
tHo 7,8,9,10,11
Note:
1. 7Cl66 only.
2-130
CY7C167
CYPRESS
Features
deselected
The CY7C167 is a high performance
CMOS static RAM organized as
Reading the device is accomplished by
taking the chip enable (CE) LOW,
fI
16,384 words x 1 bit. Easy memory ex- while write enable (WE) remains
CMOS for optimum
speed/power pansion is provided by an active LOW HIGH. Under these conditions the
chip enable (CE) and three-state driv- contents of the memory location speci-
High speed-25 ns ers. The CY7C167 has an automatic fied on the address pins will appear on
Low active power power-down feature, reducing the pow- the data output (~O) pin.
-275mW er consumption by 67% when deselect- The output pin stays in high impedance
ed. state when chip enable (CE) is HIGH
Low standby power
-83mW Writing to the device is accomplished or write enable (WE) is LOW.
when the chip enable (CE) and write A die coat is used to insure alpha im-
TTL compatible inputs and enable (WE) inputs are both LOW.
outputs munity.
Data on the input pin (01) is written
Capable of withstanding greater into the memory location specified on
than 2001 V electrostatic the address pins (Ao through A13)'
discharge

01
01')
.... OO~
<e<e><e Ao Vee
Al A13
A2 A12
A2 A12
A3 All
A3 A11
DO A4 A10 A4 A10
AS Ag As Ag
A6 AS A6 As
DO A7 DO A7
CE W! 01
GNO CE
I~ C)
~I~ 0
0017-3
WE 0017-2
0017-1
Selection Guide
7C167-25 7C167-35 7C167-45
Maximum Operating
STD I Commercial 60 60 50
Current (rnA)
I I Military 60 50
2-131
~ CY7C167
~~~UaoR =====================================================================
Maximum Ratings
(Pin 20 to Pin 10) .................... -0.5V to + 7.0V
Range Vee
in High Z State ...................... - O. 5V to + 7.0V Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to + 70C 5V 10%

7C16725 7C16735 7C16745
Vee = Min., IOL = 12.0 rnA,
VOL Output LOW Voltage 0.4 0.4 0.4 V
8.0 rnA Mil
IIX Input Load Current GND ~ VI ~ Vee -10 + 10 -10 + 10 -10 +10 p.A
Output Leakage GND ~ Vo ~ Vee
Ioz Current Output Disabled
-50 +50 -50 +50 -50 +50 p.A
Output Short[1] Vee = Max., -350 -350 -350
los mA
Circuit Current VOUT = GND
lee mA
Supply Current lOUT = OmA Military 60 50
Automatic CE[2] Max. Vee, Commercial 20 20 15
ISB mA
Power Down Current CE ~ VIR Military 20 20
Capacitance [5]
CIN Input Capacitance 4
TA = 25C, f = 1 MHz
CoUT Output Capacitance Vee = 5.0V 6 pF
CeE Chip Enable Capacitance 5
Notes:
1. Duration of the short circuit should not exceed 30 seconds. 3. TA is the "instant on" case temperature.
2. A pull-up resistor to Vee on the eE input is required to keep the 4. See the last page of this specification for Group A subgroup testing
device deselected during Vee power-up, otherwise ISB will exceed information.
values given. S. Tested initially and after any design or process changes that may
R13290 R13290
(481 o MIL) (481 o MIL) All Input Pulses
5 v O----.J,J..",...., 5 v o----JtI',/v-..,
3.0 V ------::ro..... ---L
OUTPUT 0---9---"" OUTPUT 0 - - - . . _ - - - 1
I
GND
R2 R2
2020 5pF 2020
INCLUDING 30 pF (256f1 MIL) (2560 MIL)
JIG AND INCLUD,Nl 0017-6
SCOPE JIG AND
SCOPE ':" Figure 2
':" 0017-4
Figure 1a Figure 1b
l2S.n.
OUTPUT~ 1.9V COMMERCIAL
l67.n.
OUTPUT~1.73V MILITARY 0017-5
2-132
~ CYPP.fSS CY7C167
WnlCONDUcrOR =================================================================
Parameters Description
7C167-25 7C167-35 7C167-45 I Units
READ CYCLE
tRC Read Cycle Time (Commercial) 25 30 40 ns
tRC Read Cycle Time (Military) 25 35 40 ns
tAA Address to Data Valid (Commercial) 25 30 40 ns
tAA Address to Data Valid (Military) 35 40 ns
tOHA Data Hold from Address Change 3 3 3 nS
tLZCE CE LOW to Low Z[s] 5 5 5 ns
tHZCE CE HIGH to High Z[7, s] 15 20 25 ns
WRITE CYCLE[9]
tAw Address Set-up to Write End 25 30 40 ns
tHzwE WE LOW to High Z[7, S] 15 20 20 ns
tLzwE WE HIGH to Low Z[S] 0 0 0 ns
Notes:
loading of the specified Ior/IOH and 30 pF load capacitance. write and either signal can terminate a write by going high. The data
7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb.
input setup and hold timing should be referenced to the rising edge
Transition is measured 500 mV from steady state voltage. of the signal that terminates the write.
S. At any given temperature and voltage condition, tHz is less than tLZ 10. WE is HIGH for read cycle.
for any given device. I 1. Device is continuously selected, CE = VIL.
Switching Waveforms
ADDRESS ---J:I--_-_-_-_-_-_tRC-=--=--=--=--=-~--.l*_ _
DATA OUT
~~~~----tOHA------~
0017-7
2-133
~ CY7C167
~~~UaoR==================================================================
tRC
J ...,'f-
t
tACE . I
DATA OUT
lZCE
t
HIGH IMPEDANCE
::-! 1/ / / f J " DATA VALID
_tHZCE~1 HIGH
IMPEDANCE
1
/
!--tpu
I" " " " " I\. i---tpo
--j
VCC _ _ _ _ _ _
SUPPLY
CURRENT _
50%
5:t- ICC
156
0017-8
~-----------------------------~C--------------------------~~
ADDRESS
~-------------------tSCE----------------------~
~-----------------------tAW----------------------~~---
~---------tSA------------.l ~------t~E------~~
'----'-------tso-------__+-
DATA 1/0 ----------DA-T-A-U-N-D-E-FI-N-ED--------

tHZWE~
>)O---.. . . . . . . . . . . . . . .--~"- ______
0017-9

~---------------------------~c--------------------------~
---------t-----------tSCE ----------1
~---------t~E--~--------~
~_+_----------tso-------__+-
DATA-IN VALID
tHZWE------l
------------------~
DATA I/O DATA UNDEFINED /)0---------------------- HIGH IMPEDANCE
0017-10
2-134
~ CY7C167
~~~UcrOR =====================================================================

1.4 1.2 60
1.2 / 1.0
~ <
E 50 ~
., .,
~
""
Icy I- Vee = 5.0 V
1.0 ~ Til = 25"C
~
8N 0.8 V ~
S
0.8 a:
a:
~
u
40
:::i 0.6

V N
::;

0.6 w
u
a:
~
30
~
::!! :IE
a: 0.4 a: 0.4 ~ 20
0
z 0
z
Vee = 5.0V
VIN = 5.0 V
I- ,,~
~
0.2 0.2 r-ISB I- 10
"
ISB ~
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE rC) OUTPUT VOLTAGE (V)

-
1.4 1.6 ~----.-------.., 150
~
1.3
1.4 .....- - - - + - - - - - - - i
< 125
4:
:5 1.2 '"
:5
E
I-
Z
w 100
~V
S
8N
:::i 1.1 i'oo.. N
::;

1.2 ~----t----'7"''''--t a:
a:
~
u 75
(
/

:0
a:
'" ............. TA = 25'C ~ 1.0 ~---__:::...,-::------t z"
iii /
- oz
0 1.0 50
~
z
/
I-
~
0.9 0.8 ~-----+-------i I-
~ 25 ~~e= =2~;~ V -
o/
0
0.8
0.6 '--_ _ _ _L.-_ _ _ _ _.... I
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0 5.0

3.0 30r--~--r--~~-.--~ 1.1 r-----,----T---...,
TA = 25'C Vee = 5.0 V
2.5 Vee = 4.5 V TA = 25'C
VIN = 0.5 V
.E 2.0 20~-~--+-~~-+--~ ~ 1 . 0 1 - - - - - - i - - - - + - - -.....
...0
N
@
N
::; 1.5 ::;

::!!

a: :IE
z0
1.0 10~-~~-+-~~-+--~ :5z 0.9 ~--_t-~c--+----f
L
0.5
0.0
0.0 1.0 2.0 -
SUPPLY VOLTAGE (V)
V
3.0 4.0 5.0 200 400 600
CAPACITANCE (pF)
800 1000 20

30
0017-11
2-135
~~============================================C=Y=7=C=1=6=7
Speed IcC Ordering Package Operating
(ns) rnA Code Type Range
25 60 CY7C167-25PC P5 Commercial
CY7C 167-250C 06
CY7C167-25LC L51
CY7C167-25VC V5
CY7C167-350C 06
CY7C167-35LC L51
CY7C167-35VC V5
CY7C167-350MB 06 Military
CY7CI67-35LMB L51
CY7C 167-450C 06
CY7C167-45LC L51
CY7C167-45VC V5
CY7CI67-45LMB L51
2-136
~ CY7C167
~~~NDUcrOR ================================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
fJI
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #: 38-00033-0
2-137
CY7C167A
CYPRESS
Automatic powerdown when The CY7C167A is a high performance Reading the device is accomplished by
16,384 words x 1 bit. Easy memory ex while write enable (WE) remains
CMOS for optimum
speed/power pansion is provided by an active LOW HIGH. Under these conditions the
High speed-20 ns ers. The CY7C167A has an automatic fied on the address pins will appear on
Low active power power-down feature, reducing the pow- the data output (DO) pin.
- 275 mW er consumption by 67% when deselect- The output pin stays in high impedance
ed. state when chip enable (CE) is HIGH
Low standby power
-83mW Writing to the device is accomplished or write enable (WE) is LOW.
when the chip enable (CE) and write A die coat is used to insure alpha im-
TIL compatible inputs and enable (WE) inputs are both LOW.
outputs munity.
Data on the input pin (DI) is written
Capable of withstanding greater into the memory location specified on
than 2001 V electrostatic the address pins (Ao through A13).
discharge
VIH of 2.2V
...--------c ~----- 01
01<)
- 00-
.:(.:(>.:( Ao Vee
Al Al3
Ao A2 A'2
A12
Al
A11 A3 All
A2
DO A 10 A4 A,O
A3
A4 Ag As Ag
As As A6 As
A6 A7 DO A7
CE ~ 01
I~ ~I~ 0 GNO CE
C)
0161-2 0161-3
We
0161-1
Selection Guide
7C167A20 7C167A25 7C167A35 7C167A45
Maximum Operating
Current (rnA)
STD I Commercial 80 60 60 50
I I Military 70 60 50
2-138
~ CY7C167A
~~~~UcrOR=====================================================================
Maximum Ratings

DC Voltage Applied to Outputs Range
Ambient
Vee
in High Z State ...... , ............... -0.5V to + 7.0V Temperature

7C167A-20 7C167A-25 7C167A-35 7C167A-45
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 2.4 2.4 2.4 V
Vee = Min., IOL = 12.0 rnA,
VOL Output LOW Voltage 0.4 0.4 0.4 0.4 V
S.O rnA Mil
VIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee 2.2 Vee V
VIL Input LOW Voltage[5A] -0.5 O.S -0.5 O.S -0.5 O.S -0.5 O.S V
IIX Input Load Current GND:S;; VI:S;; Vee -10 +10 -10 +10 -10 +10 -10 +10 ""A
Output Leakage GND:S;; Vo:S;; Vee
Ioz -10 +10 -10 +10 -10 +10 -10 +10 ""A
Output Shortl1] Vee = Max.,
los -350 -350 -350 -350 rnA
Circuit Current VOUT = GND
Vee Operating Vee = Max. Commercial SO 60 60 50
lee rnA
Supply Current lOUT = OmA Military 70 60 50
Automatic CE[2] Max. Vee, Commercial 40 20 20 15
ISB rnA
Power Down Current CE:::: VIH Military 20 20 20
Capacitance [5]
TA = 25C, f = 1 MHz
COUT Output Capacitance Vee = 5.0V 6 pF
CeE Chip Enable Capacitance 5
Notes:
1. Duration of the short circuit should not exceed 30 seconds. 4. See the last page of this specification for Group A subgroup testing
device deselected during Vee power-up, otherwise ISB will exceed S. Tested initially and after any design or process changes that may
3. T A is the "instant on" case temperature. SA. VIL min. = - 3.0V for pulse durations less than 30 ns.

R13290 R13290
(481 o MIL) (481 o MIL) All Input Pulses
5 v C>----...JVVv-...., 5VC>----.JI,I'.>/'v---.
3.0V-----.I~-_-~
OUTPUT 0 - - - _ - - - 1 OUTPUT 0---_----"

GND
R2 R2
202f! 5pF 202f!
'NCLUD'NGI30 pF (255f! MIL) (255f! MIL)
JIG AND ,NCLUD'Nl 0161-6
JIG AND
SCOPE
SCOPE -= -= 0161-4
Figure 2
Figure 1a Figure 1b
125.0.
OUTPUT o----wv--o 1.9Y COMMERCIAL
167.0.
OUTPUT o----wv--o 1.73Y MILITARY 0161-5
2-139
~ CY7C167A
~~~NDUcrOR ~========================================================~======~
7C167A-20 7C167A-25 7C167A-35 7C167A-45
READ CYCLE
tRC Read Cycle Time (Commercial) 20 25 30 40 ns
tRC Read Cycle Time (Military) 25 35 40 ns
tAA Address to Data Valid (Commercial) 20 25 30 40 ns
tAA Address to Data Valid (Military) 35 40 ns
toHA Data Hold from Address Change 5 5 5 5 ns
tLZCE CE LOW to Low Z[S] 5 5 5 5 ns
tHZCE CE HIGH to High Z[7,S] 8 10 15 15 ns
tPD CE HIGH to Power Down 20 20 20 25 ns
WRITE CYCLE[9]
tHzwE WE LOW to High Z[7, S] 7 7 10 15 ns
tLZWE WE HIGH to Low Z[8] 5 5 5 5 ns
Notes:
loading of the specified IOI/IOH and 30 pF load capacitance. ;.vrite and either signal can terminate a write by going high. The data
mput setup and hold timing should be referenced to the rising edge
7. tHZCE and tHZWE are specified with CL = 5 pF as in Figure 1h.
Transition is measured 500 m V from steady state voltage. of the signal that terminates the write.
8. At any given temperature and voltage condition, tHZ is less than tLz 10. WE is HIGH for read cycle.
for any given device. 11. Device is continuously selected, CE = VIL.
Switching Waveforms
--J:f4--_-_-_-_-_-_":,-=--=--=--=--=--_----.1*_ _
~~--~----tOHA------~
ADDRESS
0161-7
2-140
~ CY7C167A
~~~NDUcroR =====================================================================
tRC
Jr- -l-
\.
tACE . I
tLZCE~ _tHZCE1
HIGH
HIGH IMPEDANCE I, , , I , If IMPEDANCE
DATA OUT DATA VALID
1
I'-~ \.._\..~ ~ J
_tpu i---1PD
VCCV _ _ _ _ _ _
SUPPL
CURRENT _
50%
=:C'"
50%
158
0161-8
~-----------------------------twc--------------------------~~
ADDRESS
14----------- t SCE - - - - - - - - - - - . - j
~-------------------tAW-----------------4~---
~-------tSA---------..j ~------t~E------_._j
........--'------tSD------~1+-
tHZWE~
DATAIIO ----------D-AT-A-U-N-D-E-F-IN-E-D------- )-----------c_______
0161-9

~----------------------twc-----------------~
ADDRESS
------too-------tSCE----------i
~-----t~E---------~
WE
1--+--------tSD-----~-
IHZWE---"
------------------~ HIGH IMPEDANCE
DATA 110 DATA UNDEFINED J~---------------------
0161-10
2-141
~ CY7C167A
~~~NDUcrOR =====================================================================

1.4 1.2 60
1.2
ley
L 1.0
~
E 50 ~
~
"
III .... Vee = 5.0 V
1.0 ~ Z
w TA = 25"C
~
&1
0.8 V ~ O.B IE:
IE:
::l
u
40
.~
N
:::i 0.6 V &1
N 0.6 w
u
30
~
:::i a:
<l <l ::l
:E ::!:
a: 0.4 IE: 0.4 ~ 20
0
z 0 Vee = 5.0 V ....
0.2
z
0.2 r--ISB
VIN = 5.0 V
~
.... 10 "r-....
"
ISB ::l
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 55 25.0 125.0 o 1.0 2.0 3.0 4.0

1.4 1.6 r-----,..-------.., 150
"---
1.3
1------+-------1 125 ~

:! 1.2

:!
1.4 E
....Z
100
/'
w
C
w
N
:::i
<l
1.1
10..
............
&1
N
:::;
<l
1.2 t----:--t----:7'0::-, a:
a:
::l
u
:<:
75
If
/
--
TA = 25C ~ 1.0 I--------:~------I z
~ i
:E
a: iii
o 50
0
z
1.0
r---. z
h,;C----+------,
....
~
.... I
0.9 0.8
::l 25
roc
Vee = 5.0 V_
D.B
4.0 4.5 5.0 5.5 6.0
0.6 ' - - - - - - " - - - - - - -....
-55 25 125
0
V 1.0 2.0 3.0
TA =
4.0 5.0

3.0 3Dr--~--r--,--,--, 1.1 r-----.---~---....,
TA = 25C Vee = 5.0 V

2.5 Vee = 4.5 V TA = 25C
VIN = 0.5 V
~ 2.0 2DI---;---r-~~-+--~ 1l 1.0 t----Ir------t---~
cW
N
&1
N
:::; 1.5 :::;
<l <l
::eIE: :!:
1.0 lDI---~~~-~---+_--I ~ 0.9 t----t-~I:--+---_i
~
0.5 L
0.0
0.0 1.0 2.0 -
SUPPLY VOLTAGE (V)
V
3.0 4.0 5.0 200 400 600
CAPACITANCE (pF)
BOO 1000 20

30 40
0161-11
2142
~RESS CY7C167A
~~~O~UcrOR==================================================================
Icc

Speed Ordering Package Operating
(ns) rnA Code Type Range
20 60 CY7C167A-20PC PS Commercial
CY7C167A-20DC D6
CY7C167 A-20VC VS
2S 60 CY7CI67A-2SPC PS Commercial
CY7CI67A-2SDC D6
CY7CI67A-2SLC LSI
CY7CI67A-2SVC VS
CY7CI67A-2SDMB D6 Military
CY7C167 A-2SLMB LSI
3S 60 CY7CI67A-3SPC PS Commercial
CY7CI67A-3SDC D6
CY7CI67A-3SLC LSI
CY7CI67A-3SVC VS
CY7C167 A-3SLMB LSI
4S SO CY7CI67A-4SPC PS Commercial
CY7CI67A-4SDC D6
CY7CI67A-4SLC LSI
CY7CI67A-4SVC VS
CY7CI67A-3SPC PS
CY7CI67A-4SLMB LSI
2-143
~ CY7C167A
~~~~~~================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAw 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-144
CY7C168
CY7C169
CYPRESS
Features
Automatic power down when Capable of withstanding greater Data on the four input/output pins
deselected (7C168) than 2001 V electrostatic (1/00 through 1/03) is written into the
discharge memory location specified on the ad-
power dress pins (Ao through All).
Functional Description Reading the device is accomplished by
High speed The CY7C168 and CY7C169 are high taking chip enable (CE) LOW, while
- 25 ns tAA
performance CMOS static RAMs orga- write enable (WE) remains HIGH. Un-
- 15 ns tACE (7CI69)
nized as 4096 x 4 bits. Easy memory der these conditions the contents of the
Low active power expansion is provided by an active memory location specified on the ad-
- 385 mW LOW chip enable (CE) and three-state dress pins will appear on the four data
Low standby power (7CI68) drivers. The CY7C168 has an automat- I/O pins.
-83mW ic power-down feature, reducing the The I/O pins stay in high impedance
power consumption by 77% when de- state when chip enable (CE) is HIGH,
TTL compatible inputs and selected.
outputs or write enable (WE) is LOW.
Writing to the device is accomplished
when the chip enable (CE) and write
munity.
enable (WE) inputs are both LOW.

A4 Vee
As A3
A6 A2
A7 Al
As Ao
Ag 1/00
Ala 1/0 1
All 1/02
CE 1/03
1/00
GND WE
1/01
0021-2
(J
1/0 2 1I)..q-(J1I)
<0( <0( >-<
1/03
A6 A2
A7 4 A,
CE As Ao
Ag 1/0
A,o I/O,
we A" 1/2
0021-1
Itl ~I~ at<)

C,!) ~
0021-3
Selection Guide
7C168-25 7C16835
7C16940 7C16845
7C16925 7C16935
Maximum Operating
Current (rnA)
2-145
CY7C168
5n .
~U~==================================================================
Maximum Ratings
CY7C169
(Pin 20 to Pin 10) .................... -O.SV to + 7.0V
Operating Range
Range Vee
in High Z State ...................... -O.SV to +7.0V Temperature
Electrical Characteristics Over Operating Rangel3]

7C168-25 7C168-35 7C168-45
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 2.4 2.4 V
IIX Input Load Current GND:O:;: VI:O:;: Vee -10 +10 -10 +10 -10 +10 p,A
Output Leakage GND:O:;: Vo:O:;: Vee,
IOZ -50 +50 -50 +50 -50 +50 p,A
loS Currendll
Vee = Max., VOUT = GND -350 -350 -350 mA

lee mA
Automatic CE Max. Vee, Commercial 20 20 15
ISBl mA
Power Down Current CE ~ VIH Military 20 20
ISB2 mA
Power Down Current CE ~ Vee - 0.3V Military 20 20
Capacitance [4]
Notes:
2. TA is the "instant on" case temperature. 4. Tested initially and after any design or process changes that may

Rl481H R1481H 3.0 V --------j_____"'-
5V~------~~~~ 5V <r-------.....J'VV'w-......
OUTPUT ~----....- - - - - -.... OUTPUT o----~--- .. GND
30 pF R2 5 pF R2 <;; 5 ns -<;; 5 ns
I INCLUDING
_JIG AND
- SCOPE
_
-
255H
I-=- INCLUDING
JIG AND
SCOPE -=-
255\!
0021-4
Figure 2
0021-6
Figure 1a Figure Ib
16m
OUTPUT O--~""'''''''''~w---''''O 1.73V 0021-5
2-146
CY7C168
WA ~~NDUcrOR =====================================================================
CY7C169
Switching Characteristics Over Operating Rangd 3, 5]

7C16825 7C16835
7C16940 7C16845
Parameters Description 7C16925 7C16935 Units
READ CYCLE
tACE CE LOW to Data Valid

I 7C168 25 35 45 ns
17C169 15 25 25 ns
tHzCE CE HIGH to High Z[6, 7] 15 20 20 25 ns
tpu CE LOW to Power Up (7CI68) 0 0 0 ns
tpD CE HIGH to Power Down (7CI68) 25 25 30 ns
tRCS Read Command Set-up 0 0 0 0 ns
tRCH Read Command Hold 0 0 0 0 ns
WRITE CYCLErS]
tHZWE WE LOW to High Z[6, 7] 10 15 20 20 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing 8. The internal write time ofthe memory is defined by the overlap of
6. tHzCE and tHzwE are tested with CL = 5 pF as in Figure lb. Tran- data input setup and hold timing should be referenced to the rising
sition is measured 500 mV from steady state voltage. edge of the signal that terminates the write.
II. Address valid prior to or coincident with CE transition LOW.
Switching Waveforms
__
ADDRESS ---J:14---_-_-_-_-_-_-_t Rc
_ -_-_-
_-_-
_- _~*
DATA OUT
----1""-----tOHA---.. .
0021-7
2-147
CY7C168
fin~~~UcrOR ===================================================================== CY7C169

tRC
~ -f
tACE
DATA OUT
t
LZ
HIGH IMPEDANCE
=! " / / / / "
DATA VALID
~tHzj
~
HIGH
IMPEDANCE
'\.'\.'\.'\.'\. J
!---tpu_
I--tPO---\
(7C168) VCC ICC
SUPPLY j'l50% 50%
CURRENT ISB
~Il ~~
--
-J
i--tRcS I---tRCH - - -
0021-8

~----------------------------twc--------------------------~
ADDRESS
__/I~________________________________________- J
~-------------------tSCE--------------------~
I~~~~~~~~~~
CE
~~~----------------------------~~~L~~~~~
~----------------------~w-----------------------+~---
1.----------tSA--------..I ~------tME------~
r----------------------
!.--'-------tSD ---------+114-
DATA IN
-------------------J!'~~ __ DATA-IN VALID
--------~
tHzwE~
__ II~__- - - - - -_____
DATA 1/0 ---------D-A-T-A-U-N-D-EF-IN-E-D-------- )~--...;.;.;.;;.;..;.;,;;,~...;.;;.;;...--_<\,_ _ _ _ _ __
0021-9

I.---------------------------~C--------------------------~
ADDRE~ ___ ~-------------------------------------------'II'--------------

.--14------------ tSCE ------------1
--~--------------~I I~----~-------------
DATA IN ___________________~'-4_---------D~AT-A---IN-V-A-L-ID-----------'I~--------_ _ _ _ ___
tHzwE~
------------------..;..----__\1 HIGH IMPEDANCE
DATA 1/0 DATA UNDEFINED J).------------...-....;~----------
0021-10
2-148
CY7C168
5A~~u~==================================================================
. CY7C169
1.4
1.2
vs SUPPLY VOLTAGE
./
1.2
vs AMBIENT TEMPERATURE
~
!
120
vs OUTPUT VOLTAGE
til
1.0 100
~
leV I-
~ 1.0 ~ ffiIX:
U
.!t
Q 0.8 lL j
Q
0.8
IX:
:I
U
80
~
~
III III
N N 0.6 III
60
u
'" "
:::; 0.6 ~ IX: Vee =5.0 V
c( c( :I TA =25"C
~ ~
IX: 0.4 IX: 0.4 ~ 40
0 0 Vee -5.0 V I-
Z z VIN z 5.0 V :I
A.
0.2 0.2 I---ISB I- 20
~
ISB :I
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0

1.4 1.6 140
1.3
1.4 .......----~-----~

!
120 .JI'
./V"
c c I- 100
~ Z
~
Q
III
1.2
S 1.2 I------I-----..,.".I!:...--f
III
IX:
IX: 80
/ Vee - 5.0 V
TA =25'C
N
:::; 1.1
"'" ............
N
:::;
:I
U /
c(
~
IX: ~
TA =25C !o 1.0 I--------::....-::~-----f
~
z
Ui
60
7
0
z
1.0
0.9
r--- t--- z
0.8 "'""'ttC----~------4
I-
::I
A.
I-
::I
40
/
20
0.8 0.61.-----"-------..1
0
V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0

3.0 30.0 1.1.----....,.----r-----,
2.5 25.0
.,-- Vee = 5.0 V
TA = 25C
~
Q
2.0 ! 20.0
/ VIN = 0.5 V
III
N
:::;
c(
1.5 <c
c
15.0 1/
/
~ I-
IX:
1.0
...I
~ 10.0
/
i
0.5 1/ 5.0
.IV TA = 25C
vee =4.50 V
0.0
0.0 1.0 2.0
-V
SUPPLY VOLTAGE (V)
3.0 4.0 5.0
0.0 V
o 200 400 600
CAPACITANCE (pF)
BOO 1000
0021-11
2-149
CY7C168
fiA~~UaoR==============================================================~~
.
CY7C169
Speed Icc Ordering Code

Package Operating Speed Icc Ordering Code
Package Operating
(ns) rnA Type Range (ns) rnA Type Range
25 90 CY7C 168-25PC P5 Commercial 25 90 CY7C169-25PC P5 Commercial
CY7C168-25DC D6 CY7C169-25DC D6
CY7C168-25LC L5I CY7C169-25LC L5I
CY7C168-25VC V5 CY7C169-25VC V5
35 90 CY7C168-35PC P5 Commercial 35 90 CY7C169-35PC P5 Commercial
CY7C168-35DC D6 CY7C169-35DC D6
CY7C168-35LC L51 CY7C169-35LC L5I
CY7C168-35VC V5 CY7C169-35VC V5
CY7CI68-35LMB L5I CY7CI69-35LMB L5I
45 70 CY7C168-45PC P5 Commercial 40 70 CY7C169-40PC P5 Commercial
CY7C168-45DC D6 CY7CI69-40DC D6
CY7C168-45LC L5I CY7C I69-40LC L51
CY7C168-45VC V5 CY7C 169-40VC V5
CY7CI68-45LMB L5I CY7CI69-40LMB L5I
2-150
CY7C168
&Ii
-.. CY7C169
~ ~~~UaoR~==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB1[12] 1,2,3
ISB2[12] 1,2,3
Note:
12. 7C168 only.
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tRCS 7,8,9,10,11
tRCH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-151
CY7C168A
CY7C169A
CYPRESS
Features
Automatic power-down when Capable of withstanding greater Data on the four input/output pins
deselected (7CI68A) than 2001 V electrostatic (1/00 through 1/03) is written into the
discharge memory location specified on the ad-
power dress pins (Ao through All).
High speed The CY7C168A and CY7C169A are taking chip enable (CE) LOW, while
- 20 ns tAA
high performance CMOS static RAMs write enable (WE) remains HIGH. Un-
- 15 ns tACE (7CI69A)
organized as 4096 x 4 bits. Easy memo- der these conditions the contents of the
Low active power ry expansion is provided by an active memory location specified on the ad-
-385 mW LOW chip enable (CE) and three-state dress pins will appear on the four data
Low standby power (7CI68A) drivers. The CY7C168A has an auto- I/O pins.
-83mW matic power-down feature, reducing
The I/O pins stay in high impedance
the power consumption by 77% when state when chip enable (CE) is HIGH,
TTL compatible inputs and deselected.
outputs or write enable (WE) is LOW.
Writing to the device is accomplished
VIR of 2.2V A die coat is used to insure alpha im-
when the chip enable (CE) and write munity.

A4 Vee
A5 A3
A6 A2
A7 A1
As Ao
Ag 1/00
A10 1/01
A11 1/02
CE 1/03
1/00 GND WE
1/01 0162-2
1/0 2 10 ~ ~ tI')
><
1/03
As A2
A7 Al
CE AS AO
Ag 1/0
A10 1/1
WE A11 1/2
0162-1
I~ ~I~ ~
(!) ~
0162-3
Selection Guide
7C168A-20 7C168A-25 7C168A-35
7C169A-40 7C168A-45
7C169A-20 7C169A-25 7C169A-35
Maximum Operating
Current (rnA) 1 STn
l Commercial
1 Military
90 70
80
70
70
50
70
50
70
2-152
CY7C168A
5A~~NDUcrOR =====================================================================
Maximum Ratings
CY7C169A
(Pin 20 to Pin to) .................... -0.5V to +7.0V
Operating Range
Range Vee
in HighZ State ...................... -0.5Vto +7.0V Temperature
Military[2] - 55C to + 125C 5V 1O%

7C168A20 7C168A35 7C168A45
7C168A25
Parameters Description Test Conditions 7C169A20 7C169A25
7C169A35 7C169A40 Units
VOH Output HIGH Voltage Vee = Min.,loH = -4.0 rnA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 0.4 V
VIR Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee 2.2 Vee V
VIL Input LOW Voltagd 4A] -0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V
IIX Input Load Current GND::;; VI::;; Vee -10 +10 -10 +10 -10 +10 -10 +10 p,A
Output Leakage GND::;; Vo::;; Vee, -10 -10 -10 +10 -10
loz +10 +10 +10 p,A
loS Current[l] Vee = Max., VOUT = GND -350 -350 -350 -350 rnA
Vee Operating Vee = Max. Commercial 90 70 70 70

lee rnA
Automatic CE Max. Vee, Commercial 40 20 20 20
ISB} rnA
Power Down Current CE:2 VIR Military 20 20 20
Automatic CE Max. Vee, Commercial 20 20 20 20
ISB2 rnA
Power Down Current CE:2 Vee - 0.3V Military 20 20 20
Capacitance [4]
Notes:
1. Not more than} output should be shorted at one time. Duration of 3. See the last page of this specification for Group A subgroup testing
4A. VIL min. = - 3.0V for pulse durations less than 30 ns.

5V~------~~~~
R148H!
5V ~-----JW'__-.
R1481H 3.0 V - - - - - .. -----i
OUTPUT Q--------.. OUTPUT 0 - - -......- - -..
GND
30 pF R2 5 pF R2 .;; 5 ns -.;; 5 ns
I_
-
INCLUDING
JIG AND _
SCOPE -
255n
I-= INCLUDING
JIG AND
SCOPE -=
255U
0162-4
Figure 2
0162-6
Figure la Figure Ib
16712
OUTPUT O----"~
....~....- -...... o 1.73 V 0162-5
2-153
CY7C168A
fiji~~~u~================================================================== CY7C169A
Switching Characteristics Over Operating Range3, 5]

7C168A20 7C168A25 7C168A35
7C169A40 7C168A45
Parameters Description 7C169A20 7C169A25 7C169A35 Units
READ CYCLE
tOHA Output Hold from Address Change 5 5 5 5 5 ns
17C168A 20 25 35 40 45 ns
tACE CE LOW to Data Valid
17C169A 12 15 25 25 ns
tLZCE CE LOW to Low Z[7, 12] 5 5 5 5 5 ns
tHZCE CE HIGH to High Z[6, 7] 8 10 15 15 15 ns
tpu CE LOW to Power Up (7CI68A) 0 0 0 0 ns
tpD CE HIGH to Power Down (7CI68A) 20 20 20 20 25 ns
tRCS Read Command Setup 0 0 0 0 0 ns
tRCH Read Command Hold 0 0 0 0 0 ns
WRITE CYCLE[8]

tAW Address Setup to Write End 15 20 25 30 30 ns
tLZWE WE HIGH to Low Z[7] 7 7 10 15 15 ns
tHZWE WE LOW to High Z[6, 7] 5 5 5 5 5 ns
Notes:
loading ofthe specified lor/IOH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
6. tHzCE and tHZWE are tested with CL = 5 pF as in Figure 1h. Tran- data input setup and hold timing should be referenced to the rising
sition is measured 500 mV from steady state voltage. edge of the signal that terminates the write.
7. At any given temperature and voltage condition, tHz is less than tLz 9. WE is HIGH for read cycle.
for any given device. to. Device is continuously selected, CE = VIL.
12. 3 ns min. for the CY7CI69A.
Switching Waveforms
~t::~~--------------------------tRc--~----------------------~1.
ADDRE~_~~I_:~-_~~~~~~~~-~~H~A~~~~~tA~A~-_.-!------.-----.-,---~----------------------~------------------
DATA OUT
______
---------------------------------------- 0162-7
2-154
5n~NDUcroR =====================================================================
CY7C168A
. CY7C169A

~.-
IRC
-l- PI
I~CE
ILZ:! ~IHZ~ HIGH

HIGH IMPEDANCE 1/ / / / / II" IMPEDANCE
DATA OUT DATA VALID
~ \. \. \. "- /
I---Ipu f--IPO---j
(7C 16BA) Vcc ICC
SUPPLY
CURRENT
.f50% 50%
ISB
..,~ ~k-
..J
- I--IRCS i---IRCH ----
0162-8

~-----------------------------IWC----------------------------~
ADDRESS
~--------------------ISCE----------------------~
CE ~~--~~----~----~
~~~~------------------------------~~~~~~~~~~
~-----------------------IAW------------------------~---
I+-------ISA---------......! I+--------I~E-----......!
r------------------
1+----'-----ISo-----+l_
IHZWE~
DATA 1/0 ----------D-A-T-A-U-N-D-EF-IN-E-D-------- )~--....;.;.;.;,;~;;..;;.;;.;.;;.;.;.;;.----c\_______
0162-9

I+---------------------------IWC---------------------------~
ADDRESS
.-..1.------------ tSCE -----------1

--~------------~ 1,-----4-------------
I+---+---------------tso------'--
------------~,~------------------II~----------
tHZWE----!
-------------...;----~ HIGH IMPEDANCE
DATA 1/0 DATA UNDEFINED J~-----------.;;.......;..;;...-;.;..------
0162-10
2-155
CY7C168A
5Ji~NDUcrOR=====================================================================
. CY7C169A

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs OUTPUT VOLTAGE
1.4 1.2 120
1.2
/: ~ i
!
I~y
1.0
... 100
11 1.0 ~ ~ Z
w
2
U
fil 0.8
V U 0.8
!t
0
a:
a:
;:)
I.)
80
~
N
V w
N
:::;
0.6 w
I.) 60
'" '"
:i 0.6 a: Vee = 5.0 V
c(
~
<
:e
;:) TA = 25"C
0
IX: a: 0.4 en 40
0
Z
0.4 0
z
Vee =5.0V
VIN =5.0 V
...
0.2 0.2 r---ISB ...~ 20
~
ISB ;:)
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLT AGE (V)

VS. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.6 r-----.,......------, 140
~
1.3 i 120
1.4 t-----+-------I ! V
... /
" ~" 100
~
0
w
1.2
....
@
N
1.2 r-----+-----:::::ootC--t
a:i
IX:
IX:
;:)
80
/ Vee = 5.0 V
TA = 25'C
N
:::; 1.1 :::; I.) ;{
< ............ TA = 25C < ~
z 60
~ 1.0 r----~~"-------t
:IE
a: b-...... o ...iii /
-
1.0
0
z :----- z
...~
40
0.9 0.8 htC----+--------1 ;:)

0 20
/
0.8
4.0 4.5 5.0 5.5 6.0
0.6 L-._ _ _ _ ~ _ _ _ _ _....... V
-55 25 125 0.0 1.0 2.0 3.0 4.0

3.0 30.0 1.1 r-----,..------,..----.......
~ Vee ~ 5.0 V
2.5 25.0 TA = 25C
E 2.0 ! 20.0 / ~ 1.0t----~--~~---..I

VIN = 0.5 V
,/
0
W ~
N
:i 1.5 "" 15.0
;;.
N
:::;
c(
<
:e
~ ~
a:
i 1.0 ~ 10.0
/ a:
i
/ / TA = 25C
Vee =4.50V
-V
0.5 5.0 ./
0.0
0.0 1.0 2.0 3.0 4.0 5.0
0.0 V
o 200 400 600 800 1000 20 40
SUPPL Y VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz)
0162-11
2-156
CY7C168A
WA ~~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
CY7C169A
Speed Icc Ordering Code

Package Operating Speed Icc Ordering Code
Package Operating
(ns) rnA Type Range (ns) rnA Type Range
20 90 CY7CI68A-20PC P5 Commercial 20 90 CY7CI69A-20PC P5 Commercial
CY7CI68A-20DC D6 CY7CI69A-20DC D6
CY7CI68A-20VC V5 CY7CI69A-20VC VS
CY7CI68A-25LC L51 CY7C 169A-25LC LSI
CY7CI68A-25VC V5 CY7CI69A-25VC V5
CY7CI68A-25DMB D6 Military CY7CI69A-25DMB D6 Military
CY7CI68A-25LMB L51 CY7CI69A-25LMB LSI
CY7CI68A-35LC LSI CY7C169A-35LC L51
CY7CI68A-35VC V5 CY7C169A-35VC V5
CY7CI68A-35DMB D6 Military CY7C169A-35DMB D6 Military
CY7CI68A-35LMB LSI CY7C169A-35LMB LSI
45 70 CY7CI68A-45PC P5 Commercial 40 70 CY7C169A-40PC PS Commercial
CY7CI68A-45DC D6 CY7C169A-40DC D6
CY7CI68A-45LC L51 CY7C169A-40LC LSI
CY7CI68A-45VC V5 CY7C169A-40VC V5
CY7CI68A-45DMB D6 Military CY7C169A-40DMB D6 Military
CY7CI68A-45LMB L51 CY7C169A-40LMB LSI
2-157
CY7C168A
fWi CYPRESS CY7C169A
s~COWUcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
ICC 1,2,3
ISB1[12] 1,2,3
ISB2[12] 1,2,3
Note:
12. 7C168A only.
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tRCS 7,8,9,10,11
tRCH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-158
CY7C170
CYPRESS
Features
CMOS for optimum
speed/power
High speed
- 25 ns tAA
- 15 ns tACS
CMOS static RAM organized as 4096
words x 4 bits. Easy memory expansion
is provided by an active LOW chip se-
lect (CS), an active LOW output enable
(OE), and three-state drivers.
taking chip select (CS) and output en-
able (OE) LOW, while write enable
(WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins

Low active power will appear on the four data 110 pins.
- 495 mW (commercial) Writing to the device is accomplished
- 660 mW (military) when the chip select (CS) and write en- The 110 pins stay in high impedance
able (WE) inputs are both LOW. Data state when chip select (CS) or output
on the four input/output pins enable (OE) is HIGH, or write enable
outputs
(1/00 through 1103) is written into the (WE) is LOW.
Capable of withstanding memory location specified on the ad-
greater than 2001 V A die coat is used to insure alpha im-
dress pins (Ao through All). munity.
Output enable

DIP
1/0
1/1 0037-2
SOJ
1/2
Vee
A3
1/3 A2
CS Ao
NC
NC
WE 17 1/00
OE
0037-1 1/1
1/2
1/3
WE
0037-12
Figure 1
:election Guide
7C17025 7C17035 7C17045
Maximum Operating
Current (rnA)
I Commercial 90 90 90
I Military 120 120
2-159
~ CY7C170~
~~~UcrOR =====================================================================
Maximum Ratings
(Pin 22 to Pin 11) .................... -O.SV to +7.0V
Operating Range
Ambient
Temperature
in High Z State ...................... - O.SV to + 7.0V
Commercial OC to +70C SV 1O%
DC Input Voltage ................... - 3.0V to + 7.0V Military [4] - SsoC to + 12SoC SV 1O%

7CI70
Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 V
VIR Input HIGH Voltage 2.0 Vee V
IIX Input Load Current GNDs VI s Vee -10 +10 /-LA
Output Leakage GNDs Vo s Vee -SO
IOZ +SO /-LA
Output Short[l]
los Circuit Current Vee = Max., VOUT = GND -3S0 mA
Icc
Vee Operating
Supply Current
Vee = Max.
lOUT = OmA
I Commercial 90
mA
I Military 120
*-25, -35 and -45 only
Capacitance [2]
pF
Output Capacitance Vee = S.OV 7
CoUT
Notes:

ALL INPUT PULSES
5V
OUTPUT
o----~~_ ..
0---..----....
R1481Sl R1481H
5 V D-----VVIr--.
OUTPUT 0 - - -.....- - -...
3.0 V -----,.-----i
30 pF R2 5 pF R2 GND
I INCLUDING
_JIGAND _
- SCOPE -
25511
I-=- INCLUDING
JIG AND
SCOPE -=-
25512 .; 5 ns
Figure 2
0037-6
0037-4
Figure Ia Figure Ib
Equivalent to:
THEVENIN EQUIVALENT
16712
OUTPUT O---"\.~...
~~ ..--"""O 1.73 V
0037-5
2-160
S)l CY7C170
~ ~~~UcrOR ~====================================================================~
7C170-25 7C170-35 7C170-45
READ CYCLE
tACS CS Low to Data Valid 15 25 30 ns
tLZCS CS LOW to Low Z[7] 3 5 5 ns
tHZCS CE HIGH to High Z[6, 7] 15 20 25 ns
WRITE CYCLErS]
tscs CS LOW to Write End 25 35 35 ns
tHzwE WE LOW to High Z 10 15 20 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing 8. !he internal write time of the memory is defined by the overlap of
reference levels of l.5V, input pulse levels of 0 to 3.0V and output CS LOW and WE LOW. Both signals must be LOW to initiate a
loading of the specified Ior/IOH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
6. tHZOE. tHzcS and tHzWE are tested with CL = 5 pF as in Figure 1h. data input setup and hold timing should be referenced to the rising
7. At any given temperature and voltage condition, tHZCS is less than 9. WE is HIGH for read cycle.
tLzCS for all devices. These parameters are sampled and not 100% to. Device is continuously selected, CS = VIL and OE = VIL.
tested. 11. Address valid prior to or coincident with CS transition LOW.
12. Data I/O will be high impedance ifOE = VIH.
Switching Waveforms
_----.-1*_
ADDRESS ____.c\4---_-_ -_tR_C-

_ -
DATA OUT
~~--~----~HA------~
0037-11
2-161
~ CY7C170
~~~NDUcroR=====================================================================
tRC
).- -t-
J
lACS
~I\
/4--tLZOEi
tOOE L ~,o.~
__ IHZCS_
HIGH
IMPEDANCE
HIGH IMPEDANCE 1/ / / / L IF DATA VALID
DATA OUT
ILlCS 1" \ \ \ \ I\. /
0037-7
~-----------------------------twc--------------------------~
1------------------ Iscs ------------------~
~--------------------tAW-----------------------.~---
~--------tSA-----+I ~-----t~E-----~
1+--'------t50----------+l-
DATA IN DATA-IN VA"LID
tHZWE~
DATA 110 ----------D-AT-A-U-N-D-E-FI-N-ED-------- ) .....- - - - - - - - - " " " " " -_ _ _ _ __
0037-8
Write Cycle No.2 (CS Controlled) (Notes 8, 12)
~--------------------------twc-----------------------~
ADDRESS
------t-----------ISCS-------~
1+------t~E-------~
WE
~~----------~O----~.-
tHZWE----j
DATA I/O
------------------_\!/)0----------------------
DATA UNDEFINED
HIGH IMPEDANCE
0037-9
2-162
~ CY7C170
~~~aIDUcrOR==================================================================
Ordering Code
(ns) Type Range
CY7C170-25DC DIO
CY7C170-25VC V13
CY7C170-35DC DIO
CY7C170-35VC V13
CY7C170-35DMB DIO Military
CY7C170-45DC DIO
CY7C170-45VC V13
2-163
~ CY7C170
~~~~UcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL Max. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACS 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tscs 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #: 38-00035-E
2-164
CY7C170A
CYPRESS
Features
CMOS for optimum
speed/power
The CY7C170A is a high performance
CMOS static RAM organized as 4096
taking chip select (CS) and output en-
fI
High speed words x 4 bits. Easy memory expansion able (OE) LOW, while write enable
- 20 ns tAA is provided by an active LOW chip se- (WE) remains HIGH. Under these
- 15 ns tACS lect (CS), an active LOW output enable conditions the contents of the memory
(OE), and three-state drivers. location specified on the address pins
Low active power will appear on the four data I/O pins.
- 495 mW (commercial) Writing to the device is accomplished
- 660 mW (military) when the chip select (CS) and write en- The I/O pins stay in high impedance
able (WE) inputs are both LOW. Data state when chip select (CS) or output
on the four input/output pins enable (OE) is HIGH, or write enable
outputs
(1/00 through 1/03) is written into the (WE) is LOW.
Capable of withstanding memory location specified on the ad-
greater than 2001V A die coat is used to insure alpha im-
dress pins (Ab through Al1). munity.
Output enable
VIR of 2.2V

DIP
1/0
0149-2
1/1
SOJ
1/2
1/3
CS
WE
DE
0149-1
Figure 1
Selection Guide
7C170A-20 7C170A-25 7C170A35 7C170A45
Maximum Operating
Current (rnA)
I Commercial 90 90 90 90
I Military 120 120 120
2-165
~ CY7C170A
~J'~UcrOR==================================================================
Maximum Ratings
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... > 2001V
(Pin 22 to Pin 11) .................... -0.5V to + 7.0V
Operating Range
Range Vee
in High Z State ...................... -0.5V to +7.0V Temperature
DC Input Voltage ................... -3.0V to +7.0V Commercial OCto + 70C 5V 1O%
Electrical Characteristics Over Operating Rangel 3]

7C170A
Min. Max.
IIX Input Load Current GND::;; VI::;; Vee -10 +10 J.LA
Output Leakage GND::;; Vo::;; Vee -10
IOZ +10 J.LA
Output Short[l]
los Vee = Max., VOUT = GND -350 rnA
Circuit Current
lee
Vee Operating
Supply Current
Vee = Max.
lOUT = OmA
I Commercial 90
rnA
I Military * 120
25, -35 and -45 only
Capacitance [2]
CIN Input Capacitance TA = 25C, f = I MHz 4
pF
COUT
Notes:

ALL INPUT PULSES
R1 481Sl R1481H
5Vcr------~~~~ 5 V O------Jw'\r-....., 3.0 V - - - - - ...----~
OUTPUT 0---..-----.... OUTPUT 0---_---.. .
30 pF R2 5 pF R2 GND ---~
I INCLUDING
_ JIG AND _
- SCOPE -
255H
I INCLUDING
JIG AND
-=SCOPE -=
255H .;; 5 n$
Figure 2
0149-6
0149-4
Figure la Figure Ib
Equivalent to:
THEVENIN EQUIVALENT
16m
OUTPUT OI---~V"V.tw-.---O 1.73V
0149-5
2-166
~PRRSS
..nEMlCONDUcrOR ;;;=:;;;=:;;;=:;;;=:;;;=:;;;=:;;;=:;;;=:;;;=:;;;=:================================================
CY7C170A

7C170A20 7C170A25 7C170A35 7C170A45
READ CYCLE
tOHA Data Hold from Address Change 5 5 5 5 ns

tACS CS Low to Data Valid 15 15 25 30 ns
tLZOE OE LOW to Low Z 3 3 3 3 ns
tHzOE OE HIGH to High Z[6] 8 10 12 15 ns
tHZCS CE HIGH to High Z[6, 7] 8 10 15 15 ns
WRITE CYCLErS]

tHzwE WE LOW to High Z 7 7 10 15 ns
tLZWE WE HIGH to Low Z 5 5 5 5 ns

Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CS LOW and WE LOW. Both signals must be LOW to initiate a
loading of the specified lor/IOH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
6. tHZOE, tHZCS and tHzwE are tested with CL = 5 pF as in Figure lb. data input setup and hold timing should be referenced to the rising
tLZCS for all devices. These parameters are sampled and not 100% 10. Device is continuously selected, CS = VIL and OE = VIL.
tested. 11. Address valid prior to or coincident with CS transition LOW.
12. Data 110 will be high impedance ifOE = VIR.
Switching Waveforms
0149-7
2-167
~ CY7C170A
~~~UcrOR==================================================================
IRC
~r- -,l
~ 1
lACS
~\
~Ilzoel
loDe L ."'''~
f4-IHZCS-
HIGH
IMPEDANCE
HIGH IMPEDANCE 1/ / / / / I DATA VALID
DATA OUT
I"\'\'\'\' f
IllCS
0149-8
~-----------------------------IWC--------------------------~~
1+----------------- Iscs-----------------~
I+----------------IAW-----------------.~---
I+-----------ISA----------+I I+--------t~e------~
I+-----'--------tso --------+1-
DATA IN DATA-IN VA-LID
tHzwe~
DATA 110 ----------D-A-TA-U-N-D-E-F-IN-E-D------- ) , . - - - - - - - - - - . \.._ _ _ _ _ __
0149-9
Write Cycle No.2 (CS Controlled) (Notes 8, 12)
~----------------------~c-----------------------~
-----t----------ISCS--------~
I+--~------I~e------------~
14--+-------------ISO-----.......-
DATA-IN VALID
IHzwe-----l
DATA 110
------------------___\1
DATA UNDEFINED
HIGH IMPEDANCE
, ..- - - - - - - - - - - - - - - - - - - - - -
0149-10
2-168
~ CY7C170A
~~~NDUcrOR =====================================================================
Ordering Code
(ns) Type Range
20 CY7CI70A-20PC P9 Commercial
CY7CI70A-20DC DIO
CY7CI70A-20VC V13
25 CY7C 170A-25PC P9 Commercial
CY7C 170A-25DC DIO
CY7CI70A-25VC Vl3
CY7CI70A-25DMB DIO Military
35 CY7CI70A-35PC P9 Commercial
CY7CI70A-35DC DIO
CY7CI70A-35VC Vl3
45 CY7C 170A-45PC P9 Commercial
CY7CI70A-45DC DIO
CY7CI70A-45VC Vl3
2-169
~ CY7C170A
~~~~UcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACS 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tscs 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-170
CY7C171
CY7C172
CYPRESS
Separate I/O
Features
Automatic power-down when Capable of withstanding greater Data on the four input pins (10 through
deselected than 2001 V electrostatic 13) is written into the memory location
discharge specified on the address pins (AD
power through All).
High speed The CY7C171 and CY7Cl72 are high taking chip enable (CE) LOW, while
- 25 ns tAA
performance CMOS static RAMs orga- write enable (WE) remains HIGH. Un-
Transparent Write (7CI71) nized as 4096 x 4 bits with separate der these conditions the contents of the
Low active power I/O. Easy memory expansion is pro- memory location specified on the ad-
-385 mW vided by an active LOW chip enable dress pins will appear on the four data
(CE) and three-state drivers. They have output pins.
Low standby power an automatic power-down feature, re-
-83mW The output pins stay in high impedance
ducing the power consumption by 77%
TTL compatible inputs and when deselected. (7Cl72 only), or chip enable (CE) is
outputs Writing to the device is accomplished HIGH. A die coat is used to insure al-
when the chip enable (CE) and write pha immunity.

r-------------------------<~-----'O A4 Vcc
A3
A2
A7 Al
'-------f--< 1------ '2 As Ao
Ag '0
A10 '1
A11 0
I-----If---I ~----- 0 0 '3 1
'2 2
I-----If-+-I ~--- 0 1 cr 3
GND WE
I-----If-+-I ~--- O2
0051-2
I-----If-+-I ~--- 0 3
4 3
As 5 Al
Ag 6 Ao
NC 7 23 '0NC
""'---~-.___WE
.-
~""""'"--'----"'.
NC
A 10
A11
S
9
10
22
21
20
NC
'1
'3 1 \ 2131415 16171 ~9 00
_Nltl ~ I~ 0' 0' 0

0051-1
(!) 0051-3
.Selection Guide
7C171-25 7C171-35 7C171-45
7Cl72-25 7Cl72-35 7Cl72-45
Maximum Operating
Current (rnA)
STD I Commercial 90 90 70
I I Military 90 70
2-171
CY7C171
5A .
Maximum Ratings
~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CY7C172
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... > 2001V
(Pin 24 to Pin 12) .................... -0.5V to +7.0V
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OCto +70C 5V 10%

7C17125 7C171-35 7C17145
Parameters Description Test Conditions 7Cl7225 7Cl72-35 7Cl7245 Units
VIH Input HIGH Voltage 2.2 2.2 2.2 V
IIX Input Load Current GND:::;; VI:::;; Vee -10 + 10 -10 +10 -10 +10 }.LA
GND:::;; Vo:::;; Vee,

loz Output Leakage Current -50 +50 -50 +50 -50 +50 }.LA
Output Disabled
los Current [1] Vee = Max., VOUT = GND -350 -350 -350 rnA

Icc rnA
ISB} rnA
Power Down Current CE;;:: VIH Military 40 20 20
ISB2 rnA
Power Down Current CE;;:: Vee -0.3V Military 20 20 20
Capacitance [4]
Notes:
1. Not more than} output should be shorted at one time. Duration of 3. See the last page of this specification for Group A subgroup testing
2. T A is the "instant on" case temperature. 4. Tested initially and after any design or process changes that may

R1481H
5 v o------"'Mw---, 5 V o-----J'W~....,
R1481H 3.0 V -----j-----o1.
OUTPUT 0 - - -......- - -.... OUTPUT 0 - - -.....- - -.....
GND
30 pF R2 5 pF R2 .; 5 ns -.; 5 ns
I INCLUDING
_JIG AND
- SCOPE
_
-
255H
I INCLUDING
JIG AND
-=-SCOPE ":'
255H
0051-4
Figure 2
0051-6
Figure la Figure lb
167H
OUTPUT O--~V-...,V-Ir.--~O 1.73 V 0051-5
2-172
CY7C171
~RRSS
..~ICONDUcroR
CY7C172
;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;:::;;;;;:::
Switching Characteristics Over Operating Rangel3, 5]

7C17125 7C17135 7C17145
II
Parameters Description 7Cl7225 7Cl7235 7Cl7245 Units
READ CYCLE
tRCS Read Command Set-up 0 0 0 ns
tRCH Read Command Hold 0 0 0 ns
WRITE CYCLErS]
tLzwE WE HIGH to Low Z[7] (7CI72) 0 0 0 ns
tHzwE WE LOW to High Z[6, 7] (7CI72) 10 15 20 ns
tADv Data Valid to Output Valid (7CI71) 25 30 35 ns
Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CE LOW and WE LOW. Both signals must be low to initiate a write
loading of the specified IoLiIoH and 30 pF load capacitance. and either signal can terminate a write by going high. The data input
6. tHzCE and tHZWE are tested with CL = 5 pF as in Figure lb. Tran- setup and hold timing should be referenced to the rising edge of the
sition is measured 500 mV from steady state voltage. signal that terminates the write.
Switching Waveforms
0051-7
2-173
CY7C171
5n .-
~NDUcrOR =======================================================================
CY7C172

tAC -_ .. -
~~ .J
-l-
-----IACE
tLZ:-1 ~tHZ~ HIGH

IMPEDANCE
HIGH IMPEDANCE 1/I / I I 'i'
DATA OUT DATA VALID
\.\.\.\.\.1\ /
i----tpu- I---tPO--j
ICC
VCC
SUPPLY }'f.- 50% 50%
CURRENT IS8
--l- ~~
...I
- :+-tRCS -tRCH-
0051-8

twc
ADDRESS ~ -:I
I
tSCE ,
\\ ,\\~ ,/11111111111/
tAW -tHA-
I
tSA _ t pWE -
'I
WE -\:\ \ ~ ..,f-
t so - t:i tHO
*
DATA IN -:If- DATA-IN VALID
DATA OUT
l - tHZWE.:-! -tLZWE-1
HIGH IMPEDANCE
DATA UNDEFINED
(7C172) "'-
~tAOV-
DATA OUT
(7C171) _ _ _ _ _ _ _D_A_TA_U_ND_E_Fl_N_ED_ _ _ _~X~
~I. ____D_A_TA_VA_L_ID_ _ _ __
0051-9

twc ,
ADDRESS -:I
tSA " tsCE -

~ ..,f-
, tAW , - tHA -
- tpWE -
\\ ,\ \ \ \ \ \ \ \ \ \ \ \\ \ \ \-l ~I I I I I I / / / / / / /
I::- t s o -!::::i tHO
J(
*
' - tHzwE-1
DATA OUT '\I HIGH IMPEDANCE
DATA UNDEFINED
(7C172)
DATAOUT---------D-AT-A-U-N-D-EF-IN-E-D------------~~I---DA-T-A-V-AL-ID-------
- tAwE -
(7C171) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _______ -...J)K~
0051-10
Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7Cl72)_
2-174
CY7C171
~RESS
WflEMICONDUcrOR ====================================================================
CY7C172

1.4
1.2
vs. SUPPLY VOLTAGE
I~;/
./
1.2
1.0
~
!
120
100
vs OUTPUT VOLTAGE
II
~
I-
~ 1.0 '"en ~
U
.!:!
0 0.8
V ~
5lN
0.8 a::
a::
::l
u
80
~
w
N
::::; V 0.6 w
u 60
'" '"
0.6 ::::; a:: Vee = 5.0 V
::l TA = 25'C
~ ~ 0
a:: a:: 0.4 til 40
0 0.4 0 Vee =5.0 V I-
z z VIN = 5.0V
~
0.2 0.2 I- 20
'"
ISB ::l
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ('C) OUTPUT VOLTAGE (V)

1.4 1.6 140
120
.,..
1.3
1.4 ! V
<! <! I- 100
/
~
:!
0
w
1.2
..... 5lN
j
1.2 a::
a:: 80
/ Vee = 5.0 V
TA = 25'C
N
::::;

1.1
............ TA = 25'C
::::;

::l
U
lO: 60
V
z
~
~
~
a:: a:: 1.0
en /
---- -
0 1.0 0
z z I-
::l
40
0.9 0.8
0
~
I-
::l 20
/
0.8 0.6 ~
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0

3.0 30.0 1.1...---....,.---..,..----,
~ Vee = 5.0 V
2.5 25.0 TA = 26'C
~
0
2.0 ] 20.0
/ VIN = 0.6 V
w
N
::::;
1.5
j

15.0 /
/
I-
~
a::
1.0
-J
W
o 10.0
/
~ TA = 25'C
/ .IV Vee =4.50 V
-V
0.5 5.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0
0.0
V 200 400 600 800 1000 20
0051-11
2175
CY7C171
(;A~~UcrOR==================================================================
. CY7C172
(ns) Ordering Code Ordering Code
Type Range (ns) Type Range
25 CY7C171-25PC P13 Commercial 25 CY7Cl72-25PC P13 Commercial
CY7C171-25DC D14 CY7Cl72-25DC D14
CY7C171-25LC L64 CY7Cl72-25LC L64
CY7C171-25VC V13 CY7Cl72-25VC V13
CY7C171-35DC D14 CY7Cl72-35DC D14
CY7C171-35LC L64 CY7Cl72-35LC L64
CY7C171-35VC Vl3 CY7Cl72-35VC V13
CY7CI71-35DMB D14 Military CY7Cl72-35DMB D14 Military
CY7C171-35LMB L64 CY7Cl72-35LMB L64
CY7C171-45DC D14 CY7Cl72-45DC D14
CY7C171-45LC L64 CY7Cl72-45LC L64
CY7C171-45VC V13 CY7Cl72-45VC V13
CY7C171-45DMB D14 Military CY7Cl72-45DMB D14 Military
2-176
CY7C171
5n "
.
~NDUcrOR
CY7C172
================================================================
DC Characteristics
Parameters
VOH
VOL
VIH
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
Ioz 1,2,3
ICC 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tRCS 7,8,9,10,11
tRCH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
tAWE[12] 7,8,9,10,11
tADV[12] 7,8,9,10,11
Note:
12. 7C171 only.
2-177
CY7C171A
CY7C172A
CYPRESS
Separate I/O
Features
Automatic powerdown when Capable of withstanding greater Data on the four input pins (10 through
deselected than 2001 V electrostatic 13) is written into the memory location
discharge specified on the address pins (Ao
power through All).
High speed The CY7CI71A and CY7CI72A are taking chip enable (CE) LOW, while
- 20 ns tAA high performance CMOS static RAMs write enable (WE) remains HIGH. Un-
Transparent Write (7CI71A) organized as 4096 x 4 bits with separate der these conditions the contents of the
Low active power I/O. Easy memory expansion is pro- memory location specified on the ad-
- 375 mW vided by an active LOW chip enable dress pins will appear on the four data
(CE) and three-state drivers. They have output pins.
Low standby power an automatic power-down feature, re-
-93mW The output pins stay in high impedance
ducing the power consumption by 77% state when write enable (WE) is LOW
TTL compatible inputs and when deselected. (7CI72A only), or chip enable (CE) is
outputs Writing to the device is accomplished HIGH. A die coat is used to insure al-
when the chip enable (CE) and write pha immunity.

10
A4 VCC
A3
As A2
AI
12
Ao
A9 10
13
00
00 01
O2
a, 03
GND WE
O2
0148-2
03 u
<.<tn<tt("~4.~~
4 3
CE As 5 A,
A9 S Ao
NC 7 10
NC 8 NC
A,o 9 NC
A'1 10 I,
13 00
-"'Itl ~I~ 0"'6'0 0148-3

0148-1
Selection Guide
7C171A20 7C171A25 7C171A35 7C171A45
7Cl72A20 7Cl72A25 7Cl72A-35 7Cl72A-45
Maximum Operating
Current (rnA)
2-178
CY7C171A
fin~NDUcrOR =====================================================================
.
Maximum Ratings
CY7C172A
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... > 2OO1V
fJI
(Pin 24 to Pin 12) .................... - 0.5V to + 7.0V
Range Vee

7C171A20 7C171A25 7C171A35 7Cl71A45
Parameters Description Test Conditions 7Cl72A20 7Cl72A25 7Cl72A35 7Cl72A45 Units
VOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 2.2 2.2 V
Input LOW Voltage - 3.0 0.8 - 3.0 0.8 - 3.0 0.8 - 3.0 0.8 V
Input Load Current GND S VI S Vee -10 + 10 -10 + 10 -10 + 10 -10 + 10 p,A
Output Leakage GND S Vo S Vee,
loz Current Output Disabled
-10 + 10 -10 + 10 -10 + 10 - 10 + 10 p,A
lOS Output Short Circuit Vee = Max., VOUT = GND -350 -350 -350 -350 rnA
Current [1]
Vee Operating Vee = Max. ~C_o_m_m
__er_c_ia_I~__+-_80__~__+-_70__~__~7_0~~__~5_0~ rnA
lee Supply Current lOUT = OmA Military 80 70 70
Automatic CE Max. Vee, CE ~ VIH ~C_o_m_m
__er_c_ia_I~__+-_40__~__+-_20__~__~2_0~~__~2_0~ rnA
Power Down Current Min. Duty Cycle = 100% Military 20 20 20
Max. Vee, Commercial 20 20 20 20
Automatic CE CE ~ Vee -0.3V ~-------+---+----~--+---~---+----~--~--- rnA
Power Down Current VIN ~ Vee -0.3V or
VIN S 0.3V Military 20 20 20
Capacitance [4]
Notes:

Rl481H R1481H
5 V ~--------.JW~...... 3.0 V - - - - - ..- - - -....
5V~------~~~~
OUTPUT n---_----.. OUTPUT 0---_---1

GND ---~
30 pF R2 5 pF R2
.;; 5 ns -.;; 5 ns
I
_
-
INCLUDING
JIGAND _
SCOPE -
255H
I ,NCLUD,NG
_JIG AND
- SCOPE
_
-
25512
0148-4 Figure 2
0148-6
Figure la Figure Ib
16712
OUTPUT O----~\JI'\J;\to-.- - - 0 1.73 V 0148-5
2-179
rm ~~~UcrOR=====================================================================
CY7C171A
CY7C172A
7C171A-20 7Cl71A-25 7C171A-35 7C171A-45

Parameters Description 7Cl72A-20 7Cl72A-25 7Cl72A-35 7Cl72A-45 Units
READ CYCLE
tHZCE CE HIGH to High Z[6, 7] 8 10 15 15 ns
tpD CE HIGH to Power Down 20 20 20 25 ns
tRCS Read Command Set-up 0 0 0 0 ns
tRCH Read Command Hold 0 0 0 0 ns
WRITE CYCLE[S]
tpwE WE Pulse Width 15 15 20 20 ns
tLZWE WE HIGH to Low Z[7] (7Cl72) 5 5 5 5 ns
tHZWE WE LOW to High Z[6, 7] (7CI72) 7 7 10 15 ns
tAWE WE LOW to Data Valid (7CI71) 20 25 30 35 ns
tADV Data Valid to Output Valid (7C171) 20 25 30 35 ns
Notes:
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output CE LOW and WE LOW. Both signals must be low to initiate a write
loading of the specified lor/IOH and 30 pF load capacitance. and either signal can terminate a write by going high. The data input
6. tHZCE and tHZWE are tested with CL = 5 pF as in Figure 1b. Tran- setup and hold timing should be referenced to the rising edge of the
sition is measured 500 mV from steady state voltage. signal that terminates the write.
Switching Waveforms
~~~--------------------------tAc--------------------------~1~M
~~I_;~':-~ ':-~ _-~_-_~ H~A~ ~ ~tA~A~-_.-'- - - - - -'-___________________________

ADDR'$ _______
DATA OUT PREVIOUS DATA VALID

, ~------------------
DATA VALID
---------------------------------------- 0148-7
2-180
CY7C171A
~RESS
'nEMICONDUcrOR ====================================================================
CY7C172A

tRC
~.\. J'f-
lACE
DATA OUT
t
HIGH IMPEDANCE
ll
::! 1/ / / / / If
DATA VALID
~tHZ~ HIGH
IMPEDANCE
\. \. \. \. \. /
f---tpu- I----- tPD---j
ICC
VCC
SUPPLY }'- 50"!. 50''"-1--- ISB
CURRENT
-,~ ~~
.J
- -tRCS f-o---- tRCH - -
0148-8

twc .
ADDRESS
tSCE .
\\ ,\\~ j i l l IIIIIIIII
tAW tHA-
tSA ~tpWE-
I
~\\:.,(-
t so - =I tHO
DATA IN DATA-IN VALID l(
DATA OUT
I - tHZWE-=! - tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
(7C172A) 11 I\.
~L......____D...A_TA_VA_L_ID_
-tADV-
DATA OUT
(7C171A) _ _ _ _ _ _ _D_A_TA_UN_D_E_FI_NE_D_ _ _ _ --...X _ _ __
0148-9

twc
ADDRESS j U
tSA tscE-
. tAW
~
~tpWE-
f"
-tHA-
\\ ,\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ . ~I I I I I I I I I / I II
I::!--tSD .1 tHO
DATA IN l( DATA-IN VALID l(
~ tHZWE.:j
DATA OUT HIGH IMPEDANCE
DATA UNDEFINED
(7C172A)
DATAOUT-------D-AT-A-U-N-D-EF-IN-E-D--------~~I~-DA-T-A-V-AL-ID------
- tAWE -
(7C171A) )1(......_________
0148-10
Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7Cl72A).
2-181
CY7C171A
fiA~~u~==================================================================
. CY7C172A

vs.SUPPLYVOLTAGE vs. AMBIENT TEMPERATURE vs OUTPUT VOLTAGE
1.4 1.2 120
1.2
./ ~
E
I~y
1.0 100
~
III I-
J! 1.0
en Z
w
0
J:
0 0.8 V U 0.8
.!:l
Q
a:
a:
:::
(.J
80
~
UI
N
:J 0.6
<
./ w
N
:::i
ct
0.6 w
(.J
a:
:::
60
~ Vee =5.0 V
TA = 25'C
~ :IE 0.4 0
It a: en 40
""
0 0.4 0 Vee =5.0 V I-
Z z VIN = 5.0 V :::
~
0.2 I- 20
~
0.2 ISB :::
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPL Y VOLTAGE (V) AMBIENT TEMPERATURE ('C) OUTPUT VOLTAGE (V)

1.4 1.6 140
1.3 120
V
./
1.4 E
<t I- 100
/
<t z
0
w
3 1.2 3
Q
w
1.2
w
a:
a:
::: 80
/ vee = 5.0 V
TA = 25'C
N
:J 1.1
~
............
N
:::i
c(
(.J
:.::
V
c(
TA = 25'C z 60
~
:IE
:IE
ct
0
Z
1.0
r----- r---
a:
0
Z
1.0
in
I-
::: 40 /
0.9 0.8
~
I-
::: 20
7
V
0
0.8 0.6
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0

3.0 30.0 1.1
2.5 25.0
,,- Vee = 5.0 V
TA = 25'C
j 2.0 ! 20.0
/ ] 1.0
VIN 0.5 V
/
Q
w <t faN
N
:J 1.5 <<t
15.0 :::i
ct
:IE
a: ~ /11' ct
:IE
a:
1.0 ~ 10.0 0
i V z
0.5
/ 5.0 ~
TA = 25'C
Vee = 4.50 V
0.0
0.0 1.0 2.0 ---V 3.0 4.0 5.0
0.0 V
o 200 400 600 BOO 1000 20 40
0148-11
2-182
CY7C171A
&n .
~~ucr~~================================================================
CY7C172A

20 CY7CI71A-20PC P13 Commercial 20 CY7CI72A-20PC P13 Commercial
CY7C171A-200C 014 CY7CI72A-200C 014
CY7CI71A-20LC L64 CY7CI72A-20LC L64
CY7C171A-250C 014 CY7CI72A-250C 014
CY7C171A-250MB 014 Military CY7CI72A-250MB 014 Military
CY7CI71A-25LMB L64 CY7CI72A-25LMB L64
CY7C171A-350C 014 CY7CI72A-350C 014
CY7CI7IA-35LC L64 CY7CI72A-35LC L64
CY7C171A-450C 014 CY7CI72A-450C 014
2-183
CY7C171A
~~ CY7C172A ~
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tRCS 7,8,9,10,11
tRCH 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
tAWE[12] 7,8,9,10,11
tAOv[12] 7,8,9,10,11
Note:
12. 7C171A only.
2-184
CY7C183
PRELIMINARY CY7C184
CYPRESS
SEMICONDUCTOR 2 X 4096 X 16 Cache RAM
Features
Pin programmable into direct They are designed specifically for use enables cache bank A, and WEB en-
mapped or twoway set with the Intel 82385 Cache Controller, ables cache bank B to receive whatever
associative format and their addresses are latched on the data resides on the data bus. OEA and
CMOS for optimum speed/ falling edge ofthe Address Latch En- OEB similarly enable cache banks A
power able (ALE) signal. When ALE is and B, respectively, to drive the data
HIGH, the latch is transparent. The bus.
High speed-2S ns CY7C183 has all address bits latched Writing is accomplished, in the direct
Common I/O by the ALE signal except A12, which is mode, by tying WEA and WEB togeth-
unlatched. A12, which bypasses the er externally, and using Al2 to deter-
Internal address latch latch, has a faster access time. All ad- mine which 4K x 16 memory bank is
TTL compatible inputs and dress bits are latched by the ALE sig- selected.
outputs nal in the CY7C184. The mode pin
controls whether they are configured as Reading is accomplished, in the two-
Capable of withstanding greater way mode, by taking CE LOW, insert-
direct mapped 8K x 16 or two-way set
than 2001V electrostatic ing the respective OEx and CSx sig-
associative 2 x 4K x 16 RAMs. When
discharge nals LOW, and the respective WEx
mode is HIGH, the circuits are placed
Compatible with Intel 82385 in the two-way mode. In the two-way signal HIGH. The contents of the
Cache Controller mode, the upper address bit, Al2 is a memory location specified on the ad-
"don't care", and is externally wired to dress pins will appear on the 16 out-
Functional Description ground. When mode is LOW, the cir- puts. Activation ofOEA and OEB
The CY7C183 and CY7C184 are high cuits are placed in the direct mode. simultaneously will cause both banks
performance monolithic CMOS static to be deselected. Reading is accom-
Writing is accomplished, in the two-
RAMs which contain 128K bits orga plished, in the direct mode, by tying
way mode, by taking CE LOW and by
nized into either two, two-way set asso- inserting the respective CSx and WEx OEA and OEB together externally. Al2
ciative blocks of 4K x 16 RAM, or one will determine which 4K x 16 memory
signals LOW. CSo enables bits Do-D7 bank is enabled.
directly mapped 8K x 16-bit RAM. while CSI enables bits Dg-DI5. WEA
Logic Block Diagrams

TwoWay Set Associative (Mode = HIGH) Direct Map (Mode = LOW)
OEA------I
WEA-----I
ALE
OEs1------I
WEs------1
Way B
0145-2
0145-1
Selection Guide
7C18325 7C18335 7C18345
7C18425 7C18435 7C18445
Maximum Address Commercial 25 35 45
Access Time (ns) Military 35 45
Maximum Output Enable Commercial 10 14 16
Access Time (ns) Military 14 16
2-185
CY7C183
(;n~~NDU~R =====================================================================
PRELIMINARY CY7C184
Maximum Ratings
Supply Voltage to Ground Potential .... - O. 5V to + 7.0V
Operating Range
inHighZState ...................... -0.5Vto +7.0V Ambient
Range Vee
Temperature
Commercial OC to +70C 5V 10%
Output Current into Outputs (LOW) ............ 20 rnA
Military - 55C to + 125C 5V 1O%

7C18325 7C183-35 7C18345
Parameters Description Test Conditions 7C18425 7C18435 7C18445
Units
IIX Input Load Current GND < VI < Vee -10 +10 -10 + 10 -10 +10 ,..,A
Output Leakage GND < Vo < Vee,
IOZ -10 +10 -10 +10 -10 +10 ,..,A
Output Short Circuit Vee = Max.,
los -350 -350 -350 rnA
Current[l) VOUT = GND
Vee = Max.
Vee Operating lOUT = OmA
lee rnA
Supply Current Duty Cycle = 45%
Single Way Write Military 200 160
Capacitance [2]
pF
Vee = 5.0V[3)
Notes:
2. Tested initially and after any design or process changes that may S. Test conditions assume signal transition times of 3 ns or less, timing
affect these parameters. reference levels of l.SV, input pulse levels of 0 to 3.0V and output
3. TA is the "instant on" case temperature. loading of the specified IorJIOH and 100 pF load capacitance.
5VFl
OUTPUT
INCLUDING
JIG AND
I
Rl 1000.0.
100 f
P
R2
667.0.
5VF1
OUTPUT
INCLUDING
JIG AND
I
Rl 1000.0.
5 f
P
R2
667.0.
3.0 v------t.~'!'-'--""
GNO
:s;;3n8
0145-5
SCOPE -= - 0145-3
SCOPE -= 0145-4
Figure 2. All Input Pulses
Figure la Figure Ib
400n
OUTPUT o--wv---o 2.00V
0145-6
2-186
CY7C183
5Il~DUcrOR=======================================================================
.
Switching Characteristics Over Operating Range [4, 51

PRELIMINAR Y CY7C184
7C183-25 7C183-35 7C183-45

READ CYCLE
tRC Read Cycle Time
Min.
25
Max. Min.
35
Max. Min.
45
Max.
ns
fI
tAA A12[121 Address to Data Valid A 12 17 25 35 ns
tCE Chip Enable to Data Valid 12 15 20 ns
tcs Chip Select to Data Valid 12 15 20 ns
tOE Output Enable to Data Valid 10 14 16 ns
tOH Output Hold from Address Change 3 3 3 ns
tLZCE Chip Enable to Low Z[7] 3 3 3 ns
tLZOE Output Enable to Low Z[7, 8] 0 0 0 ns
tHZCE Chip Enable to High Z 15 25 30 ns
tHZOE Output Enable to High Z 9 10 12 ns
tpALE ALE Pulse Width 8 10 12 ns
tSALE Address Set-up to ALE Low 4 6 8 ns
tHALE Address Hold from ALE Low 4 4 4 ns
WRITE CYCLE[8]

tSCE Chip Enable to Write End 20 25 30 ns
tscs Chip Select to Write End 20 25 30 ns
tpwE Write Enable Pulse Width 20 25 30 ns
tSA Address Set-up to Write Enable 0 0 0 ns
tHA Address Hold from Write Enable 2 2 2 ns
tLZWE Write Enable HIGH to Low Z[7] 3 3 3 ns
tHzwE Write Enable LOW to High Z[7, 8] 15 15 20 ns
tpALE ALE Pulse Width 8 10 12 ns
tSALE Address ICE Set-up to ALE Low 4 6 8 ns
tHALE Address ICE Hold from ALE Low 4 4 4 ns
Notes:
6. tHZCE and tLZCE are specified with CL = 5 pF as in Figure lb. 8. Both WEA and WEB must be HIGH for read cycle.
Transition is measured 500 mV from steady state voltage. 9. Device is continuously selected, CE and CS are LOW.
7. The internal write time of the memory is defined by the overlap ofCE, 10. Address valid prior to or coincident with CE transition LOW.
CSx, and WEx. All signals must be LOW to initiate a write and any II. OE is selected (LOW).
signal can terminate a write by going HIGH. The data input set-up
and hold timing should be referenced to the rising edge of the signal 12. CY7CI83 only.
that terminates the write.
2-187
CY7C183
5n CYPRESS
~IOO~ucrOR==================================================================
Switching Waveforms
Read Cycle No.t[9, 10, 12]
ALE -----c:~tPALE-tS-AL-E-=-:..~i.!""~-~~~::::::~tR~C~~=~-t=H=AL=E=--==--==--==--,==I===::~
ADDRESS - - - - - - - )C
-------- ~tM-'t~M---A-12---------------
tOHA
DATA _ _~P~R~EV~IO~U~S~D~A~TA~VA~L~ID~_ _~~~~_ _ _ _~D~AT~A~V~A~L~ID~_ ____
0145-7
Read Cycle No. 2[9, 10, 12]
RC
1
ALE
tpALE
tSALE
-----i tHALE
f
.t::=..tM - A12 -
ADDRESS A12 )( -
)(
(7C183)
'I -
ADDRESS
Ao - All (7C183)
- ~
(
Ao - A12 (7C184)
tM
I--- tOHA --==-,
DATA PREVIOUS DATA VALID .xxx DATA VALID
0145-8
Read Cycle No. 3[9]
ALE ----~-.--~:PALEd-tR-C----tH-A-LE-:..-=--=--:.-:.-:.:.:.::~--'r
ADDRESS
----
cr,es
0145-9
2-188
CY7C183
WA . CYPRFSS PRELIMINAR Y CY7C184
s~~O~UcrOR==================================================================
ALE ------l=;=
, ,PAL,---+ll""'------------Jr
SALE . tHALE
fII
twc
-
ADDRESS 1\
tAW
tSCE,tSCS
-
XXXXXXX IXXXXX~ LXX) XXXX
I+---tSA tpWE tHA
J~
- t HZWE - _ =l t SO f--- t
LZWE
I+-tHD:I_ -
X >--~
DATA I/O DATA OUT VALID --{
- XDATA IN VALID
- .-.
OE _ _ _ _ _ _ _.... F------------{
t HZOE - - t
LZOE
0145-10
Write Cycle No.1 (CE, CS Controlled)
ALE ------l=;=,PAl,---'l-------------Jr
. SALE . twc
tHALE
ADDRESS
- tAW
tpWE -I
XXXXXXX XXXXX~ llXXXXXXXX XXXX
r.-tSA tSCE,tSCS tHA
,I
J~
EE,cs
'-
VALlOb~-----
tSD I+-tHD
DATA I/O - - - - - - - - - - - - - - c 1 0 A T A IN
0145-11
2-189
CY7C183
Wn~U~==================================================================
.
Pin Configurations
PRELIMINARY CY7C184
Vce ALE
A6 A7
A12 A5 As
CE A4 Ag
Vss A3 A10
1/15 A2 All
1/14 AI A12
7C183 1/13 Ao CE
7C184
PLCC 1/12 Vss Vss
Vss 1/0 1/15
1/11 1/1 1/14
1/10 1/2 1/13
I/Og 1/12
1/3
I/Os Vss Vss
NC
1/4 1/11
1/5 1/10
1/6 I/Og
1/7 I/Os
0145-12
Vee Vee
(,J 10.1 0
CSo Vee
Nit).... II) co (,J...J ....... 00 CJ) ... ..-
-< -< -< -< -< > -< -< -< -< -<-< WEe MODE
WEA CS 1
6 5 43 2 11 148 47 46 45 44 43
L....
42 A12 Vss OE e
Al
CE Vss OEA
Ao
Vss Vss 0145-13
1/0 1/15
1/1 1/14
1/2 7C183 1/13
7C184
1/3 LCC 1/12
Vss Vss
1/4 1/11
1/5 1/10
1/6 17 I/Og
1/7 18 I/Os
19 20 21 22 23 24 25 26 27 28 29 30
(,Jom -<1Il1ll-<m-1oI (,J(,J

I~ C
>(,J 1111
u 110.~1 110.1 III III 110.1 110.1
~ > > 0 0 ~ >(,J >(,J
0145-14
2-190
CY7C183
5n~~UaoR==================================================================
.
Truth Tables
PRELIMINARY CY7C184
Two-Way Mode (MODE = HIGH)

CE CSo CSt OEA OED WEA WED Operation
H X X X X X X Outputs Hi-Z, Write Disabled
L H H X X X X Outputs Hi-Z, Write Disabled
X X X H H X X Outputs Hi-Z
X X X L L X X Outputs Hi-Z
L L H L H H H Read 1/00-1/07 Way A
L L H H L H H Read 1/00-1/07 WayB
L H L L H H H Read 1/08-1/015 Way A
L H L H L H H Read 1/08-1/015 WayB
L L L L H H H Read 1/00-1/015 Way A
L L L H L H H Read 1/00-1/015 WayB
L L H X X L H Write 1/00-1/07 Way A
L L H X X H L Write 1/00-1/07 WayB
L H. L X X L H Write 1/08-1/015 Way A
L H L X X H L Write 1/08-1/015 WayB
L L L X X L H Write 1/00-1/015 Way A
L L L X X H L Write 1/00-1/015 WayB
L L H X X L L Write 1/00-1/07 WayA&B
L H L X X L L Write 1/08-1/015 WayA&B
L L L X X L L Write 1/00-1/015 WayA&B
Direct Mode (MODE = LOW)

CE CSo CSt OEA OED WEA WED Operation
H X X X X X X Outputs Hi-Z, Write Disabled
L H H X X X X Outputs Hi-Z, Write Disabled
X X X H H X X Outputs Hi-Z
L L H L L H H Read 1/00-1/07
L H L L L H H Read 1/08-1/015
L L L L L H H Read 1/00-1/015
L L H X X L L Write 1/00-1/07
L H L X X L L Write 1/08-1115
L L L X X L L Write 1/00-1/015
25 CY7C183-25DC D26 Commercial 25 CY7C184-25DC D26 Commercial
CY7C183-25JC J69 CY7C184-25JC J69
35 CY7C183-35DC D26 35 CY7C184-35DC D26
CY7C183-35JC J69 CY7C184-35JC J69
CY7C183-35LMB L68 CY7C184-35LMB L68
45 CY7C183-45DC D26 Commercial 45 CY7C184-45DC D26 Comme~cial
CY7C183-45JC J69 CY7C184-45JC J69
2-191
, CY7C183
&A , CYPRESS PRELIMINAR Y CY7C184
~~UcrOR============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
lIX 1,2,3
IOZ 1,2,3
los 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-192
CY7C185
CYPRESS
SEMICONDUCTOR 8192 x 8 Static RAM
Features
Automatic power-dowu when
deselected
performance CMOS static RAMs orga-
operation of the memory. When CEI
and WE inputs are both LOW, data on
til
CMOS for optimum speed! nized as 8192 words by 8 bits. These the eight data input/output pins (1/00
power RAMs are developed by Aspen Semi- through 1/07) is written into the mem-
conductor Corporation, a subsidiary of ory location addressed by the address
High speed-12 ns Cypress Semiconductor. Easy memory present on the address pins (Ao
Low active power expansion is provided by an active through Al2). Reading the device is ac-
- 550 mW at 40 MHz LOW chip enable (CEl), an active complished by selecting the device and
HIGH chip enable (CE2), and active enabling the outputs, CEI and OE ac-
Low standby power LOW output enable (OE) and three- tive LOW, CE2 active HIGH, while
-150 mW state drivers. Both devices have an au- (WE) remains inactive or HIGH. Un-
TTL compatible inputs and tomatic power-down feature (CEl), re- der these conditions, the contents of
outputs ducing the power consumption by 75% the location addressed by the informa-
when deselected. The CY7C185 is in tion on address pins is present on the
than 2001 V electrostatic the space saving 300 mil wide DIP eight data input/output pins.
discharge package and leadless chip carrier. The The input/output pins remain in a high
CY7C186 is in the standard 600 mil impedance state unless the chip is se-
wide package. lected, outputs are enabled, and write
An active LOW write enable signal enable (WE) is HIGH.
(WE) controls the writing/reading

Vee
WE
eE2
A3
A2
A8 AI
A9 Or
GND
0147-2
<CDI/)<C.... ~I~
3 2 1 2827
NC 4 26 CE2
A7 5 25 A3
A8 6 24 A2
A9 7 23 AI
A 0 8 22 Of
CE, '
All 9 21 Ao
eE 2 A'2 10 20 CE,
r-r--'T"T"'VIoo_ 1/0 11 19 1/7
WE 1/1 12 18 1/6
1314151617
0147-1
f~f~g 0147-3
Selection Guide
7C185-12 7C185-15
I 7C186-12 7C186-15
Maximum Access Time (ns) 12 15
Commercial 125 120
Military 155 145
Commercial 30 30
Maximum Standby Current (rnA)
Military 50 50
2-193
CY7C185
5Il~~UcrOR=====================================================================
.
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ................. " .. >2oo1V
(Pin 28 to Pin 14) .................... -0.5V to + 7.0V
Ambient
Temperature
Input Voltage[14] .................... - 3.0V to + 7.0V Commercial OCto + 70C 5V 1O%

7C18512 7C18515
Min. Max. Min. Max.
VOR Output HIGH Voltage Vee = Min., lOR = -4.0mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 V
VIR Input HIGH Voltage 2.2 Vee 2.2 Vee V
VIL Input LOW Voltage[14] -0.5 0.8 -0.5 0.8 V
IIX Input Load Current GND:S:: VI:S:: Vee -10 10 -10 10 p,A
Output Leakage GND:S:: VI:S:: Vee -10 -10
loz +10 +10 p,A
Output Short -300 -300
los Vee = Max., VOUT = GND mA
Circuit Current[l]
Vee Operations Vee = Max. Commercial 110 110

leel Supply lOUT = OmA mA
f = 40 MHz Military 135 135
Vee Operating Vee = Max. Commercial 125 120
lee2 mA
Max. Vee, Commercial 30 30
ISH Automatic CEI CEI ~ VIR, mA
Power Down Current Min. Duty
Cycle = 100% Military 50 50
Capacitance [2]
Parameters Description Test Conditions Max.l13] Units
CIN Input Capacitance TA=25C,f=IMHz 5
pF
COUT
Notes:

RI481n RI481n All Input Pulses
5v 0-----."""'--, 5Vo----""".........
OUTPUTo---....--~ OUTPUT 0 - -......- -.......
CL R2
~:Sn
I
5pF
I
265n
INCLUDING INCLUDING
_JIGAND _ _JIG AND _
- SCOPE - - SCOPE - 0147-6
0147-4 0147-5
Equivalent to: TREVENIN EQUIVALENT

16m
OUTPUT 0--'"'1-."'''''''''.--0 1.73V 0147-7
2-194
CY7C185
5A .
~UcrOR ==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Switching Characteristics Over Operating Range[4, s1
7C185-12 7C185-15
Parameters Description 7C186-12 7C186-15 Units
Min. Max. Min. Max.
READ CYCLE
tRc Read Cycle Time 12 15 ns
tAA Address to Data Valid 12 15 ns
tOHA Data Hold from Address Change 3 3 ns
tACEl CEI LOW to Data Valid 12 15 ns
tACE2 CE2 HIGH to Data Valid 12 15 ns
tDOE OE LOW to Data Valid 10 10 ns
tLZOE OE LOW to Low Z 3 3 ns
tHZOE OE HIGH to High Z[6] 8 8 ns
tLZCEl CEI LOW to Low Z[7] 3 5 ns
tLZCE2 CE2 HIGH to Low Z 3 3 ns

CEI HIGH to High Z[6, 71
tHZCE 8 8 ns
CE2 LOW to High Z
tpu CEI LOW to Power Up 0 0 ns
tpD CEI HIGH to Power Down 12 15 ns
WRITE CYCLErS]
twc Write Cycle Time 12 15 ns
tSCEl CEI LOW to Write End 10 12 ns
tSCE2 CE2 HIGH to Write End 10 12 ns
tAW Address Set-up to Write End 10 12 ns

tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns

tpwE WE Pulse Width 10 12 ns
tSD Data Set-up to Write End 10 10 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[6] 7 7 ns
tLZWE WE HIGH to Low Z 5 5 ns

Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing to initiate a write and either signal can terminate a write by going
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output HIGH. The data input setup and hold timing should be referenced to
loading of the specified lorJIOH and CL = 30 pF load capacitance the rising edge of the signal that terminates the write.
for 15 ns tAA devices and CL = 20 pF load capacitance for 12 ns 9. WE is HIGH for read cycle.
tAA devices. 10. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
6. tHZOE, tHZCE and tHZWE are specified with CL = 5 pF as in Figure 11. Address valid prior to or coincident with CE transition LOW.
1h. Transition is measured 500 mV from steady state voltage.
12. Data 1/0 is HIGH impedance if OE = VIH.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. 13. For all packages except cerdip (D22, D16) which has maximums of
CIN = 10 pF, CoUT = 12 pF.
CEI LOW, CE2 HIGH and WE LOW. Both signals must be LOW 14. Vldmin.) = - 3.0V for pulse width < 20 ns.
Switching Waveforms
AOO'=
DATA OUT
=t;~,.~,
PREVIOUS DATA VAUO ~=================D=A=TA==VA=L=ID=================
2-195
*- 0147-8
CY7C185
5n . ADVANCED INFORMATION
~~UaoR==================================================================
CY7C186

~------------------tRC--------------II,-___________
HIGH
DATA OUT --t=7~=*E:E~====~D~AT~A~V~A~LlDC=:::t==~I~MP~EE;DA~N~CLE
Vcc tPo~
SUPPLY ------------------------------------5~ ICC
CURRENT - - - - - - -.... IS8
0147-9

twc .
ADDRESS
tSCEl .
\V :;111 IIIIIIIII
1/ /IT :\\\\ \\\\\\\\\
tSCE2
:.u tAW
~\\\\\\\\
t HA -
tSA - tpWE -
I
h\ "'If'-
I tso - t:i tHO

DATA IN I DATA-IN VALID I
, - tHZWE.:! I-tLZWE
HIGH IMPEDANCE
'\l II
DATA I/O DATA UNDEFINED II
"' 0147-10

twc .
ADDRESS -it- jt-
1 tSCEl
~ "'If'-
tSA
-f- -'1\
tAW
i - t SCE2 -
-- t HA -
t pWE -
\\\\\\\\\\\\\\\\\\\~ f.LIU /i ILl I I II
I~tso .1 tHO
DATA IN II DATA-IN VALID I
I- tHZWE-
DATA I/O ___________D_A_TA_U_N_D_EF_IN_ED
__________ ---J~)o-------------------
HIGH IMPEDANCE
0147-11
2-196
CY7C185
fiA~~UaoR==================================================================
Truth Table
CEI
H
X
L
L
CE2
X
L
H
H
WE
X
X
H
L
OE
X
X
X
L
Input/Outputs
HighZ
HighZ
Data Out
Data In
Mode
Deselect Power Down
Deselect
Read
Write
,.
L H H H HighZ Deselect
CY7C185-12VC V21 CY7C186-12DC D22
CY7C185-12DC D22 CY7CI86-12DMB D22 Military
CY7C185-12LC L54 15 CY7C186-15PC P21 Commercial
CY7CI85-12DMB D22 Military CY7C186-15DC D22
CY7CI85-12LMB L54 CY7C186-15DMB D22 Military
CY7C185-15VC V21
CY7C185-15DC D22
CY7C185-15LC L54
CY7CI85-15LMB L54
2-197
. CY7C185
(;n~~u~==============================================================
. ADVANCED INFORMATION CY7C186 ~
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISBl 1,2,3
READ CYCLE
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACEl 7,8,9,10,11
tACE2 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
tscEl 7,8,9,10,11
tSCE2 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #: 38-A-OOOI6
2-198
CY7C185
CY7C186
CYPRESS
Features
The CY7C185 and CY7C186 are high the eight data input/output pins (1/00
II
deselected performance CMOS static RAMs orga- through 1/07) is written into the mem-
nized as 8192 words by 8 bits. Easy ory location addressed by the address
power memory expansion is provided by an present on the address pins (Ao
active LOW chip enable (CEI), an ac- through A12). Reading the device is ac-
High speed-20 ns tive HIGH chip enable (CE2), and accomplished by selecting the device and
Low active power tive LOW output enable (OE) and enabling the outputs, CEI and OE ac-
-550mW three-state drivers. Both devices have tive LOW, CE2 active HIGH, while
an automatic power-down feature (WE) remains inactive or HIGH. Un-
Low standby power (CEI), reducing the power consump- der these conditions, the contents of
-110 mW tion by 73% when deselected. The the location addressed by the informa-
TTL compatible inputs and CY7C185 is in the space saving 300 mil tion on address pins is present on the
outputs wide DIP package and leadless chip eight data input/output pins.
carrier. The CY7C186 is in the stan- The input/output pins remain in a high
dard 600 mil wide package. impedance state unless the chip is se-
discharge An active LOW write enable signal lected, outputs are enabled, and write
(WE) controls the writing/reading op- enable (WE) is HIGH. A die coat is
eration of the memory. When CEI and used to ensure alpha immunity.
WE inputs are both LOW, data on
A12
1/00 11 1/6
1/1 1/0 5
1/2 1/04
GND 15 1/03
0055-2
3212827
NC 26 CE2
A7 25 A3
As 6 24 A2
Ag 7 23 Al
A10 8 22 Of
A11 9 21 Ao
A12 10 20 eEl
1/0 11 19 1/7
1/1 18 1/6
0055-1
~~~~~ 0055-3
Selection Guide
7C185-20 7C185-25 7C185-35 7C185-45 7C185-55
7C186-20 7C186-25 7C186-35 7C186-45 7C186-55
Current (rnA) Military 125 100 100 100
Maximum Standby Commercial 40/20 20/20 20/20 20/20 20/20
Current (rnA) Military 40/20 20/20 20/20 20/20
2-199
CY7C185
fiA . CYPRFSS
SEMlCONDUcrOR
Maximum Ratings
=====================================================================
CY7C186
Supply Volt~ge to Ground Potential Operating Range
(Pm 28 to Pm 14) .................... -O.SV to +7.0V
Range Vee
in High Z State ...................... -O.SV to + 7.0V Temperature
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to +70C SV 10%
Output Current into Outputs (Low) ............. 20 rnA Military [3] - 55C to + 125C SV 10%
Electrical Characteristics Over Operating Rangd4]
7C185-20 7C185-25, 35, 45 7C185-55
Parameters Description Test Conditions 7C186-20 7C186-25, 35, 45 7C186-55 Units
VIL Input LOW Voitagd4Al -3.0 0.8 -3.0 0.8 -3.0 0.8 V
IIX Input Load Current GND S VI S Vee -10 10 -10 10 -10 10 p,A
Output Leakage GND S VI S Vee -10 -10 -10
loz +10 +10 +10 p,A
Output Short -300
los Vee = Max., VOUT = GND -300 -300 rnA
Circuit Current [1 1
Coml. 100 100 80
lee Supply Current lOUT = OmA
Mil.~
35,45
125
100
100
rnA

Automatic CEI CEI 2 VIR,
Mil.~
ISBI 40 rnA
Power Down Current Min. Duty 20
Cycle = 100% 35,45 20
Automatic CEI CEI 2 Vec-0.3V, rnA
ISB2 Power Down Current VIN 2 Vec-0.3V
orVIN S 0.3V Mil. 20 20
Capacitance [2]
CIN Input Capacitance TA = 25C,f= 1 MHz 5
pF
CoUT
Notes:
5 v o---~Nv--, 5 V o---~"""'--,
3.0V----.i~---!L
OUTPUT 0 - -.......- - - - . . OUTPUT 0 - -.......-----+
30pF R2
5pF ~~11
I I
255fl GND
INCLUDING INCLUDING
_JIGAND _ _JIG AND _
- SCOPE - - SCOPE - 0055-6
0055-4 0055-5
Figure 1a Figure 1b Figure 2

16m
OUTPUT 0_--"l'' ' ' ' ' -_01.73V 0055-7
2-200
CY7C185
fiji
... CY7C186
~ ~NDUcroR =====================================================================
7C18520 7C18525 7C18535 7C18545 7C18555
Parameters Description 7C18620 7C18625 7C18635 7C18645 7C18655 Units
READ CYCLE
til
tACEI CE I LOW to Data Valid 20 25 35 45 55 ns
tACE2 CE2 HIGH to Data Valid 20 25 25 30 40 ns

tLZCEI CEI LOW to Low Z[7] 5 5 5 5 5 ns
tLZCE2 CE2 HIGH to Low Z 3 3 3 3 3 ns

CEI HIGH to High Z[6, 7]
tHZCE 8 10 15 15 20 ns
CE2 LOW to High Z
tpu CEI LOW to Power Up 0 0 0 0 0 ns
tpD CEI HIGH to Power Down 20 20 20 25 25 ns
WRITE CYCLE[S]
tSCEI CEI LOW to Write End 15 20 25 30 40 ns
tSCE2 CE2 HIGH to Write End 15 20 20 25 30 ns
tAW Address Setup to Write End 15 20 25 30 40 ns

tpWE WE Pulse Width 15 15 20 20 25 ns
tHZWE WE LOW to High Z[6] 7 7 10 15 20 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing to initiate a write and either signal can terminate a write by going
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output HIGH. The data input setup and hold timing should be referenced to
loading of the specified lor/loH and 30 pF load capacitance. the rising edge of the signal that terminates the write.
6. tHZOE, tHZCE and tHZWE are specified with CL = 5 pF as in Figure 9. WE is HIGH for read cycle.
1b. Transition is measured 500 mV from steady state voltage. 10. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
7. At any given temperature and voltage condition, tHZCE is less than II. Address valid prior to or coincident with CE transition LOW.
tLZCE for any given device. 12. Data I/O is HIGH impedance ifOE = VIH.
CEI LOW, CE2 HIGH and WE LOW. Both signals must be LOW
Switching Waveforms
~D", =tL.~,
DATA OUT PREVIOUS DATA VAuo ~=================D=A=TA==VA=L=ID=================
*- 0055-8
2-201
CY7C185
(in~NDUcrOR =====================================================================
. CY7C186

~-------------------tRc--------------1,____________
HIGH
DATA OUT
---t:~~::::~Et!3at:::::::::J~~~:::::t::::~IM~P~E~DA~N~CE~
DATA VALID
Vcc tPo~
SUPPLY - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -50% ICC
CURRENT _______..J IS8
0055-9

twc I
ADDRESS
. tscEl
"\V :;11/ IIIIIIIII
I
II Li-f- :\ \ \ \ 1\\\\\\\\\
I tscE2
:..u tAW
~\\\\\\\\
t HA-
tSA _ t pWE -
I
\:~: ~
tso .1 tHO

.1
DATA IN
DATA-IN VALID
~tHZWE:1 -tLZWE-1
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED
" I\.
0055-10

twc
-
I
ADDRESS I-
.1 tSCE1 -
\:
tSA
1
_-f-
. tAW
I - - tSCE2 -
t pwE -
-- t HA -
\\\\\\\\\\\\\\\\\\\\ ... ~/ /////////// /

I-tso 1tHO
DATA IN AI DATA-IN VALID I
I-- t HZWE
DATA I/O ____________
DA_T_A_U_ND_E_FI_NE_D___________ )..J-.. . . . . ;.;. ;,; ; .-. . . ~---------
HIGH IMPEDANCE
0055-11
2-202
CY7C185
(iJl~NDUcroR =======================================================================
.' CY7C186

1.4
1.2
vs SUPPLY VOLTAGE
./
1.2
1.0
~ ;;(
!
120
vs OUTPUT VOLTAGE
til
le~
100
~
I-
~ 1.0 ~ ~
.:;
.!t
S 0.8 ./ '"
.!t
S
0.8 II:
II:
:J
U
80
~
N
::..c( 0.6 ./ N
::.
.c(
0.6 w
u
II:
:J
60
~ Vee = 5.0 V
TA = 25'C
~ ~ 0
II: II: 0.4 II) 40
0.4
'"
0 0 Vee = 5.0 V I-
Z z VIN =5.0V :J
C>.
02 0.2 -ISB I- 20
~
ISB :J
0
0.0 0.0 o
4.0 4.5 5.0 5.5 6.0 55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OCI OUTPUT VOLTAGE (V)

1.4 1.6 140
JIf'
1.3 <i 120
1.4 ! /V
<l I- 100
<l
~ ~
~
S
1.2
....
S 1.2 /' II:
a:: 80
/ Vee = 5.0 V
TA = 25'C
/
N :J
N
::..c( 1.1 ::. U I
"'" TA = 25'C
<I: :..: 60
~
~ :E Z
II:
1.0
r:;;
/
/
II:
---- -
0 1.0 0 Vee = 5.0 V
Z I- 40
Z :J
0.9 0.8
~
C>.
I-
:J
0 20
/
0.8 0.6
V
4.0 4.5 5.0 5.5 6.0 55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ('C) OUTPUT VOLTAGE (VI

r----r----.....,r------,
--
3.0 30.0 1.25
Vee = 5.0 V
2.5 25.0 TA = 25C
E 2.0 :g 20.0
/ II
VIN = 0.5 V
1.0 t---~I_-----il---......
,/
S
N
..:
..:
@
N
::..c( 1.5 ; 15.0 ::..c(
~
II:
1.0
~o 10.0
L ~
~ 0.751_---:1;00""""'"---:1----:1
! z
L /V TA = 25'C
Vee =4.50 V
0.5
0.0
0.0 1.0 2.0 -
SUPPL Y VOLTAGE (VI
~
3.0 4.0 5.0
5.0
0.0
o
/ 200 400 600
CAPACITANCE (pF)
800 1000
0.501~0---000:12":-0---....
3 0 - - -.......
CYCLE FREQUENCY (MHzI

4O
0055-13
2-203
CY7C185
fjn
.
. .
~~UcrOR==================================================================
CY7C186
Truth Table
CEi CE 2 WE OE Input/Outputs Mode
H X X X HighZ Deselect Power Down
X L X X HighZ Deselect
L H H L Data Out Read
L X L X Data In Write
CY7C185-20VC V21 CY7C186-20DC D22
CY7C185-20DC D22 25 CY7C186-25PC P21 Commercial
CY7C186-20LC L54 CY7C186-25DC D22
25 CY7C185-25PC P21 Commercial CY7C186-25DMB D22 Military
CY7C185-25VC V21 35 CY7C186-35PC P21 Commercial
CY7C185-25DC D22 CY7C186-35DC D22
CY7C185-25LC L54 CY7C186-35DMB D22 Military
CY7C185-25DMB D22 Military 45 CY7C186-45PC P21 Commercial
CY7C185-25LMB L54 CY7C186-45DC D22
CY7C185-25KMB K74 CY7C186-45DMB D22 Military
CY7C185-35VC V21 CY7C186-55DC D22
CY7C185-35DC D22 CY7C186-55DMB D22 Military
CY7C185-35LC L54
CY7C185-35LMB L54
CY7C185-35KMB K74
CY7C185-45VC V21
CY7C185-45DC D22
CY7C185-45LC L54
CY7C185-45LMB L54
CY7C185-45KMB K74
CY7C185-55VC V21
CY7C185-55DC D22
CY7C185-55LC L54
CY7C185-55LMB L54
CY7C185-55KMB K74
2-204
CY7C185
WA .
~~UcrOR ==================================================================~
CY7C186

Address Address Pin
A4 X3 2
A5 X4 3
A6 X5 4
A7 X6 5
A8 X7 6
A9 YI 7
AIO Y4 8
All Y3 9
AI2 YO 10
AO Y2 21
Al XO 23
A2 Xl 24
A3 X2 25
0055-14
2-205
CY7C185
5'n CYPRESS CY7C186
S~OO~UaoR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tAcEl 7,8,9,10,11
tACE2 7,8,9,10,11
tOOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCEl 7,8,9,10,11
tSCE2 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tso 7,8,9,10,11
tHO 7,8,9,10,11
Document #: 38-00037-0
2-206
CY7C187
CYPRESS
Automatic power-down when The CY7C187 is a high performance Reading the device is accomplished by
CMOS for optimum speed/ 65,536 words x 1 bit. Easy memory ex- while write enable (WE) remains
power pansion is provided by an active LOW HIGH. Under these conditions the
High speed-20 ns ers. The CY7C187 has an automatic fied on the address pins will appear on
Low active power power-down feature, reducing the pow- the data output (DO) pin.
-440mW er consumption by 80% when deselect- The output pin stays in high impedance
Low standby power ed. state when chip enable (CE) is HIGH
-110 mW
Writing to the device is accomplished or write enable (WE) is LOW.
TIL compatible inputs and when the chip enable (CE) and write
outputs The 7C187 utilizes a Die Coat to en-
enable (WE) inputs are both LOW. sure alpha immunity.
Capable of withstanding greater Data on the input pin (DI) is written
than 2001 V electrostatic into the memory location specified on
discharge the address pins (Ao through AlS).

AO Vee Ao Vee
A 5 A, A'5
01 '
A'4 A2 A'4
A3 A A3 A 3
'3
'
A'2 A4 A'2
NC A5 A,l
A,l A6 A'0
A'2 A7 A9
A'0
AI3
A9 Dour A8
A'4
AI5 DO Dour A8 WE DIN
Act WE DIN GND CE
A, GND CE
Az 0029-2
A3 0029-16 011)
_00_
CE ~~>~
NC Vee
Ao A'5 A'4
WE A, A 3
A'4
A2 A '
A'2
'3
A4As AI A7 Ae At A'0 A" 0029-1 A3 A12 A11
A
A" '0
NC A9
A8
A'0
A9
A8 I~ ~I~ J
DIN 0029-3
CE
0029-17
Selection Guide
7C187-20 7C18725 7C187-35 7C187-45
2-207
~ CY7C187
~~~NDUcrOR =======================================================================
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ...... " ............. >2OO1V
(Pin 22 to Pin 11) .................... -O.SV to + 7.0V
Range Vee
Temperature
in High Z State ...................... -O.SV to +7.0V
Commercial OCto + 70C 5V 1O%
Military [4] - 55C to + 125C 5V 10%
Electrical Characteristics Over Operating Range[5)
7C187-20 7C187-25,35 7C187-45
VOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 2.4 2.4 V
VOL Output LOW Voltage V M'

ee= m.
IIOL = S.OmA Military
0.4 0.4 0.4 V
IIOL = 12.0 rnA Commercial
VIL Input LOW Voltage[SA] -3.0 O.S -3.0 O.S -3.0 O.S V
IIX Input Load Current GND ~ VI ~ Vee -10 +10 -10 +10 -10 +10 ,..,A
loz Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -10 +10 -10 +10 -10 +10 ,..,A
los Vee = Max., VOUT = GND -350 -350 -350 rnA
Current!t]
Vee Operating Vee = Max. Commercial SO 70 50
lee rnA
Commercial 40 20 20
ISB}
Automatic CE[2]
Power Down Current
Max. Vee,
CE ~ VIH Military ffi
35
40
20
20
rnA
Max. Vee,CE ~ Vee - 0.3V, Commercial 20 20 20

Automatic CE[2]
ISB2 Power Down Current VIN ~ Vee - 0.3Vor rnA
VIN ~ 0.3V Military 20 20
Capacitance [3]
pF
COUT Output Capacitance Vee = 5.0V 7
Notes:
2. A pull-up resistor to Vee on the CE input is required to keep the 4. T A is the "instant on" case temperature.
device deselected during Vee power-up, otherwise ISB will exceed 5. See the last page of this specification for Group A subgroup testing
SA. VIL min. = - 3.0V for pulse durations less than 30 ns.
R1 329 n R1 329 n
(480 n MIL) (480 n MIL)
5 V Q-----.A,J'V'Ir-, 5 v o-----iI,II/'v--, 3.0V----~~---L
O U T P U T D - - - _ - -... OUTPUT o---_--~

GND
R2 R2
2020 5 pF 202n
INCLUDINGI30 pF (25Sn MIL) 0029-5
JIG AND ,NCLUDINl (2550 MIL)
SCOPE JIG AND
-= Figure 2
SCOPE
-= 0029-4
Figure la Figure lb
Equivalent to: THE-VENIN EQUIVALENT
1670 1250
OUTPUT ~1.73V OUTPUT ~ 1.90V 0029-12
0029-6
Military Commercial
2-208
~ CY7C187
~~~NDUcrOR =====================================================================
tRC
)t ~~
tAce . 1
DATA OUT
t
Lzce
HIGH IMPEDANCE
:-! 1/ / / I / V
DATA VALID
1-'"' '1 HIGH
IMPEDANCE
I" \. \. \. \. I\.
1
J
f---tpu ~tpo
--j ICC
VCC _ _ _ _ _ _
SUPPLY
CURRENT _
50%
=t= ISB
0029-8

~------------------------------~C----------------------------~
ADDRESS
1+------------------- tscE-----------------------t
1+-------------------------tAW------------------------~.---
t--------tsA-------~ 1-0-------- tPWE-----t
I-o--:---------tso-----I+-
tHZWE~
DATA OUT ----------DA-T-A-U-N-D-E-F-IN-E-D-------- -----------"'\"'_______
0029-9
Write Cycle No.2 (CE Controlled)[9]

t--------------------------twc----------------------------~
ADDRESS
1------ tsA--------~-----------tscE----------~
t----------tPWE - - - - - - - - 1
I---+---------tso---------.....-
IHZWE---1
--------------------__\[ HIGH IMPEDANCE
DATA OUT DATA UNDEFINED /)-----------------------
0029-10
2-210
~ CY7C187
~~~NDUcroR =====================================================================
NORMALIZED NORMALIZED
1.4
1.2
SUPPLY CURRENT
vs SUPPLY VOLTAGE
/
1.2
SUPPLY CURRENT
~ ~
120
vs. OUTPUT VOLTAGE
fI
!
I~y 1.0 100
~
I-
~
ID
1.0 ffi
.!:
<..i
/ ~ 0.8 cr:
cr: 80
" '"
0.8 ::::l
8N 8N
V
U
0.6 w 60
:::; 0.6 :J u
Vee =5.0 V
< cr:
:E < ::::l TA = 25'C
cr: :E 0.4 0
0.4 cr: (Il 40
'" .'"
0 0 Vee =5.0V
z z VIN = 5.0 V
I-
::::l
a..
0.2 0.2 - I S 8 I- 20
IS8 ::::l
0
0.0 0.0
4.0
o
4.5 5.0 5.5 6.0 -55 25.0 125.0 0.0 1.0 2.0 3.0 4.0
NORMALIZED FREQUENCY NORMALIZED FREQUENCY OUTPUT SINK CURRENT

vs SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE
1.4 1.6 140
1.3 ~ 120
.-

1.4 t-----+-------1 ! /~
I- 100
~ ~ Vee = 5.0 V
S
~ 1.2
S
N
1.2 t-----+----.....,..,c..-j cr:
cr: BO / TA =25-C
N
:::;
<
1.1
" .............. TA = 25'C
:::;
<
U
::::l
:.: 60
I
z
:E
~ ~ 1.0 t-------:~::....------j
cr:
0
z
1.0
r--
o
z
iii
I- 40 /
0.9
0.8
----- 0.8 b.;c...---+---------j
0.6 ......._ _ _ _oL-_ _ _ _ _.....

ir
I-
::::l
0 20
Ii
/
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0

3.0 30.0 1.25
2.5 25.0
.,..- Vee = 5.0 V
TA = 25C
g
0
2.0 :g 20.0 / u
u
VIN = 0.5 V
W
N
:J
<
1.5

;{ 15.0
~
/ N
0
W
:J
<
~
:E
cr:
i 1.0 o 10.0
/ :E
a:
i
/ LV TA = 25'C
Vee = 4.50 V
-
0.5 5.0
~ /
0.0 0.0 0.50
0.0 1.0 2.0 3.0 4.0 5.0 o 200 400 600 BOO 1000 10 20 30 40
0029-14
2-211
~ CY7C187
~~~~UcrOR==================================================================
Truth Table
CE WE Input/Outputs Mode
H X HighZ Deselect Power Down
L H Data Out Read
L L Data In Write
CY7C187-20VC V13 CY7C187-35VC V13
CY7C187-20DC DIO CY7C187-35DC DIO
CY7C187-20LC L52 CY7C187-35LC L52
25 CY7C187-25PC P9 Commercial CY7C187-35DMB DIO Military
CY7C187-25VC V13 CY7C187-35LMB L52
CY7C187-25DC DIO CY7C187-35KMB K73
CY7C187-25LC L52 45 CY7C187-45PC P9 Commercial
CY7C187-25DMB DIO Military CY7C187-45VC V13
CY7C187-25LMB L52 CY7C187-45DC DIO
CY7C187-25KMB K73 CY7C187-45LC L52
CY7C187-45LMB L52
CY7C187-45KMB K73
2-212
~ CYPRESS CY7C187
~~~O~U~R ========================================================~====~~
Address Designators BitMap
Address Address Pin
AO
Al
X3
X4
1
2
fI
A2 X5 3
A3 X6 4
A4 X7 5
A5 Y7 6
A6 Y6 7
A7 Y2 8
A8 Y3 14
A9 Y1 15
AlO YO 16
All Y4 17
A12 Y5 18
A13 XO 19
A14 Xl 20
A15 X2 21
0029-15
2-213
~ CY7C187
~~~U~============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
ISB! 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-214
CY7C189
CY7C190
CYPRESS
Fully decoded, 16 word x 4-bit The CY7C189 and CY7C190 are ex- rect data is present at the data outputs
high speed CMOS RAMs tremely high peformance 64-bit static (00-03) when the write cycle is com-
RAMs organized as 16 words x 4-bits. plete. This precondition operation in-
Inverting outputs CY7C189
Easy memory expansion is provided by sures minimum write recovery times by
Non-inverting outputs CY7C190 an active LOW chip select (CS) input eliminating the "write recovery glitch".
High speed and three-state outputs. The devices Reading is accomplished with an active
- 15 ns and 25 ns commercial are provided with inverting (CY7C189) LOW on the chip select line (CS) and a
- 25 ns military and non-inverting (CY7C190) outputs. HIGH on the write enable (WE) line.
Low power An active LOW write enable (WE) sig- The information stored is read out
- 303 mW at 25 ns nal controls the writing and reading of from the addressed location and pre-
- 495 mW at 15 ns the memory. When the write enable sented at the outputs in inverted
(WE) and chip select (CS) are both (CY7C189) or non-inverted
Power supply 5V 10% LOW the information on the four data (CY7C190) format.
Advanced high speed CMOS inputs (00-03) is written into the lo- During the write operation or when the
processing for optimum cation addressed by the information on chip select line is HIGH the four out-
speed/power product the address lines (Ao-A3). The outputs puts of the memory go to an inactive
are preconditioned such that the cor- high impedance state.
greater than 2000V static
discharge
Three-state outputs
TTL compatible interface levels
Logic Block Diagrams Pin Configuration

CY7C189 CY7C190
Do Do
Ao Vee
0, 0,
cs A,
02 02 WE A2
Do A3
03 03
(00)00 03
0, 03 (ch)
Ao Ao (0,)0, 02
00 00
GNO 02 (02)
A, A,
0, 0,
0011-3
A2
02
A2 02 (7CI89)
7C190
03 03
A3 A3
cs cs
WE WE
0011-1
Selection Guide
7C18915 7C18925
7C190-15 7C190-25
Commercial 15 25
Military 25
Commercial 90 55
Military 70
2-215
CY7C189
(fA .
. ~~UcrOR=====================================================================
CY7C190
Maximum Ratings
Power Applied .................... - 55C to + 125C Latchup Current .......................... > 200 rnA
Supply Voltage to Ground Potenial
(Pin 16 to Pin 8) ..................... -0.5V to + 7.0V
Operating Range
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to +70C 5V 1O%
Output Current, into Outputs (Low) ............. 20 rnA Military [4] - 55C to + 125C 5V 1O%
Electrical Characteristics Over the Operating Range[S)

7C189-15 7C189-25
Parameters Description Test Conditions 7C190-15 7C190-25 Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min.,loH = -5.2 mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 16.0 mA 0.45 0.45 V
VIR Input HIGH Voltage 2.0 Vec 2.0 Vce V
IIX Input Leakage Current GND S VI S Vee -10 +10 -10 +10 J.tA
Input Diode Clamp
VeD Voltage[l)
IoZ Output Leakage Current GND S Vo s Vce -40 +40 -40 +40 J.tA
Output Short
lOS Vee = Max., VOUT = GND -90 -90 mA
Circuit Current[2]
Ice Power Supply Current

Vee = Max., I Commercial 90 55 mA
lOUT = OmA
I Military 70 mA
Capacitance [6]
pF
COUT Output Capacitance Vcc = 5.0V 7
Notes:
1. The CMOS process does not provide a clamp diode. However the 4. T A is the "instant on" case temperature.
CY7C189 and CY7C190 are insensitive to - 3V dc input levels and S. See the last page of this specification for Group A subgroup testing
- 5V undershoot pulses of less than 5 ns (measured at 50% points). information.
3. Output is preconditioned to data in (inverted or non-inverted) during
write to insure correct data is present on all outputs when write is
terminated. (No write recovery glitch).
2-216
CY7C189
fin ~~~UcrOR=======================================================================
Switching Characteristics Over the Operating Range[S, 7]
CY7C190
7C189-15 7C189-25
Test 7C190-15 7C190-25
Parameter Description Units
Conditions
Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 15 25 ns
tACS Chip Select to Output Valid Note 10 12 15 ns
tHZCS Chip Select Inactive to High Z Notes 9,11 12 15 ns
tLZCS Chip Select Active to Low Z 12 15 ns
tOHA Output Hold from Address Change 5 5 ns
tAA Address Access Time Note 10 15 25 ns
WRITE CYCLE[3, 8]

tHZWE Write Enable Active to High Z Notes 9,11 12 20 ns
tLzwE Write Enable Inactive to Low Z 12 20
tAWE Write Enable Inactive to Output Valid Note 10 12 20 ns
tPWE Write Enable Pulse Width 15 20 ns
tSD Data Setup to Write End 15 20 ns
tSA Address Setup to Write Start 0 0 ns
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing 9. Transition is measured at steady state HIGH level - 500 m V or
reference levels of 1.5V, output loading of the specified IOL /IOH steady state LOW level + 500 mV on the output from 1.5V level on
and 30 pF load capacitance. the input.
S. The internal write time ofthe memory is defined by the overlap of 10. tAA, tACS and tAwE are tested with CL = 30 pF as in Figure 1a.
CS LOW and WE LOW. Both signals must be LOW to initiate a Timing is referenced to 1.5V on the inputs and outputs.
write and either signal can terminate a write by going HIGH. The 11. tHZCS and tHZWE are tested with CL = 5 pF as in Figure lb.
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.

1 - - - - - - , - - - COLUMN Address Address Pin
i-------OUTPUTS
Ao AXO 1
Al AXI 15
A2 AYO 14
A3 AYI 13
ROWO
ROW3
0011-5
2-217
CY7C189
5'n~U~================================================================
.
ACTest Loads and Waveforms

CY7C190
ALL INPUT PULSES

Rt23ltn Rt23tO
5 V o------'~rv---, 3.0 V-----w"!"!"'~--_
OUWUT~----~-------+ OUTPUT 0-----_------..... GND----"'I
30pF R2 5pF R2 .;;5 ns .;;5 ns
I I
150n 150n
0011-8
,NCLUD,NG INCLUDING
JIG AND _JIGAND _
':" SCOPE ':" - SCOPE -
0011-6
Figure la Figure lb
OUTPUT oO---.J<'\M.,----O 1.92V

920
0011-7
Read Mode
J;~~----tRC----------~~
AD~~E~----------~~::::::::~-t-A-A:::::::::-.~-'----~-~-H-A--------------------------------...~
~
CHIP SELECT
DATA
OUTPUTS----------------------~----_t~~f<
OO~3 ~~~~---------~~~f\------~~----~~~
NOTE 9
0011-9
Write Mode
AD~~E~ _________ ~~:~~~~~~~~~~~~~~~~~~~-~-C--------------_-_-_-_-_-_-_-_-_-

tsA -
___--...~---------------
.-tHA
~
CHIP SELECT
tso tHO ....

00-0 3
DATA IN 7f- j f-
tPWE
WRITE ENABLE
~ --'
~ ./-
tHZWE '-_L_NOTE9 !---tAWE~
00-03 ~"""""- JLIfflJ
DATA OUTPUTS
-tLZWE.J""""
.I.~
LOAD
LNOTE9
0011-10
(All above measurements referenced to 1.5V.)
Note:
2-218
CY7C189
Wn . CYPRESS
S~ICO~UaoR========================================================~~~~
CY7C190
NORMALIZED Icc NORMALIZED Icc OUTPUT SOURCE CURRENT

1.2 r---........,r---....,...---"';";;;;""----. 1.4 r----~-,..-------.;.;;;;.., 60
~
! 50
"'"
I- Vee = 5.0 V
1.0 1.2 Z TA = 25'C
<J <J w
!: !: a: 40
c cw a:
w ~
N N CJ
:::i 0.8 ::::i w 30
CJ
~
c( c(
~ ~
a:
~
a: a:
0 0 Sl 20
Z 2
Vee = 5.5 V
I-
~
a..
I- 10 "r\.
'"
~
TA = 25'C 0
0.4 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0

1.6 1.4 ..------~-------, 150
0.-
~
125
!
~V
1.4
1.2f-----+_---~.......j
I-
'"
:! :!'" 2
w 100
C
w 1.2 c
w
a:
a:
~ /
-
N
::::i ~ 1.01-------:::IO~----___l CJ 75
c( c( ~ 'I
~
a:
1.0 ~
a:
2
iii
)
50
~ 0.8~----+_----__l
/
0 I-
2 ~
a..
0.8 Vee = 5.0 V_
~ 25
TA i 25'C Vee =5.0V 0
/ TA =r'c
0.6 0.6~----..L...--------I o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0 5.0
ACCESS TIME CHANGE NORMALIZED Icc

30..---~-~-~--r-~ 1.4
TA = 25C
Vee =4.5 V 1.3
1/
! 20f--+--~-~~-~~ !:
cw
<J
1.2
~/
c(
'"
:! N
::::i
c(
/V
!:i ~
a: 1.1
~ 10~-~~~--+--~~ 0
2 V
1.0 /
200 400 600 800 1000 00 10 20 30 40 50 60 70

0011-11
2-219
CY7C189
5'A .
~~UcrOR================================================================
Ordering Information Pin Configuration
CY7C190

(ns) Ordering Code . Range
Type
15 CY7C189-15PC PI Commercial
CY7C190-15PC
CY7C189-15DC D2
CY7C190-15DC
CY7C189-15LC L61
CY7C190-15LC
25 CY7C189-25PC PI
CY7C190-25PC
.-0 ('4 ('40
CY7C189-25DC D2 0%00%
........ C!> ........
CY7C190-25DC
CY7C189-25LC L61
~ I~
0011-4
CY7C190-25LC
(7C189)
7C190
CY7CI90-25DMB
CY7C 189-25LMB L61
CY7CI90-25LMB
2-220
CY7C189
fin CY7C190
~~~UcrOR================================================================
DC Characteristics
Parameters
VOR
VOL
VIR
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tACS 7,8,9,10,11
tORA 7,8,9,10,11
tAA 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tAWE 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tRD 7,8,9,10,11
tSA 7,8,9,10,11
tRA 7,8,9,10,11
2-221
CY7C191
PRELIMINARY CY7C192
CYPRESS
Separate I/O
Features
Automatic power-down when Capable of withstanding greater Data on the four input pins (10 through
deselected than 2001V electrostatic 13) is written into the memory location
Transparent write (7CI91) discharge specified on the address pins (Ao
through A1S).
CMOS for optimum speed/ Functional Description Reading the device is accomplished by
power
The CY7C191 and CY7C192 are high taking the chip enable (CE) LOW,
High speed performance CMOS static RAMs orga- while the write enable (WE) remains
- 25 ns tAA nized as 65,536 x 4 bits with separate HIGH. Under these conditions the
Low active power I/O. Easy memory expansion is pro- contents of the memory location speci-
- 385 mW vided by active LOW chip enable (CE) fied on the address pins will appear on
and three-state drivers. They have an the four data output pins.
Low standby power automatic power-down feature, reduc-
- 110 mW The output pins stay in himpedance
ing the power consumption by 71 %
TI'L compatible inputs and when deselected.
(7C192 only), or chip enable (CE) is
outputs Writing to the device is accomplished HIGH.
when the chip enable (CE) and write
munity.

'0 Ae Vee
As
,1.4
,1.8 ,1.3
'2
,1.2
'3 AI
Au Ao
Au
Ao 00
AI
,1.2
,1.3 2
0,
,1.4
As
,1.6 2
,1.7
,1.8
,1.9 03 0108-2
~.t'~~ ...'"
3 2lTI2827
CE AI 4 26 ,1.4
,1.,0 5 25 ,1.3
All 6 24 ,1.2
,1.12 7 23 AI
,1.13
WE
8 22 Ao
,1.,4 9 21 '3
A,S 10 20 '2
'0 11 19 03
12 18 2
" 1314151617
0108-1
Itt ~I~ 6'0-
<:>
0108-10
Selection Guide
7C191-25 7C191-35 7C191-45
7C192-25 7C192-35 7C192-45
Maximum Access Time (ns) 2S 3S 45
2-222
CY7C191
Wn ~~~UcrOR==================================================================
Maximum Ratings

Ambient Temperature with (Per MIL-STD-883, Method 3015)
(Pin 28 to Pin 14) .................... -O.5V to + 7.0V
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to +70C 5V 1O%
Output Current into Outputs (LOW) ............ 20 rnA Military [2] -55C to + 125C 5V 1O%

7C191-25 7C191-35 7C191-45
IIX Input Load Current GND S VI S Vee -10 +10 -10 +10 -10 + 10 ].LA
Ioz Output Leakage Current GND s Vo s Vee, Output Disabled -10 +10 -10 +10 -10 +10 ].LA
Output Short Circuit -350 -350 -350
lOS Vee = Max., VOUT = GND rnA
Current[l]
Icc rnA
Automatic CE Max. Vee, CE 2 VIH Commercial 20 20 20
ISB! rnA
Power Down Current Min. Duty Cycle = 100% Military 20 20 20
Max. Vee, Commercial 20 20 20
Automatic CE CE 2 Vee - 0.3V rnA
ISB2 Power Down Current VIN 2 Vee - 0.3Vor
VIN s 0.3V Military 20 20
Capacitance [4]
Notes:
1. Not more than one output should shorted at one time. Duration of 3. See the last page of this specification for Group A subgroup testing
Rl 48H! R1481H
5Vo-------JV~~ 5VC-------~~ __
)UTPUT o----..-------t OUTPUT 0..--_---.. . 3 . 0 V - - - - .....---~
30 pF R2
5pF ~:5n
I_
-
INCLUDING
JIGAND _
SCOPE -
255H
I INCLUDING
_JIG AND
- SCOPE
_
- 0108-3
GND
0108-5
l.quivalent to: THEVENIN EQUIVALENT
16m
OUTPUT O~-~V~V"\r.---O 1.73V
0108-4
2-223
CY7C191
f;A~~UaoR================================================================
. PRELIMINARY CY7C192

7C19125 7C19135 7C19145
READ CYCLE
toHA Output Hold from Address Change 3 3 3 ns
tLZCE CE LOW to LOW Zl71 3 3 3 ns
WRITE CYCLErS]
tAw Address Setup to Write End 20 25 35 ns
tSA Address Setup to Write Start 0 0 0 ns
tLZWE WE HIGH to Low Z[7] (7CI92) 3 3 3 ns
tHZWE WE LOW to High Z[6, 7] (7CI92) 10 10 15 ns
tADv Data Valid to Output Valid (7C191) 20 30 35 ns
Notes:
reference levels of 1.5V, input pulse levels ofOV to 3.0V and output CE LOW and WE LOW. Both signals must be LOW to initiate a
6. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb. data input setup and hold timing should be referenced to the rising
for any given device. 10. Device is continuously selected. CE = VIL.
Switching Waveforms
AOOR ... ----J;14--_-_-_-_-_-_-_-_-_-_tRC=======~~~--.I*___

---{
... -I----tOHA---~
0108-1
2-224
rm
...
~ ~~~UaoR==================================================================
PRELIMINAR Y
CY7C191
CY7C192

tRC
)r , J'f-
DATA OUT
HIGH IMPEDANCE
tACE
I" .
, , L LY
I' , , , ,
-I
i
DATA VALID
Hx'1 HIGH
IMPEDANCE
1 tLZCE
1\ 1
- J
f4>---tpu -tPD
----j ICC
VceY _ _ _ _ _
SUPPL
CURRENT _
50"10
=t='SB 0108-7
-- 1t
twc "
ADDRESS ~t
L
tSCE
\\ .\\~ -,:1 I I I :1 I I I I I I II
tAW t HA -
tSA
", - tpWE -
~\""'-'t -,~
tso " I tHO

DATA IN ~t- DATA-IN VALID I:
DATA OUT
- t HZWE.:1 '\I
~tLZWE
HIGH IMPEDANCE II'
DATA UNDEFINED
(7C192) 11 ~
e-- tAOV-
DATAOUT--------------DA-T-A-U-N-DE-F-IN-E-D-----------I----------D~A~T-A-V~AL~ID~--------
(7C191) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ....J~
0108-8
ADDRESS -- Jt twc
.
"
J~
tSA t SCE -
~ 1~
tAW - tHA -
~tpWE-
\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \)t- -,~I I I I ILULllll

tso .1 tHO

I
DATA IN I: DATA-IN VALID
r- tHzwE-1
DATA OUT '\I HIGH IMPEDANCE
DATA UNDEFINED
(7C192) II
- tAWE -
(7C191) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....,j)K
DATAOUT--------------DA-T-A-U-N-DE-F-IN-E-D------------------1---DA-T-A-V-AL-ID-----
Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C192 only). 0108-9
2-225
CY7C191
(in
.. PRELIMINARY CY7C192
~NDU~================================================================
CY7C191-25VC V21 CY7C192-25VC V21
CY7C191-250C 022 CY7C192-250C 022
CY7C191-25LC L54 CY7C 192-25LC L54
CY7C191-35VC V21 CY7C192-35VC V21
CY7C191-350C 022 CY7Cl92-350C 022
CY7C191-35LC L54 CY7C192-35LC L54
CY7C191-350MB 022 Military CY7Cl92-350MB 022 Military
CY7C191-45VC V21 CY7C192-45VC V21
CY7C191-450C 022 CY7C192-450C 022
CY7C191-45LC L54 CY7C192-45LC L54
CY7C191-450MB 022 Military CY7Cl92-450MB 022 Military
2-226
CY7C191
(;Ii~OOUaoR==============================================================
DC Characteristics
Parameters
VOH
VOL
VIH
VILMax.
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3

IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
ISBI 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
tAWE[l] 7,8,9,10,11
tADV[l] 7,8,9,10,11
Note:
1. 7C191 only.
Document #: 38-00076-A
2-227
CY7C194
PRELIMINARY CY7C196
CYPRESS
Features
Automatic power-down when Capable of withstanding greater CY7C194, CEI, CE2 on the CY7C196)
deselected than 2001V electrostatic and write enable (WE) inputs are both
Output Enable (OE) feature discharge LOW. Data on the four input pins
(7C196) (1/00 through 1/03) is written into the
Functional Description memory location, specified on the ad-
CMOS for optimum speed/ dress pins (Ao through AIS).
power The CY7C194 and CY7C196 are high
performance CMOS static RAMs orga- Reading the device is accomplished by
High speed nized as 65,536 x 4 bits. Easy memory taking the chip enable(s) (CE on the
- 25 ns tAA expansion is provided by active LOW CY7C194, CEI, CE2 on the CY7C196)
Low active power ~ enable(s) (CE on the CY7C194, LOW, while write enable (WE) re-
-385mW CE}, CE2 on the CY7C196) and three- mains HIGH. Under these conditions
state drivers. They have an automatic the contents of the memory location
Low standby power power-down feature, reducing the pow- specified on the address pins will ap-
-110 mW er consumption by 71 % when deselect- pear on the four data output pins. A
TTL compatible inputs and ed. die coat is used to insure alpha immu-
outputs Writing to the device is accomplished nity.
when the chip enable(s) (CE on the

VCC VCC
A5 A5
A4 A4
A9 A3
A9 A2
A 10 A2
A 10 AI
AI
Ao
Ao
NC
A 13 1/3
1/2
CE2
A14 1/3
1/1 A 15 1/2
GND
1/0
WE
cr, 1/01
OE 1/0
GND WE
0109-2
0109-3
110,
...... u tlu
-z>% .t'~~.R
1/0 0
3 2 1 2827 3 2 1 2827
A8 4 26 .0.5 .0.8 26 A4
.0.9 5 25 A4 Ag 25 A3
_ _ _ _~ ~2(7CI960NLY)
A 10 6 24 A3 A 10 6 24 A2
a:, All 7 23 .0. 2 All 7 23 AI
7C194 7C196
A12 8 22 AI A12 8 22 Ao
A13 9 21 Ao A 13 9 21 NC
WE)
_ _- ( t i E
CE2
A14 10 20 1/3 A14 10 20
(7C196 ONLY) A 15 11 19 A15 11 19 1/3
1/2
CE 12 18 1/1 CE1 12 18 1/2
0109-1 1314151617
I:::~I~~~
0109-11 0109-12
Selection Guide
7C194-25 7C194-35 7C194-45
7C19625 7C196-35 7C196-45
2-228
CY7C194
~RSS PRELIMINARY CY7C196

WnICONDUCTOR =======================================================================
Maximum Ratings
Storage Temperature ............... - 65C to + 150C
Supply Voltage to Ground Potential .... -0.5V to + 7.0V
DC Input Voltage .... , .............. -3.0V to + 7.0V
Static Discharge Voltage ..................... > 2001 V
Latch-up Current .......................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
OCto + 70C
Vee
5V 10%

Output Current into Outputs (Low) ............. 20 mA Military[3] - 55C to + 125C 5V 10%

7C19425 7C19435 7C19445
Parameters Description Test Conditions 7C19625 7C19635 7C19645 Units
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 2.4 2.4 V
IIX Input Load Current GND:;;: VI:;;: Vee -10 +10 -10 +10 -10 +10 fJ-A
IOZ Output Leakage Current GND :;;: Vo :;;: Vee, Output Disabled -10 +10 -10 +10 -10 +10 fJ-A
los Current[1] Vee = Max., VOUT = GND -350 -350 -350 mA
Vcc Operating Vee = Max. Commercial 80 80 70

Icc mA
Automatic CE[2] Max. Vee, CE ~ VIH Commercial 20 20 20
ISB} mA
Automatic CE[2] CE ~ Vee - 0.3V
ISB2 Power Down Current VIN ~ Vee -0.3Vor rnA
VIN:::;: 0.3V Military 20 20
Capacitance [5]
Vee = 5.0V pF
Notes:
device deselected during Vee power-up, otherwise ISB will exceed S. Tested initially and after any design or process changes that may

Rl481l! R1481l! 3.0V----~~--~L
5 V 0 - - - - , . . , . "........-. 5 V Q----"V',."...-,
OUTPUT 0--_---.. OUTPUT 0--_.---1
GND
30 pF R2 5 pF R2
I_
-
INCLUDING
JIGAND _
SCOPE -
255!l
I INCLUDING
_JIG AND
- SCOPE
_
-
255l!
0109-4 Figure 2
0109-5
Figure 1a Figure 1b

16m
OUTPUT O---~ .."..~--o 1.73 V
..,.., 0109-6
2-229
CY7C194
5A~~~============================================================
. PRELIMINAR Y CY7C196

7C19425 7C194-35 7C19445
Parameters Description 7C19625 7C196-35 7C19645 Units
READ CYCLE
tACE1,ACq CE LOW to Data Valid 25 35 45 ns
tDOE OE LOW to Data Valid 7CI96 15 25 30 ns

tLzOE OE LOW to LOW Z 7CI96 3 3 3 ns
tHZOE OE HIGH to HIGH Z 7CI96 15 15 15 ns
tLZCE1,Cq CE LOW to LOW Z[8] 3 3 3 ns
tHZCE1,Cq CE HIGH to High Z[7, 8] 10 15 15 ns

WRITE CYCLE[9]
tLZWE WE HIGH to LOW Z[8] 3 3 3 ns
tHZWE WE LOW to HIGH Z[7, 8] 0 10 0 10 0 15 ns
Notes:
reference levels of 1. 5V, input pulse levels of 0 to 3.0V and output CEI LOW, CE2 LOW and WE LOW. Both signals must be LOW to
loading of the specified lor/IOH and 30 pF load capacitance. initiate a write and either signal can terminate a write by going
7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb. HIGH. The data input setup and hold timing should be referenced to
Transition is measured 500 mV from steady state voltage. the rising edge of the signal that terminates the write.
8. At any given temperature and voltage condition, tHZCE is less than 10. WE is HIGH for read cycle.
tLZCE for any given device. 11. Device is continuous~elected, CEI = VlrJCE2 = VIL.
(7C196: OE = VIL, CE2 = VILalso.)
12. Address valid prior to or coincident with CEI and CE2 transition
LOW.
13. 7C196 only: Data I/O will be high impedance ifOE = VIR.
Switching Waveforms
=i
ADDRESS
~-------------------------tRC--------------------------*
_ _ _ _
DATA OUT ____I4~~~~_-:_-_to_H_A.~~~~t_A-A=_..

PREVIOUS DATA VALID
.' DATA VALID
----------------------------------- 0109-;
2230
CY7C194
fill .
~UcroR =====================================================================
PRELIMINARY CY7C196

tRC
~1/~2 ~~
tAcE
-l- fI
OE
~r
L
(7C196)
I\.
tooE
I---tlZOEi
'"'o,~
f.-tHZCE~
HIGH
HIGH IMPEDANCE If / / / / IJ IMPEDANCE
DATA OUT DATA VALID
-1 I"'"
IlZCE /
!+-IPU i-tpo
Vce _ _ _ _ _ _
SUPPLY 50%
CURRENT ___
0109-8

~-----------------------------twc----------------------------~
ADDRESS
t-------------------- ISCE----------------------..j
~1/~2
~-----------------------tAW----------------------~~---
.....--------tsA-------------..I ~-------tME------~~
I-.....!...----tso------I-_
tHZWE~
DATA 1/0 ----------D-A-T-A-U-N-DE-F-IN-E-D------- )).--...;.;.;.;.;~;;..;;.;;.;.;;.;;.;.;;._ _~ _ _ _ _ _ __
0109-9

~---------------------------IWC----------------------------~
---------If------------ IseE ------------1
~-----IME-------~
t - - 4 - - - - - - - - lso'------l1--
DATA-IN VALID
tHZWE---!
------------------~ HIGH IMPEDANCE
DATA I/O DATA UNDEFINED J)o-----------;....;..;.;.;;.;;......;.;.~------
Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 0109-10
2-231
CY7C194
5Ji~~U~R==================================================================

CE WE Input/Outputs Mode CEl CE2 WE OE Inputs/Outputs Mode
H X HighZ Deselect/Power Down H X X X
HighZ Deselect/Power Down
L H Data Out Read X H X X
L L Data In Write L L H L Data Out Read
L L L X Data In Write
L L H H HighZ Deselect
Spee4 Package Operating Speed Package Operating
CY7C194-25VC V13 CY7C196-25VC V21
CY7C194-25DC D14 CY7C196-25DC D22
CY7C194-25LC L54 CY7C196-25LC L54
CY7C194-35VC V13 CY7C196-35VC V21
CY7C194-35DC D14 CY7C196-35DC D22
CY7C194-35LC L54 CY7C196-35LC L54
CY7C194-45VC V13 CY7C196-45VC V21
CY7C194-45DC D14 CY7C196-45DC D22
CY7C194-45LC L54 CY7C196-45LC L54
CY7CI94-45LMB L54 CY7C196-45LMB L54
2-232
CY7C194
~CfPRESS PRELIMINARY CY7C196
~~~CO~UcroR~==============================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
til
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACEl,ACE2 7,8,9,10,11
tDOE[l] 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tpwE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
tAWE 7,8,9,10,11
tADv 7,8,9,10,11
Note:
1. 7C196 only.
2-233
PRELIMINARY CY7C197
CYPRESS
SEMICONDUCTOR 262,144 x 1 Static R/W RAM
Automatic powerdown when The CY7C197 is a high performance Reading the device is accomplished by
262,144 words x 1 bit. Easy memory while write enable (WE) remains
power expansion is provided by an active HIGH. Under these conditions the
LOW chip enable (CE) and three-state contents of the memory location speci-
High speed-25 ns drivers. The CY7C197 has an automat- fied on the address pins will appear on
Low active power-330 mW ic power-down feature, reducing the the data output (DOUT) pin.
power consumption by 67% when de- The output pin stays in high impedance
Low standby power-110 mW selected. state when chip enable (CE) is HIGH
TIL compatible inputs and Writing to the device is accomplished or write enable (WE) is LOW.
outputs when the chip enable (CE) and write The 7C197 utilizes a Die Coat to en-
Capable of withstanding greater enable (WE) inputs are both LOW. sure alpha immunity.
than 2001 V electrostatic Data on the input pin (DIN) is written
discharge into the memory location specified on
the address pins (Ao through A17).

r - - - - - - - - - < 1------ 01 Ao Vee
Al A17
A2 A1S
A3 A15
A13
A4 A14
A14
As A13
A15
As A12
A16
A7 A"
A17
AS A l0
Ao DO DOUT Ag
Al
WE DtN
A2
GND CE
A3
A4 0110-2
u ....
<'< ~~<
NC Ne
A1S
WE
A15
A14
Au
A12
0110-1
All
Al o
NC
I~ ~I~
(!)
~~
0110-11
Selection Guide
7C19725 7C19735 7C19745
Time (ns) Military 3S 45
Maximum Standby Commercial 20/20 20/20 20/20
Current (mA) Military 20/20 20/20
2-234
~~~NDUcroR ==================================================================~
Maximum Ratings

Storage Temperature ............... -65C to + 150C Static Discharge Voltage ............ , ........ > 2001V
(Pin 24 to Pin 12) .................... -0.5Vto +7.0V
Range VCC

7C19725 7C19735 7C19745
VOH Output HIGH Voltage Vee = Min., 10H = -4.0mA 2.4 2.4 2.4 V
VOL Output LOW Voltage Vee = Min. I IOL = S.OmA Military 0.4 0.4 0.4 V
IIOL = 12.0 rnA Commercial
VIL Input LOW Voltage -3.0 O.S -3.0 O.S -3.0 O.S V
IIX Input Load Current GND:S:: VI:S:: Vee -10 +10 -10 +10 -10 +10 p.A
loz Output Leakage Current GND :S:: Vo :S:: Vee, Output Disabled -50 +50 -50 +50 -50 +50 p.A
los Current[l] Vee = Max., VOUT = GND -350 -350 -350 rnA

lee rnA
Supply Current lOUT = OmA Military so SO
Automatic CE[2] Max. Vee, Commercial 20 20 20
ISBl rnA
Power Down Current CE ~ VIR Military 20 20
Automatic CE[2] Max. Vee, CE ~ Vee - 0.3V, Commercial 20 20 20

rnA
ISB2 VIN ~ Vee - 0.3Vor
Power Down Current Military 20 20
VIN s: 0.3V
Capacitance [3]
pF
COUT
Notes:
2. A pull-up resistor to Vee on the CE input is required to keep the 4. TA is the "instant on" case temperature.
device deselected during Vee power-up, otherwise ISB will exceed S. See the last page of this specification for Group A subgroup testing
Rl 329.0 R1329n 3.0 V -----J~~---~
(480.0 MIL) (480.0 MIL)
5 V O-----.J\oM..--. 5Vo-----JV~~
GND
OUTPUT 0-----1~--....... OUTPUT 0 - - - _......- -.......
<;; 5 ns -<;; 5 ns
R2 0110-4
R2
INCLUDINGI30 pF
202.0 5pF 202.0 Figure 2
(255.0 MIL) INCLUDINGf" (2550 MIL)
JIG AND
SCOPE JIG AND
SCOPE ~
.L
0110-3
Figure la Figure lb
Equivalent to: THEVENIN EQUIVALENT 1670
OUTPUT~1.73V
1250
OUTPUT O---..."""..,,"'r----O 1.90 V
0110-5
Military 0110-6
Commercial
2-235
~~~NDUcrOR =====================================================================
Switching Characteristics Over Operating Range[S, 61
7C19725 7C19735 7C19745
READ CYCLE
toHA Output Hold from Address Change 3 3 3 ns
tLZCE CE LOW to Low ZIS] 3 3 3 ns
tHZCE CE HIGH to High Z(7, s] 0 15 0 20 0 20 ns
WRITE CYCLE(9]
tAw Address Set-up to Write End 20 30 40 ns
tLZWE WE HIGH to Low Z(S] 0 0 0 ns
tHzwE WE LOW to High Z(7, S] 0 15 0 20 0 20 ns
Notes:
loading of the specified 10UlOH and 30 pF load capacitance. write and either signal can terminate a write by going HIGH. The
7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb. data input setup and hold timing should be referenced to the rising
Transition is measured 500 m V from steady state voltage. edge of the signal that terminates the write.
S. At any given temperature and voltage condition, tHZCE is less than 10. WE is HIGH for read cycle.
tLZCE for any given device. 11. Device is continuously selected, CE = VIL.
Switching Waveforms
Read Cycle No. 1[10,111
0110-7
2-236
~~~NDUcrOR =====================================================================
Read Cycle No. 2[11]
tRC
J \
tAce .
-,1{.
I til
tLzce~ -tHzce1
HIGH
IMPEDANCE
HIGH IMPEDANCE 1/ / / / / "
DATA OUT DATA VALID
1 1""'1\. J
!+--tpu -tpo
Vcc _ _ _ _ _ _
SUPPLY
CURRENT _
50% so;,t==
-----1 ICC
IS8
0110-8

~-------------------------------twc----------------------------~~
ADDRESS
t------------tsce-----------------~~
t------------------------tAW-------------------------.t----
)4----------tsA-----------~ t-----t~E-----~
~---'--------tso ----------I~-
tHzwe-+j tLZwe-!
DATA OUT -------------------------------------------------~~
DATA UNDEFINED !"______H_I_G_H_IM_P_E_D_A_N_C_E_____-<I~:~~~~~~~~~~~~~=
'-
0110-9
Write Cycle No.2 (CE Controlled)[lO]

t-----------------------------~c----------------------------~
ADDRESS
t--------- tsA--------_+-------------tsce----------.j
~------------------tAW----------------~t--
~------t~e------------~
f+--+-------------tso----__e.....-
tHzwe---l
DATA OUT
--------------------------------------~
DATA UNDEFINED
HIGH IMPEDANCE
I~--------------------------------------------
0110-10
2-237
~~~~==============================================================
Truth Table
CE WE Input/Outputs Mode
H X HighZ DeselectlPower Down
L H Data Out Read
L L Data In Write
Ordering Code
(ns) Type Range
25 CY7C197-25PC Pl3 Commercial
CY7C197-25VC V13
CY7C197-25DC D14
CY7C197-25LC L54
CY7C197-35VC V13
CY7C197-35DC D14
CY7C197-35LC L54
CY7CI97-35LMB L54
CY7C197-45VC V13
CY7C197-45DC D14
CY7CI97-45LC L54
CY7CI97-45LMB L54
2-238
~~~~============================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
Ell
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
ISBI 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
Document #:: 38-00078-A
2-239
CY7C198
PRELIMINARY CY7C199
CYPRESS
SEMICONDUCTOR 32,768 x 8 Static R/W RAM
Automatic power-down when The CY7C198 and CY7C199 are high the eight data input/output pins (1/00
deselected performance CMOS static RAMs orga- through 1/07) is written into the mem-
nized as 32,768 words by 8 bits. Easy ory location addressed by the address
power memory expansion is provided by an present on the address pins (Ao
active LOW chip enable (CE) and ac- through A14). Reading the device is ac-
High speed-35 ns tive LOW output enable (OE) and complished by selecting the device and
Low active power-550 mW three-state drivers. Both devices have enabling the outputs, CE and OE ac-
an automatic power-down feature, re- tive LOW, while (WE) remains inac-
Low standby power-110 mW ducing the power consumption by 80% tive or HIGH. Under these conditions,
TTL compatible inputs and when deselected. The CY7C199 is in the contents of the location addressed
outputs the space saving 300 mil wide DIP by the information on address pins is
package and leadless chip carrier. The present on the eight data input/output
CY7C198 is in the standard 600 mil pins.
wide package. The input/output pins remain in a high
discharge
An active LOW write enable signal impedance state unless the chip is se-
(WE) controls the writing/reading op- lected, outputs are enabled, and write
eration of the memory. When CE and enable (WE) is HIGH. A die coat is
WE inputs are both LOW, data on used to ensure alpha immunity.
A6
A7
"8
"9
A'0
"11
A'2
"13
A'4
>-I-++-t-t-4~-1/02 1/00 11
1/1
1/2
GND
0111-2
3212827
As 4 26 A.
A9 5 25 A3
A'0 6 24 "2
Al1 7 23 A,
A'2 22 6E
"13 21 Ao
A14 10 20 cr
1/0 11 19 1/7
6E----.._ _ 1/0 , 12 18 1/6
1314151617
0111-1 Ne to') .... 10
~t5~~~ 0111-11
Selection Guide
7C198-35 7C198-45 7C198-55
7C199-35 7C199-45 7C199-55
Maximum Standby Commercial 20/20 20/20 20/20
Current (rnA) Military 20/20 20/20
2-240
CY7C198
5Ii ~~~UcrOR=====================================================================
Maximum Ratings
PRELIMINARY CY7C199
Ambient Temperature with (Per MIL-STD-883 Method 3015) ~
Power Applied .................... - 55C to + 125C Latch-up Current .......................... > 200 rnA ~
(Pin 28 to Pin 14) .................... -0.5V to + 7.0V
Operating Range
Range Temperature Vee
in High Z State ...................... -0.5V to + 7.0V
DC Input Voltage ................... -3.0Vto +7.0V Commercial OCto + 70C 5V 1O%

7C198-35 7C198-45 7C198-55
7C19935 7C19945 7C19955
IIX Input Load Current GND ~ VI ~ Vee -10 10 -10 10 -10 + 10 ,..,A
loz Output Leakage Current GND ~ VI ~ Vee -10 +10 -10 +10 -10 +10 ,..,A
Output Disabled
Output Short Circuit -300 -300 -300
lOS Current[l] Vee = Max., VOUT = GND rnA
Vee Operating Vee = Max. Commercial 110 110 100 rnA
lee Supply Current lOUT = OmA Military 120 120
Automatic CE CE:<: VIH, rnA
IISBI Power Down Current Min. Duty
Cycle = 100% Military 20 20

ISB2 Automatic CE CE:<: Vee - 0.3V, rnA
Power Down Current VIN:<: Vee - 0.3Vor
VIN ~ 0.3V Military 20 20
Capacitance [2]
pF
Notes:

5 V o------'w';,-~ 5 V O----~"r-..,
OUTPUTo--_----t OUTPUT 0--_---.... 3.0V----j~~--oi.
30 pF R2 5 pF R2 GND
I INCLUDING
_JIG AND _
- SCOPE -
255n
I-:~~:~D ':'
INCLUDING
255n
0111-5
0111-3 0111-4 Figure 2
Figure la Figure lb
16m
OUTPUT O---'""",,"tr.- -.... 01.73 V
0111-6
2-241
CY7C198
511 .
~UcrOR==================================================================
PRELIMINARY CY7C199
7C19835 7C19845 7C19855

Parameters Description 7C19935 7C19945 7CI9955 Units
READ CYCLE
toHA Data Hold from Address Change 3 3 3 ns

tAcE CE LOW to Data Valid 35 45 55 ns

WRITE CYCLErS]

tHzwE WE LOW to High Z[6] 15 20 25 ns
Notes:
reference levels of 1.5V, input levels of 0 to 3.0V and output loading data input setup and hold timing should be referenced to the rising
of the specified loI/loH and 30 pF load capacitance. edge of the signal that terminates the write.
6. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure 9. WE is HIGH for read cycle.
1b. Transition is measured 500 mV from steady state voltage. to. Device is continuously selected. OE, CE = VIL.
tLZCE for any given device. 12. Data I/O is high impedance ifOE = VIR.
CE LOW and WE LOW. Both signals must be LOW to initiate a
Switching Waveforms
~t:~~-------------------------tRc---------------------------1~~
DATA OUT
~I_:~~~~~~~~~H~A~~~~-t_A~A-_-.'------------.-'--------------____________~-----------------
ADDR' _______
--------------------------------------- 0111-7
2-242
CY7C198
WA .
~NDUcroR =====================================================================

t RC
~ ...
t ACE
J til
-'1\ T
j 4 - tOOE - t HZOE -
DATA OUT
t LZOE
HIGH
IMPEDANCE / /
DATA VALID
tHZCE
- HIGH
IMPEDANCE
'\
~tLZCE-
SUP~~~ ~~-5-0%-.---------------------------------------5~:~
I- tpu -tpo
_________
CURRENT
0111-8
twc I
ADDRESS - -l
~~
.1" tSCE I
\\ ,\\~ . ,i-I I I I VIIIIIII/

tAW t HA -
tSA "I - tpWE -
~\ \ 1\ ..,~
tso I tHO
DATA IN i DATA-IN VALID )l
I - tHZWEj -tLZWE-1
'\I HIGH IMPEDANCE I#'
DATA I/O DATA UNDEFINED II
'"
0111-9

~----------------------twc-------------------I
ADDRESS
---'I~-----------------------------------------I'~----------
~---------tSA----------~----

------------------------_I~----------------'I~--------------
HIGH IMPEDANCE
DATA I/o DATA UNDEFINED
----------------------------------~ 0111-10
Note: IfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-243
CY7C198
5Jl~U~ ================================================================
.
Truth Table
CE WE OE Input/Outputs Mode
H X X HighZ Deselect Power Down
L H L Data Out Read
L L X Data In Write
35 CY7C 198-35PC P15 Commercial 35 CY7C199-35PC P21 Commercial
CY7C198-35DC D16 CY7C199-35VC V21
45 CY7C198-45PC P15 Commercial CY7C199-35DC D22
CY7C198-45DC D16 CY7C199-35LC L54
CY7CI98-45DMB D16 Military 45 CY7C199-45PC P21 Commercial
55 CY7C198-55PC P15 Commercial CY7C199-45VC V21
CY7C198-55DC D16 CY7C199-45DC D22
CY7CI98-55DMB D16 Military CY7C199-45LC L54
CY7CI99-45LMB L54
CY7C199-55VC V21
CY7C199-55DC D22
CY7C199-55LC L54
CY7CI99-55LMB L54
2-244
CY7C198
(in
-.. PRELIMINARY CY7C199
~ ~~UaoR================================================================
DC Characteristics
Parameters
VOH
Subgroups
1,2,3
fI
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
loS 1,2,3
Icc 1,2,3
ISBl 1,2,3
ISB2 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tOHA 7,8,9,10,11
tACE 7,8,9,10,11
tDOE 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSCE 7,8,9,10,11
tAW 7,8,9,10,11
tHA 7,8,9,10,11
tSA 7,8,9,10,11
tPWE 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
2-245
CY74S189, CY27LS03
CY27S03, CY27S07
CYPRESS
Fully decoded, 16 word x 4-bit These devices are high performance insures minimum write recovery times
high speed CMOS RAMs 64-bit static RAMs organized as 16 by eliminating the "write recovery
Inverting outputs 27S03, words x 4-bits. Easy memory expan- glitch".
27LS03,74S189 sion is Evided by an active LOW chip Reading is accomplished with an active
select (CS) input and three-state out- LOW on the chip select line (CS) and a
Non-inverting outputs 27S07 puts. The devices are provided with in- HIGH on the write enable (WE) line.
High speed verting and non-inverting outputs. The information stored is read out
-25 ns
An active LOW write enable (WE) sig- from the addressed location and pre-
Low power nal controls the writing and reading of sented at the outputs in inverted or
- 210 mW (27LS03) the memory. When the write enable non-inverted format.
Power supply 5V 10% (WE) and chip select (CS) are both During the write operation or when the
Advanced high speed CMOS LOW the information on the four data chip select line is HIGH the four out-
processing for optimum speed/ inputs (00-03) is written into the lo- puts of the memory go to an inactive
power product cation addressed by the information on high impedance state.
the address lines (Ao-A3). The outputs
Capable of withstanding greater are preconditioned such that the cor-
than 2001 V static discharge rect data is present at the data outputs
Three-state outputs (00-03) when the write cycle is com-
TTL compatible interface levels plete. This preconditioning operation
Logic Block Diagrams Pin Configurations

27S07
27S03, (27S03, 27LS03, 74S189)
27LS03, 74S189 27S07
.-------<1- 0 0 Do Ao Vee
CS A,
- - " ' .... 0, 0,
WE A2
02 Do A3
(001 0 0 03
03
0, 03 (031
(0,10, 02
00 00 GND 02 (021
0, 0006-3
DIP
02 Top View
03 CS Ao He Vee A,
0006-1 0006-2
He GHO He Oz{!JV O2 0006-10

LCC
Top View
Selection Guide (For higher performance and lower power refer to CY7C189/90 data sheet.)
27S03A 27S03,27S07
27LS03
27S07A 74S189
Maximum Access Time (ns) Commercial 25 35
Military 25 35 65
Maximum Operating Current (rnA) Commercial 90 90
Military 100 100 38
2-246
CY74S189, CY27LS03
fill~U~==================================================================
. CY27S03, CY27S07
Maximum Ratings
Storage Temperature ....... , ....... -65C to + 150C Static Discharge Voltage ..................... >2001 V
Power applied ..................... - 55C to + 125C Latchup Current .......................... > 200 mA
(Pin 16 to 8) ........................ -0.5V to + 7.0V
Operating Range
DC Voltage Applied to Outputs Range Ambient
Temperature Vee
Commercial OC to + 70C 5V 10%
DC Input Voltage ................... -3.0V to +7.0V
Military [5] - 55C to + 125C 5V 10%

74S189,
27LS03
Parameters Description Test Conditions 27S03,27S07 Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = - 5.2 mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 16.0 mA 0.45 V
Vee = Min., IOL = 8.0 mA 0.45 V
VIR Input HIGH Voltage 2.0 Vee 2.0 Vee V
IIX Input Leakage Current GND::;; VI::;; Vee -10 +10 -10 +10 p,A
VeD \ Input Diode Clamp Voltage[1]
loz \ Output Leakage Current GND::;; Vo::;; Vee -40 +40 -40 +40 p,A
los Output Short Circuit Current [2] Vee = Max., VOUT = GND -90 -90 mA
lee
\
Power Supply Current
Vee = Max., I Commercial 90 mA
lOUT = OmA I Military 100 38 mA
Capacitance [4]
pF
Notes:
1. The eMOS process does not provide a clamp diode. However these 4. Tested initially and after any design or process changes that may
devices are insensitive to - 3V dc input levels and - 5V undershoot affect these parameters.
pulses ofless than 5 ns (measured at 50% points). 5. TA is the "instant on" case temperature.
3. Output is precoditioned to data in (inverted or non-inverted) during
write to insure correct data is present on all outputs when write is
terminated. (No write recovery glitch.)
2-247
CY74S189, CY27LS03
5"A .
. ~okoUcrOR =====================================================================
Switching Characteristics Over the Operating Rangel6, 71
CY27S03, CY27S07
27S03A 27S03
748189 27LS03
Parameters Description 27807A 27807 Units
READ CYCLE
tAA Address to Data Valid[101 25 35 35 65 ns
tACS CS Low to Data Validl101 15 17 22 35 ns
tHZCS CS HIGH to High Z[9, 11, 121 15 20 17 35 ns
WRITE CYCLE[3, 7, 81
tscs CS Set-up to Write Start 0 ns
tHCS CS Hold from Write End 0 ns
tHzwE WE LOW to High Z[9, 11, 121 20 25 20 35 ns
tAWE WE HIGH to Output Valid[101 20 35 30 35 ns
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing 9. Transition is measured at steady state HIGH level -500 mV or
reference levels of 1.5 V, output loading of the specified IoUIOH and steady state LOW level + 500 mV on the output from 1.5V level on
30 pF load capacitance. the input.
8. The internal write time of the memory is defined by the overlap of CS 10. tAA, tACS and tAWE are tested with CL = 30 pF as in Figure 1a.
LOW and WE LOW. Both signals must be LOW to intiate a write Timing is referenced to 1.5V on the inputs and outputs.
and either signal can terminate a write by going HIGH. The data 11. tHZCS and tHzwE are tested with CL = 5 pF as in Figure lb.
input setup and hold timing should be referenced to the rising edge of 12. At any given temperature and voltage condition, tHZCS is less than
the signal that terminates the write. tLZCS for any given device.
BitMap 1~123012~11~123012~1: ~OLUMN

Address Designators
~ 111~ ~222 333~~'--------OUTPUTS Address Address Pin
Ao AXO 1
Al AXI 15
A2 AYO 14
A3 AYI 13
ROWO
ROW 3
0006-9
2-248
CY74S189, CY27LS03
5A~NDUcroR =====================================================================
. CY27S03, CY27S07

ALL INPUT PULSES

R12380 R12380
5 V 0------'''''',.."..--, 5 V o-----~--. 3.0 v-------ul"'!"!~---~
OUTPUTo----~------. OUTPUT 0 - - - -....- - -......

GND--;';';';'''!
R2 R2 .;;5n5 ,,;;5n5
30pF 5pF
I I
15012 150H
0006-6
,NCLUD,NG INCLUDING
JIG AND _ JIG AND _
':" SCOPE ':" - SCOPE -
0006-4
Figure la Figure lb

OUTPUT 0 VV\ 0 1.92V
9212
0006-5
Read Mode
~-------*----------x=
~------tRC-----------j~~
AD~~E~ _ _ _
~-~------tAA------~~!
cs
CHIP SELECT
DATA
OUTPUTS-----------~---~~~<
0
00- 3 ~~~__-------"~~r~------~~----~~~
NOTE 7
0006-7
Write Mode
~t~~--------------~C---------------~:j~,
AD~~E~ _ _ j _______ ~---
CS
CHIP SELECT
,
1\
tsA f4-- .... tHA
-- - tscs
Iso
.... tHCS
00-0 3
DATA IN J( ~
t tPWE tHO-=-!
WRITE ENABLE
WE -' r- ... ~
I. -tAwE
00~3 ~1~
tHZWE ~ NOTE 6
______________________
DATA OUTPUTS __
LOAD
LNOTE6
0006-8
(All above measurements referenced to 1.5V)
Note: Timing diagram represents one solution which results in optimum cycle time. Timing may be changed in various applications as long as the worst
case limits are not violated.
2-249
CY74S189, CY27LS03
(in~~~============================================================
CYPRESS CY27S03, CY27S07
Ordering Code
(ns) Type Range
25 CY27S03APC PI Commercial
CY27S07APC
CY27S03ADC 02
CY27S07ADC
CY27S03ALMB L61 Military
CY27S07 ALMB
CY27S03ADMB D2
CY27S07 ADMB
35 CY27S03PC PI Commercial
CY27S07PC
CY74S189PC
CY27S03DC 02
CY27S07DC
CY74S189DC
CY27S03LC L61
CY27S07LC
CY27S03LMB L6I Military
CY27S07LMB
CY27S03DMB D2
CY27S07DMB
65 CY27LS03LMB L6I Military
CY27LS03DMB D2
2-250
CY74S189, CY27LS03
fin CYPRESS CY27S03, CY27S07
S~~~============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
READ CYCLE
tRC 7,8,9,10,11
tAA 7,8,9,10,11
tACS 7,8,9,10,11
WRITE CYCLE
twc 7,8,9,10,11
tSA 7,8,9,10,11
tHA 7,8,9,10,11
tscs 7,8,9,10,11
tHCS 7,8,9,10,11
tSD 7,8,9,10,11
tHD 7,8,9,10,11
tPWE 7,8,9,10,11
tAwE 7,8,9,10,11
2-251
CY93422A/93L422A
CY93422/93L422
CYPRESS
256 x 4 static RAM for control The CY93422 is a high performance operation insures minimum write re-
stores in high speed computer CMOS static RAM organized as covery times by eliminating the "write
256 x 4 bits. Easy memory expansion is recovery glitch."
Processed with high speed
CMOS for optimum provided by an active LOW chip select Reading is performed with the chip se-
speed/power one (CSl) input, an active HIGH chip lect one (CSt) input LOW, the chip se-
select two (CS2) input, and three-state lect two input (CS2) and write enable
Separate inputs and outputs outputs. (WE) inputs HIGH, and the output en-
Low power An active LOW write enable input able input (OE) LOW. The information
- Standard power: (WE) controls the writing/reading op- stored in the addressed word is read
660 mW (commercial) eration of the memory. When the ~ out on the four non-inverting outputs
715 mW (military) select one (CSl) and write enable (WE) 00 to 03.
- Low power: inputs are LOW and the chip select
440 mW (commercial) The outputs of the memory go to an
two (CS2) input is HIGH, the informa- active high impedance state whenever
495 mW (military) tion on the four data inputs Do to D3 is chip select one (CSl) is HIGH, chip se-
5 volt power supply 10% written into the addressed memory lect two (CS2) is LOW, output enable
tolerance both commercial and word and the output circuitry is pre- (00) is HIGH, or during the writing
military conditioned so that the correct data is operation when write enable (WE) is
present at the outputs when the write LOW.
Capable of withstanding greater cycle is complete. This preconditioning
than 2001 V static discharge
0002-2
A2 WE
Al 25 CS 1
Ao 6 24 OE
As 23 CS 2
A6 22 03
0002-1 A7 9 21 D3
NC 10 20 2
NC 11 19 D2
NC 12 18 1
~~88c
~
0002-8
Selection Guide (For higher performance and lower power refer to CY7C122 data sheet)
93422A 93IA22A 93422 93IA22
Military 45 55 60 75
Military 130 90 130 90
2-252
e-z
'nrCONDucroR
CYPRESS
======================================================================
CY93422A/93L422A
CY93422/93L422
Maximum Ratings Function Table

(Above which the useful life may be impaired. For user

guidelines, not tested.) Inputs Outputs
Mode
Storage Temperature ............... -65C to + 150"C CS2 CSt WE OE Dn On
Ambient Temperature with L X X X X *HIGHZ Not Select
Supply Voltage to Ground Potential X H X X X *HIGHZ Not Select
(Pin 22 to Pin 8) ..................... -0.5V to + 7.0V H L H H X *HIGHZ Output Disable
DC Voltage Applied to Outputs Selected
for High Output State .............. -0.5V to Vee Max H L H L X Read Data
Data
DC Input Voltage ................... -0.5V to + 5.5V
H L L X L *HIGHZ Write "0"
DC Input Current ............... - 30 mA to + 5.0 mA H L L X H *HIGHZ Write "I"
Static Discharge Voltage ..................... > 200 1V H = High Voltage Level L = Low Voltage Level X = Don't Care
(per MIL-STD-883 Method 3015) "HIGH Z implies outputs are disabled or off. This condition is defined
as a high impedance state for the CY93422.
Latchup Current .......................... > 200 mA
Operating Range
Ambient
Range Vcc Temperature
Commercial SV 1O% OCto +7SoC
Military [6] SV 1O% - SsoC to + 12SoC
DC Electrical Characteristics Over Operating Range[S]

93422 93L422
Parameters Description Test Conditions 93422A 93L422A Units
Min. Max. Min. Max.
Vec = Min.,
VOH Output HIGH Voltage
VIN = VIH or VIL
IOH = -S.2mA 2.4 2.4 V
Vcc = Min.,
VOL Output LOW Voltage
VIN = VIH or VIL
IOL = S.OmA O.4S O.4S V
Guaranteed Input Logical HIGH

VIH Input HIGH Level[l] 2.1 2.1 V
Voltage for all Inputs
Guaranteed Input Logical LOW
VIL Input LOW Level[l] O.S O.S V
Voltage for all Inputs
IlL Input LOW Current Vcc = Max., VIN = 0.40V -300 -300 p.A
IIH Input HIGH Current VCC = Max., VIN = 4.SV 40 40 p.A
Output Short
Isc Circuit Current
Vee = Max., VOUT = 0.OV[2] -90 -90 rnA
TA = 12SoC 110 70
All Inputs = GND, TA = 7SoC 110 70
Icc Power Supply Current mA
Vee = Max. TA = OC 120 SO
TA = -SsoC 130 90
VCL Input Clamp Voltage See Note 4 See Note 4
VOUT = 2.4V SO SO
ICEX Output Leakage Current p.A
VOUT = O.SV, Vec = Max. -SO -SO
CIN Input Pin Capacitance See Note 3 4 4 pF
COUT Output Pin Capacitance See Note 3 7 7 pF
Notes:
1. These are absolute voltages with respect to device ground pin and 4. The CMOS process does not provide a clamp diode. However, the
include all overshoots due to system and/or tester noise. Do not at- CY93422 is insensitive to - 3V dc input levels and - 5V undershoot
tempt to test these values without suitable equipment. pulses ofless than 10 ns (measured at 50% point).
2. Not more than one output should be shorted at a time. Duration of 5. See the last page ofthis specification for Group A subgroup testing
the short circuit should not be more than one second. information.
2-253
CY93422A/93L422A
Wii .
. ~~u~================================================================
CY93422/93L422
Commercial Switching Characteristics vcc = 5V 10%, TA = aoc to + 75C (Unless Otherwise Noted)
93422A 93IA22A 93422 93IA22
tPLH(A)[l] Delay from Address to Output
35 45 45 60 ns
tpHL(A) [1] (Address Access Time) (See Figure 2)
tpZH (CSl, CS2) Delay from Chip Select to Active
25 30 30 35 ns
tPZL (CSl, CS2) Output and Correct Data (See Figure 2)
Delay from Write Enable to
tPZH(WE)
Active Output and Correct Data 25 40 40 45 ns
tPZL(WE)
(Write Recovery) (See Figure 1)
tPZH (OE) Delay from Output Enable to Active
25 30 30 35 ns
tpZL(OE) Output and Correct Data (See Figure 2)
Setup Time Address (Prior to
ts(A)
Initiation of Write) (See Figure 1)
5 5 10 10 ns
Hold Time Address (After

th (A) 5 5 5 5 ns
Termination of Write) (See Figure 1)
Setup Time Data Input (Prior to
ts (DI) 5 5 5 5 ns
Hold Time Data Input (After
th (DI) 5 5 5 5 ns
Setup Time Chip Select (prior to
ts (CS l, CS2) Initiation of Write) (See Figure 1)
5 5 5 5 ns
Hold Time Chip Select (After

th (CSl, CS2) 5 5 5 5 ns
Minimum Write Enable Pulse Width
tpw(WE) 20 40 30 45 ns
to Insure Write (See Figure 1)
tpHZ (CSl, CS2) Delay from Chip Select to Inactive
30 40 30 45 ns
tpLz (CSt. CS2) Output (HIGH Z) (See Figure 2)
tPHZ(WE) Delay from Write Enable to Inactive
Output (HIGH Z) (See Figure 1)
30 40 35 45 ns
tpLZ(WE)
tpHZ (OE) Delay from Output Enable to Inactive
30 40 30 45 ns
tpLz (OE) Output (HIGH Z) (See Figure 2)
Notes:
1. tpLH (A) and tpHL (A) are tested with SI closed and CL = 15 pF timing referenced to 1.5V. tpHZ (WE),tPHZ (CSt. CS2) and tpHZ
with both input and output timing referenced to 1.5V. (OE) are measured with SI open, CL S; 5 pF and are measured be-
2. tpZH (WE), tpZH (CSh CS2) and tpZH (OE) are measured with SI tween the 1.5V level on the input to the VOH - 500 m V level on the
open, CL = 15 pF and with both the input and output timing refer- output. tpLZ (WE), tpLZ (CSt. CS2) and tpLZ (OR) are measured with
enced to 1.5V. tPZL (WE), tPZL (CSh CS2) and tPZL (OE) are mea- SI closed and CL S; 5 pF and are measured between the 1.5V level on
sured with SI closed, CL = 15 pF and with both the input and output the input and the VOL + 500 m V level on the output.
2-254
CY93422A/93L422A
51]~UcrOR==================================================================
. CY93422/93L422
Military Switching Characteristics vcc = 5V 10%, TA = -55e to + 125e (Unless Otherwise Noted)[5]

93422A 93IA22A 93422 93IA22
tpLH(A) [1] Delay from Address to Output
45 55 60 75 ns
tPHL(A)[l] (Address Access Time) (See Figure 2)
tPZH (CSI. CS2) Delay from Chip Select to Active
35 40 45 45 ns
tPZL (CS 1. CS2) Output and Correct Data (See Figure 2)
Delay from Write Enable to
tPZH(WE)
Active Output and Correct Data 40 45 50 50 ns
tpZL(WE)
(Write Recovery) (See Figure 1)
tPZH (OE) Delay from Output Enable to Active
35 40 45 45 ns
tpZL(OE) Output and Correct Data (See Figure 2)
Setup Time Address (Prior to
ts (A) 5 10 10 10 ns
Hold Time Address (After
th (A) 5 5 5 10 ns
Setup Time Data Input (Prior to
ts (DI) 5 5 5 5 ns
Hold Time Data Input (After
th (DI) 5 5 5 5 ns
Setup Time Chip Select (Prior to
ts (CSl, CS2) 5 5 5 5 ns
Hold Time Chip Select (After
th (CSl, CS2) 5 5 5 10 ns
Minimum Write Enable Pulse Width
tpw(WE) 35 40 40 45 ns
to Insure Write (See Figure 1)
tPHZ (CSl, CS2) Delay from Chip Select to Inactive
35 40 45 45 ns
tpLZ (CSl, CS2) Output (HIGH Z) (See Figure 2)
tpHz(WE) Delay from Write Enable to Inactive
40 40 45 45 ns
tpLz(WE) Output (HIGH Z) (See Figure 1)
tpHZ (OE) Delay from Output Enable to Inactive
35 40 45 45 ns
tpLz(OE) Output (HIGH Z) (See Figure 2)
Notes:
1. tPLH (A) and tpHL (A) are tested with SI closed and CL = 15 pF timing referenced to 1.5V. tpHZ (WE), tpHZ (C81, CS2) and tpHZ
with both input and output timing referenced to 1.5V. (OE) are measured with SI open, CL ~ 5 pF and are measured be-
z. tpZH (WE), tPZH (CS J, CS2) and tPZH (OE) are measured with S1 tween the 1.5V level on the input to the VOH -500 mV level on the
output. tPLZ (WE), tpLZ (C8J, CS2) and tpLZ (OE) are measured with
open, CL = 15 pF and with both the input and output timing refer-
enced to 1.5V. tPZL (WE), tPZL (C8J, CS2) and tPZL (OE) are mea- SI closed and CL :::;; 5 pF and are measured between the 1.5V level on
sured with SI closed, CL = 15 pF and with both the input and output the input and the VOL + 500 mV level on the output.
2-255
CY93422A/93L422A
(in~NDU~================================================================
. CY93422/93L422
Switching Waveforms
Write Mode (with OE = Low) Key to Timing Diagram
CSl Waveform Inputs Outputs
CHIP
SELECT CS2 Must be Will be
steady steady
Ao-A7 ---+""'1IIa. Will be
ADDRESS
INPUTS _ _ _____________--J May change
changing
\\\\\\.
-
+
~
_
I
,
"
fromHtoL
fromHto L
~==tJ~~~!
Will be
DATA May change
Ox
INPUT
lII/JJ from LtoH
changing
from LtoH
we Don't care; Changing;
WRITE
ENABLE ~ any change state
permitted unknown
Does not Center line
Ox
DATA - -..........1+(
OUTPUT
H apply is high
impedance
tPZH (CSl CS2) tPHZ(CS1, CS2) 0002-4 "off" state
tPZL (CSl CS2) tPLZ(CS1, CS2)
0002-3
Figure 1
Read Mode
AD~~~~ --ADDRESS j - - + - - - - - - - - A D D R E S S k - - - - - - - - - I - - - - - - A D D R E S S i _ _ _ __ 1.5V
OEO
RCS
l ---w~----t-------------~~----~,------+-----------~------------- 1.5V
CS2 ___ J~--------~------------------JI\------~~------~----------~-------------
Ox
DA TA OUT _____.....,A,,&.I,jlool
'--r---' ~,-...,...-~ L...~~~~~~~ti~~!...., L...~~i~~~~~~--' '----,.------'

OUTPUT READ'A HIGH READ A LOW DISABLE ENABLE READ A HIGH DISABLE
DISABLED IN ADDRESS j IN ADDRESS k OUTPUT OUTPUT IN ADDRESS i OUTPUT
0002-5
Switching delays from address input, output enable input and the chip select inputs to the data output. The CY93422 disabled output in the "OFF"
condition is represented by a single center line.
Figure 2
AC Test Load and Waveform

ACTestLoad Input Pulses
Vee 0-----/0>---.., S1 3.0V

R1
600n 10%
GND
OUTPUT 0 - - - -.....- - - -.. <10n5
3.0V
90%
R2
1200 n
GND
0002-7
-= 0002-6
Figure 3 Figure 4
See Notes 1 and 2 of Switching Characteristics
2-256
CY93422A/93L422A
5A~ucr~================================================================
. CY93422/93L422
Speed Ordering Code Package Operating
(ns) Std. Power Low Power Type Range
35 CY93422APC P7 Commercial
CY93422ADC D8
CY93422ALC L54
45 CY93422PC CY93L422APC P7 Commercial
CY93422DC CY93L422ADC D8
CY93422LC CY93L422ALC L54
CY93422ADMB D8 Military
CY93422ALMB L54
55 CY93L422ADMB D8 Military
CY93L422ALMB L54
60 CY93422DMB D8 Military
CY93422LMB L54
CY93U22PC P7 Commercial
CY93L422DC D8
CY93U22LC L54
75 CY93L422DMB D8 Military
CY93U22LMB L54
2-257
CY93422A/93L422A
(in~~u~==================================================;=========
CYPRESS CY93422/93L422
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IlL 1,2,3
IIH 1,2,3
Icc 1,2,3
ICEX 1,2,3
tPLH(A) 7,8,9,10,11
tPHL(A) 7,8,9,10,11
tpZH ( CS h CS2) 7,8,9,10,11
tpZL (CS1. CS2) 7,8,9,10,11
tpZH(WE) 7,8,9,10,11
tPZL(WE) 7,8,9,10,11
tpzH (OE) 7,8,9,10,11
tPZL(OE) 7,8,9,10,11
ts(A) 7,8,9,10,11
th (A) 7,8,9,10,11
ts (01) 7,8,9,10,11
th (01) 7,8,9,10,11
ts (CSJ, CS2) 7,8,9,10,11
th (CS J, CS2) 7,8,9,10,11
tpw(WE) 7,8,9,10,11
2-258
PRELIMINARY CYM1420
CYPRESS
SEMICONDUCTOR 128K X 8 Static RAM
Module.
Features Functional Description through 1/07) is written into the memory
location specified on the address pins (Ao
High-density 1 Megabit SRAM Module The CYM1420 is a very high performance
through A, 6)' Reading the device is
High speed CMOS SRAMs 1 Megabit Static RAM module organized
accomplished by taking chip select (CS),
as 128K words by 8 bits. The module is
- Access time - 45 ns and output enable (OE) LOW, while write
constructed using four 32K x 8 Static
32 pin - 0.6 in. wide DIP package RAMs in Leadless Chip Carriers mounted enable (WE) remains inactive or HIGH.
JEDEC compatible pin-out onto a double sided multilayer ceramic Under these conditions, the contents of
substrate. A decoder is used to interpret the memory location specified on the
Low active power - 1.2 W (max)
the higher order addresses A,IS and A'6 address pins will appear on the eight data
Hermetic SMD Technology and select one of the four RAMs. input/output pins.
TTL compatible inputs and outputs The input/output pins remain in a high
Writing to the memory module is accom-
Commercial and Military plished when the chip select (CS) and impedance state unless the module is
Temperature Ranges write enable (WE) inputs are both LOW. selected, outputs are enabled, and write
2 V data retention (L version) Data on the eight input/output pins (lIOo enable (WE) is HIGH.
AO-A14--~~lS---------------r----------~ NC Vee
ot----------------~r--------.
A16 A1S
A14 NC
~----------------~~------~ A12 WE
A7 A13
As As
As Ag
A4 All
A3 DE'
A2 AlO
Al ~
Ao 1/0 7
1/0 0 1/6
A16 10f4 1/1 I/Os
Decoder 1/2 1/0 4
GND 1/0 3
DIP
~---------....I.---....I.-_r_- 1/00 - 1/07
1420-1 1420-2
Selection Guide
1420HD-45 1420HD-55
Maximum Access time (ns) 45 55
Commercial 210 210
Military 210 210
Commercial 80 80
Maximum Standby Current (mA)
Military 80 80
2-259
~PRRSS
WnEMICONDUcrOR
PRELIMINARY CYM1420
Maximum Ratings Operating Range

(Above which the useful life may be impaired) Ambient
Range
Temperature Vee
Storage Temperature ..................... -65C to + 150C
Commercial OOC to +70 o C SV 10%
Power Applied ......................... -55C to + 125C Military -55C to + 125C SV 10%
Supply Voltage to Ground Potential ....... " -O.sV to + 7.0V
in High Z State ........................... -O.sV to +7.0V
DC Input Voltage ........................ -O.sV to +7.0V
Output CUrrent into Outputs (Low) .................. 20 rnA

CYM1420HD
Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnA 2.4 V
VOL Output LOW Voltage Vee =. Min., IOL = 8.0 rnA 0.4 V
\lH Input HIGH Voltage 2.2 Vee V
\lL Input LOW Voltage -0.5 0.8 V
IIX Input Load CUrrent GND~Vi ~Vee -15 + 15 JJA
loz Output Leakage Current GND ~ Vo :::;; Vee, Output Disabled -15 + 15 JJA
los CUrrent (1] Vee = Max., Your = GND -300 rnA
Vee Operating Vee = Max., lour = OmA 210 rnA

Icc Supply CUrrent CS = VIL
Automatic CS [2] Max. Vee, CS ~ VIH,
IsBl 80 rnA
Power Down Current Min. Duty Cycle = 100%
Automatic CS [2] Max. Vee, CS ~ Vee - 0.3V,

IsB2 Power Down CUrrent VIN ~ \Ce - 0.3V or 80 rnA
VIN ~ 0.3V
Capacitance[3]
pF
Cour Output Capacitance Vee=S.OV 40
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. A pull-up resistor to Vee on the <:;S input is required to keep the device
short circuit should not exceed 30 seconds. deselected during \f:e power-up, otherwise ISB will exceed values
given.
3. Tested on a sample basis.

R1 4810 R1 4810 All Input Pulses
5V~ R2 5V~
3.0V-----
OUTPUT OUTPUT
. R2
1 30PF 2550 J 5pF _ 2550 GND---"I
~5ns
-- -- - -
INCLUDING INCLUDING
JIG AND JIG AND 1420-3 1420-4
SCOPE SCOPE
Equivalent to: THEVENIN EQDlVALENT
1670
OUTPUT C>----'vvv-<) 1.73V 1420-5
2-260
Q"'&1ooaa PRELIMINARY CYM1420
Switching Characteristics Over Operating Range [4]

1420HD-45 1420HD-55

Parameters Description Unit
Min. Max. Min. Max.
READ CYCLE
tACS CS LOW to Data Valid 45 55 ns
tLZOE "OELOWtoWWZ 5 5 ns
tHZOE OE HIGH to HIGH Z 20 25 ns
tLZCS CS LOW to Low Z[6] 5 5 ns
tHZCS CS HIGH to High Z [5, 6) 20 25 ns
tpu CS LOW to Power Up 0 0 ns
tpD CS HIGH to Power Down 45 55 ns
WRITE CYCLE (7)
!wc Write Cycle Time 45 55 ns

tscs CS LOW to Write End 40 45 ns
tpWE WE Pulse Width 2S 30 ns
tSD Data Set-up to Write End 20 2S ns
tLZWE WE HIGH to Low Z(6) 5 5 ns
tHZWE WE WW to High Z[5,6] 0 15 0 25 ns
~otes:
4.Test conditions assume signal transition times of 5 ns or less, timing 7.The internal write time of the memory is defined by the overlap ofrs
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified I OL /lOH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5.t HZCS and tHZWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
Transition is measured 500 mV from steady state voltage. signal that terminates the write.
6.At any given temperature and voltage condition t HZCS is less than 8.WE is HIGH for read cycle.
tLzcs for any given device. These parameters are guaranteed and not 9.Device is continuously selected, <::S = V1Land 00 = VIL"
100% tested.
1O.Address valid prior to or coincident with CS transition low.
l1.Data 110 will be high impedance if OE = VIH
2-261
6!!!~::~{P'USS PRELIMINARY CYM1420
_~ICONDUcrOR
Data Retention Characteristics (L Version Only)
CYM1420
Min. Max.
\bR Vee for Retention Data 2.0 V
IeeDR Data Retention Current Vee = 2.0V, 16 rnA
CS ;;;:: Vee - 0.2V
teDR(13) Chip Deselect to Data Retention Time 0 ns
\iN;;;:: \Ce - 0.2V
tR (13) Operation Recovery Time or \iN s: 0.2V tRe(12) ns
IU(13) Input Leakage Current 8 J.LA
Notes:
= Read Cycle Time.
12. tRC 13. Guaranteed, not tested.
Data Retention Waveform
DATA RETENTION MODE 1

tC:j:I
4.5V
.....---: ~
....._ _ _ _
'''''Z--Z-Z-Z'''''Z-~~-VIH--'------_-.J'
VO_R_~_2V_____
V
OR
~SVtR----.!
~ I
~H1\S SSS\
14208
Switching Waveforms (10)
=f=___--*-
Read Cycle No. 1[8,9)
RC
ADDRESS t
~ tOHA----;~
~===================D=A=T=A=V=A=LI=D================
DATA OUT
PREVIOUS DATA VAUO
1420-,
2-262
~PRESS
.nEMICONDUCTOR
PRELIMINARY CYM1420

Read Cycle No. 2[8, 10)
t RC
~
~
...:l~
tACS
...,~
....,IL
Ell
tOOE ~ t HZOE -
t LZOE t HZCS
DATA OUT
HIGH IMPEDANCE 11777 f II
~ \. \. \. \.
DATA VALID
, HIGH IMPEDANCE
~ t LZCS - "
~E--------~ri----ICC
14-- tpu
14-- tpD
Vee
SUPPLY
CURRENT
-------.:;f" 50% 50% I ' - - - 19B
1420-8
Write Cycle No.1 (WE Controlled) [7, 11)
ADDRESS -- -'f"
twc
~~
I
tscs
'\. '\.'\ '\.'\.'\.-T --, ~////
'/////////
tAW t HA -
tSA t PWE
1
WE ~'\. '\.~r- Ir....
I
tSD tHO
DATA IN ~E- DATA-IN VALID ~F

I--- t HZWE - tlZWE
HIGH IMPEDANCE
1420-9
Write Cycle No.2 (CS Controlled)!7, 11)
--
twc
ADDRESS -'
~ ~~
tSA tscs
T
-.~
-T
I tHA
tAW
tPWE
WE '\.'\.'\.'\."""'\.'\.'\.'\."~'\.'\.'\.'\.'\.~r- -.'f-// / / / / / / / / / / / /
L
I
tSD I tHO
DATA IN
*"I
DATA-IN VALID
- - t HZWE
*"I
HIGH IMPEDANCE
1420-10
2-263
...
(;n CYPRESS
SEMICONDUCTOR
PRELIMINARY CYM1420
Truth Table
CS WE OE Input/Outputs Mode
L H L Data Out Read
L L X Data In Write
Type Range
45 CYM1420HD-45C HD04
Commercial
CYM1420LHD-45C HD04
CYM1420HD-45MB HD04
Military
CYM1420LHD-45MB HD04
55 CYM1420HD-55C HD04
Commercial
CYM1420LHD-S5C HD04
CYM1420HD-5SMB HD04
Military
Document #: 38-M-OOOOI
2-264
CYM1421
CYPRESS
SEMICONDUCTOR 128K X 8 Static RAM I:I1II
Module ~
Features Functional Description through 1/07 ) is written into the memory
High-density 1 Megabit SRAM Module The CYM1421 is a high performance through AI6)' Reading the device is ___
High speed CMOS SRAMs 1 Megabit Static RAM module organized accomplished by ta~ chip select (CS),
as 128K words by 8 bits. The module is and oUte!!!....enable (OE) LOW, while write
- Access time - 70 ns constructed using four 32K x 8 Static enable (WE) remains inactive or HIGH.
32 pin - 0.6 in. wide DIP package RAMs in Leadless Chip Carriers mounted Under these conditions, the contents of
JEDEC compatible pin-out onto a double sided multilayer ceramic the memory location specified on the
Low active power - 660 m W (max) substrate. A decoder is used to interpret address pins will appear on the eight data
the higher order addresses AI!! and Al6 input/output pins.
Hermetic SMD Technology and select one of the four RAMs.
TTL compatible inputs and outputs The input/output pins remain in a high
Writing to the memory module is accom- impedance state unless the module is
Commercial and Military plished when the chip select (CS) and selected, outputs are enabled, and write
Temperature Ranges write enable (WE) inputs are both LOW. enable (WE) is HIGH.
2 V data retention (L version) Data on the eight input/output pins (110 0
AO-A14---~15~------~r------,
~--~~---------rr-------,
~-------------.+4------~
1 of 4
Decoder
DIP
1421-1 1421-2
Selection Guide
1421HD-70 1421HD-85
Maximum Access time (ns) 70 8S

Commercial 120 120
Military 120 120
Commercial 70 70
Military 70 70
2-265
~PFESS
WnMICONDUCTOR
CYM1421

Range
Temperature Vee
Ambient Temperature with Commercial OC to +70C SV 10%
Power Applied ......................... -55C to + 12SoC Military -55C to + 12SC SV 10%
Supply Voltage to Ground Potential. . . . . . . .. -0.3V to + 7.0V
in High Z State. . . . . . . . . .. . . . . . . . . . . . . . . .. -O.3V to + 7.0V
DC Input Voltage ........................ -0.3V to +7.0V
Output Current into Outputs (Low) .................. SO rnA

CYMl42lHD
Min. Max.
\iH Input HIGH Voltage 2.2 Vee V
\iL Input LOW Voltage -0.3 0.8 V
IIX Input Load Current GND:::;;;\1 :::;;;Vee -10 +10 J.lA
Ioz Output Leakage Current GND :::;;; Va :::;;; Vee, Output Disabled -10 +10 J.lA
Vee Operating Vee = Max., lOUT = 0 rnA 120 rnA
Ice Supply Current CS = VIL
Automatic CS (2) Max. Vee, CS ~ VIH, 70 rnA
IsB! Power Down Current Min. Duty Cycle = 100%
Max. Vee, CS ~ Vee - 0.2V,
Automatic CS (2)
IsB2 Power Down Current ~N ~ ~~~ - O.2V or 20 rnA
IN :::;;; O.
Capacitance(3)
CIN Input Capacitance TA = 2SC, f = 1 MHz 35
pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the 2. A pull-up resistor to Vee on the CS input is required to keep the device
short circuit should not exceed 30 seconds. deselected during \te power-up, otherwise ISB will exceed values
given.

5V~ R2 5V~ R2
3.0V-----
90%
OUTPUT OUTPUT
J 30pF _ 6670 J 5pF _ 6670 GND---"I

:::;;;5 ns
- - - -
INCLUDING INCLUDING
JIG AND JIG AND
SCOPE SCOPE 14213 1421-4
Figure la Figure lb Figure 2
4000
OUTPUT ()----v'I,v-() 2.0 V 1421-5
2-266
~~~ CYM1421

1421HD-70 1421HD-8S
Min. Max. Min. Max.
READ CYCLE
tLZOE on LOW to LOW Z 5 5 ns
tLZCS CS LOW to Low Z[6] 5 5 ns
tHZCS CS HIGH to High Z[S,6] 35 35 ns
WRITE CYCLE [7]
tAw Address Set-up to Write End 65 75 ns
tpWE WE Pulse Width 30 35 ns
tLZWE WE LOW to Low Z[6] 5 5 ns
tHZWE WE HIGH to High Z[S,6] 0 45 0 50 ns
Notes:
4.Test conditions assume signal transition times of 5 ns or less, timing 7.The internal write time of the memory is defined by the overlap of ~
reference levels of l.SV, inputlevelsofO to 3.0Vandoutput loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified IOL IIOH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
5. t HZCS and tHzwE are specified with Q = 5 pF as in Figure lb. signal that terminates the write.
Transition is measured SOO mV from steady state voltage. S.WE is HIGH for read cycle.
6.At any given temperature and voltage condition, t HZCS is less than 9.Device is continuously selected, CS' = VILand DE = VII:
t LZCS for any given device. These parameters are guaranteed and not lO.Address valid prior to or coincident with CS transition low.
100% tested. 1l.Data 110 will be high impedance ifUE = "'IH'
2-267
~PRESS
WAICONDUcrOR
CYM1421
CYM1421
Parameter Description Test Conditions Units
Min. Max.
'DR Vee for Retention Data 2.0 V
Vee = 2.0V,
IeeDR Data Retention Current CS ~ Vee - 0.2V 250 ~A
teDR(13) Chip Deselect to Data Retention Time \iN ~ \te - 0.2V 0 ns

or \iNS 0.2V
tR(13) Operation Recovery Time . tRe(12) ns
Notes:
12. tRC = Read Cycle Time. 13. Guaranteed, not tested.
J:::- DATA RETENTION MODE :}:

tc:t:. . f-----V.- _~_2_V
t--_4_.5_V
OR
- _____ /1~5~:=L
' ' 'Z-'' 'Z' ' -Z'' '-Z'' ' ' Z-'7fv-lrV
-'H-"""'" V
OR
''''---~"'''''IIII!-I\~S~S--or-S-S~S~
1421-6

ADDRESS
~"'---tOHA------I-t~~-t""" -*-
~======:=============D=A=TA==V=AL=ID==================
DATA OUT
PREVIOUS DATA
1421-7
2-268
~~DUCTOR CYM1421

Read Cycle No.2 [8, 10]
til
t RC
~ ....,It-
~
tACS
....,f-
-'~
tOOE HZOE
- t -
t LZOE t HZCS
HIGH IMPEDANCE HIGH IMPEDANCE

DATA OUT / / / / II' DATA VALID
\. \. \. \. ~
~tLZCS-
1421-8
Write Cycle No.1 (WE Controlled) [7, 11]

twc
ADDRESS ~f
- I.
tscs
-'lE-
""\ """-T tSA

tAW
tPWE
--: ~////
t HA -
V/////////
L
WE ..3k-" ,,~~ -,f-
I
tSD tHD
DATA IN ~f DATA-IN VALID -J(""
---- t
HZWE
- I--- t LZWE -
HIGH IMPEDANCE
1421-9
Write Cycle No.2 (CS Controlled)[7, 11]

twc
ADDRESS ~~ ~IIL
- I\.
tSA
.1 tscs
~ -;~
I tHA
tAW
tpWE
""""""""""""""""""""""~~
WE ,'-// / / / / / / / / / / / /
l
tSD -; tHD
I
DATA IN
*" *"
DATA-IN VALID
I I
DATA I/O _______

- t HZWE
DA_T_A_UN_D_EF_IN_E_D_ _ _ _ _ _ _ _ _ _ _ _ "l_ HIGH IMPEDANCE
1421-10
Note: If CS goes HIGH simultaneous]ywith WE HIGH, the output remains in a high impedance state.
2-269
~RESS
.nEMICONDUcrOR
CYM1421
Truth Table
L H L Data Out Read
L L X Data In Write
Package Operating
Speed Ordering Code
Type Range
CYM1421HD-7OC HD04
Commercial
CYM1421LHD-7OC HD04
70
CYM1421HD-70M HD04
Military
CYM1421LHD-70M HD04
CYM1421HD-85C HD04
Commercial
CYM1421LHD-85C HD04
85
CYM1421HD-85M HD04
Military
CYM1421LHD-85M HD04
Document #: 38-M-00002
2-270
PRELIMINARY CYM1422
CYPRESS
Module.
Features Functional Description through I/07) is written into the memory
High-density 1M bit SRAM Module The CYM1422 is a high performance 1 through A16). Reading the device is ac-
High speed CMOS SRAMs Megabit Static RAM module organized as complished by taking chip select (CS) and
- Access time - 30 ns 128K words by 8 bits. This module is con- output enable (OE) WW, while write
structed using four 64K x 4 Static RAMs enable (WE) remains inactive or HIGH.
Low active power - 1.3 W (max) in SOJs mounted onto a single sided mul- Under these conditions, the contents of
SMD technology tilayer epoxy laminate board with pins. A the memory location specified on the
decoder is used to interpret the higher
TTL compatible inputs and outputs address pins will appear on the eight data
order address A16 and select one pair of
input/output pins.
Low profile the four RAMs.
- Max. height - .50 in. Writing to the memory module is accom- The input/output pins remain in a high
plished when the chip select (CS) and impedance state unless the module is
Small PCB footprint - 0.8 sq in. write enable (WE) inputs are both LOW. selected, outputs are enabled, and write
2V data retention (L version) Data on the eight input/output pins (IlOo enable (WE) is HIGH.
Ao-A15~~16----------~--------------~
OE ------------0+--------------,
WE ----------~~------------~
1 of 2
decoder
'-------------------'----'-r'-- 110 0 - 1/0 7
SIP
1422-1
Component Side 1422-2
Selection Guide
1422PS-30 1422PS-35 1422PS-45 1422PS-55
Maximum Access time (ns) 30 35 45 55
Maximum Operating Current (rnA) 230 230 230 230
Maximum Standby Current (rnA) 80 80 80 80
2-271
'
till ,., CYPRESS
_ SEMICONDUCTOR
PRELIMINARY CYM1422

Range
Temperature Vee
Storage Temperature .......... , .......... -6SoC to + IS0C o
Commercial OC to +70 C SV 10%
Power Applied .......................... _10C to +90C
Supply Voltage to Ground Potential. . . . . . . .. -O.SV to + 7.0V
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
Output Current into Outputs (Low) .................. 20 rnA

CYM1422PS
Min. Max.
IIX Input Load Current GND :s; \1 :s; Vee -15 +15 J.lA
Ioz Output Leakage Current GND:S; Vo:S; Vee. Output Disabled -15 +15 J.lA
Vee Operating Vee = Max., lOUT = 0 rnA
Ice Supply Current CS :s; VIL 230 rnA
Automatic CS [2] Max. Vee; CS ~ VIH
IsBI Power Down Current Min. Duty Cycle = 100% 80 rnA
Automatic CS [2] Max. Vee CS ~ \te - 0.3V,

ISB2 Power Down Current VIN ~ Vee - 0.3V or 80 rnA
VIN :s; 0.3V
Capacitance[3]
TA = 25C, f = 1 MfJz, pF
COUT Output Capacitance Vee= 5.0V 30
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. A pull-up resistor to \f::c on the"CS input is required to keep the device
short circuit should not exceed 30 seconds. deselected during \CC power-up, otherwise ISB will exceed values
given.

5V~ R2 5V~ R2
3.0V-----
90%
OUTPUT OUTPUT
30PF I5PF 2550 GND---""I
I 2550
-- -- -- -- :s; 5 ns
INCLUDING INCLUDING
SCOPE SCOPE
Equivalent to: TIIEVENIN EQUIVAlENT
1670
OUTPUT o-----vw--o 1.73V
1422-5
2-272

~~~ PRELIMINARY CYM1422
~ SEMICONDUCTOR
. CYPRESS

1422PS-30 1422PS-35 1422PS-45 1422PS-55
READ CYCLE
tACS CS LOW to Data Valid 30 35 4S 55 ns
tDOE OE LOW to Data Valid 20 2S 30 30 ns
tLZOE ITE LOW to LOW Z 3 3 3 3 ns
tLZCS CS LOW to Low Z [6] 3 3 3 3 ns
tHZCS CS HIGH to High Z [5,6) 15 20 20 20 ns
tpu CS LOW to Power Up 0 0 0 0 ns
tPD CS HIGH to Power Down 30 35 45 55 ns
WRITE CYCLE [7]
twc Write Cycle Time 2S 30 40 50 ns

tpWE WE Pulse Width 25 35 35 40 ns
tLZWE WE HIGH to Low Z [6] 3 3 3 3 ns
tHZWE 'WE LOW to High Z[S,6] 0 15 0 20 0 25 0 30 ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing 7. The internal write time of the memory is defined by the overlap oft;S
reference levels of l.SV, input levels of 0 to 3.0V and output loading LOW and WE LOW, Both signals must be LOW to initiate a write and
of the specified IodIoH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. t HZCS and t HZWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
Transition is measured SOO mV from steady state voltage. signal that terminates the write.
6. At any given temperature and voltage condition, t HZCS is less than 8. WE is HIGH for read cycle.
tLZCS for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = \lL and DE = \lL'
100% tested.
10. Address valid prior to or coincident with ~ transition low.
11. Data 110 will be high impedance if OE = VIH
2-273
~PRESS
WnEMICONDUCTOR
PRELIMINARY CYM1422

CYM1422
Min. Max.
\DR Vee for Retention Data 2.0 V

Chip Deselect to Data Retention Time CS ~ Vee - 0.2V 0 ns
teDR(13)
\TN ~ \te - 0.2V
tR(13) Operation Recovery Time or\TN:S': 0.2V tRe[l2) ns
IU[l3) Input Leakage Current 16 ~
Notes:
12. = Read Cycle Time.
tRC 13. Guaranteed, not tested.
DATA RETENTION MODE ::k

tc:tI. .
1-_4_.5_V :~ _____ VO_R_~_2_V_____/~5:R-1
OR
'''-Z-''--Z''''Z-Z''''Z-7Iv'''''-!!-V,H- - V I 1\S SSS \
VIH
1422-6
Switching Waveforms [11)

Read Cycle No. 118 ,91
ADDRE~ -={ t~--;~

DATA OUT PREVIOUS DATA ~===================D=A=T=A=V=A=LI=D================
*--
1422-7
2-274
~PFESS
WnMICONDUCTOR
PRELIMINARY CYM1422

Read Cycle No.

2[8,10]
t RC
~~ -,t..
tACS
..l~ ,"",it-
tOOE ~ t HZOE -
t LZOE t HZCS
HIGH IMPEDANCE 11////11 HIGH IMPEDANCE
DATA OUT
!" \. \. \. \. " DATA VALID
~
~ t LZCS -
VCC
~ tpu - tpD
~
50%~
ICC
SUPPLY ISB
CURRENT
1422-8
Write Cycle No. 1 (WE Controlled) [7]
ADDRESS -- -: {-
L
twc
~~
"" !"""-T
tscs
--: ~//// V/////////
\ tAW
t HA -
tSA t PWE
I
~"
I ,,-' I<'"" 7'-
tSD tHD
DATA IN -u- DATA-IN VALID -:(....
HZWE - tlZWE
-- t -
HIGH IMPEDANCE
1422-9
Write Cycle No.2 (CS Controlled)[7]

twc
ADDRESS
-
~
~
tSA
I tscs
....,it-
~t
tAW
~ tHA
t pWE
""""""""""""""""""""""~~
..... '-// / / / / / / / / / / //
L J tHD
tSD
I
DATA IN
DATA OUT _______

- t HZWE
DA_T_A_uN_D_EF_IN_E_D_ _ _ _ _ _ _ _ _ _ _ _
* I
DATA-IN VALID
l_ HIGH IMPEDANCE
*- I
1422-10
Note: If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-275
~PRLSS
.nEMICONDUcrOR
PRELIMINARY CYM1422
Truth Table
L H L Data Out Read
L L X Data In Write
Package Operating
Speed Ordering Code
Type Range
25 M1422PS-30C PS03 Commercial
M1422LPS-30C PS03
3S M1422PS-3SC PS03
M1422LPS-35C PS03
45 M1422PS-45C PS03
M1422LPS-45C PS03
55 M1422PS-55C PS03
M1422LPS-55C PS03
2-276
PRELIMINARY CYM1460
CYPRESS
Module
II
Features Functional Description the memory. When MS and WE inputs
are both LOW, data on the eight data
High-density 4 Megabit SRAM Module The CYMl460 is a high performance input/output pins is written into the
High speed CMOS SRAMs 4-Megabit Static RAM module organized memory location specified on the address
as 512K words by 8 bits. This module is pins. Reading the device is accomplished
- Access time - 45 os
constructed from sixteen 32K x 8 SRAMs
Low active power - 2.5 W (max) by select~ the device and enabling the
in plastic surface mount packages on an
~uts, MS and OEactive LOW, while
Double-sided SMD Technology epoxy laminate board with pins. Two
WE remains inactive or HIGH. Under
TTL compatible inputs and outputs choices of pins are available for vertical
these conditions, the content of the loca-
(PS) or horizontal (PF) through-hole
Low profile version (PF) tion addressed by the information on the
mounting. On-board decoding selects
- Max. height - .315 in. address pins is present on the eight data
one of the sixteen SRAMs from the high
input/output pins.
Small footprint SIP version (PS) order address lines keeping the remaining
- PCB layout area - 1.5 sq in. fifteen devices in standby mode for mini- The input/output pins remain in a high
mum power consumption. impedance state unless the module is
An active LOW write enable signal (WE) selected, outputs are enabled, and write
controls the writing/reading operation of enable (WE) is HIGH.
rH rH r l r
/
/15
H 32Kx8
SRAM
32Kx8
SRAM
32Kx8
SRAM
32Kx8
SRAM
I I I I I I I I I I I
I I
~ r-~
10tB
H 32Kx8
SRAM
rH r H rH r
32Kx8
SRAM
32KxB
SRAM
32KxB
SRAM
decoder
'--l~
-- I I
H 32Kx8
SRAM
rH rH rH r
32KxB
SRAM
32KxB
SRAM
32Kx8
SRAM
I I
-~
10tB
~ y 32Kx8
SRAM
~ H 32KxB
SRAM
r 32KxB
SRAM
r 32Kx8
SRAM
r
decoder
~ ~l I I
-~
,/ I
1460-1 SIP 1460-2
Selection Guide
1460PS-45 1460PS-55 1460PS-70
1460PF-45 1460PF-55 1460PF-70
Maximum Access time (ns) 45 55 70
Maximum Operating Current (rnA) 450 450 450
Maximum Standby Current (rnA) 320 320 320
2-277
~~ PRELIMINARY CYM1460
Maximum Ratings
(Above which the useful life may be impaired)
Storage Temperature ........... ; ......... -65C to + 150C Output Current into Outputs (Low) ............ ~ .. . .. 20 rnA
Power Applied ............................ OOC to +70 o C Operating Range
Ambient
Supply Voltage to Ground Potential ......... -0.5V to +7.0V Range
Temperature Vee
in High Z State. .. . . . . . . . . . . . . . . . . . . . . . . .. -O.SV to + 7.0V Commercial OOC to +70 o C 5V 10%
DC Input Voltage ........................ -O.SV to + 7.0V

CYM1460 Units
Parameters Description Test Conditions
Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH =. -4.0 rnA 2.4 V
IIX Input Load Current GND ~VI ~Vee -20 +20 J.l.A
Output Leakage Current GND ~VI ~Vee -20
loz Output Disabled +20 J.l.A
los Current!!] Vee = Max., VOUT = GND -300 rnA
Vee Operating Vee = Max., MS ~ VIL

Ice Supply Current lOUT = OmA 450 rnA
Automatic MS Max. Vee, MS ~ VIH,
IsB! Power Down Current Min. Duty Cycle = 100% 320 rnA
Automatic MS Max. Vee, m

~ 'te - 0.3V,
IsB2 Power Down Current VIN ~ Vee - 0.3V or 320 rnA
VIN ~ 0.3V
Capacitance[2]
Parameters Description Test Conditions Max. Unit
CIN Input Capacitance o
TA= 2S C,f = 1 MHz 100
pF
Notes:
1. Not more than 1 outputshould be shorted at one time. Duration of the 2. Tested on a sample basis.
short circuit should not exceed 30 seconds.

OUTP~~~ 5V~ R2
3.0V----
90%
OUTPUT
. J..3O pF
R2
-= 2550 .r.- 5PF
_ 2550
-
GND ----'I
~5ns
INCLUDING INCLUDING
JIG AND JIG AND
SCOPE SCOPE 1460-3 1460-4
Equivalent to: 1HEVENIN EQUIVALENT
OUTPUT ~1.73V 1460-5
2-278
~PFE3S
W~ICONDUcrOR
PRELIMINARY CYM1460
Switching Characteristics Over Operating Range (3)
1460PS45 1460PS55 1460PS70

Parameters Description 1460PF45 1460PF55 1460PF70 Units
READ CYCLE
fJI
tAMS MS LOW to Data Valid 45 55 70 ns
tDOE OE LOW to Data Valid 20 2S 30 ns
tLZOE <JE LOW to Low Z 0 0 0 ns
tHZOE OE HIGH to High Z(4) 2S 2S 30 ns
tLZMS m LOW to Low Z[S) 5 5 5 ns
tHZMS MS HIGH to High Z[4,S) 2S 30 35 ns
tpu MS LOW to Power Up 0 0 0 ns
tpD MS HIGH to Power Down 45 55 70 ns
WRITE CYCLE (6)
tSMS MS LOW to Write End 40 50 60 ns
tAW Address Setup to Write End 40 50 60 ns
tSA Address Setup to Write Start 5 5 5 ns
tSD Data Set-up to Write End 20 2S 30 ns
tHzWE WE LOW to High Z(4) 15 20 2S ns
tLZWE m HIGH to Low'Z 3 5 5 ns
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing 6. The internal write time of the memory is defined by the overlap ofm
reference levels of l.SV, input levels of 0 to 3.0V and output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified lodloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
4. tHZOE , t HZMS and tHZWE are specified with C L = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
5. At any given temperature and voltage condition, tHZMS is less than 7. WE is HIGH for read cycle.
tLZMS for any given device. These parameters are guaranteed and not
100% tested.
8. Device is continuously selected.rm, MS = "IL'
9. Address valid prior to or coincident with m transition LOW.
10. Data 110 is HIGH impedance if OE = VIH
Switching Waveforms
ADDRESS
~-tOHA-------1-t~~_tRC " .. --*-
VA0C~===================D=A=T=A=V=A=L1=D===============:
DATA OUT
PREVIOUS DATA 1460-8
2-279
5r~DOCIa PRELIMINARY CYM1460

Rea~ Cycle No. Z[7,9]
t Rc
~~ -It.
tAMS
..:l~ -~
tOOE 14-- tHZOE-----"

tLZOE t HZMs
DATA OUT
HIGH IMPEDANCE ////11
DATAVAUD
, HIGH IMPEDANCE
\. \. \. \. "- ~
I--- tLZMS-
I---
~ tpu
t pD
::1
SUPPLY
CURRENT
Vcc
-----1- 5O%~ISB
1460-7
ICC
Write Cycle No. 1 (WE C;:::ontrolled) [6, 10]
twc
ADDRESS
-
~~
I
t SMS
jF-
"\'\.\ '\.'\.'\.~ - 'q/// /////////

tAW t HA -
tSA tpWE
"I
.lk-'\. '\.~ ..- ~IC
1
tSD tHO
DATA IN ~E- DATA-IN VAUD ..J~
I+- t HzwE - - ~ tLZWE -----
HIGH IMPEDANCE
1460-8
Write Cycle No. Z (MS Controlled)[6, 10]
twc ~
ADDRESS
-
~
~
tSA
~1
~
I
tSMS
~~
tHA
..:lit
tAW ~
tPWE
'\.'\.'\.,\.'\.\.\.'\.\.'\.'\.\.,','\.,",\.~~ ....,~/ / / //J/// / / // /
.1 tSD 1 tHO
DATA IN
* J. *
DATA-IN VALID
'I I+-t
'I
DATA UNDEFINED ,H. ZWE )0-_H:.::;IG~H.:.:.:IM=P~ED~A::.INC:.:IiEi--_ _ _ _ _ _ __
DATA 1/0
------------~-------------------
Note: IfMS goes HIGl! simultaneously with WE HIGH, the output remains in a high impedance state_ 1460-t
2-280
~
...
,.' CYPRESS PRELIMINARY CYM1460
SEMICONDUCTOR

MS WE OE Input/Outputs Mode Package Operating
Speed Ordering Code
H X X HighZ Deselect Power Down Type Range
L
L
H
L
L
X
Data Out
Data In
Read
Write
45
55
CYMl460PS-45C
CYMl460PF-45C
CYMl460PS-55C
PSOI
PFOI
PSOI
Commercial
Commercial
fI
L H H HighZ Deselect CYMl460PF-55C PFOI
Document #: 38-M-00004 70 CYMl460PS-7OC PSOI Commercial
CYMl460PF-7OC PFOI
2-281
CYM1461
CYPRESS
Module
Features Functional Description the memory. When MS and WE inputs
are both LOW, data on the eight data
High-density 4 Megabit SRAM Module The CYMI461 is a high performance input/output pins is written into the
High speed CMOS SRAMs 4-Megabit Static RAM module organized memory location specified on the address
as 512K words by 8 bits. This module is pins. Reading the device is accomplished
- Access time - 70 ns constructed from sixteen 32K x 8 SRAMs
Low active power - 660 mW (max) by selecting the device and enabling the
in plastic surface mount packages on an
~uts, MS and OEactive LOW, while
Double-sided SMD Technology epoxy laminate board with pins. Two
WE remains inactive or HIGH. Under
TTL compatible inputs and outputs choices of pins are available for vertical
these conditions, the content of the loca-
(PS) or horizontal (PF) through-hole
Low profile version (PF) tion addressed by the information on the
mounting. On-board decoding selects
- Max. height - .315 in. address pins is present on the eight data
one of the sixteen SRAMs from the high
input/output pins.
Small footprint SIP version (PS) order address lines keeping the remaining
- PCB layout area - 1.5 sq in. fifteen devices in standby mode for mini- The input/output pins remain in a high
mum power consumption. impedance state unless the module is
An active LOW write enable signal (WE) selected, outputs are enabled, and write
controls the writing/reading operation of enable (WE) is HIGH.

/ NC
'15
H 32Kx8
SRAM
tH 32Kx8
SRAM
~ n tH
32Kx8
SRAM
32Kx8
SRAM
~
Vee
WE
1/02 4
I I I I I I I I I I J 1/03
1/00
5
6
7
I I Al
A2 8
~r-~
1018
decoder
K 32Kx8 }
SRAM
I I I
K 32Kx8
SRAM
I I I
rK 32Kx8 }
SRAM
1 I J
H
32Kx8
J
SRAM
I
r A3
A4
GND
1/0 5
Al0
9
10
11
12
13
14
All
L...-f""J~
A5 15
-r--
I I A13
A14
16
17
tH rH t H t NC lS
H 32KxS
SRAM
32Kx8
SRAM
32Kx8
SRAM
32KxS
SRAM
m
A 15
19
20
21
I I I I It I I I I I A16
A12
A18
22
23
I I A6 24
r-~
25
r
1/01
GND 26
1018
1 t- 32Kx8
SRAM
32Kx8
SRAM
r 32Kx8
SRAM
32Kx8
SRAM
r Ao
A7
As
27
28
29
decoder
1 1 1 1 1 1 .1 1 I 1 I A9 30
~
1/0 7 31
-
----l
I I 1/0 4
1/0 6
A17
32
33
34
, /8 1/00 -1/0 7 Vee 35
OE 36
14611 SIP 14612
Selection Guide
1461PS-70 1461PS-85 1461PS-l00
1461PF-70 1461PF-85 1461PF-l00
Maximum Operating Current (mA) 120 120 120
2-282
~PRESS
'nMICONDUCTOR
CYM1461

Range Vee
Storage Temperature ..................... -65C to + 150C Temperature
Ambient Temperature with Commercial OC to +70C 5V 10%
Power Applied ............................ OC to +70 o C
Supply Voltage to Ground Potential. . . . . . . .. -O.3V to + 7.0V

CYMl46l
Min. Max.
\lH Input HIGH Voltage 2.2 Vee +0.3 V
IIX Input Load Current GND;:5;VI ~Vee -20 +20 jJA
Output Leakage Current GND;:5;VI ;:5; Vee -20

Ioz Output Disabled +20 J..lA
Vee Operating Vee = Max., MS ;:5; VIL
Ice Supply Current lOUT = OmA 120 rnA
Automatic MS Max. Vee, MS ~ VIH,
IsBl Power Down Current Min. Duty Cycle = 100% 50 rnA
Automatic MS Max. Vee, MS ~ 'te - 0.3V,

IsB2 Power Down Current VIN ~ Vee - 0.3Vor 32 rnA
VIN;:5; 0.3V
Capacitance[2]
CIN Input Capacitance TA= 25C,f = 1 MHz 100
pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the 2. Tested on a sample basis.

5V~ R2 5V~ R2
3.0V-----
90%
OUTPUT OUTPUT
J 30 pF _ 10200 J 5 pF _ 10200 GND---~
;:5;5 ns
- - --
INCLUDING INCLUDING
JIG AND JIG AND 1461-4
1461-3
SCOPE SCOPE
6670
OUTPUT o---vvv----o 1.73V 14615
2-283
w?:= SEMICONDUCTOR

CYM1461
1461PS-70 1461PS-85 1461PS-I00

Parameters Description 1461PF-70 1461PF-85 1461PF-I00 Units
READ CYCLE
tAMS MS LOW to Data Valid 70 85 100 ns
tLZOE LiE LOW to Low Z 5 5 5 ns

tLZMS MS LOW to Low Z[S] 5 5 5 ns
tHZMS MS HIGH to High Z[4,S] 35 35 40 ns
WRITE CYCLE [6]
tSMS MS LOW to Write End 70 80 85 ns
tHZWE WE LOW to High Z[4] 30 35 40 ns
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing 6. The internal write time of the memory is defined by the overlap ofm
reference levels of 1.5V, inputlevels of 0 to 3.0V and output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified IodIoH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
4. t HZOE ' t HzMS and t HzWE are specified with C L = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
5. At any given temperature and voltage condition, t HZMS is less than 7. WE is HIGH for read cycle.
tLZMS for any given device. These parameters are guaranteed and not
100% tested.
8. Device is continuously selected. 00,m = "Iv
9. Address valid prior to or coincident with MS transition LOW.
10. Data 110 is HIGH impedance if OE = VIH'
Switching Waveforms
Read Cycle No. 1[8,9]
ADDRESS
~t~A~~ *-
~====================D=A=TA==V=AL=I=D=================
DATA OUT
PREVIOUS DATA VAUD 14616
2-284
~PRESS
wnMICONDUCTOR
CYM1461

Read Cycle No. 2 17,9]
~
~
tAMS
t AC
-:~ II
~~ -:~
tOOE I-t-- t HZOE -

t LZOE t HZMS
HIGH IMPEDANCE II / / / / I HIGH IMPEDANCE

DATA OUT
- tLZMS~
" \. \. \. \. '-
DATA VALID
14617
Write Cycle No.1 (WE Controlled) 16, 10)

twc
ADDRESS ~ f -:]too
--..:I
I
t SMS
'\'\\ I\,\.\'-T """"" t//// / / / / / / / / / /

tAW t HA -
tSA tpWE
I
~'\V IL "7 .....
I
tSD tHD
DATA IN ~t" DATA-IN VALID jf

r-- t HZWE - - t
LZWE
-
HIGH IMPEDANCE
14618
Write Cycle No.2 (MS Controlled)[6, 10]
ADDRESS -- .... ~.
twc
~t
tSA
-T
.1 tSMS
-.,..
I tHA
tAW
tpWE
'\'\'\\.\.'\\.'\'\'\'\'\'\'\'\'\\.'\'\'\\.'\~t -.~// / / / / // / / / / / /
l
r tSD I tHD
DATA IN
'* *"
DATA-IN VALID
I ~ t HZWE I
DATA I/O _______DA_T_A_UN_D_EF"!"IN_E_D_ _ _ _ _ _ _ _ _ _ _ _ :l_ HIGH IMPEDANCE
14619
Note: IfMS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
2-285
fin CYPRESS
. SEMICONDUCIOR

CYM1461
MS WE OE Input/Outputs Mode Package Operating

Speed Ordering Code
H X X HigbZ Deselect Power Down Type Range
L H L Data Out Read 70 CYMl461PS-7OC PS01 Commercial

CYMl461PF-7OC PF01
L L X Data In Write
85 CYMl461PS-85C PS01 Commercial
L H H HigbZ Deselect CYMl461PF-85C PF01
Document #: 38-M-OOOOS 100 CYMl461PS-100c PS01 Commercial
CYMl461PF-100c PF01
2-286
CYM1610
CYPRESS
Module.
Features Functional Description input/output pins of the selected byte
(I/Oe - I/Ol~' 1/00 - 1/07 ) is written into
High-density 256K bit SRAM Module The CYM1610 is a high performance the memory location specified on the ad-
High speed CMOS SRAMs 256K-bit Static RAM module organized dress pins (Ao through A 13).
- Access times - 25 ns as 16K words by 16 bits. This module is Reading the device is accomplished~
constructed from four 16K x 4 SRAMs taking chip select (CS), ~ select (VB,
Low active power - 1.8 W (max) in Leadless Chip Carriers mounted on a
Hermetic SMD Technology LB) and output enable (OE) LOW, while
ceramic substrate with pins. WE remains inactive or HIGH. Vnder
TTL compatible inputs and outputs Selecting the device is achieved by a chip these conditions, the contents of the
Low profile select~u.!..Ein as well as two byte select memory location specified on the address
- Max. height - .215 in. pins (VB, LB) for independently selecting pins will appear on the appropriate data
upper or lower byte for read or write input/output pins.
Small PCB footprint - 1.2 sq in. operations. The input/output pins remain in a high
JEDEC defined pinout
Writing to the memory module is accom- impedance state when chip select (CS),
Independent byte select plished when the chip select (CS), ~ ~ select (VB, LB) or output enable
2 V data retention (L version) select (VB, LB) and write enable (WE) (OE) is HIGH, or write enable (WE) is
inputs are LOW. Data on the LOW.
Ao-A13~~14------------~------------------------~ Vee Vee

~ ~
~--------,.--I---------.
1/15 mr
~ --------~---~~---------------~ 1/14 [8
O'E" ---,--+--4--+----~ 1/13 NC
1/0 12 A13
1/11 A12
1/10 A11
1/0 9 A l0
I/Oa Ae
GND GND
1/0 7 Aa
I/Oe A7
I/O a - 1/015 1/0 5 A6
1/0 4 A5
1/0 3 A4
1/0 2 A3
1/0 1 A2
1/0 0 A1
'O'E" Ao
~--------------~-+------------~ DIP
1/00 -1/7
1610-1 16102
;election Guide
1610HD-25 1610HD-35 1610HD-45 1610HD-50
Commercial 330 330 330 330
Military 80 80 80
2-287
~~ CYM1610
Maximum Ratings
Storage Temperature ..................... -65C to + 150C Static Discharge Voltage ......................... >2001V
(per MIt-STD-883 Method 3015.2)
Power Applied ......................... -55C to + 125C Latch-up Current . . . .. . . . .. . . .. . . . . .. . . . . . . . . ... > 200 rnA
Operating Range
bc Voltage Applied to Outputs Ambient
in High Z State ........................... -O.5V to +7.0V Range
Temperature Vee
DC Input Voltage ........................ -3.0V to + 7.0V
Commercial OOC to +70 o C 5V 10%
Military -55C to + 125C 5V 10%

CYM1610HD
Min. Max.
'iH Input HIGH Voltage 2.2 Vee V
'iL Input LOW Voltage -3.0 0.8 V
IIX Input Load Current GND ~ VI ~ Vee -15 +15 JJ.A
loz Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -15 +15 JJ.A
los Current[l) Vee = Max., VOUT = GND -350 rnA
Vee Operating Vee == Max., lOUT = 0 rnA

IcCx16 Supply Current CS, UB, & LB = VIL
330 rnA

Icexs Supply Current CS = VIL, UB or LB = VIL
Automatic CS [2) Max. Vee, CS ~ Vm,
IsBl 80 rnA
Automatic CS [2) Max. Vee, CS ~ Vee - 0.3V,

ISB2 VIN ~ Vee - 0.3V or 80 rnA
Power Down Current VIN ~ 0.3V
Capacitance[3)
pF
COUT Output Capacitance \te = 5.0V 40
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the deselected during 'Cc power-up, otherwise ISB will exceed values
short circuit should not exceed 30 seconds. given.
2. A pull-up resistor to 'Cc on the eE input is required to keep the device 3. Tested on a sample basis.

R1 4810 R1 4810 Alllnput Pulses
5V~ R2 5V~ R2
3.0V----
OUTPUT OUTPUT
J 30pF _ 2550 J 5pF _ 2550 GND---"I

~5ns
- - - -
INCLUDING INCLUDING
JIG AND JIG AND
SCOPE SCOPE 16103
161C
1670
OUTPUT o----vvv---o 1.73V 161()'5 2-288

2!'-.,~ CYM1610
., CYPRESS
~. SEMICONDUCTOR
Switching Characteristics Over Operating Range [4)
1610HD-25 1610HD-35 1610HD-45 1610HD-50

READ CYCLE
tOHA Data Hold. from Address Change 5 5 5 5 ns
tLZOE (jE LOW to LOW Z 5 5 5 5 ns

tLZCS CS LOW to Low Z [6) 5 5 5 5 ns
tHZCS CS HIGH to High Z [5,6) 10 15 15 20 ns
tpD CS HIGH to Power Down 25 35 40 50 ns
WRITE CYCLE [7)
tLZWE WE HIGH to Low Z[6) 3 5 5 5 ns
tHZWE WE LOW to High Z[5. 6) 0 7 0 12 0 12 0 15 ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing 7. The internal write time of the memory is defined by the overlap of<:;S
reference levels of l.SV, input levels of 0 to 3.0V and output loading LOW and WE LOW. Both signals must be LOW to initiate a write and
of the specified IOL/IOH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. t HZCS and t HzWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
6. At any given temperature and voltage condition, t Hzcs is less than 8. WE is HIGH for read cycle.
fLzcs for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = VJL and 00 = VJL'
100% tested.
10. Address valid prior to or coincident with 7:S' transition low.
11. Data 110 will be high impedance if OE = VIH
2-289
~PRESS
.nMICONDUcrOR
CYM1610
D ata Retenbon Ch aracterlsbcs (L Version Only:
CYM1610
Min. Max.
\])R Vee for Retention Data 2.0 V
teDR[13]
\iN ~ \te - 0.2V
tR[13] Operation Recovery Time or \iN :s: 0.2V tRe[12] ns
IU(13) Input Leakage Current 8 ~
Notes:
12. tRc = Read Cycle Time. 13. Guaranteed, not tested.
DATA RETENTION MODE :}:

tC~R...__4_.5_"~_ _ _ _ _VO_R_~_2V_____/~~R~
~-,~~~~~~~_ _~ VOR I
'/ZzzZ V1H ' I 1'SSSS\
VIH
1610-
Switching Waveforms [10]

ADDRE$ ~--t-OHA---1-t_~~
__ tRC-",-----*----
DATA OUT PREVIOUS DATA VAillC~====================D=A=TA==V=AL=ID================== 1610
2-290
.
~~~ Jil
,
CYPRESS
SEMICONDUCTOR
CYM1610

t RC
~~
...3.-
tACS
-.f-
-,1-
fI
tOOE ~ t HZOE -
tLZOE t HZCS

DATA OUT 1'- '\ '\ '\ '\ 1'-
DATA VALID
- tLZCS-
!4--- t pD
. . - t pu
-1 ICC
=~
VCC
SUPPLY IS8
CURRENT
1610-8
Write Cycle No.1 (WE Controlled) [7, 11)
ADDRESS -- -: t-
twc
~~
",,\ .""~ L
tAW
tscs
---,
"-//// V / / / / / / / / /
t HA -
tSA t pWE
I
WE ~"V, I~
I
L
tSD tHO
DATA IN
I
~~
*"I
DATA-IN VALID
- t HZWE f4-- tLZWE
HIGH IMPEDANCE
1610-9
Write Cycle No.2 (CS Controlled) [7, 11)
ADDRESS -- ~
f
tSA
twc
..Jl~
tscs
T
......,~
-T
I tHA
tAW
tpWE
""""""""""""""""""""""~~
WE -; ~/ / / / / / / / / / / / //
L
DATA IN
r tSD -; tHD
* *
DATA-IN VALID
DATA I/O _______DA_T_A_uN_O_EF_IN_E_D_ _ _ _ _ _ _ _ _ _ _ _

I foI-- t HZWE
l_ HIGH IMPEDANCE
I
Note: If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 1610-10
2-291
~mss
.nMICONDUCTOR
CYM1610

CS UB LB OE WE Input/Outputs Mode Package Operating
Speed Ordering Code
X X Type Range
L H H X X HighZ Deselect Power Down 25 CYM16 10HD-25C HDOl Commercial
L L L L H Data OutO-1S Read Word CYM16 10LHD-25C HDOl
L H L L H Read Lower Byte 35 CYM1610HD-35C HDOl Commercial
Data OutO-7
L L H L H Data Out 8-15 Read Upper Byte CYM16 10LHD-35C HDOl
L L X L Write Word CYM16 10HD-35MB HDOl Military

L Data In 0-15
CYM16 10LHD-35MB HDOl
L H L X L Data In 0-7 Write Lower Byte
45 CYM1610HD-4SC HDOl Commercial
L L H X L Data In8_15 Write Upper Byte
CYM161OLHD-45C HDOl
L L L H H HighZ Deselect
CYM1610HD-45MB HDOl Military
L H L H H HighZ Deselect
CYM1610LHD-45MB HDOl
L L H H H HighZ Deselect
50 CYM16 10HD-5OC HDOl Commercial
CYM16 10LHD-5OC HDOl
CYM1610HD-50MB HDOl Military
CYM1610LHD-50MB HDOl
2-292
CYM1611
CYPRESS
Module.
Features Functional Description through D,IS) is written into the memory
High-density 256K bit SRAM Module The CYM1611 is a very high perfonnance through A,3).
High speed 256K-bit Static RAM module organized
as 16K words by 16 bits. The module is Reading the device is accomplished by
- Access time - 25 ns constructed from four 16K x 4 SRAMs in taking chip select @ and output enable
16 bit wide organization (OE) WW, while WE remains inactive or
Leadless Chip Carriers mounted on a ce-
ramic substrate with pins. A vertical DIP HIGH. Under these conditions, the con-
Low active power - 1.8 W (max)
fonnat minimizes board space (footprint tents of the memory location specified on
Hermetic SMD Technology the address pins will appear on the sixteen
= 0.4 sq in.) while still keeping a maxi-
TTL compatible inputs and outputs mum height of 0.5 in. data input/output pins.
Low profile Writing to the memory module is accom- The input/output pins remain in a high
- Max. height - .0.5 hi. impedance state unleSs the module is
plished when the chip select (CS) and
write enable (WE) inputs are both WW. selected, outputs are enabled, and write
Small PCB footprint - 0.4 sq in. enable (WE) is HIGH.
Data on the sixteen input/output pins (Do
2V data retention (L version)
Ao-A13~1~4------------~------------------------~
~----rlf---------.
~ ------~-+-4------------
O"E" ----r--+--+--+-----
VDIP
~ _________________..L.._...L...,L. Do - 0
15
16111 1611-2
~election Guide
1611HV-25 1611HV-30 1611HV-3S 1611HV-45
Maximul11 Access time (ns) 25 30 35 45
Commercial 330 330 330 330
Maximum Operating Current (mA)
Military 80 80 80
2-293
~PFE3S
WnMlcoNDucroR
CYM1611
Maximum Ratings
(AbOve which the useful life may be impaited)
Storage Temperature .. : .................. -65C to + 150C Static Discharge Voltage ................ :: .. ; ... >2001V
(per MILSTD-883 Method 3015)
Power Applied ......................... -55C to + 125C Latch-up Current.. . . .. . . . . . . . .. . . .. .. . . .. .. . ... > 200 mA
Supply Voltage to Ground Potential ....... " -O.5V to + 7.0V
Operating Range
in High Z State. .. . . . . . . . . . .. . .. .. .. .. .... -O.SV to + 7.0V Ambient
Range
Temperature Vee
DC Input Voltage.. .. .. .. .. . .. .. .. .... ... -3.0V to + 7.0V
Commercial OOC to +70C 5V 10%
Output Current into Outputs (Low) ... , .............. 20 mA
Military -55C to + 125C SV lO%
Electrical Characteristics Over. Operating Range
CYM1611HV
Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnA 24 V

VOL Output LOW Voltage Vee = Min., IOL == 8.0 mA 0.4 V
"iH Input HIGH Voltage 2.2 Vee V
"iL Input LOW Voltage -3.0 0.8 V
IIX Input LOad Current GND ~\'J ~Vee -20 +20 ~
loz Output Leakage Current GND ~\'J ~ Vee, Output Disabled -20 +20 ~
los Current!l] . Vee = Max., VOUT = GND -350 rnA
Vee Operating
Ice Supply Current Vee = Max., lOUT = 0 rnA, CS ~ VIL 330 mA
Automatic CS Max. Vee, CS ~ VIH, 80 rnA

lsBl Power Down Current Min. Duty Cycle = 100%
Max. Vee, CS ~ Vee- 0.3V,
Automatic CS
lsB2 VIN ~ \(:e - 0.3V or 80 mA
Power Down Current
VIN ~ 0.3V
Capacitance!2]
~= 25C,f = 1 MHz pF
COUT Output Capacitance ee= 5.0V 15
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. Tested on a sample basis.
OUTPUT
5V~.
R1 481 0
l30PF~ 2550
R2
OUTPUT
5V9S1. l 5 PF
R1 481 0
R2
~ 2550
3.0V----
GND---""I
All Input Pulses
90%
~5ns
INCLUDING INCLUDING
JIG AND JIG AND
SCOPE SCOPE 16113 1611-4

1670
OUTPUT o----vv".-.o 1.73V 16115
2-294
~~~ CYM1611
1611HVZ5 1611HV30 1611HV35 161lHV45

II
READ CYCLE
tRC Read Cycle Time 2S 30 35 45 ns
tAA Address to Data Valid 2S 30 35 45 ns
tACS CS LOW to Data Valid 2S 30 35 45 ns
tnoE OE LOW to Data Valid 15 20 2S 30 ns
tLZOE <JE LOW to Low Z 0 0 0 0 ns
tHZOE OE HIGH to High Z[4] 10 15 20 20 ns
tLZCS CS LOW to Low Z[S) 5 10 10 10 ns
tHZCS CS HIGH to High Z[4. S] 10 15 15 20 ns
WRITE CYCLE [6]
twc Write Cycle Time 20 2S 2S 35 ns

tAW Address Set-up to Write End 20 2S 30 40 ns
tpwE WE' Pulse Width 20 25 25 30 ns
tSD Data Set-up to Write End 13 20 20 2S ns
tHZWE WE LOW to High Z[4] 0 7 0 12 0 12 0 15 ns
tLZWE WE HIGH to Low Z 3 5 5 5 ns
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing 6. The internal write time of the memory is defined by the overlap of rS'
reference levels of 1.5V, inputlevels of 0 to 3.0V and output loading of LOW and WELOW. Both signals must be LOW to initiate a write and
4. t HZOE ' t HZCS and HZWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
t LZCS for any given device. These parameters are guaranteed and not 8. Device is continuously selected. 00, (;S = VIL
100% tested.
9. Address valid prior to or coincident with 'CS' transition LOW.
10. Data 110 is HIGH impedance if OE = VIH'
2-295
~~~ CYM1611

CYM1611
Min. Max.
\bR Vee for Retention of Data 2.0 V
IceDR Data Retention Current Vee = 2.0V, 4 rnA

Chip Deselect to Data Retention Time CS ~ 'te - O.2V 0 ns
tCDR
'iN ~ \te - 0.2V
tR Operation Recovery Time or'iN~ 0.2V tRe lll) ns
ILl Input Leakage Current 5 J.1A
Note:
11. tRC = Read Cycle Time.
~ DATA RETENTION MODE ::1

tc:J:.__ :~-----v.-:-:-:_z.J_----/~~R-1
4_.5_V
...V,-H ~
r.,...Z....,.Z.....,.-Z.,..Z.....,.-Z.,...7fv I V
1H
1\S sss S
1611-6
Switching Waveforms
Read Cycle No. 117,8)
ADDRESS
~-tOHA-------j-t~~_tRC., ----*--
VAUrC~===================D=A=T=A=V=AL=ID=================
DATA OUT
PREVIOUS DATA
1611-7
2-296
~PRESS
WnMlcoNDucroR
CYM1611

t RC
~~
tos
-:.~
til
... ~ -;'f-
tOOE 14-- t HZOE -

t LZOE t HZCS

DATA OUT
LZCS
" \. \. \. \. I" DATA VALID
- t -
Vee _______
. - tpu
j -----------------------------------------------------~~------ICC
50%
I--- tpD
::1I " ' - -
50% 19B
SUPPLY
CURRENT
1611-8
Write Cycle No. 1 (WE Controlled) [6, 10]

twc
ADDRESS ~ f ~E-
-----I
L
tscs
\. \. \ \. \. \'-T ~
'-L//L. //////////
tAW t HA -
tSA tpWE
I
WE ~\.. \...3 ~ ~~
I
tSD tHO
DATA IN 7t" DATA-IN VALID -:If

~ t HZWE .....-- tLZWE-
HIGH IMPEDANCE
1611-9
Write Cycle No.2 (CS Controlled)[6,10]

twc
ADDRESS
-
~
~
tSA
I tscs
-,~
~f-
-T
I tHA
tAW
tpWE
WE -"~.......\."'-\.\.""-\.\."-\.\.\.\.\.\.\.\.\.\.\..~~ l
-,~// / / / / / / / / / / //
tSD -I tHD
r
DATA IN

* I I-- t
DATA-IN VALID
HZWEJ
__
*- I
~HIG~H~I~MP~E~DA~N~C~E ___________________
-------------------------------------------- 1611-10
Note: If CS goes HIGH simultaneously with WEHIGH, the output remains in a high impedance state.
2-297
~PFESS
WnEMICONDUcrOR
CYM1611
Truth Table
L H L Data Out Read
L L X Data In Write
Type Range
25 CYM1611HV-25C Commercial
HVOI
CYM1611LHV-25C
HVOI
CYM1611LHV-30C
CYM1611HV-30MB Military
HVOI
CYM1611LHV-30MB
HVOI
CYM1611LHV-35C
HVOI
CYM1611LHV-35MB
HVOI
CYM1611LHV-45C
HVOI
CYM1611LHV-45MB
2-298
PRELIMINARY CYM1620
CYPRESS
Module II
Features Functional Description (I/Oe - I10 15, 1/00 - 1/07 ) is written into
the memory location specified on the
High-density 1 Megabit SRAM Module The CYM1620 is a very high performance address pins (Ae through A15)'
High speed CMOS SRAMs 1 Megabit Static RAM module organized Reading the device is accomplished~
- Access time - 45 ns as 64K words by 16 bits. The module is taking chip select (CS), ~ select (UB,
constructed using four 32K x 8 Static ~ and output enable (OE) LOW, while
40 pin - 0.6 in. wide DIP package RAM's in Leadless Chip Carriers WE remains inactive or HIGH. Under
JEDEC compatible pin-out mounted onto a double sided multilayer these conditions, the contents of the
Low active power - 1.9 W (max) ceramic substrate. A decoder is used to memory location specified on the address
interpret the higher order address A 15 and pins will appear on the appropriate data
Hermetic SMD Technology select one of the two pairs of RAMs. input/output pins.
TTL compatible inputs and outputs
Writing to the memory module is accom- The input/output pins remain in a high
Commercial and Military plished when the chip select (CS), byte impedance state when chip select (CS),
Temperature Ranges select (UB, LB) and write enable (WE) byte select (UB, LB) or output enable
2 V data retention (L version) inputs are both LOW. Data on the (OE) is HIGH, or write enable (WE) is
input/output pins of the selected byte LOW.
AO-A14----~lL5--------------.------------, A 15 Vee
~--------------------~~----------. rn WE
1/15 US"
~--------------~,r~------_, 1/0 14 LB
1/0 13 A14
1/0 12 A 13
1/0 11 A12
1/0 10 All
1/0 9 AlO
A15 -----.----l I/Os A9
rn ---,.-+---l GND GND
L..--.----I 1/08 - 1/0 15 1/0 7 As
DB --4-+-----' 1/0 6 A7
1/0 5 A6
1/0 4 A5
1/0 3 A4
1/0 2 A3
1/1 A2
1/0 0 Al
TIE Ao
1/0 -1/07 DIP
1620-1 1620-2
Selection Guide
1620HD-45 1620HD-55
Maximum Access time (/1s) 45 55
Commercial 340 340
Military 340 340
Commercial 80 80
Military 80 80
2-299
~PRESS
~, SEMICONDUcrOR
PRELIMINARY CYM1620

Storage Temperature ..................... -65C to + 150C Ambient
Range
Temperature Vee
Commercial OOC to +70 oC SV 10%
Power Applied ......................... -55C to + 125 C
Supply Voltage to Ground Potential ........ , -0.5V to + 7.0V Military -55C to + 12SoC SV 10%


CYM1620HD
l)arameters Description Test Conditions Units
Min. Max.
\1H Input HIGH Voltage 2.2 Vee V
\1L Input LOW Voltage -0.5 0.8 V
IIX Input Load Current GND ~ \'I ~ Vee -15 +15 ~
loz Output Leakage Current GND ~ Va ~ Vee, Output Disabled -15 +15 j.lA
los Current[!) Vee = Max., VOUT = GND -300 rnA
Vee Operating Vee = Max., lOUT = OmA rnA

Icex16 340
Supply Current CS, VB, & LB = VIL
Icex8 Supply Current CS = VIL, VB or LB = VIL
Automatic CS [2) Max. Vee, CS ~ VIH, 80 rnA
IsB! Power Down Current Min. Duty Cycle = 100%
Automatic CS [2) Max. Vee, CS ~ Vee - O.3V,

ISB2 VIN ~ Vee - O.3V or 80 rnA
Capacitance[3)

pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the 2. A pull-up resistor to \(:e on the es inpu t is req uired to keep the device
short circuit should not exceed 30 seconds. deselected during Vee power-up, otherwise ISB will exceed values
given.

5V~ 5V~
3.0V-----
90%
OUTPUT OUTPUT
J 30pF _ 2550
R2
I 5 2550 pF
R2
GND ----'1
- - -- -- ~5ns
INCLUDING INCLUDING
SCOPE SCOPE 1620-3

Equivalent to: THEVENIN EQUlVALENT
1670 1620-5
OUTPUT 0----'Vvv---0 1.73V
2-300
~PFESS
.~[CONDUCTOR
PRELIMINARY CYM1620
Switching Characteristics Over Operating Range [4[

1620HD-4S 1620HD-SS
Min. Max. Min. Max.
READ CYCLE
fI
tLZOE OE'LOW to LOWZ 5 5 ns
tLZCS CS LOW to Low Z(6) 5 5 ns
tHZCS CS HIGH to High Z [5, 6) 20 25 ns
tpu CS LOW to Power Up 0 0 ns
tpD CS HIGH to Power Down 45 55 ns
WRITE CYCLE (7)
tRA Address Hold from Write End 5 5 ns
tpWE WE Pulse Width 25 30 ns
tLZWE WE HIGH to Low Z(6) 5 5 ns
tHZWE WE LOW to High Z[S, 6) 0 15 0 25 ns
Notes:
4.Test conditions assume signal transition times of 5 ns or less, timing 7.The internal write time of the memory is defined by the overlap of ~
reference levels ofl.5V, input levels of 0 to 3.0V and output loading of WW and WE WW. Both signals must be WW to initiate a write and
the specified lodloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5.tHZCS and tHzWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
Transition is measured 500 mV from steady state voltage.
8.WE is HIGH for read cycle.
6.At any given temperature and voltage condition, t HZCS is less than
9.Device is continuously selected, ~ = VILand DE = VIL.
t LZCS for any given device. These parameters are guaranteed and not
100% tested. IO.Address valid prior to or coincident with CS transition low.
11.Data liD will be high impedance if OE" = VIH
2-301
~PFESS
WnMICONDUcrOR
PRELIMINARY CYM1620
Data Retention charactenstlcs (L Version Only)

CYM1620
Min. Max.
IceDR Data Retention Current Vee = 2.0V, 16 mA
CS ~ Vee - O.2V
tCDR(13) Chip Deselect to Data Retention Time 0 ns
\iN ~ 'te - O.2V
tR[l3) Operation Recovery Time s:
or \iN O.2V tRe(12) ns
ILl (13) Input Leakage Current 8 ~
Notes:
12. tRe = Read Cycle Time. 13. Guaranteed, not tested.
DATA RETENTION MODE -::i

t:j:. . ,.-_4_.5_V:~....._ _ _ _VO_R_;;::_2V_ _ _ _ _/~~ l
c
'/2 Z /Z7fv'H OR
V ''''--~'''''I\-S--S--S-S~S-
162Q.8

)k--
=t=t_~~
ADDRESS
~===================D=A=T=A=V=AL=I=D===============:
DATA OUT
PREVIOUS DATA VAUO
1620-7
2-302
~~, PRELIMINARY CYM1620

EI
tRC
~k" -.:ilL
tACS
...:l~ ~~
tDOE I-t--- tHZOE-
tLZOE t HZCS
HIGH IMPEDANCE ~ HIGH IMPEDANCE

DATA OUT ////11
'\ '\ '\ '\ ., DATAVAUD
~
14-- tLZcs-
~E-50%---------:?i-+-.)l....-lee
Vee _ __....Jf 14-- tpu
14---- t pD
SUPPLY
CURRENT
~ISB
1620-8
Write Cycle No.1 (WE Controlled) [7,11)
ADDRESS -- -;: f

twc
~~
tscs
\. \. \ ! \ .\ . . \..-lk- - 'q/7/ [7/////////
tAW t HA -
tSA t pWE
1
WE .3k-\. \.~ r ~~
I I
r tSD l tHO
DATA IN
*" "*
DATA-IN VAUD
1 'I
~ tHZWE LZWE
- t -
HIGH IMPEDANCE
1620-9
Write Cycle No.2 (CS Controlled)[7,l1)
--
twc
~If
...;:
ADDRESS ~
tSA tscs
:l
-T -~
I tHA
tAW
tpWE
WE \..\..\.\..\..\..\..\..\..\..\.\..\..\.\..\.\..\.\..\.\..\.~~ -~/ / / / / / / / / / ///L
r tSD 1 tHO
DATA IN
"* *
DATA-IN VALID
'I 'I
DATA I/O _ _ _ _ _ _D_A_TA_u_N_DE_F_IN_ED_ _ _ _ _ _ _ _ _ _ _ _
14- tHZWE
l_ HIGH IMPEDANCE
1620-10
2-303
.
~~~
~
" CYPRESS
SEMICONDUCTOR
PRELIMINARY CYM1620

Speed Ordering Code
H X X X X HighZ Deselect Power Down Type Range
L H H X X HighZ Deselect Power Down 4S CYM1620HD-4SC HD03 Commercial

L L L L H Data OutO-IS Read CYM1620LHD-4SC HD03
L H L L H Data OutO-7 Read Lower Byte CYM1620HD-4SMB HD03 Military
L L H L H Data Out8-IS Read Upper Byte CYM1620LHD-4SMB HD03
L X L Write SS CYM1620HD-SSC HD03 Commercial

L L Data InO-IS
CYM1620LHD-SSC HD03
CYMl620HD-SSMB HP03 Military
L L H X L Data In8':'IS Write Upper Byte
CYM1620LHD-SSMB HD03
L L L H H HighZ) Deselect
2-304
CYM1621
CYPRESS
Module II
Features Functional Description on the data lines (Dx) is written into the
memory location specified on the address
High-density 1 Megabit SRAM Module The CYM1621 is a high performance pins (Ao through Als).
High speed CMOS SRAMs I-Megabit Static RAM module organized
as 64K words by 16 bits. This module is
- Access time - 25 ns taking the chi~lect (CSxx) LOW, while
constructed from sixteen 64K x 1 SRAMs
Customer configurable - x4, xS, x16 write enable (WE) remains HIGH. Under
in I..eadless Chip Carriers mounted on a
these conditions the contents of the mem-
Low active power - 6.S W (max) ceramic substrate with pins. Four separate
ory location specified on the address pins
Hermetic SMD Technology CS pins are used to control each 4-bit
will appear on the data lines (Dx).
nibble of the 16-bit word. This feature
TTL compatible inputs and outputs permits the user to configure this module The Data output is in the high impedance
Low profile as either 256K x 4, 128K x 8 or 64K x 16 state when ch~nable (CSxx) is HIGH or
organization through external decoding write enable (WE) is LOW.
- Max. height - .270 in.
and appropriate pairing of the outputs. Power is consumed in each 4-bit nibble
Small PCB footprint - 2 sq in.
Writing to the device is accomplished only when the appropriate CS is enabled,
2 V data retention (L version) thus reducing power in the x4 or x8 mode.
when the chip select (CSxx) and write
enable (WE) inputs are both LOW. Data

AO-A15 ~1~6~-r __________~__________' -________~
GND
WE ----r+--------r+--------r4------~
D15
eS O- 3 ---ri-t-------.-~~------.-~------~ ~12-15
D4
WE
A1
D14
A2
eS4- 7 ---r~t_------,-~--------~~------~ D5
A3
A4
D13
A5
D6
eSS- 11 ---r;-+-------,-~~------T_~------~
A6
A14
D12
~4-7
D7
A15
eS12- 15 ---ri-t-------,-t-1I--------'T""'~------~
DIP
L -_ _ _ _ _ _ _----L__________--L.__________ ..L__--L!1~6~ Do -D
15
1621-1 16212
Selection Guide
1621HD-25 1621HD-30 1621HD-35 1621HD-45

Commercial 1250 1250 1250 1250
Military 1250 1250 1250
Commercial 320 320 320 320
2-305
~PRESS
WnMICONDUCTOR
CYM1621
Maximum Ratings
Storage Temperature ..................... -65C to + 150C Static Discharge Voltage ................ ; ........ >2001V
Power Applied ......................... -55C to + 125C Latch-up CUrrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Operating Range
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V Range
Temperature Vee
DC Input Voltage ........................ -3.0V to + 7.0V OOC to +70 o C
Commercial 5V 10%
Output CUrrent into Outputs (Low) .................. 20 rnA
Military [4) -55C to + 125C 5V 10%

CYM1621HD
Min. Max.

. I IOL = 8.0 rnA Military
0.4 V
Vee = Mm. I.
IOL = 12.0 rnA Commercial
'iH Input HIGH Voltage 2.2 Vee V
'iL Input LOW Voltage -3.0 0.8 V
lJx Input Load Current GND ~ \'I ~ Vee -20 +20 ~
Ioz Output Leakage CUrrent GND ~ Vo ~ \te, Output Disabled -20 +20 ~
los CUrrent [1) Vee = Max., VOUT = GND -350 rnA
Vee Operating Supply Vee = Max., lOUT = 0 rnA

leex16 1250 rnA
CUrrent by 16 mode CSxx ~VIL
850 rnA
leexs CUrrent by 8 mode CSxx ~VIL
Vee Operating Supply Vee = Max., lOUT = 0 rnA 650
leCx4 CUrrent by 4 mode CSxx ~VIL rnA
Automatic CS [2) Max. Vee, CSxx ~ \1H
IsB1 Power Down CUrrent Min. Duty Cycle = 100% 320 rnA
Automatic CS[2) Max. Vee, CSxx ~ Vee - 0.3V,

IsB2 Power Down CUrrent VIN ~ Vee - 0.3V or VIN ~ 0.3V 320 rnA
Capacitance[3)
CIN Input Capacitance TA= 25C,f = 1 MHz 130
pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 3. Tested initially and after any design or process changes that may affect
short circuit should not exceed 30 seconds. these parameters.
2. A pull-up resistor to Vee on the es input is required to keep the device 4. TA is the "instant on" case temperature.
deselected during Vee power-up, otherwise ISB will exceed values
given.
2-306
~~~ CYM1621
1621HD-25 1621HD-30 1621HD-35 1621HD-45

READ CYCLE
tRe Read Cycle Time 25 30 35 45 ns
tLZes CS LOW to Low Z(7) 5 5 5 5 ns
tHZCS t;S' HIGH to High Z[6. 7) 20 25 30 30 ns
WRITE CYCLE (8)
twe Write Cycle Time 25 30 35 45 ns
tses CS LOW to Write End 22 25 30 40 ns
tLzWE WI! HIGH to Low Z(7) 5 5 5 5 ns
tHZWE WE LOW to High Z[6. 7) 0 20 0 25 0 25 0 25 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing 8. The internal write time of the memory is defined by the overlap of rS'
reference levels of 1.5V, input levels of 0 to 3.0Vand output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified ladloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
6. t HZCS and tHzWE are specified with CL = 5 pF as in Figure lb. setup and hold timing shou)d be referenced to the rising edge of the
tLZCS for any given device.
10.Device is continuously selected, es = V1L
I1.Address valid prior to or coincident with es transition LOW.
OUTPUT
5V
~ ~62Q
J-
R1 3290
(481 0 MIL)
30 pF
_-
OUTPUT
(255 0 MIL)
5V
F R1 3290
(481 0 MIL)
J- -_~62Q
5 pF
(255 0 MIL)
3.0V-----
GND ----'I
~5ns
90%
INCLUDING INCLUDING
JIG AND JIG AND
Equivalent to: THEVENIN EQUIVAlENT

1670 1250
OUTPUT ~ 1.73V OUTPUT ~ 1.90V
1621-6
Military 1621-5 Commercial
2-307

wn
.' CYPRESS
SEMICONDUCTOR
CYM1621
Data RetentIOn characterlstIcs (L Version Onlv)

CYM1621
Min. Max.
\bR Vee for Retention of Data 2.0 V
Chip Deselect to Data Retention Time CS ~ Vee- 0.2V
tcDR 0 ns
\iN ~ \te - O.2V
tR Operation Recovery Time or\iN~ O.2V tRe(12) ns
ILl Input Leakage Current 10 ~
Notes:
J=- DATA RETENTION MODE :-1

tc,. . _-4-.5-vf-------\'o-~-:---2-V----. . /1~5:=L
..V-,H- -
,...Z-,-Z.,.Z-,....Z-,-Z"""7fv ''''--VIH~S~Sr-'''''r'S-Sr--''C\~
16217

Read Cycle No. 119 ,10)
ADDRESS
~t_~~
~ tAC
*--
~===================D=A=T=A=V=A=LI=D================
DATA OUT
PREVIOUS DATA VAUD
16211
2-308
~PRESS
.~ICONDUCTOR
CYM1621

II
t RC
~ -J.
~
tACS
f4-- tLZCS- t HZCS
DATA OUT
HIGH IMPEDANCE 11////11 , HIGH IMPEDANCE
" '\ '\ '\ '\ '" DATA VALID
f4- 14-
-1-
tpu t pD
Vee
SUPPLY
CURRENT
1621-9
Write Cycle No.1 (WE Controlled) [8]
ADDRESS -- -: f
L
twc
tscs
-3~
'\.,\\ 1,\'\.'\.~ - ~ V/////////

tAW t HA -
tSA -I tPWE
WE ~\. '\..... ~ ,t..

I
I
tSD 1 tHO
DATA IN
"*
--3f- DATA-IN VALID
I
f4-- t HZWE - ~ t LZWE -
HIGH IMPEDANCE
1621-10

twc
~
ADDRESS
- ~
tSA -y
.-T
tscs
~f-
-~
.1 tHA
tAW
tPWE
WE '\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.\.'\.'\~~\.'\'\~~ -~// / / / / // / / / / / /
I
r tSD 1 tHO
DATA IN
*" *"
DATA-IN VALID
I ~ t HZWE I
DATA OUT _____--O-AT-A-U-ND-E-FI-NE-D----_--------:1- HIGH IMPEDANCE
1621-11
Note: IfCS goes HIGH simultaneouslvwith WE HIGH, the output remains in a high impedance state.
2-309
~PF2S
.nEMICONDUcrOR
CYM1621
Truth Table
CS xx WE Input/Outputs Mode
L H Data Out Read
L L Data In Write
Package Operating
Speed Ordering Code
Type Range
25 CYM1621HD-2SC HD02 Commercial
CYM1621LHD-2SC HD02
30 CYM1621HD-3OC HD02 Commercial
CYM1621LHD-3OC HD02
CYM1621HD-30MB HD02 Military
35 CYM1621HD-35C HD02 Commercial
CYM1621LHD-35C HD02
CYM1621LHD-3SMB HD02
CYM1621LHD-45C HD02
ADVANCED INFORMATION CYM1622
CYPRESS
SEMICONDUCTOR 64K x 16 Static RAM
Module fI
Features Functional Description Reading the device is accomplished by
taking chip select ~ and output enable
High-density 1M bit SRAM Module The CYM1622 is a very high performance (OE) LOW, while WE remains inactive or
High speed 1M-bit Static RAM module organized HIGH. Under these conditions, the con-
as 64K words by 16 bits. The module is tents of the memory location specified on
- Access time - 30 ns constructed from four 64K x 4 SRAMs in the address pins will appear on the sixteen
16 bit wide organization Leadless Chip Carriers mounted on a ce- data input/output pins.
40 pin Vertical DIP ramic substrate with pins. A vertical DIP
format minimizes board space (footprint The input/output pins remain in a high
Low active power - 1.8 W impedance state unless the module is
= 0.45 sq in.) while still keeping a maxi- selected, outputs are enabled, and write
Hermetic SMD Technology mum height of 0.5 in.
TTL compatible inputs and outputs enable (WE) is HIGH.
Writing to the memory module is accom-
Low profile plished when the chip select (CS) and
- Max. height - 0.5 in. write enable (WE) inputs are both LOW.
Data on the sixteen input/output pins (Do
Small PCB footprint - 0.45 sq in.
through D II,) is written into the memory
2V data retention (L version) location specified on the address pins (Ao
through A 15).
Logic Block Diagram Package Configuration
Ao-A15~~16--------~----------------~
~--------~~----------~
WE -----r--+-+-------,
OE" ---r--+-+--I------,
D 2.0"
1622-1
D
_....-....._..c==:J.,;;,--.1 0.22"
f
1622-2
2-311
CYM1623
CYPRESS
Module
Features Functional Description (lIOe - I/O,!!, I/Oo - 1/07) is written into
the memory location specified on the
High-density 1 Megabit SRAM Module The CYM1623 is a high performance address pins (Ao through A,!!).
High speed CMOS SRAMs 1 Megabit Static RAM module organized
Reading the device is accomplished~
as 64K words by 16 bits. The module is
- Access time - 70 ns taking chip select (CS), b~ select (UB,
constructed using four 32K x 8 Static LB) and output enable (OE) LOW, while
40 pin - 0.6 in. wide DIP package RAMs in Leadless Chip Carriers mounted WE remains inactive or HIGH. Under
JEDEC compatible pin-out onto a double sided multilayer ceramic
these conditions, the contents of the
Low active power - 1.3 W (max) substrate. A decoder is used to interpret
memory location specified on the address
the higher order address AUI and select
Hermetic SMD Technology pins will appear on the appropriate data
one of the two pairs of RAMs.
input/output pins.
TTL compatible inputs and outputs Writing to the memory module is accom- The input/output pins remain in a ~h
Commercial and Military plished when the chip select (CS), ~ impedance state when chip select (CS),
Temperature Ranges select (UB, LB) and write enable (WE)
~ select (UB, LB) or output enable
2 V data retention (L version) inputs are both LOW. Data on the
(OE) is HIGH, or write enable (WE) is
input/output pins of the selected byte LOW.
AO-A14----~lL5--------------,-----------, A15
~
~----~---------r+-------,
1/15
~------------_,rr+-----~ 1/0 14
1/0 13
1/0 12
1/11
1/10
1/9
A15 ---~--I
II0a
~ -----.--+---1 GND
1...--.----1 1/0 7
tm--+-+----' 1/6
1/0 5
1/0 4
1/0 3
1/0 2
1/0 1
1/0
~
DIP
1623-1 1623-2
SeIection GUlde
1623HD-70 1623HD-85 1623HD-I00
Commercial 70 70 70
Military 70 70 70
2-312
~
IIIIf ~PRESS CYM1623
~, SEMICONDUCTOR

(Above which the useful life may be impaired.) Ambient
Range Vee
Storage Temperature ..................... -65C to + 150C Temperature
Power Applied ......................... -55C to + 125C
Supply Voltage to Ground Potential. . . . . . . .. -0.3V to + 7.0V
Commercial
Military
OC to +70C
-55C to + 125C
5V 10%
5V 10% II
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.3V to + 7.0V
. f ICS 0 ver 0'peratmg R ange

' I Charac t ens
EIec trICa
CYM1623HD
Min. Max.
IIX Input Load Current GND ~ Vi: ~ Vee -10 + 10 jJA
loz Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -10 +10 jJA
Vee Operating Vee-=-Max~OUT = 0 rnA
leCx16 Supply Current CS, VB, & LB = VIL 240 rnA
Vee Operating Vee = Max., I OUT = 0 rnA

120 rnA
leexs Supply Current CS = VIL, VB or LB = VIL
Automatic CS [2] Max. Vee, CS ~ VIH, 70 rnA
IsBl Power Down Current Min. Duty Cycle = 100%
Max. Vee, CS ~ Vee - 0.2V,
Automatic CS [2]
IsB2 VIN ~ Vee - 0.2V or 20 rnA
Capacitance [3]
pF
COUT Output CapacitanCe \te = 5.0V 40
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. A pull-up resistor to \Ce on the rs input is required to keep the device
given.
OUTPUT 5V~
R2
I 30PF 6670
--
R1 10000
--
OUTPUT 5VT-i J
R1 1000 0
5pF
R2
_ 6670
3.0V-----
GND---""I
~5ns
All Input Pulses
90%
- -
INCLUDING INCLUDING
JIG AND JIG AND 16233
SCOPE SCOPE 1623-4

4000
OUTPUT o----vvv----o 2.0V 1623-5
2-313
5r~oocroR CYM1623
Switching Characteristics Over Operating Range [4J
1623HD-70 1623HD-85 1623HD-I00

READ CYCLE
tACS CS LOW to Data Valid 70 85 100 ns
tnoE OE LOW to Data Valid 40 50 60 ns
tLZOE trn LOW to Low Z 5 5 5 ns
tHZOE OE HIGH to High Z 35 35 40 ns
tLZCS CS LOW to Low Z[6J 5 5 5 ns
tHZCS CS HIGH to High Z [5, 6J 35 35 40 ns
WRITE CYCLE [7J
tSD Data Set-uJ> to Write End 20 20 25 ns
tLzwE WE HIGH to Low Z[6J 5 5 5 ns
tHZWE WE LOW to High Z[S,6J 0 30 0 35 0 40 ns
Notes:
4.Test conditions assume signal transition times of 5 ns or less, timing 7.The internal write time of the memory is defined by the overlap of a;
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified IodIoHand 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
5.t Hzcs and t HZWE are specified with CL = 5 pF as in Figure lb.
signal that terminates the write.
Transition is measured 500 mV from steady state voltage.
S.WE is HIGH for read cycle.
6.At any given temperature and voltage condition, tHZCS is less than
9.Device is continuously selected, a; = V1Land OE = V1L.
t LZCS for any given device. These parameters are guaranteed and not
100% tested. 10.Address valid prior to or coincident with CS transition low.
1l.Data 110 will be high impedance if OE" = VIH
2-314
~PRESS
.nMICONDUCTOR
CYM1623
Daa
t R
e en . f ICS
t fIon Ch arac t erls (LVerslon 01)
fli'
CYM1623
Min. Max.
\bR
IeeDR
Vee for Retention Data
Data Retention Current
Vee = 2.0V,
CS ~ Vee - 0.2V
2.0
250
V
}JA
II
teDR[I3) Chip Deselect to Data Retention Time \iN ~ \te - 0.2V 0 ns
or \iN:::;; 0.2V
tR(13) Operation Recovery Time tRe(12) ns
Notes:
12. t RC = Read Cycle Time. 13. Guaranteed, not tested.
DATA RETENTION MODE -:i

tC:t. .1--_4._5v_f-----V.-:-:-R~-2-V-------'/I~~l
' ' ' Z' ' ' Z--''-Z'' ' 'Z--''-Z'' ' >fvir-V1-H ----". '''--~'''''~H
~-S-orS--S~S \~ ...
1623-6

Read Cycle No.
*--
1[8,9)
=fto~~~
ADDRESS
~====================D=A=TA==V=AL=I=D=================
DATA OUT
PREVIOUS DATA VAUD
16237
2-315
~PFESS
_~MICONDUcrOR
CYM1623

Read Cycle No. 2[8, 101
t RC
~~
tACS
.... '"
.... (' ~~
tOOE ~ t HZOE -
t LZOE t HZCS

DATA OUT DATA VALID
"-~"'I'
I+-- t LZcs -
1623-8
Write Cycle No.1 (WE ControlIed)[7,l1)
ADDRESS -- ~ f
I
twc
tscs
~~
\. \. \ I\,\.\'-T ~I{.//// V/////////

tAW t HA -
tSA tpWE
I
WE .3k-\. \...:!!~ ~~
I I I
tSD
.1 tHO
1
DATA IN if
*"
DATA-IN VALID
I I
- tHZWE- I-- tLZWE
HIGH IMPEDANCE
1623-9
Write Cycle No.2 (CS Controlled)[7,ll)
ADDRESS -- ~~
tSA
twc
tscs
~~
I
-f-
tAw
~ tHA
tpWE
WE \. \. \. \. \. \. \. \. \.\.\. ='\."'-\.'\. \. \. \. \. \. \. \. ~ ~ -:,../ / / / ///LL/ / / / /
I
tSD I tHO
DATA IN
*"I I-
DATA-IN VALID
t HZWE.::::1
.,..
*"I 1623-10
HIGH IMPEDANCE
I
2-316
.
~~
~
" CYPRESS
SEMICONDUCTOR
CYM1623

Speed Ordering Code
H X X X X HighZ Deselect Power Down Type Range
L H H X X High Z Deselect Power Down 70 CYM1623HD-7OC HD03 Commercial

L L L L H Data OutO-15 Read CYM1623LHD-7OC HD03
L H L L H Data OutO 7 Read Lower Byte CYM1623HD-70M HD03 Military
L L H L H Data Outs 15 Read Upper Byte CYM1623LHD-70M HD03
L L L X L 85 CYM1623HD-85C HD03 Commercial
Data InO-15 Write
CYM1623LHD-85C HD03
L H L X L Data InO 7 Write Lower Byte
CYM1623HD-85M HD03 Military
L L H X L Data InS 15 Write Upper Byte
CYMI623LHD-85M HD03
100 CYMI623HD-lOOC HD03 Commercial
CYM1623LHD-100C HD03
CYM1623HD-100M HD03 Military
Document #: 3S-M-000ll
CYM1623LHD-100M HD03
2-317
PRELIMINARY CYM1626
CYPRESS
Module
Features Functional Description put pins of the selected byte (1108 -
1101$ 1100 - 1107) is written into the
High-density 1M bit SRAM Module The CYM1626 is a high performance 1M- memory location specified on the address
High speed CMOS SRAMs bit Static RAM module organized as 64K pins (AO through Als).
words by 16 bits. This module is con-
- Access time - 30 ns Reading the device is accomplished~
structed from four 16K x 4 SRAMs
Low active power - 2.4 W (max) in SOJ packages mounted on an epoxy taking chip select (CS), ~ select (UB,
laminate board with pins. ~ and output enable (OE) LOW, while
SMD technology WE remains inactive or HIGH. Under
ITL compatible inputs and outputs Selecting the device is achieved by a chip these conditions, the contents of the
select~u.!2in as well as two byte select memory location specified on the address
Low profile pins (UB, LB) for independently selecting pins will appear on the appropriate data
- Max. height - .50 in. upper or lower byte for read or write input/output pins.
Small PCB footprint - 0.9 sq in. operations.
The input/output pins remain in a high
2V data retention (L version) Writing to the memory module is accom-
impedance state when chip select (CS),
plished when the chip select (CS), ~
b~ select (UB, LB) or output enable
select (VB, LB) and write enable (WE)
(OE) is HIGH, or write enable (WE) is
inputs are LOW. Data on the input/out-
LOW.

A6
A5
A4
AO-A15~~16---------r---------------' A3
A2
~-----.--4--------., A1
ag
WE - - - - . - - 4 - 4 - - - - - - - . , ...l.
O"E" ---......--1--4-4-------. WE
vee
GND
1/00
1/01
1/02
1/03
1/04
1/05
1/06
I/QZ
Q
L.....-4--I-+-+---__--L.__~~ I/0s - 1/015 OE
1/08
1/09
1/010
1/011
1/012
1/013
1/014
1/015
GND
A.1
L.....______________--L.__ ~~ 1/0 - 1/0 UB
0 7 A7
A8
1626-1 A9
A10
A11
A12
A13
A14--...-w.:::._ _.....
SIP 1626-2
Selection Guide
1626PS-30 1626PS-35 1626PS-45
Maximum Access time (ns) 30 3S 4S
Maximum Operating Current (mA) 440 440 440
Maximum Standby Current (mA) 160 160 160
2-318
~PRESS
WnMICONDUcrOR
PRELIMINARY CYM1626
Maximum Ratings
DC Input Voltage ......................... -O.5V to +7.0V
Power Applied .......................... -lODC to +90 DC
Output Current into Outputs (Low) ................ " 20 rnA
Operating Range
til
Ambient
Range Vee
DC Voltage Applied to Outputs Temperature
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to + 7.0V
Commercial ODC to +70 DC 5V 10%
fICS 0 ver 0Jperatmg R ange
rIcaI Charac t erls
EIec t
CYM1626PS
Min. Max.
IIX Input Load Current GND S\1 SVee -20 +20 pA
Ioz Output Leakage Current GND S Va S Vee, Output Disabled -20 +20 pA
los Current (1) Vee= Max., VOUT = GND -350 rnA
Vee Operating ~e = Max., lOUT = 0 rnA

IcCx16 Supply Current ,tm, &LBSVIL 440 rnA
IcCx8
Vee Operating ~e = Max., 10 $ 0 rnA 290 rnA
Supply Current :S VIL, tm or :S V IL
Automatic CS [2] Max. Vee, CS ~ VIH, 160 rnA
IsB1 Power Down Current Min. Duty Cycle = 100%
Automatic CS [2] Max. Vee, CS ~ Vee - 0.3V,

VIN S 0.3V
:apacitance[3]
CIN Input Capacitance TA = 25OC, f = 1 MHz, 45
pF
COUT Output Capacitance vee = 5.0V 3S
Jotes:
Not more than 1 output should be shorted at one time. Duration of 2. A pull-up resistor to \CC on the ~ input is required to keep the device
the short circuit should not exceed 30 seconds. deselected during \f:c power-up, otherwise ISB will exceed values
given.
~C Test Loads and Waveforms

OUTP~~~ 5V~ R2
3.0V----
90%
OUTPUT
J. 30 pF -=
R2
2550 J. 5 pF -= 2550 GND---"I
S5ns
INCLUDING INCLUDING
SCOPE SCOPE
quivalent to: THEVENIN EQUIVALENT
1670
OUTPUT o----wv--o 1.73V 1626-5
2-319
~~DUC1CO PRELIMINARY CYM1626
1626PS-30 1626PS-35 1626PS-45

READ CYCLE
tM Address to Data Valid 30 35 45 ns
tLZOE Lrn LOW to LOW Z 3 3 3 ns
tHzOE OE HIGH to HIGH Z 20 20 20 ns
tLZCS CS LOW to Low Z [6) 3 3 3 ns
tHZCS CS HIGH to High Z[S, 6) 15 20 20 ns
tpu CS WW to Power Up 0 0 0 ns
tpD CS HIGH to Power Down 30 35 45 ns
WRITE CYCLE [7)

tLZWE WE HIGH to Low Z[6) 3 3 3 ns
tHZWE WE LOW to High Z [5, 6) 0 15 0 15 0 15 ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing 7. The in ternal write time of the memory is defined by the overlap of"CS'
reference levels of 1.5V, input levels of 0 to 3.0V and output loading LOW and WE LOW. Both signals must be LOW to initiate a write and
of the specified lodloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. tHZCS and tHZWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
tLZCS for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = \1Land OE = VII.:
100% tested. 10. Address valid prior to or coincident with CS transition low.
11. rs, VB and LB are represented byCS in the switching Character-
istics and Waveforms.
2-320
~~o5l.ucrOR PRELIMINARY CYM1626

CYM1626
III
Min. Max.
CS ~ Vee - 0.2V
teDR[13) Chip Deselect to Data Retention Time 0 ns
\iN ~ \te - 0.2V
tR[13) Operation Recovery Time or\fN~ 0.2V tRe[12) ns
IU[13) Input Leakage Current 5 IlA
Notes:
:J: DATA RETENTION MODE ":1

t
c
~~
: ]....:_ _4_.5_V _____ VD_~-R~_2V___--/i~~R =L
I""Z~/""'-z--z""'z-7fv"""""VIH-- '--~-I~H '-'-,-,,-,,--'-S-S-
1626-6

ADDRESS~I~_=-_tRC
-f.- tAA~.1 t oHA - - /
_ _ *__
DATA OUT
PREVIOUS DATA VAUD ====================D=A=TA==VA=L=ID==================
1626-7
2-321
~~~ PRELIMINARY CYM1626

t Rc
~ It" ...,l-
t ACS
.J~ -.~
tOOE I--- t HZOE -

tLZOE t HZCS
HIGH IMPEDANCE / / / / II HIGH IMPEDANCE

DATA OUT
~tLZCS-
" \. \. \. \. I" DATAVAUD
i4---- t pD
~ tpu
=j
VCC
SUPPLY
CURRENT ---1c- 5O%~ISB
ICC
1626-8
ADDRESS -- """
f
I
twc
~~
"" """-T
tscs
-:: "-//// V/////////
\ tAW t HA -
tSA t PWE
I
WE ~"-\.-' ~ _7"-
I
tSD tHO
DATA IN -3{- DATA-IN VAUD -3{-
~ t HZWE - - t
LZWE
-
HIGH IMPEDANCE
1626-9
Write Cycle No.2 (CS Controlled)[7)
ADDRESS -- ~
~
tSA
twc
~t
I tscs
-.'f-
tAw
~ tHA
t pWE
""""""""""""""""""""""~[""
WE """}'f-/ / / / / / / / / / / / / /
I
L
tSD I tHO
DATA IN
*"I DATA-IN VALID
*
DATA OUT _______DA_T_A_uN_D_EF_IN_E_D_ _ _ _ _ _ _ _ _ _ _ _
I- t HZWE
l_ HIGH IMPEDANCE
I
1626-10
2-322
~'::b PRELIMINARY CYM1626
~
. CYPRESS
SEMICONDUCTOR
Truth
Table
CS UB LB OE WE Input/Outputs Mode
H X X X X HighZ Deselect Power Down
L H H X X HighZ Deselect Power Down
L L L L H Data OutO-lS Read Word
L H L L H Data OUtO-7 Read Lower Byte
L L H L H Data Out S-15 Read Upper Byte
L L L X L Data InO-lS Write Word
L L H X L Data InS-IS Write Upper Byte
Package Operating
Speed Ordering Code
Type Range
30 M1626PS-3OC PS02 Commercial
M1626LPS-30C PS02
35 M1626PS-3SC PS02
M1626LPS-35C PS02
45 M1626PS-45C PS02
M1626LPS-4SC PS02
2-323
PRELIMINARY CYM1641
CYPRESS
Module
Features Functional Description Data on the data lines (Ox) is written into
the memory location specified on the ad-
High-density 4 Megabit SRAM Module The CYM1641 is a high performance dress pins (Ao through A 17).
4-Megabit Static RAM module organized
High speed CMOS SRAMs as 256K words by 16 bits. This module is Reading the device is accomplished by
- Access time - 25 ns constructed from sixteen 256K x 1 SRAMs taking the chip select (CSxx) LDW, while
in Leadless Chip Carriers mounted on a write enable (WEU,L) remains HIGH. Un-
Customer configurable - x4, x8, x16
ceramic substrate with pins. Four separate der these conditions the contents of the
Low active power - 7.2 W (max) CS pins are used to control each 4-bit nib- memory location specified on the address
Hermetic SMD Technology ble of the 16-bit word. This feature per- pins will appear on the data lines (Ox).
mits the user to configure this module as
TTL compatible inputs and outputs either 1M x 4, 512K x 8 or 256K x 16 or- The Data output is in the high impedance
ganization through external decoding and state when chip enable (C"Sxx) is HIGH or
Low profile
appropriate pairing of the outputs. write enable (WEU,L) is LDW.
Writing to the device is accomplished Power is consumed in each 4-bit nibble
Small PCB footprint - 2.2 sq in. when the chip select (CSxx) and write only when the appropriate CS is enabled,
2 V data retention (L version) enable (WEU,L) inputs are both LDW. thus reducing power in the x4 or x8 mode.

Ao-A17 -.:.18: r-_.--____--r _ _ _ _ _-r-_ _ _ _--.
WEL-----r-~-----~-+--------~+-------,
CS _ ---,-+_~-----r_t_+-----.......,._+_+_----_..,
O3
CS4- 7 -~~~-----~~-----~~+-----~
WEu ____~~-----~_+-------~+_----__
CS8-11---r+_~----r_t_+------.......,.~+_----_..,
CS12- 15 ---r+_t------r_t_+------.......,.~+_----___,
DIP
1641-1 TOP VIEW 1641-2
Selection Guide
1641HD-25 1641HD-35 1641HD-45 1641HD-55
Maximum Access time (ns) 25 35 4S SS
Maximum Operating Current (mA) Commercial 1310 1310 1310 1310

Military 1310 1310 1310
Maximum Standby Current (mA) Commercial 320 320 320 320
2-324
C~PRESS
~, SEMICONDUcrOR
PRELIMINARY CYM1641
Maximum Ratings
Storage Temperature ......... , ........... -65C to + 150C Static Discharge Voltage ......................... >2001V
Power Applied ......................... -55C to + 125C Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Operating Range
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V Ambient
Range Vee
Temperature
DC Input Voltage .......................... -3.0V to 7.0V
Commercial OOC to +70C 5V 10%
Military [4) -55C to + 125C SV 10%
CYM1641HD
Min. Max.

. I IOL = 8.0 rnA
Vee = Mm.
Military
0.4 V
I IOL = 12.0 rnA Commercial
\fH Input HIGH Voltage 2.2 Vee V
\fL Input LOW Voltage -3.0 0.8 V
IIX Input Load Current GND :s;; \'l :s;; Vee -80 +80 J.lA
loz Output Leakage Current GND :s;; Va :s;; Vee. Output Disabled -10 +10 J.lA
los Current [1) Vee = Max., VOUT = GND -350 rnA
Icex16
Vee Operating Supply Vee = Max., lOUT = 0 rnA 1310 rnA
Current by 16 mode CSxx :s;; VIL
Icex8 Current by 8 mode CSxx :s;; VIL 850 rnA
Icex4 Current by 4 mode CSxx :s;; VIL 650 rnA
Automatic CS [2) Max. Vee, CSxx ~ \'lH 320 rnA
Automatic CS [2) Max. Vee, CS xx ~ Vee - O.3V,
IsB2 Power Down Current VIN ~ Vee - 0.3V or VIN :s;; 0.3V 320 rnA
Capacitance[3)
TA = 25C, f = 1 MHz pF
Notes:
1. Not more than 1 ou tpu t should be shorted at one time. Duration ofthe 3. Tested initially and after any design or process changes that may affect
2. A pull-up resistor to Vee on the es input is required to keep the device 4. TA is the "instant on" case temperature.
given.
2-325
~~DUC1O' PRELIMINARY ~lMl
Switching Characteristics Over Operating Range (S]

1641HD-25 1641HD-35 1641HD-45 1641HD-55
READ CYCLE
tLZCS CS WW to Low Z(7] 3 3 3 3 ns
tHZCS ~HIGH to High Z(6,7] 15 20 25 25 ns
tpu CS WW to Power Up 0 0 0 0 ns
tPD CS HIGH to Power Down 25 35 45 55 ns
WRITE CYCLE (8]

tscs CS WW to Write End 25 35 45 55 ns
tpWE ~ Pulse Width 25 35 35 35 ns
tLzwE ~ HIGH to Low Z(7] 3 3 3 3 ns
tHZWE WE WW to High Z(6,7] 0 20 0 25 0 25 0 25 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing 8. The internal write time of the memol}' is defined by the overlap oft;S'
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of WW and~ WW. Both signals must be WW to initiate a write and
6. t HZCS and tHzWE are specified with C1. = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
tLZCs for any given device.
10.Device is continuously selected, CS = VII..
11.Address valid prior to or coincident with CS transition WW.
12.CS 0-3, ~4-7, CSS- ll , and CS12-1S are represented by ~ and
WEu and WEL are represented by WE in the switching characteris-
tics and timing waveforms.

R1 3290 R1 3290
OUTP: B(481 0 MIL) OUTP~~ T-}(481
0 MIL) 3.0V----
90%
30 pF
R2
2020 I':' 5 pF R2
2020 GND---""I
I':' ':' (255 0 MIL) ':' (255 0 MIL) :S: 5 ns
INCLUDING INCLUDING
JIG AND JIG AND

1670
OUTPUT ~ 1.73V OUTPUT~ 1.90V
1641-6
2-326
~PRSS
WArcoNDucroR
PRELIMINARY CYM1641
Data Retention Characteristics (L Version Onl ')

CYM1641
Min. Max.
\bR
IeeDR
Vee for Retention of Data
Data Retention Current Vee = 2.0V,
2.0
64
V
rnA
fI
CS ~ Vee- 0.2V
teDR Chip Deselect to Data Retention Time 0 ns
\iN ~ 'te - 0.2V
tR Operation Recovery Time or\iN~ O.2V tRe[12) ns
IU Input Leakage Current 32 jJA
Notes:
12. tRc = Read Cycle Time.
DATA RETENTION MODE 1

4.5V
tC:tI"'~I----: ~ ______'
_____
' ' 'z' ' z-''-z'' ' z-''-/'' '>fv'' V1H -~-
VO_R_~_2_V_____
V
OR
~5VtR--./
--- I
\'JH1'S: S:S:S: s:
1641-7
Switching Waveforms [10, 12)
F
ADDRESS
~t~A~~
t~
*--
~===================D=A=T=A=V=AL='D=================
DATA OUT
PREVIOUS DATA VAUO
1641-8
2-327
~PRRSS
.nMICONDUcrOR
PRELIMINARY CYM1641

ReadCycle No. 2[9,10)
t RC
~ -It-
~
tACS
'-- ~
14-- t LZCS - t HZCS
HIGH IMPEDANCE II , , , , II ~ HIGH IMPEDANCE

DATA OUT '" '\ '\ '\ '\ ~
DATA VALID
J
----------~~
I-t- tpu 1---. t pD
=-1 ICC
5O%~ISB
VCC
SUPPLY
CURRENT
1641-9
Write Cycle No.1 (WE Controlled) [8)

twc
-
ADDRESS
- ~ f
I
tscs
~f-
'\ '\ \ 1,\'\.'\T ....., ~7/// V/////////
tAw t HA -
tSA tPWE
1
~,\,,~~ ~~
1
, tSD tHO
DATA IN
r
* "*
DATA-IN VALID
1
I+- t HZWE - I+-- t LZWE -
HIGH IMPEDANCE
1641-10

twc
ADDRESS ~If
- -
~~
tSA tscs
,I
-T j~
I tHA
tAw
tpWE
WE ,\'\.,\'\.,\,\'\.,\'\.'\.,\'\.'\."'\."'\."',\'\.,\~r- -,v'77 / / / / / / / / / / //
.1
1
tSD :1 tHO
DATA IN
DATA OUT ________D_AT_A_UN_D_E_FIN_E_D_ _ _ _ _ _ _ _ _ _ _ _

.~
1 j4-
DATA-IN VALID
t HZWE
~-
-+
HIGH IMPEDANCE
Note: If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 1641-11
2-328

~RESS
WnrCONDUCTOR
PRELIMINARY CYM1641
Truth Table
CS xx WEn Input/Outputs Mode

L H Data Out Read
L L Data In Write
Ordering Code Package Operating
Speed Type Range
25 CYMl641HD-25C HD05 Commercial
CYM1641LHD-25C HD05
CYM1641LHD-35C HD05
CYM1641LHD-45C HD05
CYMl641LHD-45MB HD05
CYM1641LHD-55C HD05
2-329
ADVANCED INFORMATION CYM1804
CYPRESS
SEMICONDUCTOR lK X 32 Static RAM
Module with Separate I/O
Features Functional Description Reading the device is accomplished by
taking the chip select (CS) LOW, while
Ideal for Cache Tag Applications The CYMI804 is a high performance the write enables (WEN) remain HIGH.
High speed CMOS SRAMs 32K-bit Static RAM module organized Under these conditions the contents of
- Access time - 15 ns as lK words by 32 bits. Thismodule is the memory location specified on the ad-
constructed from eight resettable lK x 4 dress pins will appear on the data output
Low active power - 4 W (max)
SRAMs in SOJ packages mounted on pins (OX>.
SMD Technology an epoxy laminate board with pins. The The data output pins stay in the high im-
TTL compatible inputs and outputs module's reset capability combined with pedance state whenever chip select (CS)
84 pin ZIP the 15 ns access time makes it ideal for is HIGH, Reset (RS) is LOW, output en-
cache tag applications. able (DE) is HIGH, or during the writing
Low profile
Writing to the module is accomplished operation when Write Enable (WEN) is
when chip select (CS) and the appropriate LOW.
Small PCB footprint - 1.4 sq in.
write enables (WE, and/or WE2) are both Reset is initiated by selecting the device
Two cycle reset for cache flush LOW. Data on the input pins (IX> is writ- (CS = LOW) and pulsing the reset (RS)
Separate WE for "Valid Bits" update ten into the memory location specified on input LOW. Within two memory cycles all
the address pins (Ao through As). bits are internally cleared to zero.
Logic Block Diagram Package Configuration

r- 0.5
11
-\
Ao-A9~1~0----~------------------------~
~------~r----------------------'
~1------r~+---------------------~
~2------r~+--------------------'
1/0 0 -1/0 3
o
110 8 -1/0 11
110 20 -1/0 23
D D
4.2"
D D
~~~------~------------~--------~
~~----------------------~ 1804-1
D
EJ' T--'- 0.33"
18042
2-330
CYM1821
CYPRESS
Module fJI
Features Functional Description location specified on the address pins
(Ao through A13)'
High-density 512K bit SRAM Module The CYM1821 is a high performance Reading the device is accomplished by
High speed CMOS SRAMs 512K-bit Static RAM module organized as taking the chip selects (CSN) LOW, while
- Access time - 25 ns 16K words by 32 bits. This module is con- write enable (WE) remains HIGH. Under
Low active power - 4 W (max) structed from eight 16K x 4 SRAMs SOJ these conditions the contents of the mem-
packages mounted on an epoxy laminate ory location specified on the address pins
SMD Technology board with pins. Four chip selects (CS 1, will appear on the data input/output pins
TTL compatible inputs and outputs CS2 , CS3 and CS4 ) are used to independ- (I/Ox).
Low profile ently enable the four bytes. Reading or The data input/output pins stay in the
writing can be executed on individual ~ impedance state when write enable
- Max. height - .50 in. bytes or any combination of multiple (WE) is LOW, or the appropriate chip
Small PCB footprint - 1.0 sq in. bytes through proper use of selects. selects are HIGH.
JEDEC compatible pinout Writing to each byte is accomplished Two pins (PDO and PD1) are used to
2V data retention (L version) when the appropriate chip selects (CSN) identify module memory density in
and write enable (WE) inputs are both applications where alternate versions
LOW. Data on the input/output pins of the JEDEC standard modules can be
(IlOx) is written into the memory interchanged.

PDO-GND GND
PD1-0pen PD1
Ao-A13--~14~----r-----------------------,
1/0 8
~------~-------------------, 1/0 9
1/0'0
~-----~~~--------------~ 1/0'1
Ao
A,
1/0 0 -1/0 3 110 4 -1/0 7 A2
1/'2
1/0'3
'CS'1 1/0'4
1/0'5
GND
NC
1/0 8 -1/0 11 1/012 -1/0 15 'CS'2
'CS'2
1/016 -1/019 1/0 20 -1/0 23
'CS'3
110 24 -1/ 27 11 28 -1/0 31
'CS'4
ZIP
Top View
1821-1 '821-2
ISelection Guide
I
1821PZ-25 1821PZ-35 1821PZ-45
2-331
~~DUcnJR CYM1821
Maximum Ratings
(per MIL-STD-883 Method 3015.2)
Power Applied ............................ OC to + 70C Latch-up Current . . . . . . . . . . . .. . . . .. . .. .. . . . .. ... > 200 rnA
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
Operating Range
Ambient
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V Range
Temperature Vee
Output Current into Outputs (Low) . '.' ............... 20 rnA
. f ICS Over Operating Range

' I Ch arac t erls
EIec trIca
CYM1821PZ
Min. Max.
IIX Input Load Current GND :s; VI :s; Vee -20 +20 JJ.A
Ioz Output Leakage Current GND :s; Vo :s; Vee, Output Disabled -20 +20 JJ.A
los Current [1] Vee = Max., VOUT = GND -350 rnA

Ice Supply Current 720 rnA
CSN :s; \iL
Automatic CS [2] Max. Vee; CSN ~ VIH 160 rnA
Automatic CS [2] Max. Vee; CSN ~ 'te - 0.3V,

IsB2 VIN ~ Vee - 0.3V or 160 rnA
Power Down Current
VIN :s; 0.3V
Capacitance[3]
Parameters DeSCription Test Conditions Max. Units

pF
CoUT Output Capacitance Vee =5.0V 35
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. A pull-up resistor to Vee on the C::;S input is required to keep the device
short circuit should not exceed 30 seconds. deselected during \Ce power-up, otherwise ISB will exceed values
given.

5V~ R2 5V~ R2
3.0V----
90%
OUTPUT OUTPUT
J 30pF _ 2550 J 5pF _ 2550 GND---""1

:s; 5 ns
-
INCLUDING
- -
INCLUDING
-
JIG AND JIG AND 18213 18214
SCOPE SCOPE
Equivalent to: THEVENIN EQUIVAlENT
1670 18215
OUTPUT ~ 1.73V
2-332
.
~.'~ , CYPRESS
. , SEMICONDUCTOR
CYM1821
1821PZ-25 1821PZ-35 1821PZ-45

fI
READ CYCLE
tOOE OE LOW to Data Valid 15 25 30 ns
tLZOE (jE LOW to LOW Z 3 3 3 ns
tLZCS CS LOW to Low Z (6) 5 10 10 ns
tHZCS CS HIGH to High Z[5. 6) 10 15 20 ns
tpu CSLOW to Power Up 0 0 0 ns
tpo CS HIGH to Power Down 25 35 45 ns
WRITE CYCLE (7)

tso Data Set-up to Write End 13 15 20 ns
tHO Data Hold from Write End 2 2 2 ns
tLZWE WE HIGH to Low Z(6) 3 5 5 ns
tHzwE WE LOW to High Z [5, 6) 0 7 0 10 0 15 ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing 7. The interna) write time of the memory is defined by the overlap of<:;S'
of the specified IOLlloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. tHZCS and tHzWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
6. At any given temperature and voltage condition. t Hzcs is less than 8. WE is HIGH for read cycle.
tLZCS for any given device. These parameters are guaranteed and not 9. Oevice is continuously selected, CS = VILand OE = VII.:
100% tested. 10. Address valid prior to or coincident with CS' transition low.
11. CSv CS;, CS3 and ~ are represented by CS in the switching Char-
acteristics and Waveforms.
2-333
~~UCTO' CYM1821

CYM1821
Min. Max.
IeCDR Data Retention Current Vee = 2.0V, 8 rnA

Chip Deselect to Data Retention Time CS ~ Vce - 0.2V 0 ns
tCDR[13]
\iN ~ \tC - 0.2V
tRI13] Operation Recovery Time or \iN ~ 0.2V tRC[12] ns
IU[13] Input Leakage Current 10 J.lA
Notes:
~ DATA RETENTION MODE :i:

tc. . !-----V.-:-:-'2N-----/i:~R l
,.--_4_.S_"
,.,.Z-Z.,.Z--Z-Z.,.7fv.....jp-V,H-~ I---"'H~S-S-S-S-S-
1821-6

Read Cycle No.
*--
1[8,9]
ADDRESS ~ 'Re
~ 'CHA----;~
DATA OUT PREVIOUS DATA VAUD ~==================D=A=T=A=V=A=LI=D===============:
18217
2-334
~PRESS
WnMlcoNDucroR
CYM1821

Read Cycle No. 2[8, 10J
fI
t RC
~ ...,~
~
t ACS
..J~ -1iC
tOOE 14---- t HZOE - - - -

t LZoE
tHZCS
HIGH IMPEDANCE II' / / / / II ~ HIGH IMPEDANCE

DATA OUT
I--- tLZcs-
" '\ '\ '\ '\ '" DATAVAUD
VCC _____
I+- t pu
j -----------------------------------------------------~~~-----
50% 50% I ' - - - 19B
ICC
14- tpD
-1
SUPPLY
CURRENT
1821-8
Write Cycle No.1 (WE Controlled) [7J
ADDRESS -- ...;
~
I
twc
~f-
"" l"""-T
tscs
....., ~//// /////////
\ tAW tHA-
tSA -I tpWE
WE .~" '\.~~ ~~
1
tSD tHD
DATA IN ~~
*
DATA-IN VAUD
I-- t HzwE - 14-- tLZWE -
HIGH IMPEDANCE
1821-9
Write Cycle No.2 (CS Controlled)[7J

twc
~ .J1tC
ADDRESS
- t
tSA tscs
:1
-T -IlL
I tHA
tAW
t pwE
WE """,,\.\.\.\.\.\.\.\.\.\.\.\.\.~~~ ...,'qT77/ / / / / / / / / /
--.
r tSD l tHD
DATA IN
*"1 14-
DATA-IN VAUD
*" I
HZWE~>.__
t
~HI~GH~I~M~PE~D~AN~C~E __________________
--------------------------------------- 1821-10
2-335
~PFESS
'nMICONDUCTOR
CYM1821
Truth Table
CSN WE OE Input/Outputs Mode
L H L Data Out Read
L L X Data In Write
Package Operating
Speed Ordering Code
Type Range
25 CYM1821PZ-25C PZOI Commercial
CYM1821LPZ-25C PZOI
3S CYM1821PZ-35C PZOI
CYM1821LPZ-35C PZOI
45 CYM1821PZ-45C PZOI
CYM1821LPZ-45C PZOI
Document #: 38-M-OOOIS
2-336
CYM1822
CYPRESS
SEMICONDUCTOR 16K X 32 Static RAM Module
with Separate I/O
Ell
Features Functional Description LOW. Data on the input pins (DIX> is
written into the memory location specified
High-density 512K bit SRAM Module The CYM1822 is a high performance on the address pins (Ao through A'3).
High speed CMOS SRAMs 512K-bit Static RAM module organized Reading the device is accomplished ~
- Access time - 25 ns as 16K words by 32 bits. This module is taking the chip selects (CSu and/or CSL)
constructed from eight 16K x 4 Separate and ou~enable (OE) LOW, while write
Low active power - 4 W (max) I/O SRAMs in Leadless Chip Carriers enable (WE) remains HIGH. Under these
Hermetic SMD Technology mounted on a ceramic substrate with pins. conditions the contents of the memory
TTL compatible inputs and outputs Two chip selects (CSu and CSd are used location specified on the address pins will
to independently enable the upper and appear on the data output pins (DOX>.
Low profile lower 16-bit Data words.
- Max_ height - .52 in. The output pins stay in the hi@.J..mped-
Writing to the device is accomplished ance state when write enable (WE) is
Small PCB footprint - 1.0 sq in. when the chip selects (CSu and/or CSd LOW, the ~ropriate chip selects are
2V data retention (L version) and write enable (WE) inputs are both HIGH, or OE is HIGH.

GNO vee
010 DOC
011 001
AO-A13~~14~~----------~-----------'-----------' 012 002
013 003
ot---.1-------~r_~----rT------1 014 D04
~---T1~----_._r+_----~~r_--~ 015 005
016 006
01 16- 01 31 "t.+++---.---++-+---.----t-t-+---.--+-t--t----, 017
AO
007
Al
A2 A3
A4 A5
018 008
019 009
0110 0010
0111 0011
0112 0012
0113 0013
0114 0014
0115 0015
~ m
vee GNO
~ ~
0116 0016
0117 0017
0118 0018
0119 0019
0120 0020
0121 0021
0122 0022
0123 0023
A6 A7
A8 A9
~L--------~~--------~~------~-;------~ Al0 All
A12 A13
L....----------'------------.l....-----------L-r::- 00 0 - 0015 0124 0024
0125 0025
0126 0026
0127 0027
18221 0128 0028
0129 0029
0130 0030
0131 0031
GNO vee
VDIP
18222
Selection Guide
1822HV-25 1822HV-30 1822HV-35 1822HV-45
I

Commercial 720 720 720 720
Maximum Operating Current (rnA
Commercial 160 160 160 160
2-337
~PFESS
.nEMICoNDucroR
CYM1822
Maximum Ratings
(per MIlrSTD-883 Method 3015.2)
Power Applied ......................... -55C to + 12SoC Latch-up Current . . . . .. . . . . . . . . . . .. . .. .. . .. . .. .. > 200 rnA
Operating Range
Ambient
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to + 7.0V Range
Temperature Vee
DC Input Voltage ........................ -3.0V to + 7.0V Commercial OOC to +70 oC 5V 10%
Military -55C to + 12SoC 5V 10%

CYM1822HV
Min. Max.
\1:L Input LOW Voltage -3.0 0.8 V
IIX Input Load Current GND~\l ~Vee -20 +20 J.I.A
Ioz Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -20 +20 J.I.A
los Current [1) Vee = Max., VOUT = GND -350 mA
Ice
Vee Operating Vee = Max., lOUT = 0 mA 720 mA
Supply Current CSvCSu ~VIL
Automatic CS (2) Max. Vee; CSu, CSL~ VIH
IsBl 160 rnA
Automatic CS [21 Max. Vee; CSu, CSL~ \te - 0.3V,

IsB2 VIN ~ Vee - 0.3V or 160 mA
Power Down Current
VIN ~ 0.3V
Capacitance(3)
CIN Input Capacitance TA = 2SoC, f = 1 MHz, 70
pF
COUT Output Capacitance \te = 5.0V 35
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the 2. A pull-up resistor to \Ce on the eE input is req uired to keep the device
given.

R1 481 Q R1 481 Q All Input Pulses
5V~ 5V~
3.0V-----
90%
OUTPUT OUTPUT
J 30 pF _ 255
R2
Q J 5 pF
R2
_ 255 Q GND---"l
~5ns
-
INCLUDING
- --
INCLUDING
JIG AND JIG AND 1822'
18223
SCOPE SCOPE

1670
OUTPUT ~ 1.73V 18225 2-338
~PRESS
.nEMICONDUCTOR
CYM1822
SWItC
. h109 Charactenstlcs Over OQe]atingRaJ!ge [4]
1822HV25 1822HV30 1822HV35 1822HV45
READ CYCLE
tLZOE <m LOW to LOW Z 3 5 5 5 ns
tHZCS CS HIGH to High Z[S, 6] 10 15 15 20 ns
WRITE CYCLE [7]

tpWE WE' Pulse Width 20 25 25 30 ns
tHO Data Hold from Write End 3 3 3 3 ns
tHzwE WE LOW to High Z[S, 6] 0 7 0 12 0 12 0 15 ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing 7. The internal write time of the memory is defined by the overlap of~
reference levels of 1.SV, input levels of 0 to 3.0Vand output loading WWandWEWW.BothsignalsmustbeWWtoinitiateawriteand
of the specified JoLlIoH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
S. tHZCS and tHZWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
tLZCS for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = \'JL and OE = VII;
11. Both (;SL and CSuare represented by rS' in the switching Character-
istics and Waveforms.
2-339
~PRSS
WnEMICONDUcrOR
CYM1822
Data Retention Characteristics (!..Version Only

CYM1822
Min. Max.
teDR[l3)
\iN ~ 'Ce - 0.2V
tR[l3) Operation Recovery Time or\fNS 0.2V tRe[l2) ns
IU(13) Input Leakage Current 10 ~
Notes:
12. tRe = Read Cycle Time. 13. Guaranteed, not tested .
1
.Data Retention Waveform
~
DATA RETENTION MODE
<.5V ~ VD_R_~_2V_____
_____ ~5VtR-../
c
t :1:.......- : VcR --- I
''''''Z'''''Z'''''''''Z'''''Z'''''''''Z'''''7fv'''V-
'H
~--_ _ _ _ _....I' V
IH
1'S SSs S
18226

Read Cycle No.1 [8, 9)
ADDRESS
~-tOHA----1-t~~_tRC.,=-~_*-==
DATA OUT PREVIOUS DATA VAUD ~__________D_A_T_A_V_A_Ll_D_ _ _ _ _ _ __
1822-,
2-340
~~~
. ,
~iI CYPRESS
SEMICONDUcrOR
CYM1822

Read Cycle No. 2[8, 101
t RC
~~
tACS
-~
fI
...:It "]~
tDOE \oot-- tHZOE-

t LZOE t HZCS
HIGH IMPEDANCE V////II HIGH IMPEDANCE

DATA OUT DATA VALID
"""'
I\. \. \. \. \ '"
~ t LZCS -
I----
SUPPLY
VCC ___jtw%~ tpu
tpD
=1
50%~ISB
ICC
CURRENT
1822-8
Write Cycle No.1 (WE Controlled) (7)

twc
~
ADDRESS
- f
I
tscs
1~
-'"\. \ .'\'\,\..y - ~ '/////////

tAW t HA -
tSA t pWE
I
WE t'\ '\.~ ~ ~F-
tSD tHD
DATA IN ...,~ DATA-IN VALID

-1f
I+- t HzwE - I--- t LZWE -
HIGH IMPEDANCE
1822-9
twc
~
ADDRESS
- ~
tSA
~I tscs
..3~
-T ~~
I tHA
tAW
tPWE
'\'\'\'\'\.'\'\.'\.'\.'\.'\.'\.'\'\'\'\'\.,,'\.'\'\.'\~--- -f/// / / / / / / / / // /
I
tSD 1 tHO
DATA IN i
*
DATA-IN VALID
DATA OUT DATA UNDEFINED ZW9

---------------------------------------------
I ~ tH E
~. __
I
~HI~GH~I~M~PE~D~AN~C~E ___________________
1822-10
2-341
~PFE.SS
WnEMICONDUcrOR
CYM1822
Truth Table
CSu CSL OE WE Input/Outputs Mode
H H X X HighZ Deselect Power Down
L L L H Data OUtO-3I Read
H L L H Data OutO-IS Read Lower Word
L H L H Data Out16-3I Read Upper Word
L L X L Data In 0-31 Write
H L X L Data InO-1S Write Lower Word
L H X L Data In16-3I Write Upper Word
L L H H HighZ Deselect
H L H H HighZ Deselect
Speed
Type Range
25 CYM1822HV-25C HV02 Commercial
CYM1822LHV-25C HV02
30 CYM1822HV-3OC HV02 Commercial
CYM1822LHV-3OC HV02
CYM1822HV-30MB HV02 Military
CYM1822LHV-30MB HV02
CYM1822LHV-35C HV02
CYM1822LHV-45C HV02
Document #: 38-M-OOOI6
2-342
PRELIMINARY CYM1830
CYPRESS
SEMICONDUCTOR 64Kx 32 Static RAM r:.
Module I.:.
Features Functional Description and write enable (WEx) inputs are both
The CYM1830 is a high performance 2M- LOW. Data on the input/output pins
High-density 2 Megabit SRAM Module
bit Static RAM module organized as 64K (VOx) is written into the memory location
High speed CMOS SRAMs specified on the address pins (Ao through
words by 32 bits. This module is con-
- Access time - 25 ns structed from eight 64K x 4 SRAMs in Aus).
Independent byte and word controls LeC packages mounted on a ceramic sub- Reading the device is accomplished by
Low active power - 4.8 W (max) strate with pins. Four chip selects (CSo taking the chip selects (CSx) LOW, while
CSt ,C~ and CS3 ) are used to independ- write enables(WEx) remains HIGH. Un-
Hermetic SMD technology
ently enable the four bytes. Two write en- der these conditions the contents of the
TTL compatible inputs and outputs memory location specified on the address
ables (WEo and WEt ) are used to inde-
Low profile pendently write to either upper or lower pins will appear on the data input/output
- Max. height - .270 in. 16 bit word of RAM. Reading or writing pins (!lOx ).
Small PCB footprint - 1.8 sq in. can be executed on individual bytes or any The Data input/output pins stay in the
combination of multiple bytes through high impedance state when write enables
2 V data retention (L version)
proper use of selects and write enables. (WEx) are WW, or the appropriate chip
Writing to each byte is accomplished selects are HIGH.
when the appropriate chip select (CSx)

Ao-A15 --~1':-6-r---------------'
DE ---r4--------------------~
WEo ---.+-r----------~
4 110 0 -1/0 3
CSa
1/0 8 -1/0 11
CS1
WE 1
1I~6-1/~9
CS:!
C~--------~------------------~
1830-1 1830-2
Selection Guide
1830HD-30 1830HD-35 1830HD-45 1830HD-55
Commercial 880 880 880 880
Commercial 320 320 320 320
2-343
~PRFSS
.nICONDUcrOR
PRELIMINARY CYMl830
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines not tested.)
Storage Temperature ..................... -6SoC to + lS0C Static Discharge Voltage ......................... >2001V
(per MIL-STD-883 Method 301S)
Power Applied ......................... -SSoC to + 12SC Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Operating Range
Ambient
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.SV to + 7.0V Range
Temperature Vee
DC Input Voltage ......................... -0.5V to +70V
Commercial OC to +70C SV 10%
Output Current into Outputs (Low) ................ , . 20 rnA
Military (4) -SSoc to + 12SoC SV 10%
CYM1830HD
Min. Max.
VOL Output LOW Voltage Vee =

. I IOL = 8.0 rnA
Mm. I
Military
0.4 V
IOL = 12.0 rnA Commercial
\1.H Input HIGH Voltage 2.2 Vee V
ViL Input LOW Voltage O.S 0.8 V
IIX Input Load Current GND~\l ~Vee -20 +20 J.LA
loz Output Leakage Current GND ~ Vo ~ \tc. Output Disabled -10 10 J.LA
los Current[l) Vee = Max., VOUT = GND -3S0 rnA
vee Operating Supply Vee = Max., lOUT = 0 rnA

Ice 880 rnA
Current by 16 mode CSx ~VIL
Automatic CS (2) Max. Vee, CSx ~ VIH
Automatic CS (2) Max. Vee, CSx ~ Vee - 0.3V,
IsB2 Power Down Current VIN ~ Vee - 0.3V or VIN ~ 0.3V 160 rnA
Capacitance(3)
CIN Input Capacitance TA = 2SoC,f = 1 MHz 90
pF
COUT Output Capacitance Vee=S.OV 30
Notes:
1. Not more than 1 output should be shorted at one time. Duration of the 3. Tested initially and after any design or process changes that may affect
2. A pull-up resistor to Vee on the es input is r~quired to keep the device 4. TA is the "instant on" case temperature.
given.
2-344
~PRESS
WnEMlcoNDucroR
PRELIMINARY CYMl830
Switching Characteristics Over Operating Range [SI

1830HD-30 1830HD-35 1830HD-45 1830HD-55
READ CYCLE
fI
trzcs CS LOW to Low Z(7) 3 3 3 3 ns
tHZCS CS' HIGH to High Z[6, 7) 15 20 20 20 ns
WRITE CYCLE (8)
trzWE wn HIGH to Low Z(7) 3 3 3 3 ns
tHZWE WE LOW to High Z[6, 7) 0 20 0 20 0 20 0 20 ns
Notes:
5. Test conditions assume signa) transition times of 5 ns or )ess, timing 8. The internal write time of the memory is defined by the overlap of(;S'
reference )evels of 1.5V, inputlevels of 0 to 3.0V and output loading of LOW and WE LOW. Both signals must be LOW to initiate a write and
the specified IodIoHand 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
6. t HZCS and tHZWE are specified with Q = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
t LZCS for any given device.
lO.Device is continuously selected, CS = VII.,
l1.Address valid prior to or coincident with CS transition LOW.

R1 3290 R1 3290
5V ~(481
0 MIL) 5V T . 1 ( 4
08MIL)
1
3.0V-----
90%
OUTPUT OUTPUT
R2 R2
J 30 pF
=
2020
(2550 MIL) J 5 pF
=
2020
(255 0 MIL)
GND---~
::; 5 ns
INCLUDING INCLUDING
JIG AND JIG AND

1670 1250
OUTPUT ~ 1.73V OUTPUT 0--'vvv---0 1.90V
1830-6
2-345
~PFESS
WnlcoNDucroR
PRELIMINARY CYMl830

CYM1830
Min. Max.
\DR Vee for Retention of Data 2.0 V
IceDR Data Retention CUrrent Vee = 2.0V, 32 mA
CS ~ Vee- 0.2V
tCDR Chip Deselect to Data Retention Time 0 ns
\iN ~ \te - 0.2V
tR Operation Recovery Time or \iN S 0.2V tRe[121 ns
IU Input Leakage CUrrent 8 JJ.A
Notes:
J: DATA RETENTION MODE :-1
,- _4_.5_Vf-----:-:-:-2V----.. . ./~:_j
t c: ].....:
' '-Z-'Z' ' ' ' ' ' ' Z' ' ' Z' ' ' ' ' ' ' Z' ' '7fv'' V---
'H I ~H1\S SSS S
1830--7
F
ADDRESS
DATA OUT
~to~~~
t~
PREVIOUS DATA VAUD ~:::::::::::::::::::D:A:T:A:V:A:LI:D:::::::::::::::=

*--
1830-8
2-346
~~DUC1CO PRELIMINARY CYM1830

II
t RC
~~ -.'-
tACS
.... 1(- T
_ t OOE
t HZOE -
t LZOE
t HZCS
HIGH IMPEDANCE , HIGH IMPEDANCE

DATA OUT
!4"- t LZCS -
\. \. \. \. I"
'////11 DATAVAUD
r-- t pu 14-- tpD ----1

VCC ~ ICC
SUPPLY 50% I ' - - - 19B
CURRENT
1830-9

twc
~f
ADDRESS
- l
tscs
~(-
\. \. \ \.'\. '\.-T ---; ~//// I/LLL/////

tAw t HA -
tSA tPWE
I
~\. \.~ ~ 7'-
I
tSD tHO
DATA IN ~~ DATA-IN VALID -'If

I--- t HZWE - - t
LZWE
-
HIGH IMPEDANCE
18330-10
ADDRESS -- ~~
tSA
twc
~~
tscs
...l~ ---;~
I-
tHA
tAW
tPWE
WE \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.~~ "")~/ / / // / / / / / / / / /
tSD I tHO
*
DATA IN
*
DATA-IN VALID
I I
- t HZWE
DATA OUT _______DA_T_A_UN_D_EF_IN_E_D_ _ _ _ _ _ _ _ _ _ _ _ :1...... HIGH IMPEDANCE
1830-11
2-347
~PRRSS
_~ICONDUcrOR
PRELIMINARY CYMl830
Truth Table
CS x WEx Input/Outputs Mode
L H Data Out Read
L L Data In Write
Package Operating
Speed Ordering Code
Type Range
30 M1830HD-3OC HD06 Commercial
M183011ID-30C HD06
35 M1830HD-3SC HD06 Commercial
M1830LHD-3SC HD06
M1830HD-3SMB HD06 Military
M183011ID-3SMB HD06
45 M1830HD-4SC HD06 Commercial
M183011ID-4SC HD06
M1830HD-4SMB HD06 Military
M183011ID-4SMB HD06
S5 M1830HD-SSC HD06 Commercial
M183011ID-SSC HD06
M1830HD-SSMB HD06 Military
M183011ID-SSMB HD06
2-348
PRELIMINARY CYM1831
CYPRESS
Module
fI
Features Functional Description location specified on the address pins
(Ao through A,s).
High-density 2M bit SRAM Module
The CYM1831 is a high performance 2M- Reading the device is accomplished by
High speed CMOS SRAMs bit Static RAM module organized as 64K taking the chip selects (CSN) LOW, while
- Access time - 25 ns words by 32 bits. This module is con- write enable (WE) remains HIGH. Under
Low active power - 4 W (max) structed from eight 64K x 4 SRAMs SOJ these conditions the contents of the mem-
packages mounted on an epoxy laminate ory location specified on the address pins
SMD Technology board with pins. Four chip selects (CS" will appear on the data input/output pins
TTL compatible inputs and outputs CS2 , CS3 and CS4) are used to independ- (1/00
Low profile ently enable the four bytes. Reading or The data input/output pins stay in the
writing can be executed on individual ~ impedance state when write enable
- Max. height - .50 in. bytes or any combination of multiple (WE) is LOW, or the appropriate chip
Small PCB footprint - 1.2 sq in. bytes through proper use of selects. selects are HIGH.
JEDEC compatible pinout Writing to each byte is accomplished Two pins (pDO and PD 1) are used to
2V data retention (L version) when the appropriate chip selects (CSN) identify module memory density in
and write enable (WE) inputs are both applications where alternate versions
LOW. Data on the input/output pins of the JEDEC standard modules can be
(1/00 is written into the memory interchanged.

PDO-Open GND
PD1-GND PD~
AO-A15~~16~----~----------------------' 1/0 0 PD1
1/0 8
1/1
~--------~---------------------------, 1/0 2 I/0g
1/0 10
~----~4-~----------------~ 1/0 3 1/0 11
Vee Ao
A7 Al
1/00 -1/0 3 As A2
Ag 1/0 12
1/0 4 1/0 13
1/0 5 1/0 14
~1-----+~4---~---------------+~4---~ 1/0 6
1/0 7 1/0 15
GND
II0 a -1/ 11 ~ A15
~2
CS'1
~3 CS'4
~2-----+~+---~--------------+-~--~ NC
NC
GND UE'
1/0 16 1/0 24
1/0 17 1/25
1/0 18 1/26
1/0 19 1/0 27
~3-----+~+---L---------------+-~--~ Ala A3
All A4
A12 A5
A13 Vee
1/0 20 A6
1/0 21 1/0 28
~4------------~----------------------~ 1/0 22 1/ 29
1/23 1/0 30
GND 1/31
ZIP
Top View
1831-1 1831-2
Selection Guide
1831PZ-25 1831PZ-35 1831PZ-45
2-349
~p~
WnEMICONDUcrOR
PRELIMINARY CYMl831
Maximum Ratings
Storage Temperature ..................... -6S o C to + 150C Static Discharge Voltage ......................... >2OO1V
(per MIL-STD-883 Method 3015.2)
Power Applied ............................ OOC to + 70C Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Supply Voltage to Ground Potential ......... -O.SV to +7.0V
Operating Range
Ambient
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to + 7.0V Range
Temperature Vee
. f ICS 0 ver 0)peratmg R ange

rIcaI Charac tens
EIec t
CYM1831PZ
Min. Max.
\]H Input HIGH Voltage 2.2 Vee V
\]L Input LOW Voltage -3.0 0.8 V
IIX Input Load Current GND s: \l s: Vee -20 +20 J,IA
Ioz Output Leakage Current GND s: Va s: Vee, Output Disabled -20 +20 J,IA
los Current (1) Vee = Max., VOUT = GND -350 rnA

Ice 720 rnA
Supply Current CSN s: \]L
Automatic CS (2] Max. Vee; CSN ~ VIH 160 rnA
!sB1 Power Down Current Min. Duty Cycle = 100%
Automatic CS (2) Max. Vee; CSN ~ "\Ce - 0.3V,

!sB2 Power Down Current VIN ~ "ce - 0.3V or 160 rnA
VIN s: 0.3V
Capacitance(3)
pF
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe 2. A pull-up resistor to \CC on the't;S input is required to keep the device
short circuit should not exceed 30 seconds. deselected during \tc power-up, otherwise ISB will exceed values
given.

5V~ R2 5V~ R2
3.0V----
90%
OUTPUT OUTPUT
J 30pF _ 2550 J 5pF _ 2550 GND---"I
S:5 ns
- - -
INCLUDING
-
INCLUDING
SCOPE SCOPE
OUTPUT ~
1670
1.73V 1831-6
2-350
~~~ PRELIMINARY ~1~1
Switching Characteristics Over Operating Range [4)
1831PZ-25 1831PZ-35 1831PZ-45

READ CYCLE
tRC Read Cycle Time
Min.
25
Max. Min.
35
Max. Min.
45
Max.
ns
II
tnoE OE LOW to Data Valid 15 25 30 ns
tLZOE trn LOW to LOW Z 0 0 0 ns
tLZCS CS LOW to Low Z [6) 3 3 3 ns
tHzCS CS HIGH to High Z[5,6) 10 15 20 ns
tpu CS LOW to Power Up 0 0 0 ns
WRITE CYCLE (7)

tpWE WE: Pulse Width 20 25 30 ns
tLZWE WE HIGH to Low Z(6) 3 5 5 ns
tHzwE WE" LOW to High Z [5, 6) 0 10 0 12 0 15 ns
Notes:
of the specified lodloH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. tHZCS and tHzWE are specified with CL = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
tLZCS for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = \1L and OE = Vu:
100% tested. 10. Address valid prior to or coincident with ~ transition low.
11. (;S"l' ~, ~3 and ~ are represented by ~ in the switching Char-
2-351
~PFESS
.nMICONDUcrOR
PRELIMINARY CYM1831
Daa
t R
e en f lCS
t fIon Charact eriS (L Version Only)
CYM1831
Min. Max.
IceDR Data Retention Current Vee = 2.0V, 32 rnA

CS ~ Vee - 0.2V
tCDR[13] Chip Deselect to Data Retention Time 0 ns
\iN ~ '\te - O.2V
tR[13] . Operation Recovery Time or\iN~ O.2V tRe(12) ns
IU[13] Input Leakage Current 20 J.LA
Notes:
12. tRC = Read Cycle Time. 13. Guaranteed, not tested.
DATA RETENTION MODE ~
tc:t'-.: :f
4.5V ___4.5V --I
1....._ _ _ _"o_R_~_2_V_____
tR I
,.,.Z--Z.,.Z.....,..Z--Z..,.Ifv-lr-V,H--'-----VO-R___--..J' "'H1\S SSS S
1831-6
=f=_----------t----------*--------
RC
ADDRESS
~~-;~
~===================D=A=T=A=V=A=LI=D================
DATA OUT
PREVIOUS DATA VAUD
1831-7
2-352
~PRE5S
WnMICONDUCTOR
PRELIMINARY CYM1831

~~
tACS
t RC
-,~ II
...JI(" J~
t DOE ~ t HZOE -
t LZOE t HZCS
DATA OUT
HIGH IMPEDANCE I
,,'\
/ L L /
'\ '\ '\
I DATA VALID ," HIGH IMPEDANCE
I+-- t LZCS - "

VCC _____
14- t pu
~OO%
- tpD
=1
50%~
ICC
SUPPLY ISB
CURRENT
1831-8
twc
~{.. ~{..
ADDRESS
- I
tscs
\. \. \ \.\.\.~ ......,
'-/ / / / //////////
tAW
t HA -
tSA t PWE
I
~\.\.-'~ "7<-
I
tSD tHD
DATA IN 4~ DATA-IN VALID 4~
I-- t HZWE - tLZWE
HIGH IMPEDANCE
DATAOUT DATA UNDEFINED
1831-9
ADDRESS -- ~t
tSA
twc
tscs
~(-
.1
~
I
,~
tHA
tAW
t PWE
'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.\.~["" "J~LLLLL/LL/L// //
tSD 1 tHD
I
DATA IN
*"I DATA-IN VALID
*"I
- tHZW
E~ .~ __H~IG~H~IM~P~E~DA~N~C~E___________________
--------------------------------------------~
1831-10
2-353
~
"~PRESS PRELIMINARY ~1~1
~, SEMICONDUCTOR
Truth Table
CSN WE OE Input/Outputs Mode
L H L Data Out Read
L L X Data In Write
Package Operating
Speed Ordering Code
Type Range
25 CYM 183 1PZ-25C PZ01 Commercial
CYM 183 1LPZ-25C PZ01
35 CYM1831PZ-35C PZ01
CYM1831LPZ-35C PZ01
45 CYM1831PZ-45C PZ01
CYM 183 1LPZ-45C PZ01
2-354
CYM1832
CYPRESS
Module til
Features Functional Description (IlOX> is written into the memory
location specified on the address pins
High-density 2M bit SRAM Module The CYM1832 is a high performance (Ao through A 111).
High speed CMOS SRAMs 2M-bit Static RAM module organized as
64K words by 32 bits. This module is con- Reading the device is accomplished by
- Access time - 35 ns taking the chi~lects (CSN) LOW, while
structed from eight 64K x 4 SRAMs SO]
Low active power - 5.4 W (max) packages mounted on an epoxy laminate write enable (WE) remains HIGH. Under
board with pi~ Four chip selects (CS" these conditions the contents of the mem-
SMD Technology
CS2 , CS3 and CS4) are used to independ- ory location specified on the address pins
TTL compatible inputs and outputs will appear on the data input/output pins
ently enable the four bytes. Reading or
Low profile writing can be executed on individual (I/Ox)
- Max. height - .50 in. bytes or any combination of multiple The data input/output pins stay in the
Small PCB footprint - 1.0 sq in. bytes through proper use of selects. h impedance state when write enable
Writing to each byte is accomplished (WE) is WW, or the appropriate chip
when the appropriate chip selects (CSN) selects are HIGH.
and write enable (WE) inputs are both
LOW. Data on the input/output pins
Logic Block Diagram
Ao-A15~~16----~----------------------~
~----,--+----------------~
liDo -1/0 3
~1-----r--~~~-------------+--+-~
110 8 -1/0 11
~2-----r~--~--------------+--+--~
110 20 -1/0 23
~3-----r--r-~~-------------+--+-~
~4----------~~------------------~
ZIP
Top View
1832-1 1832-2
Selection Guide
1832PZ-35 1832PZ-45 1832PZ-55
2-355
~PFESS
.nMICONDUCTOR
CYMl832

Storage Temperature ................. ~ ... -45C to + 125C
Ambient Temperature with Commercial OC to +70C SV 10%
Power Applied ........................... 10C to +8S o C
in High Z State. . . . . . . . . . . . .. . . .. .. . .. . ... -O.SV to + 7.0V
DC Input Voltage ........................ -O.SV to + 7.0V

CYM1832PZ
Min. Max.
\lL Input LOW Voltage[l] -0.5 0.8 V
IIX Input Load Current GND =::;; Vi: =::;; Vee -20 +20 jJ.A
Ioz Output Leakage Current GND :cs;; Vo =::;; Vee, Output Disabled -100 +100 jJ.A
Ice Supply Current 980 rnA
CSN =::;; \lL
Automatic CS [2] Max. vee; CSN ~ VIH
Automatic CS [2] Max. Vee; CSN ~ 'te - 0.2V,
VIN :cs;; 0.2V
Capacitance[3]
pF
Notes:
1. V1L(MIN) = -3.0V for pulse widths less than 20ns. 3. Tested on a sample basis.
2. A pull-up resistor to Vee on the~ input is required to keep the device
given.

5V~ R2 5V~ R2
3.0V-----
OUTPUT OUTPUT
J 30pF _ 2550 J 5pF _.2550 GND ----'I

- - - -
INCLUDING INCLUDING
SCOPE SCOPE
1670 1832-5
OUTPUT 0----'vvv---<) 1.73V
2-356
~PFESS
'nMICONOUCfOR
CYM1832
SwItc
. h'InJ! Ch aractensbcs Over Operating Range [4]
1832PZ-35 1832PZ-45 1832PZ-55
READ CYCLE
tORA Data Hold from Address Change 5 5 5 ns
tLZCS CS LOW to Low Z [6] 5 5 5 ns
tHZCS CS'"HIGH to High Z[5,6] 0 25 0 30 0 30 ns
tpu CS LOW to Power Up 0 0 0 ns
WRITE CYCLE [7]

tRA Address Hold from Write End 5 5 5 ns
tLZWE WE HIGH to Low Z[6] 3 5 5 ns
tHZWE WE LOW to High Z [5, 6] 0 15 0 20 0 30 ns
Notes:
reference levels of I.SV, input levels of 0 to 3.0V and output loading WWandWEWW. Both signals must be WWto initiate a write and
of the specified IodIoH and 30 pF load capacitance. either signal can terminate a write by going HIGH. The data input
5. tHzcs and tHzWE are specified with C L = 5 pF as in Figure lb. setup and hold timing should be referenced to the rising edge of the
tLZCS for any given device. These parameters are guaranteed and not 9. Device is continuously selected, CS = VIu
11. CS"1' CS2 , CS3 and ~ are represented by CS in the switching Char-
*________
Read Cycle No.1 [8,9]
ADDRESS~~_- _ - _ t R e_ _
--f.'- tOHA--1
tAA~.1
)ATA OUT
PREVIOUS DATA VAUD =====================D=A=TA==VA=L=ID===================
1832-6
2-357
~PRLSS
.nMICONDUcrOR
CYMl832

t RC
CS ~~ .. "';;11.
tACS
t HZCS
DATA OUT
HIGH IMPEDANCE ~////I;, DATAVAUD
HIGH IMPEDANCE
14-- t LZCS ----r~""

14--
14- t pu tpD
-1
-----j-
ICC
Vcc
SUPPLY =~ISB
CURRENT
1832-7
Write Cycle No. 1 (WE Controlled) (7)
ADDRESS -- -l l-
L
twc
tscs
~f-
~\.\ '\.'\.'\.T -, ~/ / / /. //////////

tAW tHA - - -
tSA tPWE
I
WE -T'\ \..... ~ "1'-
I
tSD tHO
DATA IN ~(- DATA-IN VAUD

-J~
HZWE LZWE
- t - - t -
HIGH IMPEDANCE
1832-8
ADDRESS -- ~LL
tSA
twc
-I tscs
~~
tAW
~ -;""" tHA
tPWE
WE '\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\'\~~ ..,~/ / / / / / / / / / / / / /
I
tSD I tHO
DATA IN
*"I DATA-IN VAUD
*" I
HZWE~
I-- t
_~HIG~H~I~MP~E~DA~N~C.E _ _ _ _ _ _ _ _ __
--------------------------------------------
1832-9
2-358
~PFSS
_~ICONDUcrOR
CYMl832
Truth Table
CSN WE Input/Outputs Mode
L
L
H
L
Data Out
Data In
Read
Write
EI
Package Operating
Speed Ordering Code
Type Range
35 CYM1832PZ-35C PZ02 Commercial
45 CYM1832PZ-45C PZ02
55 CYM1832PZ-55C PZ02
2-359
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
-
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES
~ Section Contents
~~~~UaoR==================================================================
PROMs (Programmable Read Only Memory) Page Number
Introduction to PROMs .................................................................................. 3-1
CY7C225 512 x 8 Registered PROM .................................................. 3-4
CY7C235 1024 x 8 Registered PROM ................................................. 3-15
CY7C245 2048 x 8 Reprogrammable Registered PROM .................................. 3-26
CY7C245A 2048 x 8 Reprogrammable Registered PROM .................................. 3-38
CY7C261 8192 x 8 Reprogrammable Power Switched PROM ............................. 3-60
CY7C265 64K Registered PROM ................................................. 3-71
CY7C266 8192 x 8 Reprogrammable EPROM .......................................... 3-81
CY7C281 1024 x 8 PROM ......................................................... 3-118
CY7C282 1024 x 8 PROM ......................................................... 3-118
CY7C291 2048 x 8 Reprogrammable PROM .......................................... 3-129
CY7C292 2048 x 8 PROM ......................................................... 3-129
PROM Programming Information ....................................................................... 3-147
~~
. J4
,
CYPRESS
SEMICONDUCTOR
Introduction to CMOS PROMs
====================================================================
1: Product Line Overview 3: Design Approach
The Cypress CMOS family of PROMs span 4K to 256K A. Four Transistor Differential Memory Cell
bit densities, three functional configurations, and are all
byte-wide. The product line is available in both 0.3 and 0.6 The 4K, 8K, and 16K PROM (except "A" version) use an
inch wide dual-in-line plastic and CERDIP as well as LCC N-Well CMOS technology along with a new differential
and PLCC packages. The programming technology is four transistor EPROM cell that is optimized for speed.
EPROM and therefore windowed packages are available in The area of the four transistor cell is 0.43 square mils and
both dual-in-line and LCC configurations, providing eras- the die size is 19,321 square mils for the 2K by 8 PROM
able products. These byte-wide products are available in (Figure 1). The floating gate cell is optimized for high read ~
registered versions at the 512, lK, 2K, and 8K by 8 densi- current and fast programmability. This is accomplished by ~
ties, and in non-registered versions at the lK, 2K, 8K, 16K separating the read and program transistors (Figure 2). The
and 32K by 8 densities. The registered devices operate in program transistor has a separate implant to maximize the
either synchronous or asynchronous output enable modes generation and collection of hot electrons while the read
and may have an initialize feature to preload the pipeline transistor implant dose is chosen to provide a large read
register. The 8K by 8 registered devices feature a diagnos- current. Both the nand p channel peripheral transistors
tic shadow register which allows the pipeline register to be have self-aligned, shallow, lightly doped drain (LDD) junc-
loaded or examined via a serial path. tions. The LDD structure reduces overlap capacitance for
speed improvement and minimizes hot electron injection
Cypress PROMs perform at the level of their bipolar equiv- for improved reliability. Although common for NMOS
alents or beyond with reduced power levels of CMOS tech- static and dynamic RAMs, an on-chip substrate bias gener-
nology. They are capable of 2001 volts of ESD and operate ator is used for the first time in an EPROM technology.
with 10% power supply tolerances. The results are improved speed, greater than 200 mA
latch-up immunity and high parasitic field inversion volt-
2: Technology Introduction ages during programming.
Cypress PROMs are executed in an "N" well CMOS
EPROM process. Densities of 128K and under with the
exception of the "A" series devices use the 1.2 micron
PROM I technology. The 16K "A" series devices and the
future 256K PROMs use the 0.8 micron PROM II tech-
nology with a single ended memory cell. The process pro-
vides basic gate delays of 235 picoseconds for a fanout of
one at a power consumption of 45 femto joules. The pro-
cess provides the basis for the development of LSI products
that outperform the fastest bipolar products currently
available.
Although CMOS static RAMs have challenged bipolar
RAMs for speed, CMOS EPROMs have always been a
factor of three to ten times slower than bipolar fuse
PROMs. There have been two major limitations on CMOS
EPROM speed; 1) the single transistor EPROM cell is in-
herently slower than the bipolar fuse element, and 2)
CMOS EPROM technologies have been optimized for cell
programmability and density, almost always at the expense
of speed. In the Cypress CMOS EPROM technology, both
of the aformentioned limitations have been overcome to
create CMOS PROMs with performance superior to
PROMs implemented in bipolar technology.
0034-1
In all Cypress PROMs, speed and programmability are op- Figure 1
timized independently by separating the read and write
transistor functions. Also, for the first time a substrate bias
generator is employed in an EPROM technology to im-
prove performance and raise latchup immunity to greater
than 200 mAo The result is a CMOS EPROM technology WORD LINE
that challenges bipolar fuse technology for both density
and speed. In addition, at higher densities, performance
and density surpasses the best that bipolar can provide.
Limitations of devices implemented in the bipolar fuse 0034-2
technology such as PROGRAMMING YIELD, POWER Figure 2. Non-volatile cell optimized

DISSIPATION and HIGHER DENSITY PERFORM- for speed and programmability
ANCE are eliminated or greatly reduced using Cypress Access times of less than 35 ns at 16K densities and 30 ns
CMOS EPROM technology. at 4K and 8K densities over the full operating range are
achieved by using differential design techniques and by to-
3-1
~ Introduction to CMOS PROMs (Continued)
~~~DUcrOR =====================================================================
r----------------, I
I
OPERATIONAL AMPLIFIER I
I
r--------.I
CASCODE AMP
.--
I
I
I
I
-- ..
I
I
I
!S1
YR~
I
I
._------------------
I
SA
0034-3
Figure 3. Differential sensing
tally separating the read and program paths. This allows levels to input pins. Both logic "ONE" and logic "ZERO"
the read path to be optimized for speed. The X and Y are programmed into the differential cell. A BIT is pro-
decoding paths are predecoded to optimize the power-delay grammed by applying 12 to 14 volts on the control gate
product. A differentail sensing scheme and the four transis- and 9 volts on the drain of the floating gate write transis-
tor cell are used to sense bit-line swings as low as 100 mV tor. This causes hot electrons from the channel to be inject-
at high speed. The sense amplifier (Figure 3) consists of ed onto the floating gate thereby raising the threshold volt-
three stages of equal gain. A gain of 4 per stage was found age. Because the read transistor shares a common floating
to be optimum. The Cascode stage amplifies the bit line gate with the program transistor, the threshold of the read
swings and feeds them into a differential amplifier. The transistor is raised from about 1 volt to greater than 5 volts
output of the differential amplifier is further amplified and resulting in a transistor that is turned "OFF" when select-
voltages shifted by a level shifter and latch. This signal is ed in a read mode of operation. Since both sides of the
then fed into an output buffer having a TTL fan-out of ten. differential cell are at equal potential before programming,
a threshold shift of 100mV is enough to be determined as
B. Two Transistor Memory Cell the correct logic state. Because an unprogrammed cell has
The Cypress 64K and greater density PROMs use a two neither a ONE nor a ZERO in it before programming, a
transistor memory cell. This cell uses a single ended sens- special BLANK CHECK mode of operation is implement-
ing scheme with the exception of the 256K device which ed. In this mode the output of each half of the cell is com-
uses a differential sensing circuit. This combination allows pared against a fixed reference which allows distinction of
for a more compact design and reduced manufacturing a programmed or unprogrammed cell. A MARGIN mode
costs. This is an excellent compromise between perform- is also provided to monitor the thresholds of the individual
ance and high density, allowing the development of devices BITs allowing the monitoring of the quality of program-
with performance of 35 ns and 45 ns access times at densi- ming during the manufacturing operation.
ties from 64K to 256K bits and 25 ns for the "A" series
16K using the PROM II technology. This two transistor B. Single Ended Memory Cells
cell still uses the high speed read transistor and the opti- The programming mechanism of the EPROM transistor in
mized EPROM transistor for performance and reliable a single ended memory cell is the same as its counterpart in
programming. The sense amplifier uses a reference voltage a double ended memory cell. The difference is that only
on one input and the read transistor on the other, instead ones "1"s are programmed in a single ended cell. A "I"
of two read transistors. This single ended sensing is a more applied to the I/O pin during programming causes an
conventional technique and has the effect of causing an erased EPROM transistor to be programmed while a "0"
erased device to contain all "O"s. allows the EPROM transistor to remain unprogrammed.
4: Programming 5: Erasability
A. Differential Memory Cells For the first time at PROM speeds, Cypress PROMs using
CMOS EPROM technology offer reprogrammability when
Cypress PROMs are programmed a BYTE at a time by packaged in windowed CERDIP. This is available at densi-
applying 12 to 14 volts on one pin and the desired logic ties of 16K and larger, both registered and non-registered.
3-2
~FESS Introduction to CMOS PROMs (Continued)
~~IOO~UcrOR==================================================================
Wavelengths of light less than 4000 Angstroms begin to Some devices are sensitive to photo-electric effects during
erase Cypress PROMs. For this reason, an opaque label programming. Cypress recommends covering the windows
should be placed over the window if the PROM is exposed of reprogrammable devices during programming.
to sunlight or fluorescent lighting for extended periods of
time. 6: Reliability
The recommended dose of ultraviolet light for erasure is a The CMOS EPROM approach to PROMs has some signif-
wavelength of 2537 Angstroms for a minimum dose (UV icant benefits to the user in the area of programming and
intensity X exposure time) of 25 Wsec/cm2. For an ultra-
violet lamp with a 12 mW/cm 2 power rating the exposure
time would be approximately 30-35 minutes. The industry
functional yield. Since a cell may be programmed and
erased multiple times, CMOS PROMs from Cypress can be
tested 100% for programmability during the manufactur-
II
EPROM erasure standard is 15 Wsec/cm2. Cypress ing process. Because each CMOS PROM contains a
EPROMs require 1% longer erase times. PHANTOM array, both the functionality and performance
The PROM needs to be within 1 inch of the lamp during of the devices may be tested after they are packaged thus
erasure. Permanent damage may result if the PROM is assuring the user that not only will every cell program, but
exposed to high intensity light for an extended period of that the product performs to the specification.
time. 7258 Wsec/cm2 is the recommended maximum dos-
age.
3-3
CY7C225
CYPRESS
SEMICONDUCTOR 512 X 8 Registered PROM
Features
CMOS for optimum Slim, 300 mil, 24 pin plastic or floating gate technology and byte-wide
speed/power hermetic DIP, or 28 pin LCC intelligent programming algorithms.
High speed 5V 10% Vcc, commercial and The CY7C225 replaces bipolar devices
- 25 ns max set-up military and offers the advantages of lower
- 12 ns clock to output TIL compatible I/O power, superior performance and high
programming yield. The EPROM cell
Low power Direct replacement for requires only 13.5V for the supervolt-
- 495 mW (commercial) bipolar PROMs
- 660 mW (military) age and low current requirements allow
Capable of withstanding for gang programming. The EPROM
Synchronous and asynchronous greater than 1500V static cells allow for each memory location to
output enables discharge be tested 100%, as each location is
On-chip edge-triggered written into, erased, and repeatedly ex-
registers Product Characteristics ercized prior to encapsulation. Each
PROM is also tested for AC perform-
Buffered Common PRESET and The CY7C225 is a high performance ance to guarantee that after customer
CLEAR inputs 512 word by 8 bit electrically Program- programming the product will meet
mable Read Only Memory packaged in AC specification limits.
EPROM technology, 100% a slim 300 mil plastic or hermetic DIP
programmable The CY7C225 has asynchronous PRE-
and 28 pin Leadless Chip Carrier. The
memory cells utilize proven EPROM SET and CLEAR functions.

A7 Vee
07 A6 As
As ~
ROW 32 x 128 06
DECODER PROGRAMMABLE A4
1 OF 32 ARRAY
A3 ~
Os
A2 Es
04 A, CP
Ao 07
03 00 06
A3 0, Os
A2 COLUMN 02
02 04
DECODER
A, 1 OF 16 GND 03
Ao 0,
0020-2
~ 00
.'f<"'~~ Jl.fl~
ern 4 3
CP A4 5 E
A3 CLR
A2 Es
ES Al 8 CP
Ao 9 NC
NC 10
7
0020-1
0 6
... NO 0 ...., ..,. It)
OOzzooo
(!) 0020-11
Selection Guide
7C225-25 7C225-30 7C225-35 7C225-40
Maximum Set-up Time (ns) 25 30 35 40
Maximum Clock to Ouput (ns) 12 15 20 25
Maximum Operating I Commercial 90 90 90
Current (rnA)
I Military 120 120 120
3-4
~ CY7C225
~~~~UcrOR=====================================================================
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage .......... , .......... > 1500V

(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Operating Range
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to +70C 5V 10%
DC Program Voltage (Pins 7, 18,20) ............. 14.0V Military [6] - 55C to + 125C 5V 10%

Vee = Min.,loH = -4.0mA
VOH Output HIGH Voltage 2.4 V
VIN = VlHorVIL
Vee = Min.,IOL = -16 rnA
VOL Output LOW Voltage 0.4 V
VIN = VIH or VIL
VIH Input HIGH Level 2.0 V
Voltage for All Inputs[2]
VIL Input LOW Level 0.8 V
Voltage for All inputs[2]
IIX Input Leakage Current GND:::;: VIN :::;: Vee -10 +10 JLA
Input Clamp Diode
VeD Note 1
Voltage
loz Output Leakage Current GND :::;: Vo :::;: Vee Output Disabled[4] -40 +40 JLA
los Output Short Circuit Current Vee = Max., VOUT = 0.OV[3] -20 -90 rnA
lee Power Supply Current

GND :::;: VIN :::;: Vee I Commercial 90
rnA
Vee = Max.
I Military 120
Capacitance [5]
Notes:
1. The eMOS process does not provide a clamp diode. However, the 4. For devices using the synchronous enable, the device must be clocked
eY7e225 is insensitive to - 3V dc input levels and - 5V undershoot after applying these voltages to perform this measurement.
pulses of less than 10 ns (measured at 50% point). 5. Tested initially and after any design or process changes that may
2. These are absolute voltages with respect to device ground pin and affect these parameters.
include all overshoots due to system and/or tester noise. Do not at- 6. TA is the "instant on" case temperature.
tempt to test these values without suitable equipment (see Notes on 7. See the last page of this specification for Group A subgroup testing
Testing). information.
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3-5
~ CY7C225
~~~~UcrOR=====================================================================
Switching Characteristics Over Operating Range[7, S]
7C22525 7C22530 7C22535 7C22540
tSA Address Setup to Clock HIGH 25 30 35 40 ns
tHA Address Hold from Clock HIGH 0 0 0 0 ns
teo Clock HIGH to Valid Output 12 15 20 25 ns
tpwe Clock Pulse Width 10 15 20 20 ns
tSEs Es Setup to Clock HIGH 10 10 10 10 ns
tHEs Es Hold from Clock HIGH 0 5 5 5 ns
tDP, tDe Delay from PRESET or CLEAR to Valid Output 20 20 20 20 ns
tRP, tRe PRESET or CLEAR Recovery to Clock HIGH 15 20 20 20 ns
tpwp, tpwe PRESET or CLEAR Pulse Width 15 20 20 20 ns
Valid Output from
teos Clock HIGH[l] 20 20 25 30 ns
tHze Inactive Output from Clock HIGH[I, 3] 20 20 25 30 ns

tDOE Valid Output from E LOW[2] 20 20 25 30 ns
Inactive Output from
tHZE EHIGH[2,3] 20 20 25 30 ns
Notes:
1. Applies only when the synchronous (ES) function is used. 5. See Figure 1a for all switching characteristics except tHZ.
2. Applies only when the asynchronous (E) function is used. 6. See Figure 1b for tHZ.
3. Transition is measured at steady state HIGH level - 500 m V or 7. All device test loads should be located within 2" of device outputs.
steady state LOW level + 500 m V on the output from the 1.5V level S. See the last page of this specification for Group A subgroup testing
on the input with loads shown in Figure lb. information.
4. Tests are performed with rise and fall times of 5 ns or less.
AC Test Loads and Waveforms [5, 6, 7]

Rl 250 n R1250n
5VO-------~~~~ 5V o--------tIV'lr--.
ALL INPUT PULSES
OUTPUT 0-----......------.. OUTPUT 0-----_------.. . 3.0 V - - - - - -.i.......---~i.....
50 pF ~:7 n 5pF R2
I INCLUDING
JIG AND
":" SCOPE ":"
I INCLUDING
_JIGAND _
- SCOPE -
16712 GND
.;;5 n5 .. 5n5
0020-5
0020-3
Equivalent to:
THEVENIN EQUIVALENT
loon
OUTPUT ~2.0V
0020-4
The CY7C225 is a CMOS electrically Programmable Read applying the memory location to the address inputs (Ao-
Only Memory organized as 512 words x 8bits and is a pin As) and a logic LOW to the enable (Es) input. The stored
forpin replacement for bipolar TTL fusible link PROMs. data is accessed and loaded into the master flip-flops of the
The CY7C225 incorporates a Dtype, masterslave register data register during the address set-up time. At the next
on chip, reducing the cost and size of pipelined micropro- LOW-to-HIGH transition of the clock (CP), data is trans-
grammed systems and applications where accessed PROM ferred to the slave flip-flops, which drive the output buff-
data is stored temporarily in a register. Additional flexibili- ers, and the accessed data will appear at the outputs (00-
ty is provided with synchronous (Es) and asynchronous 07) provided the asynchronous enable (E) is also LOW.
(E) output enables, and CLEAR and PRESET inputs. The outputs may be disabled at any time by switching the
Upon power-up, the synchronous enable (Es) flip-flop will asynchronous enable (E) to a logic HIGH, and may be
be in the set condition causing the outputs (00-07) to be returned to the active state by switching the enable to a
in the OFF or high impedance state. Data is read by logic LOW.
3-6
~ CY7C225
~~~NDUcrOR ==================================================================~
Functional Description (Continued)
Regardless of the condition ofE, the outputs will go to the The CY7C225 has buffered asynchronous CLEAR and
OFF or high impedance state upon the next positive clock PRESET input (INIT). The initialize function is useful
edge after the synchronous enable (Es) input is switched to during power-up and time-out sequences.
a HIGH level. Ifthe synchronous enable pin is switched to Applying a LOW to the PRESET input causes an immedi-
a logic LOW, the subsequent positive clock edge will re- ate load of all ones into the master and slave flip-flops of
turn the output to the active state ifE is LOW. Following a
positive clock edge, the address and synchronous enable
the register, independent of all other inputs, including the
clock (CP). Applying a LOW to the CLEAR input, resets
3
inputs are free to change since no change in the output will the flip-flops to all zeros. The initialize data will appear at
occur until the next low to high transition of the clock. the device outputs after the outputs are enabled by bringing
This unique feature allows the CY7C225 decoders and the asynchronous enable (E) LOW.
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs. When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in
System timing is simplified in that the on-chip edge trig- the high impedance state. In order to enable the outputs a
gered register allows the PROM clock to be derived direct- clock must occur and the Es input pin must be LOW at
ly from the system clock without introducing race condi- least a setup time prior to the clock LOW to HIGH tran-
tions. The on-chip register timing requirements are similar sition. The E input may then be used to enable the outputs.
to those of discrete registers available in the market.
Switching Waveforms
AO-A10 __________________________________~---J~~l-----+----J~~~~~~~-------------------
CP
0020-6
Notes on Testing
Incoming test procedures on these devices should be carefully planned, 3. Do not attempt to perform threshold tests under AC conditions.
taking into account the high performance and output drive capabilities of Large amplitude, fast ground current transients normally occur as the
the parts. The following notes may be useful. device outputs discharge the load capacitances. These transients flow-
1. Ensure that adequate decoupling capacitance is employed across the ing through the parasitic inductance between the device ground pin
device Vee and ground terminals. Multiple capacitors are recom- and the test system ground can create significant reductions in observ-
mended, including a 0.1 ,..,F or larger capacitor and a 0.01 ,..,F or able input noise immunity.
smaller capacitor placed as close to the device terminals as possible. 4. Output levels are measured at 1.5V reference levels.
Inadequate decoupling may result in large variations of power supply 5. Transition is measured at steady state HIGH level - 500 m V or
voltage, creating erroneous function or transient performance failures. steady state LOW level + 500 m V on the output from the 1.5V level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure 1h.
3-7
~ CY7C225
~~~~ucr~==================================================================
NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT CLOCK TO OUTPUT TIME
VS. SUPPLY VOLTAGE AMBIENT TEMPERATURE
VS. VS. Vee
1 . 6 . - - - - - , - - - - r - - . . . , . . . . - -..... 1 . 2 . - - - - - - . . . . . - - - - - -..... 1.6
!il
i=
1.4 r----1I----+--_+_---..,~ !5 1.4
,
1.1 r - - - - - + - - - - - - - - 1
] ] I!:
::l
oW 1.21---~---+--_IoIL---f o o 1.2 ~
~
N
::i
~
::i :.: "'-
~ <
-----
...I
a:
1.01----1--~fC--_+_---1 :E ~ 1.0
~ i w
N
::i
< O.B
:E
TA" 26C a: TA = 25C
f-MAX.
O.BO'--_ _ _ _..L..-_ _ _ _ _ ~ ~ 0.6 I
4.6 6.0 6.6 6.0 -66 26 125 4.0 4.6 5.0 5.6 6.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('CI SUPPL Y VOLTAGE (VI
CLOCK TO OUTPUT TIME NORMALIZED SETUP TIME NORMALIZED SETUP TIME

w 1.6 VS. TEMPERATURE SUPPLY VOLTAGE
VS. TEMPERATURE
VS.
1.2 1.6
:IE
,
i=
I-
::l 1.41-----+-"------_f
w
:E
~~ 1.4
~ i= 1.0 Q,
~
::l
o A-
::l
I-
W
~ I- (I)
1.2
-
W
:.: (I) 0
w
0 O.B
9
CJ 1.0 t------::::OI.......~----_f
w
N
::i
N
::::i
< 1.0
oW < :E ~
:E a:
N a: 0
0.6 z
~ O.Br-----+------_f 0
z 0.8
:IE
a: TA i 26C
~ 0.6 '-----.......II..-----~ 0.4 0.6
-66 26 126 4.0 4.5 6.0 5.5 6.0 -66 25 125
AMBIENT TEMPERATURE (OCI SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OCI
OUTPUT SOURCE CURRENT TYPICAL ACCESS TIME CHANGE OUTPUT SINK CURRENT
VS. VOLTAGE VS. OUTPUT LOADING VS. OUTPUT VOLTAGE
60 30.0 176
:i
! 60 26.0
.,-- :i 160
!
.."",.,- ~
I-
w
a:
Z
40 "- ! 20.0
/ I-
zw
a:
126
V
" /
a:
::l
w
CJ
30 ~ :
<C
15.0
/ a:
::l
CJ
:.:
100
/
" /'f'
CJ
a: ~ z 76
iii
::l
0 20 ~ 10.0
!5 / Vee =6.0 V
TA "26C
'"
V
(I)
I-
TA" 25C A-
60
::l
Q,
I- 10 6.0
,J Vee =4.5 V I-
::l /
~
0 26
::l
0
o
o 1.0 2.0 3.0 4.0
0.0
o
L 200 400 600 BOO 1000
o
I
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (VI CAPACITANCE (pFI OUTPUT VOLTAGE (VI
0020-7
3-8
~
CY7C225
_Ts~NDUcrOR ======================================
Device Programming
Overview:
There is a programmable function contained in the 7C225 The 512 x 8 array uses a differential memory cell, with
CMOS 512 x 8 Registered PROM; the 512 x 8 array. All of differential sensing techniques. In the erased state the cell
the programming elements are "EPROM" cells, and are in contains neither a one nor a zero. The erased state of this
an erased state when the device is shipped. array may be verified by using the "BLANK CHECK
ONES" and "BLANK CHECK ZEROS" function, see
II
Table 3.
DC Programming Parameters TA = 25C

Table 1
Parameter Description Min. Max. Units
Vpp[l] Programming Voltage 13.0 14.0 V
Vccp Supply Voltage 4.75 5.25 V
VIHP Input High Voltage 3.0 V
VILP Input Low Voltage 0.4 V
VOH[2] Output High Voltage 2.4 V
VOL[2] Output Low Voltage 0.4 V
Ipp Programming Supply Current 50 rnA
AC Programming ParametersTA = 25C

Table 2
tpp Programming Pulse Width 100 10,000 JJ.s
tAS Address Setup Time 1.0 JJ.s
tDS Data Setup Time 1.0 JJ.s
tAH Address Hold Time 1.0 JJ.s
tDH Data Hold Time 1.0 JJ.s
tR, tF[3] Vpp Rise and Fall Time 50 ns
tVD Delay to Verify 1.0 JJ.s
tvp Verify Pulse Width 2.0 JJ.s
tDV Verify Data Valid 1.0 JJ.s
tDZ Verify HIGH to High Z 1.0 JJ.s
Notes:
1. Vccp must be applied prior to Vpp. 3. Measured 10% and 90% points.
2. During verify operation.
3-9
~ CY7C225
~~~~UaoR====================================~============================
Mode Selection
Table 3
Pin Function[l]
Mode Read or Output Disable CP Es CLR E PS Outputs
Other PGM VFY Vpp E PS (9-11,13-17)
Pin (18) (19) (20) (21) (22)
Read[2,3] X VIL VIH VIL VIH OataOut
Output Disable[5] X VIH VIH X VIH HighZ
Output Disable X X VIH VIH VIH HighZ
CLEAR X VIL VIL VIL VIH Zeros
PRESET X VIL VIH VIL VIL Ones
Program [4] VILP VIHP Vpp VIHP VIHP OataIn
Program Verify[4] VIHP VILP Vpp VIHP VIHP OataOut
Program Inhibit[4] VIHP VIHP Vpp VIHP VIHP HighZ
Intelligent Program[4] VILP VIHP Vpp VIHP VIHP OataIn
Blank Check Ones[4] Vpp VILP VILP VILP. VIHP Ones
Blank Check Zeros[4] Vpp VIHP VILP VILP VIHP Zeros
Notes:
1. X = Don't care but not to exceed Vpp. 4. During programming and verification, all unspecified pins to be at
2. During read operation, the output latches are loaded on a "0" to "1" VILP.
transition ofCP. 5. Pin 19 must be HIGH prior to the "0" to "1" transition on CP (18)
3. Pin 19 must be LOW prior to the "0" to "1" transition on CP (18) that loads the register.
that loads the register.
The CY7C225 programming algorithm allows significantly
faster programming than the "worst case" specification of
A7 Vce 10msec.
A6 As
A5 II!
Typical programming time for a byte is less than 2.5 msec.
The use of EPROM cells allows factory testing of pro-
A4 E
grammed cells, measurement of data retention and erasure
A3 VPP(~)
to ensure reliable data retention and functional perform-
A2 VFY(~s) ance. A flowchart of the algorithm is shown in Figure 4.
A,
Ao
PGM(CP)
07
The algorithm utilizes two differen
pptr
types: initial and
overprogram. The duration of the G pulse (tpp) is 0.1
DO 06 msec which will then be followed by a longer overprogram
01 05 pulse of 24 (0.1) (X) msec. X is an iteration counter and is
02 04 equal to the NUMBER of the initial 0.1 msec pulses ap-
Vss 03 plied before verification occurs. Up to four 0.1 msec pulses
0020-8 are provided before the overprogram pulse is applied.
Figure 3. Programming Pinouts The entire sequence of program pulses and byte verifica-
tions is performed at VCCP = 5.0V. When all bytes have
been programmed all bytes should be compared (Read
mode) to original data with Vcc = 5.0V.
3-10
START
Veep - 6.0V. Vpp - 13.6V
II
PROGRAM ONE PULSE

OF 0.1 msec
YES
FAIL
PROGRAM ONE PULSE

OF 24 (0.1) (X) msec
DEVICE BAD
READ ALL BYTES? FAIL

Vee =5.0V .....- - -......
0020-9
Figure 4. Programming Flowchart
3-11
~ CY7C225
~~~~UcrOR=====================================================================
Programming Sequence 512 x 8 Array
Power the device for I).ormal read mode operation with pin additional programming pulse should be applied of dura-
18, 19,20 and 21 at VIH. Per Figure 5 take pin 20 to Vpp. tion 24X the sum of the previous programming pulses be-
The device is now in the program inhibit mode of operation fore advancing to the next address to repeat the process.
with the output lines in a high impedance state; see Figure
5. Again per Figure 5 address, program, and verify one Blank Check
byte of data. Repeat this for each location to be pro- A virgin device contains neither one's nor zero's because of
grammed. the differential cell used for high speed. To verify that a
If the brute force programming method is used, the pulse PROM is unprogrammed, use the two blank check modes
width of the program pulse should be 10 ms, and each provided in Table 3. In both of these modes, address and
location is programmed with a single pulse. Any location read locations 0 thru 511. A device is considered virgin if
that fails to verify causes the device to be rejected. all locations are respectively "l's" and "O's" when ad-
If the intelligent programming technique is used, the pro- dressed in the "BLANK ONES AND ZEROS" modes.
gram pulse width should be 100 /J-s. Each location is ulti- Because a virgin device contains neither ones nor zeros, it
mately programmed and verified until it verifies correctly is necessary to program both one's and zero's. It is recom-
up to and including 4 times. When the location verifies, one mended that all locations be programmed to ensure that
ambiguous states do not exist.
PROGRAM
t + - - - - - PROGRAM------t_---VERIFY _ _ _......_ _O_TH"""ER 5 = = B Y T E S
VIHP -A~~RESS
VILP - - -
_ _ _ _... I.._ _ _ _r-__A_D_D_R_ES_S_S_TA_B_L_E__
1-
~---------'I "'__~
------0(
VIHP - - -
DATA ~--+---~j~-----------
~
VILP - - -
VPP---
PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -
VILP - - -
Ir-------~-------+--------------~S~-------------
VIHP - - -
PGM
VILP - - -
VIHP - - -
VILP - - -
0020-10
Figure S. PROM Programming Waveforms
3-12
~ CY7C225
~~~DU~R==================================================================
Speed
ns Ordering Package Operating
Code Type Range
tSA teo
CY7C225-250C 014
CY7C225-25LC L64
CY7C225-300C 014
CY7C225-30LC L64
CY7C225-30LMB L64
35 20 CY7C225-350MB 014 Military
CY7C225-35LMB L64
CY7C225-400C 014
CY7C225-40LC L64
CY7C225-40LMB L64
3-13
~ CY7C225
~~~~UcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
tSA 7,8,9,10,11
tHA 7,8,9,10,11
teo 7,8,9,10,11
tDP 7,8,9,10,11
tRP 7,8,9,10,11
Document #: 38-()()()()2-B
3-14
CY7C235
CYPRESS
SEMICONDUCTOR 1024 X 8 Registered PROM
Features
CMOS for optimum 5V 10% vcc, commercial and power, superior performance and high
speed/power military programming yield. The EPROM cell
requires only 13.5V for the supervolt- ~
High speed TTL compatible I/O
age and low current requirements allow ~
- 25 ns max set-up Direct replacement for bipolar
- 12 ns clock to output for gang programming. The EPROM
PROMs cells allow for each memory location to
Low power Capable of withstanding greater be tested 100%, as each location is
- 495 mW (commercial) than 1500V static discharge written into, erased, and repeatedly
- 660 mW (military) exercised prior to encapsulation. Each
Synchronous and asynchronous Product Characteristics PROM is also tested for AC perform-
output enables ance to guarantee that after customer
The CY7C235 is a high performance programming the product will meet
On-chip edge-triggered registers 1024 word by 8 bit electrically Pro- AC specification limits.
grammable Read Only Memory pack-
Programmable asynchronous The CY7C235 has an asynchronous
register (lNIT) aged in a slim 300 mil plastic or her-
metic DIP or 28-pin Leadless Chip car- initialize function (INIT). This func-
EPROM technology, 100% rier. The memory cells utilize proven tion acts as a 1025th 8-bit word loaded
programmable EPROM floating gate technology and into the on-chip register. It is user pro-
byte-wide intelligent programming al- grammable with any desired word or
Slim, 300 mil, 24 pin plastic or
gorithms. may be used as a PRESET or CLEAR
hermetic DIP or 28 pin LCC
function on the outputs.
The CY7C235 replaces bipolar devices
and offers the advantages of lower

mrr------~~~----------------------_,
A6
07
Ag
As
64.128 Os
A7 PROGRAMMABLE
~ ARRAY
A5 05
A4
04
03
A3
A2 COLUMN 02 0005-2
DECODER
Al 1 OF 16
0,
Ao
4 3
00 A4 5
A3 6
CP
A2 7
Al 8
Ao 9
ES
NC 10
00
0005-1
- N Q 0 If) ... an
OO%ZOOO
(!) 0005-12
Selection Guide
7C23S-2S 7C23S-30 7C23S-40
Maximum Set-up Time (ns) 25 30 40
Maximum Clock to Output (ns) 12 15 20
Maximum Operating
Current (rnA)
I Military 120 120
3-15
~ CY7C235
~~~akoUcrOR =====================================================================
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Volume ..................... > ISooV
(Pin 24 to Pin 12 for DIP) ............. -0.5V to + 7.0V Operating Range
in High Z State ...................... - O. 5V to + 7.0V Range Vee
Temperature
DC Input Voltage ................... -3.0V to +7.0V Commercial OCto + 70C 5V 1O%
DC Program Voltage Military [6] - 55C to + 125C 5V 1O%
(Pins 7, 18,20 for DIP) ........................ 14.0V

Vee = Min., IOH = - 4.0 mA
VIN = VIH or VIL
Vee = Min.,IOL = 16mA
VIN = VIH or VIL
Voltage for All Inputs[2]
Voltage for All Inputs [2]
IIX Input Leakage Current GND ::;; VIN ::;; Vee -10 + 10 /J-A
Input Clamp Diode
VeD Note 1
Voltage
Ioz Output Leakage Current GND ::;; Vo ::;; Vee Output Disabled[4] -40 +40 /J-A
los Vee = Max., VOUT = 0.OV[3] -20 -90 mA
Current
Icc Power Supply Current

GND ::;; VIN ::;; Vee I Commercial 90
mA
Vee = Max.
I Military 120
Capacitance [5]
pF
Notes:
1. The CMOS process does not provide a clamp diode. However, the 4. For devices using the synchronous enable, the device must be clocked
eY7e23s is insensitive to - 3V dc input levels and - SV undershoot after applying these voltages to perform this measurement.
pulses of less than 10 ns (measured at 50% point). 5. Tested initially and after any design or process changes that may
2. These are absolute voltages with respect to device ground pin and affect these parameters.
include all overshoots due to system and/or tester noise. Do not at- 6. TA is the "instant on" case temperature.
tempt to test these values without suitable equipment (see Notes on 7. See the last page of this specification for Group A subgroup testing
Testing). information.
3. For test purposes, not more than one output at a time should be
3-16
~ CY7C235
~~~NDUCTOR =======================================================================
7C235-25 7C235-30 7C235-40
tSA Address Setup to Clock HIGH 25 30 40 ns
tHA Address Hold from Clock HIGH 0 0 0 ns
teo
tpwe
Clock HIGH to Valid Output
Clock Pulse Width 12
12
15
15
20
20 ns
ns II
tSEs Es Setup to Clock HIGH 10 10 15 ns
tHEs ES Hold from Clock HIGH 5 5 5 ns
tOl Delay from INIT to Valid Output 25 25 35 ns
tRI INIT Recovery to Clock HIGH 20 20 20 ns
tpwI INIT Pulse Width 20 20 25 ns
teos Inactive to Valid Output from Clock HIGH[1] 20 20 25 ns
tHze Inactive Output from Clock HIGH[1, 3] 20 20 25 ns
tDOE Valid Output from E LOW[2] 20 20 25 ns
tHZE Inactive Output from E HIGH [2, 3] 20 20 25 ns
Notes:
1. Applies only when the synchronous (Es) function is used. 4. Tests are performed with rise and fall times of 5 ns or less.
2. Applies only when the asynchronous (E) function is used. 5. See Figure la for all switching characteristics except tHZ.
3. Transition is measured at steady state High level - 500 mV or steady 6. See Figure 1b for tHZ.
state Low level + 500 mV on the output from the 1. 5V level on the 7. All device test loads should be located within 2" of device outputs.
input with loads shown in Figure lb. 8. See the last page of this specification for Group A subgroup testing
information.
AC Test Loads and Waveforms [5,6,7]

R1 250 n R1250n ALL INPUT PULSES
5V O----.JVV'v--.., 5Vo----~~~~
3.0v-----~----~L
OUTPUT 0 - - -__- - -.....
OUTPUT 0 - - -.....- - -....
GND --.....;~
50 pF ~:711 5 pF R2 .;;5ns .;;5 ns
I-= INCLUDING
JIG AND
SCOPE -=
I_
-
INCLUDING
JIG AND _
SCOPE -
16712
Figure 2
0005-5
0005-3
Figure la Figure Ib
Equivalent to:
THEVENIN EQUIVALENT
100n
OUTPUT ~2.0V
0005-4
The CY7C235 is a CMOS electrically Programmable Read applying the memory location to the address input (Ao-
Only Memory organized as 1024 word x 8-bits and is a pin- A9) and a logic LOW to the enable (Es) input. The stored
for-pin replacement for bipolar TTL fusible link PROMs. data is accessed and loaded into the master flip-flops of the
The CY7C235 incorporates a D-type, master-slave register data register during the address set-up time. At the next
on chip, reducing the cost and size of pipelined micropro- LOW-to-HIGH transition of the clock (CP), data is trans-
grammed systems and applications where accessed PROM ferred to the slave flip-flops, which drive the output buff-
data is stored temporarily in a register. Additional flexibili- ers, and the accessed data will appear at the outputs (00-
ty is provided with synchronous (ES) and asynchronous 07) provided the asynchronous enable (E) is also LOW.
(E) output enables and asynchronous initialization (INIT). The outputs may be disabled at any time by switching the
Upon power-up, the synchronous enable CBs) flip-flop will asynchronous enable (E) to a logic HIGH, and may be
be in the set condition causing the outputs (00-07) to be returned to the active state by switching the enable to a
in the OFF or high impedance state. Data is read by logic LOW.
3-17
~ CY7C235
~~~~UaoR==================================================================
Regardless of the condition of:S, the outputs will go to the and the initialize function can be used to load any desired
OFF or high impedance state upon the next positive clock combination of"l"s and "O"s into the register. In the un-
edge after the synchronous enable (Bs) input is switched to programmed state, activating lNIT will generate a register
a HIGH level. If the synchronous enable pin is switched to CLEAR (all outputs LOW). If all the bits of the initialize
a logic LOW, the subsequent positive clock edge will re- word are programmed, activating INIT performs a register
turn the output to the active state ifE is LOW. Following a PRESET (all outputs HIGH).
positive clock edge, the address and synchronous enable
inputs are free to change since no change in the output will
Applying a LOW to the mrr input causes an immediate
load of the programmed initialize word into the master and
occur until the next low to high transition of the clock. slave flip-flops of the register, independent of all other in-
This unique feature allows the CY7C235 decoders and puts, including the clock (CP). The initialize data will ap-
sense amplifiers to access the next location while previously pear at the device outputs after the outputs are enabled by
addressed data remains stable on the outputs. bringing the asynchronous enable (B) LOW.
System timing is simplified in that the on-chip edge trig- When power is applied the (internal) synchronous enable
gered register allows the PROM clock to be derived direct- flip-flop will be in a state such that the outputs will be in
ly from the system clock without introducing race condi- the high impedance state. In order to enable the outputs, a
tions. The on-chip register timing requirements are similar clock must occur and the P;s input pin must be LOW at
to those of discrete registers available in the market. least a setu~time prior to the clock LOW to HIGH tran-
The CY7C235 has an asynchronous initialize input (INIT). sition. The E input may then be used to enable the outputs.
The initialize function is useful during power-up and time- When the asynchronous initialize input, INIT, is LOW,
out sequences and can facilitate implementation of other the data in the initialize byte will be asynchronously loaded
sophisticated functions such as a built-in "jump start" ad- into the output register. It will not, however, appear on the
dress. When activated the initialize control input causes the output pins until they are enabled, as described in the pre-
contents of a user programmed 1025th 8-bit word to be ceding paragraph.
loaded into the on-chip register. Each bit is programmable
Switching Waveforms
AO-A,O ________________________________~--~~~~----+_--.J~~~~~~~------------------
CP
Notes on Testing
device Vee and ground terminals. Multiple capacitors are recom- and the test system ground can create significant reQuctions in observ-
mended, including a 0.1 p,F or larger capacitor and a 0.01 p,F or able input noise immunity.
smaller capacitor placed as close to the device terminals as possible. 4. Output levels are measured at 1.SV reference levels.
Inadequate decoupling may result in large variations of power supply S. Transition is measured at steady state HIGH level - SOO mVor
voltage, creating erroneous function or transient performance failures. steady state LOW level + SOO mV on the output from the l.SV level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure lb.
3-18
~ CY7C235
~~~NDUcrOR =====================================================================
NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT NORMALIZED CLOCK TO OUTPUT
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE TIMEvs. Vee
1.8 1.2,..-----..,.-------, 1.6
w
:I
j:

1.4 ~ 1.4
1.1 t-----+-------f
0
w
u
.!:
1.2 / JI
o
~
~
go 1.2 "-
"
~
N
/
------
:::i
~
:::i ~
.J
:I 1.0 :I ~ 1.0
V
II: II:
0 w
z liE N
:::i
0.8 < 0.8
0.8
V TA - 25C
f-MAX.
0.80 ......_ _ _ _..I...-_ _ _ _ _..J
:I
II:
oZ
0.6
TA i 25C
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ec) SUPPLY VOLTAGE (V)
NORMALIZED CLOCK TO OUTPUT NORMALIZED SETUP TIME NORMALIZED SETUP TIME

TIME vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE
w 1.6,------T"""'------, 1.6
:I 1.2
j:
I-
w ~
1.4 t-----+-------f ~
~
:I 1.4
~ j: 1.0 Go
~
~ ~
o Go
~
I-
w
g
-
I-
~
III 1.2
w 0
~ III
0 0.8
w
9 N
-
w ::::i
N
CJ :::i < 1.0
oW < :I
II:
N
:I 0
:::i
II: 0.6 z
0.8 t-----+-------f z0 0.8
~
II: TA i 2SoC
i 0.8~------~--------~ 0.4 0.6
-55 25 125 4.0 4.5 5.0 5.5 8.0 -56 25 125
AMBIENT TEMPERATURE (OC) SUPPL Y VOLTAGE (V) AMBIENT TEMPERATURE (OC)
vs. OUTPUT VOLTAGE vs. OUTPUT LOADING vs.OUTPUTVOLTAGE
60 30.0 175
ct
.s
I-
Z
w
50
40 ~ !
25.0
/ --- ct
.s
I-
zw
150
125
,;t""
---
II:
II:
~
CJ
w 30
" ~ :
c
20.0
15.0
/
II:
II:
~
CJ
100
/
/ "
""
CJ ~
z
II:
~
!:i /" iii
75
~ 20 ~ 10.0
i / Vee -5.0 V
TA -25C
~V
I- TA - 25C 50
~
~ 10 6.0
Vee -4.5V
~ /
~
0 25
~
0
o
o 1.0 2.0 3.0 4.0
0.0 /
o 200 400 600 800 1000
o
V
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V) CAPACITANCE (pF) OUTPUT VOLTAGE (V)
0005-7
3-19
~ CY7C235
~~~~NDUcrOR =======================================================================
Device Programming
Overview:
There are two independent programmable functions con- the use of the initialize function. The 1K x 8 array uses a
tained in the 7C235 CMOS lK x 8 Registered PROM; the differential memory cell, with differential sensing tech-
lK x 8 array, and the INITIAL BYTE. All of the pro- niques. In the erased state the cell contains neither a one
gramming elements are "EPROM" cells, and are in an nor a zero. The erased state of this array may be verified by
erased state when the device is shipped. The erased state using the "BLANK CHECK ONES" and "BLANK
for the "INITIAL BYTE" is all "O's" or "LOW". The CHECK ZEROS" function, see Table 3.
"INITIAL BYTE" may be accessed operationally through

Table 1
VOL[2] Output Low Voltage 0.4 V
Ipp Programming Supply Current 50 mA
AC Programming Parameters TA = 25C

Table 2
tpp Programming Pulse Width 100 10,000 ,..,S
tAS Address Setup Time 1.0 ,..,s

tos Data Setup Time 1.0 ,..,S
tAH Address Hold Time 1.0 ,..,S
tOH Data Hold Time 1.0 ,..,S
tR,tp[3] Vpp Rise and Fall Time 1.0 ,..,S
tvo Delay to Verify 1.0 ,..,S
tvp Verify Pulse Width 2.0 ,..,S

tov Verify Data Valid 1.0 ,..,s
toz Verify HIGH to High Z 1.0 ,..,s
Notes:
1. V ccp must be applied prior to Vpp.
2. Ouring verify operation.
3. Measured 10% and 90% points.
3-20
~ClPRFSS CY7C235
WnrCONDucroR =========================================
Mode Selection
Table 3
Pin Function
Read or Output Disable A2 CP Es INIT E Al Outputs

Mode Other A2 PGM VFY Vpp E Al (9-11,13-17)
DIP
(DIP) Pin (6) (18) (19) (20) (21) (7)
Read [2,3] X X VIL VIH VIL X Data Out
Output Disable[5] X X VIH VIH X X HighZ
Output Disable X X X VIH VIH X HighZ
Initialize[6] X X X VIL VIL X 1025th word
Program[I,4] X VILP VIHP Vpp VIHP X Data In
Program Verify[I,4] X VIHP VILP Vpp VIHP X Data Out
Program Inhibit[I,4] X VIHP VIHP Vpp VIHP X HighZ
Intelligent Program[1,4] X VILP VIHP Vpp VIHP X Data In
Program Initial Byte[4] VILP VILP VIHP Vpp VIHP Vpp Data In
Blank Check Ones[I,4] X Vpp VILP VILP VILP X Ones
Blank Check Zeros[I,4] X Vpp VIHP VILP VILP X Zeros
Notes:
2. During read operation, the output latches are loaded on a "0" to "I" VILP
transition ofCP. 5. Pin 19 must be HIGH prior to the "0" to "I" transition on CP (18)
3. Pin 19 must be LOW prior to the "0" to "I" transition on CP (18) that loads the register.
that loads the register. 6. LOW to HIGH clock transition required to enable outputs.

10 msec.
A7 Vce
Typical programming time for a byte is less than 2.5 msec.
A6 As
As Ag grammed cells, measurement of data retention and erasure
A4 E to ensure reliable data retention and functional perform-
A3 VPP (lNIT) ance. A flowchart of the algorithm is shown in Figure 4.
A2 VFY (Es) The algorithm utilizes two different pulse types: initial and
A, PGM (CP) overprogram. The duration of the PGM pulse (tpp) is 0.1
Ao 07 msec which will then be followed by a longer overprogram
DO 06 pulse of 24 (0.1) (X) msec. X is an iteration counter and is
0, Os equal to the NUMBER of the initial 0.1 msec pulses ap-
02 04
plied before verification occurs. Up to four 0.1 msec pulses
are provided before the overprogram pulse is applied.
Vss D3
0005-8 The entire sequence of program pulses and byte verifica-
Figure 3. Programming Pinouts tions is performed at V cCP = 5.0V. When all bytes have
been programmed all bytes should be compared (Read
mode) to original data with V cc = 5.0V.
3-21
~CYPRESS CY7C235
~~I~UcrOR==================================================================
START
VCCP = 5.0V. Vpp = 13.5V
PROGRAM ONE PULSE

OF 0.1 msec
FAIL
PROGRAM ONE PULSE

OF 24 eO.11 eXI msec
DEVICE BAD

Vce = S.OV 1 - - - - -.....
0005-9
3-22
~ CY7C235
~~~NDUcrOR ==================================================================~
Programming Sequence lK x 8 Array
Power the device for normal read mode operation with pin location is programmed with a single pulse. Any location
18,19,20 and 21 at VIR. Per Figure 6 take pin 20 to Vpp. that fails to verify causes the device to be rejected.
The device is now in the program inhibit mode of operation If the intelligent programming technique is used, the pro-
with the output lines in a high impedance state; see Figures gram pulse width should be 100 fJ-s. Each location is ulti-
5 and 6. Again per Figure 6 address program and verify mately programmed and verified until it verifies correctly
one byte of data. Repeat this for each location to be pro-
grammed.
up to and including 4 times. When the location verifies, one
additional programming pulse should be applied of dura-
3
If the brute force programming method is used, the pulse tion 24X the sum of the previous programming pulses be-
width of the program pulse should be 10 ms, and each fore advancing to the next address to repeat the process.
PROGRAM
\4----- PROGRAM---_~---VERIFY _ _ _-!+--O-TH~ER ~BYTES

~~---
V'LP ~~D_RESS _ _ _"'I~_~_~ _ _ _ _ _ _-+________II"_ _-; ~_ __
V'HP---
OATA - - - - - - (
~~~--~j~-----------
~
VILP - - -
Vpp---
VIHP - - -
V'LP---
VIHP - - -
i5GM
V'LP---
VIHP - - -
VILP - - -
0005-10
Figure 5. PROM Programming Waveforms
____~I
~------------------PROGRAM-----------------------~
1------
VIV - - -
Vpp---
VIHP - - -
VILP---
VIHP - - -
DATA
VILP - - -
---+----.....,
~----------------~H------------------~
Vpp---
PROGRAMMING
VOLTAGE (PIN 20, DIP)
VIHP---
V.LP - - -
VIHP---
PGM
VILP---
0005-11
Figure 6. Initial Byte Programming Waveforms
3-23
~ CY7C235
~~~~ucr~==~~~~====================================~======~==========
Programming the Initial Byte Blank Check
The CY7C235 registered PROM has a 1025th byte of data A virgin device contains neither one's nor zero's because of
used to initialize the value of the register. This initial byte the differential cell used for high speed. To verify that a
is value "0" when the part is received. If the user desires to PROM is unprogrammed, use the two blank check modes
have a value other than "0" for register initialization, this provided in Table 3. In both of these modes, address and
must be programmed into the 1025th byte. This byte is read locations 0 thru 1023. A device is considered virgin if
programmed in a similar manner to the 1024 normal bytes all locations are respectively "1 's" and "O's" when address-
in the array except for two considerations. First, since all of es in the "BLANK ONES AND ZEROS" modes.
the normal addresses of the part are used up, a super volt- Because a virgin device contains neither ones nor zeros, it
age will be used to create additional effective addresses. is necessary to program both one's and zero's. It is recom-
The actual address has Vpp on Al pin 7, and VILP onA2, mended that all locations be programmed to ensure that
pin 6, per Table 3. The programming and verification of ambiguous states do not exist.
"INITIAL BYTE" is accomplished operationally by per-
forming an initialize function.
BitMap Data Ordering Information

Programmer Address RAM Data Speed
ns Ordering Package Operating
Decimal Hex Contents Code Type Range
0 0 Data tsA teo
CY7C235-25DC D14
30 15 CY7C235-30PC P13
1023 3FF Data CY7C235-30DC D14
1024 400 Init Byte CY7C235-30JC J64
CY7C235-30LMB L64
40 20 CY7C235~4OPC P13 Commercial
CY7C235-4ODC D14
CY7C235-4ODMB D14 Military
CY7C235-4OLMB L64
3-24
~ CY7C235
~~~NOOcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
tSA 7,8,9,10,11
tHA 7,8,9,10,11
teo 7,8,9,10,11
3-25
CY7C245
CYPRESS
SEMICONDUCTOR Reprogrammable 2048 X 8
Registered PROM
Features
Windowed for reprogrammability Programmable synchronous or 5V 10% Vee, commercial and
CMOS for optimum asynchronous output enable military
speed/power On-chip edge-triggered registers TIL compatible I/O
High speed Programmable asynchronous Direct replacement for bipolar
- 25 ns max set-up register (INIT) PROMs
- 12 ns clock to output Capable of withstanding greater
EPROM technology, 100%
Low power programmable than 2000V static discharge
- 330 mW (commercial) for
-35 ns, -45 ns Slim, 300 mil, 24 pin plastic or
hermetic DIP
- 660 mW (military)
INIT------~~o-----------------------_,
A,o
Ag
As ROW 128 x 128
A7 DECODER PROGRAMMABLE
A6 1 OF 128 ARRAY
A5
A4
0016-2
COLUMN 1------------...1 02
DECODER
1 OF 16 I------------------J 0,
00 A. ~
A3 INIT
0
A2 EIEs
CP-..... " __....,.--"" A, 8 CP
Ao 9 21 NC
0016-1 NC 10
70 6
0 11
12131415161718
19
- ('ooIQ U t i ) ... II)

0 OZzOOO
C>
0016-13
Selection Guide
7C245-25 7C245-35 7C24545
Maximum Setup Time (ns) 25 35 45
Commercial 90 90 90
Maximum Operating STD
L Commercial 60 60
3-26
~ CY7C245
~~~UcrOR==================================================================
Product Characteristics Maximum Ratings
The CY7C245 is a high performance 2048 word by 8 bit (Above which the useful life may be impaired. For user
electrically Programmable Read Only Memory packaged guidelines, not tested.)
in a slim 300 mil plastic or hermetic DIP. The ceramic Storage Temperature ............... -65C to + 150"C
package may be equipped with an erasure window; when Ambient Temperature with
exposed to UV light the PROM is erased and can then be Power Applied .................... - 55C to + 125C

reprogrammed. The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent program- Supply Voltage to Ground Potential
ming algorithms. (Pin 24 to Pin 12) .................... -0.5V to + 7.0V
The CY7C245 replaces bipolar devices and offers the ad- DC Voltage Applied to Outputs
vantages of lower power, reprogrammability, superior per- in High Z State ...................... -0.5V to +7.0V
formance and high programming yield. The EPROM cell DC Input Voltage ................... ...:. 3.0V to + 7.0V
requires only 13.5V for the supervoltage and low current DC Program Voltage (Pins 7, 18,20) ............. 13.0V
requirements allow for gang programming. The EPROM
UV Erasure .................. , ....... 7258 Wsec/cm2
cells allow for each memory location to be tested 100%, as
each location is written into, erased, and repeatedly exer- Static Discharge Voltage ..................... > 200 1V
cized prior to encapsulation. Each PROM is also tested for (Per MIL-STD-883 Method 3015)
AC performance to guarantee that after customer pro- Latchup Current .......................... > 200 rnA
gramming the product will meet AC specification limits.
Operating Range
The CY7C245 has an asynchronous initialize function
(INIT). This function acts as a 2049th 8-bit word loaded Ambient
Range Vee
into the on-chip register. It is user programmable with any Temperature
desired word or may be used as a PRESET or CLEAR Commercial OCto +70C SV 1O%
function on the outputs.
Military [7] - SSC to + 12SC SV 1O%
7C245L-35, 45 7C245-25 7C245-35, 45
Output HIGH Voltage Vee = Min.,loH = -4.0mA 2.4 2.4 2.4 V
VOH
VIN = VIH or VIL
Output LOW Voltage Vee = Min.,IOL = 16 mA 0.4 0.4 0.4 V
VOL VIN = VIH or VIL
Input HIGH Level Guaranteed Input Lo~ical HIGH 2.0 2.0 2.0 V
VIH Voltage for All Inputs 1] Vee Vee Vee
Input LOW Level Guaranteed Input Lo~ical LOW 0.8 0.8 0.8 V
VIL Voltage for All Inputs 1]
IIX Input Leakage Current GND =s;; VIN =s;; Vee -10 +10 -10 +10 -10 +10 p.A
Input Clamp Diode
VeD NoteS NoteS
Voltage
GND =s;; Vo =s;; V~e
Output Leakage Current Output -40 +40 -40 +40 -40 +40 p.A
loz Disabled[3
Output Short Circuit Vee = Max., VOUT = 0.OV[2] -20 -90 -20 -90 -20 -90
los mA
Current

GND =s;; VIN =s;; Vee Commercial l 60 90 90
mA
Vee = Max. Military I 120
Capacitance [4]
CIN Input Capacitance TA = 2SC, f = 1 MHz S
pF
COUT
Notes:
1. These are absolute voltages with respect to device ground pin and 4. Tested initially and after any design or process changes that may
include all overshoots dueto system and/or tester noise. Do not at- affect these parameters.
tempt to test these values without suitable equipment (see Notes on 5. The eMOS process does not provide a clamp diode. However, the
Testing). eY7C245 is insensitive to - 3V dc input levels and - 5V undershoot
2. For test purposes, not more than one output at a time should be pulses ofless than 10 ns (measured at 50% point).
shorted. Short circuit test duration should not exceed 30 seconds. 6. See the last page of this specification for Group A subgroup testing
3. For devices using the synchronous enable, the device must be clocked information.
after applying these voltages to perform this measurement. 7. TA is the "instant on" case temperature.
3-27
~RESS
.nEMICONDUcrOR ====================================
CY7C245

7C24525 7C24535 7C24545
tSA Address Setup to Clock HIGH 25 35 45 ns
tHA Address Hold from Clock HIGH 0 0 0 ns
teo Clock HIGH to Valid Output 12 15 25 ns
tpwc Clock Pulse Width 15 20 20 ns
tSEs Es Setup to Clock HIGH 12 15 15 ns
tHES Es Hold from Clock HIGH 5 5 5 ns
tm Delay from INIT to Valid Output 20 20 35 ns
tRI INIT Recovery to Clock HIGH 15 20 20 ns
tPWI INIT Pulse Width 15 20 25 ns
Valid Output from
teos 15 20 30 ns
Clock HIGH[l]
tHZC Inactive Output from Clock HIGH[I, 3] 15 20 30 ns
tDOE Valid Output from E LOW[2] 15 20 30 ns
tHZE EHIGH[2,3] 15 20 30 ns
Notes:
1. Applies only when the synchronous CES) function is used. 5. See Figure 1a for all switching characteristics except tHZ.
2. Applies only when the asynchronous (E) function is used. 6. See Figure 1b for tHZ.
3. Transition is measured at steady state High level - 500 mV or steady 7. All device test loads should be located within 2" of device outputs.
state Low level + 500 mV on the output from the 1.5V level on the 8. See the last page of this specification for Group A subgroup testing
input with loads shown in Figure 1b. information.
4. Tests are performed with rise and fall times of 5 ns or less.
AC Test Loads and Waveforms[S, 6, 7]

R1250n R1 260 n ALL INPUT PULSES
6v Q----"IM---. 6V o-----tv'.--,
3.0V-----~~~--~1.
OUTPUTQ--_---t OUTPUT o - - _ - - - t
r
50PF R2 6pF R2 GND
I
167!! 167!!
INCLUDING INCLUDING .;5 ns .;5 ns
,:,~~~~D
JIG AND 0016-5
':' SCOPE ':' ':'
0016-3 Figure 2
Figure la Figure Ib
Equivalent to:
THEVENIN EQUIVALENT
loon
OUTPUT ~2.0V 0016-4
The CY7C245 is a CMOS electrically Programmable Read (00-07) to be in the OFF or high impedance state. If the
Only Memory organized as 2048 words x 8bits and is a asynchronous enable (E) is being used, the outputs will
pin-for-pin replacement for bipolar TTL fusible link come up in the OFF or high impedance state only ifthe
PROMs. The CY7C245 incorporates aD-type, master- enable (E) input is at a HIGH logic level. Data is read by
slave register on chip, reducing the cost and size of pipe- applying the memory location to the address inputs
lined microprogrammed systems and applications where (AQ-AIO) and a logic LOW to the enable input. The stored
accessed PROM data is stored temporarily in a register. data is accessed and loaded into the master flip-flops of the
Additional flexibility is provided with a programmable data register during the address set-up time. At the next
synchronous (Es) or asynchronous (E) output enable and LOW~to-HIGH transition of the clock (CP), data is trans-
asynchronous initialization (INIT). ferred to the slave flip-flops, which drive the output buff-
Upon power-up the state ofthe outputs will depend on the ers, and the accessed data will appear at the outputs
programmed state of the enable function (Es or E). If the (00- 0 7)'
synchronous enable (ES) has been programmed, the regis- If the asynchronous enable (E) is being used, the outputs
ter will be in the set condition causing the outputs may be disabled at any time by switching the enable to a
~RE$S CY7C245
_~ICONDUcrOR ==========================================================
logic HIGH, and may be returned to the active state by The CY7C245 has an asynchronous initialize input (INIT).
switching the enable to a logic LOW. The initialize function is useful during power-up and time-
If the synchronous enable (s) is being used, the outputs out sequences and can facilitate implementation of other
will go to the OFF or high impedance state upon the next sophisticated functions such as a built-in "jump start" ad-
positive clock edge after the synchronous enable input is dress. When activated the initialize control input causes the
switched to a HIGH level. If the synchronous enable pin is contents of a user programmed 2049th 8-bit word to be
switched to a logic LOW, the subsequent positive clock loaded into the on-chip register. Each bit is programmable
edge will return the output to the active state. Following a and the initialize function can be used to load any desired
positive clock edge, the address and synchronous enable combination of" 1"s and "O"s into the register. In the un-
inputs are free to change since no change in the output will programmed state, activating INIT will generate a register
occur until the next low to high transition of the clock. CLEAR (all outputs LOW). If all the bits of the initialize
This unique feature allows the CY7C245 decoders and word are programmed, activating INIT performs a register
sense amplifiers to access the next location while previously PRESET (all outputs HIGH).
addressed data remains stable on the outputs. Applying a LOW to the INIT input causes an immediate
System timing is simplified in that the on-chip edge trig- load of the programmed initialize word into the master and
gered register allows the PROM clock to be derived direct- slave flip-flops of the register, independent of all other in-
ly from the system clock without introducing race condi- puts, including the clock (CP). The initialize data will ap-
tions. The on-chip register timing requirements are similar pear at the device outputs after the outputs are enabled by
to those of discrete registers available in the market. bringing the asynchronous enable (E) LOW.
Switching Waveforms
AO-Al0 ----------------------------------1-----~~~-----t----~~~~~~~--------------------
Es
CP
INIT
0016-6
Notes on Testing
Inc?mi.ng test procedures on these devices should be carefully planned, 3. Do not attempt to perform threshold tests under AC conditions.
takmg mto account the high performance and output drive capabilities of Large amplitude, fast ground current transients normally occur as the
Inadequate decoupling may result in large variations of power supply 5. Transition is measured at steady state HIGH level - 500 m V or
voltage, creating erroneous function or transient performance failures. steady state LOW level + 500 mV on the output from the 1.5V level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure Jb.
3-29
~ CY7C245
~~~NDUcrOR =====================================================================

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. Vee
1.6 1.2.-------r------.., w
1.6
~
j:
1.4 !5 1.4
/
1.11------+-------1 IL
~
tJ I-
.!i ;:)
~
0
w 1.2 o
W eo 1.2
/ "'
N N
:::i :::i
~
--- -
~
< < -J
~
a:
1.0 ~
a: ~ 1.0
0
2
O.B / i
w
N
:::i
< 0.8
,,/' TA =25C
f"MAX. O.BO'--_ _ _ _..L.-_ _ _ _ _ ~
~
II:
o2 TA i 25C
0.6 0.6
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE rc) SUPPLY VOLTAGE (V)

vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE
~ 1 . 6 r - - - - - - - r - - - - - -.... 1.6
1.2
j:
I-
~ 1.4 r-----+-------I
w
~
~ ............. 1.4
j: 1.0 IL
" '"
;:) ;:)
o IL I-
e 1.2t-----t----'7I"~-i
;:)
I-
W
III 1.2
-
W
~ III 0
cw O.B w
9 N
CJ
o
w
N
~
1.0 r-------::;;;""""''-------I
O.Bt-----t-------i
N
:::i
<
~
II:
0
2
0.6
:::i
<
~
a:
0
2
1.0
0.8
-
~
a: TA i 2!iC
i 0.6
-55
'-------'-------...1
25 125
0.4
4.0 4.5 5.0 5.5 6.0
0.6
-55 25 125
AMBIENT TEMPERATURE (OC) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC)
vs. VOLTAGE vs. OUTPUT LOADING vs. OUTPUT VOLTAGE
60 30.0 175
<
! 50 25.0
,,-- < 150
! ~
40 ~ /
I-
2 I-
2 125 ~
w
a: ! 20.0 w
a: V
"'"
a: ./
w
;:)
CJ
30 ;

15.0 / a:
;:)
CJ
100
/
" '"
~
CJ
a: ~ /v 2
iii
75
Vee =5.0V
J
;:)
0 20 ~ 10.0 TA = 25C
III
!5
I- V TA = 25C IL
50
IL
I-
;:)
10 5.0 ~
Vee" 4.5 V I-
;:)
0 25 /
'" V
;:)
0
o 0.0 o
V
o 1.0 2.0 3.0 4.0 o 200 400 600 BOO 1000 0.0 1.0 2.0 3.0 4.0
0016-7
3-30
~RESS CY7C245
WnICONDUcrOR ====================================================================
Erasure Characteristics Device Programming
Wavelengths of light less than 4000 Angstroms begin to OVERVIEW:
erase the 7C245. For this reason, an opaque label should be
placed over the window ifthe PROM is exposed to sun- There are three independent programmable functions con-
light or fluorescent lighting for extended periods of time. tained in the 7C245 CMOS 2K x 8 Registered PROM; the
2K x 8 array, the initial byte, and the synchronous enable
The recommended dose for erasure is ultraviolet light with bit. All of the programming elements are "EPROM" cells,
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm2. For an ultra-
and are in an erased state when the device is shipped. This
erased state manifests itself differently in each case. The
3
violet lamp with a 12 m W/ cm2 power rating the exposure erased state for ENABLE bit is the "ASYNCHRONOUS
time would be approximately 30-35 minutes. The 7C245 ENABLE" mode. The erased state for the "INITIAL
needs to be within 1 inch of the lamp during erasure. Per- BYTE" is all "O's" or "LOW". The "INITIAL BYTE"
manent damage may result if the PROM is exposed to high may be accessed operationally thru the use of the initialize
intensity UV light for an extended period of time. 7258 function. The 2K x 8 array uses a differential memory cell,
Wsec/cm 2 is the recommended maximum dosage. with differential sensing techniques. In the erased state the
cell contains neither a one nor a zero. The erased state of
this array may be verified by using the "BLANK CHECK
ONES" and "BLANK CHECK ZEROS" function, see
Table 3.
DC Programming Parameters T A = 25C

Table 1
Vpp[1] Programming Voltage 12.0 13.0 V
VOL [2] Output Low Voltage 0.4 V

Table 2
tpp Programming Pulse Width 100 10,000 /Ls
tAS Address Setup Time 1.0 /Ls
tos Data Setup Time 1.0 /Ls
tAH Address Hold Time 1.0 /Ls
tOH Data Hold Time 1.0 /Ls
tR, tF[3] Vpp Rise and Fall Time 1.0 /Ls
tvo Delay to Verify 1.0 /Ls
tvp Verify Pulse Width 2.0 /Ls
tov Verify Data Valid 1.0 /Ls
toz Verify HIGH to High Z 1.0 /Ls
Notes:
1. vccp must be applied prior to Vpp.
3-31
~ CY7C245
~J'~NDUcrOR=====================================================================
Mode Selection
Table 3
Pin Function
Read or Output Disable A2 CP E/Es INIT Al
Mode Outputs
Other A2 :roM VFY Vpp Al (9-11,13-17)
Pin (6) (18) (19) 20 (7)
Read[2,3] X X VIL VIH X Data Out
O~tput Disable[5] X X VIH VIH X HighZ
Program [1,4] X VILP VIHP Vpp X Data In
Program Verify[l,4] X VIHP VILP Vpp X Data Out
Program Inhibit[I,4] X VIHP VIHP Vpp X HighZ
Intelligent Program[I,4] X VILP VIHP Vpp X Data In
Program Synch Enable[4] VIHP VILP VIHP Vpp Vpp HighZ
Program Initial Byte [4] VILP VILP VIHP Vpp Vpp Data In
Blank Check Ones[l,4] X Vpp VILP VILP X Ones
Blank Check Zeros[l,4] X Vpp VIHP VILP X Zeros
Notes:
2. During read operation, the output latches are loaded on a "0" to "1" VILP
transition of CP. 5. If the registered device is being operated in a synchronous mode, pin
3. If the registered device is being operated in a synchronous mode, pin 19 must be HIGH prior to the "0" to "I" transition on CP (18) that
19 must be LOW prior to the "0" to "I" transition on CP (18) that loads the register.
loads the register~

10 msec.
A7 Vcc Typical programming time for a byte is less than 2.5 msec.
As
As
A5 As
A4 A,o
ance. A flowchart of the algorithm is shown in Figure 4.
A3 vpp (lNIT)
The algorithm utilizes two different pulse types: initial and
A2 VFV (E/Es)
overprogram. The duration of the PGM pulse (tpp) is 0.1
A, PGM (CP)
msec which will then be followed by a longer overprogram
Ao 07 pulse of 24 (0.1) (X) msec. X is an iteration counter and is
Do Os equal to the NUMBER of the initial 0.1 msec pulses ap-
0, 05 plied before verification occurs. Up to four 0.1 msec pulses
02 04 are provided before the overprogram pulse is applied.
Vss 03 The entire sequence of program pulses and byte verifica-
0016-8 tions is performed at Vccp = 5.0V. When all bytes have
Figure 3. Programming Pinouts been programmed all bytes should be compared (Read
mode) to original data with Vcc = 5.0V.
BitMap Data
Programmer Address RAM Data
Decimal Hex Contents
0 0 DATA

2047 7FF DATA
2048 800 INITBYTE
2049 801 CONTROL BYTE
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
3-32
~~~===================================================C=Y=7=C==2=4=5
START
Vccp = 500V. Vpp = 1305V
II
PROGRAM ONE PULSE

OF 0.1 msec
YES
FAIL
PROGRAM ONE PULSE

OF 24 (OoH (XI msec
DEVICE BAD
...-_--_..
Vee SoO ......- - -.....
0016-9
3-33
Programming Sequence 2K x 8 Array
18, 19 and 20 at VIR. Per Figure 5 take pin 20 to Vpp. The that fails to verify causes the device to be rejected.
device is now in the program inhibit mode of operation If the intelligent programming technique is used, the pro-
with the output lines in a high impedance state; see Figures
gram pulse width should be 100 fJ-s. Each location is ulti-
5 and 6. Again per Figure 5 address program and verify
mately programmed and verified until it verifies correctly
one byte of data. Repeat this for each location to be pro- up to and including 4 times. When the location verifies, one
grammed.
additional programming pulse should be applied of dura-
If the brute force programming method is used, the pulse tion 24X the sum of the previous programming puJses be-
width ofthe program pulse should be 10 ms, and each
VIHP -A~~RESS
VILP - - -
____
1 - - - - - - PROGRAM-----r__---VERIFY _ _ _.....__-OT_H-\ER
"I'---.....j~--A-D-DR-E-SS-S-T-A-BL-E-I_---------II--~
:t
fore advancing to the next address to repeat the process.
PROGRAM
BYTES
VIHP - - -
DATA ------0( ~--~----~ j~-------------
~
VILP - - -
VPP - - -
0016-10
I-----------------PROGRAM--------------------~
VIHP - - -
Vpp - - -
VILP - - -
VIHP - - -
DATA ----~-----__f
VILP - - -
1---------------tAH-----------~
Vpp---
PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -
VILP - - -
tpp
VIHP - - -
VILP - - - 0016-11
3-34
~ CY7C245
~~~~U~R==================================================================
Programming the Initialization Byte Programming Synchronous Enable
The CY7C245 registered PROM has a 2049th byte of data The CY7C245 provides for both a synchronous and asyn-
used to initialize the value of the register. This initial byte chronous enable function. The device is delivered in an
is value "0" when the part is received. If the user desires to asynchronous mode of operation and only requires that the
have a value other than "0" for register initialization, this user alter the device if synchronous operation is required.
must be programmed into the 2049th byte. This byte is The determination of the option is accomplished thru the
programmed in a similar manner to the 2048 normal bytes use of an EPROM cell which is programmed only if syn-
in the array except for two considerations .. First, since all of
the normal addresses of the part are used up, a super volt-
age will be used to create additional effective addresses.
chronous operation is required. As with the INITIAL byte,
this function is addressed thru the use of a supervoltage.
Per Table 3, Vpp is applied to pin 7 (AI) with pin 6 (A2) at
a:.
.:.
The actual address has Vpp on Al pin 7, and VILP on A2, VIHP. This addresses the cell that programs synchronous
pin 6, per Table 3. The programming and verification of enable. Programming the cell is accomplished with a 10 ms
"INITIAL BYTE" is accomplished operationally by per- program pulse on pin 18 (roM) but does not require any
forming an initialize function. data as there is no choice as to how synchronous enable
may be programmed, only if it is to be programmed.
VIHP - - -
VILP - - -
t----tAs - - - - t
VIHP - - -
PGM
VILP - - -
t----tAs - - - - t _ - - - - t p P ------..!
VIHP - - -
VFY
VILP - - -
Vpp - - -
VIHP - - -
VILP - - -
Vpp---
PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -
VILP - - -
0016-12
Figure 7. Program Synchronous Enable
Verification of Synchronous Enable Blank Check

Verification of the synchronous enable function is accom- A virgin device contains neither one's nor zero's because of
plished operationally. Power the device for read operation the differential cell used for high speed. To verify that a
with pin 20 at VIH, cause clock pin 18 to transition from PROM is unprogrammed, use the two blank check modes
VIL to VIH. The output should be in a High Z state. Take provided in Table 3. In both of these modes, address and
pin 20, ENABLE, to VIL. The outputs should remain in a read locations 0 thru 2047. A device is considered virgin if
high Z state. Transition the clock from VIL to VIH, the all locations are respectively "I 's" and "O's" when ad-
outputs should now contain the data that is present. Again dressed in the "BLANK ONES AND ZEROS" modes.
set pin 19 to VIH. The output should remain driven. Clock- Because a virgin device contains neither ones nor zeros, it
ing pin 18 once more from VIL to VIH should place the is necessary to program both one's and zero's. It is recom-
outputs again in a High Z state. mended that all locations be programmed to ensure that
3-35
~ CY7C245
~~~~UqOR==================================================================
Speed (ns) Icc Ordering Package Operating Speed (ns) Icc Ordering Package Operating
rnA Code Type Range rnA Code Type Range
tSA teo tSA teo
25 12 90 CY7C245-25PC P13 Commercial 45 25 60 CY7C245L-45PC P13 Commercial
CY7C245-25WC W14 CY7C245L-45WC W14
35 15 60 CY7C245L-35PC P13 Commercial 90 CY7C245-45PC P13
CY7C245L-35WC W14 CY7C245-458C 813
90 CY7C245-35PC P13 CY7C245-45WC W14
CY7C245-35SC S13 CY7C245-45LC L64
CY7C245-35WC W14 120 CY7C245-45WMB W14 Military
CY7C245-35LC L64 CY7C245-45LMB L64
120 CY7C245-350MB 014 Military CY7C245-450MB 014
CY7C245-35QMB Q64 CY7C245-45QMB Q64
CY7C245-35WMB W14
CY7C245-35LMB L64
3-36
~ CY7C245
~~~NOOcrOR============================================================
DC Characteristics
VOH 1,2,3
VOL
VIH
VIL
1,2,3
1,2,3
1,2,3
III
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
tSA 7,8,9,10,11
tHA 7,8,9,10,11
teo 7,8,9,10,11
3-37
CY7C245A
CYPRESS
Registered PROM
Features
Windowed for reprogrammability Programmable synchronous or 5V 10% Vcc, commercial and
asynchronous output enable military
CMOS for optimum
speed/power Onchip edgetriggered registers TTL compatible I/O
High speed Programmable asynchronous Direct replacement for bipolar
- 15 ns max setup register UNIT) PROMs
- 10 ns clock to output EPROM technology, 100% Capable of withstanding greater
Low power programmable than 2000V static discharge
- 330 mW (commercial) for Slim, 300 mil, 24 pin plastic or
-35 os hermetic DIP
- 660 mW (military)
0121-2
~~<''i~.f~
4 3 2 :1.282726
A4 5 25 A,o
A3
A27
A, 8
Ao 9
6
0 23
22
21
INIT
CP
NC
NC 10 07
0 0 11 19 06
12131415161718
- NO (,) tt); ...,
0 Ozzooo
(!)
0121-3
Selection Guide
7C245A15 7C245A18 7C245A25 7C245A35
Maximum Setup Time (ns) 15 18 25 35
Maximum Clock to Output (ns) 10 12 15 20
L Commercial 60
338
~ CY7C245A
~~~NDUcrOR =====================================================================
Product Characteristics Maximum Ratings
The CY7C245A is a high performance 2048 word by 8 bit (Above which the useful life may be impaired. For user
electrically Programmable Read Only Memory packaged guidelines, not tested.)
in a slim 300 mil plastic or hermetic DIP. The ceramic Storage Temperature ............... -65C to + 150C
package may be equipped with an erasure window; when Ambient Temperature with
exposed to UV light the PROM is erased and can then be Power Applied .................... - 55C to + 125C
reprogrammed. The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent program-
(Pin 24 to Pin 12) .................... -0.5Vto +7.0V
ming algorithms.
The CY7C245A replaces bipolar devices and offers the ad- in High Z State ...................... - 0.5V to + 7.0V
vantages of lower power, reprogrammability, superior per-
formance and high programming yield. The EPROM cell DC Input Voltage ................... - 3.0V to + 7.0V
requires only 12.5V for the supervoltage and low current DC Program Voltage (Pins 7, 18,20) ............. 13.0V
requirements allow for gang programming. The EPROM UV Erasure .......................... 7258 Wsec/cm2
cells allow for each memory location to be tested 100%, as
Static Discharge Voltage ..................... > 200 1V
each location is written into, erased, and repeatedly exer-
cized prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after customer pro- Latchup Current .......................... > 200 rnA
gramming the product will meet AC specification limits.
Operating Range
The CY7C245A has an asynchronous initialize function
(INIT). This function acts as a 2049th 8-bit word loaded Ambient
Range Vee
into the on-chip register. It is user programmable with any Temperature
desired word or may be used as a PRESET or CLEAR Commercial OC to + 70C 5V 1O%
function on the outputs. Military [41 - 55C to + 125C 5V 1O%
7C245A-15, 18 7C245A-25,35 7C245AL-35
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 2.4 2.4 V
VOH
VIN = VIH or VIL
Vee = Min.,loL = 16 rnA
VOL Output LOW Voltage 0.4 0.4 0.4 V
VIN = VIH or VIL
Input HIGH Level Guaranteed Input Lo~ical HIGH

VIH 2.0 Vee 2.0 Vee 2.0 Vee V
Voltage for All Inputs 11
Input LOW Level Guaranteed Input Lo~cal LOW 0.8 0.8 0.8 V
VIL Voltage for All Inputs 11
hx Input Leakage Current GND ::;; VIN ::;; Vee -10 +10 -10 +10 -10 +10 J-LA
Input Clamp Diode
VeD Note 5 Note 5
Voltage
Output Leakage Current GND::;; VO::;; V~e -40 +40 -40 +40 -40 +40
loz Output Disabled[3 J-LA
los Vee = Max., VOUT = 0.ov[21 -20 -90 -20 -90 -20 -90 rnA
Current

GND ::;; VIN ::;; Vee ICommercial 120 90 60
rnA
Vee = Max. IMilitary 120
Capacitance [6]
pF
COUT
Notes:
1. These are absolute voltages with respect to device ground pin and 4. TA is the "instant on" case temperature.
include all overshoots due to system and/or tester noise. Do not at- 5. The eMOS process does not provide a clamp diode. However, the
tempt to test these values without suitable equipment (see Notes on eY7e24SA is insensitive to - 3V dc input levels and -:- SV under-
Testing). shoot pulses ofless than 10 ns (measured at 50% point).
3. For devices using the synchronous enable, the device must be clocked 7. See the last page of this specification for Group A subgroup testing
after applying these voltages to perform this measurement. information.
3-39
~ CY7C245A
~~~NDUcrOR ==================================================================~
Switching Characteristics Over Operating Range[S]
7C245A15 7C245A18 7C245A25 7C245A35
tSA Address Setup to Clock HIGH 15 18 25 35 ns
tHA Address Hold from Clock HIGH 0 0 0 0 ns
teo Clock HIGH to Valid Output 10 12 12 15 ns
tpwc Clock Pulse Width 10 12 15 20 ns
tSEs Es Setup to Clock HIGH 10 10 12 15 ns
tHES Es Hold from Clock HIGH 5 5 5 5 ns
tOl Delay from INIT to Valid Output 15 20 20 20 ns
tRI INIT Recovery to Clock HIGH 10 15 15 20 ns
tpwI INIT Pulse Width 10 15 15 20 ns
Valid Output from
tcos 15 15 15 20 ns
Clock HIGH[I]
tHzC Inactive Output from Clock HIGH[I, 3] 15 15 15 20 ns
tOOE Valid Output from E LOW[2] 12 15 15 20 ns
tHzE EHIGH[2,3] 15 15 15 20 ns
Notes:
1. Applies only when the synchronous (Es) function is used. 4. Tests are performed with rise and fall times of 5 ns or less.
2. Applies only when the asynchronous (E) function is used. 5. See Figure la for all switching characteristics except tHZ.
3. Transition is measured at steady state High level - 500 mV or steady 6. See Figure 1b for tHZ.
state Low level + 500 mV on the output from the 1.5V level on the ,. All device test loads should be located within 2" of device outputs.
input with loads shown in Figure lb. S. See the last page ofthis specification for Group A subgroup testing
information.
AC Test Loads and Waveforms[4, 5, 6, 7]

R1 250 n R1 250 n ALL INPUT PULSES
5 V O-----J'I.,..,...--, 5 v O----J'IN'It.....,
3.0 V - - - - - . i.....---'"'""!'!l.
OUTPUTo--.......- - - f OUTPUT o--_----i
r
R2 6pF R2
50PF GND
I
16712 167H
.;;5 ns .. 5 ns
INCLUDING INCLUDING
JIG AND _JIGAND _
-= SCOPE -= - SCOPE -
0121-5
0121-4 Figure 2
Figure 1a Figure 1b
Equivalent to:
THEVENIN EQUIVALENT
100n
OUTPUT~2.0V 0121-6
The CY7C245A is a CMOS electrically Programmable (00-07) to be in the OFF or high impedance state. If the
Read Only Memory organized as 2048 words x 8-bits and asynchronous enable (E) is being used, the outputs will
is a pin-for-pin replacement for bipolar TTL fusible link come up in the OFF or high impedance state only if the
PROMs. The CY7C245A incorporates aD-type, master- enable (E) input is at a HIGH logic level. Data is read by
slave register on chip, reducing the cost and size of pipe- applying the memory location to the address inputs
lined microprogrammed systems and applications where (Ao-AlO) and a logic LOW to the enable input. The stored
accessed PROM data is stored temporarily in a register. data is accessed and loaded into the master flip-flops ofthe
Additional flexibility is provided with a programmable data register during the address set-up time. At the next
synchronous (ES) or asynchronous (E) output enable and LOW-to-HIGH transition of the clock (CP), data is trans-
asynchronous initialization (INIT). ferred to the slave flip-flops, which drive the output buff-
Upon power-up the state of the outputs will depend on the ers, and the accessed data will appear at the outputs
programmed state of the enable function (Es or E). If the (00-0 ,).
synchronous enable (Es) has been programmed, the regis- If the asynchronous enable (E) is being used, the outputs
ter will be in the set condition causing the outputs may be disabled at any time by switching the enable to a
3-40
logic HIGH, and may be returned to the active state by The CY7C245A has an asynchronous initialize input
switching the enable to a logic LOW. (INI~). The initialize function is useful during power-up
If.the synchronous enable (Es) is being used, the outputs and time-out sequences and can facilitate implementation
wIll. ~o to the OFF or high impedance state upon the next of other sophisticated functions such as a built-in "jump
PO~ltlve clock edge after the synchronous enable input is
start" address. When activated the initialize control input
causes the contents of a user programmed 2049th 8-bit
sWitched to a HIGH level. If the synchronous enable pin is
switched to a logic LOW, the subsequent positive clock word to be loaded into the on-chip register. Each bit is 3
edge will return the output to the active state. Following a programmable and the initialize function can be used to
positive clock edge, the address and synchronous enable load any desired combination of" 1"s and "O"s into the
inputs are free to change since no change in the output will register. In the unprogrammed state, activating INIT will
occur until the next low to high transition ofthe clock. generate a register CLEAR (all outputs LOW). If all the
This unique feature allows the CY7C245A decoders and bits of the initialize word are programmed, activating INIT
sense amplifiers to access the next location while previously performs a register PRESET (all outputs HIGH).
addressed data remains stable on the outputs. Applying a LOW to the INIT input causes an immediate
System timing is simplified in that the on-chip edge trig- load of the programmed initialize word into the master and
gered register allows the PROM clock to be derived direct- slave flip-flops of the register, independent of all other in-
ly from the system clock without introducing race condi- puts, including the clock (CP). The initialize data will ap-
tions. The on-chip register timing requirements are similar pear at the device outputs after the outputs are enabled by
to those of discrete registers available in the market. bringing the asynchronous enable (E) LOW.
Switching Waveforms
AO-AID -----------------------------------:r----,~~,.----_r----~~~~~~ctr_--------------------
CP
0121-7
Notes on Testing
Inc~mi.ng test procedure~ on these devices should be carefully planned, 3. Do not attempt to perform threshold tests under AC conditions.
takmg mto account the hIgh performance and output drive capabilities of Lar~e amplitude: fast ground current transients normally occur as the
the parts. The following notes may be useful. deVIce outputs dIscharge the load capacitances. These transients flow-
mended, incl~ding a 0.1 J-LF or larger capacitor and a 0.01 J-LF or able input noise immunity.
smaller capacItor placed as close to the device terminals as possible. 4. Output levels are measured at 1.5V reference levels.
Inadequate d~coupling may result in large variations of power supply 5. Transition is measured at steady state HIGH level - 500 m V or
voltage, creatmg erroneous function or transient performance failures. steady state LOW level + 500 mV on the output from the l.5V level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure I h.
3-41

VS. SUPPLY VOLTAGE n. AMBIENT TEMPERATURE VS. Vee
1.8 1.2,..----........,r--------.., III
1.6
:I
j:
1.4 S 1.4
11
0
III
1.2
/ 11
1.1 t - - - - - - - i - - - - - - - - i
S
e
o
1.2
~
/ "
N
::::i
<
:I 1.0
!S
~
~
a: 1.0
............... r---
i
0.8
/ ~
::::i
~ 0.8
0.8
V TA - 26'C
t-MAX. 0.80 ......______'--_ _ _ _---'
a:
i 0.6
TA j25'C
4.0 4.6 6.0 6.6 8.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ('C) SUPPL Y VOLTAGE (V)

n. TEMPERATURE SUPPLY VOLTAGE
VS. n. TEMPERATURE
~ 1.8 r----........,r--------, 1.2 1.6
~
~ ~-----II---------1 III ~
1.4 :I
~ 1.0 ~ Do
1.4
~
:::I
o Do I-
e :::I III
---
1.2 t-------'1i-------,~~ l- en
"-
1.2
~ ll! 0
III
0 0.8
9 N
-
III
N ::::i
CJ ::::i <
:I
1.0
o
III
< a:
:I
N
::::i 0.8 t - - - - - - - ' 1 i - - - - - - - - t
a:
0
0.6 i 0.8
z
~
a:
0.6 '"-_ _ _--"i...-_ _ _ _ TA i 2S'C
i ~
0.4 0.6
-66 25 125 4.0 4.5 5.0 5.5 6.0 -55 25 126
AMBIENT TEMPERATURE ('C) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ('C)
VS. VOLTAGE VS. OUTPUT LOADING VS. OUTPUT VOLTAGE
60 30.0 175
C( ,,-
!
I-
Z
50
~
25.0
/
i
~
150
125
."",.,.
.---
III
a: 40 ! 20.0 III
a: fI"
"
a: /
:::I
CJ
III 30
~ $ 15.0
< / a:
:::I
CJ
100
1/
'" ."
CJ
a:
:::I !:i /rr lie:
z
iii
75
Vee -5.0V
~
I-
20 ~ 10.0
V TA - 25'C ~ 50 / TA - 25'C
:::I
Do
I- 10 5.0
,J Vee - 4.5 V
S /
~
0 25
:::I
0
o
o 1.0 2.0 3.0 4.0
0.0 /
o 200 400 600 800 1000
oV
0.0 1.0 2.0 3.0 4.0
0121-9
3-42
~ CY7C245A
~~~~UcrOR==================================================================
Erasure Characteristics Device Programming
Wavelengths of light less than 4000 Angstroms begin to OVERVIEW:
erase the 7C245A. For this reason, an opaque label should
be placed over the window if the PROM is exposed to There are three independent programmable functions con-
sunlight or fluorescent lighting for extended periods of tained in the 7C245A CMOS 2K x 8 Registered PROM;
the 2K x 8 array, the initial byte, and the synchronous
time.
The recommended dose for erasure is ultraviolet light with
a wavelength of2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm2. For an ultra-
enable bit. All of the programming elements are
"EPROM" cells, and are in an erased state when the de-
vice is shipped. This erased state manifests itself differently
III
in each case. The erased state for ENABLE bit is the
violet lamp with a 12 m W/ cm2 power rating the exposure "ASYNCHRONOUS ENABLE" mode. The erased state
time would be approximately 30-35 minutes. The 7C245A for the "INITIAL BYTE" is all "O's" or "LOW". The
needs to be within 1 inch of the lamp during erasure. Per- "INITIAL BYTE" may be accessed operationally thru the
manent damage may result if the PROM is exposed to high use of the initialize function.
intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.

Table 1

Table 2
tpp Programming Pulse Width 200 10,000 IJ.s
tAS Address Setup Time 1.0 IJ.s
tos Data Setup Time 1.0 IJ.s
tAH Address Hold Time 1.0 IJ.s
tOH Data Hold Time 1.0 IJ.s
tR, tp[3] Vpp Rise and Fall Time 1.0 IJ.s
tvo Delay to Verify 1.0 IJ.s
tvp Verify Pulse Width 2.0 IJ.s
tov Verify Data Valid 1.0 p;s
toz Verify HIGH to High Z 1.0 IJ.s
Notes:
1. vccp must be applied prior to Vpp.
3-43
~~ =======================C=Y=7=C=2=45=A=
Mode Selection
Table 3
Pin Functionlt]
Mode
Read or Output Disable A3 CP E/Es INIT Ao
Outputs
Qther A3 PGM VFY Vpp Au (9-11,13-17)
Pin (5) (18) (19) 20 (8)
Read[2,3] X X VIL VIH X Data Out
Output Disable[5] X X VIH VIH X HighZ
Program [4] X VILP VIHP Vpp X Data In
Program Verify [4] X VIHP VILP Vpp X Data Out
Program Inhibit[4] X VIHP VIHP Vpp X HighZ
Intelligent Program[4] X VILP VIHP Vpp X Data In
Program Synch Enable[4] VIHP VILP VIHP Vpp Vpp HighZ
Program Initial Byte4] VILP VILP VIHP Vpp Vpp Data In
Notes:
1. X = Don't care put not to exceed Vpp. 4. During programming and verification, all unspecified pins to be at
2. During read operation, the output latches are loaded on a "0" to "I" VILP.
transition ofCP. 5. If the registered device is being operated in Ii synchronous mode, pin
3. If the registered device is being operated in a synchronous mode, pin 19 must be HIGH prior to the "0" to "I" transition on CP (18) that
19 must be LOW prior to the "0" to "I" transition on CP (18) that loads the register.
loads the register.
The CY7C245A programming algorithm allows signifi-
cantly faster programming than the "worst case" specifica-
tion of 10 msec.
A7 Vee Typical programming time for a byte is less than 2.5 msec.
A6
As
As Ag
A4 A10 ance. A flowchart ofthe algorithm is shown in Figure 4.
A3 VPP(lNIT)
A2 VFY (E/ES) The algorithm utilizes two different pulse types: initial and
overprogram. The duration of the PGM pulse (tpp) is 0.2
A, PGM (CP)
msec which will then be followed by a longer overprogram
Ao 07 pulse of 4 (0.1) (X) msec. X is an iteration counter and is
Do 06 equal to the NUMBER of the initial 0.2 msec pulses ap-
D, Ds plied before verification occurs. Up to ten 0.2 msec pulses
D2 D4 are provided before the overprogram pulse is applied.
VIiIi The entire sequence of program pulses and byte verifica-
0121-10 tions is performed at Vccp = 5.0V. When all bytes have
Figure 3. Programming Pinouts been programmed all bytes should be compared (Read
mode) to original data with V cc = 5.0V.
BitMap Data
0 0 DATA

2047 7FF DATA
2048 800 INITBYTE
Control Byte
00 Asynchronous output enable (default state)
3-44
~ CY7C245A
~~~NDUcroR =====================================================================
II
0121-8
3-45
~ CY7C245A
~Jr;~~ucr~~================================================================
Programming Sequence 2K x 8 Array
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The that fails to verify causes the device to be rejected.
with the output lines in a high impedance state; see Figures gram pulse width should be 200 1-'-s. Each location is ulti-
one byte of data. Repeat this for each location to be pro- up to and including 10 times. When the location verifies,
grammed. one additional programming pulse should be applied of du-
If the brute force programming method is used, the pulse ration 4X the sum of the previous programming pulses
width of the program pulse should be 10 ms, and each before advancing to the next address to repeat the process.
PROGRAM
14-_ _ _ _ PRoGRAM------<+----VERIFy---~--O-TH__\ER : t = B Y T E S
V1HP--- ---~I_-----------+--------~.I,.-.......;
ADDRESS ADDRESS STABLE
V1LP - - -
V1HP - - -
DATA
VILP - - -
------0(
Vpp - - -
PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -
VILP - - -
VILP - - -
VIHP - - -
VILP - - -
0121-11
~------------------PROGRAM---------------------~
VIHP - - -
A3
VILP - - -
Vpp - - -
Ao
VIHP - - -
VILP - - -
VIHP - - -
DATA ---~----I
VILP - - -
~-----------tAH-----------~
Vpp---
PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -
VILP - - -
VIHP - - -
VILP - - -
0121-12
3-46
~RESS
.nEMICONDUcrOR =======================================================================
CY7C245A
Programming the Initialization Byte Programming Synchronous Enable

The CY7C245A registered PROM has a 2049th byte of The CY7C245A provides for both a synchronous and asyn-
data used to initialize the value of the register. This initial chronous enable function. The device is delivered in an
byte is value "0" when the part is received. If the user asynchronous mode of operation and only requires that the
desires to have a value other than "0" for register initializa- user alter the device if synchronous operation is required.
tion, this must be programmed into the 2049th byte. This The determination of the option is accomplished thru the
byte is programmed in a similar manner to the 2048 nor- use of an EPROM cell which is programmed only if syn-
mal bytes in the array except for two considerations. First, chronous operation is required. As with the INITIAL byte, ~
since all of the normal addresses of the part are used up, a this function is addressed thru the use of a supervoltage. ~
super voltage will be used to create additional effective ad- Per Table 3, Vpp is applied to pin 8 (Ao) with pin 5 (A3) at
dresses. The actual address has Vpp on Ao pin 8, and VILP VIHP. This addresses the cell that programs synchronous
on A3, pin 5, per Table 3. The programming and verifica- enable. Programming the cell is accomplished with a 10 ms
tion of "INITIAL BYTE" is accomplished operationally program pulse on pin 18 (PGM) but does not require any
by performing an initialize function. data as there is no choice as to how synchronous enable
may be programmed, only if it is to be programmed.
VIHP - - -
VILP - - -
VIHP - - -
PGM
VILP - - -
t----tAs ---i4------tpP-----~
VIHP - - -
ffi
VILP - - -
Vpp---
AO
VIHP - - -
VILP - - -
Vpp---
PROGRAMMING
VOLTAGE (PIN 20)
VIHP - - -
VILP - - -
0121-13
Figure 7. Program Synchronous Enable
Verification of Synchronous Enable Blank Check

Verification of the synchronous enable function is accom- A virgin device contains all zeros. To blank check this
plished operationally. Power the device for read operation PROM, use the verify mode to read locations 0 thru 2047.
with pin 20 at VIH, cause clock pin 18 to transition from A device is considered virgin if all locations are "O's" when
VIL to VIH. The output should be in a High Z state. Take addressed.
pin 20, ENABLE, to VIL. The outputs should remain in a
high Z state. Transition the clock from VIL to VIH, the
outputs should now contain the data that is present. Again
set pin 19 to VIH. The output should remain driven. Clock-
ing pin 18 once more from VIL to VIH should place the
outputs again in a High Z state.
3-47
~ CY7C245A
~~~NDUcrOR================================================================
Speed (ns) Icc Ordering Package Operating Speed (ns)Icc Ordering Package Operating
tSA teo mA Code Type Range
tSA teo mA Code Type Range
15 10 120 CY7C245A-15PC P13 Commercial 35 20 60 CY7C245AL-35PC P13 Commercial

CY7C245A-15WC W14 CY7C245AL-35WC W14
18 12 120 CY7C245A-18PC P13 Commercial 90 CY7C245A-35PC P13
CY7C245A-18WC W14 CY7C245A-358C 813
25 15 90 CY7C245A-25PC P13 Commercial CY7C245A-35WC W14
CY7C245A-258C 813 CY7C245A-35LC L64
CY7C245A-25WC W14 120 CY7C245A-35WMB W14 Military
CY7C245A-25LC L64 CY7C245A-35LMB L64
120 CY7C245A-250MB 014 Military CY7C245A-350MB 014
CY7C245A-25QMB Q64 CY7C245A-35QMB Q64
CY7C245A-25WMB W14
CY7C245A-25LMB L64
3-48
c;~ CY7C245A
~ ~~~UcrOR============================================================
DC Characteristics

VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
ICC 1,2,3
tSA 7,8,9,10,11
tHA 7,8,9,10,11
teo 7,8,9,10,11
3-49
CY7C251
CY7C254
CYPRESS
SEMICONDUCTOR 16,384 X 8 PROM
Power Switched and
Features
Reprogrananaable
CMOS for optimum Direct replacement for bipolar The CY7C251 and CY7C254 are plug-
speed/power PROMs in replacements for bipolar devices and
Windowed for reprogrammability Capable of withstanding > 2001V offer the advantages oflower power,
static discharge superior performance and program-
High speed ming yield. The EPROM cell requires
- 45 ns (commercial) Product Characteristics only 12.5V for the supervoltage and
- 55 ns (military) low current requirements allow for
Low power performance 16,384 word by 8 bit gang programming. The EPROM cells
- 550 mW (commercial) CMOS PROMs. When deselected, the allow for each memory location to be
- 660 mW (military) 7C251 automatically powers down into tested 100%, as each location is written
a low power stand-by mode. It is pack- into, erased, and repeatedly exercised
Super low standby power prior to encapsulation. Each PROM is
(7C251) aged in the 300 mil wide package. The
7C254 is packaged in 600 mil wide also tested for AC performance to
- Less than 165 mW when guarantee that after customer program-
deselected packages and does not power down
when deselected. The 7C251 and ming the product will meet DC and
- Fast access: 50 ns AC specification limits.
7C254 reprogrammable CERDIP
EPROM technology 100% packages are equipped with an erasure Reading is accomplished by placing all
programmable window; when exposed to UV light, four chip selects in their active states.
Slim 300 mil or standard 600 these PROMs are erased and can then The contents of the memory location
mil packaging available be reprogrammed. The memory cells addressed by the address lines (AQ-
utilize proven EPROM floating gate A13) will become available on the out-
5V 10% Vcc, commercial and technology and byte-wide intelligent
military put lines (00-07).
programming algorithms.
TI'L compatible I/O
~!! ~!! ~~! t~~ tl.2j ~:1: !~:

As :~! m A'2
Os All A4 I1 n! A
'3
o.
A'2
AU
A3
A2 ..
7' ~ ~r
~~!
cs,
CS 2
0
B,
B2 A, I1 .,. CS 3
03 Ao 10' ~H CS 4
NC ]I! ~! NC
02 00
00 12' ~~~ 07
0,
0_.0_ _ _ _. 0_' ....
0, :14: !IS: :16: :'7: :'8: :19: :20:
00 0086-2 0086-11
Top View
0088-1
Selection Guide
7C251-45 7C251-55 7C251-65
7C254-45 7C254-55 7C254-65
Standby Current (rnA) Commercial 30 30 30
(7C251 only) Military 35 35
3-50
CY7C251
WA .
~NDUcroR
Maximum Ratings
=====================================================================
CY7C254
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... > 2OO1V
Ambient Temperature with (per MIL-STD-883, Method 3015)
Power Applied .................... - 55C to + 125C Latchup Current .......................... > 200 mA
Supply Voltage to Ground Potential UV Exposure ........................ 7258 Wsec/cm2
(Pin 28 to Pin 14) .................... -0.5V to + 7.0V
DC Voltage Applied to Outputs Operating Range
in High Z State ...................... - O. 5V to + 7.0V Range
Ambient
Vee
Temperature
Commercial OCto +70"C 5V 10%
DC Program Voltage (Pin 22) ................... 13.5V
Military[S] - 55C to + 125C 5V 10%

7C251-45 7C251-55,65
Parameters Description Test Conditions 7C254-45 7C25455,65 Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 16.0 rnA 0.5 0.5 V
VIL Input LOW Level[1] 0.8 0.8 V
IIX Input Current GND ~ VIN s:: Vee -10 +10 -10 +10 J.LA
Input Diode Clamp
VeD Note 2 Note 2
Voltage
loz Output Leakage Current VOL s:: VOUT s:: VOH, Output Disabled -40 +40 -40 +40 J.LA
Output Short
los Circuit Current[3] Vee = Max., VOUT = GND -20 -90 -20 -90 rnA
IcC Power Supply Vee = Max., VIN = 2.0V Commercial 100 100 rnA
Current lOUT = OmA Military 120 rnA
ISB Standby Supply Vee = Max., CS ~ VIH Commercial 30 30 rnA

Current (7C251) lOUT = OmA Military 35 rnA
Capacitance [4]
CIN Input Capacitance TA = 25C,f = 1 MHz 10
Vee = 5.0V pF
CoUT Output Capacitance 10
Notes:
1. These are absolute voltages with respect to device ground pin and 3. For test purposes, not more than one output at a time should be
include all overshoots due to system and/or tester noise. Do not ai- shorted. Short circuit test duration should not exceed 30 seconds.
tempt to test these values without suitable equipment. 4. Tested initially and after any design or process changes that may
2. The CMOS process does not provide a clamp diode. However, the affect these parameters.
CY7C2S 1 and CY7C2S4 are insensitive to - 3V dc input levels and S. TA is the "instant on" case temperature.
- SV undershoot pulses ofless than 10 ns (measured at SO% point). 6. See the last page of this specification for Group A subgroup testing
information.
351
CY7C251
(in
.. CY7C254
~UcrOR==================================================================
Switching Characteristics Over the Operating Range[6, 7]
7C25145 7C25155 7C25165
Parameters Description 7C254-45 7C25455 7C25465 Units
tAA Address to Output Valid 45 55 65 ns
tHZCSt Chip Select Inactive to High Z[8, 9] 25 30 35 ns
tHZcs2 Chip Select Inactive to High Z (7C251, 'CSt Only)[S] 50 60 70 ns
tACSt Chip Select Active to Output Valid[9] 25 30 35 ns
tAcs2 Chip Select Active to Output Valid (7C251, 'CSt Only) 50 60 70 ns
tpu Chip Select Active to Power Up (7C251) 0 0 0 ns
tpD Chip Select Inactive to Power Down (7C251) 50 60 70 ns
INCLUDING
H 5VF1
OUT:U~
I
R1
30 f
P
' 235.c.
R2
159.c.
OUTPUT
INCLUDING I
R1235.c.
5 f
P
R2
159.c.
3.0 V ------:::J:~~--~
GND--....;;;;r
~ &na ~ 5na

SCOPE =- - SCOPE =- - Figure 2. Input Pulses
0086-4
Figure 18 Figure Ib

95.c.
OUTPUT ~ 2.02 V 0086-5
SUPPLY
Vec
_ t PD .:1
'-.50%
- r- tpu Note: Power Down controlled by CSh only.
1fSO%
CURRENT I
Ao-Au
ADDRESS
I(
CS 3
cs 1CS 2 CS 4
:j~"'----------~~~N~0~TE~8~
___-_f-"'F-- NOTE 8 ________~~~~r------------
--tM I-tHZCS I - - tACS
0 0- 07 _ _ _ _ ....:X~X~~ ~
0086-7
Notes:
7. Test conditions assUme signal transition times of 5 ris or less, timing S. tHZCS is tested with load shown in Figure 1h. Transition is measured
reference levels of 1.5V, output loading ofthe specified Iou'IOH and at steady state High level - 500 mV or steady state Low level + 500
loads shown in Figure la, 1h. mV on the output from the 1.5V level on the input.
9. tHzCS\ and tACS\ refers to 7C254 (all chip selects); and 7C251 CCS2,
CS3 and CS4 only).
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm2. For an ultra-
erase the 7C251 and 7C254 in the windowed package. For violet lamp with a 12 mW/cm2 power rating the exposure
this reason, an opaque label should be placed over the win- time would be approximately 45 minutes. The 7C251 or
dow if the PROM is exposed to sunlight or fluorescent 7C254 needs to be within 1 inch of the lamp during era-
lighting for extended periods of time. sure. Permanent damage may result ifthe PROM is ex-
The recommended dose of ultraviolet light for erasure is a posed to high intensity UV light for an extended period of
wavelength of 2537 Angstroms for a minimum dose (UV time. 7258WXsec/cm2 is the recommended maximum
dosage.
3-52
CY7C251
~ CY7C254
~~~NDUcrOR~================================================================
Programming Algorithm
Device Programming
The CY7C251 and CY7C254 all program identically. They Programming is accomplished with an intelligent algo-
utilize an intelligent programming algorithm to assure con- rithm. The sequence of operations is to enter the program-
sistent programming quality. These 128K PROMS use a ming mode by placing Vpp on pin 22. This should be done
single ended memory cell design. In an unprogrammed after a minimum delay from power up, and be removed
prior to power down by the same delay (see the timing
-=-
state, the memory contains all "O"s. During programming,
a "1" on a data-in pin causes the addressed location to be diagram and AC specifications for details). Once in this
programmed, and a "0" causes the location to remain un- mode, programming is accomplished by addressing a loca-
programmed. tion, placing the data to be programmed into a location on
the data pins, and clocking the PGM signal from VIHP to .:.
Programming Pinout VILP and back to VIHP with a pulse width of 200 p.s. The
data is removed from the data pins and the content of the
The Programming Pinout of all three devices are shown in location is then verified by taking the VFY signal from
Figure 3 below, and are identical. The programming mode VIHP to VILP, comparing the output with the desired data
is entered by raising the pin 22 to Vpp. The addressed and then returning VFY to VIHp. If the contents are cor-
location is programmed and verified with the application of rect a second overprogram pulse of 4 times the original
a PGM and VFY pulse applied to pins 23 and 21 respec- 200'fJ-s is delivered with the data to be programmed again
tively. Entering and exiting the programming mode should on the data pins. If the data is not correct, a second 200 fJ-s
be done with care. Proper sequencing as described in the pulse is applied to PGM with the data to be programme:ct
dialog on the programming algorithm and shown in the on the data pins. The compare and overprogram operatIOn
timing diagram and programming flow chart must be im- is repeated with an overprogram pulse width 4 times the
plemented. sum of the initial program pulses. This operation is contin-
ued until the location is programmed or 10 initial program
Programming And Blankcheck pulses have been attempted. If on the 10th attempt, t~e
Blankcheck location fails to verify, an overprograrn pulse of 8 ms 1S
applied, and the content of the location is once more veri-
Blankcheck is accomplished by performing a verify cycle fied. If the location still fails to verify, the device is reject-
(VPY toggles on each address), sequencing through all ed. Once a location verifies successfully, the address is ad-
memory address locations, where all the data read will be vanced to the next location, and the process is repeated
"O"s. until all locations are programmed. After all locations are
programmed, they should be verified at Vccp = 5.0V.
A9 28 vee
A8 27 Al0
A7 26 All
A6 25 A12
A5 A13
A4 PGM
A3 7 VPP
A2 8 21 VFY
Al 9 NA
AO 10 07
DO 11 06
01 12 05
02 13 04
VSS 14 03
0086-8
Figure 3. Programming Pinout (DIP Package)
3-53
CY7C251
5'A~NDUcrOR=======================================================================
.
Operating Modes Programming Sequence

CY7C254
Read The flowchart in Figure 4 is a detailed description of the

intelligent programming cycle used to program the devices
Read is the normal operating mode for a programmed de- covered in this specification. Of particular importance are
vice. In this mode, all signals are normal TTL levels. The the areas of power sequencing used to enter and exit the
PROM is addressed with a 14 bit field, 4 chip select bits, programming operation. This flowchart combined with the
and the contents of the addressed location appear on the timing diagrams AC and DC parameters accurately de-
data out pins. scribe this complete operation.
Program, Program Inhibit, Program Verify The timing diagram in Figure 5 contains all of the timing
These modes are entered by placing a high voltage Vpp on information necessary for describing the relations required
pin 22. Pin 23 becomes an active LOW program (PGM) for programming the devices covered in this specification.
signal and pin 21 becomes an active LOW verify (VFY) Some of the information pertains to each cycle of program-
signal. Pins 21 and 23 should never be active LOW at the ming as specified in Figure 4, and some pertains only to
same time. The PROGRAM mode exists when PGM is entry and exit from the programming mode of operation.
LOW, and VFY is HIGH. The VERIFY mode exists when Tp, TpD and THP refer to the entry and exit from the
the reverse is true, PGM HIGH and VFY LOW and the programming mOdeyf operation. Note that this is refer-
PROGRAM INHIBIT mode is entered with both PGM enced to PGM and FYoperations.
and VFY HIGH. PROGRAM INHIBIT is specifically
provided to allow data to be placed on and removed from TDS, TAS, TAH and TDH refer to the required setup and
hold times for the address and data for PGM and VFY
the data pins without conflict.
operations. These parameters must be adhered to, in all
Blankcheck operations, including Vpy. This precludes the option then
of verifying the device by holding the Vpy signal LOW,
Blankcheck mode is identical to PROGRAM VERIFY
and sequencing the addresses.
and is entered in the same manner as described above.
Table 1. Operating Modes

Pin Function
Read or Output Disable CS4 CS3 CS2 CSt Outputs
Mode
Other N/A VFY Vpp PGM (11-13,15-19)
Pin Number (20) (21) (22) (23)
Read VIL VIH VIL VIL Data Out
Output Disable[1] X X X VIH HighZ
Output Disable[1] X X VIH X HighZ
Output Disable[1] X VIL X X HighZ
Output Disabldl] VIH X X X HighZ
Program X VIHP Vpp VILP Data In
Program Verify X VILP Vpp VIHP Data Out
Program Inhibit X VIHP Vpp VIHP HighZ
Blank Check X VILP Vpp VIHP Data Out
Note:
1. X = Don't care but not to exceed Vee + 5%.
3-54
CY7C251
(;n~~UcrOR=====================================================================
. CY7C254
Typical AC and DC Characteristics

NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE 1.2 vs. AMBIENT TEMPERATURE 1.2 vs. SUPPLY VOLTAGE
1.6
!oJ
r--- r--
---
~
1.4 ~
(J
1.1\--~---+------~ 1.0
...Y
Q 1.2 ./
VI
VI
!oJ
0
r---
!oJ
N V 1.01----"'k------j
0
oc(
.08
::::i
oc(
~ 1.0 ./ Q
!oJ
N
/
0:
0 ::::i
z 0.9 I------+------"'~__I
oc(
~ 0.6
0.8 ./ 0:
V" TA = 25C
0
Z
f=MAX. TA =~50C
0.6 0.8 ~----'--------' 0.4
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME OUTPUT SOURCE CURRENT TYPICAL ACCESS TIME

vs. TEMPERATURE vs. VOLTAGE CHANGE vs. OUTPUT LOADING
1.6 , . - - - - - , - - - - - - - - , 60 30.0
':(
!oJ
~
1.4 \ - - - - - - + - - - - - - _ _ 1
!.
.... 50 25.0
-..:.
~
..,.- ~
"-
Z
VI !oJ
0:
~ 0: 40 1/1 20.0
o 1.2 I----+-----~ :::I ........ /'
~
'"" "- /
0
!oJ 30 -~ 15.0
Q
!oJ
1.0 I----~"""I""'----__I
0
0: ~ /
N
::::i
:::I
0 20
...J
!oJ 10.0 /
~/
"
oc( VI Q
~ ....
0:
o 0.8 I----+-----~ :::I
10 ~ 5.0
TA =25OC
I!: Vee = 4.5V -
""
Z
0.6 ' - - - - - - ' - - - - - - - - '

:::I
0
o o 1/ I
-55 25 125 o 1.0 2.0 3.0 4.0 o 200 400 600 800 1000
AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V) CAPACITANCE (pr)
OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE
175
':(
150
!.
.... ~
z 125 ~
!oJ ;'
0:
0:
:::I 100 /
0
~
z 75 L Vee = 5.0V
TA =25OC -
iii
....
:::I
50
/
a...
....
:::I 25
/
0
If
o
o 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)
0086-12
3-55
~ CY7C251
~~~~~ucr~==============================================~C~Y~7~C~2~5~4
0086-13
3-56
CY7C251
5n .
. ~~NDUcrOR =============::::::=======================
CY7C254
VpP ______-+_~-----------------____------__-~
Vpp PIN 22 V1HP - - - - - - - t
ADDRESS VIHP-=::$:::~~~~~~~(::::j::::::l:::::t:::::::t::::::)-------
V1LP -
III
DATA VIHP-=4=====~----DAT:::ii;---I"i
VILP--t------~------......--+-....;r
_ PIN 23 VIHP--J~------------i..1
PGM V1LP -
_ry PIN 21 VIHP--J~--------------------~I
V V1LP-
0086-14
Figure 5. Programming Waveforms
Note: Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.
Table 2. DC Programming Parameters TA = 25C

Vpp Programming Voltage 12.0 13.0 V
Veep Power Supply Voltage During Programming 4.75 5.25 V
Ipp Vpp Supply Current 50 rnA
VIHP Input High Voltage During Programming 3.0 Veep V
VILP Input Low Voltage During Programming -3.0 0.4 V
VOH Output High Voltage 2.4 V
VOL Output Low Voltage 0.4 V
Table 3. AC Programming Parameters TA = 25C

tAS Address Setup Time to PGM/VFY 1.0 IJ-s
tAH Address Hold Time from PGM/VFY 1.0 IJ-s
tos Data Setup Time to PGM 1.0 IJ-s
tOH Data Hold Time PGM 1.0 IJ-s
tpp Program Pulse Width 0.2 10 ms
tR,F Vpp Rise and Fall Time 100 ns
tov Delay to Verify 1.0 IJ-s
tvo Verify to Data Out 1.0 IJ-s
tVH Data Hold Time from Verify 1.0 IJ-s
tvp Verify Pulse Width 2.0 IJ-s
toz Verify to High Z 1.0 IJ-s
top Delay to Function 1.0 IJ-s
tHP Hold from Function 1.0 IJ-s
tp Power Up/Down 20.0 ms
3-57
~ CY7C251
_r,~UcrOR ===:;;.;====================C=Y;::7;::C;::2;::5;;;;:4
Speed Ordering .Package Operating
(ns) Code Type Range
CY7C251-45WC W22
CY7C254-45WC W16
CY7C254-45PC P15
. CY7C254-45DC 016
55 CY7C251-55PC P21
CY7C251-55WC . W22
CY7C254-55WC W16
CY7C254-55PC P15
CY7C254-550C 016
CY7C251-55WMB W22 Military
CY7C251-550MB 022
CY7C254-55WMB W16
CY7C254-55DMB 016
CY7C251-65WC W22
CY7C254-65WC W16
CY7C254-65PC P15
CY7C254-650C 016
CY7C251-650MB 022
CY7C251-65LMB L55
CY7C251-65QMB Q55
CY7C254-65WMB W16
CY7C254-65LMB L55
CY7C254-65QMB Q55
CY7C254-650MB 016
3-58
CY7C251
fin CY7C254
~~NOOcrOR==============================================================
DC Characteristics

VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB[2] 1,2,3
tAA 7,8,9,10,11
tACSl [1] 7,8,9,10,11
tACS2[2] 7,8,9,10,11
Notes:
1. 7C254 and 7C251 (CS2. CS3 and CS4 only).
2. 7C251 (CSI only).
3-59
CY7C261
CY7C263/CY7C264
CYPRESS
SEMICONDUCTOR 8192 X 8 PROM
Power Switched and
Features
Reprogrammable
CMOS fol' optimum Direct replacement for bipolar The CY7C261, CY7C263 and
speed/power PROMs CY7C264 are plug-in replacements for
Windowed for reprogrammability Capable of witbstanding > 2000V bipolar devices and offer the advan-
static discharge tages oflower power, superior perform-
High speed ance and programming yield. The
- 35 ns (commercial) Product Characteristics EPROM cell requires only l2.5V for
- 45 ns (military) the supervoltage and low current re-
The CY7C261, CY7C263 and
Low power CY7C264 are high performance 8192 quirements allow for gang program-
- 550 mW (commercial) word by 8 bit CMOS PROMs. When ming. The EPROM cells allow for each
- 660 mW (military) deselected, the 7C261 automatically memory location to be tested 100%, as
powers down into a low power stand- each location is written into, erased,
Super low standby power and repeatedly exercised prior to en-
(7C261) by mode. It is packaged in the 300 mil
wide package. The 7C263 and 7C264 capsulation. Each PROM is also tested
- Less than 185 mW when for AC performance to guarantee that
deselected are packaged in 300 mil and 600 mil
wide packages respectively and do not after customer programming the prod-
- Fast access: 35 ns uct will meet DC and AC specification
power down when deselected. The re-
EPROM technology 100% programmable CERDIP packages are limits.
programmable equipped with an erasure window; Reading is accomplished by placing an
Slim 300 mil or standard 600 when exposed to UV light, these active LOW signal on CS. The contents
mil packaging available PROMs are erased and can then be re- of the memory location addressed by
programmed. The memory cells utilize the address lines (Ao-A12) will become
5V 10% VCC, commercial and proven EPROM floating gate technolo-
military available on the output lines (00-07).
gy and byte-wide intelligent program-
TTL compatible I/O ming algorithms.
0052-2
4 3 2 1 282726
0
A4 5 25 Ato
A3 6 24 ~
t A2
At
7
8
23
22
An
At2
Ao 9 21 NC
NC 10 20 07
00 "'2'3'4'5'6'7,i9 Os
~-;~~------------+---------------~
... NO U ,., .... \I)
0 o~zooo
0052-1 0052-3
Selection Guide
7Cl61-35 7Cl61-40 7Cl61-45 7Cl61-55
7Cl6335 7Cl63-40 7C263-45 7Cl63-55
7ClM-35 7Cl64-40 7Cl64-45 7Cl64-55
Standby Current (rnA) Commercial 30 30 30 30
(7C261 only) Military 30 30
3-60
CY7C261
5A .
~~NDUcrOR
Maximum Ratings
=====================================================================
CY7C263/CY7C264
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... >2oo1V
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
in High Z State ...................... -0.5V to + 7.0V Ambient
Range Vee
DC Input Voltage ................... -3.0V to +7.0V Temperature
Commercial OCto +70C 5V 1O%
DC Program Voltage
(Pin 19 DIP, Pin 23 LCC) ...................... 13.0V Military [5) - 55C to + 125C 5V 1O%

7C261-35,40 7C261-45,55
7C263-35, 40 7C263-45,55
Parameters Description Test Conditions 7C264-35, 40 7C264-45,55 Units
Min. Max. Min. Max.

VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 16.0mA 0.4 0.4 V
VIL Input LOW Level[l) 0.8 0.8 V
IIX Input Current GND ~ VIN ~ Vee -10 +10 -10 +10 /LA
Input Diode Clamp
VeD Note 2 Note 2
Voltage
loz Output Leakage Current VOL ~ VOUT ~ VOH, Output Disabled -40 +40 -40 +40 /LA
Output Short
los Circuit Current[3) Vee = Max., VOUT = GND -20 -90 -20 -90 rnA
Icc Power Supply Vee = Max., VIN = 2.0V Commercial 100 100 rnA
Current lOUT = OmA Military 120 rnA
Standby Supply Vee = Max., CS;<:: VIH Commercial 30 30 rnA
ISB
Current (7C261) lOUT = OmA Military 30 rnA
Capacitance [4]
Vee = 5.0V pF
Notes:
include all overshoots due to system and/or tester noise. Do not at- shorted. Short circuit test duration should not exceed 30 seconds.
CY7C261, CY7C263 & CY7C264 are insensitive to - 3V dc input 5. TA is the "instant on" case temperature.
levels and - 5V undershoot pulses ofless than 10 ns (measured at 6. See the last page of this specification for Group A subgroup testing
50% point). information.
3-61
CY7C261
fin ~~NDUcrOR ==========================~~~~~~~~~~~~~~~~~~==~~~=
CY7C263/CY7C264

7C26135 7C26140 7C261-45 7C26155
7C26335 7C26340 7C26345 7C26355
Parameters Description 7C264-35 7C264-40 7C264-45 7C264-55 Units

tAA Address to Output Valid 35 40 45 55 ns
tHZCSl Chip Select Inactive to High Z[S] 25 25 30 35 ns
tHZCS2 Chip Select Inactive to High Z (7C261)[S] 30 35 45 55 ns
tACSl Chip Select Active to Output Valid 25 25 30 35 ns
tACS2 Chip Select Active to Output Valid (7C261) 40 45 45 55 ns
tpu Chip Select Active to Power Up (7C261) 0 0 0 0 ns
tPD Chip Select Inactive to Power Down (7C261) 35 40 45 55 ns

R12500 R12500
5Vo---------~~~ 5Vo-------~~~
3.0 V------:~~~--~
OUTPUT 0 - - - -.......- - - -... OUTPUT 0-----.....- - - - - 4
I
GND--.....iii!i
INCLUDING
JIG AND
SCOPE
30 pF
R2
1670 INCLUDING
JIG AND
SCOPE
1 6
pF
R2
1670
s; 5n8
Figure 2. Input Pulses

s; 5n8
0052-6
0052-4
Figure 1a Figure 1b

1000
OUTPUT O---~",.. ..I>.,...----O 2.0 V 0052-5
Vee
SUPPLY
- tpD - - -
311\.50%
tpu
') 50%
CURRENT
Ao-A 12
ADDRESS
j \.
~tAA ~tAes
~~~J -~~~N~OT~E~8!...------......----=:j~~~
I-tHzes
X~_____~~- NOTE 8 ~(
__________ ...- - - - -............
0 0-07
0052-7
Notes:
7. Test conditions assume signal transition times of5 ns or less, timing S. tHzcS is tested with load shown in Figure 1h. Transition is measured
reference levels of 1.5V, output loading ofthe specified IOr/IOH and at steady state High level - 500 m V or steady state Low level + 500
loads shown in Figure la, 1h. mV on the output from the 1.5V level on the input.
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm2. For an ultra
erase the devices in the windowed package. For this reason, violet lamp with a 12 m W / cm2 power rating the exposure
an opaque label should be placed over the window if the time would be approximately 45 minutes. The 7C261 or
PROM is exposed to sunlight or fluorescent lighting for 7C263 needs to be within 1 inch of the lamp during era
extended periods of time. sure. Permanent damage may result if the PROM is ex
wavelength of 2537 Angstroms for a minimum dose (UV time. 7258WX sec/cm2 is the recommended maximum
dosage.
362
CY7C261
~FSS
WnEMICONDUcrOR ==========================================================
CY7C263/CY7C264
Device Programming loaded into an onboard register by clocking pin 21, the
latch signal, from VILP to VIHP and back to VILp. The
The CY7C261, CY7C263 & CY7C264 all program identi- lower 8 address bits are then placed on pins 8 through 1,
cally. They utilize an intelligent programming algorithm to with the least significant bit on pin 8. The upper 5 bits
assure consistent programming quality. These 64K remain in the onboard latch until a new value is loaded or
PROMS use a single ended memory cell design. In an un- power is removed from the device. All 256 bytes addressed
programmed state, the memory contains all "O"s. During by the lower 8 bits may be accessed by sequencing the

programming, a "1" on a data-in pin causes the addressed lower 8 addresses without changing the upper 5 bits or re-
location to be programmed, and a "0" causes the location latching the value in the onboard register.
to remain unprogrammed.
Blankcheck
Programming Pinout Blankcheck is accomplished by performing a verify cycle,
The Programming Pinout of all three devices are shown in sequencing through all memory address locations, where
Figure 3 below, and are identical. The programming mode all the data read will be "O"s.
is entered by raising the pin 19 to Vpp. In this mode, pin 21
becomes a latch signal, allowing the upper 5 address bits to Programming Algorithm
be latched and held in an onboard register, while the lower Programming is accomplished with an intelligent algo-
8 address bits are presented on the same pins for selecting rithm. The sequence of operations is to enter the program-
one of 256 memory bytes. The addressed location is pro- ming mode by placing Vpp on pin 19. This should be done
grammed and verified with the application of a PGM and after a minimum delay from power up, and be removed
VFY pulse applied to pins 22 and 23 respectively. Entering prior to power down by the same delay (see the timing
and exiting the programming mode should be done with diagram and AC specifications for details). Once in this
care. Proper sequencing as described in the dialog on the mode, programming is accomplished by addressing a loca-
programming algorithm and shown in the timing diagram tion as described above, placing the data to be programmed
and programming flow chart must be implemented. into a location on the data pins, and clocking the PGM
signal from VIHP to VILP and back to VIHP with a pulse
Programming And Blankcheck width of 200 ILs. The data is removed from the data pins
and the content of the location is then verified by taking
Addressing During Programming and Blankcheck the VFY signal from VIHP to VILP, comparing the output
Addressing to these devices in all modes of operation other with the desired data and then returning VFY to VIHP. If
than normal read operation is accomplished by multiplex- the contents are correct, a second overprogram pulse of 4
ing the upper 5 address bits with the lower 8. The address times the original 200 ILs is delivered with the data to be
designations for the lower 8 addressing bits is AXO through programmed again on the data pins. If the data is not cor-
AX7 and the upper 5 address bits are designated A Y8 rect, a second 200 ILs pulse is applied to PGM with the
through AYI2. This allows sufficient pins for an intelligent data to be programmed on the data pins. The compare and
programming algorithm to be implemented without the overprogram operation is repeated with an overprogram
need to switch high voltage signals during the blankcheck, pulse width 4 times the sum of the initial program pulses.
programming, and verification operation. This operation is continued until the location is pro-
Addressing while in these modes is accomplished by plac- grammed or 10 initial program pulses have been attempted.
ing the upper 5 bits of address on pins 8, 7, 6, 5, and 4 with If on the 10th attempt, the location fails to verify, an over-
the least significant bit on pin 8. These address bits are program pulse of 8 ms is applied, and the content of the
AX7 Vee
AX6 2 23 VfY
AX5 3 22 PGM
AX4/ AY12 4 21 LATCH
AX3/ AYll 5 CS
AX2/ AY10 6 19 Vpp
AX1/ AY9 7 NA
AXO/ AY8 8 017
010 9 016
011 10 015
012 11 014
Vss 12 013
0052-8
Figure 3. Programming Pinout (DIP Package)
3-63
CY7C261
5n .
.
. CY7C263/CY7C264
~NDUcrOR ==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~======~
location is once more verified. If the location still fails to Programming Sequence
verify, the device is rejected. Once a location verifies suc-
cessfully, the address is advanced to the next location, and The flowchart in Figure 4 is a detailed description of the
the process is repeated until alliocatio.ns are programmed. intelligent programming cycle used to program the devices
After all locations are programmed, they should be verified covered in this specification. Of particular importance are
at Vccp = 5.0V. the areas of power sequencing used to enter and exit the
programming operation. This flowchart combined with the
Operating Modes timing diagrams AC and DC parameters accurately de-
scribe this complete operation. Note should be taken of the
Read inner and outer addressing loops which allow 256 bytes to
Read is the normal operating mode for a programmed de- be programmed each time the onboard register containing
vice. In this mode, all signals are normal TTL levels. The the upper 5 address bits is loaded.
PROM is addressed with a 13 bit field, a chip select, (active The timing diagram in Figure 5 contains all of the timing
LOW), is applied to the CS pin, and the contents of the information necessary for describing the relations required
addressed location appear on the data out pins. for programming the devices covered in this specification.
Program, Program Inhibit, Program Verify Some of the information pertains to each cycle of program-
ming as specified in the inner loops of Figure 5, some for
These modes are entered by placing a high voltage Vpp on the outer loop where the upper address is advanced, and
pin 19, with pins 18 and 20 set to VILP. In this state, pin 21 some pertains only to entry and exit from the programming
becomes a latch signal, allowing the upper 5 address bits to mode of operation.
be latched into an onboard register, pin 22 becomes an
active LOW program (PGM) signal and pin 23 becomes an In particular, the timing sequence associated with the
active LOW verify (VFY) signal. Pins 22 and 23 should Latch signal on pin 21 and addresses AY8 through AY12
never be active LOW at the same time. The PROGRAM pertain only to the outer loop where the upper 5 (N in the
mode exists when PGM is LOW, and VFY is HIGH. The flow chart) address bits are incremented.
VERIFY mode exists when the reverse is true, PGM Tp, Tpo and THP refer to the entry and exit from the
HIGH and VFY LOW and the PROGRAM INHIBIT programming mode of operation. Note that this is refer-
mode is entered with both PGM and VFY HIGH. PRO- enced to LATCH, PGM and VFY operations.
GRAM INHIBIT is specifically provided to allow data to ToS, TAS, TAH and TOH refer to the required setup and
be placed on and removed from the data pins without con- hold times for the address and data for PGM and VFY
flict. operations. These parameters must be adhered to, in all
Blankcheck operations, including Vpy. This precludes the option then
of verifying the device by holding the Vpy signal LOW,
Blankcheck mode is identical to PROGRAM VERIFY and sequencing the addresses. .
and is entered in the same manner as described above.
Table 1. Operating Modes

Pins 4 thru 8
Pins 1 thru 3 Pins 9 thru 11 Pins 13 thru 17 Pin Pin Pin Pin Pin Pin
Mode A4-AO, AX4-AXO
A7-A5, AX7-AX5 DO thruD2 D3thruD7 18 19 20 21 22 23
AY12-AY8
Read A7thruA5 A4thruAO DOOthruD02 D03 thruD07 A12 All CS AlO A9 A8
Program AX7thruAX5 AX4thruAXO DIothru D12 DIJ thruDh
AYI2-AY8 Input Input VILP Vpp VILP LAT VILP VIHP
Program Inhibit AX7thruAX5 AX4thruAXO
AYI2..,.AY8
HighZ HighZ VILP Vpp VILP LAT VIHP VIHP
Program Verify AX7thruAX5 AX4thruAXO DOOthruD02 D03thruD07

AYI2-AY8 Output Output VILP Vpp VILP LAT VIHP VILP
Blank Check AX7thruAX5 AX4thruAXO DIothruDh DIJ thruDh

AYI2-AY8 Output Output VILP Vpp VILP LAT VIHP VILP
3-64
~ CY7C261
.~~NDUCTOR =====================C=Y=7=C=2=6=3=I=C=Y=7=C=2=6=4

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. SUPPLY VOLTAGE
1.6 1.2 .------r--------, 1.2
~
0
I.&J
N
:::i
oc(
1.4
1.2
~
V
./
-~
o
I.&J
N
~
1.1 t--~--+--------I
lDI----~~----___l
1.2
.08
r---
--- --- r--...
:::E 1.0 :::E
/
0:: 0::
0 o
z Z
0.9 t------+----~---t 0.6
0.8 ./
~ TA = 25C
f=MAX. TA=f5 0 C
0.6 0.8 ' - - - - - - ' - - - - - - - - ' 0.4
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME OUTPUT SOURCE CURRENT TYPICAL ACCESS TIME CHANGE
vs. TEMPERATURE vs. VOLTAGE vs. OUTPUT LOADING
1.6,------...,.--------, 60 30.0
I.&J
<-
,,
",
:::E 1.41-----+--------1 50 25.0
i= I-
en
Z
I.&J
./
~
0:: "iii' 20D
~ 0:: 40 c
u 1.2 1 - - - - - + - - - - - - - - 1 ::l ........ /
u
oc(
U
I.&J 30
} 15.0 /
o
I.&J
u
0:: ........ ~ /
N
:::::i
1.0 t--------::::iiII"""F'--------t ::l
0 20 ~ ..J
I.&J 10.0 /
en 0
"-
oc(
:::E
0::
o 0.8 I - - - - - - + - - - - - - _ _ _ l
I-
::l
Q.. 10 ~ 5.0
LV TA = 25C
Vcc =4.5V -
"
Z I-
0.6 ' - - - - - - ' - - - - - - - - - '

-55 25 125
::l
0
o
o 1.0 2.0 3.0 4.0
o
o
1/ 200 400 600
J
800 1000
AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V) CAPACITANCE (pF)
OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE
175
<-
,.,.- .---
150
,,
I-
z 125
I.&J
0::
0::
::l 100 / "
U
~
z 75 1/ Vcc =5.0V
TA = 25C -
iii
I- 50 /
/
::l
Q..
I-
::l 25
0
V
o
o 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE(V)
0052-11
3-65
~ CY7C261
~)r;~ucroR==================================~C~Y~7~C~26~3~/~CY~7~C~2~64
0052-9
3-66
CY7C261
(;n~~UcrOR==================================================================
. CY7C263/CY7C264
I - TP TP-
V PIN 24 Vccp
cc Vss
Vpp
-
- I-TR
T _
F l-
V 1\

Vpp PIN 19 VIHP
I--- THP -
Vss TOp I\-
TOp THP
TopJ-
V1HP
TOPJ- tTL~
TH
LATCH PIN 21
VILP
It 1i
I
I TALH I- TAH
TA:>
V1HP TALS-l l+- F- TAS"" I-- TAH -
~
#-
ADDRESS V AY8-AY12 AXO-AX7
-
1LP
I+-- Tos- TOH
PROGRAM "1" "1"- Toz
V1HP
DATA V
1LP
DATA IN ~ ...... DATA OUT ~
DON'T PROGRAM "0" "0"
I-- Tov
V1HP I -
PGM PIN 22 V
1LP
_.J 1'I~I--TOV-
1 j
Tpp
V
V PIN 23 IHP j
FY V1LP -..J
I-- Tvp-l
0052-10
Note: Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.
3-67
CY7C261
fiA~~NDUcroR =====================================================================
CY7C263/CY7C264

Vccp Power Supply Voltage
4.75 5.25 V
During Programming
Ipp V pp Supply Current 50 mA
VIHP Input High Voltage
4.75 5.25 V
During Programming
VILP Input Low Voltage
-3.0 0.4 V
During Programming

TAS Address Setup Time to PGM/VFY 1.0 p,s
TAH Address Hold Time from PGM/VFY 1.0 p,s
TDS Data Setup Time to PGM 1.0 p,s
TDH Data Hold Time PGM 1.0 p,s
Tpp Program Pulse Width 0.2 10 ms
TR,F Vpp Rise anq Fall Time 100 ns
TALS Address Setup Time to Latch 1.0 p,s
TALH Address Hold Time from Latch 1.0 p,s
TLP Latch Pulse Width 1.0 p,s
Tov Delay to Verify 1.0 p,s
Tvo Verify to Data Out 1.0 p,s
TVH Data Hold Time from Verify 1.0 p,s
Tvp Verify Pulse Width 2.0 p,s
Toz Verify to High Z 1.0 p,s
Top Delay to Function 1.0 p,s
THP Hold From Function 1.0 p,s
Tp Power Up/Down 20.0 ms
3-68
CY7C261
(;n~~NDUcrOR================================================================
CY7C263/CY7C264
Speed Ordering Package Operating Speed Ordering Package Operating
(ns) Code Type Range (ns) Code Type Range
35 CY7C26l-35PC P13 Commercial 55 CY7C26l-55PC P13 Commercial
CY7C26l-35WC W14 CY7C26l-55WC W14

CY7C263-35PC P13 CY7C263-55PC P13
CY7C263-35WC W14 CY7C263-55WC W14
CY7C264-35PC P13 CY7C264-55PC Pll
CY7C264-35WC W14 CY7C264-550C 012
CY7C264-350C 012 CY7C264-55WC W12
40 CY7C26l-40PC P13 Commercial CY7C26l-55WMB W14 Military
CY7C26l-40WC W14 CY7C261-550MB 014
CY7C263-40PC P13 CY7C26l-55LMB L64
CY7C263-40WC W14 CY7C26l-55QMB Q64
CY7C264-40PC Pll CY7C263-55WMB W14
CY7C264-400C 012 CY7C263-550MB 014
CY7C264-40WC W12 CY7C263-55LMB L64
CY7C26l-45PC P13 CY7C263-55QMB Q64
45
CY7C264-550MB 012
CY7C26l-45WC W14
CY7C264-55WMB W12
CY7C263-45PC P13
CY7C263-45WC W14
CY7C264-45PC Pll
CY7C264-450C 012
CY7C264-45WC W12
CY7C26l-45WMB W14 Military
CY7C26 I-450MB 014
CY7C26l-45LMB L64
CY7C26l-45QMB Q64
CY7C263-45WMB W14
CY7C263-450MB 014
CY7C263-45LMB L64
CY7C263-45QMB Q64
CY7C264-450MB 012
CY7C264-45WMB W12
3-69
CY7C261
(in . CYPRFSS CY7C263/CY7C264
s~oo~ucr~==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB[2] 1,2,3
tAA 7,8,9,10,11
tHZCSl l1 ] 7,8,9,10,11
tHZCS2[2] 7,8,9,10,11
tACSl [1] 7,8,9,10,11
tACS2[2] 7,8,9,10,11
Notes:
1. 7C263 and 7C264 only.
2. 7C26l only.
Document #: 38-00005-0
3-70
CY7C265
CYPRESS
SEMICONDUCTOR 64K Registered PROM
Features
CMOS for optimum speed/ Slim, 300 mil 28 pin plastic or memory location into the Pipeline Reg-
power hermetic DIP ister on each rising edge. The data will
High speed appear on the Outputs if they are en-
- 40 ns max set-up Functional Description abled. One pin on the CY7C265 is pro-
- 20 ns clock to output The CY7C265 is a 64K Registered grammed to perform either the Enable
PROM. It is organized 8192 words by or the Initialize function.
Low power 8 bits wide, and has a Pipeline Output
- 550 mW (commercial) If the asynchronous enable (E) is being
- 660 mW (military) Register. In addition, the device fea- used, the outputs may be disabled at
tures a Programmable Initialize Byte any time by switching the enable to a
On-chip edge-triggered registers which may be loaded into the Pipeline logic HIGH, and may be returned to
- Ideal for pipelined Register with the Initialize signal. The the active state by switching the enable
microprogrammed systems Programmable Initialize Byte is the to a logic LOW.
EPROM technology 8193rd byte in the PROM and its value
If the synchronous enable (Es) is being
- 100% programmable is programmed at time of use.
used, the outputs will go to the OFF or
- Reprogrammable (7C265W) Packaged in 28 pins, the PROM has 13 high impedance state upon the next
5V 10% Vee, commercial and Address Signals (Ao through AI2), 8 positive clock edge after the synchro-
military Data Out Signals (00 through 07), lVI, nous enable input is switched to a
(Enable or Initialize) and CLOCK. HIGH level. If the synchronous enable
Capable of withstanding greater pin is switched to a logic LOW, the
than 2001 V static discharge CLOCK functions as a pipeline clock,
loading the contents of the addressed subsequent positive clock edge will

A12
0, Vee
All
As
Al0
Ag ROW Ag
256 x 256 06
DECODER
Aa 1 OF 256 PROGRAMMABLE A 10
A7 ARRAY
Os All
Aa
A5--1~_"'" A12
8 BIT 04
EDGE- E/Es.i
TRIGGERED GND
REGISTER 03
A.4 GND
Aa
A2
COLUMN
DECODER
02 70
1 OF 32 6
Al
Ao
01
5
00 4
03
0126-2
4 3 2 I 1 1282726
0126-1 5
I I
25 A 10
A3
A2 6 24 All
GND 7 23 A12
ClK 8 CY7C265 22 E/Es.i
Al 9 21 GND
Ao 10 20 GND
0 0 11 19 0 7
12 13 14 15 16 17 18
I') ~ U') ...
o- 0'" z o
Q 0 0 0
<.:>
0126-3
3-71
~ CY7C265
~~~NDUcrOR =====================================================================
Selection Guide
7C26540 7C26550 7C26560
Maximum SetUp Time (ns) 40 50 60
Maximum Operating
Current (rnA)
I Military 120 100
Functional Description (Continued) Maximum Ratings

return the output to the active state. Following a positive (Above which the useful life may be impaired. For user
clock edge, the address and synchronous enable inputs are guidelines, not tested.)
free to chang~ since no change in the output will occur Storage Temperature ............... - 65C to + 150C
until the next low to high transition of the clock. This Ambient Temperature with
unique feature allows the CY7C265 decoders and sense Power Applied ............... ~ .... - 55C to + 125C
amplifiers to access the next location while previously ad
dressed data remains stable on the outputs. Supply Voltage to Ground Potential .... - 0.5V to + 7.0V
If the Ell pin is used for INIT (asynchronous) then the DC Voltage Applied to Outputs
outputs are permanently enabled. The initialize function is in High Z State ...................... -0.5V to + 7.0V
useful during power-up and time-out sequences and can DC Input Voltage ................... - 3.0V to + 7.0V
facilitate implementation of other sophisticated functions
such as a built-in "jump start" address. When activated the DC Program Voltage .......................... 13.0V
initialize control input causes the contents of a user pro- Static Discharge Voltage ..................... > 200 1V
grammed 8193rd 8-bit word to be loaded into the on-chip (per MIL-STD-883, Method 3015)
register. Each bit is programmable and the initialize func- Latchup Current .......................... > 200 mA
tion can be used to load any desired combination of" 1"s
and "O"s into the register. In the unprogrammed state, ac- UV Exposure ........................ 7258 Wsec/cm 2
tivating INIT will generate a register CLEAR (all outputs
LOW). If all the bits of the initialize word are pro- Operating Range
grammed, activating lNIT performs a register PRESET
Ambient
(all outputs HIGH). Range Vee
Temperature
Applying a LOW to the INIT input causes an immediate
load of the programmed initialize word into the pipeline Commercial OCto 70C 5V 1O%
register and onto the outputs. The INIT LOW disables Military [1] - 55C to + 125C 5V 10%
clock and must return HIGH to enable CLOCK indepen-
dent of all other inputs, including the clock.

Commercial Military
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min.,loH = -2 rnA 2.4 2.4 V
Vee"'; Min.,IOL = 12 rnA
VOL Output LOW Voltage 0.4 0.4 V
(IOL = 8 rnA for Military)
VIH Input HIGH Voltage 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 V
IIX Input Load Current GND:S;; VIN:S;; Vee 10 10 p.A
Output Leakage GND :s;; VOUT :s;; Vee
loz 40 40 p.A
los Vee = Max., VOUT = GND 90 90 rnA
Current
7C265-4O 100
Vee Operating Supply Vee = Max.
Icc Current lOUT = OmA 7C265-50 80 120 rnA
7C265-60 80 100
3-72
~ CY7C265
~~~NDUcrOR =======================================================================
Capacitance [3]
pF
COUT

Switching Characteristics Over the Operating Range[2]
7C26540 7C26550 7C26560
tAS Address Set-Up to Clock 40 50 60 ns
tHA Address Hold from Clock 0 0 0 ns
teo Clock to Output Valid 20 25 25 ns
tpw Clock Pulse Width 15 20 20 ns
tSES ES Set-Up to Clock (Sync Enable Only) 15 15 15 ns
tHES ES Hold from Clock 5 5 5 ns
tm Init to Out Valid 25 35 35 ns
tRI Init Recovery to Clock 20 25 25 ns
tpWI Init Pulse Width 25 35 35 ns
teos Output Valid from Clock (Sync. Mode) 20 25 25 ns
tHze Output Inactive from Clock (Sync. Mode) 20 25 25 ns
tOOE Output Valid from E Low (Async. Mode) 20 25 25 ns
tHZE Output Inactive from E High (Async. Mode) 20 25 25 ns
Notes:
2. See the last page of this specification for Group A subgroup testing affect these parameters.
information.

R1338!l R1338n ALL INPUT PULSES
5V 5V
(soon FOR MIL.) (soon FOR MIL.) 3.0 V
OUTPUT OUTPUT
R2 R2 GND
I
SOpF 248n 5pF 248n
(333n FOR MIL.) (333n FOR MIL.)
I'NCLUD'NG INCLUDING 0126-5
JIG AND _JIGAND _
-=SCOPE -= - SCOPE - 0126-4
143n
(2OOn F~~ ~"L)
OUTPUT O---"'.~.~ ..----O 2 11V
(z'OY FOR MIL)
0126-6
3-73
~ CY7C265
.Ts~NDUcrOR =================================
Switching Waveforms
ADDRESS
-------------------
SYNCHRONOUS ENABLE
(PROGRAMMABLE) _____-'I
t1 ~
OUTPUT ~~~~~~.Ji----'\._----
tHZE
ASYNCHRONOUS _
_ _ _I----"""\.,_____
,-
k tOOE
ENABLE
0126-7
Notes on Testing:
mended, including a 0.1 ,...F or larger capacitor and a 0.01 ,...F or able input noise immunity.
Inadequate decoupling may result in huge variations of power supply 5. Transition is measured at steady state HIGH level - 500 mV or
voltage, creating erroneous function or transient performance failures. stea:dy state LOW level + 500 mV on the output from the 1.5V level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure J b.
Device Programming Programming Algorithm

The CY7C265 utilizes an intelligent programming algo- Programming is accomplished with an intelligent algo-
rithm to assure consistent programming quality. These rithm. The sequence of operations is to enter the program-
64K PROMs use a single ended memory cell design. In an ming mode by placing 12.5V on Vpp. This should be done
unprogrammed state, the memory contains all "O"s. Dur- after a minimum delay from power up, and be removed
ing programming, a "1" on a data-in pin causes the ad- prior to power down by the same delay (see the timing
dressed location to be programmed, and a "0" causes the diagram and AC specifications for details). Once in this
location to remain unprogrammed. mode, programming is accomplished by addressing a loca-
tion as described above, placing the data to be programmed
Programming Pinout into a location on the data pins, and clocking the PGM
signal from V IHP to V ILP and back to V IHP with a pulse
The Programming Pinout is shown in Figure 3. The pro- width of 200 JLs. The data is removed from the data pins
gramming mode is entered by putting 12.5V on the Vpp and the content of the location is then verified by taking
pin. The addressed location is programmed and verified the VFY signal from VIHP to VILP, comparing the output
with the application of a PGM and VFY pulse. Entering with the desired data and then returning VFY to VIHP. If
and exiting the programming mode should be done with the contents are correct, a second overprogram pulse of 4
care. Proper sequencing as described in the dialog on the times the original 200 JLs is delivered with the data to be
programming algorithm and shown in the timing diagram programmed again on the data pins. If the data is not cor-
and programming flow chart must be implemented. rect, a second 200 JLs pulse is applied to PGM with the
data to be programmed on the data pins. The compare and
Programming and Blankcheck (Memory Bits) overprogram operation is repeated with an overprogram
Blankcheck pulse width 4 times the sum of the initial program pulses.
This operation is continued until the location is pro-
Blankcheck is accomplished by performing a verify cycle grammed or 10 initial program pulses have been attempted.
(VFY toggles on each address), sequencing through all If on the 10th attempt, the location fails to verify, an over-
memory address locations, where all the data read will be program pulse of 8 ms is applied, and the content of the
"O"s. (Refer to mode table for pin states)
3-74
~ CY7C265
~~~~UcrOR==================================================================
Programming and Blankcheck (Memory Bits) (Continued)
with a single 10 ms wide pulse in place of the intelligent
A7 vee algorithm mainly because these features are verified opera-
As A8 tionally, not with the VFY pin. Architecture programming
Ag
is implemented by applying the supervoltage to two addi-
As
tional pins during programming. In programming the
A4 A10
7C265 architecture Vpp is applied to pins 3,9 and 22.
A3 A11 Specific choice of a particular mode will depend on the
states of the other pins during programming so it is impor-
3
A2 A'2
PGM Vpp tant that the condition of the other pins be met as set forth
CLOCK GNO
in the mode table. The same considerations with respect to
power up and power down apply during architecture pro-
A, VFY
gramming as during intelligent programming. Once the su-
Ao 7 pervoltages have been established and the correct logic
00 Os states exist on the other device pins, programming may
0, Os
begin. Programming is accomplished by pulling PGM from
HIGH to LOW and then back to HIGH with a pulse width
2 4 equal to 10 ms.
Vss 03
To check whether a 7C265 has been programmed as output
0126-8 enable or initialize enable, pin 22 (Ell) should be pulled
Figure 3. 7C265 Programming Pinout LOW followed by a LOW to HIGH transition on pin 8
(CLOCK). The data read at the outputs is stored and com-
location is once more verified. If the location still fails to plement data is shifted into the shadow register. A shift
verify, the device is rejected. Once a location verifies suc- from shadow to pipeline is performed and the CLOCK is
cessfully, the address is advanced to the next location, and again pulled from LOW to HIGH. At this point, if the new
the process is repeated until all locations are programmed. data read is data-complement, the device has been pro-
grammed as Output enable while if the new data read-true
After all locations are programmed, they should be verified then the device is programmed as Initialize enable. The
at Veep = 5.0V. configuration of the Initialize byte can be read directly by
Programming Algorithm for the Architecture pulling Ell from HIGH to LOW.
The CY7C265 offers a limited selection of programmed
architecture. Programming these features should be done
Mode Table
P22
P2 P3 P26 P6 P7 P8 P9 PIO P20 P24 P23
Mode Select Ell
A6 AS A9 A2 PGM eLK Al AO VFY All Vpp
All
Normal Read A6 AS A9 A2 L L/H Al AO HIZ All H/L AI2
Program (Memory) A6 A5 A9 A2 L L Al AO H All Vpp AI2
Program Verify A6 A5 A9 A2 H L Al AO L All Vpp AI2
Program Inhibit A6 A5 A9 A2 H L Al AO H All Vpp AI2
Async. Enable Read A6 A5 A9 A2 L L Al AO HIZ All L AI2
Sync. Enable Read A6 AS A9 A2 L L/H Al AO HIZ All L AI2
Async. Init. Read A6 A5 A9 A2 L L Al AO HIZ All L AI2
Program Sync. Enable[l] H Vpp A9 H L L Vpp L H H Vpp H
Program Initialize[2] H Vpp A9 L L L Vpp L H H Vpp L
Program Initial Byte H Vpp A9 L L L Vpp H H L Vpp AI2
Notes:
1. Default is Async. Enable.
2. Default is Enable.
3-75
~ CY7C265
~~~NDUcrOR =====================================================================
Vccp Power Supply Voltage During Programming 4.75 5.25 V
Ipp Vpp Supply Current 50 mA
VIHP Input High Voltage During Programming 3.0 V

tpp Program Pulse Width (Per Byte) 10.0 ms
tAS Addres!! Set-Up Time 1.0 p.s
tAH Address Hold Time 1.0 p.s
tOH Data Hold Time 1.0 p.s
tos Data Set-Up Time 1.0 p.s
tR,F Vpp Rise and Fall Time 1.0 p.s
tOY Delay to Verify 1.0 p.s
tyO Verify to Data Out 1.0 p.s
tYH Data Hold Time from Verify 1.0 p.s
typ Verify Pulse Width 2.0 p.s
toz Verify to High Z 1.0 p.s
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm 2 For an ultra-
erase the CY7C265 in the windowed package. For this rea- violet lamp with a 12 m W / cm2 power rating the exposure
sop, an opaque label should be placed over the window if time would be approximately 45 minutes. The CY7C265
the PROM is exposed to sunlight or fluorescent lighting needs to be within 1 inch of the lamp during erasure. Per-
for extended periods of time. manent damage may result if the PROM is exposed to high
The recommended dose of ultraviolet light fQr erasure is a intensity UV light for an extended period of time. 7258
wavelength of2537 Angstroms for ~ minimum dose (UV Wsec/cm2 is the recommended maximum dosage.
BitMap Data
0 0 DATA

8191 IFFF DATA
8192 2000 INITBYTE
Control Byte
00 Asynchronous output enable (default condition)
02 Asynchronous initialize
3-76
~ CY7C265
~~~NDUcroR=====================================================================
II
0126-9
3-77
~ CY7C265
~~~NDUcrOR ==============================================================~==~
Vee
~------------tDP------------~
Vpp
VSS
ADDRESS
V1LP -
V _
1HP
DATA
V1LP -
PGM
VFY
V1LP
0126-10
Figure 5. Programming Waveforms (Memory)
Note:
Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.
Vee
Vpp
PIN 22 (DIP)
~-------tDP----~--~ ~--------tHP--------~
PINS 3,9 (DIP)

V ___
IHP
ADDRESS
V1LP - - -
VOHP
DATA
VOLP
VIHP
PGM V
1LP
0126-11
Data required on I/O's only during initial programming.
Figure 6. Programming Waveforms for the Architecture
3-78
~ CY7C265
~~~NDUcrOR =====================================================================
NORMALIZED SUPPLY NORMALIZED SUPPLY
CURRENT vs. SUPPLY CURRENT vs. AMBIENT NORMALIZED ACCESS TIME
VOLTAGE TEMPERATURE vs. TEMPERATURE
1.6 1.2 r - - - - . , . . - - - - - - - , 1.6 r - - - - , . . - - - - - - - - ,

1.4 1.4 1 - - - - - + - - - - - - - 1
1.1 ..........: - - - - + - - - - - - 1
./
()
..Y
Q
IoJ
1.2 1.2 1----+-----"""""'''---1
N
::::i
<
~ 1.0 / 1.01------'"...-----1
1.0 I---~"I""------I
~V
0::
0
z 0.9 1 - - - - - + - - - - - - 1
0.8 0~~---~----_4
/' TA = 25C
f=MAX.
0.6 O~~---~-----J 0.6 ' - - - - - " ' - - - - - - - - - '
4.0 4.5 5.0 5.5 6.0 -55 25 125 -55 25 125
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) AMBIENT TEMPERATURE (OC)
TYPICAL ACCESS TIME

OUTPUT SOURCE CHANGE vs. OUTPUT OUTPUT SINK CURRENT
CURRENT vs. VOLTAGE LOADING vs. OUTPUT VOLTAGE
60 30.0 175
~
E ~ 150
;:- 50 25.0 !,
Z
IoJ
0:: ~ .. / I-
z 125
40 20.0
--
IoJ
0::
-=.. 0::
::;)
0
IoJ 30
"l'... J. 15.0
,,/ 0::
::;)
u
100
V
~/'
""
0 ~ ./
0:: ~ z 75
::;)
0 20
-I
IoJ 10.0 Vi
/
" /
VI Q I- 50
/
I- ::;)
::;)
0.. 10 ~ 5.0
0..
I- Vcc =5.0V
::;) 25
" /
I- TA - 25C
::;)
0
o 0.0
Vcc =4.5V
0
o V TAl 25C
0.0 1.0 2.0 3.0 4.0 o 200 400 600 800 1000 0.0 1.0 2.0 3.0 4.0

0126-12
Speed Icc Ordering Package Operating Speed Icc Ordering Package Operating
(ns) (rnA) Code Type Range (ns) (rnA) Code Type Range
40 100 CY7C265-4OPC P21 Commercial 60 80 CY7C265-60PC P21 Commercial
CY7C265-400C 022 CY7C265-600C D22
CY7C265-4OWC W22 CY7C265-60WC W22
50 80 CY7C265-50PC P21 100 CY7C265-600MB D22 Military
CY7C265-500C 022 CY7C265-60WMB W22
CY7C265-50WC W22 CY7C265-60LMB L64
120 CY7C265-500MB 022 Military CY7C265-60QMB Q64
CY7C265-50WMB W22
CY7C265-50LMB L64
CY7C265-50QMB Q64
3-79
~ CY7C265
~~~WUcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
IOZ 1,2,3
lee 1,2,3
ISB 1,2,3
tAS 7,8,9,10,11
tHA 7,8,9,10,11
teo 7,8,9,10,11
tpw 7,8,9,10,11
tSES 7,8,9,10,11
tHES 7,8,9,10,11
teos 7,8,9,10,11
Document #:: 38-00084-A
3-80
CYPRESS
SEMICONDUCTOR 8192 X 8 PROM
Power Switched and
Reprogrannnnable
Features
CMOS for optimum
speed/power
Direct replacement for
EPROMs
The CY7C266 is a plug-in replacement
for EPROM devices. The EPROM cell
II
Windowed for reprogrammability Capable of withstanding > 2000V requires only 12.5V for the supervolt-
static discharge age and low current requirements allow
High speed for gang programming. The EPROM
- 55 ns (commercial) Product Characteristics cells allow for each memory location to
- 55 ns (military) be tested 100%, as each location is
Low power 8192 word by 8 bit CMOS PROM. written into, erased, and repeatedly ex-
- 440 mW (commercial) When deselected, the 7C266 automati- ercised prior to encapsulation. Each
- 495 mW (military) cally powers down into a low power PROM is also tested for AC perform-
stand-by mode. It is packaged in the ance to guarantee that after customer
Super low standby power programming the product will meet
- Less than 85 mW when 600 mil wide package. The reprogram-
mabIe CERDIP packages are equipped DC and AC specification limits.
deselected
with an erasure window; when exposed Reading is accomplished by placing an
EPROM technology 100% to UV light, these PROMs are erased active LOW signal on OE and CE. The
programmable and can then be reprogrammed. The contents of the memory location ad-
5V 10% Vee, commercial and memory cells utilize proven EPROM dressed by the address lines (Ao-AI2)
military floating gate technology and byte-wide will become available on the output
intelligent programming algorithms. lines (00-07).
TTL compatible I/O
NC
7 As As
All
Os
DE
A10
s CE
7
Os
0.
1 5
0.
03
0137-2
2 ..r-;~~ ~>~~
4 3 2 ~~! 32 31 3029
As 5 As
1 AS 6 28 Ag
A. 7 27 All
A3 8
0
26 NC
0
A2 9 25 DE
Al 10 24 AlO
AO 11 23 CE
0137-1 NC 12 22 7
0 0 13 21 Os
14151617181920
- NO 0 I"') .... II')
o0{5zooo
0137-3
Selection Guide
7C266-55
Maximum Access Time (ns) 55
Maximum Operating Commercial 80
Current (rnA) Military 90
Standby Current (rnA) Commercial 15
Military 15
3-81
~~~NDUcrOR=====================================================================
Maximum Ratings
Ambient Te1l1perature with (per MIL-STD-883, Method 3015)
(Pin 28 to Pin 14) .................... -0.5V to +7.0V
Operating Range
Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Temperature
DC Program Voltage .......................... 14.0V Commercial OC to + 70C 5V 1O%

7C266-55
Min. Max.
VOH Output HIGH Voltage Vec = Min., IOH = -4.0mA 2.4 V
VOL Output LOW Voltage Vcc = Min.,IOL = 16.0mA 0.4 V
VIH Input HIGH Level[t] 2.0 V
VIL Input LOW Level[t] 0.8 V
IIX Input Current GND ~ VIN ~ VCC -10 +10 p,A
Input Diode Clamp
VCD Note 2
Voltage
loz Output Leakage Current VOL ~ VOUT ~ VOH, Output Disabled -10 +10 p,A
Output Short
loS Circuit Current[3]
VCC = Max., VOUT = GND -20 -90 mA
Power Supply CMOS Inputs: GND 0.3V or Commercial 20 mA

Icci
Current[S] VCC 0.3V Military 30 mA
Power Supply TTL Inputs Commercial 25 mA
ICC2
Current[S] VIL ~ 0.8V, VIH ~ 2.0V Military 35 mA
Standby Supply CE = Vcc 0.3V Commercial 15 mA
ISBI
Current [7] CMOS Inputs (GND or Vcd 0.3V Military 15 mA
Standby Supply TTL Inputs Commercial 15 mA
ISB2
Current [7] VIL ~ 0.8V, VIH ~ 2.0V Military 15 mA
Capacitance [4]
pF
CoUT Output Capacitance Vcc = 5.0V 8
Notes:
I. These are absolute voltages with respect to device ground pin and 4. Tested initially and after any design or process changes that may
include all overshoots due to system and/or tester noise. Do not at- affect these parameters.
tempt to test these values without suitable equipment. 5. TA is the "instant on" case temperature.
CY7C266 is insensitive to - 3V de input levels and - 5V undershoot information.
pulses of less than 10 ns (measured at 50% point). 7. AC power component add I mA/MHz, Vee = max, lOUT = O.
3. For test purposes, not more than one output at a time should be S. AC power component add 3 mA/MHz, Vee = max, lOUT = O.
3-82
~~~NDUcrOR =====================================================================
Switching Characteristics Over the Operating Range[5, 6, 9]
7C266-55
Min. Max.
tAA Address to Output Valid 55 ns
tHZCE Chip Enable Inactive to High Z[lO] 55 ns
tHZOE
tAOE
tACE
Output Enable Inactive to High Z[tO]
Output Enable Active to Output Valid
Chip Enable Active to Output Valid
20
20
55
ns
ns
ns
II
tOHA Data Hold from Address Change 3 ns
5V o----\N\_ Rl 250.0. Rl 250.0.

5V 0---""""'1"""'........
3.0V ----1.-_---1
OUTPUT 0 - - - + - - - 4 OUTPUT 0 - -....- -..... GND
INCLUDING
JIG AND
I 30
pF'
R2
167.0. INCLUDING
JIG AND
IS pF'
R2
167.0. 0137-5
SCOPE -= SCOPE -= Figure 2. Input Pulses

0137-4
Figure la Figure Ib
100.0.
OUTPUT o----'V+IV--O 2.0V
0137-6
Vec _ _ _ _ _ _ _ _ _ _ _ _ _ _"'" POWER DOWN CONTROLLED BY CE

SUPPLY
CURRENT
''''' _ _ _ --J/
Ao-A12
ADDRESS ~I\.
J '1\.
I - tHZCE_ j . - - - t ACE - - - I
I - tAA - t HZOE
tOHA~ t AOE I
NOTE 8 TJ7
KXX~I\. ~
NOTE 8 " \:
I
0137-7
Notes:
9. Test conditions assume signal transition times of 5 ns or less, timing 10. tHzCS is tested with load shown in Figure lb. Transition is measured
reference levels of 1.5V, output loading of the specified 101l10H and at steady state High level - 500 mV or steady state Low level + 500
loads shown in Figure lao lb. mV on the output from the 1.5V level on the input.
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm2. For an ultra-
erase the devices in the windowed package. For this reason, violet lamp with a 12 mW/cm 2 power rating the exposure
an opaque label should be placed over the window if the time would be approximately 45 minutes. The 7C266 needs
EPROM is exposed to sunlight or fluorescent lighting for to be within 1 inch of the lamp during erasure. Permanent
extended periods of time. damage may result if the EPROM is exposed to high inten-
The recommended dose of ultraviolet light for erasure is a sity UV light for an extended period of time.
wavelength of 2537 Angstroms for a minimum dose (UV 7258W X sec/cm2 is the recommended maximum dosage.
383
~~~NDUcrOR================================================================
55 CY7C266-55PC PIS Commercial
CY7C266-55WC W16
CY7C266-550C 016
CY7C266-550MB D16
CY7C266-55LMB L55
CY7C266-55QMB Q55
3-84
~~~~UcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB 1,2,3
tAA 7,8,9,10,11
tHZOE 7,8,9,10,11
tHZCE 7,8,9,10,11
tAOE 7,8,9,10,11
tACE 7,8,9,10,11
3-85
CY7C268
CY7C269
CYPRESS
SEMICONDUCTOR 64K Registered
Diagnostic PROM
CMOS for optimum speed/ The CY7C268 and CY7C269 are 64K dard featured diagnostics of the 7C268
power Registered Diagnostic PROMs. They utilizes the SI and SO (shift in and shift
High speed are both organized 8192 words by 8 out), MODE and DCLK signals. These
- 40 ns max set-up bits wide, and have both a Pipeline signals allow serial data to be shifted
- 20 ns clock to output Output Register and an Onboard Diag- into and out of the Diagnostic Shift
nostic Shift Register. In addition, both Register at the same time the Pipeline
Low power devices feature a Programmable Initial- Register is used for normal operation.
- 550 mW (commercial) ize Byte which may be loaded into the The MODE signal is used to control
- 660 mW (military) Pipeline Register with the Initialize sig- the transfer of the information in the
On-chip edge-triggered registers nal. The Programmable Initialize Byte Diagnostic Register to the Pipeline
- Ideal for pipelined is the 8193rd byte in the PROM and its Register or the data on the Output Bus
microprogrammed systems value is programmed at time of use. into the Diagnostic Register. The data
On-chip diagnostic shift register The 7C268 has 32 pins and features full on the Output Bus may be provided
- For serial observability and diagnostic capabilities while the 7C269 from the Pipeline Register or an exter-
controllability of the output provides limited diagnostics and is nal source.
register available in a space efficient 28 pin When the MODE signal is LOW, the
EPROM technology package. This allows the designer to PROM operates in a normal pipeline
- 100% programmable optimize his design for either board mode. The contents of the addressed
- Reprogrammable (7C269W) area efficiency with the 7C269, or com- memory location is loaded into the
SV 10% Vee, commercial and bine the 7C268 with other diagnostic Pipeline Register on the rising edge of
military products with the standard interface. PCLK. The outputs are enabled with
CY7C268: The 7C268 provides 13 ad- the ENA signal either synchronously
Capable of withstanding greater or asynchronously, depending on how
than 2001V static discharge dress signals (Ao through A12), 8 data
out signals (00 through 07), ENA (en- the device is configured when pro-
Slim, 300 mil 28 pin plastic or able), PCLK (pipeline clock) and INIT grammed. If programmed for asyn-
hermetic DIP (7C269) chronous enable, ENA LOW enables
(initialize) for control. The full stan-

CY7C268 CY7C269
VCC
AIO
A"
A'2
E/Es.T
SOl
SDO
t/T_
(7C269)
CLO(~~269f' CONTROL
PCLK~ LOGIC DCLK
(7C268)
(7C268)
ENA--+
(7C268)
iNiT--+
(7C268)
l_Ji)i:li:E3:a~Ii:E=!J 0112-3
0112-2
4 .3 2: 1 :28 21 26
A3 5 1._4 25 Al0
4 3 2: 1 :32 31 30 A2 6
A3 5 .. _.. 29 Al0 MODE 7 23 A'2
A2 6 28 A" CLOCK 8 CY7C269 22 EI Es. T
MODE 7 27 rNA A, 9 21 SOl
NC 8 26 iNiT Ao 10 20 SDO
DCLK 9 CY7C268 25 NC 0 0 11 19 0 7
121314151617 18
PCLK 10 24 A'2
0112-1 A, 11 23 SOl
Ao 12 22 soo
0 0 13 21 07 0112-5
14 15 16 17 18 19 20
o8 ~ 0' 0" cf 0'4 0112-4
3-86
CY7C268
WA ..
~~NDUcroR
Selection Guide
=====================================================================
CY7C269
7C268/9-40 7C268/950 7C268/9-60

Maximum Set-up Time (ns) 40 50 60
Maximum Operating
Current (rnA)
I Military 120 100

the outputs. If configured for synchronous enable, ENA Enable or the Initialize function. If the Ell pin is used for a
LOW during the rising edge ofPCLK will enable the out- INIT (Asynchronous Initialize) function, the outputs are
puts synchronously with PCLK. ENA HIGH during the permanently enabled and the Initialize Word is loaded into
rising edge of PCLK will synchronously disable the out- the Pipeline Register on a High to LOW transition of the
puts. The asynchronous Initialize signal INIT transfers the INIT signal. The INIT LOW disables CLOCK and must
Initialize Byte into the Pipeline Register on a HIGH to return high to re-enable CLOCK. If the Ell pin is used for
LOW transition. INIT LOW disables PCLK and needs to an enable signal, it may be programmed for either synchro-
transition back to a HIGH in order to enable PCLK. nous or asynchronous operation. This enable function then
DCLK shifts data into SI and out of SO on each rising operates exactly the same as the 7C268.
edge. When the MODE signal is HIGH, the 7C269 operates in
When MODE is HIGH, the rising edge of the PCLK sig- the diagnostic mode. The Ell signal becomes a secondary
nalloads the Pipeline Register with the contents of the mode signal designating whether to shift the Diagnostic
Diagnostic Register. Similarly, DCLK, in this mode, loads Shift Register or to load either the Diagnostic Register or
the Diagnostic Register with the information on the Data the Pipeline Register. If Ell is HIGH, CLOCK performs
Output Pins. The information loaded will be either the con- the function of DCLK, shifting SI into the least significant
tents of the Pipeline Register if the outputs are enabled, or location of the Diagnostic Register and all bits one location
data on the bus, if the outputs are disabled (in a high im- toward the most significant location on each rising edge.
pedance state). The contents of the most significant location in the Diag-
CY7C269: This product is optimized for applications that nostic Register are available on the SO pin.
require diagnostics in a minimum amount of board area. If the Ell signal is LOW, SI becomes a direction signal;
Packaged in 28 pins, the PROM has 13 Address Signals transferring the contents of the Diagnostic Register into
(Ao through A12), 8 Data Out Signals (00 through 07), Ell, the Pipeline Register when SI is LOW. When SI is HIGH,
(Enable or Initialize) and CLOCK (pipeline and diagnostic the contents of the Output pins are transferred into the
clock). Additional diagnostic signals consist of MODE, SI Diagnostic Register. Both transfers occur on a LOW to
(shift in) and SO (shift out). Normal pipelined operation HIGH transition of the CLOCK. If the Outputs are en-
and Diagnostic operation are mutually exclusive. abled, the contents of the Pipeline Register are transferred
When the MODE signal is LOW, the 7C269 operates in a into the Diagnostic Register. If the Outputs are disabled,
normal pipelined mode. CLOCK functions as a pipeline an external source of data may be loaded intothe Diagnos-
clock, loading the contents of the addressed memory loca- tic Register. In this condition, the SO signal is internally
tion into the Pipeline Register on each rising edge. The driven to be the same as the SI signal thus propagating the
data will appear on the Outputs if they are enabled. One "direction of transfer information" to the next device in the
pin on the 7C269 is programmed to perform either the string.
3-87
CY7C268
Wn. ~DUaDR================================================================~
.
Maximum Ratings
. CY7C269
(Above which the useful1ife may be impaired. For us~r guidelines, not tested.)
Supply Voltage to Ground Potential .... -0.5V to +7.0V UV Exposure ........................... 7258 Wsec/c
Ambient
DC Input Voltage ................... - 3.0V to + 7.0V Range
Temperature Vee
DC Program Voltage .......................... 13.0V
Commercial OCto 70C 5V 1O%
Military[l] - 55C to + 125C 5V 10%

Commercial Military
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min.,IOH = -2mA 2.4 2.4 V
Vee = Min., IOL = 12 mA
VOL Output LOW Voltage 0.4 0.4 V
(IOL = 8 mA for Military)
VIL Input LOW Voltage 0.8 0.8 V
IIX Input Load Current GND ~ VIN ~ Vee 10 10 p.A
Output Leakage GND ~ VOUT ~ Vee
loz Current Output Disabled
40 40 p.A

los Current
Vee = Max., VOUT = GND 90 90 mA
7C268/9-4O 100
Vee Operating Supply Vee = Max.
Icc Current lOUT = OmA 7C268/9-50 80 120 rnA
7C268/9-6O 80 100
Capacitance [3]
CIN Input Capacitance TA = 25C,f = 1 MHz 5
pF
COUT

7C268-40 7C268-50 7C268-60
tAS Address Set-Up to Clock 40 50 60 ns
tHA Address Hold from Clock 0 0 0 ns
teo Clock to Output Valid 20 25 25 ns
tpw Clock Pulse Width 15 20 20 ns
tsES Es Set-Up to Clock (Sync Enable Only) 15 15 15 ns
tHES Es Hold from Clock 5 5 5 ns
tDI INIT to Out Valid 25 35 35 ns
tRI INIT Recovery to Clock 20 25 25 ns
3-88
~ CY7C268
--~RESS CY7C269
-W, SEMICONDUCTOR ====================================
Switching Characteristics Over the Operating Range[3] (Continued)
7C26840 7C26850 7C26860
tpWI Init Pulse Width 25 35 35 ns
tcos Output Valid from Clock (Sync. Mode) 20 25 25 ns
tHzC
tDOE
Output Inactive from Clock (Sync. Mode)
Output Valid from E Low (Async. Mode)
20
20
25
25
25
25 ns
ns
III
tHZE Output Inactive from E High (Async. Mode) 20 25 25 ns
Diagnostic Mode Switching Characteristics Over the Operating Range[2]

Commercial Military
Min. Max. Min. Max.
tSSDI Set-Up SDI to Clock 30 35 ns
tHSDI SDI Hold from Clock 0 0 ns
tDSDO SDO Delay from Clock 30 40 ns
tDCL Minimum Clock Low 25 25 ns
tDCH Minimum Clock High 25 25 ns
tSM Set-Up to Mode Change 25 30 ns
tHM Hold from Mode Change (7C269) 0 0 ns
tMS ModetoSDO 25 30 ns
tss SDIto SDO 40 45 ns
tso Data Set-Up to DCLK 25 30 ns
tHO Data Hold from DCLK 10 15 ns
Notes:
2. See the last page of this specification for Group A subgroup testing affect these parameters.
information.

R13381l R13380 ALL INPUT PULSES
5V ( } - - - - ' V ' w ' \ , _..... 5Vo----~~~
(50011 FOR MIL) (SOOIl FOR MIL.) 3.0 V-----.io~---.....
OUTPUT O----<i~--_. OUTPUT 0---..-----.
R2 GND
50 pF 24811 5pF ;:'0
I INCLUDING
JIG AND
-= SCOPE -=
(33311 FOR MIL)
I INCLUDING
-=~~:~D _
(33311 FOR MIL)
0112-6
0112-7
1430
(2000 FOR MIL) 2.11V
OUTPUT ~ (2.0VFORMIL)
0112-8
389
CY7C268
Wn
. .
.
Switching Waveforms 7C268, 7C269
CY7C269
~~UaoR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pipeline Operation (Mode = 0)
ADDRESS
----------------
SYNCHRONOUS ENABLE
(PROGRAMMABLE) _ _ _-'I
PCLK / CLOCK (7C269)

---+-"1
OUTPUT
,Q,QoIiWWIoQQjoi--o+o-"1
(7C269 PROGRAMMABLE)
ASYNCHRONOUS INIT. ~~P~...-J_--------,"~~~~~~~~~ ~J
~ ___ t
HZE
ASYNCHRONOUS
ENABLE _ _ _ _./ . . J .
\. "'-_ _ _ __
0112-9
Notes on Testing:
Inadequate decoupling may result in large variations of power supply 5. Transition is measured at steady state HIGH level - 500 mV or
voltage, creating erroneous function or transient performance failures. steady state LOW level + 500 mV on the output from the 1.5V level
2. Do not leave any inputs disconnected (floating) during any tests. on inputs with load shown in Figure lb.
7C268 Diagnostic Waveforms
DCLK
---"1
__~ _ _ _ _ _ _ _ _ _J
SOl
SOO _~ ____ ______________

'I~ ~J
MODE
PCLK _ _ _-,I
OUTPUT ________________________
tHO t
.J"'-____.J}{'-------------------------
0112-10
3-90
CY7C268
(in~UcrOR==================================================================
.. CY7C269

7C269 Diagnostic Application (Shifting the Shadow Register)
CLOCK
MODE
SOO
--Io--+'
SOl
--Io--~------JI
EIT
0112-11
7C269 Diagnostic Application (Parallel Data Transfer)
CLOCK
----+-....".1
MODE
--10-""'1
SOl
--10----+-+-"1
SOO
_ _ _ _ _-+~_____J l
EIT
teo t
00-07 _________________~OUT
0112-12
Notes:
6. Asynchronous enable mode only. 7. The mode transition to HIGH latches the asynchronous enable state.
If the enable state is changed and held before leaving the diagnostic
mode (mode H -+ L) then the output impedance change delay is
tMS
Device Programming Programming Pinout
The CY7C268 and CY7C269 program identically. They The Programming Pinout of both devices is shown in Fig-
utilize an intelligent programming algorithm to assure con- ures 3a and 3b. The programming mode is entered by put-
sistent programming quality. These 64K PROMS use a ting 12.SV on the Vpp pin. The addressed 10catipGt:pro-
single ended memory cell design. In an unprogrammed ~FYmed and verified with the application of a and
state, the memory contains all "O"s. During programming, pulse. Entering and exiting the programming mode
a "1" on a data-in pin causes the addressed location to be should be done with care. Proper sequencing as described
programmed, and a "0" causes the location to remain un- in the dialog on the programming algorithm and shown in
programmed. the timing diagram and programming flow chart must be
implemented.
3-91
CY7C268
~ CY7C269
~~~~UcrOR==================================================================
A7
As
A5
A4
A3
A2 A12
PGM Vpp
CLOCK SOl
VFY
7
Os
5
4
3
0112-14
Figure 3b. 7C269 Programming Pinout
0112-13
Figure 3a. 7C268 Programming Pinout
Programming and Blankcheck (Memory Bits)

Blankcbeck After all locations are programmed, they should be verified
at Vccp = 5.0V.
Blankcheck is accomplished by performing a verify cycle
(V'FY toggles on each address), sequencing through all Programming Algorithm for the Architecture
memory address locations, where all the data read will be Both the 7C268 and 7C269 offer a limited selection of pro-
"0"8. (Refer to mode table for pin states) grammed architecture. Programming these features should
Programming Algorithm be done with a single 10 ms wide pulse in place of the
intelligent algorithm mainly because these features are veri-
Programming is accomplished with an intelligent algo- fied operationally, not with the VFY pin. Architecture pro-
rithm. The sequence of operations is to enter the program- gramming is implemented by applying the supervoltage .to
ming mode by placing 12.5V on Vpp. This should be done two additional pins during programming. In programmmg
after a minimum delay from power up, and be removed the 7C269 architecture Vpp is applied to pins 3, 9 and 22
prior to power down by the same delay (see the timing while in programming the 7C268 architecture Vpp is ap-
diagram and AC specifications for details). Once in this plied to pins 3, 11,26. Specific choice o.f a pa~icular mode
mode, programming is accomplished by addressing a loca- will depend on the states ofthe other. I?ms dunng progr~m
tion as desc.ribed above, pla~ing the data t? be progGmmed ming so it is important that the cond1t10n of the oth~r pms
into a location on the data pms, and clocking the P M be met as set forth in the mode table. The same cons1dera-
signal from VIHP to VILP and back to VIHP with a pulse tions with respect to power up and power down apply dur-
width of 200 JLs. The data is removed from the data pins ing architecture programming as during intelligent ~ro
and the content of the location is then verified by taking gramming. Once the supervol~ages have been est~bhs~ed
the VFY signal from VIHP to VILP, comparing the output and the correct logic states eX1st on the other dev1ce pms,
with the desired data and then returning VFY to VIHP. If programming may begin. Programming is accomplished by
the contents are correct, a second overprogram pulse of 4 pulling PGM from HIGH to LOW and then back to
times the original 200 JLs is delivered with the data to be HIGH with a pulse width equal to 10 ms.
programmed again on the data pins. If the data is not cor-
rect, a second 200 JLS pulse is applied .to PGM with the To check whether a 7C269 has been programmed as output
data to be programmed on the data pms. The compare and enable or initialize enable, pin 22 (Ell) should be pulled
overprogram operation is repeated with an overprogram LOW followed by a LOW to HIGH transition on pin 8
pulse width 4 times the sum of the initial program pulses. (CLOCK). The data read at the outputs is stored and. com-
This operation is continued until the location is pro- plement data is shifted into the shadow register. A sh1ft.
grammed or 10 initial program pulses have been attempted. from shadow to pipeline is performed and the CLOCK 1S
If on the 10th attempt, the location fails to verify, an over- again pulled from LOW to HIGH. At this point, ifthe new
program pulse of 8 ms is ~pp1ied, and the ~onte~t o~ the data read is data-complement, the device has been pro-
location is once more venfied. If the locatlOn still fatls to grammed as Output enable while if the new data read-true
verify, the device is reJected. Once a location verifi~s suc- then the device is programmed as Initialize enable and the
cessfully, the address 1S advanced to the next locat10n, and configuration of the Initialize byte can be read directly by
the process is repeated until all locations are programmed. pulling Ell from HIGH to LOW.
3-92
CY7C268
5A~~NDUcrOR=======================================================================
.
Mode Table 7C268

CY7C269
P7 P22 P26
P2 P3 P30 P6 P9 PIO Pll Pl2 P23 P24 P27 P28
Mode Select MD SDO INT
A6 AS A9 A2
PGM
DCLK PCLK Al AO
VFY
SDI A12
Vpp ElEs All
Normal Read[2] A6 A5 A9 A2 L X L/H Al AO SDO X Al2 H H/L All

Load SR to PR[2] A6 A5 A9 A2 H L L/H Al AO SDI X Al2 H X All
Load Output to SR A6 A5 A9 A2 H L/H L Al AD SDI L Al2 H H All
Shift Shadow[2] A6 A5 A9 A2 L L/H L Al AD SDO DIN Al2 H X All
Program (Memory) A6 A5 A9 A2 L L L Al AD H L Al2 Vpp H All
Program Verify A6 A5 A9 A2 H L L Al AO L L Al2 Vpp H All
Program Inhibit A6 A5 A9 A2 H L L Al AD H L Al2 Vpp H All
Async. Enable Read A6 A5 A9 A2 L L X Al AD SDO L Al2 H H/L All
Sync. Enable Read A6 A5 A9 A2 L L L/H Al AO SDO L Al2 H H/L All
Async. Init. Read A6 A5 A9 A2 L L X Al AD SDO L Al2 L L All
Program Sync. Enable[I] H VHH X H L L L VHH L H L H Vpp H H
Program Initial Byte H VHH X L L L L VHH H H L X Vpp H L
Notes:
1. Default is Async. Enable. LOW. When E goes from LOW to HIGH (enable to disable) the outputs
2. For the a~chronous enable operation, the data out is enabled by will go to the high impedance state (after a propagation delay) immedi-
bringing E LOW. For the synchronous enable operation, data out is ately if the asynchronous enable was programmed. If the synchronous
enabled on the first LOW to HIGH clock transition after E is brought enable was selected, a LOW to HIGH clock transition is required.
Mode Table 7C269

P7 P20 P22
P2 P3 P26 P6 P8 P9 PIO P21 P24 P23
Mode Select
A6 AS A9 A2
MD
CLK Al AO SDI
SDO
All
Ell Al2
PGM VFY Vpp
Normal Read A6 A5 A9 A2 L L/H Al AD X HIZ All H/L Al2
Load SR to PR[3] A6 A5 A9 A2 H L/H Al AD L SDI All L Al2
Load Output to SR[3] A6 A5 A9 A2 H L/H Al AO H SDI All L Al2
Shift Shadow[3] A6 A5 A9 A2 H L/H Al AD DIN SDO All H Al2
Program (Memory) A6 A5 A9 A2 L L Al AD X H All Vpp Al2
Program Verify A6 A5 A9 A2 H L Al AD X L All Vpp Al2
Program Inhibit A6 A5 A9 A2 H L Al AD X H All Vpp Al2
Async. Enable Read A6 A5 A9 A2 L L At AD X HIZ All L At2
Sync. Enable Read A6 A5 A9 A2 L L/H Al AD X HIZ All L Al2
Async. Init. Read A6 A5 A9 A2 L L At AD X HIZ All L Al2
Program Sync. Enable[I] H VHH A9 H L L VHH L X H H Vpp H
Program Initialize[2] H VHH A9 L L L VHH L X H H Vpp L
Program Initial Byte H VHH A9 L L L VHH H X H L Vpp Al2
Notes:
1. Default is Async. Enable. 3. IfI selected, outputs always enabled. IfE selected, during diagnostic
2. Default is Enable. operation the data outputs will remain in the state they were in when
the mode was entered. When enabled, the data outputs will reflect the
outputs of the pipeline register. Any changes in the data in the pipe-
line register will appear on the data output pins.
3-93
Vccp Power Supply Voltage During Programming 4.75 5.25 V
VIHP Input High Voltage During Programming 3.0 V

tpp Program Pulse Width (per Byte) 10.0 ms
tAS Address Set-up Time 1.0 Il-s
tAH Address Hold Time 1.0 Il-s
tOH Data Hold Time 1.0 Il-s
tos Data Set-up Time 1.0 Il-s
tR,F Vpp Rise and Fall Time 1.0 Il-s
tov Delay to Verify 1.0 Il-s
tvo Verify to Data Out 1.0 Il-s
tVH Data Hold Time from Verify 1.0 Il-s
tvp Verify Pulse Width 2.0 Il-s
toz Verify to High Z 1.0 Il-s
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm2 . For an ultra-
erase the 7C268 and 7C269 in the windowed package. For violet lamp with a 12 mW/cm2 power rating the exposure
this reason, an opaque label should be placed over the win- time would be approximately 45 minutes. The 7C268 or
dow if the PROM is exposed to sunlight or fluorescent 7C269 needs to be within 1 inch ofthe lamp during era-
lighting for extended periods of time. sure. Permanent damage may result ifthe PROM is ex-
wavelength of 2537 Angstroms for a minimum dose (UV time. 7258 Wsec/cm2 is the recommended maximum dos-
age.
BitMap Data
0 0 DATA

8191 1FFF DATA
8192 2000 INITBYTE
Control Byte
00 Asynchronous output enable (default condition)
02 Asynchronous initialize (CY7C269 only)
3-94
CY7C268
5n
. CYPRESS CY7C269
S~IOO~UQOR==========================================================~======
0112-15
3-95
CY7C268
5Ii~NDUcrOR ==================================
.
. . CY7C269
Vee
7C268 PIN 32
7C269 PIN 28
~------------tDP------------~
Vpp
7C268 PIN 26
7C269 PIN 22
ADDRESS AO-A12
V1LP - tDs-----i
V _ PROGRAM "1"
1HP
DATA
V1LP -
PGM
7C268 PIN 7
7C269 PIN7
Vrv
7C268 PIN 22
7C269 PIN 20 V1LP
0112-16
Figure 5. Programming Waveforms (Memory)
Note:
Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.
Vee
PIN
Vpp
~------tDP--------~ ~--------tHP--------~
PINS
(Ppp ALSO)
V ___
1HP
ADDRESS
V1LP - - -
VOHP
DATA
VOLP
V1HP
PIN7
PGM
V1LP
0112-17
*7C268-pin 26 ***Data required on I/O's only during initial byte programming

7C269-pin 22
**7C268-pins 3,11
7C269-pins 3, 9
Figure 6. Programming Waveforms for the Architecture CY7C268 and CY7C269
l96
~ CY7C268
.n~IfE'NDUCTOR ======================================================C=Y==7=C=2=6==9
NORMALIZED SUPPLY NORMALIZED SUPPLY
CURRENT vs. SUPPLY CURRENT vs. AMBIENT NORMALIZED ACCESS TIME
VOLTAGE TEMPERATURE vs. TEMPERATURE
1.6 12r-----~--------~ 1.6 ...----------r--------~
1.4 lA~--_r-----~
J:l
/
0 1.1
_0
13 1.2 13
N
::J
-<
~ 1.0 / N
::J
-<
~
1.01-------'"100;:-----_/
1.0 I------:::o~'-------_/
V
Q:
0
z
oz
0.91-----+-----_/
0.8 OBI-------+--------_/
0.6
V TA =250C
f=MAX.
OB~----~--------~
0.6 ~ _______L._ _ _ _ _ _ _ ___'
4.0 4.5 5.0 5.5 6.0 -55 25 125 -55 25 125
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) AMBIENT TEMPERATURE (OC)
TYPICAL ACCESS TIME

OUTPUT SOURCE CHANGE vs. OUTPUT OUTPUT SINK CURRENT
CURRENT vs. VOLTAGE LOADING vs. OUTPUT VOLTAGE
60 30.0 175
<'
<'
~ 50 25.0
f~
150
~
Q:
Q: 40 "-'t'-... ]: 20.0 V 125
~'/
Q:
::l Q:
100
.:~.
(.) ::l
..... 30 15.0 (.)
/.",-
(.)
....... / :..:
0
Q:
::l
In
20 ~ a
c 10.0
z
iii
75
V
V
"
I- 50
::l
I-
::l
0.. 10 ~ 5.0
TA _25C
~
::l 25 / Vcc =5.0V
V
"
I-
oV
::l 0 TAi250C
0 Vcc =4.5V
o 0.0
0.0 1.0 2.0 3.0 4.0 o 200 400 600 800 1000 0.0 1.0 2.0 3.0 4.0

0112-18
(ns) (rnA) Code Type Range (ns) (rnA) Code Type Range
40 100 CY7C268-40DC D20 Commercial 60 80 CY7C268-60DC 020 Commercial
CY7C268-40WC W20 CY7C268-60WC W20
CY7C269-40PC P21 CY7C269-60PC P21
CY7C269-40DC D22 CY7C269-60DC 022
CY7C269-40WC W22 CY7C269-60WC W22
50 80 CY7C268-50DC D20 100 CY7C268-60DMB 020 Military
CY7C268-50WC W20 CY7C268-60WMB W20
CY7C269-50PC P21 CY7C268-60LMB L55
CY7C269-50DC D22 CY7C268-60QMB Q55
CY7C269-50WC W22 CY7C269-60DMB 022
120 CY7C268-50DMB D20 Military CY7C269-60WMB W22
CY7C268-50WMB W20 CY7C269-60LMB L64
CY7C268-50LMB L55 CY7C269-60QMB Q64
CY7C268-50QMB Q55
CY7C269-50DMB D22
CY7C269-50WMB W22
CY7C269-50LMB L64
CY7C269-50QMB Q64
3-97
CY7C268
5Il CYPRESS
SEMICONDUcrOR
CY7C269
===========================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VIL 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB 1,2,3
tAS 7,8,9,10,11
tHA 7,8,9,10,11
tco 7,8,9,10,11
tpw 7,8,9,10,11
tSES 7,8,9,10,11
tHES 7,8,9,10,11
tcos 7,8,9,10,11
Diagnostic Mode Switching

Characteristics
tssDI 7,8,9,10,11
tHsDI 7,8,9,10,11
tDSDO 7,8,9,10,11
tDCL 7,8,9,10,11
tDCH 7,8,9,10,11
t HM l1] 7,8,9,10,11
tMS 7,8,9,10,11
tss 7,8,9,10,11
Note:
1. 7C269 only.
3-98
CY7C271
CY7C274
CYPRESS
Power Switched and
Reprogrananaable
Features
CMOS for optimum
speed/power
> 2001 V static discharge
performance and programming yield.
The EPROM cell requires only 12.5V
for the supervoltage and low current
-=-
.:.
Windowed for reprogrammability
Product Characteristics requirements allow for gang program-
High speed The CY7C271 and CY7C274 are high ming. The EPROM cells allow for each
- 45 ns (commercial) memory location to be 100% tested,
- 55 ns (military) performance 32,768 word by 8 bit
CMOS PROMS. When disabled (CE with each location being written into,
Low power HIGH), the 7C271!274 automatically erased and repeatedly exercised prior
- 660 mW (commercial) powers down into a low power standby to encapsulation. Each PROM is also
- 715 mW (military) mode. The CY7C271 is packaged in tested for AC performance to guaran-
the 300 mil slim package. The tee that after customer programming
Super low standby power the product will meet DC and AC
- Less than 165 mW when CY7C274 is packaged in the industry
standard 600 mil package. Both the specification limits.
deselected
7C271 and 7C274 are available in a Reading the 7C271 is accomplished by
EPROM technology CERDIP package equipped with an ~cing active LOW signals on CSt and
100% programmable erasure window to provide for repro- CE, and an active HIGH on CS2.
5V 10% Vcc, commercial grammabiIity. When exposed to UV Reading the 7C274 is accomplished by
and military light, the PROM is erased and can be ~cing active LOW signals on OR and
reprogrammed. The memory cells uti- CEo The contents of the memory loca-
TTL compatible I/O lize proven EPROM floating gate tech- tion addressed by the address lines
Slim 300 mil package (7C271) nology and byte-wide intelligent pro- (Ao-At4) will become available on the
Direct replacement for gramming algorithms. output lines (00-07)'
bipolar PROMs The CY7C271 and CY7C274 offer the
advantage of lower power, superior

CY7C271 CY7C274
06
As
AS
5 A,.
CS,
A. CS2
4 A, CE
2
0102-2 0102-10
0, .t:t.t~~;i
4 3 2 ;~! 32 31 3029 AS S 4 3 2 :~: 32 3' 30
29
As
As 5 A,.
0
00 As 6 28 AU AS 6 28 A9
o
CE A. 7 27 A14 27 A"
(7C271) CS, A3
8
26 NC
26 NC
(7C271) CS 2 A2 9 25 CS, 25 or
(7C274) OE A, 10 24 CS2 24 AlO
0102-1 AO 11 23 CE 23 CE
NC 12 22 07 22 07
0 0 13 21 0 8
1415 16 17 18 19 20
_ NO (,,) ~ .. In
oo~zooo
0102-3 0102-11
3-99
CY7C271
Wn -
~~NDUcrOR =======================================================================
Selection Guide
CY7C274
7C2714S 7C271SS
7C2744S 7C274SS
Maximum Operating Commercial 120 120
Commercial 30 30
Standby Current (rnA)
Military 40
Maximum Ratings
Ambient Temperature with (per MILSTD883, Method 3015)
Supply Voltage to Ground Potential .... -O.SV to + 7.0V UV Exposure ........................ 7258 Wsec/cm 2
in High Z State ...................... - o. SV to + 7.0V
Ambient
DC Input Voltage ................... - 3.0V to + 7.0V Range Vee
Temperature
DC Program Voltage .......................... 13.0V Commercial OCto +70C 5V 10%
Military [4] - 5SoC to + 12SoC 5V 10%
Electrical Characteristics Over the Operating Range[S]
7C2714S 7C271SS
Parameters Description Test Conditions 7C2744S 7C274SS Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = - 2.0 rnA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA * 0.4 0.4 V
VIR Input HIGH Level[l] 2.0 Vcc 2.0 Vcc V
VIL Input LOW Level[l] 0.8 0.8 V
IIX Input Current GND ~ VIN ~ Vcc -10 +10 -10 +10 p.A
Input Diode Clamp
VCD Note 2 Note 2
Voltage
Output Leakage VOL ~ VOUT ~ VOH, -40 +40 -40 +40 p.A
Ioz Current Output Disabled
Output Short
los Circuit Current[3] Vcc = Max., VOUT = GND -20 -90 -20 -90 rnA
Power Supply Vcc = Max., VIN = 2.0V Commercial 120 120 rnA
Icc Current lOUT = OmA Military 130 rnA
Standby Supply Vcc = Max., CS ~ VIR Commercial 30 30 rnA
ISB Current lOUT = OmA Military 40 rnA
*6.0 mA military
Capacitance [6]
CIN Input Capacitance T A = 2SoC, f = 1 MHz 8
pF
Notes:
tempt to test these values without suitable equipment. 4. T A is the "instant on" case temperature.
CY7C27l and CY7C274 are insensitive to - 3V dc input levels and information.
- SV undershoot pulses of less than 10 ns (measured at SO% point). 6. Tested initially and after any design or process changes that may
3-100
CY7C271
(;Ii~~NDUcrOR =======================================================================
.'
.
CY7C274

7C27145 7C27155
Parameters Description 7C27445 7C274-55 Units
Min. Max. Min. Max.
tAA Address to Output Valid 45 55 ns
tHzCS Chip Select Inactive to High Z[B] (CSI and CS2-7C271 Only) 30 30 ns
tACS Chip Select Active to Output Valid (CSI and CS2-7C271 Only) 30 30 ns
tHZOE Output Enable Inactive to High Z[B] (OE- 7C274 Only) 25 30 ns
tOE Output Enable Active to Output Valid (OE-7C274 Only) 25 30 ns
tHZCE Chip Enable Inactive to High Z[B] (CE Only) 50 60 ns
tACE Chip Enable Active to Output Valid (CE Only) 50 60 ns
tpu Chip Enable Active to Power Up 0 0 ns
tPD Chip Enable Inactive to Power Down 50 60 ns
tOH Output Hold from Address Change 0 0 ns

Rl Rl
500.ll 500.ll
5v~(65S.llMIL) 5VJlJ(65S.ll
MIL)
3.0V~.
~~
OUTPUT OUTPUT
~~3.ll ~~3.ll GND 10% 10%
INCLUDING I 30 pF
(403.ll MIL) INCLUDING I 5 pF
(403.ll MIL) ~Sns -.: 5n.
JIG AND
SCOPE -= -= JIG AND
SCOPE -= -= 0102-4 Figure 2. Input Pulses
0102-6
Figure la Figure Ib
200.0.
OUTPUT ~ 2.00V COMMERCIAL
2S0.o.
OUTPUT ~ 1.90V MILITARY 0102-5
SUPPLY
Vce
- tpD
1-
"\.SO%
- tpu CPOWER DOWN CONTROLLED BY
-kSO%
CE
CURRENT I I
Ao-A 14
ADDRESS
CS2
)
[9J Of, CE, CS 1
_ t AA - (tHzoE) (tOE)
~ _tHZCS(E) -l -tACS(E)---J
NOTE 8 HIGH Z 'I
PREVIOUS DATA VALID IX>O DATA VALID
I ~ NOTE 8 " 0102-7
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing state Low level + 500 mV on the output from the 1.5 level on the
reference levels of 1.5V, output loading of the specified lox/IOH and input.
loads shown in Figure la, lb. 9, CS2 and CSt are used on the 7C271 only, OE is used on the 7C274
B. tHZCS(E) and tHZOE are tested with the load shown in Figure lb. only.
Transition is measured at steady state High level - 500 mV or steady
Wavelengths of light less than 4000 Angstroms begin to intensity X exposure time) or 25 Wsec/cm 2 . For an ultra-
erase the 7C271 and 7C274 in the windowed package. For violet lamp with a 12 m W / cm2 power rating the exposure
this reason, an opaque label should be placed over the win- time would be approximately 45 minutes. The 7C271 and
dow if the PROM is exposed to sunlight or fluorescent 7C274 need to be within 1 inch of the lamp during erasure.
lighting for extended periods of time. Permanent damage may result if the PROM is exposed to
The recommended dose of ultraviolet light for erasure is a high intensity UV light for an extended period of time.
7258W X sec/cm2 is the recommended maximum dosage.
wavelength of2537 Angstroms for a minimum dose (UV
3-101
~~ucroR ==============================
CY7C271
. CY7C274
.

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE SUPPLY VOLTAGE
VI.
1.6 1.2r--------r---------, 1.2
~
Q
....
!::!
-J
<
:2
II::
0
z
1.4
1.2
1.0
0.8 V
/
/
1.11-------+----------j
1.0 I-------'~------_l
0.91-------+------""0..---1
1.0
0.8
0.6
- --- --
0.6
V Tt:J:;: 0.8 ~ ______-l.-_ _ _ _ _ _ _ _- - - ' 0.4
TA=~50C
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(OC) SUPPLY VOLTAGE (V)
TYPICAL ACCESS
NORMALIZED ACCESS TIME OUTPUT SOURCE CURRENT TIME CHANGE
VI. TEMPERATURE vs. VOLTAGE vs. OUTPUT LOADING
1.6 60 30.0
....:2
1.4
<-
.s
I-
50 i\. 25.0
V
/
""'"
i=
en ....
Z
II:: ..c:
~ II:: 40 20.0
1.2
/
-
~
8<
....0
0
....0 30 J 15.0
1.0 II::
~
~ /V
~
~
< ~ 0 20 ....
-J
Q 10.0
"
(I)
:2
a::
0 0.8
I-
~
Q. 10 5.0
",V
z TA =25O C
V
'"
I-
~
0 Vee = 4.5V
0.6 o o
-55 25 125 o 1.0 2.0 3.0 4.0 o 200 400 600 800 1000
AMBIENT TEMPERATURE(OC) OUTPUT VOLTAGE (V) CAPACITANCE(pF')
OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE
175
.s<-
I-
150
....z 125
II::
II::
~ 100 ./
0
~
z 75 V
iii
I-
~
50 /" Vee = 5.0V
TA =25 0 C -
~ /1' I
~ 25
0
o /
o 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)

0102-13
3-102
FAIL
FAIL
Vee =5.0V. Vpp =12.5V.1 at addr 8c data
FAIL
PASS
0102-14
Note:
For main array only. Sync. and ALE bits use 200 50 ,""S pulses.
3-103
CY7C271
5'n~NDUcrOR=====================================================================
.
CY7C274
Parameters Description Min. Max. Units

Power Supply Voltage
Veep 4.75 5.25 V
During Programming
Input High Voltage
VIHP 3.0 Veep V
During Programming
Input Low Voltage
VILP 0.4 V
During Programming

Parameters Description Min. Max. Units
tAS Address Setup Time to PGM/VFY 1.0 ,."s
tAH Address Hold Time from PGM/VFY 1.0 ,."S
tos Data Setup Time to PGM 1.0 ,."S
tOH Data Hold Time PGM 1.0 ,."S
tpp Program Pulse Width 0.1 10 ms
tR,F Vpp Rise and Fall Time 1.0 ,."S
tov Delay to Verify 1.0 ,."S
tvo Verify to Data Out 1.0 ,."S
tvp Verify Pulse Width 5.0 ,."S
toz Verify to High Z 1.0 ,."S
tps Verify Setup/Hold to Program 1.0 ,."S
7C271 Programming PinOut 7C274 Programming PinOut
Ag Vee vpp vee

As A10 A12 A14
A7 A11 A7 A13
As A12 As AS
As A13 As Ag
A4 A14 A4 A11
A3 Vpp A3 VFY
A2 PGM A2 A10
A1 VFY A1 PGM
Ao ~ Ao 07
DO Os DO Os
01 Os 01 Os
O2 04 O2 04
Vss 03 GNO 03
0102-8 0102-12
3-104
CY7C271
5n - :-
~~~~NDUcrOR==================================================================
Read Mode Table
CY7C274
Part Vpp PGM VFY

7C271 VIL VIR VIL
7C274 VIL VIL VIL

Reading PROMs
Below are timing diagrams for the final read of the PROMs. Use 1 JLs timing for pulse widths and overlaps.
ADDRESS _ _ _ _ -'X"'__NEW_A_D_D_RE_S_S_ _ __
DATA _ _ _ _ _ _ _ _ _ _ _ _~
0102-15
V1H ----- -----~ ,.---------~ ,-----------

V
1L
~Q.-:.AJj X X
~
Vpp - - - - - - ----
V1L -----
Vpp
~ -
-- ----
--
- -
-j tos
- tpp
-
I-- t AH
tOH r-
-
1's
-+ "--
tF
O's
I-
~ toz~
V1H ----- r--
V ___
1L
VI'!. --------------------- -------------- ----
I--tOY typ
~
------------------- \. J
I - tps-J-- tyO- -J ~tps
0102-9
CY7C271-45WC W22
CY7C274-45PC P15
CY7C274-45WC W16
CY7C271-55WC W22
CY7C274-55PC P15
CY7C274-55WC W16
CY7C271-55WMB W22
CY7C271-55LMB L55
CY7C271-55QMB Q55
CY7C274-55DMB D16
CY7C274-55WMB W16
CY7C274-55LMB L55
CY7C274-55QMB Q55
3-105
CY7C271
Wn CYPRESS
.SEMlCONDUcroR
CY7C274
==============================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
10Z 1,2,3
Icc 1,2,3
ISB 1,2,3
tAA 7,8,9,10,11
tACS[1] 7,8,9,10,11
tOE [2] 7,8,9,10,11
tACE 7,8,9,10,11
Notes:
1. 7C271 only.
2. 7C274 only.
3-106
CY7C277
CY7C279
CYPRESS
SEMICONDUCTOR Reprogrammable 32,768 X 8
Registered PROM
Features
Windowed for reprogrammability Programmable address latch Slim 300 mil, 28-pin plastic or
CMOS for optimum enable input hermetic DIP
speed/power Programmable synchronous or 5V 10% Vee, commercial and
High speed asynchronous output enable military
- 40 ns max setup (7C277) TTL compatible I/O
- 20 ns clock to output Onchip edgetriggered registers Direct replacement for bipolar
Low power EPROM technology, 100% PROMs
- 660 mW (commercial) programmable Capable of withstanding greater
- 715 mW (military) than 2000V static discharge

CY7C277 CY7C279
14 Ag Vce A9 vcc
7 A10
A10 A8
An All
Os
AS A12 Au
As A13 AU
s
A14 A4
4 ALE A3
A2 CP
3 E/Es CE
7
2 0 Os Os
1 s 1 5
1
2 2 4
GNO GND 3
00
0136-2 0136-3
LCCPinout LCCPinout
.r-~.t$J.~li
:;! 302~
0
As 5 4 3 2 32 31 A12
As 6 28 A 13 AS 6 28 A13
7 A4 7 27 Au
0
A4 27 Au
A3 8 26 ALE A3 8 26 NC
E/ES --=d,.",.,.,,...fjj:'(j:C;;;""QJ A2 9 25NC A2 9 25 ALE
CP Al 10 24 CP 24 CS
Al 10
AO 11 23 E/Es AO 11 23 CE
0136-1 NC 12 22 07 NC 12 22 7
00 13 21 Os 0 0 13 21 Os
,14 15 16 17 18 19 20 14 15 16 17 18 19 20
- N C O ' " ..,.. It') -NC(J~.1t')
00(5Z000 o0t5 z o o o
0136-4 0136-5
Selection Guide
7C27945 7C27740 7C27955 7C27750
Maximum Setup Time (ns) 40 50
Maximum Clock to Output (ns) 20 25
Maximum Standby Commercial 30 30
3-107
CY7C277
Wn .
~~DUcrOR ==========================================================~~~~~
Product Characteristics
CY7C279
The CY7C277 and CY7C279 are high performance 32,768 asynchronous. When the asynchronous mode is selected,
word by 8 bit CMOS PROMs. When deselected, the 7C279 the E/Bs pin is sampled continuously and operates as an
automatically powers down into a low power standby output enable. If the synchronous mode is selected, then
mode. The 7C277 and the 7C279 both are packaged in the the EIBs pin is sampled only when CP is HIGH. Enablin~
slim 28 pin 300 mil package. The ceramic package may be the outputs in this mode is accomplished by bringing the Es
equipped with an erasure window; when exposed to UV pin LOW and pulsing the CP HIGH to latch the output
light, the PROM is erased and can then be reprogrammed. enable state. The 7C277 also provides a programmable bit
The memory cells utilize proven EPROM floating gate to enable the ADDRESS LATCH ENABLE (ALE) pin. If
technology and byte-wide algorithms. this bit is not programmed, then the device will ignore the
The CY7C277 and CY7C279 offer the advantages of lower ALE pin. If the ALE function is selected, the user may
power, reprogrammability, superior performance and high define the polarity of the ALE signal with the default being
programming yield. The EPROM cell requires only 12.5V a positive ACTIVE signal.
for the supervoltage and low current requirements allow On the 7C279, address registers are provided to easily in-
for gang programming. The EPROM cells allow for each terface with the Cypress 7C601 and other microprocessors
memory location to be 100% tested, as each location is that clock their addresses. A programmable bit is provided
written into, erased, and repeatedly exercised prior to en- to select between Latched and Registered address inputs.
capSUlation. Each PROM is also tested for AC perform- The default is registered inputs, which will sample the ad-
ance to guarantee that after customer programming the dress on the RISING EDGE of ALE and latch the address
project will meet DC and AC specification limits. into the address register. The Latched address option will
On the 7C277, the outputs are pipelined through a master- recognize any address changes while the ALE pin is
slave register. On the rising edge ofCP, data is loaded into ACTIVE and latch the address into the address registers
the 8 bit edge triggered output register. The EIBs provides on the FALLING EDGE of ALE. Ifthe latched address
a programmable bit to select between asynchronous and option is selected, then another programmable bit is pro-
synchronous operation. The default condition is vided for the user to select the polarity that will define
ALE ACTIVE, with the default being positive polarity.
Maximum Ratings
Storage Temperature ..... '" ....... -65C to + 150"C Static Discharge Voltage ........... " ........ >2001V
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
Operating Range
Range Vee
DC Input Voltage ................... -3.0Vto +7.0V Commercial OC to + 70C 5V 1O%
DC Program Voltage (Pins 7, 18,20) ............. 13.0V Military [2] -55C to + 125C 5V 10%
UV Erasure .......................... 7258 Wsec/cm2
7C27740 7C27750
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min.,IOH = -2.0 rnA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 V
VIR Input HIGH Level[4] 2.0 Vee 2.0 Vee V
VIL Input LOW Level[4) 0.8 0.8 V
IIX Input Leakage Current GND S; VIN S; Vee -10 +10 -10 +10 IJ-A
VeD Input Clamp Diode Voltage Note 5
loz Output Leakage Current VOL S; VOUT S; VOH, Output Disabled[6] -40 +40 -40 +40 IJ-A
los Output Short Circuit Current Vee = Max., VOUT = 0.OV[7] -20 -90 '-20 -90 rnA
Vee = Max., VIR = 2.0V Commercial 120 120
lec Power Supply Current rnA
ISB[9] Vee = Max., CS ~ VIH Commercial 30 30

Standby Supply Current rnA
3108
CY7C277
(in
. CY7C279
~NDUcrOR =====================================================================
Capacitance [8]
pF
Output Capacitance VCC = 5.0V 8
COUT
Notes:

1. The 7C279 only has a standby mode. 6. For devices using the synchronous enable,the device must be clocked
2. TA is the "instant on" case temperature. after applying these voltages to perform this measurement.
3. See the last page of this specification for Group A subgroup testing 7. For test purposes, not more than one output at a time should be
information. shorted. Short circuit test duration should not exceed 30 seconds.
4. These are absolute voltages with respect to device ground pin and S. Tested initially and after any design or process changes that may
include all overshoots due to system and/or tester noise. Do not at- affect these parameters.
tempt to test these values without suitable equipment (see Notes on
Testing).
5. The CMOS process does not provide a clamp diode. However, the
CY7C277 and CY7C279 are insensitive to - 3V dc input levels and
- SV undershoot pulses ofless than 10 ns (measured at 50% point).
Switching Characteristics Over Operating Range[S]

7C277-40 7C277-S0
Min. Max. Min. Max.
tAL Address Setup to ALE Active 10 10 ns
tLA Address Hold from ALE Inactive 10 15 ns
tLL ALE Pulse Width 10 15 ns
tSA Address Setup to Clock HIGH 40 50 ns
tHA Address Hold from Clock HIGH 0 0 ns
tSES Es Setup to Clock HIGH 15 15 ns
tHES Es Hold from Clock HIGH 10 10 ns
tCO[14] Clock HIGH to Output Valid 20 25 ns
tpwc Clock Pulse Width 20 20 ns
tLZC Output Low Z from Clock HIGH 20 30 ns
tHZC[l4,9] Output High Z from Clock HIGH 20 30 ns
tLZE Output Low Z from E LOW 20 30 ns
tHZE[15,9] Output High Z from E HIGH 20 30 ns
3-109
CY7C277
5A~~NDUcroR =====================================================================
Switching Characteristics Over Operating Range[8] (Continued)
CY7C279
7C27945 7C27955
Min. Max. Min. Max.
tAA[12] Address Access to Output Valid 45 55 ns
tHZCS Chip Select Inactive to High Z 30 30 ns
tACS Chip Select Inactive to Output Valid 30 30 ns
tAR Address Register Setup to ALE Active 10 10 ns
tRA Address Hold from ALE Active 10 10 ns
tADH Data Hold from ALE Active 5 5 ns
tpu Chip Enable Active to Power Up 0 0 ns
tpD Chip Enable Inactive to Power Down 50 60 ns
tOH[12] Output Hold from Address Change 0 0 ns
tPWA Address Register Pulse Width 20 30 ns
Notes:
9. tHZCS and tHZE are tested wtih the load shown in Figure 1h. Tran- 14. Applies only when the synchronous (Es) function is used.
sition is measured at steady state high level - 500 mV or steady state 15. Applies only when the asynchronous (E) function is used.
low level + 500 mV on the output from the 1.5V level on the input. 16. See Figure 1a for all switching characteristics except tHZCS and
10. These parameters apply to the 7C277 only. tHZE
11. These parameters apply to the 7C279 only. 17. See the last page of this specification for Group A subgroup testing
12. tAA and toH apply only when the latched mode is selected. information.
13. Tests are performed with rise and fall times of 5 ns or less. 18. All device test loads should be located within 2" of device outputs.
AC Test Loads and Waveforms[9, 16, 18]

R1 R1
500.0. 500.0.
(658.0. MIL) (658.0. MIL)
3.0V---~~--"""'\I
GND
R2 R2
30pF' 333.0. 5pF' 333.0.
TINCLUDING (403.0. MIL) TINCLUDING (403.0. MIL) 0136-6
...LJIG AND
- SCOPE -= ...L JIG AND
- SCOPE -= 0136-8
Figure 2
0136-7
Figure la Figure Ib
200.0.
OUTPUT o---"'NV--O 2.00V COMMERCIAL
250.0.
OUTPUT o---"'NV--O 1.90V MILITARY
0136-14
3110
e-:z CYPRESS
_~ICONDUcroR ====================================================================
CY7C277
CY7C279

1.6 1.2 1.2
---r--.
LoJ
~
1.4 i= "--
0
u
.9
LoJ 1.2 / u
.9
0
LoJ
1.1
en
en
LoJ
(,)
(,)
1.0
II
N
:i
oC(
~ 1.0 ./ N
:i
oC(
~
1.0
oC(
0
LoJ
N
0.8
V
0:: 0::
0 0 :i
z z 0.9
oC(
~ 0.6
0.8 a::
0.6
V TA =25OC
f=MAX.
0.8 ' - - - - - - ' - - - - - - - '
0
z
0.4
TA =25OC
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
1.6 60 30
1 I
1.4
50
" 25
'"'" /
~
Z
u LoJ
------ ----
.9 ~ 40 ";j' 20
.5
0
LoJ
N
:i
1.2 ;:)
(,)
LoJ 30 +'~ 15 /
'~ /r
oC( (,)
~ 1.0 0:: ~
a:: 5en
0 20 ~ 10
"" .,IV
z
0.8
10 ....... 5 TA =25C
0.6
-55 25 125
o
o 1.0 2.0 3.0 4.0
o
o
/ 200 400
Vcc =4.5V
600 800 1000
AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V) CAPACITANCE (pF')
OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE
175
<- 150
.5
~
zLoJ 125
a::
a:: 100
::.
~
(,)
:.:
z 75 ~
iii
~
::.
50 /'
a..
~
::. 25 / Vcc =5.0V-
0
o V TA = 25C
o 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)

0136-15
3-111
CY7C277
fm . CYPRESS
S~IOO~UcrOR==========================================================~~~~
CY7C279
FAIL
FAIL
Vee =5.0V. Vpp =12.5V.1 st addr Be data
PASS
0136-16
Note:
For main array only. Sync. and ALE bits use 200 50 ,...,S pulses.
3-112
CY7C277
~RRSS CY7C279
~~~O~~OR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Timing Diagram (7C277)
ALE
ES _ _ _ _ _ _- '
CP

0136-9
Timing Diagram (7C279)
VeeCURRENT
SUPPLY
cr
=e % ~
so
~
___________________________________________
5}t:0%
'Hles) f HIGH Z
CS
0-7 ---HI~GH-Z--~(l-----$---t-AD-J 'all;.'f!Ur~tA ~J.:. ___

Ao-A 14 _ _ _ _ _.JX X"'__ X"'_____ -.J
~tAR~;~~
ALE _ _ _ _ _ _...J 1 '""_-,,I-----------------------
0136-10
Note:
ALE is shown with positive polarity.
Erasure Characteristics All of the programming elements are EPROM cells and
are in an erased state when they are shipped. This erased
Wavelengths of light less than 4000 Angstroms begin to state manifests itself differently in each case. The erased
erase the 7C277 and 7C279. For this reason, an opaque state for the synchronous function is ASYNCHRONOUS
label should be placed over the window if the PROM is mode. The erased state for the ALE function is: Registered
exposed to sunlight or fluorescent lighting for extended pe- inputs on the 7C279 and no ALE function on the 7C277.
riods of time. In the erased state, the memory location contains neither a
The recommended dose for erasure is ultraviolet light with one nor a zero. The erased state of the device can be veri-
a wavelength of 2537 Angstroms for a minimum dose (UV fied by using the BLANK CHECK ONES and BLANK
intensity X exposure time) of25 Wsec/cm 2. For an ultra- CHECK ZEROS function (see mode table).
violet lamp with a 12 mW/cm2 power rating the exposure To choose the ALE function, the ALE bit must be pro-
time would be approximately 45 minutes. The 7C277 and grammed. This is done by raising A9 to Vpp, taking A14
7C279 need to be within 1 inch of the lamp during erasure. LOW and pulsing PGM LOW. When the ALE function is
Permanent damage may result if the PROM is exposed to chosen, it is active with positive polarity. To choose nega-
high intensity UV light for an extended period of time. tive polarity, A9 must be at Vpp, A14 must be raised
7258 Wsec/cm2 is the recommended maximum dosage. HIGH and PGM must be pulsed LOW. The 7C277 comes
with a synchronous option. To choose this option, the SYN
Device Programming bit must be programmed. This is done by taking A14 to
There are several independent programmable functions Vpp and pulsing PGM LOW.
contained in the 7C277 and 7C279 CMOS 32K x 8 regis- To verify these special bits, A14 must be at Vpp and the
tered PROM. Both devices have the 32K x 8 array and a Vpp must be held LOW with PGM held HIGH and CE
programmable ALE function. The 7C~7~lso contains a LOW. The ALE bit is read on 1/01, the polarity bit is read
programmable synchronous function (EIBs). on 1/02 and the synchronous bit is read on 1/00.
3-113
CY7C277
5A~NDUcrOR =====================================================================
.

CY7C279
Table 1
Vpp[1] Programming Voltage 12.0 13.0 V
Veep Supply Voltage 4.75 5.25 V
VIHP Input High Voltage 3.0 Veep V

Table 2
tpp Programming Pulse Width 0.1 10 ms
tAS Address Setup Time to PGMIVPY 1.0 JJ.s
tos Data Setup Time to PGM 1.0 JJ.s
tAH Address Hold Time from PTIMIVPY 1.0 JJ.s
tOH Data Hold Time from PGM 1.0 JJ.s
tR. tF[3] Vpp Rise and Fall Time 1.0 JJ.s
tvo Verify to Data Out 1.0 JJ.s
tov Delay to Verify 1.0 JJ.s
toz Verify HIGH to High Z 1.0 JJ.s
tps VFY Setup/Hold to PGM 1.0 JJ.s
Notes:
1. Vccp must be applied prior to Vpp.
3-114
CY7C277
5Ii~~UcrOR =====================================================================
.
Mode Selection
CY7C279
Mode Table
Ag
CP7C277 E/Es7C277 Ao-As Data
Read Al4 ALE
CS7C279 CE7C279 AIO-AI3
Mode Ao-As
Program Ag Al4 Vpp PGM VFY Data
AIO-AI3

Read A A VIL VIH VIL A Out
Program A A Vpp VIL VIH A In
Program SYN Bit X Vpp Vpp VIL VIH X X
Program ALE Bit Vpp VIL Vpp VIL VIH X X
Program ALE Low Polarity Vpp VIH Vpp VIL VIH X X
Program Verify[l] A A Vpp VIH, VIL VIL A Out
Program Inhibit A A Vpp VIH VIH A X
Blank Check 0, 1[2] A A VIH, VIL Vpp Vpp A Out
Verify Special Bits X Vpp VIL VIH VIL X Out
Notes:
1. During program verify PGM must first be held HIGH to verify ones 2. To blank check zeros, Vpp is held to VIH and all ones should be read
and then LOW to verify zeros. on the outputs. To blank check ones, Vpp is held to VIL and all zeros
should be read on the outputs.
7C277/7C279
Ag Vee
As A 10
A7 All
A6 A12
As A 13
Aol. A14
A3 Vpp
A2 PGM
Al VFY
Ao 7
DO 06
1 Os
O2 04
GNO 03
0136-12
Figure 4. Programming Pinout
X X
~
Vpp ------ -----
~________:J 'os -"-

Vpp tpp
-
t AH -
V1L -----
V1H ------
__ I- tOHj- l- tf"
I
I/O 1's O's
V1L ------ ----------------
~ tDzH
V1H -----
I~
V1L ___ VTL ------------------- ------ ~
---------------- ~tDV tvp
V1H -----
V1L --!~~- -------------------~ I \. / -
I-- tps--l-- tVD- -J -tps
0136-13
Figure S. PROM Programming Waveforms
3115
CY7C277
WA . CY7C279
~~UcrOR================================================================
CY7C277-40WC W22
CY7C279-45PC P21
CY7C279-45 WC W22
55 CY7C277-50 PC P21 Commercial
CY7C277-50WC W22
CY7C279-55PC P21
CY7C279-55 WC W22
CY7C277-50WMB W22
CY7C277-50LMB L55
CY7C277-5OQMB Q55
CY7C279-55DMB D22
CY7C279-55WMB W22
CY7C279-55LMB L55
CY7C279-55QMB Q55
3-116
CY7C277
fill~NDUcrOR================================================================
.
CY7C279

DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
ISB[ll] 1,2,3
Device Parameters Subgroups
7C277 tSA 7,8,9,10,11
tHA 7,8,9,10,11
tco 7,8,9,10,11
7C279 tAR 7,8,9,10,11
tRA 7,8,9,10,11
tDHA 7,8,9,10,11
Note:
11. These parameters apply to the 7C279 only.
3-117
CY7C281
CY7C282
CYPRESS
SEMICONDUCTOR 1024 x 8 PROM
Features
CMOS for optimum speed/ Capable of withstanding low current requirements allow for
power > 1500V static discharge gang programming. The EPROM cells
allow for each memory location to be
High speed Product Characteristics
- 30 ns (commercial) tested 100%, as each location is written
- 45 ns (military) The CY7C281 and CY7C282 are high into, erased, and repeatedly exercized
performance 1024 word by 8 bit CMOS prior to encapsulation. Each PROM is
Low power PROMs. They are functionally identi- also tested for AC performance to
- 495 mW (commercial) guarantee that after customer program-
- 660 mW (military) cal, but are packaged in 300 mil and
600 mil wide packages respectively. ming the product will meet DC and
EPROM technology 100% The CY7C281 is also available in a 28 AC specification limits.
programmable pin leadless chip carrier. The memory Reading is accomplished by placing an
Slim 300 or standard 600 mil cells utilize proven EPROM floating active LOW signal on CSl and CS2,
DIP or 28 pin LCC gate technology and byte-wide intelli- and active HIGH signals on CS3 and
gent programming algorithms. CS4. The contents of the memory loca-
5V 10% Vee, commercial and tion addressed by the address lines
military The CY7C281 and CY7C282 are plug-
in replacements for bipolar devices and (Ao-A9) will become available on the
TIL compatible I/O offer the advantages of lower power, output lines (00-07).
Direct replacement for bipolar superior performance and program-
PROMs ming yield. The EPROM cell requires
only 13.5V for the supervoltage and

A7 Vee
As As
A5 Ag
ROW 64 x 128
DECODER PROGRAMMABLE 8 x 1 OF 16
A4 CS,
10F64 ARRAY MULTIPLEXER A3 CS2
A2 CSa
A, CS4
Ao 07
00 Os
0, 05
02 04
COLUMN GND 03
DECODER
1 OF 16 0009-2
II) (D ...... O
o0 co en
oCoCoCz>oCoC
-4 '3 2111282726 ....
A4 5 '-' 25J~1
CS;-~IL. ___ A3 6 24 CS 2
CS2 A2
AI
7
8
23 CS 3
22 CS 4
eS3
C5.t Ao 9 21 NC
NC 10 20 07
0009-1 00 11 19 06
" ~13~~~17~
... NO U tf) .... It)
o 0 ~ Zoo 0 0009-3
Selection Guide
7C281-30 7C281-45
7C282-30 7C28245
3-118
CY7C281
fin .
Maximum Ratings
~NDUcroR =====================================================================
CY7C282
Storage Temperature ..... , '" ., .... -65C to + 150"C Static Discharge Voltage ..................... > 1500V

Range Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OCto + 70C 5V 1O%
DC Program Voltage (Pins 18,20) ............... 14.0V Military [1] - 55C to + 125C 5V 10%

7C281-30 7C281-45
Parameters Description Test Conditions 7C282-30 7C282-45 Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vcc = Min., IOH = - 4.0 mA 2.4 2.4 V
VOL Output LOW Voltage Vcc = Min.,IOL = 16.0mA 0.4 0.4 V
VIH Input HIGH Level[3] 2.0 2.0 V
VIL Input LOW Level[3] 0.8 0.8 V
IIX Input Current GND s VIN s Vce -10 +10 -10 +10 ILA
Input Diode Clamp
VCD Note 4 Note 4
Voltage
Ioz Output Leakage Current VOL s VOUT s VOH, Output Disabled -40 +40 -40 +40 ILA
Output Short
los Circuit Current [5]
Vcc = Max., VOUT = GND -20 -90 -20 -90 rnA
lec
Power Supply Vcc = Max., l Commercial 100 90 mA
Current lOUT = OmA
I Military 120 mA
Capacitance [6]
pF
Notes:
1. TA is the "instant on" case temperature. 4. The CMOS process does not provide a clamp diode.
2. See the last page of this specification for Group A subgroup testing However, the CY7C281 & CY7C282 are insensitive to - 3V dc input
information. levels and - 5V undershoot pulses of less than 10 ns (measured at
3. These are absolute voltages with respect to device ground pin and 50% point).
include all overshoots due to system and/or tester noise. Do not at- 5. For test purposes, not more than one output at a time should be
tempt to test these values without suitable equipment. shorted. Short circuit test duration should not exceed 30 seconds.
6. Tested initially and after any design or process changes that may
3-119
CY7C281
5A~NDUcrOR =======================================================================
. CY7C282
Switching Characteristics Over the Operating Range[2, 71

CY7C28130 CY7C281-45
Parameters Description CY7C282-30 CY7C282-45 Units
Min. Max. Min. Max.
tHZCS Chip Select Inactive to High Z[S] 20 25 ns
tACS Chip Select Active to Output Valid 20 25 ns

Rl250n Rl250n
5Vo---------~~~ 5V 0-------"""',...,......, 3.0V------Jtoo----"""""-
OUTPUT~----_1-------. OUTPUT C>------..---...
GND -----Oil
'NCLUD'NGI 30 pF
JIG AND
SCOPE
R2
167n INCLUDING
JIG AND
SCOPE
I 5 pF
R2
167n
s:5ns

S:5ns
0009-6
0009-4
Figure 18 Figure 1b
Equivalent to: THEVEN1N EQUIVALENT

100n
..
OUTPUT O~---~."-'~"-' "'.---o 2.0 V
0009-5
:~t~~ss ______ ~(. _________________________________________________________

~J~~
CS3.CS4 ------+-----------~
CSlo~2 _ _ _ _ _; -_ _ _ _ _ _ _ _ _---'J~~ _ _ _ _ _JJI\~ ~t ~( _ _ _ _ _ _ _ _ _ _ _ __
00-0 7 _ _ _ _ _ _ r---
___ ~------r----'tH_Z-CS-}""l-_-:-:-:-:-:--f------tA_cs_@+""~~~~~..J _ _ _ _ _ _ __
0009-7
Notes:
7. Test conditions assume signal transition times of 5 ns or less. timing S. tHzcS is tested with load shown in Figure lb. Transition is measured
reference levels of 1.5V. output loading of the specified loUIoH and at steady state High level + 500 m V or steady state Low level + 500
loads shown in Figure 1a. lb. m V on the output from the 1.5V level on the input.
3120
CY7C281
(fA~~NDUcrOR ====================================
.
.
CY7C282

1.6 1.2r------....--------. 1.2

w ~
1.4 :e ~
/ u ~ 1.0
" '"
u
.:: .:: ~
0 cw w
w
1.2 u
c~
/
N N
:::i :::i 0.8
<l <l w
:E 1.0 :E N
a: a:
V
:::i
a ~ <l
z
~ 0.6
0.8
~
0.6
V TA =25C
f=MAX. 0.80L..-_ _ _ _....L..._ _ _ _ _..-I 0.4
TA i 25'C
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPL V VOLTAGE (V) AMBIENT TEMPERATURE (OC) SUPPLY VOLTAGE (V)
1.6 60 30.0
~ ~
w
:E 1.4 .s 50 25.0
~
~
I-
Z
w
a: 40 ~ :g 20.0 /
- '"'"
a:
u
u
<l
@
1.2
::::I
u
w 30
'"
~ 15.0 /
'" /'t'
u
N 1.0 a:
::::I
:;
:::i
<l
~ aen 20 ~ 10.0
"'"
:E
a:
az 0.8
I-
::::I
~
10 5.0
,IV TA = 25C
Vee =4.5 V
I-
0.6
-55 25 125
::::I
a
o
o 1.0 2.0 3.0 4.0
0.0 V
o 200 400 600 800 1000
AMBIENT TEMPERATURE ec) OUTPUT VOLTAGE (VI CAPACITANCE (pF)
OUTPUT SINK CURRENT A7 Vee

vs. OUTPUT VOLTAGE A6 As
175
As Ag
~ 150 A4 CS,
!
I- ",...- ~ A3 Vpp (CS2)
zw 125
a: ~ A2 VFY (CS3)
a:
::::I 100 / A, PGM (CS4)
U
~
z
iii
75 / Vee =5.0 V
Ao
Do
07
I-
::::I 50 / TA = 25C
0,
06
05
I
~
I-
::::I 02 04
a 25
o
V GNO 03
0009-9
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)
Figure 3. Programming Pinout
0009-8
3-121
CY7C281
Q ..
~~UcrOR==================================================================
CY7C282
START
Vccp =5.0 V. Vpp =13.5
DEVICE BAD

Vcc 5.0 V ~...;..;;--...
'----....
0009-10
The CY7C281 and CY7C282 programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.
Typical programming time for a byte is less than 2.5 msec. The use of EPROM cells allows factory testing of programmed cells, measurement of data
retention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 msec which will then be followed by a
longer overprogram pulse of 24 (0.1) (X) msec. X is an iteration counter and is equal to the NUMBER of the initial 0.1 msec pulses applied before
verification occurs. Up to four 0.1 msec pulses are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verification is performed at Vee = 5.0. When all bytes have been programmed all bytes should be
compared (Read mode) to original data with Vee = 5.0V.
3-122
CY7C281
5A~~~UcrOR=======================================================================
..
Programming Information Blank Check

CY7C282
The 7C281 and 7C2821K x 8 CMOS PROMs are imple- A virgin device contains neither ones nor zeros because of
mented with a differential EPROM memory cell. The the differential cell used for high speed. To verify that a
PROMS are delivered in an erased state, containing neither PROM is unprogrammed, use the two blank check modes
"Is" nor "Os". This erased condition of the array may be provided in Table 3. In both of these modes, address and
assessed using the "BLANK CHECK ONES" and read locations 0 thru 1023. A device is considered virgin if

"BLANK CHECK ZEROS" function, see below. all locations are respectively "Is" and "Os" when addressed
in the "BLANK ONES AND ZEROS" modes .
Because a virgin device contains neither ones nor zeros, it
is neccessary to program both ones and zeros. It is recom-
mended that all locations be programmed to ensure that
Table 1
Vpp Programming Voltage [I] 13.0 14.0 V
VIHP Input HIGH Voltage 3.0 V
VILP Input LOW Voltage 0.4 V
VOH Output HIGH Voltage[2] 2.4 V
VOL Output LOW Voltagd 2] 0.4 V

Table 2
tpp Programming Pulse Width[3] 100 10,000 JJ.s
tAS Address Setup Time 1.0 JJ.s
tos Data Setup Time 1.0 JJ.s
tAH Address Hold Time 1.0 JJ.s
tOH Data Hold Time 1.0 JJ.s
tR, tp Vpp Rise and Fall Time[3] 1.0 JJ.s
tvo Delay to Verify 1.0 JJ.s
tov Verify Data Valid 1.0 JJ.s
toz Verify to High Z 1.0 JJ.s
Notes:
3-123
CY7C281
5A .
Mode Selection
~~~~~~==~~~~~~~~~~~~==========~==============
CY7C282
Table 3
Pin Function
Read or Output Disable CS4 CS3 CSl CSt Outputs
Mode
Other PGM VFY Vpp CSt (9-11,13-17)
Pin Number (18) (19) (20) (21)
Read VIH VIH VIL VIL Data Out
Output Disable[4] X X VIH X HighZ
Output Disable[4] X VIL X X HighZ
Output Disable[4] VIL X X X HighZ
Output Disable[4] X X X VIH HighZ
Program VILP VIHP Vpp VILP Data In
Program Verify VIHP VILP Vpp VILP Data Out
Program Inhibit VIHP VIHP Vpp VILP HighZ
Intelligent Program VILP VIHP Vpp VILP Data In
Blank Check Ones Vpp VILP VILP VILP Ones
Blank Check Zeros Vpp VIHP VILP VILP Zeros
Notes:
4. X = Don't care but not to exceed Vee + S%. S. During programming and verification, all unspecified pins to be at
VILP
Programming Sequence lK x 8
18, 19,20, and 21 at VIH. Per Figure 5 take pin 20 to Vpp. that fails to verify causes the device to be rejected.
The device is now in the program inhibit mode of operation If the intelligent programming technique is used, the pro-
with the output lines in a high impedance state; see Tables gram pulse width should be 100 J.LS. Each location is ulti-
one byte of data. Repeat this for each location to be pro- up to and including 4 times. When the location verifies, one
grammed. additional programming pulse should be applied of dura-
If the brute force programming method is used, the pulse tion 24 X the sum of the previous programming pulses
width of the program pulse should be 10 ms, and each before advancing to the next address to repeat the process.
PROGRAM
\+-_ _ _ _ PROGRAM------t_---VERIFY _ _ _+i"I--_OT_H""\ER ~BYTES

~~---
~~ ~~~u .
VILP--- ---..."I------------""-t----------I'---~ . ~---
VIHP - - -
DATA
VILP - - -
------0(
Vpp---
PROGRAMMING
VOL T AGE 'PIN 201
VIHP---
VILP---
VILP - - -
s
VILP - - -
0009-11
3-124
CY7C281
(in~~UcrOR==~~~~~~~~========================~==~==~====~====
. CY7C282
30ns CY7C281-30PC P13 Commercial
CY7C282-30PC Pll

CY7C281-300C 014
CY7C281-30LC L64
CY7C282-300C 012
45 ns CY7C281-45PC P13 Commercial
CY7C282-45PC Pll
CY7C281-450C 014
CY7C281-45LC L64
CY7C282-450C 012
CY7C281-45LMB L64
CY7C282-450MB 012
3-125
~
CY7C281
. CY7C282
. ~UQOR==========================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
tAA 7,8,9,10,11
tACS 7,8,9,10,11
CY7C285
CYPRESS
Reprogrammable Fast
Column Access
Features Product Characteristics
CMOS for optimum speed/ The CY7C285 and the CY7C289 are The CY7C285 and CY7C289 offer the
power high performance 65,536 by 8 bit advantage oflow power, superior per-
Windowed for reprogrammability CMOS PROMs. The CY7C285 is formance and programming yield. The
available in a 28-pin 300 mil package. EPROM cell requires only 12.5V for
Unique fast column access It features a unique fast column access the supervoltage and low current re-
- 30 ns tAA (commercial) feature which will allow access times as quirements allow for gang program-
- 35 ns tAA (military) fast as 30 ns for each byte in a 64-byte ming. The EPROM cells allow for each
WAIT signal page. There are 1024 pages in the de- memory location to be 100% tested,
vice. The access time when changing with each location being written into,
Chip Select Decoding pages will be 75 ns. In order to easily erased and repeatedly exercised prior
EPROM technology, 100% facilitate the use of the fast column ac- to encapsulation. Each PROM is also
programmable cess feature, a WAIT signal will be tested for AC performance to guaran-
generated to advise the processor of a tee that after customer programming
5V 10% Vee, commercial and
page change. The WAIT signal may be the product will meet DC and AC
military
programmed as either active HIGH or specification limits.
TTL compatible I/O active LOW. The CY7C289 also incor- Reading the CY7C285 is accomplished
Slim 300 mil package porates the fast column access feature by placing an active LOW signal on the
and adds through the use of the ALE CS pin. Reading the CY7C289 is ac-
Capable of withstanding option either synchronous address reg-
> 2001 V static discharge complished by placing an active LOW
isters or asynchronous address latches. signal on the CE pin and by placing
The CY7C289 is particularly well suit- active HIGH signals on the CSt or CS2
ed to support applications using the pins as appropriate. The contents of the
CY7C601 as well as other RISC or memory location addressed by the ad-
clse microprocessors. It is available in dress lines (Ao-Ats) will become avail-
a 32-pin 300 mil package. able on the output lines (00-07).

CY7C285 CY7C289
A3
CP/ALE
GND
0146-6
LCCPinout
LCCPinout
.~-cfrj4.tIt>'cl;i
AS 5 4 3 2 ~~! 32 31 30
29
A'2
A4 6
28 All
o
A3 7 27 A'4
0
A3 7 27 A,.
NC 8 26 AU
CP/ALE 8 26 A,s
A2 9 25 NC
A2 9 25 CE
A, 10 24 CS
A, 10 24 CS,
Ao 11 23 WAIT
Ao11 23 WAIT
GND 12 22 07 GND 12 22 0 7
00 13 21 GND
14'5 16 17 18 19 20
... N N 101) ...,. \I) 10
o 0 l3 0 0 0 00146_7
0146-3
Document #; 38-00097
3-127
CY7C286
CYPRESS
Reprogrammable Registered
CMOS for optimum speedl The CY7C286 and the CY7C287 are The CY7C286 and CY7C287 offer the
power high performance 65,536 by 8 bit advantage of low power, superior per-
Windowed for reprogrammability CMOS PROMs. The CY7C286 is conformance and programming yield. The
figured in the JEDEC standard 512K EPROM cell requires only 12.5V for
High speed EPROM pinout. It is available in a 28- the supervoltage and low current re-
- tsu = 55 ns (7C287) pin, 600 mil package. Power consump- quirements allow for gang program-
- teo = 20 ns (7C287) tion on the CY7C286 will be 120 mA ming. The EPROM cells allow for each
- tAA = 60 ns (7C286) in the active mode and 40 mA in the memory location to be 100% tested,
Low power standby mode. Access time is 60 ns. with each location being written into,
- 120 mA active (7C286) The CY7C287 has registered outputs erased and repeatedly exercised prior
- 40 mA standby and operates in the synchronous mode. to encapsulation. Each PROM is also
It is available in a 28-pin, 300 mil pack- tested for AC performance to guaran-
WAIT signal age. The address setup time is 55 ns tee that after customer programming
Chip Select Decoding and the time from clock high to output the product will meet DC and AC
valid is 20 ns. Both the CY7C286 and specification limits.
EPROM technology, 100%
programmable CY7C287 are available in a CERDIP Reading the CY7C286 is accomplished
package equipped with an erasure win- ~laci~ctive LOW signals on the
5V 10% Vee, commercial and dow to provide reprogrammability. OE and CE pins. Reading the
military When exposed to UV light, the PROM CY7C287 is accomplished by placing
TIL compatible 1/0 is erased and can be reprogrammed. an active low signal on E/Es. The con-
The memory cells utilize proven tents of the memory location addressed
Slim 300 mil package (7C287) EPROM floating gate technology and by the address line (Ao-AlS) will be-
Capable of withstanding byte-wide intelligent programming al- come available on the output lines
> 2001V static discharge gorithms. (00- 0 7)'

CY7C286 CY7C287
7
8-BIT Vee A9
EDGE- o. A12 A,.
TRIGGERED
REGISTER A7 A,~
Os
As As
0. A. A11 A.
Of
03 A2 A,D A2
BE A,
2 7
I D.
I 0,
I Os
I
I
i---:-'~-==~
I
.------------------------- -.
I 00
t___ ~ ____________________________
I ~:. ~c!~e.:~~ 2~L!l_ _____ __ ________ _j
I
0151-6 0151-2
LCCPinout LCCPinout
<t(1D.t;;~;;; .t.t~.r~1i
4 3
2 !~! 32 31 329 As
.. 3 2 ::; 32 31 3029
0151-1 AS 5 AS 5 A12
A. 6 28 Ag A. 6 28 A,~
A~ 7 27 Au
A~ 7 27 All
0 0
NC 8 26 Of NC 8 26 A,S
A2 9 25 NC ~ 9 25 NC
10 AI 10 24 CP
AI 24 AID
AD 11 23 BE Ao 11 23 EIEs
GNO 12 GNO 12 22 0 7
22 07
00 13 21 GNO
14 15 16 17 18 19 20
_ N
00(50000
Q ti) .... It) CO)
o~~ O>o. . ~r!
0151-7 0151-4
3-128
CY7C291
CY7C292
CYPRESS
PROM
Features
Windowed for reprogrammability Capable of withstanding > 2000V reprogrammability, superior perform-
CMOS for optimum static discharge ance and programming yield. The
speed/power EPROM cell requires only 13.5V for
Product Characteristics the supervoltage and low current re-
High speed quirements allow for gang program-
- 35 ns (commercial) The CY7C291 and CY7C292 are high
performance 2048 word by 8 bit CMOS ming. The EPROM cells allow for each
- 35 ns (military) memory location to be tested 100%, as
PROMs. They are functionally identi-
Low power cal, but are packaged in 300 mil and each location is written into, erased,
- 330 mW (commercial) 600 mil wide plastic and hermetic DIP and repeatedly exercised prior to en-
- 413 mW (military) packages respectively. The 300 mil ce- capsulation. Each PROM is also tested
ramic DIP package is equipped with an for AC performance to guarantee that
EPROM technology 100% after customer programming the prod-
programmable erasure window; when exposed to UV
light the PROM is erased and can then uct will meet DC and AC specification
Slim 300 mil or standard 600 be reprogrammed. The memory cells limits.
mil packaging available utilize proven EPROM floating gate Reading is accomplished by placing an
5V 10% VCC, commercial and technology and byte-wide intelligent active LOW signal on CSt. and active
military programming algorithms. HIGH signals on CS2 and CS3. The
The CY7C291 and CY7C292 are plug- contents of the memory location ad-
TTL compatible I/O
in replacements for bipolar devices and dressed by the address lines (Ao-AlO)
Direct replacement for bipolar offer the advantages oflower power, will become available on the output
PROMs lines (00-07).

07
128 x 128
PROGRAMMABLE axl0F16 06 As ~1n",,1D~':i. ~~..r
ARRAY MULTI PLEXER
5 4 3 2 Ej282726
Os A4 25 A10
A3 S 24 Cs1
0
A2 23 CS 2
04 CS2 AI 22 CS 3
Ao 9 21 NC
NC 10 20 7
03
00 0 0 11 19 6
06 12131415161718
COLUMN t----------' 02 0' NO (,) ..., .... It)
ts Zooo
DECODER
10F16 1-------------' 0, 0008-3
Window available on
0008-2 300 mil cerdip only
00
C8;_--rr-.....
CS2 } - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......J
CS3-----
0008-1
Selection Guide
7C291-35 7C29150
7C29235 7C29250
Commercial 90 90
Current (rnA) Military 120* 120
L Commercial 60 60
*7C2910nly
3-129
CY7C291
5A~~UcrOR =====================================================================
.. CY7C292
Maximum Ratings
Storage Temperature ...... " ....... -65C to + 150C Static Discharge Voltage ..................... >2oo1V
(Pin 24 to Pin 12) Operating Range
Range VCC
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OCto +70C 5V 1O%
DC Program Voltage (Pins 18, 20) ............... 13 .OV Military [6] - 55C to + 125C 5V 1O%
UV Exposure ........................ 7258 Wsec/cm 2

7C291L.35, 50 7C29135,50
Parameters Description Test Conditions 7C292L.35, 50 7C292.35, 50 Units
Min. Max. Min. Max.
VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 16.0mA 0.4 0.4 V
VIH [1 I Input HIGH Voltage 2.0 Vee 2.0 Vee V
VIL[I] Input LOW Voltage 0.8 0.8 V
IIX Input Load Current GND ~ VIN ~ Vee -10 + 10 -10 +10 ,.,.A
VeD Input Diode Clamp
Note 2 Note 2
Voltage
Ioz Output Leakage GND ~ VOUT ~ Vee, -40 -40
+40 +40 ,.,.A
los Output Short Vee = Max., -20 -90 -20 -90 mA
Circuit Current[l] VOUT = GND
Icc Vee Operating Vee = Max., I Commercial 60 90 rnA
Supply Current lOUT = ornA I Military 120 rnA
*-35: 7C291 only
Capacitance [4]
pF
COUT Output Capacitance Vce = 5.0V 8
Notes:
CY7C291 and CY7C292 are msensitive to - 3V dc input levels and 5. See the last page ofthis specification for Group A subgroup testing
- 5V undershoot pulses ofless than 10 ns (measured at 50% point). information.
3-130
CY7C291
fin ~~NDUcrOR =====================================================================
CY7C292
Switching Characteristics Over the Operating Ranger 5, 7]

7C29135 7C29150
Parameters Description 7C29235 7C29250 Units
Min. Max. Min. Max.
tHzCS Chip Select Inactive to High Z[s] 25 25 ns
tACS Chip Select Active to Output Valid 25 25 ns

R1250n R1 250 n
5 V o-----~""'_..., 5V~----JV~~ 3.0 v-----L-----"'"
OUTPUTo---_t------4 OUTPUT 0---_-----.. . . GND---;r
,.5 ns ,.5 ns
R2 R2
'NCLUD'NGI 30 pF 167n 'NCLUD'NGI 5 pF 167 n 0008-6
JIG AND JIG AND Figure 2. Input Pulses
SCOPE SCOPE
0008-4
Figure 18 Figure Ib

100n
OUTPUT 0 v.~ o 2.0V
0008-5
~xxa
Ao -A 10
ADDRESS
CS 2 - CS3
0-7
CS 1
tHZCS'L NOTE 8
.....-----...;~+- NOTE 8
t 'ACS 4. . .(----
--
0008-7
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing S. tHZCS is tested with load shown in Figure 1 b. Transition is measured
reference levels of 1.5V, output loading of the specified IorJ10H and at steady state High level - 500 m V or steady state Low level + 500
loads shown in Figures la, lb. m V on the output from the 1.5V level on the input.
3131
CY7C291
511 .
~NDUcroR ==================================================~==============~
CY7C292

1.6 1.2 1.2
w ~
1.4 :::E
~
/
j: 1.0
u
~u
'"
!:
C
~
w 1.2
~
/
N
::i Q 0.8
~ w
::E 1.0 N
V
II: :J
0
z
~ 0.6
0.8
~
0.6
V TA25'C
f=MAX. 0.80'--_ _ _ _......._ _ _ _ _....1
0.4
I
TA ,25'C
4.0 4.5 5.0 5.5 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
SUPPL V VOLTAGE (V) AMBIENT TEMPERATURE ('C) SUPPL Y VOLTAGE (V)
1.6 60 30.0
w "< ~
:IE 1.4 ! 50 25.0
j:
~
w
I-
Z
w
a: 40
~ ! 20.0
/
a:
"-~ /
-
CJ 1.2
~
Q
::l
u
w 30 :
" 15.0
" '"
w u
N
:::i
1.0
~
a:
::l
!:i
~
/"
< ~ 20 10.0
~V
:::E TA =25'C
a: I-
0.8 ::l Vee =4.5 V
0 Q.
z 10 5.0
~
I-
~
::l
0
0.6 o 0.0
-55 25 125 o 1.0 2.0 3.0 4.0 o 200 400 600 800 1000
AMBIENT TEMPERATURE ('C) OUTPUT VOLTAGE (V) CAPACITANCE (pF)
OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE A7 Vee
175
A6 As
"< 150 A5 Ag
! j...--- A4 A,o
I- ~
z 125
A3 Vpp (CS,)
w
a: V-
a:
::l 100 / A2 VFY (CS2)
CJ
~
Z 75
i/ Vee =5.0V
A,
Ao
PGM
07
(CS3)
iii
I-
::l
Q.
50
J TA "'25'C Do 06
I-
::l
0 25
/ 0,
02
05
04
o
V GNO 03
0.0 1.0 2.0 3.0 4.0 0008-9
OUTPUT VOLTAGE (V) Figure 3. Programming Pinout
0008-8
3-l32
CY7C291
(;A~~~NDUcrOR =======================================================================
- CY7C292
DEVICE BAD
0008-10
The CY7C291 and CY7C292 programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.
Typical programming time for a byte is less than 2.5 msec. The use of EPROM cells allows factory testing of programmed cells, measurement of data
The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 msec which will then be followed by a
longer overprogram pulse of 24 (0.1) (X) msec. X is an iteration counter and is equal to the NUMBER of the initial 0.1 msec pulses applied before
verification occurs. Up to four 0.1 msec pulses are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verification is performed at Veep = 5.0V. When all bytes have been programmed all bytes should be
compared (Read mode) to original data with Vee = 5.0V.
3-133
CY7C291
5A . CYPRESS
SEMICONDUcroR ===============================~~
CY7C292
The 7C291 needs to be within 1 inch of the lamp during
Programming Information erasure. Permanent damage may result if the PROM is
The 7C291 and 7C292 2K x 8 CMOS PROMs are imple- exposed to high intensity UV light for an extended period
mented with a differential EPROM memory cell. The of time. 7258W X sec/cm2 is the recommended maximum
PROMs are delivered in an erased state, containing neither dosage.
"ls" nor "Os". This erased condition of the array may be
assessed using the "BLANK CHECK ONES" and Blank Check
"BLANK CHECK ZEROS" function, see below. A virgin device contains neither ones nor zeros because of
the differential cell used for high speed. To verify that a
Erasure Characteristics PROM is unprogrammed, use the two blank check modes
Wavelengths of light less than 4000 Angstroms begin to provided in Table 3. In each of these modes, the locations 0
erase the 7C291. For this reason, an opaque label should be thru 2047 should be addressed and read. A device is con-
placed over the window ifthe PROM is exposed to sun- sidered virgin if all locations are respectively" Is" and "Os"
light or fluorescent lighting for extended periods of time. when addressed in the "BLANK ONES AND ZEROS"
modes.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 Angstroms for a minimum dose (UV Because a virgin device contains neither ones nor zeros, it
intensity X exposure time) of25 Wsec/cm2 . For an ultra- is necessary to program both ones and zeros. It is recom-
violet lamp with a 12 m W / cm2 power rating the exposure mended that all locations be programmed to ensure that
time would be approximately 30-35 minutes. ambiguous states do not exist.

Table 1
Vpp Programming Voltage[l] 12.0 13.0 V
Vcep Supply Voltage 4.75 5.25 V
VOL Output LOW Voltage[2] 0.4 V

Table 2
tpp Programming Pulse Width[3] 100 10,000 IJ-s
tAS Address Setup Time 1.0 IJ-s
tDS Data Setup Time 1.0 IJ-s
tAH Address Hold Time 1.0 IJ-s
tDH Data Hold Time 1.0 IJ-s
tR, tF Vpp Rise and Fall Time[3] 1.0 IJ-s
tVD Delay to Verify 1.0 IJ-s
tvp Verify Pulse Width 2.0 IJ-s
tDv Verify Data Valid 1.0 IJ-s
tDz Verify to High Z 1.0 IJ-s
Notes.
3-134
CY7C291
(in
. CY7C292
~NDUcrOR =====================================================================
Mode Selection
Table 3
Pin Function
Read or Output Disable CSa CS2 CSt Outputs
Mode
Other PGM VFY Vpp (9-11,13-17)
Read
Output Disable[4]
Output Disable[4]
Output Disable[4]
Program
Pin Number (18)
VIH
X
X
VIL
VILP
(19)
VIH
X
VIL
X
VIHP
(20)
VIL
VIH
X
X
Vpp
Data Out
HighZ
HighZ
HighZ
Data In

Program Verify VIHP VILP Vpp Data Out
Program Inhibit VIHP VIHP Vpp HighZ
Intelligent Program VILP VIHP Vpp Data In
Blank Check Ones Vpp VILP VILP Ones
Blank Check Zeros Vpp VIHP VILP Zeros
Notes:
4. X = Don't care but not to exceed Vee + 5%. 5. During programming and verification, all unspecified pins to be at
VILP
Programming Sequence 2K x 8
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The that fails to verify causes the device to be rejected.
with the output lines in a high impedance state; see Table 3. gram pulse width should be 100 p.s. Each location is ulti-
Again per Figure 5 address, program, and verify one byte mately programmed and verified until it verifies correctly
of data. Repeat this for each location to be programmed. up to and including 4 times. When the location verifies, one
If the brute force programming method is used, the pulse additional programming pulse should be applied of dura-
width of the program pulse should be 10 ms, and each tion 24 x the sum of the previous programming pulses be-
fore advancing to the next address to repeat the process.
PROGRAM
! - - - - - - P R O G R A M - - - - - + _ - - - V E R I F Y _ _ _......_ _O_T_HE-\R B~YTES

VIHP - - -
ADDRESS ADDRESS STABLE
VILP - - - -----"I'-----+--------+-----____..II'-__~ ------
VIHP---
DATA ------00( ~~----~J~-----------
~
VILP - - -
Vpp - - -
PROGRAMMING
VOLTAGE (PIN 20)
VIHP - - -
VILP - - -
1r-------~----~------------~5~----------
VIHP - - -
~
VILP - - -
VIHP - - -
VFY
Ir-------------~ S~-------------
VILP - - -
0008-11
3-135
CY7C291
WA .
~OIDUcrOR==============================================================
CY7C292
Speed IcC Ordering Package Operating Speed Icc Ordering Package Operating
(ns) (mA) Code Type Range (os) (mA) Code Type Range
35 60 CY7C291L-35PC P13 Commercial 35 60 CY7C292L-35PC PH Commercial
CY7C291L-35WC W14 CY7C292L-3SDC 012
90 CY7C291-35PC P13 90 CY7C292-35PC PH
CY7C291-35SC S13 CY7C292-35DC 012
CY7C291-35WC W14 50 60 CY7C292L-50PC PH Commercial
CY7C291-3SLC L64 CY7C292L-50DC 012
120 CY7C291-35WMB W14 Military 90 CY7C292-50PC PH
CY7C291-350MB 014 CY7C292-500C 012
50 60 CY7C291L-50PC P13 Commercial 120 CY7C292-50DMB 012 Military
CY7C291L-50WC W14
90 CY7C291-50PC P13
CY7C291-50SC S13
CY7C291-50WC W14
CY7C291-50LC L64
120 CY7C291-50WMB W14 Military
CY7C291-500MB D14
CY7C291-50LMB L64
CY7C291-5OQMB Q64
3-136
DC Characteristics

VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
Icc 1,2,3
tAA 7,8,9,10,11
tACS 7,8,9,10,11
3-137
CY7C291A
CY7C292A/CY7C293A
CYPRESS
PROM
Features
Windowed for reprogrammability Capable of withstanding > 2001V for bipolar devices and offer the advan-
CMOS for optimum static discharge tages of lower power, reprogrammabili-
speed/power ty, superior performance and program-
Product Characteristics ming yield. The EPROM cell requires
High speed The CY7C291A, CY7C292A, and only 12.SV for the supervoltage and
- 25 ns (commercial) low current requirements allow for
- 30 ns (military) CY7C293A are high performance 2048
word by 8 bit CMOS PROMs. They gang programming. The EPROM cells
Low power are functionally identical, but are pack- allow for each memory location to be
- 330 mW (commercial) aged in 300 mil (7C291A, 7C293A) tested 100%, as each location is written
- 660 mW (military) and 600 mil wide plastic and hermetic into, erased, and repeatedly exercised
DIP packages (7C292A). The prior to encapsulation. Each PROM is
Low standby power also tested for AC performance to
- 165 mW (commercial) CY7C293A has an automatic power
down feature which reduces the power guarantee that after customer program-
- 220 mW (military) ming the product will meet DC and
consumption by over 70% when dese-
EPROM technology 100% lected. The 300 mil ceramic DIP pack- AC specification limits.
programmable age is equipped with an erasure win- Reading is accomplished by placing an
Slim 300 mil or standard 600 dow; when exposed to UV light the active LOW signal on CSt, and active
mil packaging available PROM is erased and can then be repro- HIGH signals on CS2 and CS3. The
grammed. The memory cells utilize contents of the memory location ad-
SV 10% Vee, commercial and proven EPROM floating gate technolo-
military dressed by the address lines (Ao-AlO)
gy and byte-wide intelligent program- will become available on the output
TTL compatible I/O ming algorithms. lines (00-07).
Direct replacement for bipolar The CY7C291A, CY7C292A, and
PROMs CY7C293A are plug-in replacements

07
o. As ~ot(lD~~ ~~~
4 3 2 1 282726
05 .0.4 5 25 .0. 10
.0.3 24 CS1
0
.0.2 23 CS 2
04 A2
.0. 1 8 22 CS3
A, AD 9 21 HC
03 Ao HC 10 20 0,
00 11 19 06
12131415161718
02 0' NQ (J 1"'1 ~ It)
02 0t5 z 0 0 0
04
01 GND 03 0120-3
Window available on
0120-2 7C291A and 7C293A
00
only.
cs,.....J::=;jp;;;;;;;,-------'
CSz
csz-......,.....,
0120-1
Selection Guide
7C291A-25 7C291A-30 7C291A-35 7C291A-50
7C292A-25 7C292A-30 7C292A-35 7C292A-50
7C293A-25 7C293A-30 7C293A-35 7C293A-50
STD
L Commercial 60 60
Standby Current (rnA) Commercial 30 30 30
7C293AOnly Military 40 40 40
3-138
CY7C291A
WA ~~UcrOR =====================================================================
CY7C292A/CY7C293A
Maximum Ratings

Supply Voltage to Ground Potential .... - 0.5V to + 7.0V Operating Range
Ambient
Vee
Temperature
DC Program Voltage .......................... 13.0V Commercial OCto + 70C 5V 1O%
UV Exposure ........................ 7258 Wsec/cm 2

Military [5] - 55C to + 125C 5V 10%

7C291A-25 7C291A-30 7C291AL-35, 50 7C291A-35, 50
7C292A-25 7C292A-30 7C292AL-35, 50 7C292A-35, 50
7C293A-25 7C293A-30 7C293AL-35, 50 7C293A-35, 50
VOH Output HIGH Voltage Vcc = Min.,
2.4 2.4 2.4 2.4 V
IOH = -4.0mA
VOL Output LOW Voltage Vcc = Min.,
0.4 0.4 0.4 0.4 V
IOL = -16.0 rnA
VIH Input HIGH Voltage 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IIX Input Load Current GND::;; VIN::;; Vcc -10 +10 -10 +10 -10 +10 -10 +10 p.A
VCD Input Diode Clamp
Note 2 Note 2 Note 2 Note 2
Voltage
loz Output Leakage GND::;; VOUT::;; Vcc,
-40 +40 -40 +40 -40 +40 -40 +40 p.A
los Output Short Vcc = Max.,
-20 -90 -20 -90 -20 -90 -20 -90 rnA
Circuit CurrentU] VOUT = GND
Icc VCC Operating Vcc = Max., Commercial 120 60 90 rnA
Supply Current lOUT = OmA Military 120 120 rnA
Standby Supply Vcc = Max., Commercial 30 30 30 rnA
ISB
Current (7C293A Only) C81 ~ VIH Military 40 40 rnA
Capacitance [4]
pF
COUT Output Capacitance VCC = S.OV 8
Notes:
I. These are absolute voltages with respect to device ground pin and 3. For test purposes, not more than one output at a time should be
CY7C29IA, CY7C292A and CY7C293A are insensitive to - 3V dc 5. TA is the "instant on" case temperature.
input levels and - 5V undershoot pulses of less than 10 ns (measured 6. See the last page of this specification for Group A subgroup testing
at 50% point). information.
3-139
CY7C291A
5A~UcrOR =====================================================================
,
,,. ' CY7C292A/CY7C293A

7C291A25 7C291A30 7C291A35 7C291A50
7C292A25 7C292A30 7C292A35 7C292A50
7C293A25 7C293A30 7C293A35 7C293A50
tAA Address to Output Valid 25 30 35 50 ns
tHZCSl Chip Select Inactive to High Z[S] 20 20 25 25 ns
tACSl Chip Select Active to Output Valid 20 20 25 25 ns
tHZCS2 Chip Select Inactive to High Z[9]

27 32 35 45 ns
(7C293A CSI Only)
tACS2 Chip Select Active to Output Valid

27 32 35 45 ns
(7C293A CSI Only)[9]
tpu Chip Select Active to Power Up
0 0 0 0 ns
(7C293A CSl Only)
tpD Chip Select Inactive to Power Down
27 32 35 45 ns
(7C293A CSl Only)

R1250 n R1250n
5Vo--------~~~ 5 V 0-----""'1\,--, 3.0 v----~~ ......--_...jL
OUTPUT 0-----_-----... OUTPUT 0-----.....- - - - - -..
GND--.....;~
INCLUDINGI' 30 pF
JIG AND
SCOPE
R2
l67n INCLUDING
JIG AND
SCOPE
I 5 pF
R2
l67n
,;;5 ns

,;;5 ns
0120-5
0120-4
Figure la Figure Ib
Equivalent to: THE-VENIN EQUIVALENT
loon
OUTPUT O~--j,..,~
....~'\.W'"---O 2.0 v
0120-6
Vee
SUPPLY
CURRENT
- tpd I-
~~50%
- tpu I-
-,[50%
AO-A l0
ADDRESS 3l
CS 2-CS 3
..,1- ..,If
CS l
--"x~xd'------f~~N.;.;;0..;.;TE;;..8;....---~-U41(
I---tAA 1+ tHzes' I-- t ACS
NOTE 8
0 0-07 _ _ _ _ _
0120-7
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing S. tHZCS is tested with load shown in Figure lb. Transition is measured
reference levels of 1.5V, output loading of the specified Iov'IOH and at steady state High level - 500 mV or steady state Low level + 500
loads shown in Figures la, lb. mV on the output from the 1.5V level on the input.
9. tHZCS2 and tAcs2 refer to 7C293A CSt only.
3-140
CY7C291A
Wn ~~NDUcroR ==================================================================~
CY7C292A/CY7C293A

VS. SUPPLY VOLTAGE VS. AMBIENT TEMPERATURE VS. SUPPLY VOLTAGE
1.6 ,...----,---,----,...----, 1.2,.------r--------. 1.2
1.41-----i---+---+--~
w ~~
==
i= 1.0
]
II
u
~
'"'"
.!:i
0 ow w
w 1.2 (,,)
N
:J
N
:J
~ 0.8
0
~a:: w
c(
1.0 N
a::
== :J
0
2 i c(
0.6
a::
==
TA - 25C
i I
f-MAX. 0.80'--_ _ _ _......_ _ _ _.......
0.4
TA i 25C
4.5 5.0 5.5 6.0 -56 25 125 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OCI SUPPLY VOLTAGE (VI
TEMPERATURE
VS. VS. VOLTAGE VS. OUTPUT LOADING
1.6 60 30.0
w
1.4
;(
!
...2
50 25.0
/ ---
- '""
==
i=
~
w
w
a::
a::
40 ! 20.0
~
0
1.2
:I
(,,)
w 30
~ ;
c
15.0
/
/~
'"
W (,,)
N 1.0 a::
:I
~
:J ~ ~ 10.0
c( g 20
~V
"
TA25C
a:: I-
== 0.8 :I Vee 4.5 V
0
2 ...
A-
10 5.0
~ V
:I
0
0.6 o 0.0
-55 25 125 o 1.0 2.0 3.0 4.0 o 200 400 800 800 1000
AMBIENT TEMPERATURE (OCI OUTPUT VOLTAGE (VI CAPACITANCE (pFI
OUTPUT SINK CURRENT

VS. OUTPUT VOLTAGE A7 Vee
175
As As
;( 150 As Ag
.5
~~
A4 A10
I-
2 125
w
a:: V A3 Vpp (CS11
a::
:I 100 / A2 vrv (CS2)
(,,)
~
2
iii
75 1/ Vee -5.0 V
A,
Ao
PGM
07
(CS31
S
A-
50 J TA = 25C 06
I-
:I
0 25
/ 0, Os
04
o
V 03
0.0 1.0 2.0 3.0 4.0 0120-10
OUTPUT VOLTAGE (VI Figure 3. Programming Pinout
0120-9
3-141
CY7C291A
5Il ~N;UcrOR =======================================================================
CY7C292A/CY7C293A
0120-8
The CY7C291A, CY7C292A and CY7C293A programming algorithm allows significantly faster programming than the "worst case" specification of 10
ms.
Typical programming time for a byte is less than 2.5 ms. The use of EPROM cells allows factory testing of programmed cells, measurement of data
The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 ms which will then be followed by a
longer overprogram pulse of 24 (0.1) (X) ms. X is an iteration counter and is equal to the NUMBER of the initial 0.1 ms pulses applied before verification
occurs. Up to four 0.1 ms pulses are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verification is performed at Veep = S.OV. When all bytes have been programmed all bytes should be
compared (Read mode) to original data with Vee = S.OV.
3-142
CY7C291A
(in CYPRESS
SEMICONDUcrOR ===========================================================
CY7C292A/CY7C293A
Programming Information to sunlight or fluorescent lighting for extended periods of

time.
The 7C291A, 7C292A and 7C293A 2K x 8 CMOS
PROMs are implemented with a single ended EPROM The recommended dose of ultraviolet light for erasure is a
memory cell. The PROMs are delivered in an erased wavelength of2537 Angstroms for a minimum dose (UV
state, containing "Os". To verify that a PROM is unpro- intensity X exposure time) of25 Wsec/cm 2. For an ultra-
grammed, use the verify mode provided in Table 3. The violet lamp with a 12 m W I cm2 power rating the exposure
time would be approximately 30-35 minutes.
-=-
locations 0 thru 2047 should be addressed and read.
These PROMs need to be within 1 inch of the lamp during
Erasure Characteristics erasure. Permanent damage may result if the PROM is
Wavelengths of light less than 4000 Angstroms begin to exposed to high intensity UV light for an extended period ~
erase these PROMs. For this reason, an opaque label of time. 7258W X sec/cm2 is the recommended maximum
should be placed over the window if the PROM is exposed dosage.

Table 1
Vpp Programming Voltage[l] 12.0 13.0 V
VOL Output LOW Voltage!2] 0.4 V

Table 2
tpp Programming Pulse Width[3] 100 10,000 p.s
tAS Address Setup Time 1.0 p.s
tos Data Setup Time 1.0 p.s
tAH Address Hold Time 1.0 p.s
tOH Data Hold Time 1.0 p.s
tR, tp Vpp Rise and Fall Time[3] 1.0 p.s
tvo Delay to Verify 1.0 p.s
tvp Verify Pulse Width 2.0 p.s
tov Verify Data Valid 1.0 p.s
Notes.
3-143
CY7C291A
5Jl~~~UcrOR================================================================== CY7C292A/CY7C293A
Mode Selection
Table 3
Pin Function
Read or Output Disable CS3 CS2 CSt Outputs
Mode
Other PGM VFY Vpp (9-11,13-17)
Pin Number (18) (19) (20)
Read VIH VIH VIL Data Out
Output Disable[4] X X VIH HighZ
Output Disable[4] X VIL X HighZ
Output Disable[4] VIL X X HighZ
Program VILP VIHP Vpp Data In
Program Verify VIHP VILP Vpp Data Out
Program Inhibit VIHP VIHP Vpp HighZ
Intelligent Program VILP VIHP Vpp Data In
Notes:
4. X = Don't care but not to exceed Vee + 5%. 5. During programming and verification, all unspecified pins to be at
VILP
Programming Sequence 2K x 8
18, 19 and 20 at V!H. Per Figure 5 take pin 20 to Vpp. The that fails to verify causes the device to be rejected.
with the output lines in a high impedance state; see Table 3. gram pulse width should be 200 f.Ls. Each location is ulti-
Again per Figure 5 address, program, and verify one byte mately programmed and verified until it verifies correctly
of data. Repeat this for each location to be programmed. up to and including 10 times. When the location verifies,
If the brute force programming method is used, the pulse one additional programming pulse should be applied of du-
width of the program pulse should be 10 ms, and each ration 4 x the sum of the previous programming pulses
:t
before advancing to the next address to repeat the process.
PROGRAM
BYTES
1 4 - - - - - PROGRAM-----+-_---VERIFY _ _ _.....o--_OT_H""'ER
VIHP - ADDRESS
- - _ _ _....11"_ _ _ -+_______
ADDRESS STABLE -+_________""'1"""_ _"'"
VILP - - -
VIHP---
DATA - - - - - . . . . (
~-~--~ j~-------
~
VILP - - -
Vpp---
PROGRAMMING
VOLTAGE (PIN 20)
VIHP - - -
VILP - - -
VIHP - - -
!>oM
VILP - - -
VIHP - - -
VILP - - -
0120-11
Figure S. Programming Waveforms
3-144
CY7C291A
fiA ?~~NDUcrOR================================================================
CY7C292A/CY7C293A
(ns) (mA) Code Type Range (ns) (mA) Code Type Range
25 120 CY7C291A-25PC P13 Commercial 50 60 CY7C291AL-50PC P13 Commercial

CY7C291A-25WC W14 CY7C291AL-50WC W14
CY7C292A-25PC Pll CY7C292AL-50PC Pll
CY7C292A-25DC D12 CY7C293AL-50PC P13
CY7C293A-25PC P13 CY7C293AL-50WC W14
CY7C293A-25WC W14 90 CY7C291A-50PC P13 Commercial
30 120 CY7C291A-30DMB D14 Military CY7C291A-50DC D14
CY7C291A-30WMB W14 CY7C291A-50WC W14
CY7C291A-30LMB L64 CY7C291A-50LC L64
CY7C291A-30QMB Q64 CY7C292A-50PC Pll
CY7C292A-30DMB D12 CY7C292A-50DC D12
CY7C293A-30DMB D14 CY7C293A-50PC P13
CY7C293A-30WMB W14 CY7C293A-50DC D14
CY7C293A-30LMB L64 CY7C293A-50WC W14
CY7C293A-3OQMB Q64 CY7C293A-50LC L64
35 60 CY7C291AL-35PC P13 Commercial 120 CY7C291A-50DMB D14 Military
CY7C291AL-35WC W14 CY7C291A-50WMB W14
CY7C292AL-35PC Pll CY7C291A-50LMB L64
CY7C293AL-35PC P13 CY7C291A-5OQMB Q64
CY7C293AL-35WC W14 CY7C292A-50DMB D12
90 CY7C291A-35PC P13 Commercial CY7C293A-50DMB D14
CY7C291A-35DC D14 CY7C293A-50WMB W14
CY7C291A-35WC W14 CY7C293A-50LMB L64
CY7C291A-35LC L64 CY7C293A-5OQMB Q64
CY7C292A-35PC Pll
CY7C292A-35DC D12
CY7C293A-35PC P13
CY7C293A-35DC D14
CY7C293A-35WC W14
CY7C293A-35LC L64
120 CY7C291A-35DMB D14 Military
CY7C291A-35WMB W14
CY7C291A-35LMB L64
CY7C291A-35QMB Q64
CY7C292A-35DMB D12
CY7C293A-35DMB D14
CY7C293A-35WMB W14
CY7C293A-35LMB L64
CY7C293A-35QMB Q64
3-145
CY7C291A
Wn .
CYPRFSS
SEMICONDUCTOR
CY7C292A/CY7C293A
===============================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIx 1,2,3
IOZ 1,2,3
Icc 1,2,3
ISB[2] 1,2,3
tAA 7,8,9,10,11
tACSl [1] 7,8,9,10,11
tACS2[2] 7,8,9,10,11
Notes:
1. 7C291A and 7C292A only.
2. 7C293A only.
3-146
~ PROM Programming Information
~~~NDUcrOR ==========================~=========================================
Introduction with the control gate. The state of the floating gate,
PROMs or Programmable Read Only Memories have ex- charged or uncharged, is permanent because the gate is
isted since the early 1970's and continue to provide the isolated in an extremely pure oxide. The charge may be
highest speed non-volatile form of semiconductor memory removed if the device is irradiated with ultraviolet energy
available. Until the introduction of CMOS PROMs from in the form of light. This ultraviolet light allows the elec-
Cypress, all PROMs were produced in bipolar technology, trons on the gate to recombine and discharge the gate. This
because bipolar technology provided the highest possible process is repeatable and therefore can be used during the
performance at an acceptable cost level. All bipolar processing of the device repeatedly if necessary to assure
PROMs use a fuse for the programming element. The fuses programming function and performance.
are in tact when the product is delivered to the user, and Two Transistor Cells
may be programmed or written once with a pattern and
used or read infinitely. The fuses are literally blown using a In order to provide an EPROM cell that is as fast as the
high current supplied by a Programming System. Since the fuse technology employed in bipolar processes, Cypress
fuses may only be blown or programmed once, they may uses a two transistor EPROM cell. One transistor is opti-
not be programmed during test. In addition, since they mized for reliable programming, and one transistor is opti-
may not be programmed until the user determines the pat- mized for high speed. The floating gates are connected
tern, they may not be completely tested prior to shipment such that charge injected on the floating gate of the pro-
from the supplier. This inability to completely test, results gramming transistor is conducted to the read transistor,
in less than 100% yield during programming and use by biasing it off.
the customer for two reasons. First, some percentage of the Differential Memory Cells
product fails to program. These devices fall out during the In the 4K (CY7C225); 8K (CY7C235, CY7C281,
programming operation, and although a nuisance ru:e easi.ly CY7C282)' and 16K (CY7C245, CY7C291, CY7C292)
identified. Additional yield is lost because the devlce fads CMOS PROMs, Cypress employs a differential memory
to perform even though it programs correctly. This failure cell and sense amplifier. technique. Higher density devices
is normally due to the device being too slow. This is a more such as the 7C261, 7C263, 7C264 or 7C269 64K PROMs
subtle failure, and can only be found by 100% post pro- employ a single ended Cell and sense amplifier technique
gram AC testing, or even worse by trouble shooting an similar to the approach used in more conventional
assembled board or system. EPROMs.
Cypress CMOS PROMs use an EPROM programming In a conventional high density EPROM a single EPROM
mechanism. This technology has been in use in MOS tech- transistor is used to switch the input to one side of a differ-
nologies since the early 1970s. However, as with most ential sense amplifier. The other side of the sense amplifier
MOS technologies the emphasis has been on density, not is biased at an intermediate level with a dummy cell. An
performance. CMOS at Cypress is as fast as or faster than unprogrammed EPROM transistor will conduct and drive
Bipolar and coupled with EPROM, becomes a viable alter- the sense amplifier to a logic "0". A programmed EPROM
native to bipolar PROMs from a performance point-of- transistor will not conduct, and consequently drives the
view. In the arena of programming, EPROM has some sense amplifier to a logic" 1". A conventional EPROM cell
significant advantages over fuse technology. EPROM cells therefore is delivered with a specific state "0" or "1" in it
are programmed by injecting charge on an isolated gate depending on the number of inversions after the s~nse am-
which permanently turns off the transistor. This mecha- plifier and can always be programmed to the Opposlte state.
nism can be reversed by irradiating the device with ultravi- Access time in this conventional approach is heavily depen-
olet light. The fact that programming can be erased, totally dent on the time the selected EPROM transistor takes to
changes the testing and programming situation and philos- move the input of the sense amplifier from a quiescent con-
ophy. All cells can be programmed during the manufactur- dition to the threshold that the dummy cell is biasing the
ing process and then erased prior to packaging and subse- second input to the sense amplifier. This bias is several
quent shipment. While these cells are programmed, the volts, and requires a significant delay before'the sense am-
performance of each cell in the memory can be teste~ al- plifier begins to react.
lowing the shipment of devices that program every time,
and will perform as specified when programmed. In addi- Cypress PROMs employ a true differential cell approach,
tion when these devices are supplied in a windowed pack- with EPROM cells attached to both inputs of the sense
age they can be programmed and erased indefinitely pro- amplifier. As indicated above, the read transistor which is
viding the designer a RE-PROGRAMMABLE PROM for optimized for speed is actually the transistor attached to
development. the sense amplifier. In the erased state, both EPROM tran-
sistors conduct when selected eccentrically biasing the in-
put of the sense amplifier at the same level. If the in~uts
Programmable Technology were at identical levels, the output of the sense ampbfier
EPROM Process Technology would be in a mestastable condition or, neither a "I" nor
"0". In actual practice the natural bias and high gain of the
EPROM' technology employs a floating or isolated gate sense amplifier combine to cause the output to favor one or
between the normal control gate and the source/drain re- the other stable conditions. The difference between the two
gion of a transistor. This gate may be charged with elec- conditions is however only a few millivolts and the memo-
trons during the programming operation and when ry cell should be considered to contain neither a "1" nor a
charged with electrons, the transistor is permanently "0". As a result of this design approach, the memory cell
turned off. When uncharged (the transistor is unpro- must be programmed to either a "I" or a "0" depending on
grammed) the device may be turned on and off normally the desired condition and the conventional BLANK
3-147
~ PROM Programmbig Information (Continued)
~~~NDUcrOR=====================================================================
CHECK mechanism is invalid. The benefit of the approach function. This makes the need to switch high voltages un-
however is that only a small differential signal from the cell necessary during the program verify operation. See specific
begins the sense amplifier switching and the access time of data sheets for details.
the memory is extremely. fast. Programming the Data Array
Single Ended Memory Cells Programming is accomplished by applying a supervoltage
Although a more conventional approach, single ended to one pin of the device causing it to enter the. program-
memory cells and sensing techniques offer a superior trade- ming mode of operation. This also provides the program-
off between die size and performance than the differential ming voltage for the cells to be programmed. In this mode
cell for devices of 64K densities and above. The Single of operation, the address lines of the device are used to
ended technique employed by Cypress uses a dummy cell address each location to be programmed, and the data is
for the reference voltage thus providing a reference that presented on the. pins normally used for reading the con-
tracks the programmed cell in process related parameters, tents of the device. Each device has a READ and a
power supply and temperature induced variations. The WRITE pin in the programming mode. These are active
Memory cell used is a second generation two transistor cell low signals and cause the data on the output pins to be
derived from earlier work at the 16K density level. It has written into the addressed memory location in the case of
an optimized READ transistor that is matched to the sense the WRITE signal or read out of the device in the case of
amplifier, and a second transistor optimized for program- the READ signal. When both the READ and WRITE sig-
ming. The floating gates of the two transistors that make nals are high, the outputs are disabled and in a high imped-
up a memory cell are connected electrically so that the ance state. Programming therefore is accomplished by
charge programmed onto one device controls the threshold placing data on the output pins, and writing it into the
of the second transistor. addressed location with the WRITE signal. Verification of
Unlike the differential memory approach, the erased single data is accomplished by reading the information on the
ended device contains all "O"s and on the the ones are output pins while the READ signal is active.
programmed. Therefore a "1" on the data pins during pro- The timing for actual programming is supplied in the
gramming causes a "I" to be programmed into the ad- unique programming specification for each device.
dressed location.
Special Features
Programming Algorithm Depending on the specific CMOS PROM in question, ad-
Byte Addressing and Programming ditional features that require programming may be avail~
able to the designer. Two of these features are a Program-
All Cypress CMOS PROMs are addressed and pro- mable INITIAL BYTE and Programmable SYNCHRO-
grammed on a byte basis unlike the bipolar products that NOUS/ASYNCHRONOUS ENABLE available in some
they replace. The address lines used to access the memory of the registered devices. Like programming the array,
in a read mode are the same for programming, and the these features make use of EPROM cells and are pro-
address map is identical. The information to be programmed in a similar manner, using supervoltages. The
grammed into each byte is presented on the data out pins specific timing and programming requirements are speci-
during the programming operation and the data is read fied in the data sheet of the device employing the feature.
from these same pins for verification that the byte has been
programmed.
Programming Support
Blank Check for Differential Cells
Programming support for Cypress CMOS PROMs is avail-
Since a differential cell contains neither a "1" nor a "0" able from a number of programmer manufacturers, some
before it is programmed, the conventional BLANK of which are listed below.
CHECK is not valid. For this reason, all Cypress CMOS
PROMs. contain a special BLANK CHECK mode of oper- Data I/O Corporation
ation. Blank check is performed by separately examining 10525 Willows Rd. N.E.
the "0" and "I" sides of the differential memory cell to P.O. Box 97046
determine whether either side has been independently pro- Redmond, WA
grammed. This is accomplished in two passes one compar- 98073-9746
ing the "0" side of the differential cell against a reference (206) 881-6444
voltage applied to the opposite side of the sense amplifier
Data I/O 29B Uoipak II
and then repeating this operation for the "1"s side of the
cell. The modes are called BLANK CHECK ONES, and Cypress Generic Family Code
Revision
BLANK CHECK ZEROS. These modes are entered by Part Number Part Number and Pinout
the application of a supervoltage to the device. CY7C225 27S25 FO B6 V12
Blank Check for Single Ended Cells CY7C235 27S35 FO B5 V09
Single ended cells BLANK CHECK in a conventional CY7C245 27S45A FO BO V09
manner. An erased device contains all "O"s and a pro- CY7C261/3/4 27S49 EF 31 Vll
grammed call will contain a "I". Cypress PROMs that use CY7C281/2 27S281/181 EE B4 V09
the single ended approach provide a specific mode to per- CY7C291/2 27S291/191 EE AF V09
form the BLANK CHECK which also provides the verify
3-148
~ PROM Programming Information (Continued)
~~~NDUcrOR =====================================================================
Stag Microsystems Cypress Semiconductor, Inc.
1600 Wyatt Dr. 3901 North First St.
Santa Clara, CA 95054 San Jose, CA 95134
(408) 988-1118 (408) 943-2600
Stag PPZ Zm2000 Cypress CY3000 QuickPro Rev. PROM 2.10
Cypress Generic Family Code Cypress Generic Family Code

Revision
Part Number Part Number and Pinout Part Number Part Number and Pinout
CY7C225 27825 Rev 21 CY7C225
CY7C235 27S35 Rev 21 CY7C235
Menu
CY7C245 27S45A Rev 24 CY7C245
Driven
CY7C281/2 278281/181 Rev 21 CY7C261/3/4 Menu Menu
CY7C291/2 27S291/191 Rev 21 CY7C268 Driven Driven
CY7C269
CY7C281/2
CY7C291/2
3-149
PRODUCT
INFORMATION
STATIC RAMS
PROMS
riM l,iJz EPLDS f

LOGIC
RISC
..
MODULES
,.
ECL
MILITARY ,.
BRIDGEMOS
QUICKPRO
'I.
PLDTOOLKIT If-
QUALITY AND
RELIABILITY
lSI
APPLICATION BRIEFS
'G'
PACKAGES I~.
~ Section Contents
~. ~~~UcrOR==================================================================
EPLDs (Eraseable Programmable Logic Devices) Page Number
Introduction to EPLDs .................................................................................. 4-1
PAL C 20 Series 16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL Device .................... 4-7
PLD C 18G8 CMOS Generic 20 Pin Programmable Logic Device .............................. 4-26
PLD C 20G lOB CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-33
PLD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-33
PLD C 20RAlO Reprogrammable Asynchronous CMOS Programmable Logic Device ............... .4-52
PAL C 22VlOB Reprogrammable CMOS PAL Device .......................................... 4-61
PAL C 22VlO Reprogrammable CMOS PAL Device .......................................... 4-61
CY7C330 Synchronous State Machine .................................................. 4-80
CY7C331 Asynchronous Registered EPLD .............................................. 4-91
CY7C332 Combinatorial Registered EPLD ............................................. 4-103
CY7C340 EPLD Family Multiple Array Matrix High Density EPLDs .................................. .4-112
CY7C361 Ultra High Speed State Machine ............................................. 4-123
PLD Programming Information ......................................................................... 4-129
~ Introduction to CMOS EPLDs
~~~U~================================================================
Cypress EPLD Family Features
Cypress Semiconductor's EPLD family offers the user the ability. The flexibility afforded by these EPLDs allows the
next generation in Erasable Programmable Logic Devices designer to quickly and effectively implement a number of
(EPLD) based on our high performance 0.8,... CMOS pro- logic functions ranging from random logic gate replace-
cess. These devices offer the user the power saving of a ment to complex combinatorial logic functions.
CMOS-based process, with delay times equivalent to those The EPLD family implements the familiar "sum of prod-
previously found only in bipolar devices. No fuses are used ucts" logic by using a programmable AND array whose
in Cypress' EPLD family, rather all devices are based on output terms feed a fixed OR array. The sum of these can
an EPROM cell to facilitate programming. By using an be expressed in a Boolean transfer function and is limited
EPROM cell instead of fuses, programming yields of 100% only by the number of product terms available in the
can be expected since all devices are functionally tested and AND-OR array. A variety of different sizes and architec-
erased prior to packaging. Therefore, no programming
yield loss can be expected by the user.
tures are available. This allows for more efficient logic opti- 4
mization by matching input, output and product terms to
The EPROM cell used by Cypress serves the same purpose the desired application.
as the fuse used in most bipolar PLD devices. Before pro-
gramming, the AND gates or Product Terms are connect- EPLD Notation
ed via the EPROM cells to both the true and complement
inputs. When the EPROM cell is programmed, the inputs To reduce confusion and to have an orderly way of repre-
from a gate or Product Term are disconnected. Program- senting the complex logic networks, logic diagrams are
ming alters the transistor threshold of each cell so that no provided for the various part types. In order to be useful,
conduction can occur, which is equivalent to disconnecting Cypress logic diagrams employ a common logic convention
the input from the gate or Product Terms. This is similar that is easy to use. Figure 1 shows the adopted convention.
to "blowing" the fuses of a bipolar device which discon- In Figure 1, an "x" represents an unprogrammed EPROM
nects the input gate from the Product Term. Selective pro- cell that is used to perform the logical AND operation
gramming of each of these EPROM cells enables the spe- upon the input terms. The convention adopted does not
cific logic function to be implemented by the user. imply that the input terms are connected on the common
line that is indicated. A further extension of this conven-
The programmability of Cypress' EPLDs allows the users tion is shown in Figure 2 which shows the implementation
to customize every device in a number of ways to imple- of a simple transfer function. The normal logic representa-
ment their unique logic requirements. Using EPLDs in tion of the transfer function logic convention is shown in
place of SSI or MSI components results in more effective Figure 3.
utilization of boardspace, reduced cost and increased reli-
~=O-A. .C= -fH-cr-A. .C

0024-1
Figure 1
0024-2
Figure 2
0024-3
Figure 3
4-1
~ Introduction to CMOS EPLDs (Continued)
~~~~========~~~====~~====~==============================
with the register. may still be used as a device input. The
PLD Circuit Configurations proprietary CY7C330 Reprogrammable Synchronous State
Cypress EPLDs have several different. ou~put configur~ Machine macrocell illustrates, in Figure 6, the use of bur-
tions that cover a wide spectrum of apphcatIons. The avall- ied registers with provision for saving the I/O pin for use
able output configurations offer the user the benefits of as an input. If the feedback path is selected by the feedback
both lower package counts and reduced costs when used. multiplexer, the Q of the register is fed back to the array as
This approach allows the designer to select a PLD that best an input. The I/O pin can still be. routed ~o the array as ~n
fits the needs of his application. An example of some of the external input by use of a special multiplexer sh?wn m
configurations that are available are listed below. Figure 7 provided for that purpo~e for. each of the SIX m~c
rocell pairs. A special configuration bit, <=:3, selects th~ m-
Programmable I/O put register output from one of the I/O pms of the pair of
macrocell I/O pins which is to be fed to the array as an
Figure 4 illustrates the programmable I/O offered in t~e external input. By proper placement of buried register con-
Cypress EPLD family which allows product terms to di- figured I/O macrocells adja~ent to I/O macrocel~s used as
rectly control the outputs of the device. One product term normal registered outputs without feedback, maximum use
is used to directly control the three-state output buffer, of the buried macrocell I/O pins for inputs can be
which then gates the summation of the remaining terms to achieved. The CY7C330 also contains four dedicated bur-
the output pin. The output of this summation. can be fed ied or hidden registers with no external output, illustrated
back into the PLD as an input to the array. This program- in Figure 8, which are used as additional state regis~er re-
mable I/O feature allows the PLD to drive the output pin sources for creation of high performance state machmes.
when the three-state output is enabled or, the I/O pin can
be used as an input to the array when the three-state output
is disabled. Asynchronous Register Control
Cypress also offers EPLDs which may be used in asynchro-
Registered Outputs with Feedback nous systems in which register clock, set and reset are con-
trolled by the outputs of the product term array. The clock
Figure 5 illustrates the registered output offered on a. nut;n- signal is created by the processi~g of external inputs
ber of the Cypress EPLDs which allow any of these ClrcUlts and/or internal feedback by the logiC of the product term
to function as a state sequencer. The summation of the array which is then routed to the register clock. The regis-
product terms is stored in the D-type output flip-flop on ter set and reset are similarly controlled by product term
the rising edge of the system clock. The. Q output. of the outputs and can be triggered at any time independent of
flip-flop can then be gated to the output pm by enabhng the the register clock in response to external and/or feedback
three-state output buffer. The output of the flip-flop can inputs processed by the logic array. The proprietary
also be fed back into the array as an input term. The output CY7C331 Asynchronous Registered EPLD, for which the
feedback feature allows the PLD to remember and then I/O macrocell is illustrated in Figure 9, is an example of
alter its function based upon that state. This circuit can be such a device. The register clock, set and reset functions of
used to execute such functions as counting, skip, shift and the CY7C331 are all controlled by product terms and en-
branch. able their respective functions dependent only on input sig-
nal timing and combinatorial delay through the device log-
Programmable Macro Cell ic array.
The Programmable Macro Cell, illustrated in Figure 10,
provides the capability of defining the architecture of each Input Register Cell
output individually. Each of the potential outputs may be Other Cypress EPLDs provide input register cells which
specified to be "REGISTERED" or "COMBINATORI- allow capture for processing of short duration inputs which
AL". Polarity of each output may also be individually se- would not otherwise be present at the inputs for sufficient
lected allowing complete flexibility of output configuration. time to allow the device to respond. Both the proprietary
Further configurability is provided through "ARRAY" CY7C330 Reprogrammable Synchronous State Machine
configurable "OUTPUT ENABLE" for each potential out- and the proprietary CY7C332 Combinatorial E~LD. pro-
put. This feature allows the outputs to be reconfigure~ ~s vide these input register cells which are shown m Figure
inputs on an individual basis or alternately used as a bidi- 11. The clock for the input register may be provided from
rectional I/O controlled by the programmable array. one of two external clock input pins selectable by a config-
uration bit, C4, dedicated for this purpose for each .input
Buried Register Feedback register. This choice of input register clock allows Signals
A number of Cypress EPLDs provide registers which may to be captured and processed from two independent system
be "buried" or "hidden" to create registers for state ma- sources each controlled by its own independent clock.
chine implementation without sacrificing the use of the as- These input register cells are provided within I/O macro-
sociated device pin. The device pin normally associated cells, as well as, for dedicated input pins.
4-2
~ Introduction to CMOS EPLDS(Continued)
~~~UcrOR================================================================
NPUTS, FEEDBACK, AND I/O
I-Dls '1111111111111111111111111111111'
Figure 4. Programmable I/O
~'/O 0024-4
INPUTS, FEEDBACK AND I/O CLOCK

i
")- r-D......-or-- ~ 0-0
~~1
-1)_ ~ ....
0024-5
Figure 5. Registered Outputs with Feedback
GLOBAL
SYNCHRONOUS SET
INPUT OR FEEDBACK TO LOGIC ARRAY
TO SHARED INPUT
t.iACRO CELL GLOBAL STATE CLOCKS CK2 CK1
INPUT MUX REGISTER CLOCK (PIN 3)(PIN 2)
CLK(PIN 1)
0024-7
Figure 6. CY7C330 I/O Macro Cell
4-3
~~~~==================================================~========
FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
0024-8
Figure 7. CY7C330 I/O Macro Cell Pair Shared Input MUX
GLOBAL SYNCHRONOUS SET
FEEDBACK TO LOGIC ARRAY
GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)
0024-9
Figure 8. CY7C330 Hidden State Register Macro Cell
4-4
~~~ucr~==================================================================
PIN 14
OE
t.AUX
SET PRODUCT TERM

OUTPUT
REGISTER
CLOCK PRODUCT TERt.A

R
RESET PRODUCT TERM
FEEDBACK S
----~~I~------------~ t.AUX
Q D
INPUT
REGISTER
TO SHARED
INPUT t.AUX
0024-10
Figure 9. CY7C331 Registered Asynchronous Macrocell
CLOCK AR
OE I I
0 ..LL
r- ~ t.4ACRO-
-t:::t ~
~~
~
CELL
rr>o-r I/O
3
.. -
SP
0024-6
Figure 10. Programmable Macro Cell
4-5
~~~U~==~~~~~~~~~~~~~~~~~~~~~~==~~==~~~==
...,..~_ _~ INPUT TO
V1~--~ LOGIC
ARRAY
REGISTER INITIALIZED ON POWER

UP TO Q EQUAL TO LOGIC LOW
C4
CK1 CK2
(PIN 2) (PIN 3)
0024-11
Figure 11. CY7C330 Dedicated Input Cell
4-6
PAL C 20 Series
CYPRESS
SEMICONDUCTOR Reprogrammable CMOS
PAL C 16L8, 16R8, 16R6, 16R4
Features
CMOS EPROM technology for High reliability gram custom logic functions serving
reprogrammability - Proven EPROM technology unique requirements.
High performance at quarter - ;> 1500V input protection PALs are offered in 20-pin plastic and
power from electrostatic discharge ceramic DIP, Plastic SOJ, and ceramic
-tpD = 25ns - 100% ACIDC tested LCC packages. The ceramic package
-ts=20ns - 10% power supply tolerances can be equipped with an erasure win- _
- teo = 15 ns - High noise immunity dow; when exposed to UV light, the ~
-Icc = 45mA - Security feature prevents PAL is erased and can then be repro-
pattern duplication grammed.
High performance at military - 100% programming and
temperature functional testing Before programming, AND gates or
-tpD = 20ns PRODUCT TERMS are connected via
- t s = 20ns Functional Description EPROM cells to both TRUE and
- teo = 15 ns Cypress PAL C Series 20 devices are
COMPLEMENT inputs. Program-
- Icc = 70 mA ming an EPROM cell disconnects an
high speed electrically programmable INPUT TERM from a PRODUCT
Commercial and military and UV erasable logic devices pro-
temperature range TERM. Selective programming of
duced in a proprietary "N" well CMOS these cells allows a specific logic func-
EPROM process. These devices utilize tion to be implemented in a PAL C de-
the sum of products (AND-OR) struc- vice. PAL C devices are supplied in
ture providing users the ability to pro- four functional configurations, desig-
Logic Symbols and DIP and SOJ Pinouts

16R8 16R6 16R4 16L8
0038-1 0038-2 0038-3 0038-4
LCCPinouts
u U
Q. U
_u>o Q.~
_u>_ ~>~~ U
_>0
0 0 I/O I/O
0 0 0 I/o
0 0 0 I/O
0 0 0 I/O
0 0 0 I/O
- ~I~ 0 0 - ~I~ ~ 0 - >~I~ ~ ~

- 1Il-
III
0 0
> 0038-5 > - 0038-6 0038-7 > :::::- 0038-8
PAL@ is a registered trademark of Monolithic Memories Inc.

CYPRESS SEMICONDUCTOR is a trademark of Cypress Semiconductor Corporation.
4-7
~ PAL@ C 20 Series
~~~UcrOR================================================================
nated 16R8, 16R6, 16R4 and 16L8. These eight devices functionally tested during manufacturing. An ability to
have potentially 16 inputs and 8 outputs configurable by preload the registers of registered devices during the testing
the user. Output configurations of 8 registers, 8 combinato- operation makes the testing easier and more efficient. The
rial, 6 registers and 2 combinatorial as well as 4 registers PHANTOM ARRAY and PHANTOM operating mode
and 4 combinatorial are provided by the four functional allow the device to be tested for functionality and perform-
variations of the product family. All combinatorial outputs ance after it has been packaged. Combining these inherent
on the 16R6 and 16R4 as well as 6 of the combinatorial and designed-in features, an extremely high degree of func-
outputs on the 16L8 may be used as optional inputs. All tionality, programmability and assured AC performance
registered outputs have the Q bar side of the register fed are provided and testing becomes an easy task.
back into the main array. The registers are automatically The REGISTER PRELOAD allows the user to initialize
initialized on power up to Q output LOW and Q output the registered devices to a known state prior to testing the
HIGH. All unused inputs should be tied to ground. device, significantly simplifying and shortening the testing
All PAL C devices feature a SECURITY function which procedure.
provides the user protection for the implementation of pro- The PHANTOM MODE of operation provides a com-
prietary logic. When invoked, the contents of the normal pletely separate operating mode where the functionality of
array may no longer be accessed in the verify mode. Be- the device along with its AC performance may be ascer-
cause EPROM technology is used as a storage mechanism, tained. The user need not be encumbered by programmed
the content of the array is not visible under a microscope. cells in the normal operating mode. This PHANTOM
The PAL C device also contains a PHANTOM ARRAY MODE of operation allows additional input lines to be pro-
used for functional and performance testing. The content grammed to operate the PAL C device, exercising the de-
of this array is always accessible, even when security is vice functionally and allowing AC performance measure-
invoked. ments to be made. The PHANTOM MODE of operation
Cypress PAL C products are produced in an advanced 1.2 acknowledges only the INPUT TERMS shown shaded in
micron "N" well CMOS EPROM technology. The use of the functional block diagrams. Likewise, the normal
this proven EPROM technology is the basis for a superior PHANTOM INPUT TERMS do not exist in the normal
product with inherent advantages in reliability, testability, mode of operation. During the final stages of manufactur-
programming and functional yield. EPROM technology ing, some cells in the PHANTOM ARRAY are pro-
has the inherent advantage that all programmable elements grammed for final AC and functional testing. These cells
may be programmed, tested and erased during the manu- remain programmed, and may be used at incoming inspec-
facturing process. This also allows the device to be 100% tion to verify both functional and AC performance..
Commercial and Industrial Selection Guide
Generic Icc (mA) tpD (ns) ts (ns) teo (ns)
Part Output
Logic Outputs
Number Enable
L COM'L/IND -25 -35 -25 -35 -25 -35
(8) 7-wide (6) Bidirectional
16L8
AND-OR-Invert
Programmable
(2) Dedicated
45 70 25 35 - - - -
16R8 (8) 8-wide AND-OR Dedicated Registered Inverting 45 70 - - 20 30 15 25
(6) 8-wide AND-OR Dedicated Registered Inverting
16R6 (2) 7-wide 45 70 25 35 20 30 15 25
Programmable Bidirectional
AND-OR-Invert
16R4 (4) 7-wide 45 70 25 35 20 30 15 25
AND-OR-Invert
Military Selection Guide

Generic tpD (ns) ts (ns) teo (ns)
Part Logic
Output
Outputs Icc
Number Enable (mA)
20 30 40 20 30 40 20 30 40
(8) 7-wide (6) Bidirectional
16L8
AND-OR-Invert
Programmable
(2) Dedicated 70 20 30 40 - - - - - -
16R8 (8) 8-wide AND-OR Dedicated Registered Inverting 70 - - - 20 25 35 15 20 25
16R6 (2) 7-wide 70 20 30 40 20 25 35 15 20 25
AND-OR-Invert
16R4 (4) 7-wide 70 20 30 40 20 25 35 15 20 25
AND-OR-Invert
4-8
~ PAL C20Series
~~~UaoR================================================================~
Maximum Ratings
Storage Temperature ............... -65C to + 150C UV Exposure ........................ 7258 Wsec/cm 2
Ambient Temperature with Static Discharge Voltage ..................... > 1500V
Power Applied .................... - 55C to + 125C (per MIL-STD-883 Method 3015)
Supply Voltage to Ground Potential Latchup Current .......................... > 200 mA
(Pin 20 to Pin to) .................... -0.5V to + 7.0V Operating Range
in High Z State ...................... - 0.5V to + 7.0V Ambient
Range Vee
Temperature
Commercial OCto + 75C 5V 10%
DC Programming Voltage ...................... 14.0V
Military [7]
Industrial
- 55C to + 125C
-40C to + 85C
5V 1O%
5V 10% II
Electrical Characteristics Over Operating Range (Unless Otherwise Noted)[6]
Vee = Min. lOR = -3.2mA Commercial/Industrial
VOR Output HIGH Voltage 2.4 V
VIN = VIR or VIL lOR = -2mA Military
Vee = Min. IOL = 24mA Commercial/Industrial
VIN = VIR or VIL IOL = 12mA Military
VIR Input HIGH Level Guaranteed Input Logic HIGH[1] Voltage for all Inputs 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW[1] Voltage for all Inputs 0.8 V
IIX Input Leakage Current Vss s VIN s Vee -10 10 /LA
Vpp Programming Voltage Ipp = 50 mA Max. 13.0 14.0 V
Isc Current
Vee = Max., VOUT = 0.5V[2] -300 mA
All Inputs = GND, "L" 45 mA

Power Supply Current Vee = Max., COM'L/IND 70 mA
lee
lOUT = 0 mA[5]
MIL 70 mA
loz Output Leakage Current Vee = Max., VSS s VOUT s Vee -100 100 /LA
Table 1
Parameter Vx Output Waveform-Measurement Level
tpxz(-) 1.5V VOH
o.~v ~~ Vx 0038-26
Vx
tpxz(+) 2.6V
VOL O'fV rt: 0038-27
tpzx(+ ) Vthc
Vx ot
v
7t VOH
0038-28
~t
tpzx(-) Vthc Vx
O;SV
VOL 0038-29
O.~V ~l:
tER(-) 1.5V VOH
Vx 0038-26
Vx
tER(+ ) 2.6V
VOL o.}V rt: 0038-27
tEA(+ ) Vthc
Vx o.}V 7t VOH
0038-28
~
tEA(-) Vthc Vx
O}V
VOL 0038-29
4-9
~ PAL C 20 Series
~~~NDUCTOR =====================================================================
Capacitance [3]
pF
COUT Output Capacitance VIN = 0, Vee = 5.0V 7
Switching Characteristics PAL C 20 Series Over Operating Range[4, 6, 8]

Commercial/lndustrial Military
Parameters Description 25 35 20 30 40 Units
Input or Feedback to Non-Registered
tpD 25 35 20 30 40 ns
Output 16L8, 16R6, 16R4
tEA Input to Output Enable 16L8, 16R6, 16R4 25 35 20 30 40 ns
tER Input to Output Disable 16L8, 16R6, 16R4 25 35 20 30 40 ns
tpzx Pin 11 to Output Enable 16R8, 16R6, 16R4 20 25 20 25 25 ns
tpxz Pin 11 to Output Disable 16R8, 16R6, 16R4 20 25 20 25 25 ns
teo Clock to Output 16R8, 16R6, 16R4 15 25 15 20 25 ns
Input or Feedback Setup Time 16R8,
ts 20 30 20 25 35 ns
16R6,16R4
tH Hold Time 16R8, 16R6, 16R4 0 0 0 0 0 ns
tp Clock Period 35 55 35 45 60 ns
tw Clock Width 15 20 12 20 25 ns
fMAX Maximum Frequency 28.5 18 28.5 22 16.5 MHz
Notes:
1. These are absolute values with respect to device ground and all over- 5. ICC(AC) = (0.6 rnA/MHz) X (Operating Frequency in MHz) +
shoots due to system or tester noise are included. ICC(DC)' ICC(DC) is measured with an unprogrammed device.
2. Not more than one output should be tested at a time. Duration of the 6. See the last page of this specification for Group A subgroup testing
short circuit should not be more than one second. VOUT = 0.5V has information.
been chosen to avoid test problems caused by tester ground degrada- 7. TA is the "instant on" case temperature.
tion. 8. The parameters tER and tpxz are measured as the delay from the
3. Tested initially and after any design or process changes that may input disable logic threshold transition to VOH - 0.5V for an enabled
affect these parameters. HIGH output or VOL + 0.5V for an enabled LOW output. Please see
4. Figure latest load used for all parameters except tEA, tER tpzx and Table 1 for waveforms and measurement reference levels.
tpxz. Figure 1b test load used for tEA. tER. tpzx and tpxz.
5V=r.1
OUTPUT
1
Rl175 !l
50 pF
-=
R2
133S1
5v=n
OUTPUT
I
Rl175!l
5pF R2
133!l
Equivalent to:
THEVENIN EQUIVALENT COMMERCIAL
OUTPUT~2.16V=Vthc
75Q
-=- ":" 0038-10

0038-11
Figure la. Commercial Figure lb. Commercial
Equivalent to:
THEVENIN EQUIVALENT MILITARY
143Q
OUTPUT~ 2.11V=Vthm
0038-12
0038-9
Figure lc. Military Figure ld. Military
3.0V----~-----t
GND
0038-13
Figure 2
4-10
~ PALC20Series
~~~NDUcroR =====================================================================
Switching Waveforms
INPUTS, I/O,
~:~~~~~R:D ~~__~__~~~~~~l- __________________________________~~______~________
CP
REGISTERED ---,DuoO\lr------'"'1------\JJ~
OUTPUTS: ____~~~~l-------~-------l~~~
....t-~i+I~
~~L-______________~--------~------__
II
COMBINATORIAL
OUTPUTS:
_________________~_tPD_______________________________~:~~~:t---+"'~~~_tE_A_ r
0038-14
Figure 3
Wavelengths of light less than 4000 Angstroms begin to 12 inclusive). In the unprogrammed state, all inputs are
erase the PAL C device. For this reason, an opaque label connected to product terms. A "1" on a data line causes a
should be placed over the window if the device is exposed cell to be programmed, disconnecting an INPUT TERM
to sunlight or fluorescent lighting for extended periods of from a PRODUCT TERM. During verify, an unpro-
time. In addition, high ambient light levels can create hole- grammed cell causes a "1" to appear on the output, while a
electron pairs which may cause "blank" check failures or programmed cell will appear as a "0". Table 4 describes
"verify errors" when programming "windowed" parts. the operating modes of the device and the programming
This phenomenon can be avoided by use of an opaque label waveforms are described in Figures 6 through 9. The actual
over the window during programming in high ambient sequence required to program a cell is described in Figure 5
light environments. and applies for programming either standard or phantom
The recommended dose for erasure is ultraviolet light with portions of the array. The security bit should be pro-
a wavelength of 2537 Angstroms for a minimum dose (UV grammed using a single 10 ms pulse, and verified per Fig-
intensity x exposure time) of25 Wsec/cm 2. For an ultravi- ure 9.
olet lamp with a 12 m W I cm2 power rating, the exposure Vpp Veep
would be approximately 35 minutes. The PAL C device
Ao Do
needs to be placed within 1 inch of the lamp during era-
sure. Permanent damage may result if the device is exposed A, 0,
to high intensity UV light for an extended period of time. Az 02
7258 Wsec/cm 2 is the recommended maximum dosage. A3 03
04
Programming
PAL C devices are programmed a BYTE at a time using a
""
As Os
As 06
voltage to transfer electrons to a floating gate. The array A7 D7
programmed is addressed as memory of 256 bytes, using Vss PGM/()E
address Tables 5 and 6. These addresses are supplied to the 0038-15
device over Pins 2 through 9. The data to be programmed Figure 4. Programming Pin Configuration
is supplied on data inputs DO through D7 (Pins 19 through
DC Programming Parameters Ambient Temperature = 25C
Table 2
Parameter Description Min. Max. Units Notes
Vccp Supply Voltage During Programming 4.75 5.25 V
VIHP Programming Input High Voltage 3.0 V
VILP Programming Input Low Voltage 0.4 V
VOH Output High Voltage 2.4 V 1
VOL Output Low Voltage 0.4 V 1
4-11
~ PAL C 20 Series
~~~U~================================================================
AC Programming Parameters Ambient Temperature = 25C
Table 3
Parameter Description Min. Max. Units Notes
tpp Programming Pulse Width 100 10,000 p.s 2
ts Setup Time 1.0 p.s
tH Hold Time 1.0 p.s
tf> tr VPP Rise and Fall Time 1.0 p.s 2
tyO Delay to Verify 1.0 p.s
typ Verify Pulse Width 2.0 p.s
tOY Verify to Data Valid 20.0 p.s
Table 4
Pin Name Vpp PGM/OE A1 A2 A3 A4 AS D7-DO
Pin Number (1) (11) (3) (4) (5) (6) (7) (12-19) Notes
Operating Modes
PAL X X X X X X X Programmed Function 3,4
Program PAL Vpp Vpp X X X X X Data In 3,5
Program Inhibit Vpp VIHP X X X X X HighZ 3,5
Program Verify!Blank Check Vpp VILP X X X X X Data Out 3,5,11
Phantom PAL X X X X X Vpp X Programmed Function 3,6
Program Phantom PAL Vpp Vpp X X X X Vpp Data In 3, 7
Phantom Program Inhibit Vpp VIHP X X X X Vpp HighZ 3,7
Phantom Program Verify Vpp VILP X X X X Vpp Data Out 3,7
Program Security Bit Vpp Vpp Vpp X X X X HighZ 3,8
Verify Security Bit X X Note 9 Vpp X X X HighZ 3
Register Preload X X X X Vpp X X Data In 3, 10
Notes:
1. Ouring verify operation is used to select the phantom mode of operation and must be taken to
2. Measured at 10% and 90% points Vpp before selecting phantom program operation with Vpp on Pin 1.
3. Yss < X < Vccp S. See Figure 8 for security programming sequence.
4. All "X" inputs operational per normal PAL function. 9. The state of Pin 3 indicates if the security function has Qeen invoked
5. Address inputs occupy Pins 2 thru 9 inclusive, for both programming or not. If Pin 3 = VOL security is in effect, if Pin 3 = VOH, the data
and verification see programming address Tables 5 and 6. is unsecured and may be directly accessed. '
6. All "X" inputs operational per normal PAL function except that they 10. For testing purposes, the output latch on the 16RS, 16R6 and 16R4
operate on the function that occupies the phantom array. may be preloaded with data from the appropriate associated, output
line.
7. Address inputs occupy Pins 2 thru 9 inclusive, for both programming (om HIGH during all address tran-
11. It is necessary to toggle Pin 11
and verification see programming address Tables 5 and 6. Pin 7 sitions while in the Program Verify or Blank Check mode.
The programmable array is addressed as a basic 256 by 8 selecting every eighth product term starting with 0,8, 16,
memory structure with a duplication of the phantom array 24, 32, 40, 48 and 56 corresponding to PROGRAMMED
located at the same addresses as columns 0, 1, 2 and 3. The DATA INPUT on DO through D7 respectively and incre-
ability to address the phantom array as differentiated from menting each product term by one until all 64 PRODUCT
the first 4 columns of the normal array is accomplished by TERMS are addressed. Each of the INPUT TERMS is
taking Pin 7 to Vpp and entering the phantom mode of addressed 8 times corresponding to the 8 groups of individ-
operation as shown in Tables 4 and 6. In either case, phan- ual product terms addressed before being incremented.
tom or normal, product terms are addressed in groups of 8
per Table 5. Notice that this is accomplished by modulo 8
4-12
~ PALC20Series
~~~U~==================================================================
Table 5
Product Term Addresses
Binary Addresses
Pin Numbers . Line Number
(4) (3) (2)
VILP VILP VILP 0 8 16 24 32 40 48 56

VILP VILP VIHP 1 9 17 25 33 41 49 57
VILP VIHP VILP 2 10 18 26 34 42 50 58

VILP VIHP VIHP 3 11 19 27 35 43 51 59
VIHP VILP VILP 4 12 20 28 36 44 52 60
VIHP VILP VIHP 5 13 21 29 37 45 53 61
VIHP VIHP VILP 6 14 22 30 38 46 54 62
VIHP VIHP VIHP 7 15 23 31 39 47 55 63
00 01 02 03 04 05 06 07
Programmed Data Input
Table 6
Input Term Addresses Input Term Addresses
Binary Addresses Binary Addresses
Input Input
Term Pin Numbers Term Pin Numbers
Numbers (9) (8) (7) (6) (5) Numbers (9) (8) (7) (6) (5)
0 VILP VILP VILP VILP VILP 18 VIHP VILP VILP VIHP VILP
1 VILP VILP VILP VILP VIHP 19 VIHP VILP VILP VIHP VIHP
2 VILP VILP VILP VIHP VILP 20 VIHP VILP VIHP VILP VILP
3 VILP VILP VILP VIHP VIHP 21 VIHP VILP VIHP VILP VIHP
4 VILP VILP VIHP VILP VILP 22 VIHP VILP VIHP VIHP VILP
5 VILP VILP VIHP VILP VIHP 23 VIHP VILP VIHP VIHP VIHP
6 VILP VILP VIHP VIHP VILP 24 VIHP VIHP VILP VILP VILP
7 VILP VILP VIHP VIHP VIHP 25 VIHP VIHP VILP VILP VIHP
8 VILP VIHP VILP VILP VILP 26 VIHP VIHP VILP VIHP VILP
9 VILP VIHP VILP VILP VIHP 27 VIHP VIHP VILP VIHP VIHP
10 VILP VIHP VILP VIHP VILP 28 VIHP VIHP VIHP VILP VILP
11 VILP VIHP VILP VIHP VIHP 29 VIHP VIHP VIHP VILP VIHP
12 VILP VIHP VIHP VILP VILP 30 VIHP VIHP VIHP VIHP VILP
13 VILP VIHP VIHP VILP VIHP 31 VIHP VIHP VIHP VIHP VIHP
14 VILP VIHP VIHP VIHP VILP PO VILP VILP Vpp X X
15 VILP VIHP VIHP VIHP VIHP PI VILP VIHP Vpp X X
16 VIHP VILP VILP VILP VILP P2 VIHP VILP Vpp X X
17 VIHP VILP VILP VILP VIHP P3 VIHP VIHP Vpp X X
4-13
START
Vccp=5.0V
Vpp a 13.5V
1
ADDR 1ST
LOCATION
1
M=O
1
PROGRAM
ONE PULSE
OF 0.2 msec
1
M-M+1
1
M ~ 107
YES
l NO
VERIFY
FAIL ONE BYTE?
1 PASS
PROGRAM
ONE PULSE
OF4 (0.2)
(M)msec
1
M = 107
I VERIFY 1 -
YES
1 BYTE
I FAIL
l NO
PASS
I INCREMENT 1 LAST
l ADDR
I NO ADDRESS?
1 YES
READ
ALLBVTES?
I REJECT 1
Vccp = 5.5V FAIL
1 DEVICE
I
l PASS
PROGRAM
COMPLETE
GOOD
DEVICE
0038-18
4-14
~ PALC20Series
~~~NDUcrOR=======================================================================;
PROGRAM PROGRAM VERIFY
INHIBIT
tAH
VIHP- - -
ADDRESS
1.. ADDRESS AO THRU Ag
r-
-
VILP - - - -
f..--tAS_ I.--
tov- :--toz
I-tOS-
VIHP - - - -
T - ~r-
DATA
VILP - - - -
tr I
I
..\...
ItAS_
DATA IN DO THRU 07
-.
:-- -tOH
...l~
DATA OUT DO THRU 07 -
-
i----=--tAH
_L
I
tf
VpP----
~~ - - \
VIHP - - - -
Vpp-- __
VPP
VILP - - - -
VIHP - - - -
PGM/OE
I
tr_
-,,,""
PROGRAM
_tpp_
.... r
\
+-tf
...l
r-
VERIFY 7~
........

VILP - - - -
_tvo_ typ
0038-17
Figure 6. Programming Waveforms Normal Array
PROGRAM PROGRAM VERIFY

INHIBIT
VIHP- -
ADDRESS
VILP- -
). ADDRESS Ao THRU A2, As AND A7
tAH
~L -
-tAS-
Vpp - - -
-i ,,-~
As
VIHP - - -
VILP- - -
VIHP- - -
DATA
-tr r+-tOS-+
~
DATA IN Do THRU 07
..,
- -toy
DATA OUT Do THRU 07

to
- ....
-"i
-toz
VILP---
i
Vpp- - -
tr-
rl-- 1tAS
-
I+- f-tOH 14---tAH
I
tf
Vpp
VIHP- - -
I( \
VILP- - -
Vpp---
tr- ~
'""
- ""I
~
~tf
-k-_
I PROGRAM
VIHP- - -
PGM/QE
VILP- - -
....,
-tpp- ~
r--tVO-
....
~
VERIFY
typ
J
-
0038-18
Figure 7. Program Waveforms Phantom Array
4-15
tf
Vpp----
VIHP - - - -
A,
VILP- - - -
VpP----
VIHP _ - - -
Vpp
VILP- - - -
Vpp----
VIHP - - - -
PGM/ot
VILP - - - - _______ -=:1
0038-19
Figure 8. Activating Program Security
VIHP - - - -
DATA - - - - - - - - - - - - - - - -______________~ DATA OUT A, (NOTE 11
VILP - - - -
tov toz
VpP----
VIHP - - - - ~-----tvp----~~
A2
VILP - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _...;;;j~
0038-20
Figure 9. Verify Program Security
4-16
~ PALC20Series
~~~~UaoR==================================================================
Functional Logic Diagram PAL C 16L8
INPUTS (0 - 31)
~~---- 18 III
t.)~.....- - - - 17
jj 16
CD
I
S!
III:
w 5
I-
ti
~
0
0
II:
IL 15
>C~_---14
>C~_---13
>c_----12
-+~~HHH-44++-++++-~~~HH~+++-~tt=======~~---------ll
67 S 91011 1213 15 1617 19 20 28293031 0038-21
4-17
~ PALC20Series
~~~UaoR================================================================
Functional Logic Diagram PAL C 16R4
INPUTS (0 - 311
~~-+-----------19
i'i 16
UI
I
2
en
:IE
~
w
~
~
U
::I
0
0
a:
II. 15
~~~----~~----13
~~~----~-----12
11
1 23 4667 891011 12131415 18171819 20212223 24252627 28293031

0038-22
4-18
~ CYPRESS PAL C 20 Series
~~~~UaoR==============================================================
INPUTS (0 - 31)
_ _ ~~19
18
II
.-------.-. _ _ 17
c;; 16
'"I
~
III
:IE
a: 5
w
l-
I-
U
::I
0
0
g: 15
.-------.-._-14
13
Ll~'-------;-----12
11
881011 1213 28293031

0038-23
4-19
~~======================================~P~A~L~~C~2~o~s~e~r~ie~s
19
18
17
16
~
I
~
(il
:i:
tr:
L1J 5
~
~
u
~
c
C
tr:
0.
4567 891011 12131415 16171 28293031
4-20
~ PAL C 20 Series
~~~~UcmR==================================================================
NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT NORMALIZED PROPAGATION
SUPPLY VOLTAGE
VS. AMBIENT TEMPERATURE
VS. DELAYvs. SUPPLY VOLTAGE
1.4 r---"""'T--..---r--"'7I 1 . 6 _ - - - - . . . - - - - - -...
1.2
1.41--T---+-----~
1.2 1.1
"""-f"
0
] u ~
u 1.21----l~-+-----_I fil
51
N fil N
:::; 1.0 N :::; 1.0
c( :::;
:I: ~ 1.01-----:3k-----_I ~
a: a:
'"
0 a: 0
z 0.&
o
z z
0.9
0.&1-----+---~~_1
"
0.6/o...-_ _ _ _-'-_ _ _ _.....J
0.&
4.5 5.0 6.0 -55 25 125 4.0 4.5 5.0 5.5 6.0
NORMALIZED PROPAGATION DELAY DELTA PROPAGATION TIME NORMALIZED SETUP TIME

TEMPERATURE
VS. VS. OUTPUT LOADING SUPPLY VOLTAGE
VS.
1.3r-----"""'T------, 20.0 1.2
~
./ 1.1
1.2 15.0
g
fil
~ 1.11-----+--~~-~
!
g
10.0 ./
V "" e
N
:::; 1.0 "" ~
"""-
c(
V
c(
~
~
a:
~
8c a:
0
z
:; .....
5.0 0.9
0.&
200 400 600 800 1000 4.0 4.5 5.0 5.5 6.0
AMBIENT TEMPERATURE (OC) CAPACITANCE (pF) SUPPLY VOLTAGE (V)
NORMALIZED CLOCK
NORMALIZED SETUP TIME NORMALIZED CLOCK TO OUTPUT TO OUTPUT
VS. TEMPERATURE TIME VS. SUPPLY VOLTAGE TIME VS. TEMPERATURE
1.3 .......- - - . . . . . , . . - - - - - . . . , 1.1 """"'-"""'T--"T""--r---.....,
$
51N
:::;

~
a:
oz
0~.....
0--4..L.5---'5.0---5.....
5 -...........
6.0
AMBIENT TEMPERATURE (OC) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC)
DELTA CLOCK TO OUTPUT TIME OUTPUT SINK CURRENT OUTPUT SOURCE CURRENT
VS. OUTPUT LOADING VS. OUTPUT VOLTAGE VS. VOLTAGE
20.0 200 140
~ ~
1
175
V 1 120
15.0
./
to- 150
to-
~ 100 ~
/
!
g 10.0 /
V "" 15a:
a:
::::I
(,J
125
100 /
a:
a:
::::I
(,J
III
&0
r\.
'\

V
(,J
:.: a: 60
~ z j
~
::>
us 76
/ ~
",
III
Q to- 40
1 ::::I
~~c=~:;~V _ ~
:;
5.0 50
~0 / I to- 20
25 ::> ........
oI
0
0.0 0 200 400 600 800 1000 0.0 1.0 2.0 3.0 4.0 1.0 2.0 3.0 4.0
CAPACITANCE (pF) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

0038-25
4-21
~ PALC20Series
~~~~u~================================================================
tpD ts teo Icc Ordering Code Package
Operating
(ns) (ns) (ns) (rnA) Range
20 - - 70 PAL C 16LS-200MB 06 Military
PAL C 16LS-20LMB L61
PAL C 16LS-20WMB W6
PAL C 16LS-20KMB K71
PAL C 16LS-20QMB Q61
25 - - 45 PAL C 16LSL-25PC P5 Commercial
PAL C 16LSL-25VC V5
PAL C 16LSL-25LC L61
PAL C 16LSL-25WC W6
70 PAL C 16LS-25PC/PI P5
PAL C 16LS-25VC/VI V5
PAL C 16LS-25LC L61
PAL C 16LS-25WC/WI W6
PAL C 16LS-30WMB W6
PAL C 16LS-30KMB K71
35 - - 45 PAL C 16LSL-35PC P5 Commercial
PAL C 16LSL-35VC VS
PAL C 16LSL-3SLC L61
PAL C 16LSL-35WC W6
70 PAL C 16LS-35PC/PI P5
PAL C 16LS-35VC/VI V5
PAL C 16LS-3SLC L61
PAL C 16LS-3SWC/WI W6
PAL C 16LS-40WMB W6
PAL C 16LS-4OKMB K71
20 20 IS 70 PAL C 16R4-200MB 06 Military
PAL C 16R4-20LMB L61
PAL C 16R4-20WMB W6
PALC 16R4-20KMB K71
PAL C 16R4-20QMB Q61
25 20 15 45 PAL C 16R4L-2SPC PS Commercial
PAL C 16R4L-2SVC V5
PAL C 16R4L-2SLC L61
PAL C 16R4L-25WC W6
70 PAL C 16R4-25PC/PI PS
PAL C 16R4-25VC/VI VS
PAL C 16R4-2SLC L61
PAL C 16R4-2SWC/WI W6
4-22
~ PAL C20Series
~~~~UcrOR================================================================
Ordering Information (Continued)
tpD ts teo Icc Operating
Ordering Code Package
(os) (ns) (ns) (rnA) Range
30 25 20 70 PAL C 16R4-30DMB D6 Military
PALC 16R4-30WMB W6
PALC 16R4-30KMB K71
PAL C 16R4-3OQMB Q61
35 30 25 45 PAL C 16R4L-35PC P5 Commercial
PAL C 16R4L-35VC V5
PAL C 16R4L-35LC L61
PAL C 16R4L-35WC W6
70 PAL C 16R4-35PC/PI P5
PAL C 16R4-35VC/VI V5
PAL C 16R4-35LC L61
PAL C 16R4-35WC/WI W6
PAL C 16R4-40WMB W6
PAL C 16R4-40KMB K71
PAL C 16R6-20WMB W6
PAL C 16R6L-25VC V5
PAL C 16R6L-25WC W6
PAL C 16R6-25LC L61
PAL C 16R6-30WMB W6
PAL C 16R6L-35VC V5
PAL C 16R6L-35WC W6
PAL C 16R6-35LC L61
4-23
~ PALC20Series
~~~U~==============================================================
tpD ts teo Icc Operating
Ordering Code Package
(ns) (os) (os) (mA) Range
40 35 25 70 PAL C 16R6-400MB 06 Military
PAL C 16R6-4OLMB L61
PAL C 16R6-4OWMB W6
PALC 16R6-4OQMB Q61
- 20 15 70 PAL C 16RS-20DMB D6 Military
PAL C 16RS-20LMB L61
PAL C 16RS-20WMB W6
PAL C 16RS-20KMB K71
PAL C 16RS-2OQMB Q61
- 20 15 45 PAL C 16RSL-25PC P5 Commercial
PAL C 16RSL-25VC V5
PAL C 16RSL-25LC L61
PAL C 16RSL-25WC W6
70 PAL C 16RS-25PC/PI P5
PAL C 16RS-25VC/VI V5
PAL C 16RS-25LC L61
PAL C 16RS-25WC/WI W6
- 25 20 70 PAL C 16RS-300MB 06 Military
PAL C 16RS-30LMB L61
PALC 16RS-30WMB W6
PAL C 16RS-30KMB K71
PAL C 16RS-3OQMB Q61
- 30 25 45 PAL C 16RSL-35PC P5 Commercial
PAL C 16RSL-35VC V5
PAL C 16RSL-35LC L61
PAL C 16R8L-35WC W6
PAL C 16RS-35LC L61
- 35 25 70 PAL C 16R8-400MB 06 Military
PAL C 16R8-4OLMB L61
PAL C 16RS-4OWMB W6
PAL C 16R8-4OKMB K71
4-24
~ PALC20Series
~~~U~==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Vpp 1,2,3
Icc 1,2,3
Ioz 1,2,3
tpD 9,10,11
tpzx 9,10,11
teo 9,10,11
ts 9,10,11
tH 9,10,11
4-25
PRELIMINARY PLDC18G8
CYPRESS
SEMICONDUCTOR CMOS Generic 20 Pin
Programmable Logic Device
Features
Generic architecture to replace - Security feature prevents
Fast logic pattern duplication
- Commercial: tpD = 12 ns, standard logic functions
teo = 10 ns, ts = 12 ns including: 10H8, 12H6, 14H4, - > 2000V input protection for
- Military: tpD = 15 ns, 16H2, 10LS, 12L6, 14IA, 16L2, electrostatic discharge
teo = 12 ns, ts 15 ns 10P8, 12P6, 14P4, 16P2, 16H8,
16LS, 16P8, 16R8, 16R6, 16R4,
Low power 16RP8, 16RP6, 16RP4, 18P8, Cypress PLD devices are high speed
- Icc max.: 80 mA, commercial 16V8 electrically programmable Logic De-
- ICC max.: 110 mA, military
vices. These devices utilize the sum of
Commercial and military Eight product terms and one OE
product term per output products (AND-OR) structure provid-
temperature range ing users the ability to program custom
User-programmable output cells CMOS EPROM technology for logic functions for unique require-
- Selectable for registered or reprogrammability ments.
combinatorial operation Highly reliable In an unprogrammed state the AND
- Output polarity control - Uses proven EPROM gates are connected via EPROM cells
- Output enable source technology to both the true and complement of ev-
selectable from pin 11 or - Fully AC and DC tested ery input. By selectively programming
product term the EPROM cells, AND gates may be
Logic Symbol, DIP and SOJ Pinout

18G8
0139-1
LCCPinout PLCCPinout
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I 8 14 I/O
0139-2 0139-3
4-26
~ PRELIMINAR Y PLD C 18G8
~~~~u~==============================================================
Selection Guide
Generic
Part
ICC (rnA) tpD (ns) ts teo
Number Com Mil Com Mil Com Mil Com Mil
18G8-12 80 12 12 10
18G8-15 80 110 15 15 12 15 12 12
18G8-20 110 20 20 15
Functional Description (Continued) providing the next state. The register is clocked by the
connected to either the true or complement or disconnect-
ed from both true and complement inputs.
Cypress PLD C ISGS uses an advanced O.S micron CMOS
signal from Pin 1. The register is initialized on power up to
Q output LOW and Q output HIGH.
In both the Combinatorial and Registered configurations,
the source of the "OUTPUT ENABLE" signal can be indi-
II
technology and a proven EPROM cell as the programma- vidually chosen with architecture bit 'C2'. The OE signal
ble element. This technology and the inherent advantage of may be generated within the array, or from the external
being able to program and erase each cell enhances the OE pin (Pin 11). The Pin 11 allows direct control of the
reliability and testability of the circuit. This reduces the outputs, hence having faster enable/disable times.
burden on the customer to test and to handle rejects.
Each output cell can be configured for "OUTPUT PO-
A preload function allows the registered outputs to be pre- LARITY". The output can be either Active HIGH or Ac-
set to any pattern during testing. Preload is important for tive LOW. This option is controlled by architecture bit
testing the functionality of the Cypress PLD device. 'CO'.
18G8 Functional Description Along with this increase in functional density, the Cypress
PLD C ISGS provides lower power operation through the
The PLD C ISGS is a generic 20 pin device that can be use of CMOS technology, increased testability with a regis-
programmed to logic functions which include but are not ter preload feature and guaranteed AC performance
limited to: lOHS, 12H6, 14H4, 16H2, lOLS, 12L6, 14L4, through the use of a phantom array. The phantom array
16L2, lOPS, 12P6, 14P4, 16P2, 16HS, 16LS, 16PS, 16RS, allows the ISGS to be programmed with a test pattern and
16R6, 16R4, 16RPS, 16RP6, 16RP4, lSPS, 16VS. Thus, tested prior to shipment for full AC specifications without
the PLD C ISGS provides significant design, inventory and using any of the functionality of the device specified for the
programming flexibility over dedicated 20 pin devices .. It is product application. In addition, this saI?e ph~nto.m array
executed in a 20 pin 300 mil molded DIP and a 300 mll may be used to test the PLD C ISGS at mcommg mspec-
windowed Cerdip. It provides up to IS inputs and S out- tion before committing the device to a specific function
puts. When the windowed CERDIP is exposed to UV through programming.
light, the ISGS is erased and then can be reprogrammed.
The Programmable Output Cell provides the capability of Programmable Output Cell
defining the architecture of each output individually. Each
of the 10 output cells may be configured with "REGIS-
TERED" or "COMBINATORIAL" outputs, "ACTIVE
HIGH" or "ACTIVE LOW" outputs, and "PRODUCT
TERM" or "PIN 11" generated output enables. Four Ar-
chitecture Bits determine the configurations as shown in
Table 1. A total of sixteen different configurations are pos-
sible. The default or unprogrammed state is REGIS-
TERED/ACTIVE/LOW/Pin 11 OE. The entire Program-
mable Output Cell is shown in Figure 1.
The architecture bit 'Cl' controls the REGISTERED/
COMBINATORIAL option. In either "COMBINATO-
RIAL" or "REGISTERED" configuration, the output can
serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either C3 _ _.L.-....J
"REGISTERED" or "COMBINATORIAL" configura-

tion, the output of the register may be fed back to th:
2
cc, ==::=========::::::tTl---'
-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_--I___ ----
co _ _...J...__
array. This allows the creation of control-state machmes by
0139-4
Figure 1
4-27
~ PRELIMINARY PLD C 18G8
~~~U~==================================================================
Maximum Ratings
Storage Temperature ........... '" . -65C to + 150C Static Discharge Voltage ........... " ........ >2oo1V
Range Vee
Temperature
Commercial OCto +75C 5V 5%
DC Programming Voltage ...................... 13.0V
Electrical Characteristics Over Operating Range (Unless Otherwise Noted) [7)

Vee = Min. 10H = -3.2mA Commercial
VIN = VIH or VIL 10H = - 2mA Military
Vee = Min. 10L = 24mA Commercial
VIN = VIH or VIL 10L = 12mA Military
VIH Input HIGH Level Guaranteed Input Logical HIGH[1] Voltage for all Inputs 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW[I] Voltage for all Inputs 0.8 V
IIX Input Leakage Current Vss ::;; VIN ::;; Vee -10 10 IJ-A
Vpp Programming Voltage @ Ipp = 50 mA Max. 12.0 13.0 V
Ise Vee = Max., VOUT = 0.5V[2] -30 -90 mA
Current
0::;; VIN::;; Vee Commercial 80
Icc Power Supply Current mA
Vee = Max., lOUT = 0 mA Military 110
loz Output Leakage Current Vee = Max., Vss::;; VOUT::;; Vee -40 40 mA
Capacitance [3]
pF
COUT Output Capacitance VIN = 2.0V, Vee = 5.0V 8
ft n
AC Test Loads and Waveforms (Commercial)
R1 160.n R1 160.n
(319.n MIL) (319.n MIL)
OUTP~~ R2
OUTP~~ R2
INCLUDING
50 pF
I
1 24.n
(236.n MIL)
5 pF
I 1 24.n
(236.n MIL)
~~D - - -
SCOPE
0139-5
Figure2a Figure 2b
Equivalent to: THEVENIN EQUIVALENT (Commercial) Equivalent to: THEVENIN EQUIVALENT (Military)
70.n 136.n
OUTPUT ~2.18V OUTPUT ~2.13V
0139-6 0139-7
4-28
~ PRELIMINAR Y PLD C 18G8
~~~U~==================================================================
Configuration Table [8]
Table 1
C3 C2 Cl Co Configuration
0 0 0 0 Active LOW, Registered Mode, Registered Feedback, Pin 11 OE
0 0 0 1 Active HIGH, Registered Mode, Registered Feedback, Pin 11 OE
0 0 1 0 Active LOW, Combinatorial Mode, Registered Feedback, Pin 11 OE
0 0 1 1 Active HIGH, Combinatorial Mode, Registered Feedback, Pin 11 OE
0 1 0 0 Active LOW, Registered Mode, Registered Feedback, Product Term OE
0 1 0 1 Active HIGH, Registered Mode, Registered Feedback, Product Term OE
0 1 1 0 Active LOW, Combinatorial Mode, Registered Feedback, Product Term OE
0 1 1 1 Active HIGH, Combinatorial Mode, Registered Feedback, Product Term OE
1 0 0 0 Active LOW, Registered Mode, Pin Feedback, Pin 11 OE
1 0 0 1 Active HIGH, Registered Mode, Pin Feedback, Pin 11 OE
1 0 1 0 Active LOW, Combinatorial Mode, Pin Feedback, Pin 11 OE
1 0 1 1 Active HIGH, Combinatorial Mode, Pin Feedback, Pin 11 OE
1 1 0 0 Active LOW, Registered Mode, Pin Feedback, Product Term OE
1 1 0 1 Active HIGH, Registered Mode, Pin Feedback, Product Term OE
1 1 1 0 Active LOW, Combinatorial Mode, Pin Feedback, Product Term OE
1 1 1 1 Active HIGH, Combinatorial Mode, Pin Feedback, Product Term OE
Switching Characteristics PLD C 18G8 Over Operating Range[4, 9]

Commercial Military
Parameters Description -12 -15 -15 -20 Units
Input or Feedback to
tpD 12 15 15 20 ns
Non-Registered Output
tEA Input to Output Enable 12 15 15 20 ns
tER Input to Output Disable 12 15 15 20 ns
tpzx Pin 11 to Output Enable 10 12 12 15 ns
tpxz Pin 11 to Output Disable 10 10 10 15 ns
teo Clock to Output 10 12 12 15 ns
ts Input or Feedback Setup Time 12 12 15 20 ns
tH Hold Time 0 0 0 0 ns
tp[5] Clock Period 22 24 27 35 ns
tWH Clock High Time 7 8 9 10 ns
tWL Clock Low Time 8 9 10 11 ns
fMAX[6] Maximum Frequency 45.5 41.6 37.0 28.6 MHz
Notes:
1. These are absolute values with respect to device ground and all over- 6. fMAX, minimum guaranteed operating frequency, is that guaranteed
shoots due to system or tester noise are included. for state machine operation and is calculated from fMAX = I!(ts +
2. Not more than one output should be tested at a time. Duration of the teo). The minimum guaranteed fMAX for registered data path opera-
short circuit should not be more than one second. VOUT = 0.5V has tion (no feedback) can be calculated as the lower of I/(twH + twd
been chosen to avoid test problems caused by tester ground degrada- or I!(ts + tH)'
tion. 7. TA is the "instant on" case temperature.
3. Tested initially and after any design or process changes that may 8. In the virgin or unprogrammed state, a configuration bit location is in
affect these parameters. the "0" state.
4. Figure 2a test load used for all parameters except tER, tpzx and tpxz. 9. The parameters tER and tpxz are measured as the delay from the
Figure 2b test load used for tER, tpzx and tpxz. input disable logic threshold transition to VOH - 0.5V for an enabled
5. tp, minimum guaranteed clock period is that guaranteed for state ma- HIGH output or VOL + 0.5V for an enabled LOW output.
chine operation and is calculated from tp = ts + teo. The minimum
guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (tWH + twd or (ts + tH)'
4-29
~~~~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Waveform
INPUTS,I/O,
~:~~~~~:DlW~~ ______ ~CC~~~~ ______________________________________~________~________
CP
REGISTERED ---...,cr.a7J\Ir---------t------\)ot.."(+~+J+_--~1+(
OUTPUTS: _ _...J.JQOl3Q11~----~---Ju..u..U -+____
\"u"a...._ _ _ _ _ _ _--!_ _ _ _
COMBINATORIAL
OUTPUTS:
t~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __________________________________ -'~~~~~+-~H~~~~_tE_A_
r-
0139-8
Note:
For more information regarding PLD devices, refer to the Application Brief in the Appendix.
4-30
~ CYPRESS PRELIMINAR Y PLD C 18G8
~~IOO~UcrOR==============================================================~==
Functional Logic Diagram PLD C 18G8
INPUT LINES
~rt> PI P3
OE
Po P2 0 4 8 12 16 20 24 28 32
-
~
0
: ""
~ OUTPUT
CELL 19
~7 ~I>
-

-_~
.... ....
OE
-
. ....--
~~
0
""
~ OUTPUT
CELL 18
2 ~7
~I>
~-
..
OE
-==
:~
0
: ""
~ OUTPUT
CELL 17
~I>
3,~ 7
~~
p
OE
-- .. L.-.-
r---f-
~
0
...
"
../ OUTPUT
CELL :- 16
4 -b
.. -
7
. ....
_~ ~t>
"'---
OE
.....--
~
0
I-
(/)
~
c:::
I.&J
""
~ OUTPUT
CELL
I-
15
5 ~7 _~ ~I>
l-
I- p
.... I-
e.)
L.-.-
:::> .....--
Q OE f-r---,
o 0
c:::
c....
. ""
~ OUTPUT f-
~
'"" t> CELL 14
~~
... -
6 ....1'.:::.7
--
OE
0
....
-L.-.-
I-r--
""
~ OUTPUT I-<
~I
CELL f- 13
~I>
7 ~7 _~
.... I-
=
p
OE t-----.
0
""
~ OUTPUT
8; - b
-7 ~t>
CELL
H>o-r 12
... -- " ' - - - 4~
l~
9l - b
.. - - 1
0139-9
4-31
~~~UaoR================================================================
Ordering Code
(ns) Type Range
12 PLO C ISGS-12PC PS Commercial
PLO C ISGS-12WC W6
PLO C ISGS-12VC VS
PLO C ISGS-12JC J61
IS PLO C lSGS-lSPC PS Commercial
PLO C ISGS-lSWC W6
PLO C ISGS-lSVC VS
PLO C ISGS-lSJC J61
PLO C ISGS-lS0MB 06 Military
PLO C ISGS-lSWMB W6
PLO C ISGS-lSLMB L61
20 PLO C ISGS-200MB 06 Military
PLO C ISGS-20WMB W6
PLO C ISGS-20LMB L61
4-32
PLD C 20GIOB/PLD C 20GIO
CYPRESS
SEMICONDUCTOR CMOS Generic 24 Pin
Reprogrammable Logic Device
Fast Generic architecture to replace Cypress PLD devices are high speed
- Commercial: tpD = 15 ns, standard logic functions electrically programmable Logic De-
teo = 10 ns, ts = including: 20LI0, 20L8, 20R8, vices. These devices utilize the sum of
II
12 ns
- Military: tpD = 20 ns, 20R6, 20R4, 12LI0, 14L8, 16L6, products (AND-OR) structure provid-
teo = 15 ns, ts = 17 ns 18L4, 20L2 and 20V8 ing users the ability to program custom
Eight product terms and one OE logic functions for unique require-
Low power ments.
- Icc max.: 70 mA, product term per output
Commercial CMOS EPROM technology for In an unprogrammed state the AND
- Icc max.: 100 mA, Military reprogrammability gates are connected via EPROM cells
to both the true and complement of ev-
Commercial and military Highly reliable
temperature range ery input. By selectively programming
- Uses proven EPROM the EPROM cells, AND gates may be
User-programmable output cells technology connected to either the true or comple-
- Selectable for registered or - Fully AC and DC tested ment or disconnected from both true
combinatorial operation - Security feature prevents and complement inputs.
- Output polarity control logic pattern duplication
- Output enable source - > 2000V input protection for Cypress PLD C 20G 10 uses an ad-
selectable from pin 13 or electrostatic discharge vanced 0.8 micron CMOS technology
product term - 10% power supply voltage and a proven EPROM cell as the pro-
and higher noise immunity
Logic Symbol
20GI0
0053-15
LCC Pinout STD PLCC Pinout JEDEC PLCC Pinout[16]

___ ~ J!~~
He
I/o Ne I/O
I/O I I/o
I/O I/O
I/O He I/O Ne
I/o I/o I
I/O I I/o
He He
0053-17 ---~~oo
> ~ s.~ 0053-26
4-33
~CiPi?ESS PLD C 20G10B/PLD C 20G10
.r~~==============~~~
Selection Guide
Generic
Part Icc tpD ts teo
Number L Com/lnd Mil Com/lnd Mil Com/lnd Mil Com/lnd Mil
2oolOB-15 - 70 - 15 - 12 - 10
2OGlOB-20 - 70 100 20 20 - 17 15
2oo10B-25 - - 100 - 25 18 15
20010-25 - 55 - 25 - 15 - 15
20010-30 - - 80 - 30 - 20 20
20010-35 - 55 - 35 - 30 25
20010-40 - - 80 - 40 35 25
Functional Description (Continued) signal from Pin 1. T~ register is initialized on power up to

Q output LOW and Q output HIGH.
grammable element. This technology and the inherent ad-
vantage of being able to program and erase each cell en- In both the Combinatorial and Registered configurations,
hances the reliability and testability of the circuit. This re- the source ofthe "OUTPUT ENABLE" signal can be indi-
duces the burden on the customer to test and to handle vidually chosen with architecture bit 'C2'. The OE signal
rejects. may be generated within the array, or from the external
OE pin (Pin 13). The Pin 13 allows direct control of the
A preload function allows the registered outputs to be pre- outputs, hence having faster enable/disable times.
set to any pattern during testing. Preload is important for
testing the functiohality of the Cypress PLD device. Each output cell can be configured for "OUTPUT PO-
LARITY". The output can be either Active HIGH or Ac-
20GIO Functional Description tive LOW. This option is controlled by architecture bit
'CO'.
The PLD C 20GI0 is a generic 24 pin device that can be
programmed to logic functions which include but are not Along with this increase in functional density, the Cypress
limited to: 20L10, 20L8, 20R8, 20R6, 20R4, l2L10, l4L8, PLD C 20G 10 provides lower power operation through the
16L6, 18L4, 20L2 and 20V8. Thus, the PLD C 20GI0 use of CMOS technology, increased testability with a regis-
provides significant design, inventory and programming ter preload feature and guaranteed AC performance
flexibility over dedicated 24 pin devices. It is executed in a through the use of a phantom array. The phantom array
24 pin 300 mil molded DIP and a 300 mil windowed Cer- allows the 20GI0 to be programmed with a test pattern
dip. It provides up to 22 inputs and 10 outputs. When the and tested prior to shipment for full AC specifications
windowed CERDIP is exposed to UV light, the 20GI0 is without using any of the functionality of the device speci-
erased and then can be reprogrammed. fied for the product application. In addition, this same
phantom array may be used to test the PLD C 20GI0 at
The Programmable Output Cell provides the capability of incoming inspection before committing the device to a spe-
defining the architecture of each output individually. Each cific function through programming.
of the 10 output cells may be configured with "REGIS-
TERED" or "COMBINATORIAL" outputs, "ACTIVE Programmable Output Cell
HIGH" or "ACTIVE LOW" outputs, and "PRODUCT
TERM" or "PIN 13" generated output enables. Three Ar- r--------------------------,
OE PRODUCT TERN
chitecture Bits determine the configurations as shown in
Table 1 and in Figures 2 through 9. A total of eight differ-
ent configurations are possible, with the two most common 10
shown in Figure 4 and Figure 6. The default or unpro-

grammed state is REGISTERED/ACTIVE LOW/
PRODUCT TERM OE as shown in Figure 2. The entire
Programmable Output Cell is shown in Figure 1.
The architecture bit 'Cl' controls the REGISTERED/
COMBINATORIAL option. In the "COMBINATORI-
AL" configuration,the output can serve as an I/O pin, or
if the output is disabled, as an input only. Any unused
inputs should be tied to ground. In the "REGISTERED"
configuration, the output of the register is fed back to the C2==t:::t=======:t-t~
C1
array. This allows the creation of control-state machines by co _ _-!&.__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_...J__
providing the next state. The register is clocked by the PIN13 0053-32
Figure 1
~ PLD C 20GIOB/PLD C 20GIO
~~~NDU~ ==================================================================~
Configuration Table
Table 1
Figure C2 Cl Co Configuration
2 0 0 0 Product Term OElRegisteredlActive LOW
3 0 0 1 Product Term OElRegisteredlActive HIGH
6 0 1 0 Product Term OE/CombinatoriallActive LOW
7 0 1 1 Product Term OE/Combinatorial/Active HIGH
4 1 0 0 Pin 13 OElRegisteredlActive LOW
5 1 0 1 Pin 13 OE/RegisteredlActive HIGH
8 1 1 0 Pin 13 OE/Combinatorial/Active LOW
9 1 1 1 Pin 13 OE/Combinatorial/Active HIGH
Registered Output Configurations
C2 = 0
C, = 0
Co = 1
0053-37 0053-38
Figure 2. Product Term OEIActive LOW Figure 3. Product Term OEIActive HIGH
C2 = 1
C, = 0
Co = 0
0053-39 0053-40
Figure 4. Pin 13 OEIActive LOW Figure 5. Pin 13 OE/Active HIGH
Combinatorial Output Configurations [6]
C2 = 0
C, = 1
Co = 1
0053-33 0053-34
Figure 6. Product Term OEIActive LOW Figure 7. Product Term OEIActive HIGH
~ PIN13
Figure 8. Pin 13 OEIActive LOW

0053-35
~ PIN13
0053-36
Figure 9. Pin 13 OE/Active HIGH
4-35
~~~~================================================================
Maximum Ratings
Storage Temperature ............... - 65C to + 150C Static Discharge Voltage ..................... >2001V
Power Applied .................... -55C to + 125C Latchup Current .......................... > 200 mA
Supply Voltage to Ground Potential .... ~O.SV to + 7.0V Operating Range
in High Z State ...................... -O.SV to +7.0V Ambient
Range Vee
Temperature
DC Input Voltage .................. - 3.0V to + 7.0V
Commercial O"Cto +75C 5V lO%
Military [8] - 55C to + 125C 5V lO%
DC Programming Voltage
PAL C 22VlOB and CG7C323B-A ... '" ....... 13.0V Industrial - 40C to + 85C 5V 10%
PAL C 22VlO and CG7C323-A ............... 14.0V

Vee = Min. IOH = -3.2mA COM'L/IND
VIN = VIH or VIL IOH = -2mA Military
Vee = Min. IOL = 16mA COM'L/IND
VIN = VIH or VIL IOL = 12mA Military
VIR Input HIGH Level Guaranteed Input Logical HIGH[l] Voltage for all Inputs 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW[t] Voltage for all Inputs 0.8 V
IIX Input Leakage Current VSS :5: VIN :5: Vee -lO 10 p.A
Ise Vee = Max., VOUT = 0.5V[2] -90 mA
Current
COM'L/IND -15, -20 70
0:5: VIN:5: Vee COM'L/IND -25, -35 55
Iec Power Supply Current mA
Vee = Max., lOUT = OmA Military -20, -25 100
Military -30, -40 80
Ioz Output Leakage Current Vee = Max., Vss:5: VOUT:5: Vee -100 100 p.A
4-36
~~~NDUcrOR =====================================================================
Capacitance [3]
pF
COUT Output Capacitance VIN = 0, Vee = 5.0V 7
Switching Characteristics PLD C 20GIO Over Operating Rangel4, 7]

Commercial Military
Parameters Description B-15 B-20 -25 -35 B-20 B-25 -30 -40 Unit!
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input to Output
tpD 15 20 25 35 20 25 30 40 ns
Propagation Delay[15]
Input to Output
tEA 15 20 25 35 20 25 30 40 ns
Enable Delay
Input to Output
tER 15 20 25 35 20 25 30 40 ns
Disable Delay[lO]
OE Input to Output
tpzx 12 15 20 25 17 20 25 25 ns
Enable Delay
OE Input to Output
tpzx 12 15 20 25 17 20 25 25 ns
Disable Delay
Clock to Output
tco Delay[15] 10 12 15 25 15 15 20 25 ns
Input or Feedback
ts 12 12 15 30 15 18 20 35 ns
Setup Time
tH Input Hold Time 0 0 0 0 0 0 0 0 ns
External Clock
tp 22 24 30 55 30 33 40 60 ns
Period (Teo + ts)
tWH Clock Width HIGH[3,9] 8 10 12 17 12 14 16 22 ns
tWL Clock Width LOW[3,9] 8 10 12 17 12 14 16 22 ns
External Maximum
fMAXI Frequency 45.4 41.6 33.3 18.1 33.3 30.3 25.0 16.6 MHz
(l/(tco + ts[11]
Data Path
fMAX2 Maximum Frequencr 62.5 50.0 41.6 29.4 41.6 35.7 31.2 22.7 MHz
(l/(twH + tWL[12
Internal Feedback
fMAX3 Maximum Frefuenc y 66.6 45.4 35.7 20.8 33.3 32.2 28.5 18.1 MHz
(l/(tCF + ts 13]
Register Clock to
tCF Feedback Input[14]
3.0 10 13 18 13 13 15 20 ns
Notes:
1. These are absolute values with respect to device ground and all over-
shoots due to system or tester noise are included. 10. This parameter is measured as the time after output disable input
that the previous output data state remains stable on the output. This
2. Not more than one output should be tested at a time. Duration of the delay is measured to the point at which a previous high level has
short circuit should not be more than one second. VOUT = O.SV has fallen to 0.5 volts below VOH Min. or a previous low level has risen
been chosen to avoid test problems caused by tester ground degrada- to 0.5 volts above VOL Max. Please see Figure 10 for enable and
tion. disable waveforms and measurement reference levels.
3. Tested initially and after any design or process changes that may II. This specification indicates the guaranteed maximum frequency at
affect these parameters. which a state machine configuration with external feed back can
4. Figure 11a test load used for all parameters except tER, tpzx and operate.
tpxz. Figure lIb test load used for tER, tpzx and tpxz. See Figure 10 12. This specification indicates the guaranteed maximum frequency at
for waveforms. which an individual output register can be cycled.
5. Preliminary specifications. 13. This specification indicates the guaranteed maximum frequency at
6. Bidirectional I/O configurations are possible only when the combina- which a state machine configuration with internal only feed back can
torial output option is selected. operate. This parameter is tested periodically by sampling produc-
7. See the last page of this specification for Group A subgroup testing tion product.
information. 14. This parameter is calculated from the clock period at fMAX internal
8. TA is the "instant on" case temperature. (fMAX3) as measured (see note 13 above) minus ts.
9. Tested by periodically sampling production product. 15. This specification is guaranteed for all device outputs changing state
in a given access cycle.
4-37
~~~UcrOR=====================================================================
1.5V
a.}v ~k
tPXZ( -) VOH
Vx 0053-42
rr
tPXZ( +) 2.6V Vx
VOL atv 0053-43
tpZX( +) Vthc
Vx atv rr VOH
0053-44
a.}v ~I:
tpZX( -) Vthc
Vx
VOL 0053-45
l.5V
a.}v ~C-
tER( -)
VOH
Vx 0053-42
tER( + ) 2.6V
VOL atv rr Vx
0053-43
tEA( +) Vthc
Vx
a.}v rr- VOH
0053-44
a.}v ~k
tEA( -) Vthc
Vx
VOL 0053-45
n n
Rl 238.0. Rl 238.0.
(319.0. MIL) (319.0. MIL) INPUT PULSES
OUTP~~ R2
OUTP~~ R2
3 . 0 V - - - - : : i ! o - - - -......
50pF
I=
170.0.
(236.0. MIL)
5pF
I 170.0.
(236.0. MIL) GND--.....;~
INCLUDING
~~
SCOPE
= = = 0053-6
s; 5 ns
0053-8
Figure 12
Figure 11a Figure 11b
99.0. 136.0.
OUTPUT ~2.a8V=Vthc OUTPUT ~2.13V=Vthm
0053-7 0053-24
Switching Waveforms
INPUTS. 1/0.
~:~~~~:D~~_~ __ ~~~OO~~ __________________~____~~____
CP
REGISTERED
OUTPUTS: ---'lL&.JI&lfJ\-----+---~.&..~
COMBINATORIAL --------,~~'1\}.r--------------~~~~~~~!+t
OUTPUTS: --------..J.Wll~~t_--------------a.~r;f "'"",",___
0053-9
Note:
For more information regarding PLD devices, refer to the Application Brief in the Appendix.
4-38
~CYPRfSS PLD C 20GIOB/PLD C 20GIO
~~~~O~UcrOR========================================================~==
Functional Logic Diagram PLD C 20GIO
INPUT LINES
~o.{> P, P3
Po P2 0 4 8 '2 16 20 24 28 32 36 40
-=ihr
OE
0
~ CELL 23
~7':'", ... ~
~
OE
;
=
[b
0
:ct
2 ~' P
i>- ~
OUTPUT
~
CELL 22
II
OE ' ::=
h
0;; , g:f
~ )--- OUTPUT
CELL 21
~7 :B=J >
3 ,
~ .;
~ .. ,=
OE
"b
0
8>- OUTPUT
~CELL 20
4 ~', =B=1c1-
OE :
;:::::
:;;-,
0
~
OE
0
ti:>-~
::ts::=I
-
~~ >
-
~
b
OUTPUT
CELL 19
6.~
O~ ;.
>--
A- ~
=
b
OUTPUT
CELL 18
b
~
: - t::i J-- OUTPUT
CELL 17
!:::::I
7 ~ ~ >
;::=:
5 - H
8 ~
-
:;.
OE
J:tJ---
H
~~
~
=
h
OUTPUT ""
CELL 16
b
0
IP~
OUTPUT ~
CELL 15
9
...l'::.t 7 , ,
> ~
=
:.: .~
1
OE
0
: -,:
- >-- OUTPUT
..... 7- , ~~CELL ~1 4
10 -I
.....'" - ~~
11 -I
- 13
0053-23
4-39
~~~U~================================================================
The "TOP TEST" and "BOTTOM TEST" feature, allow
connection of all input terms to either pin 23 or 13. These
Wavelengths of light less than 4000 Angstroms begin to locations may be programmed and subsequently exercised
erase the PLO C 20G 10. For this reason, an opaque label in the "TOP TEST" and "BOTTOM TEST" mode. Like
should be placed over the window if the device is exposed the Phantom array above, this feature has no effect in the
to sunlight or fluorescent lighting for extended periods of normal mode of operation. Cells in the PHANTOM AR-
time. In addition, high ambient light levels can create hole- RAY, TOP TEST, and BOTTOM TEST areas are pro-
electron pairs which may cause "blank" check failures or grammed at Cypress during the manufacturing operation,
"verify errors" when programming "windowed" parts. and they therefore will be programmed when received in a
This phenomenon can be avoided by use of an opaque label non-windowed package by the user. Consequently, the user
over the window during programming in high ambient will normally have no need to program these cells.
light environments.
The architecture bits Co, Cl and C2 are used to configure
The recommended dose for erasure is ultraviolet light with each programmable output cell individually. Co selects out-
a wavelength of 2537 Angstroms for a minimum dose (UV put polarity, Cl selects the combinatorial or registered
intensity X exposure time) of25 Wsec/cm2. For an ultra- mode of operation and C2 selects the source of output en-
violet lamp with a 12 m W / cm2 power rating, the exposure able. If the registered mode of operation is selected, the
would be approximately 35 minutes. The PLO C 20G 10 feedback path is automatically selected to be from the reg-
needs to be placed within 1 inch of the lamp during era- ister. In the combinatorial mode the feedback path is auto-
sure. Permanent damage may result if the device is exposed matically selected to be from the I/O pin. In this combina-
to high intensity UV light for an extended period of time. torial mode, the output from the array may be fed into the
7258 Wsec/cm2 is the recommended maximum dosage. array or if the output is deselected using the output enable
product term the pin may be used as an external input.
Device Programming There is not a mode where the I/O pin may be used as a
The PLO C 20G 10 can be programmed on inexpensive combinatorial output or an input pin, while the register is
conventional PROM/EPROM programmers with appro- used as a state register. The architecture bits are pro-
priate personality or socket adapters and the CY3000 grammed as a separate item during normal programming.
QuickPro programmer. Once the PLO device is pro- An I/O pin is configured to be an input by programming
grammed, one additional location can be programmed to the output cell into a combinatorial mode and disabling the
prohibit logic pattern verification. This security feature ouput with the output enable product term.
gives the user additional protection to safeguard his propri-
etary logic. This feature is highly reliable and due to Pinout
EPROM technology it is impossible to visually read the The PLO C 20GlO PROGRAMMING pinout is shown in
programmed cell locations. Figure 13. In the Programming pinout configuration, the
The PLO C 20GI0 has multiple programmable functions. device may be programmed and verified for the NORMAL
In addition to the normal array, a "PHANTOM" array, mode of operation and also programmed, verified and op-
"TOP and BOTTOM TEST" and a "SECURITY" feature erated in PHANTOM and TEST modes. These special
are programmable. The PLO C 20GI0 security mecha- modes of operation are achieved through the use of super-
nism, when invoked, prevents access to the "NORMAL" voltages applied to certain pins. Care should be exercised
and "TOP/BOTTOM TEST" array. The "PHANTOM" when entering and exiting these modes, paying specific at-
array feature is still accessible, allowing programming and tention to both the operating modes as specified in Table 1
verification of the pattern in the "PHANTOM" array. and the sequencing of the supervoltages as shown in the
Functional operation of all other features is allowed re- timing diagrams.
gardless of the state of the "SECURITY BIT". In addition,
the device contains 10 programmable output cells which Programming Pinout
are programmed to configure the device functionality for
each specific application. Vpp vee
The logic array is divided into a "NORMAL" array and a AO DO
"PHANTOM" array. The normal array is used to config-
A1 01
ure the device to perform a specific function as required by
the user, and the phantom array is provided as a test array A2 02
for Cypress' testing the device prior to user programming A3 03
thus assuring a reliable, thoroughly tested product. The A4 04
"PHANTOM" array contains four additional columns
connected to input pins 2 (TRUE), 7 (INVERTING), 10 A5 05
(TRUE) and 11 (TRUE). These inputs may be pro- A6 06
grammed to be connected to all normal product terms. A7 07
This allows all sense amplifiers and programmable output A8 08
cells to be exercised for both functionality and performance
after assembly and prior to shipment. These features are in A9 09
addition to the normal array. They do not affect normal Vss PGMM
operation, allowing the user full programming of the nor-
mal array, while allowing the device to be fully tested. 0053-27
Figure 13
4-40
~~~~UcrOR================================================================
These provide NORMAL operation, PHANTOM opera-
tion, TOP TEST, BOTTOM TEST and a register preload
With the exception of the Security bit, all arrays are pro- feature for testing.
grammed in a similar manner. The data to be programmed
is represented by a "1" or "0" on the I/O pins. A "1" In the normal operating mode, all signals are TTL levels
indicates that an unprogrammed location is to be pro- and the device functions as it is internally programmed in
grammed and a "0" indicates that an unprogrammed loca- the NORMAL array. In the PHANTOM mode of opera-
tion is to remain unprogrammed. All locations to be pro- tion, the device operates logically as a function of the con-
grammed are addressed as row and column locations. Ta- tents of the PHANTOM array. In this mode pins 2, 10 &
ble 2 "Operating Modes" along with Tables 3 through 6 11 are non-inverting inputs and pin 7 is an inverting input.
provide the specific address for each addressed location to The programmable output cells function as they are pro-
grammed for normal operation. If the programmable out-
be programmed along with mode selection information for
both programming and operation in the "PHANTOM"
and "TEST" modes.
When programming the security bit, a supervoltage on pin
put cells have not yet been programmed, they are iu a reg-
istered inverting configuration. The PHANTOM mode is
invoked by placing a supervoltage Vpp on pin 6. Care
II

should be exercised when entering and leaving this mode
3 is used as data with a programming pulse on pin 13. that the supervoltage is applied no sooner than 20 ms after
Verification is controlled with a supervoltage on pins 4 and the Vee is stable, and removed a minimum of 20 ms before
the data out on pin 3. Vee is removed.
20GIO JEDEC Map TOP and BOTTOM TEST
The 20G 10 JEDEC Map is organized as follows: the The TOP TEST and BOTTOM TEST modes are entered
EPROM fuses for the product terms and input lines are and exited in the same manner, with the same concern for
located between 0000 and 3959 (decimal). The architecture power sequencing, but the supervoltage is applied to pins 9
bits are located between locations 3960 and 3989. Location & 10 respectively. In these modes an extra product term
3960 is the Polarity Bit (CO), location 3961 is the Regis- controls an output pin. TOP TEST controls pin 23, and
tered/Combinatorial Bit (Cl), and location 3962 is the BOTTOM TEST controls pin 14. These product terms are
Output Enable Bit (C2) for output pin 23. Locations 3963, controlled by the normal device inputs, and allow testing of
3964, and 3965 are the architecture bit locations for output all input structures.
pin 22. This pattern repeats for output pins 21,20, 19, 18,
17, 16, 15, and 14. Preload
Operating Modes Finally for testing of programmed functions, a preload fea-
ture allows any or all of the registers to be loaded with an
Table 2 describes the operating and programming modes of initial value for testing. This is accomplished by raising pin
the PLD C 20GI0. The majority of the programming 8 to a supervoltage Vpp, which puts the output drivers in a
modes function with a PROGRAM, PROGRAM INHIB- high impedance state. The data to be loaded is then placed
IT and PROGRAM VERIFY sequence. The exception is on the I/O pins of the device and is loaded into the regis-
the Security Program operation, which shows no program ters on the positive edge of the clock on pin 1. A "0" on the
inhibit function. Two timing diagrams are provided for I/O pin preloads the register with a "0" and a "1" preloads
these two different methodologies of programming in Fig- the register with a "1". The actual signal on the output pin
ures 15 & 16. Tables 3 through 6 are used as indicated to will be the inversion of the input data. The data on the I/O
provide the individual addresses of the various arrays and pins is then removed, and pin 8 returned to a normal TTL
cells to be programmed. There are 5 operating modes in voltage. Again care should be exercised to power sequence
addition to the programming modes for the PAL C 22VlO. the device properly.
4-41
~ . PLD C 20GIOB/PLD C 20GIO
~~~NDUcroR =====================================================================
Operating Modes
Table 2
Pins
Operating Modes Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15,16,18,
1 2 3 4 5 6 7 8 9 10 11 13 14 17 20 23
19,21 & 22
Feature Function
Program Vpp Vpp Data In
Main
Array Program Inhibit Vpp Table 3 Table 4 VIHP HighZ
Product Program Verify[3] Vpp Data Out
VILP
Output Program Vpp VIHP VIHP VIHP Vpp Vpp Data In
Enable
Program Inhibit Vpp Table 3 VIHP VIHP VIHP Vpp VIHP HighZ
Product
Terms Program Verify Vpp VIHP VIHP VIHP Vpp VILP Data Out
Data Data Data Data
Program Vpp VIHP VIHP VIHP VIHP Vpp VILP
In In In In
Top Test,
Bottom Test Program Inhibit Vpp Table 3 VIHP VIHP VIHP VIHP VIHP HighZ HighZ HighZ HighZ HighZ
Notes Data Data Data Data
Program Verify Vpp VIHP VIHP VIHP VIHP VILP Driven
Out Out Out Out
Program Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp Vpp Data In
Architec-
Program Inhibit Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Table 5 Vpp VIHP HighZ
ture Bits
Program Verify Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp VILP Data Out
Program Vpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP VILP VILP VILP VILP
Security
Bit Data
Verify VILP VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Driven Outputs
Out
Normal CP/I I I I I I I I I I I I I/O
PAL Phantom CP/I I NA NA NA Vpp I NA NA I I NA Output

Mode Top Test I I I I I I I I Vpp I I I NA Out
Operation
Bottom Test I I I I I I I I I Vpp I I Out NA
Reg Preload Notes NA NA NA NA NA NA Vpp NA NA NA VILP Data In
Phantom Program Vpp VILP VILP VILP Vpp Vpp Data In
Array
Program Inhibit Vpp VILP VILP Table 6 VILP Vpp Table 4 VIHP HighZ
Product
Terms Program Verify Vpp VILP VILP VILP Vpp VILP Data Out
Phantom Program Vpp VILP VILP Vpp VIHP VIHP VIHP Vpp Vpp Data In
VILP
Output
Enable Program Inhibit Vpp VILP VILP Table 6 VILP Vpp VIHP VIHP VIHP Vpp VIHP HighZ
Product
Program Verify Vpp VILP VIL VILP Vpp VIHP VIHP VIHP Vpp VILP Data Out
Terms
Notes:
1. DATA IN and DATA OUT for programming Synchronous Set, 2. The preload clock on pin 1 loads the Registers on a LOW going
Asynchronous Reset, TOP TEST and BOTTOM TEST is pro- HIGH transition.
grammed and verified on the following pins. 3. It is necessary to toggle OE (Pin 13) HIGH during all address tran-
Pin 14 = BOTTOM TEST sitions while in the program verifylblank check mode.
Pin 17 = Synchronous Set
Pin 20 = Asynchronous Reset
Pin 23 = TOP TEST
4-42
~~~~u~==================================================================
Input Term Addresses
Table 3 is used during the programming and verification of It provides the addressing for the 44 normal input term
the main array, output enable, asynchronous reset, syn- columns which are connected with an EPROM transistor
chronous preset, TOP and BOTTOM TEST as shown in to the product terms.
Table 2.

Table 3
Input Pin Pin Pin Pin Pin Pin

Term 2 3 4 5 6 7
0 VILP VILP VILP VILP VILP VILP
1 VIHP VILP VILP VILP VILP VILP
2 VILP VIHP VILP VILP VILP VILP
3 VIHP VIHP VILP VILP VILP VILP
4 VILP VILP VIHP VILP VILP VILP
5 VIHP VILP VIHP VILP VILP VILP
6 VILP VIHP VIHP VILP VILP VILP
7 VIHP VIHP VIHP VILP VILP VILP
8 VILP VILP VILP VIHP VILP VILP
9 VIHP VILP VILP VIHP VILP VILP
10 VILP VIHP VILP VIHP VILP VILP
11 VIHP VIHP VILP VIHP VILP VILP
12 VILP VILP VIHP VIHP VILP VILP
13 VIHP VILP VIHP VIHP VILP VILP
14 VILP VIHP VIHP VIHP VILP VILP
15 VIHP VIHP VIHP VIHP VILP VILP
16 VILP VILP VILP VILP VIHP VILP
17 VIHP VILP VILP VILP VIHP VILP
18 VILP VIHP VILP VILP VIHP VILP
19 VIHP VIHP VILP VILP VIHP VILP
20 VILP VILP VIHP VILP VIHP VILP
21 VIHP VILP VIHP VILP VIHP VILP
22 VILP VIHP VIHP VILP VIHP VILP
23 VIHP VIHP VIHP VILP VIHP VILP
24 VILP VILP VILP VIHP VIHP VILP
25 VIHP VILP VILP VIHP VIHP VILP
26 VILP VIHP VILP VIHP VIHP VILP
27 VIHP VIHP VILP VIHP VIHP VILP
28 VILP VILP VIHP VIHP VIHP VILP
29 VIHP VILP VIHP VIHP VIHP VILP
30 VILP VIHP VIHP VIHP VIHP VILP
31 VIHP VIHP VIHP VIHP VIHP VILP
32 VILP VILP VILP VILP VILP VIHP
33 VIHP VILP VILP VILP VILP VIHP
34 VILP VIHP VILP VILP VILP VIHP
35 VIHP VIHP VILP VILP VILP VIHP
36 VILP VILP VIHP VILP VILP VIHP
37 VIHP VILP VIHP VILP VILP VIHP
38 VILP VIHP VIHP VILP VILP VIHP
39 VIHP VIHP VIHP VILP VILP VIHP
40 VILP VILP VILP VIHP VILP VIHP
41 VIHP VILP VILP VIHP VILP VIHP
42 VILP VIHP VILP VIHP VILP VIHP
43 VIHP VIHP VILP VIHP VILP VIHP
4-43
~J'~u~==============================================================
Pin 7 is inverted, and the remaining 3 are normal non-in-
Product Term Addresses
verting. This PHANTOM array allows the output struc-
Table 4 is used for the programming of the "PHANTOM" tures to be tested. They are only present in PHANTOM
and normal array. It provides the addressing for the 8 modes of operation.
product terms associated with each input.
Phantom Input Term Addresses
Product Term Addresses Table 6
Table 4
Phantom
Product Pin Pin Pin Pin Pin Pin
Input
Term 8 9 10 11 4 5
Term
0 VILP VILP VILP VILP PO VILP VILP
I VIHP VILP VILP VILP PI VIHP VILP
2 VILP VIHP VILP VILP P2 VILP VIHP
3 VIHP VIHP VILP VILP P3 VIHP VIHP
4 VILP VILP VIHP VILP
5 VIHP VILP VIHP VILP
6
Programming Flow Chart
VILP VIHP VIHP VILP
7 VIHP VIHP VIHP VILP The programming flow chart describes the sequence of op-
erations for programming the NORMAL and PHANTOM
arrays, the NORMAL and PHANTOM output enable
Architecture Bit Addressing product terms, the set and preset product terms, the Top
Table 5 provides the addressing for the architecture bits Test product term, the Bottom Test product term, and the
used to control the configuration of the individual Pro- architecture bits. The exact sequencing and timing of the
grammable Output Cells. In the unprogrammed state, the signals is shown in the "Array Programming Timing Dia-
Programmable Output Cells are in a registered, active low gram".
or inverting configuration with output enable controlled
The logical sequence to program the device is described in
from the product term. They are programmed with a "1"
detail in the flow chart below, and should be followed ex-
on the pin associated with the Programmable Output Cells
actly for optimum intelligent programming that both mini-
and the appropriate address as shown in Table 5. Each
mizes programming time and realizes reliable program-
architecture bit that is not to be programmed, requires a
"0" on the 1/0 pin associated with the Programmable Out- ming. Particular attention should be paid to the application
of Vee prior to V pp, and removal of V pp prior to Vee. See
put Cells.
Figure 14 and Table 8 for specific timing and AC require-
Architecture Bit Addressing ments. Notice that all programming is accomplished with-
out switching Vpp on pin 1 and that after programming
Table 5
and verifying all locations individually, the programmed
Architecture Pin Pin locations should be verified one final time.
Bit 9 10 The normal word programming cycle, programs and veri-
Output fies a word at a time as shown in the programming flow-
Polarity chart, Figure 13 and timing diagram Figure 14. After all
VILP VILP
CO locations are programmed, the flowchart requires a verify
of all words. There is no independent timing diagram for
Registerl this operation, rather Figure 14 also provides the correct
Combinatorial VIHP VILP timing information for this operation. When performing
OutputCI this verify only operation, eliminate the program portion of
the cycle but maintain the setup and hold timing relative to
Product Term/
the verify pulse. Under no circumstances should the verify
Pin 13 signal be held low and the addresses toggled.
VILP VIHP
Output Enable
C2 Note that the overprogram pulse in step 10 of the program-
ming flowchart is a variable, "4" times the initial value
when programming the NORMAL, PHANTOM, TOP
Phantom Input Term Addressing TEST, BOTTOM TEST and OUTPUT ENABLE product
Phantom input terms are addressed as columns PO thru P3 terms and "8" times the initial value when programming
and represent inputs from pins 2,7, 10 and 11 respectively. the ARCHITECTURE BITS.
4-44
~~===========================P~L~D~C~2;OG~1~O~B~/;P~L~D~C~20~G~1~O
Programming Flowchart
START
VCC =
5.0V
Vpp = SEE NOTE 2
ADDRESS F'IRST LOCATION,
PLACE DATA TO BE PROGRAMMED

Notes:
1. This value is "4" for programming ~
-
the NORMAL array, PHANTOM
ON THE I/O PINS array TOP TEST, BOTTOM TEST
and OUTPUT ENABLE PROD-
ucr TERMS. The value is "s"
when programming ARCHITEC-
X=o TUREBITS.
2. Vpp Programming Voltage:
For 7C323B and 20G lOB = 12.SV
For 7C323 and 20G 10 = 13.SV.
PROGRAM ONE PULSE
OF' O.4ms
X=X+1
X=5?
NO
VERIFY ONE WORD

PASS
PROGRAM ONE PULSE OF'

NOTE 1) 0.4 X) ms
X=5
YES
VERIFY ALL WORDS AT
VCCP = 5.5 VOLTS
PASS
GOOD DEVICE
Vpp =O.OV
VCC = O.OV
STOP
0053-28
Figure 14
4-45
~ PLD C 20G10B/PLD C 20G10
~~~U~~==========================================================
Timing Diagrams
Programming timing diagrams are provided for two cases, DATA OUT is verified on the same pins. A "1" (VIHP) on
programming of all cells except the SECURITY BIT and an I/O pin causes the addressed location to be pro-
programming the SECURITY BIT. grammed. A "0" on the I/O pin leaves the addressed loca-
tion to be unprogrammed. All setup hold and delay times
Array must be met, and'in particular the sequence of operations
Programming the NORMAL and PHANTOM arrays and should be strictly followed. During verify only operation it
output enables, reset, preset, architecture bits and the top/ is not acceptable to hold PGMIVFY low and sequence
bottom test features uses the timing diagram in Figure 15. addresses, as it violates address setup and hold times. Prop-
ADDRESS refers to all applicable information in Tables 2 er sequencing of all power and supervoItages is essential, to
through 6 that is not specifically referenced in the timing reliable programming of the device as improper sequencing
diagram. DATA IN is provided on the I/O pins and could result in device damage.
Programming Waveforms
Veep
Vee PIN 24 -
NOTE 1 V -
SS
Vpp_
Vpp PIN 1
V1HP
ADDRESS
NOTE 2
V1LP-
V1HP
DATA
V1LP -
PGMjVFY
PIN 13
V1HP - --------.....;~
V1LP -
0053-29
Notes:
1. Power, Vpp & Vee should not be cycled for each program/verify 2. For programming OR Product Terms & Architecture bits, Pin 11
cycle. but may remain static during programming. (A9) must go to Vpp and satisfy TAS and TAN.
Figure 15
4-46
~~~NDUcroR =====================================================================
Security Cell
The security cell is programmed independently per the tim- same pin. A "0" on pin 3 indicates that the security bit has
ing diagram in Figure 16, and the information in Table 2. been programmed, and a "1" indicates that security bit has
Note again that proper sequencing of power and program- not been programmed. Security is programmed with a sin-
ming signals is required. Data in is represented as a super- gle 50 ms pulse on pin 13. A supervoltage on pin 4 is used
voltage on pin 3 and verified as a TTL signal output on the to verify security after Vpp has been removed from pin 1.
Programming Waveforms Security Cell
Vee PIN 24
Vccp
VSS -
-J Tp ~!.~___________ TP ____________~~~
Vpp_
Vpp PIN 1
VSS- Top
V _
pp
TOZ
DATA PIN3
V1HP -
V1LP -
Vpp_
PGM
PIN 13
V _
1LP
~----_TOV
Vpp_
SECURITY
VFY
PIN4
V1LP -
0053-30
Figure 16
4-47
~ PLD C 20GI0B/PLD C 20GI0
~~~~UaoR==================================================================
Table 7
Vpp for PLD C 20G1OB
Programming Voltage 12.0 13.0 Volts
and for CG7C323B-A
Vpp for PLD C 20G1O
Programming Voltage 13.0 14.0 Volts
and for CG7C323-A
Supply Voltage
Veep 4.75 5.25 Volts
During Programming
Input HIGH Voltage
VIHP 3.0 Veep Volts
During Programming
Input LOW Voltage
VILP -3.0 0.4 Volts
During Programming
VOH Output HIGH Voltage 2.4 Volts
VOL Output LOW Voltage 0.4 Volts
Programming
Ipp 40 rnA
Supply Current
AC Programming Parameters
Table 8
Delay to Programming
Tp 20 ms
Voltage
Top Delay to Program 1 p.s
Hold from Program
THP 1 p.s
or Verify
TR,F Vpp Rise & Fall Time 50 ns
TAS Address Setup Time 1 p.s
TAH Address Hold Time 1 p.s
Tos Data Setup Time 1 p.s
TOH Data Hold Time 1 p.s
Tpp Programming Pulsewidth 0.4 10 ms
Programming Pulsewidth
Tspp 50 ms
for Security
Delay from Program
Tov 2 p.s
to Verify
Tvo Delay to Data Out 1 p.s
Tvp Verify Pulse Width 2 p.s
Toz Verify to High Z 1 p.s
4-48
~~~~UaoR==================================================================
NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT NORMALIZED PROPAGATION
VS.SUPPLY VOLTAGE AMBIENT TEMPERATURE
VS. DELAYvs. SUPPLY VOLTAGE
1.4 .....- ......--,..---,.--.,. 1.2
1.2 ~--+--+--"'-----i 1.1

E ~
'" ""
S
N
::::i 1.0
c(
~
II:
i ~

0.9
0~~-----:J25~---~'25 0.8
4.5 5.0 8.0 4.0 4.5 5.0 5.5 6.0
SUPPL Y VOLTAGE (VI AMlIENT TEMPERATURE ('CI SUPPLY VOLTAGE (VI

TEMPERATURE
VS. VS. OUTPUT LOADING VS. SUPPLY VOLTAGE
1.3 ~---....,...-------. 20.0 1.2
15.0 .JI' I. 1
! V~ .............
E 10.0 ./
f .. ~
""
C
8
Q
5.0
~V 0.1 ~ .....
V 200 400 800 800 1000

O.8
4.0 4.5 5.0 5.5 6.0
CAPACITANCE (pFI SUPPLY VOLTAGE (VI
NORMALIZED CLOCK
VS. TEMPERATURE TIME VS. SUPPLY VOLTAGE TIME VS. TEMPERATURE
1.3,.....------y-----.., 1.1~-....,...--,......-...,...-......
A_lENT TEMPERATURE ('CI SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('CI
VS. OUTPUT LOADING VS. OUTPUT VOLTAGE VS. VOLTAGE
20.0 120 70
'06
~ C eo ~
15.0
.J' 1 to V !
~ ~
! /~ i
II: 75 L II:
II:
50
~
j ./ II:
~ 1/ ~
...Uu
40
~
Q
10.0
5.0
V
U
IjI
z
ill
~
eo
45
30
I
I
J
~~c:z!;~V -
II:
~
$I
~
30
20 ""- '~ ........

0.0 0
V 200 400 100 100 1000
0 '5
o Il
0.0 1.0 2.0
I
3.0 4.0
~
0
10
1.0 2.0 3.0 4.0
C~ACITANCE ("FI OUTPUT VOLTAGE (VI OUTPUT VOLTAGE (VI
0053-31
4-49
~ PLD C 20G10B/PLD C 20G10
~~~UaoR==================================================================
tpD ts tco Icc Ordering Code Package
Operating
(ns) (os) (ns) (mA) Range
15 12 10 70 PLO C 20G lOB-15PC/PI P13 Commercial!
PLO C 20GlOB-15WC/WI W14 Industrial
PLO C 20GlOB-15JC/JI* J64

CG7C323B-AI5JC/JI[16] J64
20 12 12 70 PLO C 20G lOB-20PC/PI P13 Commercial!
W14 Industrial
PLO C 20G lOB-20WC/WI
PLO C 20G lOB-20JC/JI J64
CG7C323B-A20JC/JI [16] J64
20 15 15 100 PLO C 20G lOB-200MB 014 Military
PLO C 20GI0B-20WMB W14
PLO C 20G lOB-20LMB L64
25 15 15 55 PLO C 20G 1O-25PC/PI P13 Commercial!
W14 Industrial
PLO C 20G 1O-25WC/WI
PLO C 20GlO-25JC/Jl J64
CG7C323-A25JC/Jl [16] J64
25 18 15 100 PLO C 20G lOB-250MB 014 Military
PLO C 20GI0B-25WMB W14
PLO C 20GI0B-25LMB L64
30 20 20 80 PLO C 20GlO-300MB 014 Military
PLO C 20G 1O-30WMB W14
PLO C 20G 1O-30LMB L64
35 30 25 55 PLO C 20GI0-35PC/PI P13 Commercial!
PLO C 20G 1O-35WC/WI W14 Industrial
PLO C 20GlO-35JC/JI J64

CG7C323-A35JC/JI[16] J64
40 35 25 80 PLO C 20G 1O-400MB 014 Military
PLO C 20G 10-40WMB W14
PLO C 20G 10-40LMB L64
Note:
16. The CG7C323 is the PLDC20G 10 packaged in the JEDEC compatible 28 pin PLCC pinout. Pin function and
pin order is identical for both PLCC pinouts. The principle difference is in the location of the "no connect" or
NCpins.
4-50
~ PLD C 20GI0B/PLD C 20GI0
~~~amucroR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
Ell
IIX 1,2,3
Vpp 1,2,3
IcC 1,2,3
Ioz 1,2,3
tpD 7,8,9,10,11
tpzx 7,8,9,10,11
teo 7,8,9,10,11
ts 7,8,9,10,11
tH 7,8,9,10,11
4-51
PRELIMINARY PLDC20RAIO
CYPRESS
SEMICONDUCTOR Reprogrammable
Asynchronous CMOS
Logic Device
Advanced user programmable Fast The Cypress PLD C 20RA 10 is a high
macro cell - Commercial performance, second generation pro-
tpD = 20 ns grammable logic device employing a
CMOS EPROM technology for
reprogrammability teo = 20 ns flexible macro cell structure which al-
tsu = 10 ns lows any individual output to be con-
Up to 20 input terms - Military figured independently as a combinato-
10 programmable I/O macro tpD = 25 ns rial output or as a fully asynchronous
cells teo = 25 ns D-type registered output.
tsu = 15 ns The Cypress PLD C 20RAI0 provides
Output macro cell programmable
as combinatorial or Low power lower power operation with superior
asynchronous D-type registered - Icc max = 80 mA speed performance than functionally
output Commercial equivalent bipolar devices through the
- ICC max = 100 rnA use of high performance 0.8 micron
Product term control of register Military CMOS manufacturing technology.
clock, reset and set and output
enable High reliability The PLD C 20RAlO is packaged in a
- Proven EPROM technology 24 pin 300 mil molded DIP, a 300 mil
Register preload and power-up - > 2001V input protection windowed cerdip, and a 28 lead square
reset - 100% programming and leadless chip carrier and provides up to
Four uncommitted product terms functional testing 20 inputs and 10 outputs. When the
per output macro cell Windowed DIP, windowed LCC, windowed device is exposed UV light,
DIP, LCC, PLCC available the 20RA lOis erased and then can be
reprogrammed.
Block Diagram and DIP Pinout
PROGRAMMABLE
AND ARRAY
(80 X 40)
Vee
0118-1
4-52
~ PRELIMINARY PLDC20RAIO
~~~~UcrOR==================================================================
Macro Cell Architecture
Figure 1 illustrates the architecture of the 20RAI0 macro mitted product terms of each programmable I/O macro
cell. The cell dedicates three product terms for fully asyn- cell that has been configured as an output.
chronous control of the register set, reset and clock func- An I/O cell is programmed as an input by tying the output
tions, as well as, one term for control of the output enable enable pin, pin 13, HIGH or by programming the output
function. enable product term to provide a LOW, thereby disabling
The output enable product term output is "AND'ed" with the output buffer, for all possible input combinations.
the input from pin 13 to allow either product term or hard When utilizing the I/O macro cell as an output, the input
wired external control of the output or a combination of path functions as a feedback path allowing the output sig-
control from both sources. If product term only control is nal to be fed back as an input to the product term array.
selected, it is automatically chosen for all outputs since, for
this case, the external output enable pin must be tied LOW.
When the output cell is configured as a registered output, 4
this feed back path may be used to feed back the current
The active polarity of each output may be programmed output state to the device inputs to provide current state
independently for each output cell and is subsequently control of the next output state as required for state ma-
fixed. Figure 2 illustrates the output enable options avail- chine implementation.
able.
When an I/O cell is configured as an output, combinatorial Preload and Power-up Reset
only capability may be selected by forcing the set and reset Functional testability of programmed devices is enhanced
product term outputs to be HIGH under all input condi- by inclusion of register preload capability which allows the
tions. This is achieved by programming all input term pro- state of each register to be set by loading each register from
gramming cells for these two product terms. Figure 3 illus- an external source prior to exercising the device. Testing of
trates the available output configuration options. complex state machine designs is simplified by the ability
An additional four uncommitted product terms are provid- to load an arbitrary state without cycling through long test
ed in each output macro cell as resources for creation of vector sequences to reach the desired state. Recovery from
user defined logic functions. illegal states can be verified by loading illegal states and
observing recovery. Preload of a particular register is ac-
Programmable I/O complished by impressing the desired state on the register
Because any of the 10 I/O pins may be selected as a input, output pin and lowering the signal level on the prel<;>ad
the device input configuration programmed by the user control pin (pin 1) to a logic LOW level. If the speCified
may vary from a total of nine programmable plus ten dedi- preload set up, hold and pulse width minimums have been
cated inputs (a total of nineteen inputs) and one output observed, the desired state is loaded into the register. To
down to a ten input, ten output configuration with all ten insure predictable system initialization, all registers are .
programmable I/O cells configured as outputs. Each input preset to a logic LOW state upon power up, thereby settmg
pin available in a given configuration is available as an the active LOW outputs to a logic HIGH.
input to the four control product terms and four uncom-
PL
0118-4
Figure 1. PLD C 20RAI0 Macro Cell
4-53
~~~UcrOR==================================================================~
Output Always Enabled Programmable
0118-13
0118-14
Hard-Wired Combination of
Programmable and Hard-Wired
0118-15
0118-16
Figure 2. Four Possible Output Enable Alternatives for the PLD C 20RAIO
Registered/Active LOW Combinatorial/Active LOW
0118-18
0118-17
Registered/Active HIGH Combinatorial!Active HIGH
0118-20
0118-19
Figure 3. Four Possible Macro Cell Configurations for the PLD C 20RAIO
4-54
~~~NDUcrOR =======================================================================
Selection Guide
Generic tpDns tsuns teons Iee mA
Part Number Com Com Mil Com Mil Com
Mil Mil
20RA1O-20 20 - 10 - 20 - 80 -
20RA1O-25 - 25 - 15 - 25 - 100
20RA10-30 30 - 15 - 30 - 80 -
20RA1O-35 - 35 - 20 - 35 - 100
Maximum Ratings I11III

(Above which the useful life may be impaired. For user guidelines, not tested.) ...
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... >2OO1V
Supply Voltage to Ground Potential DC Programming Voltage ...................... B.OV
(Pin 24 to Pin 12) .................... -O.5V to + 7.0V
Operating Range
in High Z State ...................... -O.5V to +7.0V Ambient
Range Vee
Output Current into Outputs (LOW) ............ 16 rnA Commercial OCto +75C 5V 1O%
Military [5] - 55C to + 125e 5V 1O%

Vee = Min., IOH = -3.2mA COM'L
VIN = VIR or VIL IOH = -2mA MIL
VOL Output LOW Voltage Vee = Min., IOL = 8 rnA 0.5 V

VIN = VIR or VIL
VIR Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[l] 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[l] 0.8 V
IIX Input Leakage Current VSS :::;:: VIN :::;:: Vee, Vee = Max. -10 10 p,A
Ioz Output Leakage Current Vee = Max., Vss :::;:: VOUT :::;:: Vee -40 40 p,A
Ise Output Short Circuit Current Vee = Max., VOUT = 0.5V[2] -30 -90 rnA
COM'L 80 rnA
lee Power Supply Current Vee = Max., VIN = GND Outputs Open
MIL 100 rnA
Capacitance [3]
eIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5
pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8
Notes:
1. These are absolute values with respect to device ground and all over- 4. Figure 4a test load used for all parameters except tEA, tER, tpzx and
shoots due to system or tester noise are included. tpxz. Figure 4b test load used for tEA, tER, tpzx and tpxz.
2. Not more than one output should be tested at a time. Duration of the 5. TA is the "instant on" case temperature.
short circuit should not be more than one second. VOUT = O.5V has 6. See the last page of this specification for Group A subgroup testing
been chosen to avoid test problems caused by tester ground degrada- information.
tion.
7. The parameters tER and tpxz are measured as the delay from the
3. Tested initially and after any design or process changes that may input disable logic threshold transition to VOH - O.5V for an enabled
affect these parameters. HIGH output or VOL + O.5V for an enabled LOW output. Please see
Table 1 for waveforms and measurement reference levels.
4-55
~~~~UcrOR==================================================================
Switching Characteristics PLD C 20RA10 Over Operating Range[4, 6, 7]
Commercial Military
Input or Feedback to
tpD
Non-Registered Output
20 30 25 35 ns
tEA Input to Output Enable 25 30 30 35 ns

tER Input to Output Disable 25 30 30 35 ns
tpzx Pin 13 to Output Enable 15 20 20 25 ns
tpxz Pin 13 to Output Disable 15 20 20 25 ns
tco Clock to Output 20 30 25 35 ns
tsu Input or Feedback Setup Time 10 15 15 20 ns
tp Clock Period 30 45 40 55 ns
tWH Clock Width HIGH 13 20 18 25 ns
tWL Clock Width LOW 13 20 18 25 ns
fMAX Maximum Frequency 33.3 22.2 25.0 18.1 MHz
ts Input to Asynchronous Set 20 35 25 40 ns
tR Input to Asynchronous Reset 25 40 30 45 ns
Asynchronous Set/Reset
tAR Recovery Time
20 30 25 35 ns
twp Preload Pulse Width 30 35 35 40 ns

tsup Preload Setup Time 20 25 25 30 ns
tHP Preload Hold Time 20 25 25 30 ns

R1.457.o. R1.457.0. INPUT PULSES
OUTP:~~(470.o.
(470.0. mil)
5V o---~Mt--.. 3.0V----::.I~~--~
mil)
OUTPUT 0--""--"" R2 R2 GNO-----=-r-
Including Jig
and Scope _
I 50pF 270.0.
(319.0. mil) I 5 pF 270.0.
_(319.0. mil)
- -- 0118-6
Figure 5
0118-7
Figure 48 Figure 4b
170.0. 190.0.
OUTPUT~1.86V =Vthc OUTPUT~2.02V =Vthm
0118-8 0118-9
LCC and PLCC Pinouts

...l 13 ~ ;; ...l 13 ~ ;;
_N.: oS> Ia.. > -::::. -::::. _N.: oS> Ia.. > -::::. -::::.
4 3 2 l1l28 27 26
25 1/02
1/02
1/03 13 1/03
1/04 14 1/04
1/05 1/05
1/06 1/06
1/07 1/07
Ne He He
12 13 14 15 16 17 18
.!'-..!D.1"JlI~~~
0118-21 -~ 0118-22
456
~~~UcroR =====================================================================
Table 1
tpxz(-)
~t
l.5V
VOH
o.}v
Vx 0118-23
tpxz( +) 2.6V
VOL rot
otv
Vx
0118-24
+rot
tpzx( +) Vthc VOH
Vx
0118-25
tpzx(-)
+~
Vthc
Vx
VOL 0118-26
tER( -)
~
1.5V
VOH
o.}v
Vx 0118-23
rr-
tER( +) 2.6V Vx
VOL
o.}v
0118-24
+1:
tEA(+) Vthc VO H
Vx
0118-25
+~t
tEA(-) Vthc
Vx
VOL 0118-26
Switching Waveforms
INPUTS, REGISTERED -~~.r-~~~~~--------~""'-\Jr---
FEEDBACK ----'l~"---""~~'I'----------'I'_-.IJ'.----
CP
-----'1
ASYNCHRONOUS
SET ----+----+-""l
ASYNCHRONOUS
RESET ----+----+--+-----'1
REGISTERED ----"""'tI\I\I,....--+--~~,....---~-~
OUTPUTS _ _ _ _ """IIAII'-__
+-_"""'WT1~ ___
..rn......ofI
OUTPUTS ---------"""'ll'nlJI--------~
COMBINATORIAL _________ _ _ _ _ _ _ _..,
~~~
PIN 13 OUTPUT --------------~~

ENABLE(OE)
REGISTEREO
COMBINATORIAL AND
OUTPUTS ':~~_
tmt tpzxt
:::::::::::::::::::::::::::::-=~'~'~--~~/~J?~======
_~~
0118-10
Preload Switching Waveforms
__t_su_pe
~t~:0~~ _____X_X_E ...
PIN 1 ------------
PRELOAD CLOCK (Pi:)
twp 0118-12
4-57
~ PRELIMINARY PLDC20RAI0
~jr;~UcroR=============================================
Functional Logic Diagram PLD C 20RAIO
-1>
0 ~
~~
7 s=r ~[).~ PL
23
R P
3 .... .A L-
~
8
3 ....
15
16
~[).~
.A L- to ~
PL
R P
22
4..1"l
23
24
~~~
.A L- toR
PL
R P
21
5...1".
31
32
~[).~
g3-
-'"'
A '- to ~
PL
R P
20
~~
1
39 ..., ~~[ PL
19
R P
6" .A '-
~~
40
47
~ff PL
R P
18
7 .... A L-
48
8..1"l
55
56
~[).~
... I- toR
PL
R P
17
9 ....
63
64
:s=r ~[).~
.A L- ~
PL
R R P
16
10
"
71
72
~[).~
A I- toR
PL
R P
15
11 ....
79
o 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
~[).~
:t>=J
_
.A '- ~
PL
R P
R
~ 13
14
0118-11
4-58
~ PRELIMINARY PLD C 20RAIO
~~~NDUcrOR================================================================
Icc tpD tsu teo Ordering Code Package Operating Range
(mA) (ns) (ns) (ns)
80 20 10 20 PLO C 20RAlO-20PC P13 Commercial
PLO C 20RAlO-20WC W14
PLO C 20RAlO-20JC J64
100 25 15 25 PLO C 20RAlO-250MB 014 Military
PLO C 20RAlO-25WMB W14
PLO C 20RAlO-25LMB L64
PLO C 20RAlO-25QMB Q64
80 30 15 30 PLO C 20RA 1O-30PC P13 Commercial
PLO C 20RAlO-30WC W14
PLO C 20RAlO-30JC J64
100 35 20 35 PLO C 20RAlO-350MB 014 Military
PLO C 20RAlO-35WMB W14
PLO C 20RAlO-35LMB L64
PLO C 20RAlO-35QMB Q64
4-59
~)r;~~U~R============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
IoZ 1,2,3
Ice 1,2,3
tpD 9,10,11
tpzx 9,10,11
teo 9,10,11
tsu 9,10,11
tH 9,10,11
4-60
PAL C 22VIOB/PAL C 22VIO
CYPRESS
SEMICONDUCTOR Reprogrammable CMOS
PAL Device
Advanced second generation - "20" military The Cypress PAL C 22VlO is a CMOS
PAL architecture 15 ns teo second generation Programmable Log-
17 ns ts ic Array device. It is implemented with
Low power 20 ns tpD the familiar sum-of-products (AND-
- 55 mA max "L"
31 MHz OR) logic structure and a new concept,
- 90 mA max standard
- 120 mA max military Up to 22 input terms and 10 the "Programmable Macro Cell".
outputs The PAL C 22VI0 is executed in a 24
CMOS EPROM technology for
reprogrammability Enhanced test features pin 300 mil molded DIP, a 300 mil
- Phantom array windowed Cerdip, a 28 lead square ce-
Variable product terms ramic leadless chip carrier, a 28 lead
- Top Test
- 2 X (8 thru 16) product square plastic leaded chip carrier and
- Bottom Test
terms provides up to 22 inputs and 10 out-
- Preload
User programmable macro cell puts. When the windowed CERDIP is
- Output polarity control High reliability exposed to UV light, the 22VlO is
- Proven EPROM technology erased and then can be reprogrammed.
- Individually selectable for
registered or combinatorial
- > 2000V input protection The Programmable Macro Cell pro-
operation
- 100% programming and vides the capability of defining the ar-
functional testing chitecture of each output individually.
- "IS" commercial & industrial
10 ns teo Windowed DIP, windowed LCC, Each of the 10 potential outputs may
10 ns ts DIP, LCC, PLCC available be specified to be "REGISTERED" or
15 ns tpD "COMBINATORIAL". Polarity of
50 MHz PAL is a registered trademark of Monolithic Memories Inc.
Logic Symbol and Pinout
0023-1
LCC and PLCC Pinout --~~>~~~

4 3 il;h82726
I 5 'W 25 1/02
I 6 24 1/03
I 7 23 I/0.
HC 8 22 HC
I 9 21 1/05
I 10 20 1/06
I 1\213141516171~9 1/7
0023-10
4-61
~ PAL C 22VIOB/PAL C 22VIO
~J'~NDUcrOR =====================================================================
each output may also be individually selected allowing registered mode of operation, the output of the register is
complete flexibility of output configuration. Further con- fed back into the array providing current status informa-
figurability is provided through " ARRAY" configurable tion to the array. This information is available for estab-
"OUTPUT ENABLE" for each potential output. This fea- lishing the next result in applications such as control-state-
ture allows the 10 outputs to be reconfigured as inputs on machines. In a combinatorial configuration, the combina-
an individual basis or alternately used as a combination torial output or, if the output is disabled, the signal present
I/O controlled by the programmable array. on the I/O pin is made available to the array. The flexibili-
The PAL C 22V1O features a "VARIABLE PRODUCT ty provided by both programmable macro cell product
TERM" architecture. There are 5 pairs of product terms term control of the outputs and variable product terms
beginning at 8 product terms per output and incrementing allows a significant gain in functional density through the
by 2 to 16 product terms per output. By providing this use of programmable logic.
variable structure the PAL C 22VI0 is optimized to the Along with this increase in functional density, the Cypress
configurations found in a majority of applications without PAL C 22VI0 provides lower power operation thru the use
creating devices that burden the product term structures of CMOS technology, increased testability with a register
with unuseable product terms and lower performance. preload feature and guaranteed AC performance through
Additional features of the Cypress PAL C 22VIO include a the use ofa phantom array. This phantom array (PO-P3)
synchronous PRESET and an asynchronous RESET prod- and the "TOP TEST" and "BOTTOM TEST" features al-
uct term. These product terms are common to all MACRO low the 22V1O to be programmed with a test pattern and
CELLS eliminating the need to dedicate standard product tested prior to shipment for full AC specifications without
terms for initialization functions. The device automatically using any of the functionality of the device specified for the
resets on power-up. product application. In addition, this same phantom array
may be used to test the PAL C 22V1O at incoming inspec-
The PAL C 22VI0 featuring programmable macro cells tion before committing the device to a specific function
and variable product terms provides a device with the flexi- through programming. PRELOAD facilitates testing pro-
bility to implement logic functions in the 500 to 800 gate grammed devices by loading initial values into the regis-
array complexity. Since each of the 10 output pins may be ters.
individually configured as inputs on a temporary or perma-
nent basis, functions requiring up to 21 inputs and only a Configuration Table 1
single output down to 12 inputs and 10 outputs are possi-
ble. The 10 potential outputs are enabled through the use Registered/Combinatorial
of product terms. Any output pin may be permanently se- Cl Co Configuration
lected as an output or arbitrarily enabled as an output and
an input through the selective use of individual product 0 0 Registered/Active Low
terms associated with each output. Each of these outputs is 0 1 Registered/Active High
achieved through an individual programmable macro cell.
These macro cells are programmable to provide a combina- 1 0 Combinatorial!Active Low
torial or registered inverting or non-inverting output. In a 1 1 Combinatorial!Active High
Macrocell
r---------------------,I
AR I
I
OUTPUT
SELECT
~------------4-~D QI-------I MUX
CP Ol-.....--~ Sl So
SP
INPUT/
FEEDBACK
MUX
Sl
C1----~----~--------------------~
Co-----~--------------------------------~
L ____________________ ~
MACROCELL
0023-2
4-62
~ PAL C22VIOB/PAL C22VIO
~~~~UcrOR =====================================================================
Selection Guide
Generic Ieel mA tpDns tsns teo ns
Part Number "L" Com/Ind Mil Com/Ind Mil Com/Ind Mil Com/Ind Mil
22VlOB-15 90 - 15 - 10 - 10 -
22VlOB-20 - - 120 - 20 - 17 - 15
22VlO-20 90 - 20 - 12 - 12 -
22VlO-25 55 90 100 25 25 15 18 15 15
22VlO-30 - 100 - 30 - 20 - 20

22VlO-35 55 90 - 35 - 30 - 25 -
22VlO-40 - 100 - 40 - 30 - 25
Maximum Ratings
Storage Temperature ............... - 65C to + 150C DC Programming Voltage
Ambient Temperature with PAL C 22VlOB ............................. 13.0V
Power Applied .................... - 55C to + 125C PAL C 22VlO .............................. 14.0V
Supply Voltage to Ground Potential Static Discharge Voltage ..................... > 200 1V
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V (per MIL-STD-883 Method 3015)
DC Voltage Applied to Outputs Latchup Current .......................... > 200 rnA
in High Z State ...................... -0.5V to + 7.0V Operating Range
DC Input Voltage ................... - 3.0V to + 7.0V Ambient
Output Current into Outputs (Low) ............. 16 rnA Range Vee
Temperature
UV Exposure ........................ 7258 Wsec/cm 2 Commercial OCto + 75C 5V 10%
Military [7] - 55C to + 125C 5V 10%
Industrial - 40C to + 85C 5V 10%
Output HIGH Voltage Vee = Min., IOH = -3.2mA COM'L/IND

VOHI 2.4 V
VIN = VIH or VIL IOH = -2mA MIL
HIGH Level CMOS Vee = Min.,
VOH2 Output Voltagd 3] IOH = 100 p,A Vee -l.OV V
VIN = VIH or VIL
Output LOW Voltage Vee = Min., IOL = 16mA COM'L/IND
VOL 0.5 V
VIN = VIH or VIL IOL = 12mA MIL
VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[l] 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[l] 0.8 V
IIX Input Leakage Current Vss ::;: VIN::;: Vee, Vee = Max. -10 10 p,A
Ioz Output Leakage Current Vee = Max., Vss ::;: VOUT ::;: Vee -40 40 p,A
Ise Output Short Circuit Current Vee = Max., VOUT = 0.5V[2] -30 -90 mA
"LH 55 mA
Standby Power COM'L/IND 90 mA
Ieel Vee = Max., VIN = GND Outputs Open
Supply Current MIL 100 mA
MIL-20 120 mA
Notes:
I. These are absolute values with respect to device ground and all over- 4. Figure la test load used for all parameters except tEA, tER, tpzx and
shoots due to system or tester noise are included. tpxz Figure 1b test load used for tEA, tER, tpzx and tpxz.
2. Not more than one output should be tested at a time. Duration of the 5. Preliminary specifications.
short circuit should not be more than one second. VOUT = O.5V has 6. See the last page of this specification for Group A subgroup testing
been chosen to avoid test problems caused by tester ground degrada- information.
tion.
4-63
~~~U~ ================================================================
Capacitance [3]
CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5 pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8 pF
Switching Characteristics PAL C 22VIO[4, 6]

Commercial & Industrial Military
Parameters Description B15 20 25 35 B20 25 30 40 Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input to Output
tpD 15 20 25 35 20 25 30 40 ns
Propagation Delay[14]
Input to Output
tEA 15 20 25 35 20 25 25 40 ns
Enable Delay
Input to Output
tER 15 20 25 35 20 25 25 40 ns
Disable Delay[9]
Clock to Output
teo 10 12 15 25 15 15 20 25 ns
Delay[15]
Input or Feedback
ts 10 12 15 30 17 18 20 30 ns
Setup Time
tH Input Hold Time 0 0 0 0 0 0 0 0 ns
External Clock
tp 20 24 30 55 32 33 40 55 ns
Period (tco + tS)
tWH Clock Width HIGH [3] 6 10 12 17 12 14 16 22 ns
tWL Clock Width LOW[3] 6 10 12 17 12 14 16 22 ns
External Maximum
fMAXl Frequency 50.0 41.6 33.3 18.1 31.2 30.3 25.0 18.1 MHz
(l/(tco + t8[10]
Data Path
fMAX2 Maximum Frequency 83.3 50.0 41.6 29.4 41.6 35.7 31.2 22.7 MHz
(l/(twH + twL[3,11]
Internal Feedback
fMAX3 Maximum Frequency 80.0 45.4 35.7 20.8 33.3 32.2 28.5 20.0 MHz
(l/(tCF + tS[12]
Register Clock to
tCF 2.5 10 13 18 13 13 15 20 ns
Feedback Input [13]
Asynchronous Reset
tAW 15 20 25 35 20 25 30 40 ns
Width
Asynchronous Reset
tAR 10 20 25 35 20 25 30 40 ns
Recovery Time
Asynchronous Reset to
tAP 20 25 25 35 25 25 30 40 ns
Registered Output Delay
Synchronous Preset
tSPR 10 20 25 35 20 25 30 40 ns
Recovery Time
Power Up
tPR 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 p.s
Reset Time[16]
464
~~~NDUcroR
Notes:
=====================================================================
8. This parameter is sample tested periodically with the device clocked 13. This parameter is calculated from the clock period at fMAX internal
at fMAX external (fMAXI) with all registers cycling on each cycle and (fMAX3) as measured (see note 12 above) minus t8.
outputs disabled (in high Z state). 14. This specification is guaranteed for all device outputs changing state
9. This parameter is measured as the time after output disable input in a given access cycle. See Figure 3 for the minimum guaranteed
that the previous output data state remains stable on the output. This negative correction which may be subtracted from tpD for cases in
delay is measured to the point at which a previous high level has which fewer outputs are changing state per access cycle.
fallen to 0.5 volts below VOH Min. or a previous low level has risen 15. This specification is guaranteed for all device outputs changing state
to 0.5 volts above VOL Max. Please see Figure 4 for enable and in a given access cycle. See Figure 3 for the minimum guaranteed
disable test waveforms and measurement reference levels. negative correction which may be subtracted from teo for cases in
10. This specification indicates the guaranteed maximum frequency at which fewer outputs are changing state per access cycle.
which a state machine configuration with external feed back can 16. The registers in the PAL C 22VlO have been designed with the
operate. capability to reset during system power-up. Following power-up, all
11. This specification indicates the guaranteed maximum frequency at registers will be reset to a logic LOW state. The output state will
which an individual output register can be cycled.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feed back can
depend on the polarity of the output buffer. This feature is useful in
establishing state machine initialization. To insure proper operation,
the rise in Vee must be monotonic and the timing constraints depict-
4
operate. This parameter is tested periodically by sampling produced in Figure 5 must be satisfied.
tion product.
n
ft
R1 238.0. R1 238.0. INPUT PULSES
(319.0. MIL) (319.0. MIL)
OUTP~~ R2
OUTP~~ R2
3.0 v------:=:----~
50 pF
INCLUDING I-=
170.0.
(236.0. MIL)
5 pF
I 170.0.
(236.0. MIL)
GND-------"'r-
JIG AND
SCOPE
-= -=-= 0023-12
Figure 2
0023-11
Figure la Figure Ib
99.n 136.n
OUTPUT~ 2.08V = Vthc OUTPUT~2.13V=Vthm
0023-13 0023-14
Minimum Negative Correction to tpD and teo

vs. Number of Outputs Switching
z
o
~., -0.2
/v
8'" ..co -0.4
LV
~! -0.6
V
0
~ _If. -0.8 V
~e //
:2 -1.0
Z
:i
-1.2
1 2 3 4 5 6 7 8 9 10
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
0023-20
Figure 3

1.5V
O.~V
tER(-)
~
VOH
Vx 0023-16
tER(+) 2.6V
VOL O;5V r Vx
0023-17
tEA(+) Vthc
Vx O;SV rr- VOH
0023-18
o.~v ~
tEA(-) Vthc Vx
VOL 0023-19
Figure 4. Test Waveforms

4-65
~~==========================~P~A~L~C~2~2V~10~B~/~P~A~L~C~2;2V~1~O
Switching Waveforms
INPUTS I/O.
REGISTERED ---Y~--~VQ~I(----------~~r-"\.iJ----
FEEDBACK
SYNCHRONOUS---~~I~::::~I~~~r---~~-~----~~-~~------
PRESET
CP
ASYNCHRONOUS
-+-____..J._JI
RESET _ _ _ _ _ _
REGISTERED -----~\Nr-+-~~Jr-------~~;:J
OUTPUTS: Jo+o+oI~Wo(I
COMBINATORIAL ---------~;bJr---------~::;;;:J
OUTPUTS: Jo+o+oI~w.l[
0023-3
Power Up Reset Waveforms [16]

POWER _ _ _ _ _ _ _ _~4~V~r~I~~--------------------------vcc
~:::::~~~_-_-_-_t.:;PR:..-_-_-_-_-_-_-__-::=--:;~.I.i'r'_ _ _ _ _ __
REGISTERED _ _ _ _ _ _ _ _ _ _
':
ACTIVE LOW
OUTPUT--------------------.J.I~/J,I
I "f
CLOCK ---------------------_1 ______~..l.~~--...II),I",----- ~
0023-21
Figure 5
4-66
~RFSS
.nEMICoNDucroR
PAL C 22V10B/PAL C 22V10
==;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:;;;;=:=;;;;=:=======
Functional Logic Diagram PAL C 22VI0
.....
....
..
OE
Pl P,
PO P2 0 , . "
,. 20 2' 2. 32 31 40
~th
0
I:El
~
COG-
7
~C[lL 23
.....
OE
~
--
:~
0 ~
3..~
22
....... >CELl
-
~
2
O~
:::::: ~
..
J - ~CELL~~ ~
21
3 ..... " == ~ #-
OE
~
~th
0
:~ ~
1= ~
.. ~
20
~"-
E::
4 ..... '3
rr'3-
:b
O~
r- CELL 19
n-
>
....... ~
.......
O~
= :th
-r-
r n ~
CELL 18
=1
6
OE
0
=
~ t:>-
....CR<>-
17
7 ..... '3
O~
~ ~~
>-- ~th
eRO-
> CELL 16
8 ...... "
~~
#- ...,...,..
:~
3
~
15
9
...... ~ ~
I>ClLl
O~
, '
......-.
10 .....
7 ...,.
>--
.A
:~
I>CELL 14
'-T-
.... Sp
.A
11 13
0023-4
4-67
~~~U~==============================================================
NORMALIZED STANDBY NORMALIZED STANDBY NORMALIZED
SUPPLY CURRENT (ICCI) SUPPLY CURRENT (lCCI) PROPAGATION DELAY
VS. SUPPLY VOLTAGE VS. AMBIENT TEMPERATURE va. SUPPLY VOLTAGE
1.4.._--.---.---...,...-- 1.2
1.2 ....---+----1....---#----1 Q
1.1
It ...............
"""'
5l
~::; 1.0 ....---+----.,.iL---+-----1
N
::; 1.0
~ "
~
&I:
i 0.8 I--~'#----il----t----i
i 0.9
'-.....
TA -25"C
'"
f-MAX~
0.& ......- - ' - - -......-~-........ O.&L.-----I.----~ 0.8
4.0 4.6 6.0 6.5 8.0 -li5 26 125 4.0 4.5 5.0 5.5 &.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('CI SUPPLY VOLTAGE (VI

vs. TEMPERATURE va. OUTPUT LOADING VS. SUPPLY VOLTAGE
1.3r-----...,...----~ 20.0 1.2
15.0 , ~ g 1.1
..............
/ 5l
! ./
'""'
N
10.0 ::; 1.0
~
'"
Q
5.0
V I"o
z
0.9 ~.....
V 200 400 800 800 1000
0.8
4.0 4.5 5.0 5.6 &.0
AMBIENT TEMPERATURE ('CI CAPACITANCE (pFI SUPPLY VOLTAGE (V)
NORMALIZED CLOCK
VS. TEMPERATURE TIME va. SUPPLY VOLTAGE TIME n. TEMPERATURE
1 . 3 r - - - - - - r - - - -....... 1.1.._-........- -___- ........- __
0~~'O--4.5L---51...0--51...5---.J8'O
AMBIENT TEMPERATURE ('CI SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE ('C)
VS. OUTPUT LOADING va. OUTPUT VOLTAGE va. VOLTAGE
20.0 120 70
I-- ~
I
105
./ 1 60
16.0
/"
~
Ii
10
/
t-
alII: 50 "-
./
'"a:
~
75
/
II:
;:)
U 40
'"
"'"
u 60
10.0
~
l!I&I:
J
/ !
i
45
/
J
~::==2:;~V -
;:)
S
t-
30
20
5.0 30
I ~ 'r-..... .......
Ii 200 400 800 800 1000
50 15
o 1/
0.0 1.0 2.0
l
3.0 4.0
0
10
1.0 2.0 3.0 4.0
CAPACITANCE (pFl OUTPUT VOLTAGE (VI OUTPUT VOLTAGE (V)

0023-15
4-68
~ PAL C 22V10B/PAL C 22V10
~~~NDUaoR =====================================================================
Wavelengths of light less than 4000 Angstroms begin to normal mode of operation. Cells in the PHANTOM AR-
erase the PAL C 22VI0. For this reason, an opaque label RAY, TOP TEST, and BOTTOM TEST areas are pro-
should be placed over the window if the device is exposed grammed at Cypress during the manufacturing operation,
to sunlight or fluorescent lighting for extended periods of and they therefore will be programmed when received in a
time. In addition, high ambient light levels can create hole- non-windowed package by the user. Consequently, the user
electron pairs which may cause "blank" check failures or will normally have no need to program these cells.
"verify errors" when programming "windowed" parts. The Cypress PAL C 22VlO contains 10 identical MACRO-
This phenomenon can be avoided by use of an opaque label CELLS which may be individually configured. Each
over the window during programming in high ambient MACROCELL is associated with a single 1/0 pin and
light environments. through the architecture bits, each associated pin may be
The recommended dose for erasure is ultraviolet light with permanently configured as an input, an output or be used
a wavelength of2537 Angstroms for a minimum dose (UV as both input and output as a function of the logical func-
intensity X exposure time) of25 Wsec/cm2 . For an ultra- tion in the array. Each MACROCELL consists of a type
violet lamp with a 12 mWI cm2 power rating, the exposure "D" latch, an output multiplexer, a feedback multiplexer
would be approximately 35 minutes. The PAL C 22VlO and a tristatable output driver that is controlled by a
needs to be placed within 1 inch of the lamp during era- unique product term. The clock is common to all MAC-
sure. Permanent damage may result if the device is exposed ROCELLS, and comes from pin 1 of the device. Each reg-
to high intensity UV light for an extended period of time. ister also has an asynchronous reset and a synchronous
7258 Wsec/cm 2 is the recommended maximum dosage. preset. These are each driven by product terms. These
product terms are common to all MACROCELLS allow-
Device Programming ing all registers to either be asynchronously reset or syn-
The PAL C 22VlO has multiple programmable functions. chronously preset by a logical function in the array. The
In addition to the normal array, a "PHANTOM" array, device is automatically reset at power up. A preload feature
"TOP and BOTTOM TEST" and a "SECURITY" feature allows the registers to be preloaded with any state for test-
are programmable. The PAL C 22VI0 security mecha- ing.
nism, when invoked, prevents access to the "NORMAL" The architecture bits CO and Clare used to configure each
and "TOP/BOTTOM TEST" array. The "PHANTOM" MACROCELL individually. CO selects the polarity of the
array feature is still accessible, allowing programming and output and Cl selects the combinatorial or registered mode
verification of the pattern in the "PHANTOM" array. of operation. If the registered mode of operation is selected,
Functional operation of all other features is allowed re- the feedback path is automatically selected to be from the
gardless of the state of the "SECURITY BIT". In addition, register. In the combinatorial mode the feedback path is
the device contains 10 MACROCELLS which are pro- automatically selected to be from the I/O pin. In this com-
grammed to configure the device functionality for each binatorial mode, the output from the array may be fed into
specific application. the array or if the output is deselected using the output
The logic array is divided into a "NORMAL" array and a enable product term the pin may be used as an external
"PHANTOM" array. The normal array is used to config- input. There is not a mode where the I/O pin may be used
ure the device to perform a specific function as required by as a combinatorial output or an input pin, while the regis-
the user, and the phantom array is provided as a test array ter is used as a state register. The architecture bits are
for Cypress' testing the device prior to user programming programmed as a separate item during normal program-
thus assuring a reliable, thoroughly tested product. The ming. An 1/0 pin is configured to be an input by program-
"PHANTOM" array contains four additional columns ming the MACROCELL into a combinatorial mode and
connected to input pins 2 (TRUE), 7 (INVERTING), 10 disabling the ouput with the output enable product term.
(TRUE) and 11 (TRUE). These inputs may be pro-
grammed to be connected to all normal product terms. Pinout
This allows all sense amplifiers and macrocells to be exer- The PAL C 22VlO PROGRAMMING pinout is shown in
cised for both functionality and performance after assem- Figure 6. In the Programming pinout configuration, the
bly and prior to shipment. These features are in addition to device may be programmed and verified for the NORMAL
the normal array. They do not affect normal operation, mode of operation and also programmed, verified and op-
allowing the user full programming of the normal array, erated in PHANTOM and TEST modes. These special
while allowing the device to be fully tested. modes of operation are achieved through the use of super-
The "TOP TEST" and "BOTTOM TEST" feature, allow voltages applied to certain pins. Care should be exercised
connection of all input terms to either pin 23 or 13. These when entering and exiting these modes, paying specific at-
locations may be programmed and subsequently exercised tention to both the operating modes as specified in Table 1
in the "TOP TEST" and "BOTTOM TEST" mode. Like and the sequencing of the supervoltages as shown in the
the Phantom array above, this feature has no effect in the timing diagrams.
4-69
(W;= SEMICONDUcrOR
PAL C 22VIOB/PAL C 22VIO
Programming Pinout
provide the individual addresses of the various arrays and
Vpp Vee cells to be programmed. There are 5 operating modes in
AO DO
addition to the programming modes for the PAL C 22VI0.
These provide NORMAL operation, PHANTOM opera-
A1 01 tion, TOP TEST, BOTTOM TEST and a register preload
A2 02 feature for testing.
A3 03 In the normal operating mode, all signals are TTL levels
A4 04 and the device functions as it is internally programmed in
AS 05 the NORMAL array. In the PHANTOM mode of opera-
tion, the device operates logically as a function of the con-
A6 06 tents ofthe PHANTOM array. In this mode pins 2, 10 &
A7 07 11 are non-inverting inputs and pin 7 is an inverting input.
AS 08 The MACROCELLS function as they are programmed for
A9 normal operation. If the MACROCELLS have not yet
09
been programmed, they are in a registered inverting config-
Vss PGM/Vr uration. The PHANTOM mode is invoked by placing a
supervoltage Vpp on pin 6. Care should be exercised when
0023-6 entering and leaving this mode that the supervoltage is ap-
Figure 6 plied no sooner than 20 ms after the Vee is stable, and
removed a minimum of 20 ms before V cc is removed.
With the exception of the Security bit, all arrays are pro- TOP and BOTTOM TEST
grammed in a similar manner. The data to be programmed The TOP TEST and BOTTOM TEST modes are entered
is represented by a "I" or "0" on the I/O pins. A "I" and exited in the same manner, with the same concern for
indicates that an unprogrammed location is to be pro- power sequencing, but the supervoltage is applied to pins 9
grammed and a "0" indicates that an unprogrammed loca- & 10 respectively. In these modes an extra product term
tion is to remain unprogrammed. All locations to be pro- controls an output pin. TOP TEST controls pin 23, and
grammed are addressed as row and column locations. Ta- BOTTOM TEST controls pin 14. These product terms are
ble 1 "Operating Modes" along with Tables 2 through 5 controlled by the normal device inputs, and allow testing of
provide the specific address for each addressed location to all input structures.
be programmed along with mode selection information for
both programming and operation in the "PHANTOM" Preload
and "TEST" modes.
Finally for testing of programmed functions, a preload fea-
When programming the security bit, a supervoltage on pin ture allows any or all of the registers to be loaded with an
3 is used as data with a programming pulse on pin 13. initial value for testing. This is accomplished by raising pin
Verification is controlled with a supervoltage on pins 4 and 8 to a supervoltage Vpp, which puts the output drivers in a
the data out on pin 3. high impedance state. The data to be loaded is then placed
on the I/O pins of the device and is loaded into the regis-
Operating Modes ters on the positive edge of the clock on pin 1. A "0" on the
Table 1 describes the operating and programming modes of I/O pin preloads the register with a "0" and a "1" preloads
the PAL C 22VI0. The majority of the programming the register with a "1". The actual signal on the output pin
modes function with a PROGRAM, PROGRAM INHIB- will depend on the output polarity selected when the
IT and PROGRAM VERIFY sequence. The exception is MACROCELL is programmed. The data on the I/O pins
the Security Program operation, which shows no program is then removed, and pin 8 returned to a normal TTL volt-
inhibit function. Two timing diagrams are provided for age. Again care should be exercised to power sequence the
these two different methodologies of programming in Fig- device properly.
ures 8 & 9. Tables 2 through 5 are used as indicated to
4-70
~ PAL C 22V10B/PAL C 22V10
~~~NDUcroR =====================================================================
Operating Modes
Table 1
Pins
Operating Modes Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15,16,18,
1 2 3 4 5 6 7 8 9 10 11 13 14 17 20 23
19,21 & 22
Feature Function
Program Vpp Vpp Data In
Main
Array Program Inhibit Vpp Table 2 Table 3 VIHP HighZ
Product Program Verify[3] Vpp Data Out
VILP
Output Program Vpp VIHP VIHP VIHP Vpp Vpp Data In
Enable
Product
Terms
Program Inhibit
Program Verify
Vpp
Vpp
Table 2 VIHP VIHP VIHP Vpp VIHP
VIHP VIHP VIHP Vpp VILP
HighZ
Data Out
II
Sync Set, Data Data Data Data
Program Vpp VIHP VIHP VIHP VIHP Vpp VILP
Async In In In In
Reset, Program Inhibit Vpp Table 2 VIHP VIHP VIHP VIHP VIHP HighZ HighZ HighZ HighZ HighZ
Top Test,
Bottom Test Program Verify Data Data Data Data
Vpp VIHP VIHP VIHP VIHP VILP Driven
Notes Out Out Out Out
Program Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp Vpp Data In
Architec-
tureBits Program Inhibit Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Table 4 Vpp VIHP HighZ
Program Verify Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp VILP Data Out
Program Vpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP VILP VILP VILP VILP
Security
Bit Data
Verify VILP VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Driven Outputs
Out
Normal CP/I I I I I I I I I I I I I/O
PAL Phantom NA I NA NA NA Vpp I NA NA I I NA Output

Mode Top Test I I I I I I I I Vpp I I I NA Out
Operation
Bottom Test I I I I I I I I I Vpp I I Out NA
Reg Preload Notes NA NA NA NA NA NA Vpp NA NA NA VILP Data In
Phantom Program Vpp VILP VILP VILP Vpp Vpp Data In
Array
Program Inhibit Vpp VILP VILP Table 5 VILP Vpp Table 3 VIHP HighZ
Product
Terms Program Verify Vpp VILP VILP VILP Vpp VILP Data Out
Phantom Program Vpp VILP VILP VILP Vpp VIHP VIHP VIHP Vpp Vpp Data In
Output
Enable Program Inhibit Vpp VILP VILP Table 5 VILP Vpp VIHP VIHP VIHP Vpp VIHP HighZ
Product
Program Verify Vpp VILP VIL VILP Vpp VIHP VIHP VIHP Vpp VILP Data Out
Terms
Notes:
1. DATA IN and DATA OUT for programming Synchronous Set, 2. The preload clock on pin 1 loads the Registers on a LOW going
Asynchronous Reset, TOP TEST and BOTTOM TEST is pro- HIGH transition.
grammed and verified on the following pins. 3. It is necessary to toggle OE (Pin 13) HIGH during all address tran-
Pin 14 = BOTTOM TEST sitions while in the program verifylblank check mode.
Pin 17 = Synchronous Set
Pin 20 = Asynchronous Reset
Pin 23 = TOP TEST
4-71
~ PAL C 22Vl0B/PAL C 22Vl0
~~~~U~R==================================================================
Table 2 is used during the programming and verification of It provides the addressing for the 44 normal input term
the main array, output enable, asynchronous reset, syn- columns which are connected with an EPROM transistor
chronous preset, TOP and BOTTOM TEST as shown in to the product terms.
Table 1.

Table 2
Input Pin Pin Pin Pin Pin Pin
Term 2 3 4. 5 6 7
0 VILP VILP VILP VILP VILP VILP
1 VIHP VILP VILP VILP VILP VILP
2 VILP VIHP VILP VILP VILP VILP
3 VIHP VIHP VILP VILP VILP VILP
4 VILP VILP VIHP VILP VILP VILP
5 VIHP VILP VIHP VILP VILP VILP
6 VILP VIHP VIHP VILP VILP VILP
7 VIHP VIHP VIHP VILP VILP VILP
8 VILP VILP VILP VIHP VILP VILP
9 VIHP VILP VILP VIHP VILP VILP
10 VILP VIHP VILP VIHP VILP VILP
11 VIHP VIHP VILP VIHP VILP VILP
12 VILP VILP VIHP VIHP VILP VILP
13 VIHP VILP VIHP VIHP VILP VILP
14 VILP VIHP VIHP VIHP VILP VILP
15 VIHP VIHP VIHP VIHP VILP VILP
16 VILP VILP VILP VILP VIHP VILP
17 VIHP VILP VILP VILP VIHP VILP
18 VILP VIHP VILP VILP VIHP VILP
19 VIHP VIHP VILP VILP VIHP VILP
20 VILP VILP VIHP VILP VIHP VILP
21 VIHP VILP VIHP VILP VIHP VILP
22 VILP VIHP VIHP VILP VIHP VILP
23 VIHP VIHP VIHP VILP VIHP VILP
24 VILP VILP VILP VIHP VIHP VILP
25 VIHP VILP VILP VIHP VIHP VILP
26 VILP VIHP VILP VIHP VIHP VILP
27 VIHP VIHP VILP VIHP VIHP VILP
28 VILP VILP VIHP VIHP VIHP VILP
29 VIHP VILP VIHP VIHP VIHP VILP
30 VILP VIHP VIHP VIHP VIHP VILP
31 VIHP VIHP VIHP VIHP VIHP VILP
32 VILP VILP VILP VILP VILP VIHP
33 VIHP VILP VILP VILP VILP VIHP
34 VILP VIHP VILP VILP VILP VIHP
35 VIHP VIHP VILP VILP VILP VIHP
36 VILP VILP VIHP VILP VILP VIHP
37 VIHP VILP VIHP VILP VILP VIHP
38 VILP VIHP VIHP VILP VILP VIHP
39 VIHP VIHP VIHP VILP VILP VIHP
40 VILP VILP VILP VIHP VILP VIHP
41 VIHP VILP VILP VIHP VILP VIHP
42 VILP VIHP VILP VIHP VILP VIHP
43 VIHP VIHP VILP VIHP VILP VIHP
4-72
~~~NDUcroR =====================================================================
Product Term Addresses Phantom Input Term Addressing
Table 3 is used for the programming of the "PHANTOM" Phantom input terms are addressed as columns PO thru P3
and normal array. It provides the addressing for the up to and represent inputs from pins 2, 7, 10 and 11 respectively.
16 product terms associated with each input. Notice that Pin 7 is inverted, and the remaining 3 are normal non-in-
the number of product terms varies from 8 to 16 and back verting. This PHANTOM array allows the output struc-
to 8 from the top to the bottom output. In Table 3, product tures to be tested. They are only present in PHANTOM
term "0" refers to the top product term associated with the modes of operation.
MACROCELLS on pins 18 and 19, while address 15 refers
to the bottom or last product term associated with the Phantom Input Term Addresses
same pins. In the same manner, the 8 product terms associ- Table 5
ated with pins 14 and 23 are addressed as "0" through "7".
The balance of the product terms associated with the re- Phantom
maining I/O pins are addressed as "0" through "10", "12" Pin Pin
Input
and "14". 4 5
Term
Product Term Addresses PO VILP VILP
PI VIHP VILP
Table 3 P2 VILP VIHP
Product Pin Pin Pin Pin P3 VIHP VIHP
Term 8 9 10 11
0 VILP VILP VILP VILP
Programming Flow Chart
1 VIHP VILP VILP VILP The programming flow chart describes the sequence of op-
2 VILP VIHP VILP VILP erations for programming the NORMAL and PHANTOM
3 VIHP VIHP VILP VILP arrays, the NORMAL and PHANTOM output enable
4 VILP VILP VIHP VILP product terms, the set and preset product terms, the Top
5 VIHP VILP VIHP VILP
Test product term, the Bottom Test product term, and the
6 VIHP VIHP
architecture bits. The exact sequencing and timing of the
VILP VILP
7
signals is shown in the "Array Programming Timing Dia-
VIHP VIHP VIHP VILP
gram".
8 VILP VILP VILP VIHP
9 VIHP VILP VILP VIHP The logical sequence to program the device is described in
10 VILP VIHP VILP VIHP detail in the flow chart below, and should be followed ex-
11 VIHP VIHP VILP VIHP actly for optimum intelligent programming that both mini-
12 VILP VILP VIHP VIHP mizes programming time and realizes reliable program-
13 VIHP VIHP VIHP
ming. Particular attention should be paid to the application
VILP
14 of Vee prior to Vpp, and removal ofVpp prior to Vee. See
VILP VIHP VIHP VIHP
15
Figure 8 and Table 7 for specific timing and AC require-
VIHP VIHP VIHP VIHP
ments. Notice that all programming is accomplished with-
out switching Vpp on pin 1 and that after programming
Architecture Bit Addresssing and verifying all locations individually, the programmed
Table 4 provides the addressing for the architecture bits locations should be verified one final time.
used to control the configuration of the individual MAC- The normal word programming cycle, programs and veri-
ROCELLS. In the unprogrammed state, the MACRO- fies a word at a time as shown in the programming flow-
CELLS are in a registered, active low or inverting configu- chart, Figure 7 and timing diagram Figure 8. After allioca-
ration. They are programmed with a "I" on the pin associ- tions are programmed, the flowchart requires a verify of all
ated with the MACROCELL and the appropriate address words. There is no independent timing diagram for this
as shown in Table 4. Each architecture bit that is not to be operation, rather Figure 8 also provides the correct timing
programmed, requires a "0" on the 110 pin associated with information for this operation. When performing this veri-
the MACROCELL. fy only operation, eliminate the program portion of the
cycle but maintain the setup and hold timing relative to the
Architecture Bit Addresssing verify pulse. Under no circumstances should the verify sig-
Table 4 nal be held low and the addresses toggled.
Architecture Pin Pin Note that the overprogram pulse in step 10 of the program-
ming flowchart is a variable, "4" times the initial value
Bit 9 10
when programming the NORMAL, PHANTOM, TOP
Output TEST, BOTTOM TEST and OUTPUT ENABLE product
Polarity VILP VILP terms and "8" times the initial value when programming
CO the ARCHITECTURE BITS.
Register/
Non-Register VIHP VILP
Output C1
4-73
~ CYFRPSS PAL C 22VI0B/PAL C 22VI0
~~~~u~========================================================~~~
Programming Flowchart
START
Vec = 5.0V
Vpp = SEE NOTE 2
ADDRESS FIRST LOCATION,
Notes:
1. This value is "4" for program-
PLACE DATA TO BE PROGRAMMED ming the NORMAL array,
ON THE I/o PINS PHANTOM array TOP TEST,
BOTTOM TEST and OUTPUT
ENABLE PRODUCT TERMS.
The value is "s" when program-
x=O ming ARCHITECTURE BITS.
2. Vpp, Programming Voltage:
For PAL C 22VlOB = 12.5V
For PAL C22VlO = 13.5V
PROGRAM ONE PULSE
OF O.4ms
x= x+ 1
X=5
NO
VERIFY ONE WORD

PASS
PROGRAM ONE PULSE OF

NOTE 1) 0.4 x) ms
x= 5
NO~--------~----~--~
"'----~
YES
VERIFY ALL WORDS AT
Vecp =5.5 VOLTS
PASS
GOOD DEVICE
Vpp =o.OV
Vee = o.OV
STOP
0023-7
Figure 7
4-74
~~~~UcrOR=====================================================================
Timing Diagrams
Programming timing diagrams are provided for two cases, DATA OUT is verified on the same pins. A "I" (V IHP) on
programming of all cells except the SECURITY BIT and an I/O pin causes the addressed location to be pro-
programming the SECURITY BIT. grammed. A "0" on the I/O pin leaves the addressed loca-
tion to be unprogrammed. All setup hold and delay times
Array must be met, and in particular the sequence of operations
Programming the NORMAL and PHANTOM arrays and should be strictly followed. During verify only operation it
output enables, reset, preset, architecture bits and the top/ is not acceptable to hold PGM/VFY low and sequence
bottom test features uses the timing diagram in Figure 8. addresses, as it violates address setup and hold times. Prop-
ADDRESS refers to all applicable information in Tables 1 er sequencing of all power and supervoltages is essential, to
through 5 that is not specifically referenced in the timing reliable programming of the device as improper sequencing
diagram. DATA IN is provided on the I/O pins and could result in device damage.
Programming Waveforms
Veep
Vee PIN 24-
NOTE 1 V -
ss
Vpp
Vpp PIN 1
Vss ~--------------TDP------------~
V1HP
ADDRESS
NOTE 2
V1LP -
V1HP
DATA
V1LP -
PGMjVF'Y
PIN 13
V1HP -
V1LP -
---------.....01(
0023-8
Notes:
1. Power, V pp & Vee should not be cycled for each program/verify 2. For programming OE Product Terms & Architecture bits, Pin II
cycle, but may remain static during programming. (A9) must go to Vpp and satisfy TAS and TAN.
Figure 8
4-75
~~~~UaoR================================================================~
Security Cell
The security cell is programmed independently per the tim- same pin. A "0" on pin 3 indicates that the security bit has
ing diagram in Figure 9, and the information in Table 1. been programmed, and a "I" indicates that security bit has
Note again that proper sequencing of power and program- not been programmed. Security is programmed with a sin-
ming signals is required. Data in is represented as a super- gle 50 ms pulse on pin 13. A supervoltage on pin 4 is used
voltage on pin 3 and verified as a TTL signal output on the to verify security after Vpp has been removed from pin 1.
Programming Waveforms Security Cell
Vee PIN 24
Vccp
VSS -
-
-J Tp ~I.~ ___________ TP ____________ ~~
vpp_
Vpp PIN 1
VSS- Top
Vpp_
DATA PIN3
V1HP -
V1LP -
Vpp_
PGM
PIN 13
V1LP _
I+------Tov
Vpp_
SECURITY
VFY
PIN4
V1LP -
0023-9
Figure 9
4-76
~~~~UaoR==================================================================
Table 6
Vpp for PAL C 22VlOB Programming Voltage 12.0 13.0 Volts
Vppfor PAL C22VlO Programming Voltage 13.0 14.0 Volts
Supply Voltage
Veep 4.75 5.25 Volts
During Programming
Input HIGH Voltage
VIHP 3.0 Veep Volts
During Programming
Input LOW Voltage
VILP -3.0 0.4 Volts
During Programming
VOH Output HIGH Voltage 2.4 Volts
VOL Output LOW Voltage 0.4 Volts
Programming
Ipp 40 rnA
Supply Current
AC Programming Parameters
Table 7
Delay to Programming
Tp 20 ms
Voltage
Top Delay to Program 1 JLs
Hold from Program
THP or Verify
1 JLs
TR,F Vpp Rise & Fall Time 50 ns
TAS Address Setup Time 1 JLs
TAH Address Hold Time 1 JLs
Tos Data Setup Time 1 JLs
TOH Data Hold Time 1 JLs
Tpp Programming Pulsewidth 0.4 10 ms
Programming Pulsewidth
Tspp 50 ms
for Security
Delay from Program
TOY 2 JLs
to Verify
Tyo Delay to Data Out 1 JLs
Typ Verify Pulse Width 2 JLs
Toz Verify to High Z 1 JLs
4-77
~~~~UcrOR================================================================
ICC tpD ts teo
Ordering Code Package Operating Range
(rnA) (ns) (ns) (ns)
90 15 10 10 PAL C 22VI0B-15PC/PI P13 Commercial/Industrial
PAL C 22VlOB-15WC/WI W14
PAL C 22VlOB-15JC/JI J64
90 20 12 12 PAL C 22VlO-20PC/PI P13 Commercial/Industrial
PAL C 22VlO-20WC/WI W14
PAL C 22VlO-20JC/JI J64
120 20 17 15 PAL C 22VlOB-200MB 014 Military
I PAL C 22VlOB-20WMB W14
PAL C 22VI0B-20LMB L64
PAL C 22VlOB-20QMB Q64
PAL C 22VlOB-20KMB K73
55 25 15 15 PAL C 22VlOL-25PC P13 Commercial
PAL C 22VlOL-25WC W14
PAL C 22VI0L-25JC J64
100 25 18 15 PAL C 22VlO-250MB 014 Military
PAL C 22VlO-25WMB W14
PAL C 22VlO-25LMB L64
PAL C 22VlO-25QMB Q64
PAL C 22VlO-25KMB K73
PAL C 22VIO-30QMB Q64
55 35 30 25 PAL C 22VlOL-35PC P13 Commercial
PAL C 22VlOL-35WC W14
PAL C 22VlOL-35JC J64
PAL C 22VlO-40QMB Q64
4-78
~~~~UcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
Ioz 1,2,3
ICC 1,2,3
tpD 7,8,9,10,11
teo 7,8,9,10,11
ts 7,8,9,10,11
tH 7,8,9,10,11
tw 7,8,9,10,11
4-79
CY7C330
CYPRESS
SEMICONDUCTOR CMOS Programmable
Synchronous State Machine
Features
12 I/O macro cells each having: 256 product terms-32 per pair The unique architecture of the
- registered, three-state I/O of macro cells, variable CY7C330, consisting of the user-con-
pins distribution figurable output macrocell, bi-direc-
- input register clock select Global, synchronous, product tional I/O capability, input registers,
multiplexer term controlled, state register and three separate clocks, enables the
- feed back multiplexer set and reset-inputs to product user to design high performance state
- output enable (OE) term are clocked by input clock machines that can communicate either
multiplexer with each other or with microproces-
66 MHz operation sors over bi-directional parallel busses
All twelve macro cell state - 3 ns input setup and 12 ns
registers can be hidden of user-definable widths.
clock to output
User configurable state - 15 ns input register clock to The three separate clocks permit inde-
registers-JK, RS, T, or D state register clock pendent, synchronous state machines
Input multiplexer per pair of to be synchronized to each other. The
Low power two input clocks, Cl, C2, enable the
I/O macro cells allows I/O pin -130 mA Icc
associated with a hidden macro state machine to sample input signals
cell state register to be saved for 28 pin 300 mil DIP, LCC that may be generated by another sys-
use as an input Erasable and reprogrammable tem and that may be available on its
4 dedicated hidden registers bus for a short period of time.
Product Characteristics The user-configurable state register
11 dedicated, registered inputs
3 separate clocks-2 inputs, The CY7C330 is a high-performance, flip-flops enable the designer to desig-
1 output eraseable, programmable, logic device nate JK, RS, T, or D type devices, so
(EPLD) whose architecture has been that the number of product terms re-
Common (PIN 14 controlled) or optimized to enable the user to easily
product term controlled output quired to implement the logic is mini-
and efficiently construct very high per- mized.
enable for each I/O pin formance synchronous state machines.
LCCPinout
DE/II 0 19 Is 17 Is 15 Vss 14 13 12 lo/CK2 CKI ClK
.:~Bd~~g:
4 3 2: 1 : 28 27 26 )
5 25
'2 1/03
6 24
I/O.
23
I/O.
Vss 22 Vee
10 9 21 Vss
Ie 10 20 I/Oe
0
17 11 19 1/ 7
12131'~ 16!ZJ! )
-..... ,~~i~~ 0101-14
PLCCPinout
.:~Bd~~g:
1/0 3
I/O.
I/O.
22 Vee
21 Vss
I/O.
1/07
1/10 I/Os 1/7 I/Os vss Vee 1/0 5 1/4 1/2 1/0 ~~~~i~~ 0101-15
0101-1
Selection Guide
CY7C33066 CY7C33050 CY7C33040 CY7C33033 CY7C33028
Commercial 66.6 50.0 33.3
Maximum Operating Frequency (MHz)
Military 50.0 40.0 28.5
Power Supply Current ICCl (rnA)
480
~ CY7C330
~~~NDUcroR =====================================================================
Product Characteristics (Continued) Macro Cell Input Multiplexer
The major functional blocks ofthe CY7C330 are (1) the Each pair of 1/0 macro cells share a Macro Cell Input
input registers and (input) clock multiplexers, (2) the Multiplexer which selects the output of one or the other of
EPROM (AND) cell array, (3) the twelve 1/0 macrocells the pair's input registers to be fed to the input array. This
and (4) the four hidden registers. multiplexer is shown in Figure 2. The Macro Cell Input
Multiplexer allows the input pin of a macro cell, for which
Input Registers and Clock Multiplexers the state register has been hidden by feeding back its input
There are a total of eleven dedicated Input Registers. Each to the input array, to be preserved for use as an input pin.
Input Register consists of a D flip-flop and a clock multi- This is possible as long as the other macro cell of the pair is
plexer. The clock multiplexer is user-programmable to se- not needed as a input or does not require State Register
lect either CKI or CK2 as the clock for the flip-flop. CK2 feed back. The input pin input register output which would
and OE can alternatively be used as inputs to the array. normally be blocked by the hidden State Register feed back
The twenty-two outputs of the registers (i.e. the Q and Q can be routed to the array input path of the companion
outputs of the input registers) drive the array of EPROM macro cell for use as array input.
cells.
State Registers
An architecture configuration bit (C4) is reserved for each
Dedicated Input Register cell to allow selection of either By use of the exclusive or gate the State Register may be
input clock CK 1 or CK2 as the input register clock for configured as a JK, RS or T Register. The default is a
each Dedicated Input Cell. If the CK2 clock is not needed D-Type register. For the D-Type register, the exclusive or
that input may also be used as a general purpose array function can be used to select the polarity or the register
input. In this case the Input Register for this input can output.
only be clocked by input clock CK 1. Figure 1 illustrates The set and reset of the State Register are global synchro-
the Dedicated Input Cell composed of input register, Input nous signals which are controlled by the logic of two global
Clock Multiplexer, and architecture configuration bit C4 product terms for which input signals are clocked through
which determines the input clock selected. the input registers by either of the input clocks, CKI or
1/0 Macro Cell CK2.
The logic diagram of the CY7C330 1/0 macro cell is Hidden Registers
shown in Figure 2. There are a total of twelve indentical In addition to the twelve macro cells, which contain a total
macro cells. of twenty-four registers, there are four hidden registers
Each macro cell consists of: whose outputs are not brought out to the device output
- An Output State Register which is clocked by the global pins. The Hidden State Register Macro Cell is shown in
state counter clock, CLK (PIN 1). The State Register Figure 3.
can be configured as a D, JK, RS, or T flip-flop (default The four hidden registers are clocked by the same clock as
is a D-type flip-flop). Polarity can be controlled in the the macrocell state registers. All of the hidden register flip-
D flip-flop implementation by use of the exclusive or flops have a common, synchronous set, S, as well as a com-
function. Data is sampled on the LOW to HIGH clock mon, synchronous reset, R, which over-ride the data at the
transition. All of the State Registers have a common D input. The Sand R signals are PRODUCT TERMS that
reset and set which are controlled synchronously by are generated in the array and are the same signals used to
Product Terms which are generated in the EPROM cell preset and reset the state register flip-flops.
array.
Macrocell Product Term Distribution
- A Macro Cell Input Register which may be clocked by
either the CKI or CK2 input clock as programmed by Each pair of macro cells has a total of thirty-two product
the user by use of architecture configuration bit C2 terms. Two product terms of each macrocell pair are used
which controls the I/O Macro Cell Input Clock Multi- for the output enables (OEs) for the two output pins. Two
plexer. The Macro Cell Input Registers are initialized product terms are also used as one input to each of the two
on power up such that all of the Q outputs are at logic exclusive OR gates in the macrocell pair. The number of
LOW level and the Q outputs are at a logic HIGH level. product terms available to the designer is then 32 - 4 =
28 for each macrocell pair. These product terms are divid-
- An Output Enable Multiplexer (OE), which is user-pro- ed between the macro cell state register flip-flops as shown
grammable, by architecture configuration bit CO, to se- in Table 1.
lect either the common OE signal from pin 14 or, for
each cell individually, the signal from the Output En- Table 1. Product Term Distribution
able product term associated with each macro cell. The Macro Cell Pin No. Product Terms
Output Enable input signal to the array product term is
clocked through the input register by the selected input
0 28 9
register clock, CK 1 or CK2.
1 27 19
2 26 11
- An input Feed Back Multiplexer which is user-pro- 3 25 17
grammable to select either the output of the State Regis- 4 24 13
ter or the output of the Macro Cell Input Register to be 5 23 15
fed back into the array. This option is programmed by 6 20 15
architecture configuration bit Cl. If the output of the 7 19 13
Macro Cell Input Register is selected by the Feed Back 8 18 17
Multiplexer, the 1/0 pin becomes bi-directional. 9 17 11
10 16 19
11 15 9
4-81
~ CY7C330
~~~U~R==================================================================
Product Characteristics (Continued)
Hidden State Register Product Term Distribution Table 2. Hidden State Register Product Term Distribution
Each pair of hidden registers also has a total of 32 product Hidden Register Cell Product Terms
terms. Two product terms are used as one input to each of
the exclusive OR gates. However, because the register out- 0 19
puts do not go to any output pins, output enable product 1 11
terms are not required. Therefore, 30 product terms are 2 17
available to the designer for each pair of hidden registers. 3 13
The product term distribution for the four hidden registers
are shown in Table 2. Architecture Configuration Bits
The architecture configuration bits are used to program the
multiplexers. The function of the architecture bits is out-
lined below.
Table 3. Architecture Configuration Bits

Architecture Number
Value Function
Configuration Bit of Bits
CO Output Enable 12 Bits, 1 Per O-Virgin State Output Enable Controlled by Product Term
SelectMUX I/O Macro Cell I-Programmed Output Enable Controlled by Pin 14
Cl State Register 12 Bits, 1 Per O-Virgin State State Register Output is Fed Back to Input Array
Feed Back MUX I/O Macro Cell I-Programmed I/O Macro Cell is Configured as an Input
and Output of Input Register is Fed to Array
C2 I/O Macro 12 Bits, 1 Per 0-Virgin State CKI Input Register Clock (Pin 2) is Connected
Cell Input I/O Macro Cell to I/O Macro Cell Input Register Clock Input
Register Clock I-Programmed CK2 Input Register Clock (Pin 3) is Connected
SelectMUX to I/O Macro Cell Input Register Clock Input
C3 I/O Macro Cell 6 Bits, 1 Per O-Virgin State Selects Data from I/O Macro Cell Input Register
Pair Input I/O Macro Cell of Macro Cell A of Macro Cell Pair
SelectMUX Pair I-Programmed Selects Data from I/O Macro Cell Input Register
of Macro Cell B of Macro Cell Pair
C4 Dedicated Input 11 Bits, 1 Per O-Virgin State CKI Input Register Clock (Pin 2) is Connected
Register Clock Dedicated Input to Dedicated Input Register Clock Input
SelectMUX Cell I-Programmed CK2 Input Register Clock (Pin 3) is Connected
to Dedicated Input Register Clock Input
INPUT REGISTER
1-+---------10 Q 1----+-11.J'1r'-_ _
PIN2:CK1
PIN3:CK2
C4
0101-5
Figure 1. Dedicated Input Cell
4-82
~R&SS CY7C330
_~bJICONDUcrOR =:=:=:=:=:=:=:=:=:=:=:=:=:=:=:=:=:=:================================
co
PIN 14: Of - - - - t
OUTPUT ENABLE PRODUCT TERM
SET PRODUCT TERM
RESET PRODUCT TERM
TO ARRAY
Cl
TO ARRAY
FROM ADJACENT MACRO CELL

C3
0101-6
Figure 2. 1/0 Macro Cell and Shared Input Multiplexer
SET PRODUCT TERM
RESET PRODUCT TERM
TO ARRAY
0101-8
Figure 3. Hidden State Register Macro Cell
4-83
~ CY7C330
~~~UaoR==================================================================
Maximum Ratings
Supply Voltage to Ground Potential DC Programming Voltage ...................... 13.0V
(Pin 22 to Pins 8 and 21) .............. -0.5V to + 7.0V
Operating Range
in High Z State ...................... -0.5V to +7.0V Ambient
Range Vee
Temperature
Commercial OOCto +75C 5V 1O%

Vee = Min., IOH = -3.2mA COM'L
VIN = VIH or VIL IOH = -2mA MIL
Vee = Min., IOL = 12mA COM'L
VIN = VIH or VIL IOL = 8mA MIL
Guaranteed Input Logical HIGH Voltage
for All Inputs [1]
Guaranteed Input Logical LOW Voltage
for All Inputs [1]
IIX Input Leakage Current VSS:;:;; VIN:;:;; Vee, Vee = Max. -10 10 p.A
Ioz Output Leakage Current Vee = Max. Vss:;:;; VOUT:;:;; Vee -40 40 p.A
Standby Power Supply Vee =Max., VIN = GND COM'L 130 mA
Ieel
Current Outputs Open MIL 150 mA
COM'L (-33 MHz & -50 MHz) 160 mA
Vee = Max.
Power Supply Current Outputs Disabled (in High Z State) COM'L (-66 MHz)[I5] 180 mA
Iee2
at Frequency [3.7] Device Operating at fMAX MIL (-28 MHz & -40 MHz) 180 mA
External (fMAXI)
MIL (-50 MHz)[I5] 200 mA
Capacitance [3]
Parameters Description Test Conditions Min Max Units
CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 7
pF
CoUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8
Notes:
1. These are absolute values with respect to device ground and all over- 10. This difference parameter is designed to guarantee that any
shoots due to system or tester noise are included. CY7C330 output fed back to its own inputs externally or internally
2. Not more than one output should be tested at a time. Duration of the will satisfy the input register minimum input hold time. This param-
short circuit should not be more than one second. VOUT = 0.5V has eter is guaranteed for a given individual device and is tested by a
been chosen to avoid test problems caused by tester ground degrada- periodic sampling of production product.
tion. 11. This specification is intended to guarantee feeding of this signal to
3. Tested initially and after any design or process changes that may another 33X family input register cycled by the same clock with
affect these parameters. sufficient output data stable time to insure that the input hold time
4. Figure 4a test load used for all parameters except tCEA. tCER. tpzx minimum of the following input register is satisfied. This parameter
and tpxz. Figure 4b test load for tCEA. tcER. tpzx. tpxz. difference specification is guaranteed by periodic sampling of pro-
duction product of CYC330 and CY7C332. This difference parame-
5. TA is the "instant on" case temperature. ter is guaranteed to be met only for devices at the same ambient
6. See the last page of this specification for Group A subgroup testing temperature and VCC supply voltage.
information. 12. This specification indicates the guaranteed maximum frequency at
7. This parameter is sample tested periodically. which a state machine configuration with external feed back can
8. This parameter is measured as the time after output register disable operate.
input that the previous output data state remains stable on the output. 13. This specification indicates the guaranteed maximum frequency at
This delay is measured to the point at which a previous high level has which an individual input or output register can be cycled.
fallen to 0.5V below VOH Min or a previous low level has risen to 14. This specification indicates the guaranteed maximum frequency at
O.SV above VOL Max. Please see Figure 6 for enable and disable test which a state machine configuration with only internal feedback can
waveforms and measurement reference levels. operate. This parameter tested periodically on a sample basis.
9. This parameter is measured as the time after output register clock 15. Preliminary specifications.
input that the previous output data state remains stable on the output.
4-84
~ CY7C330
~~~~UaoR==================================================================
Commercial Military
Parameters Description -66[15] -50 -33 -50[15] -40 -28 Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input or Feedback Setup Time
tIS 3 5 10 5 5 10 ns
to Input Register Clock
Input Register Clock to
tos 15 20 30 20 25 35 ns
Output Register Clock
Output Register Clock
tco 12 15 20 15 20 25 ns
to Output Delay
tIH Input Register Hold Time 5 5 5 5 5 5 ns
Input Register Clock To
tCEA 15 20 30 20 25 35 ns
Output Enable Delay
Input Register Clock to
tCER 15 20 30 20 25 35 ns
Output Disable Delay[8]
Pin 14 Enable to Output
tpzx 15 20 30 20 25 35 ns
Enable Delay
Pin 14 Disable to Output
tpxz 15 20 30 20 25 35 ns
Disable Delay[8]
tWH Input or Output Clock Width High[3, 7] 6 8 12 8 10 15 ns
tWL Input or Output Clock Width Low[3, 7] 6 8 12 8 10 15 ns
External Clock Period (tco + tIS)
tp 15 20 30 20 25 35 ns
Input and Output Clock Common
Output Data Stable Time from
tOH 3 3 3 3 3 3 ns
Synchronous Clock Input[9]
Output Data Stable Time
tOH-tIH This Device Minus liP Reg 0 0 0 0 0 0 ns
Hold Time Same Device[lO]
tOH- Output Data Stable Time Minus liP
0 0 0 0 0 0 ns
tIH 33X Reg Hold Time 7C330 & 7C332[11l
External Maximum Frequency
fMAXl 66.6 50.0 33.3 50.0 40.0 28.5 MHz
(l/(tco + tIS[12]
Data Path Maximum Frequency
fMAX2 83.3 62.5 41.6 62.5 50.0 33.3 MHz
(l/(tWH + tWL[7, 13]
fMAX3 Internal Maximum Frequency[14] 74.0 57.0 37.0 57.0 45.0 30.0 MHz
4-85
~ CY7C330
~~~NDUcrOR =====================================================================
R1 R1 INPUT PULSES
313.0. 313.0.
5V;i(470.o.
MIL) 5VT-i(470.o.
MIL) 3.0V-----:::~~--~~
OUTPUT OUTPUT
~~8.o.
J _~~8.o.
50pF GND
INCLUDING
JIG AND
I (319.0. MIL)
5pF
(319.0. MIL)
,;; 5ns
SCOPE -= -= Figure 5
0101-10
0101-9
Figure4a Figure4b
125.0. 190.0.
OUTPUT ~ 2.00V =Vthc OUTPUT =
o---'I/'II'v-O 2.02V Vthm
0101-11 0101-12
Switching Waveforms
I/O INPUTS, REGISTERED
FEEDBACK INPUTS
=t _ _ _ __
tiS
INPUT CLOCK
-----"'1
OUTPUT CLOCK
-------"'1
OUTPUTS ~----~r---~~----~~~--------~~----------~~------
tpxi811 ~
PIN~ ~ _______________________________________________
0101-13
4-86
4, 5,)
LO "1111111
16 3
RESET node =29
~m ~ l.L. L17028 3)
~I~
(CO ..
m--
"'U'9 L661WIIIII
III.!.{'''''''''''':; _.....
L792 node=40
'19ol~ L17032 2)(CO
III
-I ...
~L:2~17:8J11111~1I1I1I1I~1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I::~~
L17035 (co.. 3)
LITH l--i-
~ =39
node
17~~ .. L17039 2) (CO .
.....
~
~L:4:29:01l1l1l~1I1I1I1I1I1I1I1I1I1I1I1I1i1l1l1l1l1l1l1l~~~
3)
I~~
L17042 (CO
LlIH )-t. _.....

L5280 ... node=38
115~~ 100 L17046 2)(CO
-A
L6402 ...
11'~ ] node =34
L7722
17075 .
...
'~ ] node =33
I- - - - - - - - - - - T O LOWER SECTION _ _ _ _ _ _ _ _ _ _ _ _ _---1

0101-17
CY7C330 Block Diagram (Page 1 of 2)
4-87
r - - - - - - - - - - - T O UPPER SECTION - - - - - - - - - - - - - -
0101-18
CY7C330 Block Diagram (Page 2 of 2)
4-88
~ CY7C330
~~~~UaoR==================================================================
tpxz(-) 1.5V
VOH
o.~v ~- Vx 0101-19
tpxz(+) 2.6V
VOL
o.}v rr- 1.5V
Vx
0101-20
tpzx(+) Vthc
Vx
+1: VOH

0101-21
tpzx(-)
+~k
Vthc
Vx
VOL
0101-22
tCER(-) 1.5V
VOH
o.}v ~~
Vx 0101-19
tCER(+) 2.6V Vx
VOL
o.}v
1: 1.5V
0101-20
tCEA(+ ) Vthc
+rt
VOH
Vx
0101-21
tCEA(-)
+~
Vthc
Vx
VOL
0101-22
Figure 6. Test Waveforms

fmax(MHz) ICC! (mA) Ordering Code Package Operating Range
66.6 130 CY7C33066PC P21 Commercial
CY7C33066WC W22
CY7C33066JC J64
50 150 CY7C330500MB 022 Military
CY7C33050WMB W22
CY7C33050LMB L64
CY7C33050TMB T74
CY7C3305OQMB Q64
50 130 CY7C33050PC P21 Commercial
CY7C33050WC W22
CY7C33050JC J64
40 150 CY7C330400MB 022 Military
CY7C33040WMB W22
CY7C33040LMB L64
CY7C33040TMB T74
CY7C330~4OQMB Q64
33.3 130 CY7C33033PC P21 Commercial
CY7C33033WC W22
CY7C33033JC J64
28.S ISO CY7C330280MB 022 Military
CY7C33028WMB W22
CY7C33028LMB L64
CY7C33028TMB T74
CY7C33028QMB Q64
489
~ CY7C330
~~~~UaDR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
IOZ 1,2,3
IcC 1,2,3
tISU 9,10,11
tosu 9,10,11
tco 9,10,11
tH 9,10,11
tCEA 9,10,11
tpzx 9,10,11
4-90
CY7C331
CYPRESS
SEMICONDUCTOR Asynchronous Registered
EPLD
12 I/O macrocells each having: 13 inputs, 12 feedback I/O pins, The CY7C331 is the most versatile
- One state Flip-Flop with an plus 6 shared I/O macrocell PLD available for asynchronous de-
XOR sum or products input feedbacks for a total of 31 true signs. Central resources include 12 full
- One feedback Flip-Flop with and complementary inputs D-type Flip-Flops with separate set, re-
input coming from the I/O High speed: 20 tpD ns maximum set and clock capability. For increased
utility, XOR gates are provided at the
4
pin
- Independent (product term) Security bit D-inputs and the product term alloca-
set, reset, and clock inputs on Space saving 28 pin slim-line tion per Flip-Flop is variably distribut-
all registers DIP package; also available in ed.
- Asynchronous bypass 28 pin PLCC
capability on all registers, I/O Resources
under product term control Low power
- 90 mA typical Icc quiescent Pins 1 through 7 and 9 through 14
(r=s=1) serve as array inputs; pin 14 may also
- Global or local output enable - 180 mA Icc maximum
- UV-Eraseable and be used as a global output enable for
on tristate I/O the I/O macrocell tristate outputs. Pins
- Feedback from either register reprogrammable
- Programming and operation 15 through 20 and 23 through 28 are
to the array connected to I/O rnacrocells and may
100% testable
192 product terms with variable be managed as inputs or outputs de-
distribution to macrocells pending on the configuration and the
macrocell OE terms.

10 PLCCPinout
0100-2
Vss Vee 1/05 1/04 1/03 1/02 1/01 1/00

0100-1
Selection Guide
Generic ICCl mA tpDns ts ns tcons
Part Number Com Mil Com Mil Com Mil Com Mil
CY7C331-20[19] 120 20 12 20
CY7C331-25 120 150[19] 25 25[19] 12 15[19] 25 25[19]
CY7C331-30 150 30 15 30
CY7C331-35 120 35 15 35
CY7C331-40 150 40 20 40
4-91
~ CY7C331
~~~U~================================================================
I/O Resources (Continued) OUTPUT FROM
LOGIC ARRAY
It should be noted that there are two ground connections
(pins 8 and 21) which, together with Vee (pin 22) are FEEDBACK TO
located centrally on the package. The reason for this place- LOGIC ARRAY
ment and dual ground structure is to minimize the ground- Q - OUTPUT FROM
loop noise when the outputs are driving simultaneously INPUT REGISTER OF
I/O MACRO CELL A
into a heavy capacitive load. INPUT TO
LOGIC ARRAY
Q - OUTPUT FROM
co INPUT REGISTER OF
I/O MACRO CELL B
OUTPUT FROM
OUTPUT ENABLE PRODUCT TERM LOGIC ARRAY
FEEDBACK TO
LOGIC ARRAY
0100-4
Figure 2. Shared Input Multiplexer
Shared Input Multiplexer
The input associated with each pair of macrocells may be
configured by the shared input multiplexer to come from
TO ARRAY either macrocell; the 'Q' output of the Flip-Flop coming
from the I/O pin is used as the input signal source.
Product Term Distribution
INPUT REGISTER CLOCK PRODUCT TERM
The product terms are distributed to the macrocells such
that 32 product terms are distributed between two adjacent
INPUT REGISTER RESET PRODUCT TERM macrocells. The pairing of macrocells is the same as it is for
the shared inputs. 8 of the product terms are used in each
macrocell for set, reset, clock, OE and the upper part of the
TO ARRAY XOR gate. This leaves 16 product terms per pair of macro-
cells to be divided between the sum-of-product inputs to
FROM ADJACENT MACROCELL INPUT
the two state registers. The following table shows the I/O
pin pairing for shared inputs, and the product term
0100-3 (P-Term) allocation to macrocells associated with the I/O
Figure 1. Macrocell pins.
The CY7C331 has 12 macrocells. Each macrocell has two Table 2
D-type Flip-Flops. One is fed from the array, and one is fed Macrocell Pin Number Product Terms
from the I/O pin. For each Flip-Flop there are 3 dedicated
0 28 4
product terms driving the R, S, and Clock inputs respec-
tively. Each macrocell has one input to the array and for 1 27 12
each pair of macrocells there is one shared input to the 2 26 6
array. The macrocell input to the array may be configured 3 25 10
to come from the 'Q' output of either Flip-Flop. 4 24 8
5 23 8
The D-type Flip-Flop which is fed from the array (i.e., the 6 20 8
state Flip-Flop) has a logical XOR function on its input
7 19 8
which combines a single product term with a sum (OR) of
a number of product terms. The single product term is used 8 18 10
to set the polarity of the output or to implement toggling 9 17 6
(by including the current output in the product term). 10 16 12
11 15 4
The Rand S inputs to the Flip-Flops override the current
setting of the 'Q' output. The S input sets 'Q' true and the The CY7C331 is configured by three arrays of configura-
R input 'resets' 'Q' (sets it false). Ifboth Rand S are assert- tion bits (CO, Cl, C2). For each macrocell, there is one CO
ed (true) at once, then the output will follow the input bit and one C1 bit. For each pair of macrocells, there is one
('Q' = 'D'). C2 bit.
Table 1 There are 12 CO bits. If CO is programmed for a macrocell,
S
then the tristate enable (OE) will be controlled by pin 14
R Q (the global OE). If CO is not programmed, then the OE
1 0 0 product term for that macrocell will be used.
0 1 1 There is one C1 bit for each macrocell. The Cl bit selects
1 1 D input for the product term (PT) array from either the state
R-S Truth Table register (if the bit is unprogrammed) or the input register.
4-92
~ CY7C331
~~~~UcrOR =====================================================================
I/O Resources (Continued)
There are 6 C2 bits, providing one C2 bit for each pair of The timing diagrams for the CY7C33I cover state register,
macrocells. The C2 bit controls the shared input Multi- input register, and various combinational delays. Since in-
plexer (Mux); if the C2 bit is not programmed, then the ternal clocks are the outputs of product terms, all timing is
input to the product term array comes from the upper mac- from the transition of inputs causing the clock transition.
rocell (A). If the C2 bit is programmed, then the input
comes from the lower macrocell (B).
Maximum Ratings

Storage Temperature ............... -65C to + 150C Latchup Current .......................... > 200 mA
Ambient Temperature with DC Programming Voltage ...................... 13.0V
Supply Voltage to Group Potential
Operating Range
(Pin22toPinsSor21) ............... -0.5Vto +7.0V Ambient
Range Vee
Output Current into Outputs (Low) ............. 12 mA Commercial OCto + 75C 5V 10%
Static Discharge Voltage ..................... >2001V Military[S] - 55C to + 125e 5V 10%
(per MIL-STD-SS3 Method 3015)

Vee = Min., IOH = -3.2mA Commercial
Vee = Min., IOL = 12mA Commercial
VIN = VIH or VIL IOL = SmA Military
VIH Input HIGH Level Guaranteed HIGH Input, all InputsU] 2.2 V
VIL Input LOW Level Guaranteed LOW Input, all Inputs[ll O.S V
IIX Input Leakage Current Vss < VIN < Vee, < Vee = Max. -10 10 p,A
Ioz Output Leakage Current Vee = Max., VSS < VOUT < Vee -40 40 p,A
Isc Output Short Circuit Current Vec = Max., VOUT = 0.5V[2] -30 -90 rnA
Standby Power Supply Vce = Max., VIN = GND, Commercial 120 rnA
ICC I
Current Outputs Open Military 150 rnA
Vee = Max.
Commercial 180 rnA
Power Supply Current Outputs Disabled (in HIGH Z State)
Iee2 at Frequency[I9] Device Operating at fMAX
External (fMAXI) Military 200 rnA
Capacitance [3]
pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8
Notes:
1. These are absolute values with respect to device ground and all over- 3. Tested initially and after any design or process changes that may
shoots due to system or tester noise are included. affect these parameters.
2. Not more than one output should be tested at a time. Duration of the 4. Figure 3a test load used for all parameters except tpZXI, tpXZI, tpzx
short circuit should not be more than one second. VOUT = O.SV has and tpxz. Figure 3b test load for tPZXI , tpXZI, tpzx and tpxz. Figure
been chosen to avoid test problems caused by tester ground degrada- 3c shows test waveforms and measurement levels.
tion. S. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.
4-93
~ CY7C331
~~~UcrOR =====================================================================
Switching Characteristics [6]
Commercial Military
Parameters Description -20[19] -25 -35 -25[19] -30 -40 Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tpD Input to Output Propagation Delay[7] 20 25 35 25 30 40 ns
tlCO Input Register Clock to Output Delay[S] 35 40 55 45 50 65 ns
tIOH Output Data Stable Time from Input Clock[S] 5 5 5 5 5 5 ns
tiS 2 2 2 5 5 5 ns
to Input Register Clock[S]
tlH Input Register Hold Time from Input Clock[S] 11 13 15 13 15 20 ns
Input to Input Register
tlAR 35 40 55 45 50 65 ns
Asynchronous Reset Delay [8]
tlRW Input Register Reset Width[8] 35 40 55 45 50 65 ns
tlRR Input Register Reset Recovery Time[8] 35 40 55 45 50 65 ns
Input to Input Register
tlAS 35 40 55 45 50 65 ns
Asynchronous Set Delay[8]
tlSW Input Register Set Width[8] 35 40 55 45 50 65 ns
tlSR Input Register Set Recovery Time[8] 35 40 55 45 50 65 ns
tWH Input & Output Clock Width High[8, 9, 12] 12 15 20 15 20 25 ns
tWL Input & Output Clock Width Low[S, 9,121 12 15 20 15 20 25 ns
Maximum Frequency with Feedback in Input
fMAX1 27.0 23.8 17.5 20.0 18.1 14.2 MHz
Registered Mode (l/(tICO + tIS[13]
Maximum Frequency Data Path in Input
fMAX2 28.5 25.0 18.1 22.2 20.0 15.3 ns
Registered Mode (l/tICO)[8]
Output Data Stable from Input
tIOH-
Clock Minus Input Register Input Hold 0 0 0 0 0 0 ns
tIH 33X
Time for 7C330 and 7C332[15, 18]
tco Output Register Clock to Output Delay [9J 20 25 35 25 30 40 ns
toH Output Data Stable Time from Output Clock[9] 3 3 3 3 3 3 ns
Output Register Input Set Up Time to
ts 12 12 15 15 15 20 ns
Output Clock[9J
Output Register Input Hold Time from
tH 8 8 10 10 10 12 ns
Output Clock[9]
Input to Output Register
tOAR 20 25 35 25 30 40 ns
Asynchronous Reset Delay[9J
tORW Output Register Reset Width[9] 20 25 35 25 30 40 ns
tORR Output Register Reset Recovery Time[9] 20 25 35 25 30 40 ns
Input to Output Register
tOAS 20 25 35 25 30 40 ns
Asynchronous Reset Delay [9]
tosw Output Register Set Width[9] 20 25 35 25 30 40 ns
tOSR Output Register Set Recovery Time[9] 20 25 35 25 30 40 ns
tEA Input to Output Enable Delay[4, 101 20 25 35 25 30 40 ns
tER Input to Output Disable Delay[4, to] 20 25 35 25 30 40 ns
tpzx Pin 14 to Output Enable Delay[4, to] 17 20 30 20 25 35 ns
tpxz Pin 14 to Output Disable Delay[4, to] 17 20 30 20 25 35 ns
Maximum Frequency with Feedback in Output
fMAX3 31.2 27.0 20.0 25.0 22.2 16.6 MHz
Registered Mode (l/(tco + t8[14]
Max. Frequency Data Path in Output Registered
fMAX4 41.6 33.3 25.0 33.3 25.0 20.0 MHz
Mode (Lower of l/tco + l/(twH + twL[9]
Output Data Stable from Output
tOH-
Clock Minus Input Register Input Hold 0 0 0 0 0 0 ns
tIH 33X
Time for 7C330 and 7C332[16, 1S]
fMAX5 Maximum Frequency Pipelined Mode[12, 17] 35.0 30.0 22.0 28.0 23.5 18.5 MHz
4-94
~ CY7C331
~~~NDUcrOR
Notes:
=====================================================================
7. Refer to Figure 5 configuration 1. 17. This specification is intended to guarantee that a state machine con-
8. Refer to Figure 5 configuration 2. figuration created with internal or external feedback can be operated
9. Refer to Figure 5 configuration 3. with output register and input register clocks controlled by the same
source. These parameters are tested by periodic sampling of produc-
10. Refer to Figure 5 configuration 4. tion product.
11. Refer to Figure 5 configuration 5. 18. This specification is intended to guarantee interface compatibility of
12. Refer to Figure 5 configuration 6. the other members of the CY7C330 family with the CY7C331. This
13. Refer to Figure 6 configuration 7. specification is met for the devices noted operating at the same ambi-
14. Refer to Figure 6 configuration 8. ent temperature and at the same power supply voltage. These param-
eters are tested periodically by sampling of production product.
15. Refer to Figure 7 configuration 9.
19. Preliminary specifications.
16. Refer to Figure 7 configuration to.

OUTP~~ ft ft
50 pf
INCLUDING I
R1 313.(1
(470.(1 MIL)
R2
208.(1
OUTP~~
(319.(1 MIL)
5 pf
I
R1 313.(1
(470.(1 MIL)
.
R2
208.(1
(319.(1 MIL)
3.0V----~~~--~"'---
GND---""""
INPUT PULSES
JIGAND - - - - ~ 5ns
SCOPE 0100-6
0100-5
Figure 4
Figure 3a Figure 3b
125.n 190.n
OUTPUT~2.00V =Vthc OUTPUT~ 2.02V =Vthm
0100-7 0100-8
Parameters Vx Output Waveform-Measurement Level

tpxz(-) 1.5 V
a.}v ~
VOH
Vx 0100-16
tpxz(+) 2.6V
r
Vx
VOL 0~5V 0100-17
tpzx(+) Vthc
0~5V rr-
VOH
Vx
0100-18
tpzx(-) Vthc
atv ~
Vx
VOL 0100-19
tER( -) l.5V
otv ~
VOH
Vx 0100-16
tER( +) 2.6V
r
Vx
VOL Of V
0100-17
tEA(+ ) Vthc
rr-
VOH
Vx Of V
0100-18
tEA(-) Vthc
a.}v ~
Vx
VOL 0100-19
Figure 3c. Test Waveforms and Measurement Levels
4-95
~ CY7C331
~~~~================================================================
Switching Waveforms
INPUT OR
I/O PIN
I/O INPUT
REGISTER
CLOCK [20]
OUTPUT
REGISTER
CLOCK [20]
OUTPUT
~--------tco--------~
1+--------- tpD [23] -----------+l
SET AND
RESET
INPUTS [20] 0100-9
OE PRODUCT ~k-1\ l-I----

TERM INPUT[10,20]
t __
*
EA
PIN 14 AS OE[ll1
- ~ tpxz i-- -
)[
tpzx i--
II ~
OUTPUT
\\
II ,\ -l- ~
-tOAR-
OUTPUT I-tER -
REGISTER j ~~
RESET INPUT[9,20] ~tORW- I---
tORR -
OUTPUT
REGISTER j
CLOCK [9,20]
I-- tOAS- I-tOSR'"
OUTPUT
l~
REGISTER
SET INPUT[9,20]
l- I--tosw- I--
~
I-- tlAR -
I/O INPUT
~~
REGISTER
RESET INPUT [S,20]
l
I--tIRW-
tlRR -
I/o INPUT
REGISTER
CLOCK [S,20)
l-
tlAS tlS R ..
I/O INPUT
REGISTER
SET INPUT [S,20)
0100-10
Notes:
20. Because these input signals are controlled by product terms, active 24. When entering the Combinatorial Mode, input and output register
input polarity may be of either polarity. Internal active input polarity Set and Reset inputs must be stable in a HIGH state a MINIMUM
has been shown for clarity. of tISR/tIRR and tOSR/toRR respectively prior to application of logic
21. Output register is set in Transparent Mode. Output register Set and input signals.
Reset inputs are in a HIGH state. 25. When returning to the input and/or output Registered Mode, regis-
22. Dedicated input or input register set in Transparent Mode. Input ter Set and Reset inputs must be stable in a LOW state a
register Set and Reset inputs are in a HIGH state. MINIMUM of tISR/tIRR and tOSR/toRR respectively prior to the
23. Combinatorial Mode. Reset and Set inputs of the input and output application of the register clock input.
registers should remain in a HIGH state at least until the output
responds at tpD. When returning Set and Reset inputs to a LOW
state, one of these signals should go LOW a MINIMUM oftoSR (Set
input) or toRR (Reset input) prior to the other. This guarantees
predictable register states upon exit from Combinatorial Mode.
4-96
5r~ CY7C331
B ~PR~E~~CTI
~
CONFIGURATION 1
ARRAY
INPUT OR I/O PIN 6E I/o PIN
0100-11
CLOCK/SIR
PIN
INPUT PRODUCT
UNREGISTERED TERM
CONFIGURATION 2 INPUT OR I/o PIN ARRAY
III
0100-12
PIN
PRODUCT
UNREGISTERED TERM
CONFIGURATION 3 INPUT OR I/O PIN ARRAY
CLOCK/SIR
PIN
INPUT
UNREGISTERED
INPUT OR I/o PIN
0100-13
PIN
PRODUCT
CONFIGURATION 4 INPUT OR I/O PIN TERM
ARRAY
PIN
INPUT OR I/O PIN I/o PIN
0100-14
14
CONFIGURATION 5 INPUT OR I/O PIN
PRODUCT
PIN TERM
ARRAY
INPUT OR I/O PIN
0100-15
INPUT OUTPUT
REGISTER REGISTER
CONFIGURATION 6 PRODUCT
CLOCK CLOCK
UNREGISTERED TERM
INPUT OR I/o PIN ARRAY
0100-20
Figure 5. Timing Configurations
4-97
~ CY7C331
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INPUT REGISTER
PRODUCT
TERM
ARRAY
CONFIGURATION 7
0100-21
OUTPUT REGISTER
CONFIGURATION 8
0100-22
CONFIGURATION 9
0100-23
Figure 6
PRODUCT
CONFIGURATION 10 TERM
ARRAY
CLOCK
0100-26
Figure 7
4-98
~ CY7C331
~~~DUcrOR =====================================================================
--
8 16 24 32 40 48 56
1 ...
LO
11190 4 (CO l)
-{ill
4-r:rrr=r=
2 ...- ..... node 34

..... L11906 ( C2)

L806
111907 (CO l)
Hm
12
Jrt= L...- ... ~
3
L1984
""
...'-
L11909 (CO . l)
Hill
6-o-fFrL..~
..... node 33
4
L11911 ( C2)
....
L2852
~ ...
L11912 (CO l)
--{ill
10 -olT~ '--'-I""'
....
5 ..
L3968
~L..
L11914 (CO . l)
Hm
6 .
'~~~M'32 L11916 ( C2)
.....
L ~L..
L4960
L11917 (CO l)
HE
8 =-'-~
....
7
TO LOWER SECTION
0100-24
CY7C331 Logic Diagram (Upper HalO
4-99
TO UPPER SECTION
I
L5952
~(CO 1)
8-o-m=~"'~oeIe
Itt~~mf::l:~l#I=t:tm!==::;~~j
31
L11921 (C2)
~
.. r- ....
L6944
~4(CO 1)
110~"~
noele 30
L11926 (C2)
~
9052 _ _....... ~(CO 1)
6-oIFt::
m1.
....... L9920
_.,r-Io. noele 29
L11931 (C2
~
11160 ~(CO 1)
4-o-rr~
I..il
L:..=I .. r ..
~----------------~~~----~
0100-25
CY7C331 Logic Diagram (Lower Half)
4-100
~ CY7C331
~~~UaoR==================================================================
ICCl tpD ts teo Ordering Code
Package Operating
(rnA) (ns) (ns) (ns) Type Range
120 20 12 20 CY7C331-20PC P21 Commercial
CY7C331-20WC W22
CY7C331-20JC J64
150 25 15 25 CY7C331-25DMB D22 Military
CY7C331-25WMB W22

CY7C331-25LMB L64
CY7C331-25TMB T74
CY7C331-25QMB Q64
CY7C331-25WC W22
CY7C331-25JC J64
CY7C331-30WMB W22
CY7C331-30LMB L64
CY7C331-30TMB T74
CY7C331-30QMB Q64
CY7C331-35WC W22
CY7C331-35JC J64
CY7C331-4OWMB W22
CY7C331-40LMB L64
CY7C331-4OTMB T74
CY7C331-40QMB Q64
4-101
~ CY7C331
~~~~U~R==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VIL 1,2,3
IIX 1,2,3
IOZ 1,2,3
Icc} 1,2,3
tIS 9,10,11
tlH 9,10,11
tWH 9,10,11
tWL 9,10,11
teo 9,10,11
tpD 9,10,11
tIAR 9,10,11
tIAS 9,10,11
tpxz 9,10,11
tpzx 9,10,11
tER 9,10,11
tEA 9,10,11
ts 9,10,11
tH 9,10,11
4-102
CY7C332
CYPRESS
SEMICONDUCTOR Registered Combinatorial
EPLD
12 I/O macrocells each having: 13 input macrocells, each having: The CY7C332 is a versatile combinato-
- Registered, latched, or - Complementary input rial PLD with I/O registers onboard.
transparent array input - Register, latch, or transparent There are 25 array inputs; each has a
- A choice of two clock sources access macrocell which may be configured as
- Global or local output enable
(OE)
- Two clock sources a register, latch or simple buffer. Out-
puts have polarity and tristate control
4
20 ns max. delay
- Up to 19 product terms (PT) product terms. The allocation of prod-
per output Low power uct terms to I/O macrocells is varied so
- Product term (PT) output - 120 mA typical Icc quiescent that functions of up to 19 product
polarity control -180 mA max. terms can be accommodated.
- Power saving "Miser Bit"
192 product terms with variable
distribution to macrocells
feature I/O Resources
- An average of 14 PT's per Security fuse Pins 1 through 7 and 9 through 14
macrocell sum node 28 pin slim-line package; also function as dedicated array inputs. Pins
- Up to 19 PT's maximum for available in 28 pin PLC 1 and 2 function as input clocks as well
select nodes as normal inputs. Pin 14 functions as a
UV-Eraseable and global output enable as well as a nor-
2 clock inputs with configureable reprogrammable mal input.
polarity control
Programming and operation
100% testable
Block Diagram and Pinout

LCC and PLCC Pinout
O-N -OChao
.:':.:oo~~
I~ 'S--:::,.--
0134-2
0134-1
Selection Guide
Generic ICClmA iIco/tpDns tIS ns
Part Number Com Mil Com Mil Com Mil
7C332-20 120 20 3
7C332-25 120 150 25 25 3 4
7C332-30 150 30 4
4-103
~ CY7C332
~~~~~==================================================================
If C3 is 1 (programmed), the clock will be falling edge
I/O Resources (Continued)
triggered (register mode) or low asserted (latch mode).
PIN1D~--~""D-CKl I/O Macrocell
PIN1.S0
There are 12 I/O macrocells corresponding to pins 15
through 20 and 23 through 28. Each macrocell has a tri-
PIN2D~--~""D-CK2 state output control, an XOR product term to dynamically
control polarity, and a configureable feedback path.
PIN2.S0 For each I/O macrocell, the tristate control for the output
0134-3
may be configured two ways. If the configuration bit, C4, is
Figure 1. CKI and CK2
a 1 (programmed), then the global OE signal is selected.
Pins 15 through 20 and 23 through 28 are connected to Otherwise, the OE product term is used.
I/O macrocells and may be combinatorial outputs as well For each I/O macrocell, the input/feedback path may be
as registered or direct inputs. configured as a register, latch, or shunt. There are two
Input Macrocell configuration bits per I/O macrocell which configure the
feedback path. These are programmed in the same way as
for the input macrocells.
INPUT REGISTER For each I/O macrocell, the input register clock (or Latch
IN~~TH _ _ _ _ _ _ _ _ _-I Enable) which is used for the input/feedback path may be
selected as pin 1 (select bit, C2, not programmed) or pin 2
PIN 1.CKl (select bit, C2, programmed).
PIN 2.CK2 Array Allocation to Output Macrocell
The number of product terms in each output macrocell
C2
sum is position dependent. The table below summarizes the
allocation:
Table 1
0134-4 Macrocell Pin Number Product Terms
Figure 2. Input Macrocell
0 28 9
1 27 19
C3 C2 Cl CO Input Register Option
2 26 11
X X 0 0 Combinatorial 3 25 17
X X 0 1 Illegal 4 24 13
0 0 1 1 Registered, CLK 1, Rising Edge 5 23 15
0 1 1 1 Registered, CLK2, Rising Edge 6 20 15
1 0 1 1 Registered, CLK 1, Fallling Edge 7 19 13
1 1 1 1 Registered, CLK2, Falling Edge 8 18 17
0 0 1 0 Latched, CLKl, High Asserted 9 17 11
0 1 1 0 Latched, CLK2, High Asserted 10 16 19
1 0 1 0 Latched, CLK 1, Low Asserted 11 15 9
1 1 1 0 Latched, CLKl, Low Asserted
There are 13 input macrocells, corresponding to pins 1
through 7 and 9 through 14. Each macrocell has a clock
which is selected to come from either pin 1 or pin 2 by PIN 14 INVERTED, OE
configuration bit C2. Pins 1 and 2 are clocks as well as

normal inputs. There is no C2 configuration bit for either
C4
of these two input macrocells. Macrocells connected to
pins 1 and 2 do not have a clock choice, but each has a
clock coming from the other pin.
Each input macrocell can be configured as a register, latch
or a simple buffer (transparent path) to the product term
array. For a register the configuration bit, CO, is 1 (pro-
grammed) and Cl is 1. For a Latch, CO is 0 and Cl is 1. If
both CO and Cl are 0 (unprogrammed) then the macrocell
is completely transparent.
Configuration bit C3 determines the clock edge on which
the register is triggered or the polarity for which the latch
is asserted. This clock polarity can be programmed inde-
pendently for each input register. These configuration op-
tions are available on all inputs, including those in the I/O
macrocell.
If C3 is 0 (unprogrammed), the clock will be rising edge
triggered (register mode) or high asserted (latch mode). Figure 3. I/O Macrocell
4-104
~ CY7C332
~~~abU~~~~~~~~~~~~~~~~~====~============================
Maximum Ratings
Storage Temperature .... , .......... -65C to + 150C Latch-up Current .......................... > 200 mA
Ambient Temperature with DC Programming Voltage ...................... 13.0V
Operating Range
(Pin 22 to Pins 8 and 21) .............. -0.5V to + 7.OV Ambient
Range Vee
DC Input Voltage ................... - 3.0V to + 7.OV Temperature
Output Current into Outputs (Low) ............. 12 mA Commercial O"C to +7SoC SV 10%
Static Discharge Voltage ..................... >2001V Military [5] - SsoC to + 12SoC SV 10%
(per MIL-STD-883, Method 3015)
Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Units
Vee = Min., IOH = -3.2mA Commercial
Vee = Min., IOL = 12 rnA Commercial
VOL Output LOW Voltage O.S V
VIN = VIH or VIL IOL = SmA Military
VIH Input LOW Level Guaranteed HIGH Input, all Inputs[ll 2.2 V
VIL Input LOW Level Guaranteed LOW Input, all Inputs[ll O.S V
IIX Input Leakage Current Vss < VIN < Vee, Vee = Max. -10 10 p.A
Ioz Output Leakage Current Vee = Max., Vss < VOUT < Vee -40 40 p.A
Standby Power Supply Vee = Max., VIN = GND Commercial 120 mA
Ieel
Current Outputs Open Military ISO mA
Vee = Max.
Commercial ISO mA
Power Supply Current Outputs Disabled (In High Z State)
Iee2 at Frequency[6,8] Device Operating at fMAX
External (fMAXI) Military 200 mA
Capacitance [3]
pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz S
Notes:
I. These are absolute values with respect to device ground and all over- 3. Tested initially and after any design or process changes tha may affect
shoots due to system or tester noise are included. these parameters.
2. Not more than one output should be tested at a time. Duration of the 4. Figure 4a test load used for all parameters except tEA, tER, tpzx and
short circuit should not be more than one second. VOUT = O.5V has tpxz. Figure 4b test load for tEA, tER, tpzx, tpxz. Figure 4c shows
been chosen to avoid test problems caused by tester ground degrada- test waveforms and measurement reference levels.
tion.
6. Tested by periodic sampling of production product.
4-105
~ CY7C332
~~~WU~R==================================================================
Commercial Military
tpD Input to Output Propagation Delay[7] 20 25 25 30 ns
tIeO Input Register Clock to Output Delay[S] 20 25 25 30 ns
tIS 3 3 4 4 ns
to Input Register Clock[S]
tIH Input Register Hold Time[S] 3 3 4 4 ns
tEA Input to Output Enable Delay[4, 9] 20 25 25 30 ns
tER Input to Output Disable Delay[4, 9] 20 25 25 30 ns
tpzx Pin 14 Enable to Output Enable Delay[4, 10] 15 20 20 25 ns
tpxz Pin 14 Disable to Output Disable Delay [4, 10] 15 20 20 25 ns
tWH Input Clock Width High[6, s] 10 10 10 12 ns
tWL Input Clock Width Low[6, s] 10 10 10 12 ns
Output Data Stable Time from
tIOH 3 3 4 4 ns
Input Register Clock Input[S, 14]
Output Data Stable Time This Device
tIOH-tIH 0 0 0 0 ns
Minus lIP Reg Hold Time Same Device [11, 12, 14]
Output Data Stable Time Minus lIP Reg
tOH-tIH 33X 0 0 0 0 ns
Hold Time 7C330 & 7C332 Device[13, 14]
tpE External Clock Period (tIeO + tIS)[S] 23 28 29 34 ns
Maximum External Operating
fMAXl 43.4 35.7 34.4 29.4 MHz
Frequency (l/(tICO + tIS[S]
fMAX2 Maximum Frequency Data Path[S] 50.0 40.0 40.0 33.3 MHz
Notes:
7. Refer to Figure 8 configuration 1. 12. This specification is intended to guarantee that configuration 5 of
S. Refer to Figure 8 configuration 2. Figure 8 with input registered feedback can be operated with all
9. Refer to Figure 8 configuration 3. input register clocks controlled by the same source. These parame-
ters are tested by periodic sampling of production product.
10. Refer to Figure 8 configuration 4.
13. This specification is intended to guarantee interface compatibility of
11. Refer to Figure 8 configuration 5. the other members ofthe CY7C330 family with the CY7C332. This
specification is met for the devices noted operating at the same ambi-
ent temperature and at the same power supply voltage. These param-
eters are tested periodically by sampling of production product.
14. Preliminary specifications.
Switching Waveforms
INPUT
OR 1/0[15]
3 ... j'f- -l
~
t ls[8] t lH [8] J
INPUT ..,'f-
CLOCK[161 ~ . f-
PIN 14
I - - tEA[ 9 ] -
-tWH I tw~
AS OE
- ~tpxz[101 ~
l t pzx[10] --l
OUTPUT
- t lOH [81
*XXXXXX)(jt- --
I - tER[ 9 ] -
. t lco[8]
t po[7]
0134-10
Notes:
15. Because OE can be controlled by the OE product term, input signal 16. Since the input register clock polarity is programmable, the input
polarity for control ofOE can be of either polarity. Internally the clock may be rising or falling edge triggered.
product term OE signal is active high.
4-106
~ CY7C332
~~~U~================================================================
OUTP~; ft ft
50 pF'
I
R1 313.0.
(470.0. MIL)
R2
208.0.
OUTP~;
(319.0. MIL)
5 pF'
I
R1 313.0.
(470.0. MIL)
R2
208.0.
(319.0. MIL)
GND--...;;Jr
INPUT PULSES
3.0V-----~----""'"
,. 5 nS
INCLUDING
JIGAND
SCOPE
- - -=-= Figure 5. Input Pulses
0134-7
0134-6
Figure4a Figure4b
125.0. 190.0.
OUTPUT~2.00V = VTHC OUTPUT~2.02V = VTHhA
0134-8 0134-9

tpxz(-) 1.5V
tpxz(+) 2.6V
VOH
+~ Vx 0134-12
tpzx(+) Vthc
VOL
+ r- r
Vx
0134-13
+~
VOH
Vx
0134-14
tpzx(-) Vthc
tER(-) 1.5V
Vx
+~ VOL
0134-15
tER(+) 2.6V
VOH
+~ Vx 0134-12
tEA(+) Vthc
VOL
+1: Vx
0134-13
+rt
VOH
Vx
0134-14
tEA(-) Vthc
Vx
+~
Figure 4c. Test Waveforms and Measurement Levels
VOL
0134-15
4-107
J~ :1111111'1111' 'Ii
L9600
(CO.1.3)LO
i
3 L9710(."0 '0) L90S0
lit" 1bf (CO.. 4)
&~K ~
(CO.1.3) I I
'9 ~~
,
r..,. ...
-Q-
L9606 L1600 L9742 (MB32.. 44) L9660
(CO.. 3) (CO 4)
11 6
~
L9755 (MB45 .. 63)
.. 3) " ~250
(COL9610 " Ir L9665
(CO . 4)
117 IL~-----"'------'}-ml
m--t 'l-I"'r.so=~t:::::t:t#I:Iti
(CO.. 3)
L9614 ~OO~lllllllllllIiIIIIIIIIILIQ'7:7"4~~,m:"''''J4''
.13 78) ..
11
~
lb::::(
L9670
(Co .. 4)
m---1l-1?~_~=t:Fmtt~1
(COL9618
.. 3) L3950 I :1111 L9789~MB79 .. 95)
L9675
(CO 4)
1111111111111111
0134-16
CY7C332 Logic Diagram (Upper HalO
4-108
L9630 L6400
(CO . 3)
L9638 L8000
(CO .. 3)
0134-17
CY7C332 Logic Diagram (Lower Halt)
4-109
~CfPRPSS CY7C332
~~~OO~U~R================================================================
~_...... PRODUCT
CONFIGURATION 1 PIN 1------....I..... TERM
ARRAY
INPUT OR I/O PIN
INPUT REGISTER
......_---1 PRODUCT
TERM
ARRAY
CLOCK 1 OR 2
PIN 1------.. . V10--...... PRODUCT

ARRAY
PIN 1 - - - - - - - 1
V"10----I
INPUT OR I/O PIN I/O PIN
~~~--------------------------------
CONFIGURATION 4
PIN 1------....I........~_--I PRODUCT
TERM
ARRAY
INPUT OR I/O PIN I/O PIN
0134-11
INPUT REGISTER
DATA
INPUT
PRODUCT
CLOCK 1 OR 2
ARRAY
CLOCK 1 OR 2
0134-18
Figure 6. Timing Configurations
4-110
~ CY7C332
~~~~u~================================================================
Package Operating
ICCl (max) tICO/tpD (ns) tIS (ns) tlH (ns) Ordering Code
Type Range
CY7C332-20WC W22
CY7C332-20JC J64
CY7C332-25WMB W22

CY7C332-25LMB L64
CY7C332-25TMB T74
CY7C332-25QMB Q64
CY7C332-25WC W22
CY7C332-25JC J64
CY7C332-30WMB W22
CY7C332-30LMB L64
CY7C332-30TMB T74
CY7C332-30QMB Q64
4-111
CY7C340
ADVANCED INFORMATION EPLDFamily
CYPRESS
SEMICONDUCTOR Multiple Array MatriX
High Density EPLDs
Features General Description
Erasable, user-configurable The Cypress Multiple Array MatriX routes all signals within devices con-
CMOS EPLDs capable of (MAXTM) family of EPLDs provides a taining more than one LAB. This ar-
implementing high density user-configurable, high-density solu- chitecture is fabricated on the Cypress
custom logic functions tion to general purpose logic integra- advanced 0.8 micron double layer met-
tion requirements. With the combina- al CMOS EPROM process, yielding
Advanced 0.8 micron double-
metal CMOS EPROM tion of innovative architecture and devices with 3 times the integration
technology state of the art process, the MAX density at twice the system clock speed
EPLDs offer LSI density, without sac- of the largest current generation
Multiple Array MatriX rificing speed. EPLD.
Architecture optimized for speed,
density and straightforward The MAX architecture makes it ideal The density and flexibility of the
design implementation for replacing large amounts of TTL SSI CY7C340 family is accessed using the
- Typical clock frequency = and MSI logic. For example, a 74161 MAX + PLUS development system. A
SO MHz counter utilizes only 3% of the 128 PC based design system,
- Programmable Interconnect Macrocells available in the CY7C342. MAX + PLUS is optimized specifically
Array (PIA) simplifies Similarly, a 741518 to 1 multiplexer for the CY7C340 family architecture,
routing consumes less than one percent of the providing efficient design processing
- Flexible Macrocells increase over 1,000 product terms in the within the time it takes to erase an
utilization CY7C342. This allows the designer to EPLD. A hierarchical schematic entry
- Programmable clock control replace 50 or more TTL packages with mechanism is used to capture the de-
- Expander product terms just one MAX EPLD. The family sign. State Machine, Truth Table and
implement complex logic comes in a range of densities, shown Boolean Equation entry mechanisms
functions below. By standardizing on a few are also supported, and may be mixed
MAX building blocks, the designer can with schematic capture. The powerful
MAX + PLUSTM development replace hundreds of different 7400 se- Design Processor performs minimiza-
system eases design ries part numbers currently used in tion and logic synthesis, then automati-
- Runs on IBM PCIATTM and most digital systems. cally fits the design into the desired
compatible machines EPLD. Design verification is done us-
- Hierarchical schematic The family is based on an architecture
of flexible Macrocells grouped together ing a timing simulator, which provides
capture with 7400 series TTL
into Logic Array Blocks (LABs). With- full A.c. simulation, along with an in-
and custom Macrofunctions teractive graphic waveform editor
- State machine and Boolean in the LAB is a group of additional
product terms called Expander Prod- package to speed waveform creation
entry and debugging. During design process-
- Graphical delay path uct Terms. These Expanders are used
and shared by the Macrocells, allowing ing a sophisticated automatic error lo-
calculator cator shows exactly where the error oc-
- Automatic error location complex functions, up to 35 product
terms, to be easily implemented in a curred by popping the designer back
- Timing simulation into the schematic at the exact error
- Graphical interactive entry of single Macrocell. A Programmable In-
terconnect Array (PIA) globally location.
waveforms
MAX Family Members
Feature CY7C344 CY7C343 CY7C345 CY7C342
Macrocells 32 64 128 128
MAX Flip-Flops 32 64 128 128
MAX Latches[1] 64 128 256 256
MAX Inputs[2] 23 35 35 59
MAX Outputs 16 28 28 52
280 44J 44J 68J
Packages
28J 400 400 68G
Key: D- DIP J- J-Lead Chip Carrier G- Pin Grid Array
Notes:
1. When all Expander Product Terms are used to implement latches. 2. With one output.
PAL@ is a registered trademark of Monolithic Memories Inc.

IBM@ is a registered trademark of International Business Machines Corporation.
IBM PCIATTM is a trademark of International Business Machines Corporation.
MAXTM and MAX + PLUSTM are trademarks of Altera Corporation.
Drawings courtesy of Altera Corporation.
4-112
CY7C340
(;A CYPRESS ADVANCED INFORMATIONEPLD Family
S~OO~UaDR==============================================================
DEDICATED
INPUTS
/\
!l ~~~~ u
- tp>-D

I-
I- -
'~
~MULTIPLE
LO
AR ~!~~
v- V
V - H>
- r<l
/v ARRAYS
(LABS)
M
~
BL OCK
(LAB)
<}- ~
DUAL
I/O
-[>- ~ rE EDBACK
VV ~
/
EXPANDER
PRO DUCT
TE RMS
~ -.
\
~\
~ ~
\\
~
MACROCELLS PROGRAMMABLE
INTERCONNECT
ARRAY (PIA)
0138-2
Figure 1. Key MAX Features
4-113
CY7C340
~ ADVANCED INFORMATION EPLD Family
~~~~UcrOR========================================~~==~======~========
The Logic Array Block provided within an LAB, giving each functional block
complete access to the LAB resources. The LAB itself is
The Logic Array Block, shown in Figure 2, is the heart of fed by the Programmable Interconnect Array and dedic~t
the MAX architecture. It consists of a Macrocell Array, ed input bus. The feedbacks of the Macrocells and I/O pInS
Expander Product Term Array, and an I/O Block. The feed the PIA, providing access to them by other LABs In
number of Macrocells, Expanders, and I/O vary, depend- the device. The CY7C340 family EPLDs having a single
ing upon the device used. Global feedback of all signals is LAB use a global bus, and a PIA is not needed.
~-------------------------vo-~
I PINS
~~==~ ~
C
~

I
N
P P
U I
T A
S
PROGRAMMABLE
INTERCONNECT
ARRAY
0138-3
Figure 2. LAB Block Diagram
4-114
CY7C340
WnSEMICONDUCTOR ===================================~==~~~~~l~
CYPRESS

ADVANCED INFORMATION EPLD FamOly
The MAX Macrocell If more product terms are required to implement a given
Traditionally, PLDs have been divided into either PLA function, they may be added to the Macrocell from the
(programmable AND, programmable OR), or PALTM Expander Product Term Array. These additional product
(programmable AND, fixed OR) architectures. PLDs of terms may be added to any Macrocell, allowing the design-
the latter type provide faster input-to-output delays, but er to build gate intensive logic, such as address decoders,
can be inefficient due to fixed allocation of product terms. ad?ers, comparators, and complex state machines, without
Statistical analysis of PLD logic designs has shown that usmg extra Macrocells.
70% of all logic functions (per Macrocell) require 3 prod- The register within the Macrocell may be programmed for
uct terms or less. either, D, T, JK, or SR operation. It may alternately be
The Macrocell structure of MAX has been optimized to
handle variable product term requirements. As shown in
Figure 3, each Macrocell consists of a product term array
configured as a flow-through latch for minimum input to
output delays, or by-passed entirely for purely combinato-
ria110gic. In addition, each register supports both asyn-
II

and a configurab1e register. In the Macrocell, combinatori- chronous preset and clear, allowing asynchronous loading
a110gic is implemented with 3 product terms OR'ed to- of counters or shift registers, as found in many standard
gether, which then feeds an XOR gate. The second input to TTL functions. These registers may be clocked with a syn-
!he XOR gate is also controlled by a product term, provid- chr.onous system clock, or clocked independently from the
mg the ability to control active high or active low logic. logiC array.
The MAX + PLUS software will also use this gate to im-
p1em~nt complex mutually exclusive-OR arithmetic logic
functions, or to do DeMorgan's Inversion, reducing the
number of product terms required to implement a function.
PROGRAMMABLE FLIP
OUTPUT FLOP (D, T, JK, SR)
ENABLE
.. SYSTEM
CLOCK
REGISTERED OR FLOW
THROUGH LATCH
OPERATION
PRESET PROGRAMMABLE CLOCK
I ASYNC CLEAR AND
PRESET
I
I
P TO I/O
r--- CONTROL
I 01-- I-e BLOCK
I
r--
~f-4 ..- I-e

I
I r- 11 C
ARRAY
I
I
CLOCK I
I
CLEAR
I
I
MACROCELL
-A FEEDBACK
~.~
~
I) 4)
I~ C~ C~ 4~
~ ~ I. ~ ~ ~ J. ~
NOTE: One system clock
PROGRAMMABLE 32 EXPANDER 16
, per LAB
8
DEDICATED INTERRCONNECT PRODUCT MACROCELL
INPUTS SIGNALS TERMS FEEDBACKS
0138-4
Figure 3. Macrocell Block Diagram
4-115
CY7C340
5A~oo~u~R==========================================~~~~~l~Y
. CYPRFSS

ADVANCED INFORMATION EPLD Famo.
Expander Product Terms ~y de~oupling the I/O pin.s from the flip-flops, all the reg-
The Expander ~roduct Terms, as shown in Figure 4, are Isters m the LAB are "buned", allowing the I/O pins to be
fed by the Dedicated Input Bus, the Programmable Inter- used as dedicated outputs, Bi-directional outputs or as ad-
connect Array, the Macrocell Feedback, Expanders them- ditional d~dica~ed inputs. Therefore, applications requiring
selves, and the I/O pin feedbacks. The outputs of the Ex- many buned fhp-flops, such as counters, shift registers and
panders then go to each and every product term in the state machines, no longer consume both the Macrocell'reg-
Macrocell Array. This allows Expanders to be "shared" by ister and the associated I/O pin, as in earlier devices.
the product terms in the Logic Array Block. One Expander
may feed all Macrocells in the LAB, or even multiple prod- I/o OUTPUT
ENABLE
uct terms in the same Macrocell. Since these Expanders
feed the secondary product terms (Preset, Clear, Clock,
~nd Output Enable) of each Macrocell, complex logic func-
tions may be implemented without utilizing another Mac- FROM
MACRO CELL
roce11. Likewise, Expanders may feed and be shared by IN LAB
other Expanders, to implement complex multi-level logic
and input latches.
TRI-STATE
MACROCELL BUFFER
P-TERMS
TO LAB AND PIA

0138-6
Figure 5. I/O Control
The Programmable Interconnect Array
A major problem which has limited PLD density and
speed has been signal routing, i.e. getting signals from one
Macrocell to another. For smaller devices, a single array is
used and all signals are available to all Macrocells. But, as
the devices increase in density, the number of signals being
routed becomes very large, increasing the amount of silicon
used for interconnections. Also, because the signal must be
global, the added loading on the internal connection path
reduces the overall speed performance of the device. The
MAX architecture solves these problems. It is based on the
concept o~ small, ~exible Logic Array Blocks, which, in the
larger deVices, are mterconnected by a Programmable In-
terconnect Array, or PIA.
The Programmable Interconnect Array solves interconnect
limitations by routing only the signals needed by each
0138-5
LAB. :r~e ar.ch~tecture is designed so that every signal on
t~e chip IS wlthm the PIA. The PIA is then programmed to
Figure 4 give each LAB access to the signals that it requires. Conse-
The I/O Block quently, each LAB receives only the signals needed. This
effectively solves any routing problems that may arise in a
Separate from the Macrocell Array is the I/O Control design, without degrading the performance of the device.
Block of the LAB. Figure 5 shows the I/O block diagram. Un~ike masked or programmable gate arrays, which induce
The tristate buffer is controlled by a Macrocell product vanable delays dependent on routing, the PIA has a fixed
term, and drives the I/O pad. The input of this buffer from point to point. This eliminates undesired skews
comes from a Macrocell within the associated LAB. The among logic signals, which may cause glitches in internal
feedback path from the I/O pin may feed other blocks or external logic.
within the LAB, as well as PIA. .
4-116
CY7C340
5il . CYPRESS ADVANCED INFORMATION EPLD Family
s~OO~UcrOR==================================================================
Family Members The 128 Macrocells in the CY7C342 are divided into 8
The CY7C340 family is an entire set of modular building Logic Array Blocks, 16 per LAB. There are 256 Expander
blocks, optimized for high speed and high density. Listed Product Terms, 32 per LAB, to be used and shared by the
below are the 4 current members of the family. Macrocells within each LAB. Each LAB is interconnected
with a Programmable Interconnect Array, allowing all sig-
CY7C342 nals to be routed throughout the chip.
128 Macrocells in 8 LABs The speed and density of the CY7C342 allows it to be used
in a wide range of applications, from replacement of large
8 dedicated inputs, 52 bi-directional I/O pins
amounts of 7400 series TTL logic, to complex controllers
Programmable Interconnect Array
Available in 68-pin JLCC, PLCC and PGA
and multi-function chips. With greater than 25 times the
functionality of 20-pin PLOs, the CY7C342 allows the re-
placement of over 50 TTL devices. By replacing large
II

amounts of logic, the CY7C342 reduces board space, part
count, and increases system reliability.
1
2
(B6 ) INPUT/CLK
(A6 ) INPUT
=
=
r--
~ INPUT
~ INPUT
(A7) 68
(A8) 66
32 (L4) INPUT ::;- ~INPUT (L6) 36
34 (L5 ) INPUT :::. ~INPUT (K6) 35
I
LAB A ~ .7
SYSTEM CLOCK
...: r LABH
4 A5 I-- B8~ 65
------
5 B4 I-- I-- A9 64
i--
:~016~2
6 A4 A -'"
7
8
B3
A3
I--
'Ij -y
--- Bl0 61
------ ---
9 A2 i-- Bll 60
10 B2 I-- Cll 59
11 Bl ...1\ .A- i-- Cl0 58
"'I>nl"<', ~ ----v y- 128
LABB '<i). ~ lCROCEI

7 ! LAB G
121C2
13 Cl
14 02
15 01
17 E2
liE
8=
~Ar:Rr
IAACRC
IAACRC
ulr.M
IAAGRC
A
'Ij
-'"
V
~ROr:F'
IACROCEI
IACROCEI
IACROCEI
oe
99
98
9;
t::::g
~
011157
010 56
Ell 55
F'11 53
~ 1F'10 52
MACROCELLS 22-32 H P l.A- MACROCELLS 102-112

r-v I
['r-
LABC "j; ..!,7 LABF'

A
I
IAACR IACRC Gll~
~
,IS:
lIE
51
18 !F'2
19 F'1 UAr:RI eRe 84 Hll 49
21 Gl IAACR( A ..J\. 83 Hl0 48
22 H2
23 Hl
IAACRI :1'1
'of
IACRC
AACR( ~EI
82
8
t::::g Jl1)
Jl0)
47
46
MACROCELLS 38-48 H I;t- IAACROCELLS 86-96

IV !'r-
LAB 0 ,,~ ~7 LABE
24 J2 I-- Kll~ 45
---
25 Jl I-- IAACR( I-- Kl0 44
i--
~~lO 4~3
-'"
---
26 Kl
27 K2 I--
28 L2 I-- 'f v I-- K9 41
29 K3 I-- i-- L8 40
---
30 L3 I-- I-- K8 39
31 K4 ...1\ .A- ~ L7 38
'f'"nf'''' , ., 57-64 ----v \r- 73-80
3,20,37,54(B5,G2,K7,El0) D - Vee 0- PERTAIN TO 68 PIN PGA PACKAGE

16,33,50,67,(E2,K5,Gl O,B7) D - GNO
0138-7
Figure 6. CY7C342 Block Diagram
Features
Macrocells Total
Inputs I/O Pins LABs Expanders PIA
per LAB Macrocells
8 52 8 16 128 256 Yes
4-117
CY7C340
5n . ADVANCED INFORMATION
~ucr~==================================================================
EPLD Family
CY7C345 must be packed into a very small area, the CY7C345 is

128 Macrocells in 8 LABs ideally suited for applications which require large amounts
of buried logic.
8 dedicated inputs, 28 bi-directional I/O pins
It has the same number of Macrocells and expanders as the
256 Expander Product Terms CY7C345, and a Programmable Interconnect Array to al-
Programmable Interconnect Array low communications between the LABs. Each LAB has an
I/O block, with LABs A, D, E and H having 4 Bi-direc-
Available in 4O-pin CDIP, PDIP, and tional tri-stateable I/O pins, and the rest having 3 I/O
44-pin JLCC or PLCC pins. Like all other EPLDs in the MAX family, these I/O
The CY7C345 packs the same LSI density of the CY7C342 pins support dual feedback. In this way any Macrocells
into a smaller, 4O-pin DIP or 44-pin JLCC package. De- may be buried, with only the output of Macrocells needed
signed for applications in which large amounts oflogic off-chip connected to I/O pins.
8 (9) INPUT=:: - ~INPUT (35) 32

10 (11) INPUT ~ ~ INPUT/CLK (34) 31
11 (12) INPUT ;:; -;; INPUT (33) 30
12 (13) INPUT : : ~INPUT (31) 28
LAB A r11
I SYSTEM CLOCK
- LABH
~
MACROCEI ;ROC 15 i----I:::I 44~ 40
9= MACROCE
MACROCEL A J\.
\,;KOl
;RO(
14
13
c:::g 42 39
41 38
I'r- ---,I
MACROCELLS 4-1 6 tolACROCELLS 116-128

~ ;1-
1-,1 y-
LABB ~> ~~ LABG

g- MACRC ;t.L
MACRC IS
M~\';KOC
IACRO
OC
99 ~ 40!
39 37
36
MA\';I(I 19 A. J\. IA\,;KC 9lS 38 35
~ MACKC IACRe 9~ ~ 1 37 34
'I V
MACROCELLS 21-32 ----1\, P Vt- tolACROCELLS 101-11 2

---,I
I
I'r-
~BC ~j,. {.7 LABF
14 15 n-- MACRC .3 A IACRC S4 i----I:::I
15
16
17
16
17
1
18 ! g::
~
MA\';I(I;
MACRC
MAI:;RI;
i4
.5
i5
A
'I
--"
V
l.:KC
IACRC
IA\';I(O ;EI
8,)
S:
S'
~
-...... 128
27
30! 27
29 26
25
24
MACROCELLS 37-48 ~ ;1- MACRO CELLS 85-96

1-,1 y-
LABD ~> ~7 LABE
18 20
19
20 22
~19~ F
~
MACKl ;t.L
MAGRC
MAI:;RC A. J\.
IACKC
IACRC
IAI:;I(I
5.
56
55
--e ~
~
26~ 23
24 22
23 21
'r- r--v
MACROCELLS 52-64 MACROCELLS 68-S0
----l\ Vt-
--V I'r-
13.33.(3.14.25.36) ~VCC o PERTAIN TO 44-PIN J-LEAD PACKAGE
9.29(10.21.32.43) ~GND
0138-8
Features
Macrocells Total
per LAB Macrocells
8 28 8 16 128 256 Yes
4-118
CY7C340
5Jl~NDUcrOR =====================================================================
.

ADVANCED INFORMATION EPLD Family
CY7C343 in the LABs, each I/O control block has 7 I/O pins.
64 MAX Macrocells in 4 LABs Therefore, if each I/O pin was fed by a Macrocell, there
are still 9 buried Macrocells per LAB that may be used for
8 dedicated inputs, 28 tri-stateable, embedded logic. The signals generated within each LAB
bi-directional I/O pins are routed to every LAB through the Programmable Inter-
Programmable Interconnect Array connect Array.
Available in 40-pin CDIP, PDIP, The CY7C343 is perfect for designs with large I/O require-
and 44-pin JLCC, PLCC ments, along with healthy amounts of buried logic. Excel-
lent for a wide range of applications, the CY7C343 can
The CY7C343 block diagram is shown in Figure 8. It has reduce board space by absorbing large amounts of glue
16 Macrocells and 32 Expander Product Terms in each of
its 4 Logic Array Blocks. Decoupled from the Macrocells
logic. Due to the large number of I/O pins, 16-bit data l1'li
paths are no problem. ~
.--
INP UT/CLK ~ <:J INPUT
INPUT D <:JINPUT
INPUT D ~INPUT
INPUT c:: <:I INPUT
I--
LAB A
..........-t
MACRe :;ELL 1
~ .7
I SYSTEM CLOCK
~LA.O
MACRoe ELL 55 I--
I-- MACROCELL 2 MACROCELL 54 r--
I/O
I--
I--
MACROCELL 3
MACROCELL 4
fl.- ----1\ MACROCELL 53
MACROCELL 52
-- I/O
PINS I-- MACROCELL 5 \f V MACROCELL 51 - PINS
I-- MACROCELL 6 MACROCELL 50 -
I-- MACROCELL 7 MACRO CELL 49 -
I--
MACROCELLS 8-1 6 N P
,A--
\r""- MACROCELLS 56-64
r--
0 I Q !
--- LAB B !
17
MACROCELL 18
MACROCELL 19 A
A
.J\
LAB C
MACROCELL 38
MACROCELL 37
.~~
---
I/O
PINS
~
~
MACROCELL 20
MACROCELL 21 '4 V
MACROCELL 36
MACROCELL 35
-- I/O
PINS
~
~
MACROCELL 22
MACROCELL 23
MACROCELL 34
MACROCELL 33
--
I-- ~ ;t- -
MACROCELLS 24-32 r----v \r- MACROCELLS 40-48
[>-Vcc
[>-GND
0138-9
Features
Macrocells Total
per LAB Macrocells
8 28 4 16 64 128 Yes
4-119
CY7C340
fin~UaoR================================================================
.
ADVANCEDINFORMATION EPLD Family
CY7C344 Macrocells and 64 Expander Product Terms. Figure 9

High performance, high density replacement shows that even if all of the I/O pins are being driven by
for TTL, 74HC, and custom logic Macrocells, there are sti1116 "buried" Macrocells avail-
able. All inputs, Macrocells and I/O pins are interconnect~
32 Macrocells, 64 Expander Product Terms in one LAB ed within the LAB.
8 dedicated inputs, 16 I/O pins The speed and density of the CY7C344 makes it a natural
Small outline 28-pin 300 mil CDIP, PDIP, for all types of applications. With just this one device, the
or 28-pin JLCC, PLCC package designer can implement complex state machines, registered
logic, and combinatorial "glue" logic, without using multi-
Available in a 28-pin 300 mil DIP or JLCC, the CY7C344 ple chips. This architectural flexibility allows the CY7C344
represents the densest EPLD of this size. 8 dedicated in- to replace multi-chip TTL solutions, whether they are syn-
puts and 16 bi-directional I/O pins communicate to one chronous, asynchronous, combinatorial, or all three.
Logic Array Block. In the CY7C344 LAB there are 32
INPUT D~=:""--t 1 - - -....."""""110 INPUT

INPUT D~=~--t
INPUT D~~'----1
INPUT D~~""--t
-+~I---..... ..
I/o
I/o
MACROCELL 6
MACROCELL 8 I/o
MACROCELL 10 I/o
MACROCELL 12
I/o
MACROCELL 14
MACROCELL 16 I/o
MACROCELL 18 I/o
I/o
I/o
I/o
I/o
I/o
I/o
I/o
I/o
I/o
0138-12
Note:
Figures within () pertain to I-leaded packages.
Features
Macrocells Total
per LAB Macrocells
8 16 1 32 32 64 No
4120
CY7C340
5'A . ADVANCED INFORMATION
~UaoR~~~~~~~~~~~~~==~======~====================~~====
MAX + PLUSTM Development System
EPLD Family
General Description may be used in conjunction with the graphic editor, giving
The MAX + PLUS Development System represents a com- added flexibility to the design environment.
plete hardware and software solution for implementing de- In addition to a hierarchical design environment,
signs in the Cypress CY7C340 family of EPLDs. MAX + PLUS has a sophisticated processing engine to ex-
MAX + PLUS is a sophisticated Computer Aided Design ploit the CY7C340 family architecture. MAX + PLUS uses
(CAD) system that includes design entry, design simula- an advanced logic synthesizer and heuristic rules to process
tion, and device programming. Hosted on an IBM PCIAT a design into a file for programming andlor simulation.
or compatible machine. MAX + PLUS gives the designer MAX + PLUS features a powerful event-driven simulator
the tools to quickly and efficiently implement complex log- which displays typical timing results in an interactive
ic designs. A block diagram is shown in Figure 10. waveform editor display. In this waveform editor, input
Designs are entered in MAX + PLUS using a hierarchical vector waveforms may be directly modified and a new sim- ~
graphic editor. This editor has such features as multiple ulation run immediately. ..
windows, multiple zoom levels, unlimited hierarchy levels, Unlike most design environments, MAX + PLUS is uni-
symbol editing, and a library of 7400 series devices in addi- fied, with all sections controlled by the Supervisor and Data
tion to basic SSI gate and register primitives. Also available Base Manager. By unifying the software, MAX + PLUS
is a Timing Calculator, in which the designer may pick two can offer an automatic error locator. Ifa design rule has
places in the schematic, and the software will display typi- been violated,the error processor will list an error message,
cal timing between those two points. Boolean Equation, the probable cause, and pop the designer into the schematic
Netlist, State Machine, and Truth Table entry mechanisms to the exact node where the mistake was made.
DESIGN PROCESSOR
BOOLEAN
EQUATION
ENTRY
STATE
MACHINE
ENTRY
TRUTH
TABLE
ENTRY
0138-11
Figure 10. MAX + PLUS Block Diagram
4-121
CY7C340
fin . ADVANCED INFORMATION

~NDUcrOR==================================================================~
MAX + PLUS Development System (Continued)
EPLD Family
Design Entry resources. The synthesizer will also remove any unused
Design entry is easily accomplished with MAX + PLUS. logic or registers from the design.
MAX + PLUS provides multiple entry mechanisms, in- The next module in the design processor is the fitter. Its
cluding traditional Boolean equation entry. Also available function is similar to a placement and router used in semi-
are State Machine and Truth Table entry, using a high-lev- custom gate arrays. Using heuristic rules, it takes the syn-
el state machine language. Because the CY7C340 family of thesized design and optimally places it within the chosen
EPLDs offer the designer large amounts of logic capability, CY7C340 EPLD. With the larger devices, it also routes the
a Hierarchical Graphic Editor has been provided to ease signals across the Programmable Interconnect Array, free-
the design process. ing the designer from interconnection issues.
Graphic Editor Timing Simulator
The hierarchical design approach used by the graphic edi- Rounding out the software offering is a powerful timing
tor allows the designer to work with either a top-down or a simulator to aid in the verification and debugging of de-
bottom-up approach. The top down method allows the designs. The simulator is a graphical, event driven software
signer to start with a high level block diagram, and then package that yields true, worst case timings based upon
move down and design each block individually. The bot- user-defined input vectors.
tom up method allows the simulation and verification of Waveforms may be viewed using a Graphical Waveform
small building blocks, which may then be pieced together Editor, which allows graphical definitions and editing of
into a final design. input waveforms. The designer can define his input wave-
The Graphic Editor is mouse driven and uses pull down form using the mouse to draw the actual waveform as a
menus or single keystrokes to enter commands. Aiding in function of time. There are also powerful waveform editing
the design task is a library of 7400 series MSI and SSI logic commands, all menu driven, to aid in the development of
gates. The designer may use these and/or create his own the input vectors. Such options as pre-defining, copying
custom symbols. Custom functions are easily created in the and repeating waveforms are all available to the user. If
hierarchy by first designing the function. Then a symbol is graphical definition is not desired, there is a powerful vec-
made, which represents that schematic. In this way a cus- tor description language for developing input vectors.
tom function may be used in multiple places in the current The simulator itself has all the capabilities one would ex-
design, or saved and used in subsequent designs. pect from this type of design environment. Observing bur-
The function of any symbol created may be defined using ied nodes, accessing flip-flop control inputs, and initializing
graphic entry, state machine, Boolean, or truth table de- and forcing nodes to specified values are all available with-
scriptions. This provides a wide range of flexibility for the in the timing simulator. The user may also specify break-
designer, allowing Boolean equations to be combined with points during the simulation itself, and execute subroutines
state machine entry in a hierarchical schematic. dependent upon the breakpoints. All of these tools aid the
The timing calculator within the graphic editor gives the designer in verifying and debugging the design, even before
designer instant feedback concerning timing delays inher- breadboarding.
ent in a path. By placing two probes on different parts of The simulator also has advanced A.C. timing detection.
the schematic, the designer immediately knows the worst The software will warn the user when setup and hold times
case timing of the processed design. This is a valuable addi- to flip flops are being violated, and when there is oscillation
tion for design debugging and documentation. present in the simulation. Also, the user may define a mini-
mum pulse width, in which any pulse within the design
Design Processor that is smaller than a certain size will be classified as a
After the design is entered, a push of the mouse button glitch and the designer will be informed.
invokes the powerful MAX + PLUS processor. First a net-
list is extracted from the comlete hierarchical design. Dur- Supervisor and Error Processor
ing the extraction process, design rules are checked for any All facets of the MAX + PLUS system are overseen by the
errors, and if errors are found, the error processor leads the Supervisor and Data Base Manager. By tying all of the
designer directly to the schematic location where the error software together, the designer has a unified operational
occurred. The extracted design is placed in the database, environment. All the software has the same "look and
and the design is ready to be processed. feel", so that complex commands and languages are not
The versatile MAX architecture, with its Expander Prod- needed.
uct Terms and mutual exclusivity, requires a dedicated Automatic error processing is an added benefit of this ap-
processor to take optimal advantage of the MAX features, proach. If an error occurs during the processing of the
one that does much more than simplify logic. The logic design, the software will automatically tell the user what
synthesizer in MAX + PLUS uses several knowledge-based the error is, and the probable cause.
synthesis rules to factor and map logic onto the multi-level Then, by pressing a single key, the software will automati-
MAX architecture. It will then choose the mapping cally go the schematic in the graphic editor and pinpoint
aproach that ensures the most efficient use of the silicon the location of the error.
4-122
Ultra High Speed State

Machine EPLD
Features
High speed: 125 MHz internal Space saving 28 pin slim-line forms and thus allows for the use of a
processing DIP package; also available in clock with an imperfect duty cycle. The
- Multiple, concurrent 28 pin PLCC CY7C361 has two arrays which serve
processes Low power in function similar to the arrays in a
- Multiway branch or join - 140 mA max at 125 MHz PLA except that the registers are
- Full input field decode
UV -eraseable and
placed between the two arrays and the
long feedback path of the PLA is elimi-
4
32 synchronous macrocells reprogrammable nated.
Skew-controlled, OR output Programming and operation
array In the CY7C361, the state information
100% testable is contained in 32 macrocells sand-
- Outputs are sum of states
like PLA Product Characteristics wiched between the input and output
- 3 ns skew overall arrays. The current state information is
The CY7C361 is a CMOS eraseable, fed back in time to keep up with the
Metastable hardened input programmable logic device (EPLD) 125 MHz operating frequency.
registers with very high speed sequencing and
- 10 year MTBF metastable The output array performs an OR
arbitration capabilities. function over the state macrocell out-
- Configurable as 0, 1 or 2
- Clock enables on all input Applications include: cache and I/O puts. The signals from the output array
registers subsystem control for high speed mi- are connected to 14 outputs; in addi-
croprocessor based systems, control of tion they are connected to 3 groups of
8 to 12 inputs, 10 to 14 outputs, high speed numeric processors, and input macrocells to act as clock en-
1 clock control of asynchronous systems in- ables.
Programmable clock doubler and cluding dataflow organizations.
conditioner Input Macrocells
An onboard clock doubler and condi-
- 'Squares up' input clock tioning circuit allows the device to op- The CY7C361 has 12 input macrocells.
Security fuse erate at 125 MHz based on a 62.5 MHz Each macrocell can be configured to
input reference. The same circuit have 0, 1 or 2 registers in the path of
guards against asymmetric clock wave- the input data. In the configuration
Block Diagram
0165-1
4-123
~ ADVANCED INFORMATION CY7C361
~~~UaoR==================================================================
Product Characteristics (Continued)
where there is no input register, the setup time requirement OUTPUT
is largest. In the single register configuration, the setup
time is less than half. The double register configuration is
0165-4
used for asynchronous inputs.
Figure 2. Condition Decoder
TO The Condition Decoder of the CY7C361 forms a product
INPUT
DATA ARRAY of a product and a sum over the input field. Since there is
CLOCK immediate feedback information in the input field, multi-
ENABLE-.....t==..l._ way fork and join operations can be performed using this
type of condition decoder. State transitions can be made in
0165-3 half the time because there is no "state encoding" delay.
Figure 1. Input Macrocell
State Machine Macrocells
Input Register Enables
LOCAL LOCAL
The input macrocells are divided into 3 groups, each of
D~ ~f;: J~_C"':I"'"IN_~E.,l_:_OC_:'Tr_C_L:TOC_K. . . J~~y

which has a register clock enable signal coming from the
output array. The purpose of the enable signal is to allow
the inputs to be sampled at times controlled by the state of
the device.
There is one enable signal per group of input macrocells.
The assignment of enable signal node numbers to input C_OUT LOCAL GLOBAL CLOCK
RESET RESET
macrocell groups is as follows: 0165-5
Input Nodes Enable Node Figure 3. CY7C361 Macrocell
3,5,6,9 29 The CY7C361 has 32 state Macrocells. The state Macro-
10,11,12,13 30 cells each have a single condition decode and share a com-
1,2, 14, 15 31 mon clock and global reset condition. For each 4 macrocell
group there is a local reset condition.
When the enable node is true, data is clocked into the regis-
ters of the input macrocells on the rising edge of the inter- There are 3 Macrocell configurations, named START,
nal global clock. TERMINATE and TOGGLE. The purpose of the START
configuration is to create a "token" based on a condition
Metastable Immunity decode. The purpose of the TERMINATE configuration is
A high level of metastable immunity is afforded in the dou- to capture a token and maintain it until a particular condi-
ble register configuration. The CY7C361 input registers are tion is decoded, then terminate the token. The TOGGLE
offast CMOS and resolve inputs in a minimal amount of configuration is used to make counters.
time. With all inputs switching at the maximum frequency,
one metastable event capable of violating the setup time
window ofthe second input register occurs every 10 years.
The probability of failure for the configured state machine
is much lower than this calculation suggests, because there
are more registers in the device and thus more decision
time is allowed. No state machine failures due to metasta-
ble phenomena will be observed if the maximum frequency
and double register operating mode are used.
The CY7C361 is thus a superior device for constructing
state machines requiring arbitration.
Cl,CO = 0,1: START 0165-6
Input Array
Figure 4
The input array has 41 condition decoders: one global reset
decoder, 8 local reset decoders, and 32 macrocell decoders. The start configuration is shown in Figure 4.
The array has 44 true/complement inputs or 88 inputs in The start configuration creates a token at the leading edge
total; for speed reasons, the feedback signals are folded. of the condition decode or C_IN. The token is represent-
Folding or partitioning of the feedback part ofthe array ed by a true output on the macrocell register going to the
reduces the number of inputs per decoder to 56. Because of output array and back as feedback to the input array. The
the way the feedback signals are used, this array reduction CY7C361 consists of multiple machines or processes run-
has minimal impact on utility. ning concurrently, each with zero, one or more tokens ac-
tive at a given time. As the output field is independent, the
The CY7C361 condition decoder is shown in Figure 2. In a programmed pattern in the two arrays is one to one trans-
conventional PLA or PAL device, only PRODUCT 1 latable to microcode. The microcode is concurrent in oper-
would be present in the first array and the output and ation.
feedback would be encoded by a second programmable or
fixed OR array. The speed of state machines made from In addition to the main register going to the array, there is
these conventional devices is limited mainly by the feed- an R-S latch in the feedback path. The purpose of the R-S
back path. latch is to convert the input condition to a pulse.
4-124
~~~~u~ ==================================================================
Product Characteristics (Continued) ~NORMAL
~OUTPUT
In operation, the start macrocell starts from a reset condi-
OR TERM
tion (array input = FALSE). When a condition decode
"fires" or a token carries in (C_IN), the register output (Q
OR TERM BIDIR.
going to array) goes true for exactly one cycle. The OR of OUTPUT
the condition decode and the C_IN signal must go
FALSE before the start configuration can "fire" again.
Configuration bit C2 is used in all state macrocells to select
C_OUT to be active (C2 = 1) or inactive (C2 = 0).
MEALY
OUTPUT
FUNCTION
0165-9
Figure 7. Output Types
A normal output signal from the device is a boolean sum of
a subset of the macrocell outputs. The subset selection is
programmed into the output array. The number of state
0165-7 machines in the device, and the output mappings of each
CO,Cl = 1,0: TERMINATE
Figure 5 are determined by the user. The architecture is thus "hori-
zontally divisible" and offers advantages in coding efficien-
Figure 5 shows the terminate configuration which is used cy and event response time over the non-divisible architec-
to maintain state tokens until a condition occurs. tures found in most PLA and sequencer types.
In operation, the terminate configuration "captures" a to- A normal output pin is low asserted. The output gate per-
ken via. C-IN and the OR gate. The condition decode is forms an OR function over the flip-flop outputs of the state
normally false or 0 so the token circulates and the register macrocells. The OR function includes only the outputs
stays set. When the condition decode "fires", the register which are programmably connected to the OR line in the
resets. output array. When none of the connected state macrocell
flip-flops are in the true or set condition, the output is high.
If any connected macrocell flip-flop is asserted (or true)
then the OR gate function is true and the output pin is low.
Forcing a false condition is easily accomplished by not con-
necting any state macrocells to the OR line. To force a true
condition, line 33 (labelled Vcd is included in the output
array. Any OR line connected to line 33 will be permanent-
ly true which will cause a normal output to be low.
The bidirectional outputs are I/O pins which may be used
as either inputs or outputs. Under state machine control,
0165-8
CO,Cl = 11: TOGGLE these pins may be tristated and used as inputs or outputs
Figure 6 depending on how the OE term is programmed.
The third configuration, TOGGLE, is for counting and Each bidirectional output has an OE or output enable con-
signalling. If the condition decode or the C_IN signal is trol and an associated input path to the first array. The OE
true, then the register will toggle. The TOGGLE configu- control is an OR term from the output array which enables
ration is intended to make counters and state machines the output when the OR function is true. Thus, an OE
with simple control requirements. which has its OR term connected to line 33 will turn the
output on permanently.
There is one local reset signal for each group of 4 macro-
cells. The local reset condition decoders will only work The Mealy outputs are designed to implement the fastest
with TOGGLE configurations. possible path between an input to the device and an output.
Functions are available which combine the OR term and
The Output Section an input signal. These functions, XOR, AND, and OR,
There are 3 types of outputs: normal, bidirectional and with true or negated assertion levels, ure useful for data
Mealy. All 3 types can function as normal outputs, but two strobes and semaphore operations where signalling occurs
types-the bidirectional type and the Mealy type----can be depending on the state, but independent of a signal tran-
used for other purposes. The bidirectional type can be used sition.
as an input and the Mealy type can be used as a fast combi- The AND and OR functions can be used to gate data
national output. strobe signals by the state. The XOR function can be used
The different types of output structures are shown in Fig- to implement 2 cycle signalling, which is used in self-timed
ure 7. Note that the only output type that has configura- systems to minimize signalling delays. If these functions
tion information to be programmed is the Mealy type. are not needed, then the Mealy outputs can be configured
as normal outputs.
4-125
!'
~rn
c:
8
~
~
9o
0\
I-l
f"
-~
e
Q
n ~
0"1 ~
~
;'
~
~
~
i
~ ~
~ ~
~
~
~
~
~
0165-10
@
n
CN
0'\
joo6
~~~~~UcrOR=====================================================================
~~ 2
------~~~~_+--~--+__+--~--+__+~~~--~~~~_+--------_4~~~~ ~ i
- -I]]:c
:::::

------_r~~~_+---;--+__+--~--+__+~~~--_r~r_~_+--~~--_;~~ ~
------_r~r_~_+---;--+__+--~--+__+~~~--_r~r_~_+---~_~--~~~
::::: f
"':::-
~,
~.
. :::-
~~
.:::-
~g
~i
... """ ~i ~!::
... ~i .,. ~ !!!
~~
.... ~e
.,.-ali!!
~i ""r(]]~
Figure 8b. CY7C361 Block Diagram (Lower Half)
4-127
~~~U~==============================================================
IRS- r:IRH. ~ts- I--tH f4-- tWH
WL .=j
elK l( '[ l(
"
)( )~
- ~
14-17 l(
ki"p~ !+tc....,::1
l( l(
~ ~tso ~ ~tso
l( l(
I+-tco.:J
)(
2 t so
l(
_t _ t PZX j -
PXZ~
~
0165-12
Figure 9. AC Timing Waveforms
Pin Configuration
4 3 2: 1 : 28 27 26
11 5 25
12 6 24 "'3
23
"'GND
2
GND
GND
14 10 M1
15 11 19 Mo
12 13 14 15 16 17 18
0165-2
4128
~ PLD Programming Information
~~~~UaoR==================================================================
Introduction Programmable Technology
PLDs or Programmable Logic Devices provide an attract- EPROM Process Technology
ive alternative to logic implemented with discrete devices.
Because the primary requirements for this logic has been to EPROM technology employs a floating or isolated gate
provide high performance and increased functional density, between the normal control gate and the source/drain re-
in the past all programmable logic functions have been im- gion of a transistor. This gate may be charged with elec-
plemented in a bipolar technology. Bipolar technology uses trons during the programming operation and when
a fuse for the programming mechanism. The fuses are in- charged with electrons, the transistor is permanently
tact when the product is delivered to the user, and may be turned off. When uncharged (the transistor is unpro-
programmed once, then read and used indefinitely. The grammed) the device may be turned on and off normally
with the control gate. The state of the floating gate,
III
fuses are literally blown using a high current supplied by a
programming system. Programming or blowing a fuse is a charged or uncharged, is permanent because the gate is
one time event, once blown the fuse is forever open. A fuse isolated in an extremely pure oxide. The charge may be
therefore may not be tested to see that it will blow or pro- removed if the device is irradiated with ultraviolet energy .4
gram properly before it is delivered to the user. This diffi- in the form of light. This ultraviolet light allows the elec-
culty in testing fuses for programming results in less than trons on the gate to recombine and discharge the gate. This
100% programming yield in the field, and this fallout falls process is repeatable and therefore can be used during the
into three categories. processing of the device, repeatedly if necessary, to assure
programming function and performance.
A certain percentage of the product simply fails to pro-
gram. These devices are easily identified, and may be re- Two Transistor Cells
turned for replacement. A small percentage of the product In order to provide an EPROM cell that is as fast as the
will program and verify correctly, but fail to function prop- fuse technology employed in bipolar processes, Cypress
erly as a logic element. This can happen because, without uses a two transistor EPROM cell. One transistor is opti-
programming each location, the connection between the mized for reliable programming, and one transistor is opti-
programmed cell and the logic it is to control cannot be mized for high speed. The floating gates are connected
verified. Some programmers can test for this condition such that charge injected on the floating gate of the pro-
through the use of a set of test vectors for each unique code gramming transistor is conducted to the read transistor bi-
or part. Additional material will be lost, however, even if a asing it off.
structured set of test vectors is used due to the device func-
tioning too slow. This failure is much more subtle and can Programming Algorithm
only be found by 100% AC testing of the programmed Byte Addressing and Programming
device, or worse yet by troubleshooting an assembled board
or system. All Cypress Programmable Logic Devices are addressed
and programmed on BYTE or EXTENDED BYTE basis
Cypress PLDs use an EPROM programming mechanism. where an EXTENDED BYTE is a field that is as wide as
This technology has been available since the early 1970's, the output path of the device. Each device or family of
however, as with most MOS technologies, the emphasis has devices has a unique address map which is available in the
been on density, not performance. CMOS at Cypress is as product data sheet. Each BYTE or EXTENDED BYTE is
fast as or faster than Bipolar and coupled with EPROM written into the addressed location from the pins that serve
programming, offers a viable alternative to bipolar pro- as the output pins in normal operation. To program a cell,
grammable logic from a performance point of view. In ad- a "I" or HIGH is placed on the input pin and a "0" or
dition, CMOS EPROM technology offers other over- LOW is placed on pins corresponding to cells that are not
whelming advantages. EPROM cells are programmed by to be programmed. Data is also read from these pins in
injecting charge on an electrically isolated gate which caus- parallel for verification after programming. A "1" or
es the transistor to be permanently turned off. This mecha- HIGH during program verify operation indicates an un-
nism may be reversed by irradiating the cell with ultravio- programmed cell, while a "0" or LOW indicates that the
let light. This feature totally changes the testing philosophy cell accessed has been programmed.
and provides a new feature for the user. All programmable
cells may now be tested by the manufacturer prior to deliv- Blank Check
ery to the customer. This provides an easy methodology to Before programming all Programmable Logic Devices may
certify programming, functionality, and performance. With be checked in a conventional manner to determine that
built in test arrays, functionality and performance may be they have not been previously programmed. This is accom-
tested even if the device is packaged in a non-windowed plished in a program verify mode of operation by reading
package. Devices packaged in a windowed package may be the contents of the array. During this operation, a "I" or
programmed and erased indefinitely providing the designer HIGH output indicates that the addressed cell is unpro-
a tool for the development of his logic without throwing grammed, while a "0" or LOW indicates a programmed
away devices that are programmed incorrectly as the de- cell.
sign proceeds.
4-129
.~ PLD Programming Information (Continued)
~~~~~~~~==~==~~====~~~====~~~~~~~==~~~~~~==
Programming The Data Array Data I/O Corporation
Programming is accomplished by applying a supervoltage 10525 Willows Rd. N.E.
to one pin of the device causing it to enter the program- P.O. Box 97046
ming mode of operation. This also provides the program- Redmond, WA
ming voltage for the cells to be programmed. IIi this mode 98073-9746
of operation, the address lines of the device are used to (206) 881-6444
address each location to be programmed, and the data is Adapters:
Datal/029B
presented on the pins normally used for reading the con-
tents of the device. Each device has a READ/WRITE pin LOGICPAK V04 PT Generic
in the programming mode. This signal causes a write oper- Generic Family
ation when switched to a supervoltage, and a read opera- Cypress 303A-009 303A-OllA/B
Part Code and
tion when switched to a logic "0" or LOW. In the logic Part Number Revision Revision
Number Pinout
HIGH state "I" the device is in a program inhibit condi-
tion and the output pins are in a high impedance state. PALCl6R8 l6R8 [1] 28 24 V03 VOl
During a WRITE operation, the data on the output pins is PALC1 6R6 16R6 [1] 28 24 V03 VOl
written into the addressed array location. In a READ oper- PALC16R4 16R4 [1] 28 24 V03 VOl
ation the contents of the addressed location are present on PALC16L8 l6L8 [1] 28 17 V03 VOl
the output pins and may be verified. Programming there- PALC22V1O 22V1O 28 28 V04 VOl
fore is accomplished by placing data on the output pins, PLDC20G10 20G1O 28 56 V04 VOl
and writing it into the addressed location. Verification of PLDC20G10 20R4 28 65 V04 V02
data is accomplished by examining the information on the PLDC20G10 20R6 28 66 V04 V02
output pins during a READ operation. PLDC20G10 20R8 28 27 V04 V02
The timing for actual programming is supplied in the PLDC20G10 20L8 28 26 V04 VOl
unique programming specification for each device. PLDC20G10 20LlO 28 6 V04 VOl
Phantom Operating Modes PLDC20G10 20L2 28 5 V04 V02
PLDC20GIO l8L4 28 4 V04 VOl
All Cypress Programmable Logic Devices contain a PLDC20G10 l6L6 28 3 V04 VOl
PHANTOM ARRAY for the purposes of post assembly PLDC20G1O l4L8 28 2 V04 VOl
testing. This array is accessed, programmed and operated PLDC20G10 l2L10 28 1 V04 VOl
in a special PHANTOM mode of operation. In this mode, CY7C330 7C330 lA V06 VOl
28
the normal array is disconnected from control of the logic,
and in its place the PHANTOM ARRAY is connected. In Note:
normal operation the PHANTOM ARRAY is disconnect- 1. Requires Design Adapter 100.
ed and control is only via the normal array. This special
feature allows every device to be tested for both functional- Data I/O Mode160A, 60H
ity and performance after packaging and, if desired, by the Cypress Generic Family Code
user before programming and use. The PHANTOM modes Revision
Part Number Part Number and Pinout
are entered through the use of supervoltages and are
unique for each device or family of devices. See specific PALC16R8 l6R8 28 24 V05
data sheets for details. PALC16R6 l6R6 28 24 V05
PALC1 6R4 l6R4 28 24 V05
Special Features PALCl6L8 l6L8 28 17 V05
Cypress Programmable Logic devices, depending on the PALC22V1O 22V1O 28 28 V08
device, have several special features. For example the secu- PLDC20G10 20G1O 28 56 V08
rity mechanism defeats the verify operation and therefore
secures the contents of the device against unauthorized
tampering or access. In advanced devices such as the PAL Data I/O Unisite
C 22V1O, PLD C 20010, and the CY7C330 the MACRO- Cypress Generic Family Code
CELLs are programmable through the use of the architec- Revision
ture bits. This allows the user to more effectively tailor the
device architecture to his unique system requirements. PALCl6R8 l6R8 2.0
These features are also programmed though the use of PALC16R6 l6R6 2.0
EPROM cells. Specific programming is detailed in the de- PALC16R4 l6R4 Menu 2.0
vice data sheet. PALC16L8 l6L8 Driven 2.0
PALC22V1O 22V1O 2.0
Programming Support PLDC20G10 20G1O 2.0
Programming support for Cypress CMOS Programmable
Logic Devices is available from a number of programmer
manufacturers, some of which are listed as follows. The
hardware module version number listed is the earliest ver-
sion qualified by Cypress. Any subsequent version is also
qualified unless otherwise specifically noted.
4-130
~ PLD Programming Information (Continued)
~~~NDUcrOR =====================================================================
Stag Microsystems Logical Devices Inc.
1600 Wyatt Dr. 1321 N.W. 65th Place
Santa Clara, CA 95054 Ft. Lauderdale, FL 33309
(408) 988-1118 (305) 974-0975
STAG ZL32 Rev. 30A03
Logical Devices ALLPRO Rev. V1.4
STAG PPZ Zm2200 Rev. 18
Cypress Generic Family Code
ZL32 Rev. 30A03
Cypress Generic Family Code
Part Number Part Number and Pinout PALC16R8 16R8
PALC16R6 16R6
PALC16R8 16R8 Menu
PALC16R4 16R4

PALC16R6 16R6 Driven
Menu PALC16L8 16L8
PALC16R4 16R4
Driven PALC22VlO 22VlO
PALC16L8 16L8
PALC22VlO 22VlO
Kontron Electronics
1230 Charleston Road
Cypress Semiconductor Inc.
Mountain View, CA
3901 North First Street
94039-7230
San Jose, CA 95134
(415) 965-7020
(408) 943-2600
Cypress CY3000 QuickPro Rev. PLD 2.0 Kontron EPP 80 UPMP
Cypress Generic Family Code Cypress Generic Family Code

Part Number Part Number and Pinout Part Number Part Number and Pinout
PALC16R8 16R8 PALC16R8 16R8
Menu
Driven
PALC16L8 16L8 PALC16L8 16L8
PALC22VlO 22VlO PALC22VlO 22VlO
PLDC20GI0 20GlO
PLDC20GI0 20R4 Third Party Development Software Supported Devices:
PLDC20GI0 20R6 ABELTM PALC16R8
PLDC20GlO 20R8 Data I/O Corporation PALC16R6
PLDC20GlO 20L8 Menu 10525 Willows Rd. N.E. PALC16R4
PLDC20GI0 20LlO Driven P.O. Box 97046 PALC16L8
PLDC20GIO 20L2 Redmond, WA PALC22VlO
PLDC20GI0 18L4 98073-9746 PLDC20GI0
PLDC20GI0 16L6
(206) 881-6444 CY7C330
PLDC20GI0 14L8
PLDC20GI0 12LIO
PLD20RAI0 20RAlO CUPLTM PALC16R8
CY7C330 7C330 Assisted Technology PALC16R6
CY7C331 7C331 1290 Parkmoor Ave. PALC16R4
CY7C332 7C332 San Jose, CA 95126 PALC16L8
(800) 523-5207 PALC22VlO
Digelec Corporation (800) 628-8748 CA CY7C330
1602 Lawrence Ave.
Suite 113 LOG/iCTM PALC16R8
Ocean, NJ 07712 ISDATAGmbH PALC16R6
(201) 493-2420 Haid-und-Neu-Strasse 7 PALC16R4
D-7500 Karlsruhe 1 West Germany PALC16L8
DIGELEC 803 FAM-52 Rev. A-6.0
(0721) 69 30 92 PALC22VI0
Cypress Generic Family Code Adapter CY7C330
Part Number Part Number and Pinout Rev. A3 CY7C331
PALC16R8 16R8 DA-53
PALC16R6 16R6 DA-53
Menu
PALC16R4 16R4 DA-53
Driven
PALC16L8 16L8 DA-53
PALC22VlO 22VlO DA-53
ABELTM is a trademark of Data I/O Corporation.

CUPLTM is a trademark of Assisted Technology.
ISDATA is a registered trademark ofISDATA GmbH.
LOG/iCTM is a trademark of ISDATA GmbH.
4-131
PRODUCT ~~l
INFORMATION
STATIC RAMS ==~==========~~
EPLDS ~====~~===========E
MILITARY ======================~
PLD TOOLKIT ::::::::::::::::::~,.
QUALITY AND ~_
RELIABILITY
APPLICATION BRIEFS _
_ ,._ _ _... _., .. _ "'H_

.. __.__ . _. ,._.-.... .....-._,--------'-'_.__._-_.... .....,_.......
, , , ... _..-.
~ Section Contents
~~~NDUcrOR==================================================================
LOGIC
CY7C424 Cascadeable 1024 x 9 FIFO .................................................. 5-48
CY7C51O 16 x 16 Multiplier Accumulator ............................................... 5-60
CY7C516 16 x 16 Multiplier ........................................................... 5-72
CY7C517 16 x 16 Multiplier ........................................................... 5-72
CY7C901 CMOS 4-Bit Slice ........................................................... 5-84
CY7C909 Microprogram Sequencer .................................................... 5-99
CY7C91O Microprogram Controller ................................................... 5-110
CY7C9101 CMOS 16-Bit Slice ......................................................... 5-121
CY7C9115 CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
~ Section Contents
~~~~UcrOR~================================================================
LOGIC
CY7C51O 16 x 16 Multiplier Accumulator ............................................... 5-60
CY7C516 16 x 16 Multiplier ........................................................... 5-72
CY7C517 16 x 16 Multiplier ........................................................... 5-72
CY7C901 CMOS 4-Bit Slice ........................................................... 5-84
CY7C91O Microprogram Controller ................................................... 5-110
CY7C9101 CMOS 16-Bit Slice ......................................................... 5-121
CY2901C
CYPRESS
SEMICONDUCTOR CMOS Four-Bit Slice
Features
Pin compatible and functional ESD protection The operation performed is determined
equivalent to AMD AM2901C Capable of withstanding by nine input control lines (10 to Is)
greater than 2000V static that are usually inputs from an instruc-
Low power
discharge voltage tion register.
Vee margin The CY2901 is expandable in 4-bit in-
- SV lO% Functional Description crements, has three-state data outputs
- All parameters guaranteed
over commercial and military The CY2901 is a high-speed, expand- as well as flag outputs, and can use ei-
operating temperature range able, 4-bit wide ALU that can be used ther a full-look ahead carry or a ripple
to implement the arithmetic section of carry.
Eight function ALU a CPU, peripheral controller, or pro-
Performs eight operations on The CY2901 is a pin compatible, func-
grammable controller. The instruction
two 4-bit operands tional equivalent, improved perform-
set of the CY2901 is basic but yet so
ance replacement for the AM2901.
Expandable versatile that it can emulate the ALU
Infinitely expandable in 4-bit of almost any digital computer. The CY2901 is fabricated using an ad-
increments vanced 1.2 micron CMOS process that
The CY2901, as illustrated in the block
eliminates latchup, results in ESD pro-
Four status flags diagram, consists of a 16-word by 4-bit
tection over 2000V and achieves supe-
Carry, overflow, negative, zero dual-port RAM register file, a 4-bit
rior performance at a low power dissi-
ALU and the required data manipula- pation.
tion and control logic.

Top View
OE
CLOCK
'A'(READI
--===n===-..., A,
Ao
Y3
Y2
ADDRESS 16 Yo
18 P
'S'
(READ/WRITEI OVR
ADDRESS Cn +4
G
Vee
F= D GND
10 Cn
12
CP 13
03 Do
So 0,
CARRY IN B, 02
S2 03
B3
0007-2
DATA OUT
0007-1
Selection Guide See last page for ordering information.

Read Modify-Write Cycle (Min.) in ns Operating Iec (Max.) in mA Operating Range Part Number
31 140 Commercial CY2901C
32 180 Military CY2901C
5-1
~ CY2901C
~~~NDUcrOR ==================================================================~
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... >2OO1V
Power Applied .................... - 55C to + 125C Latchup Current (Outputs) .................. > 200 mA
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V
Operating Range
Range Vee
Output Current into Outputs (Low) ............. 30 mA MilitaryU] - 55C to + 125C 5V 1O%
Note:
Pin Definitions
Signal Signal
Name I/O Description Name I/O Description
These 4 address lines select one of the registers in Q3 I/O Outputs: When the destination code on lines
the stack and output its contents on the (internal) RAM3 16,7,8 indicates a shift left (UP) operation the
Aport. (Cont.) three-state outputs are enabled and the MSB of
These 4 address lines select one of the registers in the Q register is output on the Q3 pin and the
the stack and output is contents on the (internal) MSB of the ALU output (F3) is output on the
B port. This can also be the destination address RAM 3 pin.
when data is written back into the register file. Inputs: When the destination code indicates a
10- 18 These 9 instruction lines select the ALU data shift right (DOWN) the pins are the data inputs
sources (10, 1, 2), the operation to be performed to the MSB of the Q register and the MSB of the
(13, 4, 5) and what data is to be written into either RAM.
the Q register or the register file (16, 7, 8). Qo I/O These two lines are bidirectional and function in a
Do-D3 I These are 4 data input lines that may be selected RAMo manner similar to the Q3 and RAM3 lines, except
by the 10,1, 2 lines as inputs to the ALU. that they are the LSB of the Q register and RAM.
YO-Y3 0 These are three-state data output lines that, when Cn I The carry-in to the internal ALU.
enabled, output either the output of the ALU or Cn +4 0 The carry-out from the internal ALU.
the data in the A latches, as determined by the G, P 0 The carry generate and the carry propagate
code on the 16, 7, 8 lines. outputs of the ALU, which may be used to
Output Enable. This is an active LOW input that perform a carry look-ahead operation over the 4
controls the Y 0- Y 3 outputs. When this signal is bits of the ALU.
LOW the Y outputs are enabled and when it is OVR 0 Overflow. This signal is logically the exclusive-
HIGH they are in the high impedance state. OR of the carry-in and the carry-out ofthe MSB
CP Clock Input. The LOW level of the clock writes ofthe ALU. This pin indicates that the result of
data to the 16 x 4 RAM. The HIGH level of the the ALU operation has exceeded the capacity of
clock writes data from the RAM to the A-port the machine. It is valid only for the sign bit and
and B-port latches. The operation of the Q assumes two's complement coding for negative
register is similar. Data is entered into the master numbers.
latch on the LOW level of the clock and F = 0 0 Open collector output that goes HIGH if the data
transferred from master to slave when the clock is on the ALU outputs (Fa, 1,2, 3) are all LOW. It
HIGH. indicates that the result of an ALU operation is
I/O These two lines are bidirectional and are zero (positive logic).
controlled by the 16, 7, 8 inputs. Electrically they F3 0 The most significant bit of the ALU output.
are three-state output drivers connected to the
TTL compatible CMOS inputs.
5-2
~ CY2901C
~~~NDUcrOR=======================================================================
Electrical Characteristics Over Commercial and Military Operating Range[3]
Vee Min. = 4.5V, Vee Max. = 5.5V
Vee = Min.
IOH = -3.4mA
Vee = Min.
VOL Output LOW Voltage IOL = 20 mA Commercial 0.4 V
IOL = 16 rnA Military
Vee = Max.
IIH Input HIGH Current 10 ,."A
VIN = Vee

Vee = Max.
IlL Input LOW Current -10 ,."A
VIN = GND
Vee = Min.
IOH Output HIGH Current -3.4 rnA
VOH = 2.4V
IOL Output LOW Current

Vee = Min.
VOL = 0.4V
I Commercial 20 mA
I Military 16 rnA
Vee = Max. +40 ,."A
loz Output Leakage Current
VOUT = GND to Vee -40 ,."A
Vee = Max.
Ise Output Short Circuit CurrentU] -30 -85 rnA
VOUT = OV
lee Supply Current Vee = Max. I Commercial 140 rnA

I Military 180 mA
Capacitance [2]
CIN Input Capacitance TA = 25C, f= 1 MHz 5
pF
COUT
Notes:
1. Not more than one output should be tested at a time. Duration ofthe 3. See the last page of this specification for Group A subgroup testing
short circuit should not be more than one second. information.
Output Loads used for AC Performance Characteristics

+5 V
vo~VO!l
lCL
0007-4
0007-3
All outputs except open drain Open drain (F = 0)
Notes:
I. eL = 50 pF includes scope probe, wiring and stray capacitance.
2. eL = 5 pF for output disable tests.
3. Loads shown above are for commercial (20 rnA) IOL specifications
only.
Commercial Military
RI 203.0. 252.0.
R2 148.0. 174.0.
5-3
~CfPFESS CY2901C
'nEMICONDUcrOR ===================================================================
CY2901C Guaranteed Commercial Cycle Time and Clock Characteristics
Range AC Performance Characteristics CY2901- C
The tables below specify the guaranteed AC performance Read-Modify-Write Cycle (from 31 ns
of these devices over the Commercial (OGC to 70GC) operat- selection of A, B registers to
ing temperature range with Vcc varying from 4.5V to end of cycle).
5.5V. All times are in nanoseconds and are measured be- Maximum Clock Frequency to shift Q 32 MHz
tween the 1.5V signal levels. The inputs switch between OV (50% duty cycle, I = 432 or 632)
and 3V with signal transition rates of 1V per nanosecond. Minimum Clock LOW Time 15 ns
All outputs have maximum DC current loads. See previous
Minimum Clock HIGH Time 15 ns
page for loading circuit information.
Minimum Clock Period 31 ns
This data applies to parts with the following numbers:
For faster performance see CY7C901-23 specification.
CY2901CPC CY2901CDC CY2901CLC
Combinational Propagation Delays. CL = 50 pF

To Output RAMO Qo
From Input
y F3 en + 4 G,P F=O OVR
RAM3 Q3
A, BAddress 40 40 40 37 40 40 40 -
D 30 30 30 30 38 30 30 -
Cn 22 22 20 - 25 22 25 -
1012 35 35 35 37 37 35 35 -
1345 35 35 35 35 38 35 35 -
1678 25 - - - - - 26 26
A Bypass ALU
(I = 2XX) 35 - - - - - - -
Clock.-r 35 35 35 35 35 35 35 28
Set-up and Hold Times Relative to Clock (CP) Input

CP: ~
--f-
Input Set-upTime Hold Time Set-upTime Hold Time

BeforeH ~ L AfterH ~ L BeforeL ~ H AfterL ~ H
A, B Source Address 15 1 30, 15 + tpwL 1
(Note 3) (Note 4)
B Destination Address 15 +- Do Not Change ~ 1
D - - 25 0
en - - 20 0
1012 - - 30 0
1345 - - 30 0
1678 10 +- Do Not Change ~ 0
RAMo, 3,QO, 3 - - 12 0
Output EnablelDisable Times

Output disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.
3. Source addresses must be stable prior to the clock H -+ L transition
to allow time to access the source data before the latches close. The A
address may then be changed. The B address could be changed if it is
not a destination; i.e. if data is not being written back into the RAM.
Notes: Normally A and B are not changed during the clock LOW time.
1. A dash indicates a propagation delay path or set-up time constraint 4. The set-up time prior to the clock L -+ H transition is to allow time
does not exist. for data to be accessed, passed through the ALU, and returned to the
2. Certain signals must be stable during the entire clock LOW time to RAM. It includes all the time from stable A and B addresses to the
avoid erroneous operation. This is indicated by the phrase "do not clock L -+ H transition, regardless of when the clock H -+ L
change". transition occurs.
5-4
~ CY2901C
~~~~UcrOR=======================================================================
CY2901C Guaranteed Military Cycle Time and Clock Characteristics [5]
Range AC Performance Characteristics CY2901- C
The tables below specify the guaranteed AC performance Read-Modify-Write Cycle (from 32 ns
of these devices over the Military (- 55C to + 125C) op- selection of A, B registers to
erating temperature range with V cc varying from 4.5V to end of cycle).
5.5V. All times are in nanoseconds and are measured be- Maximum Clock Frequency to shift Q 31 MHz
tween the 1.5V signal levels. The inputs switch between OV (50% duty cycle, I = 432 or 632)
and 3V with signal transition rates of 1V per nanosecond. Minimum Clock LOW Time 15 ns
All outputs have maximum DC current loads. See "Electri-
Minimum Clock HIGH Time 15 ns
cal Characteristics" ofthis data sheet for loading circuit
information. Minimum Clock Period 32ns
For faster performance see CY7C901-27 specification.
CY2901CDMB
Combinational Propagation Delays CL = 50 pp[S]

To Output RAMO Qo
y F3 Cn +4 G,P F=O OVR
RAM3 Q3
From Input
A, BAddress 48 48 48 44 48 48 48 -
D 37 37 37 34 40 37 37 -
en 25 25 21 - 28 25 28 -
1012 40 40 40 44 44 40 40 -
1345 40 40 40 40 40 40 40 -
1678 29 - - - - - 29 29
A Bypass ALU
(I = 2XX)
40 - - - - - - -
Clock...tr 40 40 40 40 40 40 40 33
Set-up and Hold Times Relative to Clock (CP) Input[5]

CP: ~
--
Set-upTime Hold Time Set-upTime Hold Time
Input
BeforeH -.. L AfterH -.. L BeforeL -.. H AfterL -.. H
A, B Source Address 15 2 30,15 + tPWL 2
(Note 3) (Note 4)
B Destination Address 15 +- Do Not Change 2 -..
D - - 25 0
Cn - 20 - 0
1012 - - 30 0
1345 - - 30 0
1678 10 +- Do Not Change 0 -..
RAMo, 3,Qo, 3 - 12 - 0
Output Enable/Disable Times [5]

Output disable tests performed with CL = 5 pP and measured to 0.5V change of output voltage level.
Output 3. Source addresses must be stable prior to the clock H --+ L transition
to allow time to access the source data before the latches close. The A
Y address may then be changed. The B address could be changed if it is
Notes: Normally A and B are not changed during the clock LOW time.
1. A dash indicates a propagation delay path or set-up time constraint 4. The set-up time prior to the clock L --+ H transition is to allow time
does not exist. for data to be accessed, passed through the ALU, and returned to the
2. Certain signals must be stable during the entire clock LOW time to RAM. It includes all the time from stable A and B addresses to the
avoid erroneous operation. This is indicated by the phrase "do not clock L --+ H transition, regardless of when the clock H --+ L
change". transition occurs.
information.
5-5
~ CY2901C
~~~~DUaoR==================================================================
Read
Modify- Package Operating
Ordering Code
Write Type Range
Cycle (ns)
31 CY2901CPC P17 Commercial
31 CY290 1CDC 018 Commercial
32 CY2901CDMB 018 Military
5-6
~FSS CY2901C
~~IOO~UcrOR==================================================================
DC Characteristics Combinational Propagation Delays (Continued)
VOH 1,2,3 FromCn toY 7,8,9,10,11
VOL 1,2,3 FromCn toF3 7,8,9,10,11
VIH 1,2,3 From Cn to Cn + 4 7,8,9,10,11
VILMax. 1,2,3 From Cn to F = 7,8,9,10,11
IIH 1,2,3 From Cn to OVR 7,8,9,10,11
IlL 1,2,3 From Cn to RAMo, 3 7,8,9,10,11
IOH 1,2,3 From 1012 to Y 7,8,9,10,11
IOL 1,2,3 From 1012 to F3 7,8,9,10,11
loz 1,2,3 From 1012 to C n + 4 7,8,9,10,11
Isc 1,2,3 From 1012 to G, P 7,8,9,10,11
Icc 1,2,3 From 1012 to F = 7,8,9,10,11
From 1012 to OVR 7,8,9,10,11
Cycle Time and Clock Characteristics From 1012 to RAMO, 3 7,8,9,10,11
Parameters Subgroups From 1345 toY 7,8,9,10,11
Minimum Clock LOW Time 7,8,9,10,11 From 1345 to F3 7,8,9,10,11
Minimum Clock HIGH Time 7,8,9,10,11 From 1345 to C n + 4 7,8,9,10,11
From 1345 to G, P 7,8,9,10,11
Combinational Propagation Delays From 1345 to F = 7,8,9,10,11
Parameters Subgroups From 1345 to OVR 7,8,9,10,11
From A, B Address to Y 7,8,9,10,11 From 1345 to RAMo, 3 7,8,9,10,11
From A, B Address to F3 7,8,9,10,11 From 1678 to Y 7,8,9,10,11
From A, B Address to C n + 4 7,8,9,10,11 From 1678 to RAMO, 3 7,8,9,10,11
From A, B Address to G, P 7,8,9,10,11 From 1678 to Qo, 3 7,8,9,10,11
From A, B Address to F = 7,8,9,10,11 From A Bypass ALU to Y

(I = 2XX)
7,8,9,10,11
From A, B Address to OVR 7,8,9,10,11
From Clock ~ to Y 7,8,9,10,11
From A, B Address to RAMo, 3 7,8,9,10,11
From Clock ~ to F3 7,8,9,10,11
From DtoY 7,8,9,10,11
From Clock ~ to C n + 4 7,8,9,10,11
FromDtoF3 7,8,9,10,11
From Clock ~ to G, P 7,8,9,10,11
From D to C n + 4
FromDto G, P
7,8,9,10,11
7,8,9,10,11
From Clock ~ to F = 7,8,9,10,11
FromDto F = 7,8,9,10,11
From Clock ~ to OVR
From Clock ~ to RAMo, 3
7,8,9,10,11
7,8,9,10,11
FromDtoOVR 7,8,9,10,11
From Clock ~ to Qo, 3 7,8,9,10,11
From D to RAMo, 3 7,8,9,10,11
5-7
~ CY2901C
~~~NDUcrOR ==================================================================
A, B Source Address 7,8,9,10,11 D Hold Time After L ---+ H 7,8,9,10,11
Set-up Time Before H ---+ L C n Set-up Time Before L ---+ H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 C n Hold Time After L ---+ H 7,8,9,10,11
Hold Time After H ---+ L
1012 Set-up Time Before L ---+ H 7,8,9,10,11
A, B Source Address 7,8,9,10,11
Set-up Time Before L ---+ H 1012 Hold Time After L ---+ H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 1345 Set-up Time Before L ---+ H 7,8,9,10,11
Hold Time After L ---+ H 1345 Hold Time After L ---+ H 7,8,9,10,11
B Destination Address 7,8,9,10,11 1678 Set-up Time Before H ---+ L 7,8,9,10,11
Set-up Time Before H ---+ L
1678 Hold Time After H ---+ L 7,8,9,10,11
B Destination Address 7,8,9,10,11
Hold Time After H ---+ L
1678 Set-up Time Before L ---+ H 7,8,9,10,11

1678 Hold Time After L ---+ H 7,8,9,10,11
Set-up Time Before L ---+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11
Set-up Time Before L ---+ H
Hold Time After L ---+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11
Hold Time After L ---+ H
D Set-up Time Before L ---+ H 7,8,9,10,11
5-8
CY2909A
CY2911A
CYPRESS
SEMICONDUCTOR CMOS Micro Program
Sequencers
Features
Fast ESD protection 1) a set of four external direct inputs
- CY2909A/llA has a 40 ns Capable of withstanding greater (Di); 2) external data stored in an inter-
(min.) clock to output cycle than 2000V static discharge nal register (RO; 3) a four word deep
time; commercial voltage push/pop stack; or 4) a program coun-
- CY2909/11 has a 40 ns Pin compatible and ter register (which usually contains the
(min.) clock to output cycle functional equivalent to last address plus one). The push/pop
time; military AMD AM2909A/AM2911A stack includes control lines so that it
can efficiently execute nested subrou-
Low power
- Icc (max.) = 70 mA Description tine linkages. Each of the four outputs
commercial The CY2909A and CY2911A are high-
(Yi) can be OR'ed with an external in-
put for conditional skip or branch in-
5
- Icc (max.) = 90 mA speed, four-bit wide address sequencers
military structions. A ZERO input line forces
intended for controlling the sequence the outputs to all zeros. The outputs
Vee margin of execution of microinstructions con- are three state, controlled by the
- 5V 10% tained in microprogram memory. They Output Enable (OE) input.
- All parameters guaranteed may be connected in parallel to expand
over commercial and military the address width in 4 bit increments. The CY2911A is an identical circuit to
operating temperature range Both devices are implemented in high the CY2909A, except the four OR in-
performance CMOS for optimum puts are removed and the D and R in-
Expandable puts are tied together. The CY2911A is
Infinitely expandable in 4-bit speed and power.
available in a 20-pin, 300-mil package.
increments The CY2909A can select an address The CY2909 is available in a 28-pin,
from any of four sources. They are: 600-mil package.

R (2909.11 ONLY)
RE:
11------t4
VCC CP
R3 CP
Vcc
REGISTER {' R2 PUP
ENABLE I FE
RE
R,
RE) : 03
RO Cn+ 4
OR 3 Cn O2
I
D AND R
CONNECTED j 4 03 OE 0,
ON 2~~L~ I OR 2 Y3 DO
I O2 Y2
I GNO
DIRECT I CLOCK
OR, Y,
ZERO
INPUTS I
0,
D >-........----7'---1 ORo
Yo
5,
So
DO So
0066-3
GNO ZERO
0066-2
or o::No::l')l~ Jlfi ~
4 3 2 1 282726
RO 5 25 FE
ZERO OR 3 6 24 Cn+4
7 23 Cn
3
OR 2 8 2909A 22 OE
2 9 21 Y3
OR , 10 20 Y2
0, 11 19 Y,
12131415161718
OUTPUT
ENABLE
OE >-01 =:)-4~"""i--4'+..J
0066-5
0066-4
Cn +4 0066-1
5-9
CY2909A
5'A .
~DUcrOR=======================================================================
CY2911A
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ..................... >2oolV
Power Applied .................... - 55C to + 125C Latch-Up Current ......................... >200 mA
Supply Voltage to Ground Potential .... - 0.5V to + 7.0V
Operating Range
Ambient
in High Z State ...................... -0.5Vto +7.0V Range Vee
Temperature
DC Input Voltage ................... - 3.OV to + 7.0V Commercial OCto + 70C 5V 10%


Vee = Min.,IOH = -2.6 rnA (Comm.) 2.4 V
Vee = Min., IOH = - 1.0 rnA (Mil.) 2.4 V
VOL Output LOW Voltage Vee = Min.,IOL = 16.0mA 0.4 V
VIH Input High Voltage 2.0 Vee V
IIX Input Load Current GND s: VIs: Vee -10 +10 /LA
loz
Output Leakage GND s: Vo s: Vee -20 +20 /LA
Output Short
los Circuit Current[1] Vee = Max. VOUT = GND -30 -85 rnA
lee
Vee Operating
Supply Current
Vee = Max.
lOUT = OmA
I Commercial 70
rnA
I Military 90
Capacitance [2]
CIN Input Capacitance TA = 25C, f = 1 MHz 5 pF
COUT
Notes:
affect these parameters. .

R1 R1
n n
5V 5V
3.0V ---~~---~~
OUTPUT OUTPUT
INCLU~NGI
50pf R2 5pf R2 GND
JIG AND -
_
-
INCLUDING
JIG AND -
I _
-
5ns-1
Figure 2
1-5ns
0066-7
SCOPE SCOPE
0066-6
Figure la Figure Ib
Commercial Military
Rl 254.0 258.0
R2 187.0 216.0
5-10
CY2909A
(;A
__
~. ~~'NDUcrOR ===================================================================
CY2911A

2909A 2909A
Units
2911A 2911A
Commercial Military
Minimum Clock Low Time 20 20 ns
Minimum Clock High Time 20 20 ns
MAXIMUM COMBINATIONAL PROPAGATION DELAYS
From Input To: Y CN + 4 Y CN + 4 ns
Dj 17 22 20 25 ns
SO, SI 29 34 29 34 ns
ORjCY2909A 17 22 20 25 ns
CN - 14 - 16 ns
ZERO 29 34 30 35 ns
OE Low to Output 25 - 25 - ns
OE High to High Z[5] 25 - 25 - ns
Clock High, So, SI = LH 39 44 45 50 ns
Clock High, So, SI = LL 39 44 50 45 ns
Clock High, So, SI = HL 44 49 53 58 ns
MINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)
From Input Set-up Hold Set-up Hold
RE 19 4 19 5 ns
Ri [6] 10 4 12 5 ns
Push/Pop 25 4 27 5 ns
FE 25 4 27 5 ns
CN 18 4 18 5 ns
Di 25 0 25 0 ns
ORi (CY2909A) 25 0 25 0 ns
So, SI 25 0 29 0 ns
ZERO 25 0 29 0 ns
Notes:
5. Output Loading as in Figure lb. 6. Rj and Dj are internally connected on the CY2911A. Use Rj set-up
and hold times for Dj inputs.
Switching Waveforms
-MIN CLOCK LOW
CLOCK
HOLD
- - - - I TIMES
INPUT
(EXCEPT BE)
INPUT TO OUTPUTl
1 - - - - - CLOCK TO OUTPUT
(Y. ~~T:~) =><XXXXXXXXXXXXXXXXXX :::::::::::::

0066-8
5-11
CY2909A
5Jl . CY2911A
~~UcrOR==================================================================
Package Operating Package Operating
Type Range Type Range
CY2909APC P15 Commercial CY2911APC P5 Commercial
CY2909AOC 016 CY2911AOC 06
CY2909ALC L64 CY2911ALC L61
CY2909AOMB 016 Military CY2911AOMB 06 Military
CY2909ALMB L64 CY2911ALMB L61
5-12
CY2909A
fin
-..
~. ~~~UcrOR==================================================================
CY2911A

DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3

los 1,2,3
Icc 1,2,3
Minimum Clock Low Time 7,8,9,10,11 MINIMUM SET-UP
Minimum Clock High Time 7,8,9,10,11 AND HOLD TIMES
RE Set-up Time 7,8,9,10,11
MAXIMUM COMBINATIONAL
PROPAGATION DELAYS REHoldTime 7,8,9,10,11
DjtoY 7,8,9,10,11 Push/Pop Set-up Time 7,8,9,10,11
Dj to CN+4 7,8,9,10,11 Push/Pop Hold Time 7,8,9,10,11
So, SI to Y 7,8,9,10,11 FE Set-up Time 7,8,9,10,11
So, SI to CN+4 7,8,9,10,11 FE Hold Time 7,8,9,10,11
ORj (CY2909A) to Y 7,8,9,10,11 CN Set-up Time 7,8,9,10,11
ORj (CY2909A) to CN +4 7,8,9,10,11 CN Hold Time 7,8,9,10,11
CN to CN+4 7,8,9,10,11 Dj Set-up Time 7,8,9,10,11
ZEROtoCN+4 7,8,9,10,11 Dj Hold Time 7,8,9,10,11
Clock High, So, SI = LH 7,8,9,10,11 ORj (CY2909A) 7,8,9,10,11
toY Set-upTime
Clock High, So, S 1 = LH 7,8,9,10,11 ORj (CY2909A) 7,8,9,10,11
toCN+4 Hold Time
Clock High, So, SI = LL 7,8,9,10,11 So, SI Set-up Time 7,8,9,10,11
toY So, SI Hold Time 7,8,9,10,11
Clock High, So, SI = LL 7,8,9,10,11 ZERO Set-up Time 7,8,9,10,11
toCN+4
ZERO Hold Time 7,8,9,10,11
Clock High, So, SI = HL 7,8,9,10,11
toY
toCN + 4
5-13
CY2910A
CYPRESS
SEMICONDUCTOR CMOS Microprogram
Controller
Features
Fast 12-bit Internal loop counter and the required data manipulation
- CY2910AC has a 50 ns (min.) and control logic.
ESD protection
clock cycle; commercial Capable of withstanding over The operation performed is determined
- CY2910AM has a 51 ns 2000 volts static discharge by four input instruction lines (10-13)
(min.) clock cycle; military
voltage that in turn select the (internal) source
Low power Pin compatible and functional of the next micro-instruction to be
- ICC (max.) = 170 mA equivalent to Am2910A fetched. This address is output on the
VCC Margin 5V 10% YO- Yll pins. Two additional inputs
commercial and military Functional Description (CC and CCEN) are provided that are
examined during certain instructions
Sixteen powerful The CY2910A is a stand-alone micro- and enable the user to make the execu-
microinstructions program controller that selects, stores, tion of the instruction either uncondi-
retrieves, manipulates and tests ad- tional or dependent upon an external
Three output enable controls for
three-way branch dresses that control the sequence of ex- test.
ecution of instructions stored in an ex-
Twelve-bit address word ternal memory. All addresses are 12-bit The CY29 lOA is a pin compatible,
binary values that designate an abso- functional equivalent, improved per-
Four sources for addresses: formance replacement for the
microprogram counter (MPC), lute memory location.
Am29 lOA.
branch address bus, 9-word The CY29 lOA, as illustrated in the
stack, internal holding register block diagram, consists of a 9-word by The CY2910A is fabricated using an
12-bit LIFO (Last-In-First-Out) stack advanced 1.2 micron CMOS process
Internal 9-word by 12-bit stack that eliminates latchup, results in ESD
The internal stack can be used and SP (Stack Pointer), a 12-bit RC
(Register/Counter), a 12-bit MPC (Mi- protection of over 2000 volts and
for subroutine return address or achieves superior performance and low
data storage croprogram Counter) and incrementer,
a 12-bit wide by 4-input multiplexer power dissipation.

Y4 D3
D4 Y3
Ys D2
DS Y2
VECT Dl
PL Y1
MAP DO
13 Yo
12 CI
VCC CP
11 GND
10 OE
CCEN Y11
cc D11
RLo Y10
FULL D10
DS Yg
Ys Dg
D7 Ys
=I Y7 DS
0040-3
0040-2
Top View
Selection Guide
Clock Cycle (Min.) in ns Stack Depth Operating Range Part Number
50 9 words Commercial CY2910AC
51 9 words Military CY2910AM
5-14
~ CY2910A
~~~~UcrOR=======================================================================
Maximum Ratings
Power Applied .................... - 55C to + 125C Latchup Current (Outputs) .................. > 200 mA
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V
Operating Range
Range Vee

VCC Min. = 4.5V, VCC Max. = 5.5V
Parameter
VOH
VOL
VIH
VIL
IIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Test Condition
Vee = Min., IOH = - 1.6 rnA
Vee = Min.,IOL = 8 rnA
Vee = Max., VIN = Vee

Min.
2.4
2.0
-3.0
Max.
0.5
Vee
0.8
10
Units
V
V
V
V
""A

IlL Input LOW Current Vee = Max., VIN = GND -to ""A
IOH Output HIGH Current Vee = Min., VIH = 2.4V -1.6 rnA
IOL Output LOW Current Vee = Min., VOL = 0.5V 8 rnA
Vee = Max., +40 ""A
IOZ Output Leakage Current
VOUT = GNDIVee -40 ""A
Ise Output Short Circuit Current Vee = Max., VOUT = OV -85 rnA
lee Supply Current Vee = Max. 170 rnA
Capacitance [2]
CIN Input Capacitance T A = 25C, f = 1 MHz 8 pF
COUT Output Capacitance Vee = 5.0V 10 pF
Notes:
short circuit should not exceed one second. 4. See the last page of this specification for Group A subgroup testing
Output Load for AC Performance Switching Waveforms

Characteristics 3.0V---------'\I'-----~.I,..--
INPUTS
All Outputs
oV--------------'I~--------JI~---
1:
+5 v
3.0V
Vo~, icc
CLOCK
OV
OUTPUTS
------------'I~-------
0040-5
Notes: 0040-4
eL = 50 pF includes scope probe, writing and stray capacitance.
eL = 5 pF for output disable tests.
5-15
~ CY2910A
~~~NDUcrOR ================================================================~===
Guaranteed AC Performance Characteristics
The tables below specify the guaranteed AC performance The inputs switch between OV and 3V with signal tran-
of the CY2910A over the commercial (OC to + 70C) and sition rates of 1 Volt per nanosecond. All outputs have
the military ( - 55C to + 125C) temperature ranges with maximum DC current loads.
Vcc varying from 4.5V to 5.5V. All times are in nanosec-
onds and are measured between the 1.5V signal levels.
Clock Requirements [1, 4]

Commercial Military
Minimum Clock LOW 20 25
Minimum Clock HIGH 20 25
Minimum Clock Period I = 14 50 51
Minimum Clock Period
50 50
I = 8,9, 15 (Note 2)
Combinational Propagation Delays. CL = 50 pF[4]
To Output Commercial Military

From Input y PL, VEcr, MAp FULL y PL, VEcr, MAP FULL
DO-Dll 20 - - 25 - -
10-13 35 30 - 40 35 -
CC 30 - - 36 - -
CCEN 30 - - 36 - -
CP
I = 8,9, 15 40 - 31 - - 35
(Note 2)
CP
All Other I
40 - 31 46 - 35
OE 25 25
(Note 3) 27 - - 30 - -
Minimum Set-up and Hold Times Relative to clock LOW to HIGH Transition. CL = 50 pF[4]
Commercial Military
Input Set-up Hold Set-up Hold
DI ..... RC 16 0 16 0
DI ..... MPC 30 0 30 0
10-13 35 0 38 0
CC 24 0 35 0
CCEN 24 0 35 0
CI 18 0 18 0
RLD 19 0 20 0
Notes:
1. A dash indicates that a propagation delay path or set-up time does not 3. The enable/disable times are measured to a 0.5 Volt change on the
exist. output voltage level with CL = 5 pF.
2. These instructions are dependent upon the register/counter. Use the 4. See the last page of this specification for Group A subgroup testing
shorter delay times if the previous instruction either does not change information.
the register/counter or could only decrement it. Use the longer delay
if the instruction prior to the clock was 4 or 12 or if:RJ::n was LOW.
5-16
~ CY2910A
~~~NDUcrOR =====================================================================
Table of Instructions
REG/ RESULT
CNTR FAIL PASS
13- 10 MNEMONIC NAME REG/
CON CCEN = Landa:: = H CCEN = HorCC = L ENABLE
TENTS CNTR
Y STACK Y STACK
0 JZ Jump Zero X 0 Clear 0 Clear Hold PL
I CJS CondJSBPL X PC Hold D Push Hold PL
2 JMAP Jump Map X D Hold D Hold Hold Map
3 CJP Cond Jump PL X PC Hold D Hold Hold PL
4 PUSH Push/Cond LD CNTR X PC Push PC Push (Note 1) PL
5 JSRP Cond JSB R/PL X R Push D Push Hold PL
6 CJV Cond Jump Vector X PC Hold D Hold Hold Vect

7 JRP Cond Jump RlPL X R Hold D Hold Hold PL
Repeat Loop, *0 F Hold F Hold Dec PL
8 RFCT
CNTR*O =0 PC POP PC Pop Hold PL
RepeatPL, *0 D Hold D Hold Dec PL
9 RPCT
CNTR* 0 =0 PC Hold PC Hold Hold PL
10 CRTN CondRTN X PC Hold F Pop Hold PL
11 CJPP Cond Jump PL & Pop X PC Hold D Pop Hold PL
12 LDCT LD Cntr & Continue X PC Hold PC Hold Load PL
13 LOOP Test End Loop X F Hold PC Pop Hold PL
14 CONT Continue X PC Hold PC Hold Hold PL
*0 F Hold PC Pop Dec PL
15 TWB ThreeWay Branch
=0 D Pop PC Pop Hold PL
Notes:
1. If~ = Land CC = H, hold; else load. H = HIGH L=LOW x= Don't Care
Clock
Package Operating
Cycle Ordering Code
Type Range
(ns)
50 CY2910ADC 018 Commercial
CY2910AJC 167
CY2910ALC L67
CY2910APC P17
51 CY2910ADMB 018 Military
CY2910ALMB L67
517
DC Characteristics Minimum Set-up and Hold Times
VOH 1,2,3 DI ~ RC Set-up Time 7,8,9,10,11
VOL 1,2,3 DI ~ RC Hold Time 7,8,9,10,11
VIH 1,2,3 DI ~ MPC Set-up Time 7,8,9,10,11
VILMax. 1,2,3 DI ~ MPC Hold Time 7,8,9,10,11
IIH 1,2,3 10-13 Set-up Time 7,8,9,10,11
IlL 1,2,3 10-13 Hold Time 7,8,9,10,11
IOH 1,2,3 CC Set-up Time 7,8,9,10,11
IOL 1,2,3 CCHoldTime 7,8,9,10,11
loz 1,2,3 CCEN Set-up Time 7,8,9,10,11
Isc 1,2,3 CCEN Hold Time 7,8,9,10,11
Icc 1,2,3 CI Set-up Time 7,8,9,10,11
CIHoldTime 7,8,9,10,11
Clock Requirements 7,8,9,10,11
RLD Set-up Time
Parameters Subgroups RLD Hold Time 7,8,9,10,11
Minimum Clock LOW 7,8,9,10,11
Combinational Propagation Delays

From DO-D 11 to Y 7,8,9,10,11
From 10-13 to Y 7,8,9,10,11
From 10-13 to PL, VECT, MAP 7,8,9,10,11
FromCCtoY 7,8,9,10,11
From CCEN to Y 7,8,9,10,11
From CP (I = 8, 9, 15) to FULL 7,8,9,10,11
From CP (All Other I) to Y 7,8,9,10,11
From CP (All Other I) to FULL 7,8,9,10,11
Document #: 38-0001O-B
5-18
CY3341
CYPRESS
SEMICONDUCTOR 64 X 4 FIFO Serial Memory
Features Data Input
1.2/2 MHz data rate The four bits of data on the Do through HIGH, indicating the presence of valid
D3 inputs are entered into the first lo- data at the output pins Qo through Q3.
Fully TTL compatible cation when both Input Ready (IR) The transfer of data is initiated when
Independent asynchronous inputs and Shift In (SI) are HIGH. This caus- both the Output Ready output from
and outputs es IR to go LOW but data will stay the device and the Shift Out (SO) input
locked in the first bit location until to the device are HIGH. This causes
Direct replacement for PMOS both IR and SI are LOW. Then data
3341 OR to go LOW; output data, however,
will propagate to the second bit loca- is maintained until both OR and SO
Expandable in word length and tion, provided the location is empty. are LOW. Then the content of the adja-
width When data is transferred, IR will go
power
HIGH indicating that the device is
ready to accept new data. If the memo-
ry is full, IR will stay LOW.
cent (upstream) cell (provided it is full)
will be transferred into the last cell,
causing OR to go HIGH again. If the
memory has been emptied, OR will
stay LOW.
-=--
a:.-.
than 2000V electrostatic Data Transfer
discharge Once data is entered into the second Input Ready and Output Ready may
cell, the transfer of any full cell to the also be used as status signals indicating
Functional Description adjacent (downstream) empty cell is that the FIFO is completely full (Input
The 3341 is a 64-word x 4-bit First-In automatic, activated by an on-chip con- Ready stays LOW for at least tBT) or
First-Out (FIFO) Serial Memory. The trol. Thus, data will stack up at the end completely empty (Output Ready stays
inputs and outputs are completely inde- of the device while empty locations will LOW for at least tBT)'
pendent (no common clocks) making "bubble" to the front. tBT defines the Reset
the 3341 ideal for asynchronous buffer time required for the first data to travel
applications. from the input to the output of a previ- When Master Reset (MR) goes LOW,
ously empty device, or for the first the control logic is cleared, and the
Control signals are provided for both data outputs enter a LOW state. When
empty space to travel from the output
vertical and horizontal expansion. MR returns HIGH, Output Ready
to the input of a previously full device.
The 3341 is manufactured using Cy- (OR) stays LOW, and Input Ready
press CMOS technology and is avail- Data Output (IR) goes HIGH if Shift In (SI) was
able in both ceramic and plastic pack- When data has been transferred into LOW.
ages. the last cell, Output Ready (OR) goes
SI
WRITE POINTER VGG* Vss
IR
IR so
WRITE MULTIPLEXER
51 OR
DO Co
MEMORY Co 01 Ql
ARRAY 01
Q2 O2 02
03 03 03
Voo MR
0004-2
so *Internally not connected
READ POINTER
OR
0004-1
Selection Guide
3341 33412
Maximum Operating Frequency 1.2 MHz 2.0 MHz
5-19
~ CY3341
~~~NDUcrOR====================================================================
Maximum Ratings
Storage Temperature .... '" ........ -65C to + 150C Static Discharge Voltage ..................... >2oo1V
(Pin 16 to Pin 8) ..................... -0.5V to + 7.0V Operating Range
Range Vss VDD VGG*
in High Z State ..... , ................ -0.5V to +7.0V Temperature
DC Input Voltage ................... -3.0Vto +7.0V Commercial OCto +70C 5V 1O% GND NC
Output Current, into Outputs (Low) ............. 20 rnA Military [3] - 55C to + 125C 5V 1O% GND NC
*Intemally Not Connected.

VOH Output HIGH Voltage Vss = Min.,IOH = -0.3 rnA 2.4 V
VOL Output LOW Voltage Vss = Min.,IOL = 1.6 rnA 0.4 V
VIH Input HIGH Voltage 2.0 VSS V
IIX Input Leakage Current VDD ~ VI ~ Vss -10 +10 p"A
Output Short
lOS Vss = Max., VOUT = VDD -90 rnA
Circuit Current[1]
IDD Power Supply Current

Vss = Max.,
lOUT = OmA
l Commercial 45
rnA
1 Military 60
IGG VGGCurrent 0 rnA
Capacitance [2]
pF
CoUT Output Capacitance Vss = 5.0V 10
Notes:

ALL INPUT PULSES
R12.42 Kn
3.0 V -----.i-""!""'---""""'"
OUTPUT~----'-------~
GND
30 pF R2 10 ns 10 ns
I-=
3.28 KH 0004-5
INCLUDING
JIG AND
SCOPE -=-
0004-3
Equivalent to:
THEVENIN EQUIVALENT
1.05 Kn
OUTPUT ~ 2.08 V
0004-4
5-20
~crPRFSS CY3341
.nEMICONDUCTOR ===================================================================
Parameters
Test 3341 3341-2
Description Units
Conditions Min. Max. Min. Max.
fMAX Operating Frequency Note 6 1.2 2 MHz
tpHSI SIHIGHTime 80 80 ns
tPLSI SILOWTime 80 80 ns
tDD Data Setup to SI 0 0 ns
tHSI Data Hold from SI 200 100 ns
tIR+ Delay, SI HIGH to IR LOW 20 350 20 160 ns
tIR- Delay, SI LOW to IR HIGH 20 450 20 200 ns
tPHSO SO HIGH Time 80 80 ns
tPLSO SO LOW Time 80 80 ns
tOR + Delay, SO HIGH to OR LOW 20 370 20 160 ns
tOR- Delay, SO LOW to OR HIGH 20 450 20 200 ns
tDA Data Setup to OR HIGH 0 0 ns
tDH Data Hold from OR LOW 75 20 ns
tBT Bubble through Time 1000 500 ns
tMRW MR Pulse Width 400 200 ns
tDSI MR HIGH to SI HIGH 30 30 ns
tDOR MR LOW to OR LOW 400 200 ns
tDIR MR LOW to IR HIGH 400 200 ns
Notes:
5. Test conditions assume signal transitions of 10 ns or less. Timing 6. l/fMAX > tpHSI + tIR -, l/fMAX > tpHSO + tOR - .
reference levels of 1.5V and output loading of the specified IorJ10H
and 30 pF load capacitance.
Switching Waveforms
Data In Timing Diagram
- - - - -.......-----l/fMAX-----~
SHIFT IN
INPUT READY
DATA INPUT ~ ___xxxxxxxx___

0004-6
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUTPUT
0004-7
5-21
~ CY3341
~~~NDUcroR ~================================================================
Master Reset Timing Diagram
tMRW .
MASTER RESET ~~ ..,{
\. I
tOIR
INPUT READY
}~
toOR
OUTPUT READY
\~
. tOSI
SHIFT IN
_ _ _- - - - J
1.
t
DATA OUTPUT
\ 0004-8
Ordering Code Package Operating Ordering Code Package Operating
(l.2MHz) Type Range (2 MHz) Type Range
CY334lPC PI CY3341-2PC PI
Commercial Commercial
CY334lDC D2 CY3341-2DC D2
CY3341DMB D2 Military CY3341-2DMB D2 Military
5-22
~ CY3341
~~~~~UcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
,.
IIX 1,2,3
100 1,2,3
fMAX 7,8,9,10,11
tPHSI 7,8,9,10,11
tpLSI 7,8,9,10,11
too 7,8,9,10,11
tHSI 7,8,9,10,11
tIR+ 7,8,9,10,11
tIR- 7,8,9,10,11
tPHSO 7,8,9,10,11
tPLSO 7,8,9,10,11
tOR+ 7,8,9,10,11
tOR- 7,8,9,10,11
tOA 7,8,9,10,11
tOH 7,8,9,10,11
tBT 7,8,9,10,11
tMRW 7,8,9,10,11
tOSI 7,8,9,10,11
tOOR 7,8,9,10,11
tDIR 7,8,9,10,11
5-23
CY7C401/CY7C403
CY7C402/CY7C404
CYPRESS
SEMICONDUCTOR Cascadeable 64 X 4 FIFO and
64 x 5 FIFO
Features
64 x 4 (CY7C401 and CY7C403) Pin compatible with MMI Output Ready (OR) signal is a flag to
64 x 5 (CY7C402 and CY7C404) 67401A/67402A indicate the output contains valid data
High speed first-in first-out (HIGH), to indicate the FIFO is empty
memory (FIFO) Functional Description (LOW), and to provide a signal for cas-
Processed with high-speed The CY7C401 and CY7C403 are asyn- cading.
CMOS for optimum chronous first-in first-out memories Parallel expansion for wider words is
speed/power (FIFOs) organized as 64 four bit accomplished by logically ANDing the
words. The CY7C402 and CY7C404 Input Ready (IR) and Output Ready
25 MHz data rates
are similar FIFOs organized as 64 five (OR) signals to form composite signals.
50 ns bubble-through time- bit words. Both the CY7C403 and
25 MHz Serial expansion is accomplished by ty-
CY7C404 have an Output Enable (OE)
ing the data inputs of one device to the
Expandable in word width function.
data outputs of the previous device.
and/or length The devices accept 4/5 bit words at the The Input Ready (IR) pin of the receiv-
5 volt power supply 10% data input (DIo-DIn) under the con- ing device is connected to the Shift Out
tolerance both commercial and trol of the Shift In (SI) input. The (SO) pin of the sending device, and the
military stored words stack up at the output Output Ready (OR) pin ofthe sending
(DOo-DOn) in the order they were en- device is connected to the Shift In (SI)
Independent asynchronous inputs tered. A read command on the Shift pin of the receiving device.
and outputs Out (SO) input causes the next to last
Reading and writing operations are
TIL compatible interface word to move to the output and all
completely asynchronous, allowing the
data shifts down once in the stack. The
Output enable function available FIFO to be used as a buffer between
Input Ready (IR) signal acts as a flag
on CY7C403 and CY7C404 two digital machines of widely differing
to indicate when the input is ready to
operating frequencies. The 25 MHz op-
Capable of withstanding greater accept new data (HIGH), to indicate
than 2001 V electrostatic eration makes these FIFOs ideal for
when the FIFO is full (LOW), and to
high speed communication and con-
discharge provide a signal for cascading. The
troller applications.

CY7C401 NC CY7C402~
CY7C403i5'E Vee Vcc
SI CY7C4040E
WRITE POINTER IR so IR SO
IR
[(JE) SI OR SI OR
WRITE MULTIPLEXER
010 000 010 000
01, DO, 01, DO,
000 01 2 002
MEMORY
DO, 0 12 002
ARRAY
002 0 13 003 0 13 003
003
(004) GND ;;m 0 14 004
0014-2 GNO ~
I'"
~>~5!
SO 0014-3
READ POINTER
( ) 7C402. 7C404 !il II!
'"
~ >~5!
OR
[ I 7C403. 7C404 !il II!
0014-1 51 NC
3212019
DID OR
51 18 OR
011 DOD
01 2 DID 17 DOD
001 7C402
6
NC 00 2 011 7C404 16 001
01 2 15 00 2
01 3 14 00 3
i5"'~118"'!il 0014-16
9 10111213
i5ot~118ot~
0014-17
Selection Guide
7C401/25 7C40XIO 7C40X15 7C40X25
Maximum Shift Rate (MHz) 5 10 15 25
Current (rnA) Military - 90 90 90
S-24
CY7C401/CY7C403
(in~~NDUcrOR =====================================================================
CY7C402/CY7C404
Maximum Ratings
Storage Temperature ...... " ....... -65C to + 150"C Static Discharge Voltage ............ , ........ >2oo1V
Ambient
Vee
Temperature
Power Dissipation ............................. 1.0W Commercial OC to +700C 5V 1O%

7C40X-IO, 15,25
Min. Max.
VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 V
IIX Input Leakage Current GND::;: VI::;: Vee -10 +10 /LA
VeD[1] Input Diode Clamp Voltage[l]
GND ::;: VOUT ::;: Vee, Vee = S.SV
loz Output Leakage Current
Output Disabled (CY7C403 and CY7C404)
-so +50 /LA
lOS Output Short Circuit Current[2] Vee = Max., VOUT = GND -90 rnA

Vee = Max., I Commercial 75 rnA
lOUT = OmA I Military 90 rnA
Capacitance [5]
CIN Input Capacitance T A = 2SoC, f = 1 MHz 5
pF
Notes:
1. The eMOS process does not provide a clamp diode. However, the 3. TA is the "instant on" case temperature.
FIFO is insensitive to - 3V dc input levels and - SV undershoot 4. See the last page of this specification for Group A subgroup testing
pulses of less than 10 ns (measured at 50% point). information.
Note:
For more information onFIFOs, please refer to the FIFO Application Brief in the Appendix of this book.
5-25
CY7C401/CY7C403
(;n~~NDUcrOR =====================================================================
.. CY7C402/CY7C404

R14370 ALL INPUT PULSES
R14370
5 V C>----.A,/<\/\,---. 5Vo----~~~ 3.0 V----ir.:~---""'_
OUTPUTo---P----+ OUTPUT 0---,....----+
GND
R2
30pF 5 pF ~~20 .;5"1
I I
2720
,NCLUD,NG 0014-5
,NCLUD,NG
JIG AND _ JIG AND _
-::- SCOPE -::- - SCOPE -
0014-4
Figure 1a Figure 1b
16m
OUTPUT O--~"II'''II'-''.---O 1.73V
0014-6

7C401-5
Test 7C40X-IO 7C40X-15 7C40X-25 [12]
Parameters Description 7C402-5 Units
Conditions
fo Operating Frequency Note 7 5 10 15 25 MHz
tpHSI SI HIGH Time 20 20 20 11 ns
tPLSI SILOWTime 45 30 25 20 ns
tSSI Data Setup to SI NoteS 0 0 0 0 ns
tHSI Data Hold from SI NoteS 60 40 30 20 ns
tOLIR Delay, SI HIGH to IR LOW 75 40 35 21/22 ns
tOHIR Delay, SI LOW to IR HIGH 75 45 40 2S/30 ns
tpHSO SO HIGH Time 20 20 20 11 ns
tpLSO SO LOW Time 45 25 25 20 ns
tOLOR Delay, SO HIGH to OR LOW 75 40 35 19/21 ns
tOHOR Delay, SO LOW to OR HIGH SO 55 40 34/37 ns
tSOR Data Setup to OR HIGH 0 0 0 0 ns
tHSO Data Hold from SO LOW 5 5 5 5 ns
tBT Bubble through Time 200 10 95 10 65 10 50/60 ns
tSIR Data Setup to IR Note 9 5 5 5 5 ns
tHiR Data Hold from IR Note 9 30 30 30 20 ns
tpIR Input Ready Pulse HIGH 20 20 20 15 ns
tpOR Output Ready Pulse HIGH 20 20 20 15 ns
tpMR MR Pulse Width 40 30 25 25 ns
tOSI MR HIGH to SI HIGH 40 35 25 10 ns
tnoR MR LOW to OR LOW S5 40 35 35 ns
tDiR MR LOW to IR HIGH S5 40 35 35 ns
tLZMR MR LOW to Output LOW Note 10 50 40 35 25 ns
tooE Output Valid from OE LOW - 35 30 20 ns
tHZOE Output HIGH-Z from OE HIGH Note 11 - 30 25 15 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing 10. All data outputs will be at LOW level after reset goes high until data
reference levels of 1.5V and output loading of the specified IoUIOH is entered into the FIFO.
and 30 pF load capacitance, as in Figure 1Q. 11. HIGH-Z transitions are referenced to the steady-state VOH -500
7. I/fo > tpHSI + tOHIR,l/fO > tpHSO + tOHOR m V and VOL + 500 m V levels on the output. tHZOE is tested with 5
S. tSSI and tHSI apply when memory is not full. pF load capacitance as in Figure lb.
9. tSIR and tHiR apply when memory is full, SI is high and minimum 12. CommerciallMilitary
bubble through (tBT) conditions exist.
5-26
CY7C401/CY7C403
5n~~tDUcrOR ======================================================================= CY7C402/CY7C404
Operational Description
CONCEPT ified in a Datasheet, but necessary for reliable operation
Unlike traditional FIFOs these devices are designed using a under all conditions.
dual port memory, read and write pointer, and control log- When an empty FIFO is filled with initial information, at
ic. The read and write pointers are incremented by the maximum "shift in" SI frequency, followed by immediate
Shift Out (SO) and Shift In (SI) respectively. The availabil- shifting out of the data also at maximum "shift out" SO
ity of an empty space to shift in data is indicated by the frequency, the designer must be aware ofa window oftime
Input Ready (IR) signal, while the presence of data at the which follows the initial rising edge of the "output Ready"
output is indicated by the Output Ready (OR) signal. The OR signal during which the SO signal is not recoginized.
conventional concept of bubble through is absent. Instead, This condition exists only at high speed operation where
the delay for input data to appear at the output is the time more than one SO may be generated inside the prohibited
required to move a pointer and propagate an Output Ready window. This condition does not inhibit the operation of
(OR) signal. The Output Enable (OE) signal provides the the FIFO at full frequency operation, but rather delays the
capability to OR tie multiple FIFOs together on a common full 25 MHz operation until after the window has passed.
bus. There are several implementation techniques to manage the
RESETTING THE FIFO window so that all SO signals are recognized:
Upon power up, the FIFO must be reset with a Master 1. The first involves delaying SO operation such that it
Reset (MR) signal. This causes the FIFO to enter an empty does not occur in the critical window. This can be ac-
condition signified by the Output Ready (OR) signal being complished by causing a fixed delay of 40 ns "initiated
LOW at the same time the Input Ready (IR) signal is by the SI signal only when the FIFO is empty" to inhibit
HIGH. In this condition, the data outputs DOo-DOn) will or gate the SO activity. This however requires that the
be in a LOW state. SO operation at least temporarily be synchronized with
SHIFTING DATA IN the input SI operation. In synchronous applications this
may well be possible and a valid solution.
Data is shifted in on the rising edge of the Shift In (SI)
signal. This loads input data into the first word location of 2. Another solution not uncommon in synchronous appli-
the FIFO. On the falling edge of the Shift In (SI) signal, cations is to only begin shifting data out of the FIFO
the write pointer is moved to the next word position and when it is greater than half full. This is a common meth-
the Input Ready (IR) signal goes HIGH indicating the od of FIFO application, as earlier FIFOs could not be
readiness to accept new data. If the FIFO is full, the Input operated at maximum frequency when near full or emp-
Ready (IR) will remain LOW until a word of data is shift- ty. Although Cypress FIFOs do not have this limitation,
ed out. any system designed in this manner will not encounter
the window condition described above.
SHIFTING DATA OUT
3. The window may also be managed by not allowing the
Data is shifted out of the FIFO on the falling edge of the
first SO signal to occur until the window in question has
Shift Out (SO) signal. This causes the internal read pointer
to be advanced to the next word location. If data is present, passed. This can be accomplished by delaying the SO
40 ns from the rising edge of the initial OR "output
valid data will appear on the outputs and the Output
Ready (OR) signal will go HIGH. If data is not present, ready" signal. This however involves the requirement
that this only occurs on the first occurance of data being
the Output Ready (OR) signal will stay LOW indicating
loaded into the FIFO from an empty condition and
the FIFO is empty. Upon the rising edge of Shift Out (SO),
therefore requires the knowledge of "input ready" IR
the Output Ready (OR) signal goes LOW. The data out-
puts of the FIFO should be sampled with edge sensitive and SI conditions as well as SO.
type D flip-flop (or equivalent), using the SO signal as the 4. Handshaking with the OR signal can be a third method
clock input to the flip-flop. of avoiding the window in question. With this technique
the rising edge of SO, or the fact that the SO signal is
BUBBLE THROUGH
HIGH, will cause the OR signal to go LOW. The SO
Two bubble through conditions exist. The first is when the signal is not taken low again, advancing the internal
device is empty. After a word is shifted into an empty de- pointer to the next data, until the OR signal goes LOW.
vice, the data propagates to the output. After a delay, the This assures that the SO pulse that is initiated in the
Output Ready (OR) flag goes HIGH indicating valid data window will be automatically extended sufficient time to
at the output. be recognized.
The second bubble through condition occurs when the de- 5. There remains the decision as to what signal will be used
vice is full. Shifting data out creates an empty location to latch the data from the output of the FIFO into the
which propagates to the input. After a delay, the Input receiving source. The leading edge of the SO signal is
Ready (IR) flag goes HIGH. If the Shift In (SI) signal is most appropriate because data is guaranteed to be stable
HIGH at this time, data on the input will be shifted in. prior to and after the SO leading edge for each FIFO.
APPLICATION OF THE 7C403-25/7C404-25 This is a solution for any number of FIFOs in paralle1.
AT 25 MHz Any of the above solutions will provide a solution for cor-
Application of the CY7C403 or CY7C404 Cypress CMOS rect operation of a Cypress FIFO at 25 MHz. The specific
FIFO's requires attention to characteristics not easily spec- implementation is left to the designer and dependent on the
specific application needs.
5-27
CY7C401/CY7C403
(iA~~UcrOR===================================================================== CY7C402/CY7C404 I
Switching Waveforms
....- - - - - - I / F O > - - - - - - " * o - - - - - - - I / F O - - - - - - - . !
SHIFT IN
INPUT READY
DATA IN
0014-7

14-----I/FO------+Io_----I/FO-----~
SHIFT OUT
OUTPUT READY
DATA OUT
0014-8
Bubble Through, Data Out To Data In Diagram
SHIFT OUT --.I~t-----.,

SHIFTIN ~ \"'_ _ _ _ __
14----tBT'-----.1
INPUTAEADY
DATA IN
0014-9
Note:
Interfacing to the FIFO-
Please refer to the Interfacing to the FIFO applications brief in the Applications Section at the back of this data book.
5-28
CY7C401/CY7C403
(in . CYPRESS
SEMICONDUCTOR
CY7C402/CY7C404
==================================================================
Bubble Through, Data In To Data Out Diagram
S~"~ ~~~~~
...,,""' ~
14!.,----tBT------+---
OUTPUT READY
DATA OUT
0014-10

I--- tPMA----.i
MASTER REset ~k- )"1-

1\
tOIR
INPUT READY
)
tOOR
OUTPUT READY
)
tOSI
I
SHIFT IN
j.I.---tLZMR---.j~
t
DATA OUT
0014-11
Output Enable Timing Diagram
OUTPUT ENABLE _ _ _ _ _ _ _ _ 4_:...,._zO-'ll}; l~,={--------_-

DATA OUT - -
NOTE 9
0014-12
5-29
CY7C401/CY7C403
(iA
... CY7C402/CY7C404
~ ~DUcrOR =====================================================================
1.2 r~--r--";~"";;';;::':';;';"';";;;;'----' 1.4,..-----,....-------, 60
;(
! 50
"
"'"
l- Vee =5.0V
1.0 r--1---+--~---4 ~ 1.2 ll! TA a 25'C
w
a: 40
a:
fa
N
;)
to)
0.8 t---t----7G----+--~ :::; w 30
to)
~
a:
a:
;)
51 20
~
i ,,~
~
A-
Vee -5.5V 10
~
'"
VIN -5.0V 0
0.6'--_ _ _ _'--_ _ _ _---'
0.4L:-_--:-'=--_~--~-~ o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0

SUPPLY VOLTAGE
VS. vs. AMBIENT TEMPERATURE vs OUTPUT VOLTAGE
1.3 1.6 140
;( 120
> 1.2 >
!
".". ~
(J ~ 1.41-------1t-------4
z
III III I-
100
--- -
2
~
0 1.1 5 w
a:
fI'"
III
a:: ~ 1.2po..o::----t-------4 a:
::J 80
/
'0"' ""o
III
1.0
~ III
to)
~ /
~
N ~ 1.0t----~ioIo:::--------1 2 60
:::; Vee =6.0 V
cI:
:liE
a::
0.9 c(
lI!
a:
iii
I-
::J 40
/ TA "25C
0
Z 0.8 i 0.8 t - - - - - 1 I - - - - - - - - - 1 ~0 20
/
0.7 0.6'------''-----~ o
V
4.0 4.5 5.0 5.5 6.0 -55 26 126 0.0 1.0 2.0 3.0 4.0
TYPICAL FREQUENCY CHANGE NORMALIZED Icc

vs. OUTPUT LOADING 1.1 vs FREQUENCY
1.6
>
to)
2
w
::J
0
w
1.5
1.4
~/ --- ~
0
1.0
0.9 /
~
/
If .IV w
faN
1.3
N
:::;
/'
:::;
c( 1.2
/ ~
a:
i
0.8
V
:E
a:
0
2 1.1
/ 0.7
/
1.0
o
/ 200 400 600 800 1000 o 0 6 10 16 20 26 30 36
CAPACITANCE (pFI FREQUENCY (MHz)

0014-13
5-30
~~~~NDUcrOR=======================================================================
CY7C401/CY7C403
CY7C402/CY7C404
FIFO Expansion
128 x 4 Application
SHIFT IN OR SI OR OUTPUT READV

INPUT READY SO IR so SHIFT OUT
000 01 0 000
001 011 001

} DATA OUT
002 01 2
003 01 3 Wi 003
MAo-----___ -----------..I 0014-14
FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
192 x 12 Application
SHIFT OUT
IR so IR so IR SO
,......-- SI OR SI OR SI OR
- 01 0 000 01 0 000 01 0 000 ~
- 01, DO, 01, DO, 01, DO, -
- 0 12 002 01 2 002 01 2 002 -
- 0 13 ;;m 003 01 3 ;;m 003 D13;;m 003 -
COMPOSITE Y r y
INPUT READY COMPOSITE
,-,..- IR SO IR SO IR SO I - -
OUTPUT READY
~ ~
~SI OR SI OR SI OR
~
- 01 0 000 01 0 000 01 0 000 ~
- 01, DO, DI, DO, 01, 001 r-
- 01 2 002 01 2 002 01 2 002 r
- 01 3 IWR D0 3 01 3 ;;m D03 01 3 MA 003 r-
'( 1 1
SHIFT IN
IR so IR so IR so r---
SI OR SI OR SI OR
- 01 0 000 01 0 000 01 0 000 r-
- 01, DO, 01, DO, 01, DO, ~
- 01 2 002 01 2 002 01 2 002 r-
- 01 3 MA D03 01 3 MJi D0 3 01 3 ;;m 003 r-
'( 'i Y MR
0014-15
FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and Output
Ready flags. This need is due to the variation of delays of the FIFOs.
User Notes:
I. When the memory is empty the last word read will remain on the 4. When the master reset is brought LOW, the outputs are cleared to
outputs until the master reset is strobed or a new data word bubbles LOW, IR goes HIGH and OR goes LOW. IfSI is HIGH when the
through to the output. However, OR will remain LOW, indicating master reset goes HIGH then the data on the inputs will be written
data at the output is not valid. into the memory and IR will return to the LOW state until SI is
2. When the output data changes as a result of a pulse on SO, the OR brought LOW. If SI is LOW when the master reset is ended, then IR
signal always goes LOW before there is any change in output data and will go HIGH, but the data on the inputs will not enter the memory
stays LOW until the new data has appeared on the outputs. Anytime until SI goes HIGH.
OR is HIGH, there is valid stable data on the outputs. 5. All Cypress FIFOs will cascade with other Cypress FIFOs. However,
3. If SO is held HIGH while the memory is empty and a word is written they may not cascade with pin-compatible FIFO's from other manu-
into the input, that word will ripple through the memory to the out- facturers.
put. OR will go HIGH for one internal cycle (at least tORd and then
go back LOW again. The stored word will remain on the outputs. If
more words are written into the FIFO, they will line up behind the
first word and will not appear on the outputs until SO has been
brought LOW.
5-31
CY7C401/CY7C403
WA~~UaoR==============================================================
. CY7C402/CY7C404
Ordering Code Package Operating Ordering Code Package Operating Ordering Code Package Operating
(25 MHz) Type Range (15 MHz) Type Range (10 MHz) Type Range
CY7C40I-2SPC PI Com. CY7C40I-ISPC PI Com. CY7C40I-lOPC PI Com.
CY7C402-2SPC P3 CY7C402-ISPC P3 CY7C402-10PC P3
CY7C403-2SPC PI CY7C403-ISPC PI CY7C403-10PC PI
CY7C404-2SPC P3 CY7C404-ISPC P3 CY7C404-lOPC P3
CY7C40I-2SDC D2 CY7C40I-ISDC D2 CY7C40I-10DC D2
CY7C402-2SDC D4 CY7C402-ISDC D4 CY7C402-10DC D4
CY7C403-2SDC D2 CY7C403-ISDC D2 CY7C403-lODC D2
CY7C404-2SDC D4 CY7C404-ISDC D4 CY7C404-10DC D4
CY7C40I-2SLC L6I CY7C40I-ISLC L6I CY7C40I-lOLC L6I
CY7C402-2SLC L6I CY7C402-ISLC L6I CY7C402-10LC L6I
CY7C403-2SLC L6I CY7C403-ISLC L6I CY7C403-lOLC L6I
CY7C404-2SLC L6I CY7C404-ISLC L6I CY7C404-lOLC L6I
CY7C40I-2SDMB D2 Mil. CY7C40I-ISDMB D2 Mil. CY7C40I-10DMB D2 Mil.
CY7C402-2SDMB D4 CY7C402-ISDMB D4 CY7C402-lODMB D4
CY7C403-2SDMB D2 CY7C403-ISDMB D2 CY7C403-lODMB D2
CY7C404-25DMB D4 CY7C404-ISDMB D4 CY7C404-10DMB D4
CY7C40I-25LMB L6I CY7C40I-ISLMB L6I CY7C40I-10LMB L6I
CY7C402-25LMB L6I CY7C402-ISLMB L6I CY7C402-lOLMB L6I
CY7C403-25LMB L6I CY7C403-ISLMB L6I CY7C403-lOLMB L6I
CY7C404-25LMB L6I CY7C404-ISLMB L6I CY7C404-10LMB L6I

(5 MHz) Type Range
CY7C40I-SPC PI Com.
CY7C402-SPC P3
5-32
CY7C401/CY7C403
5J] . CYPRESS CY7C402/CY7C404
s~~O~UcrOR==============================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
los 1,2,3
Icc 1,2,3
fo 7,8,9,10,11 tOOE 7,8,9,10,11
tpHSI 7,8,9,10,11 tHzOE 7,8,9,10,11
tpLSI 7,8,9,10,11
tSSI 7,8,9,10,11
tHSI 7,8,9,10,11
tOLIR 7,8,9,10,11
tOHIR 7,8,9,10,11
tpHSO 7,8,9,10,11
tpLSO 7,8,9,10,11
tOLOR 7,8,9,10,11
tOHOR 7,8,9,10,11
tSOR 7,8,9,10,11
tHSO 7,8,9,10,11
tBT 7,8,9,10,11
tSIR 7,8,9,10,11
tHIR 7,8,9,10,11
tpIR 7,8,9,10,11
tPOR 7,8,9,10,11
tpMR 7,8,9,10,11
tOSI 7,8,9,10,11
tOOR 7,8,9,10,11
tDIR 7,8,9,10,11
tLZMR 7,8,9,10,11
Document #: 38-00040-0
5-33
CY7C408A
CY7C409A
CYPRESS
SEMICONDUCTOR Cascadeable 64 X 8 FIFO
Cascadeable 64 X 9 FIFO
Features
64 x S and 64 x 9 first-in first- AFE is HIGH when the FIFO is al- more data (IR HIGH) or are ready to
out (FIFO) buffer memory most full or almost empty, otherwise output data (OR HIGH) and thus
35 MHz shift-in and shift-out AFE is LOW. HF is HIGH when the compensate for variations in propaga-
rates FIFO is half full, otherwise HF is tion delay times between devices.
LOW. Serial expansion (cascading) for deeper
Almost FuUI Almost Empty and
Half Full flags The CY7C408A has an Output Enable buffer memories is accomplished by
(OE) function. connecting the data outputs of the
Dual port RAM architecture
The memory accepts 8- or 9-bit parallel FIFO closest to the data source (up-
Fast, 50 ns, bubblethrough words at its inputs (010-018) under stream device) to the data inputs of the
Independent asynchronous inputs the control of the Shift-In (SI) input following (downstream) FIFO (Figure
and outputs when the Input-Ready (IR) control sig- 6). In addition, to insure proper opera-
Output Enable (CY7C40SA) nal is HIGH. The data is output, in the tion, the SO signal of the upstream
same order as it was stored, on the FIFO must be connected to the IR out-
Expandable in word width and put of the downstream FIFO and the
FIFO depth 000-008 output pins under the con-
trol of the Shift-Out (SO) input when SI signal of the downstream FIFO
5V 10% supply the Output-Ready (OR) control signal must be connected to the OR output of
TTL compatible is HIGH. If the FIFO is full (IR the upstream FIFO. In this serial ex-
LOW), pulses at the SI input are ig- pansion configuration, the IR and OR
Capable of withstanding greater signals are used to pass data through
than 2000V electrostatic nored: ifthe FIFO is empty (OR
LOW), pulses at the SO input are ig- the FIFOs.
discharge voltage
nored. Reading and writing operations are
300 mil, 2S-pin DIP
The IR and OR signals are also used to completely asynchronous, allowing the
Functional Description connect the FIFO's in parallel to make FIFO to be used as a buffer between
a wider word, or in series to make a two digital machines of widely differing
The CY7C408A and CY7C409A are operating frequencies. The high shift-in
64-word deep by 8- or 9-bit wide first- deeper buffer, or both.
Parallel expansion for wider words is and shift-out rates of these FIFOs, and
in first-out (FIFO) buffer memories. In their high throughput rate due to the
addition to the industry standard hand- implemented by logically ANDing the
IR and OR outputs (respectively) of fast bubblethrough time, which is due
shaking signals, Almost FulllAlmost to their dual port RAM architecture,
Empty (AFE) and Half Full (HF) flags the individual FIFOs together (Figure
7). The AND operation insures that all make them ideal for high speed com-
are provided. munications and controllers.
of the FIFOs are either ready to accept

ArE 1
WRITE POINTER Hr
AFE IR 50
SI
51
IR WRITE MULTIPLEXER HF
Dig DOg
DO,
GNO
D?0
00 2
~10 MEMORY
ARRAY 007
01 7
(7C409A) Dis DOs (7C409A) 015
Dis
0E(7C40SA)
01 7
READ MULTIPLEXER
7C408A NC
OR 7C409A 018
MR
READ POINTER SO 0065-2
Vi ef ~ $ ~I~ ~
0065-1 Dig 5 4 3 2 fil28 27 2~5 OR
Flag Definitions 01, 24 DOg

GNo 23 DO,
HF AFE Words Stored 01 2 8 ~g!g~~ 22 GNo
013 9 21 00 2
L H 0-8 01. 10 20 003
L L 9-31 015 '''2'314'5'6'7,i9 DO.
H L 32-55
H H 56-64 0065-3
5-34
CY7C408A
511~~NDUcrOR =======================================================================
..
Selection Guide
CY7C409A
7C408A15 7C408A25 7C408A35

7C409A15 7C409A25 7C409A35
Maximum Shift Rate (MHz) 15 25 35
Current (mA)!2]
Military 140 150 N/A
Maximum Ratings
Storage Temperature ............... -65C to + 150C Static Discharge Voltage ....... , ............. >2001V
Ambient Temperature with (per MILSTD883 Method 3015)
Operating Range

Ambient
DC Voltage Applied to Outputs Range
Temperature Vee
in High Z State (7C408A) ............. -0.5V to + 7.0V
Commercial OC to + 70C 5V 1O%
Military!4] - 55C to + 125C 5V 1O%
Power Dissipation ............................. 1.0W
Output Current, into Outputs (Low) ............. 20 rnA
CY7C408A
Parameters Description Test Conditions CY7C409A Units
Min. Max.
VOR Output HIGH Voltage Vee = Min., lOR = -4.0mA 2.4 V
VOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 V
IIX Input Leakage Current GND::;; VI::;; Vee -10 +10 p,A
los Output Short Circuit Current!l] Vee = Max., VOUT = GND -90 mA
Vee = Max., lOUT = 0 mA Commercial 100 mA
leeQ Quiescent Power Supply Current
VIN ::;; VIL, VIN ~ VIR Military 125 mA
ICC Power Supply Current Icc = leCo + 1 mA/MHz X (fSI + fso)/2
Capacitance [3]
pF
Notes:
2. Icc = ICCQ + 1 rnA/MHz X (fSI + fso)/2 4. T A is the "instant on" case temperature.
S. See the last page of this specification for Group A subgroup testing
information.
AC Test Load and Waveforms
5V
5V:j
u
R1 482.0. R1 482.0.
3.0 V---~~---!IL
OUTPUT OUTPUT
GND
CL I 30 pF ~~6.n 5 pF ~~6.n
-= INCLUDING
JIG AND -= I-= INCLUDING
JIG AND -= Figure 2. All Input Pulses
0065-5
SCOPE SCOPE
0065-4 0065-21
Figure 1a Figure 1b
16m
OUTPUT o--~,"'v"'.--o 1.73 V
0065-6
CY7C408A
5A ~~NDUcrOR =======================================================================
CY7C409A

CY7C408A-15 CY7C408A-25 CY7C408A-35
Test
Parameters Description CY7C409A-15 CY7C409A-25 CY7C409A-35 Units
Conditions
fo Operating Frequency Note 7 15 25 35 MHz
tpHSI SIHIGHTime Note 7 23 11 9 ns
tpLSI SILOWTime Note 7 25 24 17 ns
tSSI Data Setup to SI Note 8 0 0 0 ns
tRSI Data Hold from SI Note 8 30 20 12 ns
tDLIR Delay, SI HIGH to IR LOW 35 21 15 ns
tDHIR Delay, SI LOW to IR HIGH 40 23 16 ns
tpHSO SO HIGH Time Note 7 23 11 9 ns
tPLSO SO LOW Time Note 7 25 24 17 ns
tDLOR Delay, SO HIGH to OR LOW 35 21 15 ns
tDHOR Delay, SO LOW to OR HIGH 40 23 16 ns
tSOR Data Setup to OR HIGH 0 0 0 ns
tHSO Data Hold from SO LOW 0 0 0 ns
tBT Fallthrough, Bubbleback Time 10 65 10 60 10 50 ns
tSIR Data Setup to IR Note 9 5 5 5 ns
tHIR Data Hold from IR Note 9 30 20 20 ns
tpIR Input Ready Pulse HIGH Note 10 6 6 6 ns
tpOR Output Ready Pulse HIGH Note 11 6 6 6 ns
tDLZOE OE LOW to LOW Z (7C408) Note 12 35 30 25 ns
tDHZOE OE HIGH to HIGH Z (7C408) Note 12 35 30 25 ns
tDHHF SI LOW to HF HIGH 65 55 45 ns
tDLHF SO LOW to HF LOW 65 55 45 ns
tDLAFE SO or SI LOW to AFE LOW 65 55 45 ns
tDHAFE SO or SI LOW to AFE HIGH 65 55 45 ns
tpMR MR Pulse Width 55 45 35 ns
tDSI MR HIGH to SI HIGH 25 10 10 ns
tDOR MR LOW to OR LOW 55 45 35 ns
tDlR MR LOW to IR HIGH 55 45 35 ns
tLzMR MR LOW to Output LOW Note 13 55 45 35 ns
tAFE MR LOW to AFE HIGH 55 45 35 ns
tHF MR LOW to HF LOW 55 45 35 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing 11 At any given operating condition tpOR ~ (tPHSI required).
reference levels of 1.5Y and output loading ofthe specified loy/IOH 12. tOHZOE and tOLZOE are specified with CL = 5 pF as in Figure 1h.
and 30 pF load capacitance, as in Figure 1. tOHZOE transition is measured 500 mY from steady state voltage.
7. lifo ~ (tPHSI + tpLSI), lifo ~ (tPHSO + tPLSO) tOLZOE transition is measured 100 mY from steady state voltage.
8. tSSI and tHSI apply when memory is not full. These parameters are guaranteed and not 100% tested.
9. tSIR and tHIR apply when memory is full, SI is HIGH and minimum 13. All data outputs will be at LOW level after reset goes HIGH until
bubblethrough (tBT) conditions exist. data is entered into the FIFO.
10. At any given operating condition tpIR ~ (tPHSO required).
Ifm CYPRESS
SEMICONDUcroR
CY7C408A
CY7C409A
Switching Waveforms
SHIFT IN
INPUT READY
DATA IN
III
AFE
HF
(LOW)
0065-7
<D FIFO Contains 8 Words

lIFO lIFO
SHIFT OUT
OUTPUT READY
DATA OUT
HF
(LOW)
AFE
FIFO Contains 9 Words

-,F 0065-8
5-37
CY7C408A
~~UCTI)R CY7C409A IIII

t - - - - - - - I / F O - - - - - - _.....- -_ _ _ _ I/FO _ _ _ _ _ _- I
SHIFT IN
INPUT READY
DATA IN
AFE
(LOW)
HF
0065-14
~ FIFO Contains 31 Words
!4------I/FO--------.j.+------I/FO------l
SHIFT OUT
\'----
OUTPUT READY
DATA OUT
HF
AFE
(LOW)
0065-15
@ FIFO Contains 32 Words
Output Enable (CY7C408A only)
OUTPUT ENABLE
DATA OUT
0065-20
5-38
CY7C408A
WA CYPRESS
SEMICONDUcrOR ====================================
CY7C409A

f-------I!FO--------+-~------I!FO------..,
SHIFT IN
INPUT READY
DATA IN
HF
AFE
0065-16

.-.----I/FO-------I_----I/FO-----,.j
SHIFT OUT
OUTPUT READY
OATA OUT
AFE
HF (HIGH)
0065-17
Bubbleback, Data Out to Data In Diagram
"""."' ~,...----+---J_ _
..,",. f t . \-------
,{ J
tBr
INPUTAEADY
)_tPIA
DATA IN ~~
j~ )(
f---tsiR tHIR
0065-9
Ii> FIFO Contains 64 Words
5-39
~
CY7C408A
CYPRESS CY7C409A
SEMICONDUcrOR ======================================
Fallthrough, Data In to Data Out Diagram
@
SHIFT IN
SHIFT OUT
OUTPUT READY
_~I.
_t_BT-)--'+--~'=1"",,-,---_
DATA OUT
______________________ --J~_tW_R_~-------------------------------
0065-10
FIFO Is Empty

I---tPMR_
MASTER RESET \r-\. -elf-

J
tOIR
INPUT READY
}'f-
tOCR
OUTPUT READY \~
tOSI
"I
SHIFT IN
'LZMR
DATA OUT ~~
HF
tHF
\
AFE tAFE If
}
0065-11
540
CY7C408A
~ CY7C409A
~~~NDUcrOR =====================================================================
Shifting Words In
EMPTY FULL
1 2 8 9 10 31 32 33 55 56 57 64
SHIFT IN .JLJ1. ... ~_... -----,i-
_.n
HF ________________~------------~
AFE
0065-18
Figure 3
Shifting Words Out
SHIFT OUT
HF
FULL
64 63
.JLJ1. ...
56 55 54 9 8 7
... n
EMPTY
1

AFE
0065-19
Figure 4
Architecture of the CY7C408A and through time when it is empty (or near empty) and by the
bubbleback time when it is full (or near full).
CY7C409A
The conventional definitions of fall through and bubbleback
The CY7C408A and CY7C409A FIFOs consist of an ar- do not apply to the CY7C408A and CY7C409A FIFOs
ray of 64 words of 8- or 9-bits each (which are implement- because the data is not physically propagated through the
ed using a dual port RAM cell), a write pointer, a read memory. The read and write pointers are incremented in-
pointer and the control logic necessary to generate the stead of moving the data. However, the parameter is speci-
handshaking (SI/IR, SO/OR) signals as well as the Almost fied because it does represent the worst case propagation
Full/Almost Empty (AFE) and the Half Full (HF) flags. delay for the control signals. That is, the time required to
The handshaking signals operate in a manner identical to increment the write pointer and propagate a signal from
those of the industry standard CY7C40l/402/403/404 the SI input to the OR output of an empty FIFO or the
FIFOs. time required to increment the read pointer and propagate
a signal from the SO input to the IR output of a full FIFO.
Dual Port RAM
The dual port RAM architecture refers to the basic memo- Resetting the FIFO
ry cell used in the RAM. The cell itself enables the read Upon power up, the FIFO must be reset with a Master
and write operations to be independent of each other, Reset (MR) signal. This causes the device to enter the emp-
which is necessary to achieve truly asynchronous operation ty condition, which is signified by the OR signal being
of the inputs and outputs. A second benefit is that the time LOW at the same time that the IR signal is HIGH. In this
required to increment the read and write pointers is much condition, the data outputs (DOo-DOs) will be LOW. The
less than the time that would be required for data to propa- AFE flag will be HIGH and the HF flag will be LOW.
gate through the memory, which would be the case if the
memory were implemented using the conventional register Shifting Data Into the FIFO
array architecture.
The availability of an empty location is indicated by the
Fallthrough and Bubbleback HIGH state of the Input Ready (IR) signal. When IR is
HIGH a LOW to HIGH transition on the Shift-In (SI) pin
The time required for data to propagate from the input to will load the data on the Dlo-Dls inputs into the FIFO.
the output of an initially empty FIFO is defined as the
Fallthrough time. The IR output will then go LOW, indicating that the data
has been sampled. The HIGH to LOW transition of the SI
The time required for an empty location to propagate from signal initiates the LOW to HIGH transition of the IR
the output to the input of an initially full FIFO is defined signal if the FIFO is not full. If the FIFO is full, IR will
as the Bubbleback time. remain LOW.
The maximum rate at which data can be passed through
the FIFO (called the throughput) is limited by the fall-
5-41
---- -_.. _._-_ ....._. __.. ........__... .

_
CY7C408A
riA?~~'NDUCTOR =======================================================================
~
. .-
Shifting Data Out of the FIFO
CY7C409A
must be inverted before being fed back to the interface SO
pin (Figure 5). Two things should be noted when this con-
The availability of data at the outputs of the FIFO is indi- figuration is implemented.
cated by the HIGH state of the Output Ready (OR) signal.
After the FIFO is reset all data outputs (000- DOs) will First, the capacity of N cascaded FIFOs is decreased from
be in the LOW state. As long as the FIFO remains empty N X 64 to (N X 63) + 1.
the OR signal will be LOW and all Shift Out (SO) pulses Secondly, the frequency at the cascade interface is less than
applied to it will be ignored. After data is shifted into the the 35 MHz rate at which the external clocks may operate.
FIFO the OR signal will go HIGH. The external control Therefore, the first device has its data Shifted-In faster
logic (designed by the user) should use the HIGH state of than it is Shifted-Out and eventually this device becomes
the OR signal to generate a SO pulse. The data outputs of momentarily full. When this occurs, the maximum sustain-
the FIFO should be sampled with edge sensitive type 0 able external clock frequency changes from 35 MHz to the
flip-flops (or equivalent), using the SO signal as the clock cascade interface frequency,[14]
input to the flip-flop. When data packets[15] are transmitted, this phenomenon
Interfacing to the FIFO Application Brief does not occur unless more than three FIFOs are depth
cascaded. For example, if two FIFOs are cascaded, a pack-
See the application brief in the back of this databook for etofI27(=2 X 63 + 1) words may be shifted-in at up to
information regarding interfacing to the FIFO under asyn- 35 MHz and then the entire packet may be shifted-out at
chronous operating conditions. up to 35 MHz.
AFE and HF Flags If data is to be shifted-out simultaneously with the data
being shifted-in, the concept of "virtual capacity" is intro-
Two flags, Almost Full/Almost Empty (AFE) and Half
duced. Virtual capacity is simply how large a packet of
Full (HF), describe how many words are stored in the
data can be shifted-in at a fixed frequency, e.g., 35 MHz,
FIFO. AFE is HIGH when there are eight or less, or 56 or
simultaneously with data being shifted-out at any given fre-
more, words stored in the FIFO. Otherwise the AFE flag is quency. Figure 8 is a graph of packet size[16] vs. shift-out
LOW. HF is HIGH when there are 32 or more words
frequency (fsox) for two different values of Shift-In fre-
stored in the FIFO, otherwise the HF flag is LOW. Flag
quency (fSIx) when two FIFOs are cascaded.
transitions occur relative to the falling edges of SI and SO
(Figures 3 and 4). The exact complement of this occurs if the FIFOs initially
contain data and a high Shift-Out frequency is to be main-
Due to the asynchronous nature of the SI and SO signals, it
tained, i.e., a 35 MHz fsOx can be sustained when reading
is possible to encounter specific timing relationships which data packets from devices cascaded two or three deep. If
may cause short pulses on the AFE and HF flags. These
data is shifted-in simultaneously, Figure 8 applies with fSIx
pulses are entirely due to the dynamic relationship of the SI
and fsox interchanged.
and SO signals. The flags, however, will always settle to Notes:
their correct state after the appropriate delay (tOHAFE, 14. Because the data throughput in the cascade interface is dependent on
tDLAFE, tOHHF or tOLHF). Therefore, use oflevel-sensi- the inverter delay, it is recommended that the fastest available invert-
tive rather than edge-sensitive flag detection devices is rec- erbe used.
ommended to avoid false flag encoding. 15. Transmission of data packets assumes that up to the maximum cu-
mulative capacity of the FIFOs is Shifted-In without simultaneous
Shift-Out clocks occurring. The complement of this holds when data
Cascading the 7C408/9A35 Above 25 MHz is Shifted-Out as a packet.
If cascaded FIFOs are to be operated with an external 16. These are typical packet sizes using an inverter whose delay is 4 ns.
17. Only devices with the same speed grade are specified to cascade
clock rate greater than 25 MHz, the interface IR signal together.
I
I
A C
IR
IRX:+-.....::~ IR SO IR SO SOX
I
SI SI OR OR X
SiX: ----:.:J.M SI OR
D
DINX:-.......I~ DOUTX
I
I 1 2 n
._--------------------------------------
+-----UPSTREAM
DOWNSTREAM -----+
0065-22
Figure 5. Cascaded Configuration Above 25 MHz
5-42
CY7C408A
~p~ CY7C409A
'nICONDUcrOR ======================================================================
FIFO Expansion
128 x 9 Configuration
HF/AFE
HF/AFE
SHIFT IN SI OR SI OR OUTPUT READY
INPUT READY IR SO IR SO SHIFT OUT
01 0 00 0 01 0 00 0
011 01 011 01
r 01 2 02 01 2 02
01 3 03 01 3 03
DATA IN 01 4 04 01 4 04 DATA OUT
015 05 015 05
01 6 00 6 01 6 00 6
Dl7 07 01 7 07
Dis DOs Dis DOs
MR MR
y y
0065-12
Figure 6. Cascaded Configuration at or below 25 MHz
FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
User Notes referencing Figures 6 and 7:
1. When the memory is empty the last word read will remain on the 3. If SO is held HIGH while the memory is empty and a word is written
outputs until the master reset is strobed or a new data word falls into the input, that word will fall through the memory to the output.
through to the output. OR will go HIGH for one internal cycle (at least tpOR) and then go
2. When the output data changes as a result of a pulse on SO, the OR back LOW again. The stored word will remain on the outputs. If
signal always goes LOW before there is any change in output data and more words are written into the FIFO, they will line up behind the
stays LOW until the new data has appeared on the outputs. Anytime first word and will not appear on the outputs until SO has been
OR is HIGH, there is valid stable data on the outputs. brought LOW.
4. When the master reset is brought LOW, the outputs are cleared to
LOW, IR goes HIGH and OR goes LOW.
5-43
CY7C408A
fin .
~NDUcrOR =====================================================================
FIFO Expansion (Continued)
CY7C409A
192 x 27 Configuration
HI'/AI'E.--------. r------+ HI'/AI'E
SHIFT OUT
50 IR
OR 51
00 0 01 0
01 7 07
018 08
Cot.tPOSITE
50 OUTPUT READY
OR
00
011 01 011 01
002 01 2 02 01 2
03 01 3 03 01 3
04 01 4
05 015
DOs DiS
01 7
04 01 4 04 01 4 04
015 05 015 05 015 05
Dis DOs Dis DOs Dis DOs
01 7 07 01 7 07 01 7 07
01 8 008 01 8 08 018 00 8
MR MR MR
hlR
0065-13
Figure 7. Depth and Width Expansion
FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and Output
Ready flags. This need is due to the variation of delays of the FIFOs.
400
350 J
II>
"E0 300
f slx = 30,MHz
I
~ 250 '\i
...
N 200 ?
Vi
t:i 150 ~~
:..: .". f slx =35 MHz
u
:: 100
50
4 8 12 16 20 24 28 32 36
OUTPUT RATE (fsox ) 01' BOnOM 1'11'0 (MHz)

0065-24
Figure 8. Virtual Capacity vs. Output Rate for Two FIFOs Cascaded Using an Inverter
5-44
CY7C408A
(;n~~NDUcrOR =======================================================================
.. CY7C409A

1.2 r----,r---~---r---.., 1.4.------r--------, 60
~
! 50
'" Vee =5.0 V
'" '" "

1.0 I-
c.J c.J
1.2 :E TA" 25C
!:t !:t w
a: 40
0 a:
w 0
N w :::I
N (.)
:;:j 0.8 ::l w 30
< < (.)
:E :E a:
a: a: :::I
0
z 0 5l 20
"'~
Z
0.6 !5A.-
VIN =5.0V Vee =5.5 V I- 10
~
:::I
TA =25C VIN =5.0 V 0
0.4 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
III
1.3 1.6,...-----r------, 140
>
(.)
zw
1.2 >
~
w
1.41------1--------; !
~ 120
..---
-----
I-
z 100
:::I
0
w
a:
1.1
:::I
ow
ff:
w
a:
a:
:::I 80
/
",
----
/
II.
Q 1.0 Q to'
w ~ w ~
N
:;:j
<
:E
0.9 V N
:;:j
<
:E
z
iii
I-
:::I
60
40
/ Vee =5.0 V
TA = 25C
a: a:
/
A.-
0 oz I-
:::I
z 0.8
0 20
0.7 0.6~----~-----... o
V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
TYPICAL FREQUENCY CHANGE NORMALIZED Icc

1.6 1.1
>
(.)
Z
w
:::I
0
w
1.5
1.4
..;V
/V --- !:t
Q
w
c.J
1.0
0.9 ./
V
/
/~
a: N
LL.
Q 1.3 :;:j
<
w
N
:;:j
< 1.2 / :E
a:
0
z
0.8
/
:E
a:
0
2 1.1 / 0.7
/
1.0
o
/ 200 400 600 800 1000 o 0 5 10 15 20 25 30 35

0065-23
5-45
CY7C408A
5A. ~~NDUcrOR==================================================================
CY7C409A
Frequency Package Operating Frequency Package Operating

(MHz) Type Range (MHz) Type Range
35 CY7C408A-35PC P21 Commercial 35 CY7C409A-35PC P21 Commercial
CY7C408A-350C 022 CY7C409A-350C 022
CY7C408A-35LC L64 CY7C409A-35LC L64
CY7C408A-35VC V21 CY7C409A-35VC V21
CY7C408A-250C 022 CY7C409A-250C 022
CY7C408A-250MB 022 Military CY7C409A-250MB 022 Military
CY7C408A-25LMB L64 CY7C409A-25LMB L64
CY7C408A-150C 022 CY7C409A-150C 022
CY7C408A-150MB 022 Military CY7C409A-150MB 022 Military
CY7C408A-15LMB L64 CY7C409A-15LMB L64
5-46
CY7C408A
, 5n ,. CY7C409A
~~6NDUcrOR================================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
lOS 1,2,3
ICCQ 1,2,3
III
fo 7,8,9,10,11 tOLAFE 7,8,9,10,11
tpHSI 7,8,9,10,11 tOHAFE 7,8,9,10,11
tpLSI 7,8,9,10,11 tB 7,8,9,10,11
tSSI 7,8,9,10,11 too 7,8,9,10,11
tHSI 7,8,9,10,11 tpMR 7,8,9,10,11
tOUR 7,8,9,10,11 tOSI 7,8,9,10,11
tOHIR 7,8,9,10,11 tOOR 7,8,9,10,11
tpHSO 7,8,9,10,11 tDIR 7,8,9,10,11
tpLSO 7,8,9,10,11 tLZMR 7,8,9,10,11
tOLOR 7,8,9,10,11 tAFE 7,8,9,10,11
tOHOR 7,8,9,10,11 tHF 7,8,9,10,11
tSOR 7,8,9,10,11
tHSO 7,8,9,10,11
tBT 7,8,9,10,11
tSIR 7,8,9,10,11
tHIR 7,8,9,10,11
tpIR 7,8,9,10,11
tPOR 7,8,9,10,11
tSIIR 7,8,9,10,11
tSOOR 7,8,9,10,11
tOLZOE 7,8,9,10,11
tOHZOE 7,8,9,10,11
tOHHF 7,8,9,10,11
tOLHF 7,8,9,10,11
5-47
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
CYPRESS
SEMICONDUCTOR Cascadeable 512 X 9 FIFO
Features
512 x 9, 1024 x 9, 2048 x 9 CY7C421 pin compatible and when the Write (W) signal is LOW.
FIFO buffer memory functional equivalent to IDT7201 Read occurs when Read (R) goes
LOW. The 9 data outputs go to the
Dual port RAM cell Functional Description high impedance state when R is
Asynchronous read/write The (CY7C420, CY7C421,) HIGH.
High speed 25 MHz read/write (CY7C424, CY7C425,) and A Half-Full (HF) output flag is provid-
independent of depth/width (CY7C428, CY7C429) are, respective- ed that is valid in the standalone and
ly, 512, 1024 and 2048 words by 9-bit width expansion configurations. In the
Low operating power wide first-in first-out (FIFO) memories
Icc (max,) = 125 mA commercial depth expansion configuration this pin
offered in 600 mil wide and 300 mil provides the expansion out (XC) infor-
Icc (max,) = 140 mA military wide packages, respectively. Each mation which is used to tell the next
Half full flag in standalone FIFO memory is organized such that FIFO that it will be activated.
the data is read in the same sequential
Empty and full flags order that it was written. Full and In the standalone and width expansion
Retransmit in standalone Empty flags are provided to prevent conf~ations a LOW on the Retrans-
over-run and under-run. Three addi- mit (RT) input causes the FIFO's to
Expandable in width and depth
tional pins are also provided to facili- retransmit the data. Read Enable (R)
Parallel Cascade minimizes tate unlimited expansion in width, and Write Enable (W) must both be
bubblethrough depth, or both. The depth expansion HIGH during a retransmit cycle, and
5V 10% supply technique steers the control signals then R is used to access the data.
from one device to another in parallel, The CY7C420, CY7C421, CY7C424,
300 mil DIP packaging thus eliminating the serial addition of CY7C425, CY7C428 and CY7C429
300 mil SOJ (512 x 9) propagation delays so that throughput are fabricated using an advanced 0.8
packaging is not reduced. Data is steered in a sim- micron N-well CMOS technology. In-
TTL compatible ilar manner. put ESD protection is greater than
The read and write operations may be 2000V and latchup is prevented by
Three-state outputs asynchronous; each can occur at a rate careful layout, guard rings and a sub-
of 25 MHz. The write operation occurs strate bias generator.

DATA INPUTS
(00-08) PLCC/LCC DIP
Top View Top View
~ ~13= ~ ~C!;:g Vee
02 5
43
2E132313~~ 06 04
05
01 6 284 07
DO 7 274 Nt 06
Xi 8 26 fLIRT 07
IT 9 25 fiR fLIRT
00 10 24 Ef fiR
01 11 23 XO/HF'
Nt 12 22 07
02 13 21 06
14151617181920 07
1'1') co 0 (.)10::: .... II) 06
oOiSz 00
0081-3 05
04
GNO
0081-2
0081-1
5-48
CY7C420, CY7C421, CY7C424
I
5Il~~NDUcrOR =====================================================================
.
Selection Guide
CY7C425, CY7C428, CY7C429
7C420-65,7C421-65
7C424-65, 7C425-65
7C429-65

Maximum Ratings
in High Z State ...................... -0.5V to +7.0V Range
Temperature Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial DOC to +7DOC 5V 10%
Power Dissipation ............................. 1.0W Military [3] - 55C to + 125C 5V 10%
Standby Current All Inputs = VIH Min. ~~~~~

All Inputs
Power Down Current Vee -D.2V
lOS Output Short Circuit
Current[1]
Capacitance [2]
CIN Input Capacitance TA = 2SC, f = 1 MHz 5 pF
COUT Output Capacitance Vee = 4.SV 7
Notes:
1. For test purposes, not more than one output at a time should be S. Icc (commercial) = 100 mA + [(l' - 12.S) 2 rnA/MHz] for
shorted. Short circuit test duration should not exceed 30 seconds. r~ 12.S MHz
2. Tested initially and after any design or process changes that may where r = the larger of the write or read
affect these parameters. operatins frequency.
3. TA is the "instant on" case temperature. 6. Icc (military) = lIS mA + [(I' - 12.S) 2 mA/MHz] for
4. See the last page of this specification for Group A subgroup testing r~ 12.5 MHz
information. where r = the larger of the write or read
operating frequency.
5-49
CY7C420, CY7C421, CY7C424I
51!= SEMICONDUCTOR

CY7C425, CY7C428, CY7C429 I
3.0 V -------u~~--""_
R1 500.0. R1 500.0.
5V o---'IIVVo--, 5V O---'V~-"""I
OUTPUT 0-....- - -.. OUTPUT 0-....- - - . GND-.....;o;.;..I!

.;;5 ns .;;5ns
R2 R2
30 PF 333.0. 5 PF 333.0.
L
0081 -5
-
INCLUDING
JIG AND -
SCOPE
L
-
INCLUDING
JIG AND -
Figure 2. All Input Pulses
SCOPE
0081-4 0081-18
Figure 1a Figure 1b
200.0.
OUTPUT~2V
0081-6
Switching Characteristics Over the Operating RangeD, 4]

5-50
CY7C420, CY7C421, CY7C424
5n
__ ;
~ ~~~NDUaOR
CY7C425, CY7C428, CY7C429
=======================================================================
Switching Characteristics Over the Operating Rangel l , 4] (Continued)
------------------.-----------------,-----,
7C42040, 7C42140
7C42440, 7C42540
7C42840, 7C42940
65 ns

tWPF 40 65 ns
Expansion Out LOW

tXOL 40 65 ns
Delay from Clock
Expansion Out HIGH
tXOH 40 65 ns
Delay from Clock
Notes:
1. Test conditions assume signal transition time of 5 ns or less, timing 3. tHzR transition is measured at + 500 m V from VOL and - 500 m V
reference levels of 1.5V and output loading of the specified IOL/loH from VOH. tOVR transition is measured at the 1.5V level. tHwz and
and 30 pF load capacitance. as in Figure la, unless otherwise speci- tLzR transition is measured at 100mV from the steady state.
fied. 4. See the last page of this specification for Group A subgroup testing
2. tHZR and tovR use capacitance loading as in Figure lb. information.
Switching Waveforms
Asynchronous Read and Write Timing Diagram
-----""""' ....._____ >-----""""'( DATA IN VALID )>-----

0081-7

1-------tt.4RSC [1J - - - - - - - 1
1-----tpt.4R - - - - - - I
i,ffi-----I 1---+-------
Hi"
_______ ~---------J'
ff
Notes:
------------------~ 0081-8
1. tMRSC = tpMR + tRMR 2. Wand R = VIH around the rising edge of MR.
5-51
CY7C420, CY7C421, CY7C424
5Jl~~NDUcrOR=====================================================================
..

CY7C425, CY7C428, CY7C429
Half-Full Flag Timing Diagram
HALF-FULL HALF-FULL+ 1 HALF-FULL
-if tRHF ~
~tWH"-
,
\ }~
0081-9
Last WRITE to First READ Full Flag Timing Diagram

ADDITIONAL
LAST WRITE FIRST READ READS FIRST WRITE
0081-10
Last READ to First WRITE Empty Flag Timing Diagram

ADDITIONAL
LAST READ FIRST WRITE WRITES FIRST READ
DATA OUT -+-----<

" ' - l I ' I ' -_ _
0081-11
Retransmit Timing Diagram

t RTC
t pRT -
1\
R.W
,\
~tRTR-
0081-12
Notes:
1. tRTC = tRT + tRTR. 2. EF. HF and FF may change state during retransmit as a result ofthe
offset of the read and write pointers, but flags will be valid at tRTC.
5-52
CY7C420, CY7C421, CY7C424
5n -
~~NDUcrOR =======================================================================
CY7C425, CY7C428, CY7C429
Empty Flag and Read Bubble-Through Mode Timing Diagram
DATA IN
_ _J 1,------------------------------------------------
DATAOUT---1--------------11~~~~~~~~~~------------------
Full Flag and Write Bubble-Through Mode Timing Diagram

0081-13

IT
--~------------~----"
DATA IN --.....jo-----------------------( 1"---"""'1
t~
DATA OUT -------~DATA OUT VALIO)@------------------------------
0081-14
Expansion Timing Diagrams

WRITE TO LAST PHYSICAL WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 1
------"', LOCATION OF DEVICE 2
0081-15
READ FROM LAST PHYSICAL READ FROM FIRST PHYSICAL

LOCATION OF DEVICE 1
,-----, LOCATION OF DEVICE 2
,
0081-16
*Expansion Out of Device 1 (XOt) is connected to Expansion In of Device 2 (Xl2)'
5-53
CY7C420, CY7C421, CY7C424
(in~~UcrOR~===================================================================
. CY7C425, CY7C428, CY7C429
Architecture
The CY7C420/421/424/425/428/429 FIFOs consist of an The falling edge ofR during the last read cycle before the
array of 512/1024/2048 words of9-bits each (implemented empty condition triggers a HIGH to LOW transition of
by an array of dual port RAM cells), a read pointer, a write EF, prohibiting any further read operations until tWEF af-
pointer, control signals (W, R, XI, XO, FL, RT, MR) and ter a valid write.
Full, Half Full, and Empty flags.
Retransmit
Dual Port RAM The Retransmit feature is beneficial when transferring
The dual port RAM architecture refers to the basic memo- packets of data. It enables the receipt of data to be interro-
ry cell used in the RAM. The cell itself enables the read gated by the receiver and retransmitted if necessary.
and write operations to be independent of each other, The Retransmit (RT) input is active in the Single Device
which is necessary to achieve truly asynchronous operation Mode only. The Retransmit feature is intended for use
of the inputs and outputs. A second benefit is that the time when 512/1024/2048 (corresponding to device depth) or
required to increment the read and write pointers is much less writes have occurred since the previous MR cycle. A
less than the time that would be required for data to propa- LOW pulse on RT resets the internal read pointer to the
gate through the memory, which would be the case if the first physical location of the FIFO. The write pointer is
memory were implemented using the conventional register unaffected. Rand W must both be HIGH during a retrans-
array architecture. mit cycle. Full, Half Full and Empty flags are governed by
Resetting the FIFO the relative locations of the Read and Write pointers and
will be updated by a retransmit operation.
Upon power up, the FIFO must be reset with a Master
Reset (MR) cycle. This causes the FIFO to enter the empty After a retransmit cycle, previously read data may be reac-
condition signified by the Empty flag (EF) being LOW, cessed using R to initiate standard read cycles beginning
and both the Half-Full (HF) and Full flag (FF) resetting to with the first physical location.
HIGH. Read (R) and Write (W) must be HIGH Single DeviceIWidth Expansion Modes
tRPw/twpw before and tRMR after the rising edge of MR
for a valid reset cycle. Single Device and Width Expansion Modes are entered by
grounding XI during a MR cycle. During these modes the
Writing Data to the FIFO HF and R T features are available. FIFOs can be expanded
The availability of an empty location is indicated by the in width to provide word widths greater than 9 in incre-
HIGH state of the Full flag (FF). A falling edge of Write ments of9. During Width Expansion Mode all control line
(W) initiates a write cycle. Data appearing at the inputs inputs are common to all devices and flag outputs from any
(DO-D8) tSD before and tHD after the rising edge ofW device can be monitored.
will be stored sequentially in the FIFO. Depth Expansion Mode (Figure 3)
The Empty flag (EF) LOW to HIGH transition occurs Depth Expansion Mode is entered when, during a MR cy-
tWEF after the first LOW to HIGH transition on the write cle, Expansion Out (XO) of one device is connected to
clock of an empty FIFO. The Half-Full flag (HF) will go Expansion In (XI) of the next device, with XO of the last
LOW on the falling edge of the write clock following the device connected to XI of the first device. In the Depth
occurrence of half full. HF will remain LOW while less Expansion Mode the First Load (FL) input, when ground-
than one half of the total memory of this device is available ed, indicates that this part is the first to be loaded. All
for writing. The LOW to HIGH transition of the HF flag other devices must have this pin HIGH. To enable the
occurs on the rising edge of Read (R). HF is available in correct FIFO, XO is pulsed LOW when the last physical
Single Device Mode only. The Full flag (FF) goes low on location of the previous FIFO is written to and is pulsed
the falling edge of W during the cycle in which the last LOW again when the last physical location is read. Only
available location in the FIFO is written, prohibiting over- one FIFO is enabled for read and one is enabled for write
flow. FF goes HIGH tRFF after the completion of a valid at any given time. All other devices are in standby.
read of a full FIFO.
FIFOs can also be expanded simultaneously in depth and
Reading Data from the FIFO width. Consequently, any depth or width FIFO can be cre-
The falling edge of Read (R) initiates a read cycle if the ated of word widths in increments of9. When expanding in
Empty flag (EF) is not LOW. Data outputs (QO-Q8) are in depth, a composite FF must be created by OR-ing the FFs
a high impedance condition between read operations (R together. Likewise, a composite EF is created by OR-ing
HIGH), when the FIFO is empty, or when the FIFO is in the EFs together. HF and RT functions are not available in
the Depth Expansion Mode but is not the active device. Depth Expansion Mode.
5-54
I ~ CY7C420, CY7C421, CY7C424
~~'NDUcrOR
.:
~~~~~~~~~~~~ CY7C425, CY7C428, CY7C429
Architecture (Continued)
-
xo
Vi ""'-
R
FF CY7C420 EF
9, 9, .. CY7C421
CY7C424
9, .
,7 I
- ,I ...>
D CY7C425 0
7 -y CY7C428
r---+
CY7C429
~ Vee
Xi
xc
FULL
JL ""'-
.....
1
~
FF-"
CY7C420
9, .. CY7C421
CY7C424
, -y CY7C425
CY7C428
CY7C429
to -
XI
I- IT
~
~
~
~
~
- .....I
EMPTY
--p'

-
XO
- FF-"
I- IT -
-
--
CY7C420 ~
9, .. CY7C421
CY7C424
7 CY7C425
RS
' ... CY7C428 -
FL
CY7C429
Xi --
FIRST DEVICE
0081-17
Figure 3. Depth Expansion
5-55
CY7C420, CY7C421, CY7C424
WAi ~~~UcrOR=====================================================================
CY7C425, CY7C428, CY7C429

12~--~----~--~--~ 1.4 60
1 50 to-....
" '"
I-
~ 1.0 12 Z
~
----
L.J
~ 40
Q
!oJ
~ OBr---~--~~--~--~
Q
L.J
N
::::i 1.0
r---. a
L.J 30
u
~
<I(
""II::
:,; ::::E 0::
o
0::
0 5 20
z 0.6 I-~~____I -__-+-__-----j z OB
Vee =5.5V
VI
10
"- ~
VIN =5.0V Vee =5.0V
"
VIN =5.0V
TA = 25C f=20MHz TA =25OC
0.4 '-------'-----'------------' 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
NORMALIZED tA NORMALIZED tA OUTPUT SINK CURRENT

1.3 1.6 ~-------,---------~ 140
.$ 1.1
Q
1.2
~
...""
8
1.4 1----------+-----------1
121----------+-------~~
'<
!.
I-
zL.J 100
0::
120
/
~ --
---
L.J 0:: 80
N
::::i 1.0 """'-- N
::::i
::::I
U
/
r--..
<I(
<I( :.: 60
::::E
0::
~ 1.0 1--------:::,..joII!==----------I z
0
z 0.9 o
z
iii
I- 40 -'
0.8
OB I--------+--------------j
::::I
~
::::I 20 / Vee =5.0V
0.7
TA = 25C 0.6 Vee = 5.0V
L...-_ _ _ _ _ _....I...._ _ _ _..;.;;.._ _---I
0
o V TA = 25C
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
TYPICAL tA CHANGE NORMALIZED Icc

1.6 1.3
1.5
/ 1.1
V
..."" jV l7'
1.4 ~ /
Q
L.J
V f3 os
~
<I(
::::E
0::
0
z
1.3
12
/
1/ I 01
0.5
[/17
.IV
1.1
Vec =5.0V / Vee = 5.0V
1.0 / TA = 25C
o
ITA =25OC
o 200 400 600 800 1000 o 5 10 15 20 25 30 35
CAPACITANCE (pF') F'REQUENCY (MHz)
0081-111
5-56
CY7C420, CY7C421, CY7C424
5Jl
__ .
~ ~~NDUcrOR
CY7C425, CY7C428, CY7C429
=======================================================================
557
CY7C420, CY7C421, CY7C424
5n CYPRESS CY7C425, CY7C428, CY7C429
s~~O~UcrOR==================================================================
5-58
CY7C420, CY7C421, CY7C424
fill , CYPRF.SS
SEMICONDUCI'OR
CY7C425, CY7C428, CY7C429
=========================================================
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
Icc 1,2,3
ISB! 1,2,3
III
ISB2 1,2,3
los 1,2,3
tRC 9,10,11 tREF 9,10,11
tA 9,10,11 tRFF 9,10,11
tRR 9,10,11 tWEF 9,10,11
tpR 9,10,11 tWFF 9,10,11
tLZR 9,10,11 tWHF 9,10,11
tOVR 9,10,11 tRHF 9,10,11
tHZR 9,10,11 tRAE 9,10,11
twc 9,10,11 tRPE 9,10,11
tpw 9,10,11 tWAF 9,10,11
tHwZ 9,10,11 tWPF 9,10,11
tWR 9,10,11 tXOL 9,10,11
tso 9,10,11 tXOH 9,10,11
tHO 9,10,11
tMRSC 9,10,11
tpMR 9,10,11
tRMR 9,10,11
tRPW 9,10,11
twpw 9,10,11
tRTC 9,10,11
tpRT 9,10,11
tRTR 9,10,11
tEFL 9,10,11
tHFH 9,10,11
tFFH 9,10,11
5-59
CY7C510
CYPRESS
SEMICONDUCTOR 16 X 16 Multiplier
Accumulator
Features
Fast Two's complement or unsigned include loading the accumulator with
- CY7C51045 has a 45 ns magnitude operation the current product, adding or sub-
(max.) clock cycle tracting the accumulator contents and
(commercial)
ESD Protection the current product, or preloading the
- Capable of withstanding
- CY7C51055 has a 55 ns greater than 2000V static accumulator from the external world.
(max.) clock cycle (military) discharge voltage All inputs (data and instructions) and
Low Power outputs are registered. These indepen-
Pin compatible and functionally
- ICC (max. at 10 MHz) = equivalent to Am29510 and dently clocked registers are positive
100 mA (commercial) TMC2110 edge triggered D-type flip-flops. The
- ICC (max. at 10 MHz) 35-bit accumulator/output register is
110 mA (military) Functional Description divided into a 3-bit extended product
(XTP), a 16-bit most significant prod-
Vee Margin The CY7C51O is a high-speed 16 X 16 uct (MSP), and a 16-bit least signifi-
-SV 10% parallel multiplier accumulator which
- All parameters guaranteed cant product (LSP). The XTP and
operates at 45 ns clocked multiply ac- MSP have dedicated ports for three-
over commercial and military cumulate (MAC) time (22 MHz multi-
operating temperature range state output; the LSP is multiplexed
ply accumulate rate). The operands with the Y -input. The 35-bit accumula-
16 X 16 bit parallel may be specified as either two's com- tor/output register may be preloaded
multiplication with accumulation plement or unsigned magnitude 16-bit through the bidirectional output ports.
to 35bit result numbers. The accumulator functions
Logic Block Diagram
CLKX >--_---_1>';:-;;;;;;,
CLKY').--....+------+----I
TC
RNO
Ace
35
0057-1
Selection Guide
7C51045 7C51055 7C51065 7C51075
Maximum Multiply- Commercial 45 55 65 75
Accumulate Time (ns) Military 55 65 75
5-60
~PRE3S CY7C510
WAICONDUcrOR
Maximum Ratings
=====================================
Operating Range
guidelines, not tested.) Range Temperature Vee
Ambient Temperature Under Bias .... - 55C to + 125C Commercial O"Cto +70"C 5V 1O%
Supply Voltage to Ground Potential .... - 0.5V to + 7.0V Military[l] - 55 to + 125C 5V 1O%
DC Input Voltage ................... -0.5V to + 7.0V Note:
DC Voltage Applied to Outputs ..... -0.5V to Vee Max.
Output Current, into Outputs (low) .............. 10 rnA
Static Discharge Voltage ..................... > 2001 V
Pin Configurations

x7
X6
Xs Xs 9 8 7 6 5 4 3 2 111686766 656463 62 6i
,
x4 Xg XIS )10 ~ 60C P2 'Y2
OEL ~ 11 59C P3 'Y3
X3 x l0 RND ) 12 58C P4 'Y4
x2 Xll SUB 13 57 PsYs
ACC 14 564 P6 'Y 6
Xl X 12 CLKX 15 55 ) P7 'Y7
Xo X 13 CLKY 16 54 ) GND
Vee 17 534 GND
YoP o X 14
Vee 18 52 P8 Ya
Yl ,P l X 1S Vee 19 51 Pg.Yg
Vee 20 50 P10'Y 10
Y2 ,P 2 OEL
TC 21 49 P11 'Y 11
Y3 ,P 3 RND OEX 22 48 P12 'Y 12
Y4 ,P 4 SUB PREL I 23 47 P13 'Y 13
OEM 24 46 P14'Y 14
YsP s ACC CLKP 25 45 P1SY 1S
Y6 ,P6 CLKX P34 26 44 P16
'- 272829303132 33 343536~38 39 ~~ 4243
Y7 ,P 7 CLKY
GND Vee
Ys,P S TC 0057-3
Yg.Pg OEX
Yl0 P l0 PREL
Yll ,P ll OEM
Y 12 ,P 12 CLKP
Y 13 ,P 13 P34
Y 14,P 14 P33
Y1S P 1S P32
P16 P3l
P 17 P30
P1S P29
P 19 P2S
P20 P27
P21 P26
P22 P2S
P23 P24
0057-2
5-61
(ij;=-s SEMICONDUcrOR
CY7CSI0
Pin Configurations (Continued)

Pin Configuration for 68Pin Grid Array
eeee8
51 50 48 46 44
8 8 8 e
42 40 38 36
e 53
8 8
52 49
e
47
8 45
e 43
e8 e8
41 39 37 35
e
34
e55
(0
54
8 32
e
33
0 e ee
30 31
ee
57 56
G 0 58 28 29
ee
59
0 G
61 60 26 27
G (0 ee 24 25
ee
63 62
(0 0 22 23
ee
65 64
e G 20 21
e ee e
67 66
8 1
e 8
3 5
e8 e
7 9 11
8 13 15 18 19
e 2
8 8
4 6
eee8 10 12
8 14
8 e
16 17
0057-13
5-62
~ CY7C510
~ ~~~~DUcrOR =======================================================================
Pin Definitions
Signal Signal
I/O Description I/O Description
Name Name
XI5-0 I X-Input Data. This 16-bit number may be OEL I Output Enable Least. When LOW, the
interpreted as two's complement or LSP bidirectional port is enabled for
unsigned magnitude. output. When HIGH, the output drivers
are disabled (high impedance) and the
YI5-0 I/O Y-Input Data/LSP Output Data. When
MSP port may be used for preloading. See
(PIS-O) this port is used to input a Y value, the
Preload Function Table.
16-bit number may be interpreted as two's
complement or unsigned magnitude. This PREL I Preload. When HIGH, the three
bidirectional port is multiplexed with the bidirectional ports may be used to preload
LSP output (PIS-O), and can also be used data into the accumulator register at the
to preload the LSP register. rising edge of CLKP. The three-state
controls (OEX, OEM, OEL) must be
P34-32 I/O Extended Product (XTP) Output Data.
HIGH to preload data.
This port is bidirectional. The extended
product emerges through this port. The When LOW, the accumulated product is
XTP register may also be preloaded loaded into the accumulator/output
through this port. register at the rising edge ofCLKP. The
output drivers must be enabled (OEX,
P3I-I6 I/O MSP Output Data. This port is OEM, OEL must be LOW) for the
bidirectional. The most significant accumulated product to be output.
product emerges through this port. The Ordinarily, PREL, OEX, OEM, and OEL
MSP register may also be preloaded are tied together. See accumulator
through this port. function table.
PI5-0 I/O LSP Output Data. This port is TC I Two's Complement Control. When
bidirectional. The least significant HIGH, the 7C51O is in two's complement
product emerges through this port. The mode, where the input and output data
LSP register may also be preloaded are interpreted as two's complement
through this port. numbers. The device is in unsigned
CLKX I X-Register Clock. X-Input Data are magnitude mode when TC is LOW. This
latched into the X-register at the rising control is loaded into the instruction
edge of CLKX. register at the rising edge of CLKX +
CLKY.
CLKY I Y-Register Clock. Y-Input Data are
latched into the Y -register at the rising RND I Round Control. When HIGH, rounding
edge ofCLKY. is enabled and a "1" is added to the MSB
of the LSB (PIS). When LOW, the
CLKP I Product Register Clock. XTP, MSP, and product is unchanged. This control is
LSP are latched into their respective loaded into the instruction register at the
registers at the rising edge of CLKP. If rising edge of CLKX + CLKY.
preload is selected, these registers are
loaded with the preload data at the output ACC I Accumulate Control. When HIGH, the
pins via the bidirectional ports. If preload accumulator/output register contents are
is not selected, these registers are loaded added to or subtracted from the current
with the current accumulated product. product (XY) and this result is stored
back into the accumulator/output
OEX I Output Enable Extended. When LOW, register. When LOW, the product is
the extended product bidirectional port is loaded into the accumulator register,
enabled for output. When HIGH, the overwriting the current contents. This
outputs drivers are disabled (high control is loaded into the instruction
impedance) and the XTP port may be register at the rising edge of CLKX +
used for preloading. See Preload Function CLKY. See accumulator function table.
Table.
SUB I Subtract Control. When both ACC and
OEM I Output Enable Most. When LOW, the SUB are HIGH, the accumulator register
MSP bidirectional port is enabled for contents are subtracted from the current
output. When HIGH, the output drivers product XY and this result is written back
are disabled (high impedance) and the into the accumulator register. When ACC
MSP port may be used for preloading. See is HIGH and SUB is LOW, the
Preload Function Table. accumulator register contents and current
product are summed, then written back to
the accumulator register. This control is
loaded into the instruction register at the
rising edge ofCLKX + CLKY. See
accumulator function table.
5-63
~ CY7C510
~~~NDUcrOR=====================================================================
Functional Description Preload Function Table
The CY7C51O is a high-speed 16 X 16-bit multiplier accu- Output Register
mulator (MAC). It comprises a 16-bit parallel multiplier PREL OEX OEM OEL
followed by a 35-bit accumulator. All inputs (data and in- XTP MSP LSP
structions) and outputs are registered. The 7C510 is divid- 0 0 0 0 Q Q Q
ed into four sections: the input section, the 16 X 16 asyn- 0 0 0 1 Q Q z
chronous multiplier array, the accumulator, and the out- 0 0 1 0 Q z Q
put/preload section. 0 0 1 1 Q z z
The input section has two 16-bit operand input registers for 0 1 0 0 z Q Q
the X and Y operands, clocked by the rising edge of CLKX 0 1 0 1 Z Q z
and CLKY, respectively. The four-bit instruction register 0 1 1 0 Z z Q
(TC; RND, ACC, SUB) is clocked by the rising edge of the 0 1 1 1 Z Z Z
logical OR of CLKX, CLKY. 1 0 0 0 Z Z Z
The 16 X 16 asynchronous multiplier array produces the 1 0 0 1 Z Z PL
32-bit product of the input operands. Either two's comple- 1 0 1 0 Z PL Z
ment or unsigned magnitude operation is selected, based on 1 0 1 1 Z PL PL
control TC. Ifrounding is selected, (RND = 1), a "I" is 1 1 0 0 PL Z Z
added to the MSB of the LSP (position PIS). The 32-bit 1 1 0 1 PL Z PL
product is zero-filled or sign-extended as appropriate and 1 1 1 0 PL PL Z
passed as a 35-bit number to the accumulator section. 1 1 1 1 PL PL PL
The accumulator function is controlled by ACC, SUB, and Z = Output buffers at High impedance (disabled.)
PREL. Four functions may be selected: the accumulator Q = Output buffers at Low impedance. Contents of output register
may be loaded with the current product; the product may available through output ports.
be added to the accumulator contents; the accumulator PL = Output disabled. Preload data supplied to the output pins will be
loaded into the output register at the rising edge of CLKP.
contents may be subtracted from the current product; or
the accumulator may be preloaded from the bidirectional
ports. Accumulator Function Table
The output/preload section contains the. accumulator/out- PREL ACC SUB P OPERATION
put register and the bidirectional ports. This section is con- L L X Q Load
trolled by the signals PREL, OEX, OEM, and OEL. When
L H L Q Add
PREL is HIGH, the output buffers are in h6gh impedance
state. When the controls OEX, OEM, and EL are also L H H Q Subtract
high, data present at the output pins will be preloaded into
H X X PL Preload
the appropriate accumulator register at the rising edge of
CLKP. When PREL is LOW, the signals OEX, OEM, and
OEL are enable controls for their respective three-state
output ports.
5-64
~ CY7C510
~~~DUcrOR================================================================~
CY7C510
Input Formats
Fractional Two's Complement Input
115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 115 14 13 12 11 10 9 8 7 6 5 4 3 2 I
_20 2- 1 2- 2 2-3 2-4 2- 5 2-6 2- 7 2- 8 2-9 2-102-11 2-122-13 2-142-15 -20 2- 1 2-2 2- 3 2-4 2-5 2-6 2-7 2- 8 2-9 2-102-112-122-13 2-142-15
(Sign) (Sign)
Integer Two's Complement Input

XIN YIN
115 14 13 12 11 10 9 7 6
_215 214 213 212 211 210 29 2 8 27 2 6 2 5 24 2 3 22 21
4 2 1 115 14 13 12 11 10 9 7 6 4 2 01
20 _215 214 213 212 211 210 29 2 8 27 26 2 5 24 2 3 22 21 20
(Sign) (Sign)
Unsigned Fractional Input
115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I 115 14 13 12 11 10 9 8 7 6 5 4 3 2 I
2- 1 2- 2 2-3 2-4 2- 5 2-6 2- 7 2- 8 2- 9 2- 10 2-11 2- 12 2- 13 2- 14 2- 15 2- 16 2- 1 2- 2 2-3 2-4 2- 5 2-6 2- 7 2- 8 2-9 2-10 2-112-12 2-13 2-142-152-16
Unsigned Integer Input
....
11_5_14_1_3_12_1_1_10_9_ _ _7_ _
6 _ _4_ _ _2_ _ _0.......1 115 14 13 12 11 10 9 7 6 4 2 01
CY7C510
Output Formats
Two's Complement Fractional Output
XTP MSP LSP
b4 33321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9 7 6 5 4 2 I
-24 23 22 21 202-12-22-32-42-52-62-72-82-92-10 2-11 2-122-132-14 2-152-162-172-182-192-202-212-222-232-242-252-26 2-27 2-28 2-29 2-30
(Sign)
Two's Complement Integer Output

XTP MSP LSP
134 33 321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I
_234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 2 19 218 217 2 16 215 214 2 13 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
Unsigned Fractional Output

XTP MSP LSP
13433321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9 7 6 5 4 2 0 I
222120 2-12-22-32-42-52-62-72-82-92-10 2- 11 2-122-13 2-14 2-15 2-16 2-172-182-192-202-212-222-232-242-252-262-272-28 2-29 2-30 2-312-32
Unsigned Integer Output

XTP MSP LSP
134 33 321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I
234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
5-65
~ CY7C510
~~~~NDUcrOR =======================================================================
Electrical Characteristics Over Operating Rangel4]
VOH Output HIGH Voltage Vcc = Min.,IOH = -O.4mA 2.4 V
VOL Output LOW Voltage Vce = Min., IOL = 4.0 rnA 0.4 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IOH Output HIGH Current Vce = Min., VOH = 2.4V -0.4 rnA
IOL Output LOW Current V CC = Min., VOL = 0.4V 4.0 rnA
IIX Input Leakage Current GND ~ VI ~ Vcc -10 +10 p.A
II Input Current, Max. Input Voltage Vcc = Max., VIN = 7.0V 10 rnA
IOS[I] Output Short Circuit Current VCC = Max., VOUT = 0.5V -3 -30 rnA
IOZL Output OFF (Hi-Z) Current Vce = Max., OE = 2.0V -25 p.A
IOZH Output OFF (Hi-Z) Current V CC = Max., OE = 2.0V 25 p.A
Vcc = Max.,
Icc (Q1)[2] Supply Current (Quiescent) 30 rnA
VIN = [GND to vId or [VIH to Vcd
Vce = Max Commercial 20
Icc (Q2)[2] Supply Current (Quiescent) rnA
Vcc ~ VIN ~ 3.85V
Military 25
0.4V ~ VIN ~ GND
Icc (Max.)[2] Supply Current l Commercial Vcc = Max., fCLK = lOMHz

100
rnA
I Military 110
Capacitance [3]
pF
COUT
Notes:
1. Not more than one output should be tested at a time. Duration of the 3. Tested initially and after any design or process changes that may
short circuit should not be more than one second. affect these parameters.
2. For Icc measurements, the outputs are three-stated. Two quiescent 4. See the last page of this specification for Group A subgroup testing
figures are given for different input voltage ranges. To calculate Icc at information.
any given clock frequency, use 30 rnA + Icc (A. C.), where Icc
(AC.) = (7 rnA/MHz) X Clock Frequency for the Commercial tem-
perature range. Icc (A. C.) = (8 rnA/MHz) X Clock Frequency for
Military temperature range.
Output Loads Used for A.C. Performance Characteristics

Normal Load (Load 1) Three-State Delay Load (Load 2)
R3
R1
102S.n TO SOO.n
n
SV OUTPUT~
.L
'4
OUTPUT PIN_...L
P V
40pr I R2
817.n 5 '
0057-5
0057-4
455.n
OUTPUT ~ 2.22V
0057-6
5-66
~ CY7C510
~ ~~~DUcrOR =======================================================================
7C510-45 7C51055 7C51065 7C51075
tMA Multiply Accumulate Time 45 55 65 75 ns
ts Setup Time 20 20 25 25 ns
tpw Clock Pulse Width 25 25 30 30 ns
tpDP Output Clock to P 30 30 35 35 ns
tpDY Output Clock to Y 30 30 35 35 ns
tpHZ OEX, OEM to P; HIGHtoZ 25 25 30 30 ns
tpLZ OEL to Y (Disable Time) LOWtoZ 25 25 30 30 ns
tPZH
tPZL
tHCL
Test Waveforms
OEX, OEM to P;
OEL to Y (Enable Time)
Relative Hold Time
TEST
ZtoHIGH
ZtoLOW
Vx
0
30
30
0
OUTPUT WAVEF'ORM - MEASUREMENT LEVEL

30
30
0
35
35
35
35
ns
ns
ns

VOH
ALLtpo's Vee *1.5V
VOL
tpHZ O.OV
VOH
kO.
....i
5V
O.OV
2.6V
tpLZ 2.6V
VOL o.5V -:rJ
O.OV
~VOH
1.5V
tpZH
O.OV
2.6V
tpZL 2.6V
~VOL
0057-7
Setup and Hold Time Pulse Width
DATA
iNPUT
xxxt~1:=~JXXX:v LOW-HiGH-LOW
PULSE
- L Tpw
=}-------
---
1.5V
~~~~~ -I----------
------------J------------------OV
1.5V
0057-9
0057-8
Notes:
1. Diagram shown for HIGH data only. Output transition may be oppo- 3. See the last page ofthis specification for Group A subgroup testing
site sense. information.
2. Cross hatched area is don't care condition.
567
~ CY7C510
~~~~~DUcrOR==========~====================================================
CY7C510 Timing Diagram
t---TpW--~
CLKX
CLKY
XIN , YIN
RND, TC
ACC, SUB
CLKP
II~;~~
OUT~~~ "P'lXI'f""lXI'f""lXI'f""lXI'f""lXI'f""lXI'f""lXI'f""lXI'f""lX""X""X""X""X""X""X""X""X""X""X""X,..,XX-X-X-X-X-X-X-X-X-X-xm:::::::::
0057-10
Preload Timing Diagram
1 4 - - - TPW - - + \
CLKP
PREL
OEX
OEM-_ _~
OEL
OUTPUT~~~~~--------~~~~~~~~~~~~~~~~~~~~~
PINS ~~:lL:~~ ________-"~~lLl~~~:lL:~~~~~~~{,JtI.~~lLl~~
0057-11
Three-State Timing Diagram

VOH
3-STATE 1.5V
CONTROL
~tpHZ- VOL
(DISABLE) ~tpZH-
(ENABLE) VOH
(HIGH LEVEL) VOH -O.5V J~ 1.SV
It:
3-STATE
OUTPUT (HIGH IMPEDANCE)
~ VOL +O.5V ~ 1.SV

VOL
(LOW LEVEL) I - - tpZL -
I - - tpLZ - ENABLE
(DISABLE) .
0057-12
5-68
~ CY7C510
~~~NDUcrOR =======================================================================

1.2 vs. SUPPLY VOLTAGE 1.4 vs. AMBIENT TEMPERATURE 30 vs OUTPUT VOLTAGE
~
5 vee l5V
25
~ TA = 25 0c -
(.) 1.0 (.) 1.2 zW
..9 ..9 0::
0:: 20
'"'"'"
0 0 :::>
w W (,)
N N
::::i 0.8 ::::i 1.0 w 15
(,)
<
::::E
<
::::E 0::
0:: 0:: :::>
0 0 0 10
z z VI
0.6 Vee =5.5V 0.8 ~
Y,N =5.0V :::>
5
1=
'"
TA = 25C :::>
0
0.4 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 0.8 1.6 2.4 3.2
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE(C) OUTPUT VOLTAGE (V)

III
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vS.OUTPUTVOLTAGE
1.3 1.6,...-----r------..., 35
>- ~ 30
1.2
(.)
zw 1.41------\-------1 5
~ . /~
z 25
-
:::>
-
1.1 w
0
w
0:: 1.2 1------"'......,-+------1
0::
0::
20
/V
:::>
------- /
L...
(,)
0 1.0 Vee =5.0V
w
!:::! V TA =25OC 1.01------\---------'''''1
~
z 15 TA =25oe-
...J
<
::::E
0.9 Vee =5.0V
iii
~ 10 /
0::
0
z 0.8
0.81------\-------1
:::>
II..
~
:::> 5 L
oV
0
0.6 L--_ _ _ ~ _____ ~
0.7
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE(V)
NORMALIZED OUTPUT DELAY NORMALIZED Icc

4.0 1.6
3.5
1.4 /
>-
j 3.0 ./ (.)
..9 //
w
0
~ 2.5 V 0
w
N
::::i
1.2
V~
:::>
II...
~
:::> 2.0
/' <
::::E
0::
0
1.0
/
0
1.5
/ Vee=5.0V
TA =250C-
z
0.8 / Vee = 5.5V
TAMB = 25C
Y,N =O,3V
1.0
o
/ 200 400 600
1
800 1000
0.6
o 5 10
I I
20
CAPACITANCE (pF') FREQUENCY (MHz)

0057-14
5-69
~ CY7C510
~~~NDUcrOR================================================================
Speed (ns) Ordering Code Package Type Operating Range
CY7C51O-45 LC L81
CY7C51O-45 JC J81
CY7C51O-45 DC D30
CY7C51O-45 GC G68
55 CY7C51O-55 PC P29 Commercial
CY7C51O-55 LC L81
CY7C51O-55 JC J81
CY7C510-55 DC D30
CY7C510-55 GC G68
CY7C51O-55 LMB L81 Military
CY7C510-55 DMB D30
CY7C51O-55 GMB G68
65 CY7C51O-65 PC P29 Commercial
CY7C51O-65 LC L81
CY7C510-65 JC J81
CY7C51O-65 DC D30
CY7C51O-65 GC G68
CY7C51O-65 DMB D30
CY7C51O-65 GMB G68
CY7C51O-75 LC LSI
CY7C51O-75 JC J81
CY7C51O-75 DC D30
CY7C51O-75 GC G68
CY7C51O-75 DMB D30
CY7C51O~75 GMB G68
5-70
~ CY7CSIO
~~NDUcrOR================================================================
DC Characteristics
VOH 1,2,3 Icc (Ql) 1,2,3
VOL 1,2,3 Icc (Q2) 1,2,3
VIR 1,2,3 IcC (Max.) 1,2,3
VIL 1,2,3
IOH 1,2,3
IOL 1,2,3

IIX 1,2,3
II 1,2,3
lOS 1,2,3
IOZL 1,2,3
IOZH 1,2,3
tMA 7,8,9,10,11
ts 7,8,9,10,11
tH 7,8,9,10,11
tpw 7,8,9,10,11
tpDP 7,8,9,10,11
tpDY 7,8,9,10,11
tPHz 7,8,9,10,11
tpLZ 7,8,9,10,11
tPZH 7,8,9,10,11
tPZL 7,8,9,10,11
tHCL 7,8,9,10,11
5-71
CY7C516
CY7C517
CYPRESS
SEMICONDUCTOR 16 x 16 Multipliers
Features
Fast Two's complement, unsigned as either two's complement or unsigned
- 38 ns clock cycle magnitude, or mixed mode magnitude numbers. Controls are pro-
(commercial) multiplication vided for rounding and format adjust-
- 42 ns clock cycle (military) CY7C516 pin compatible and ment of the full precision 32-bit prod-
functionally equivalent to uct.
Low Power
- ICC (max. at 10 MHz) Am29516, MPYOI6K, On the 7C516, individually clocked in-
100 mA (commercial) MPY016H put and output registers are provided
- ICC (max. at 10 MHz) CY7C517 pin compatible and to maximize throughput and to simpli-
110 mA (military) fy bus interfacing. On the 7C517, a sin-
functionally equivalent to
gle clock (CLK) is provided, along
Vee Margin Am29517
with three register enables. This facili-
- 5V 10%
- All parameters guaranteed Functional Description tates the use of the 7C517 in micropro-
over commercial and military grammed systems. The input and out-
The CY7C516/517 are high-speed 16 x put registers are positive edge triggered
operating temperature range 16 parallel multipliers which operate at D-type flip-flops. The output register
16 x 16 bit parallel 38 ns clocked multiply times (26 MHz may be made transparent for asynchro-
multiplication with full precision multiplication rate). The two input op- nous output.
32-bit product output erands may be independently specified
Logic Block Diagrams

CY7C516 CY7C517
V-IN/ X-IN Y-IN/LSP OUT
TCX X-IN CLKX CLKV LSP OUT TCV
CLK.>-'P---t--t-----t----'
32
FA
FT
ENP
MSP OUT/LSP OUT 0054-1

MSP OUT/LSP OUT 0054-12
Selection Guide
7C516-38 7C516-42 7C516-45 7C516-55 7C516-75
7C517-38 7C517-42 7C517-45 7C517-55 7C517-75
Maximum Multiply Time (ns) Commercial 38/58 45/65 55/75 75/100
ClockedlUnclocked Military 42/65 55/75 75/100
5-72
CY7CS16
II
5A~~NDUcrOR==================================================================


CY7CS17
Two output modes may be selected by using the output The other mode of output involves toggling of the
multiplexer control, MSPSEL. Holding MSPSEL LOW MSPSEL control, allowing both the MSP and LSP to be
causes the most significant product (MSP) to be available available for output through the dedicated 16-bit output
at the dedicated output port. The LSP is simultaneously port.
available at the bidirectional port shared with the Y -inputs.
Pin Configurations
X4 X5
X3 X6
x2 X7
XI Xs

Xo Xg
OEl X10
(ClK) ClK l XII
(ENY) ClKY X12
YO' Po X13
8 7 6 5 4 3 2 L!.J 68 67 66 65 6463 62 61 60 NC
Y1 ,P 1 X14 P15 ,P 31
Y2,P 2 X15 P14' P30 X12
Y3,P 3 ClKX (ENX) P13 P29 XII
Y4,P 4 RND P I2 P 2S X10
P11 ,P 27 Xg
Y5 ,P 5 TCX
P10 P26 Xs
Y6,P 6 TCY Pg P25 X7
Y7,P 7 vee PS,P 24 X6
Ys.P s Vee P7' P23 7C516 X5
Yg.Pg GND P6' P22 (7C517) 51 X4
GND P5, P21 X3
Y10.P 10
P4 P20 X2
Y11 ,P 11 MSPSEl
P3' P19 XI
Y12 ,P 12 FT P2P 1S Xo
Y13 ,P 13 FA Pl, P I7 OEl
Y14,P 14 OEP PO,P I6 ClK l (ClK)
Y15 ,P 15 ClKM (ENP) NC ClKY (ENY)
27 28 29 30 31 32 33 3435363738 39 40 41 4243
PO,P I6 P31 ,P 15
P1,P 17 P3o ,P 14
P2 P 1S P29 ,P 13
P3 PIg P2S ,P I2
0054-3
P4P20 P27 ,P 11
P5 ,P 21 P26 P 10
P6 P22 P25 P 9
P7 P23 P24 PS
0054-2
5-73
CY7C5161~
(;r~ CY7CS17 I.
Pin Configurations (Continued)
Pin Configuration for 68Pin Grid Array
e e e 8 E) e e
51 50 48 46 44 42 40
0
38
e
36
(0
53
e8 @eee 8
52 49
ENX
47 45 43 41 39
0) @
37
ENP
35
e
34
0 8
55 54
e
32
8 33
0 0
57 56
8 9
30 31
G 0
59 58
8 8
28 29
0 G
61 60
8 8
26 27
(2) 8
63 62
8 8
24 25
eG65 64
8 8
22 23
~(ENY)
CLKL
(CLK)
8 8
ee
67 66 20 21
ee 1
9 8
3 5 7 9
8 11
ee13 15
8 8
18 19
8 9
2 4
eeeeeee
6 8 10 12 14 16 17
0054-16
5-74
CY7C516
~RESS
.nEMICONDUcrOR =======================================================================
CY7C517

guidelines, not tested.)
Ambient Temperature Under Bias .... - 55C to + 125C Commercial OC to +70C 5V 10%
Supply Voltage to Ground Potential .... -0.5V to + 7.0V Military [11 - 55C to + 125C 5V 10%
Note:
DC Input Voltage ................... -0.5V to + 7.0V
DC Voltage Applied to Outputs ..... - O. 5V to Vcc Max.
Output Current, into Outputs (low) .............. 10 rnA
Static Discharge Voltage ..................... > 1000V
Pin Definitions
Signal

Signal
XIS-O X-Input Data. This 16-bit number may be TCY Two's Complement Control Y. V-Input data are
interpreted as two's complement or unsigned interpeted as two's complement when TCY is
magnitude. HIGH. TCY LOW means the data are
interpreted as unsigned magnitude.
I/O Y-Input/LSP Output Data. This 16-bit number
may be interpreted as two's complement or P31-161PlS-0 Output Port Three-State Control.
unsigned magnitude. The Y-input port may be When OEP is LOW, the output port is enabled;
mUltiplexed with the LSP output (PIS-O). when OEP is HIGH, the drivers are in a high
impedance state.
P3I-I6 o Output Data. This 16-bit port may carry either
(PIS-O) the MSP (P3I-I6) or the LSP (PIS-O). Y-in/PlS-0 Port Three State Control. When
OEL is LOW, the timeshared port is enabled
FT The MSP and LSP registers are made for LSP output. When OEL is HIGH, the
transparent (asynchronous operation) if FT is output drivers are in a high impedance state.
HIGH. This is required for Y-input.
FA Format Adjust Control. If FA is HIGH, a full CY7C516 Only
32-bit product is output. If FA is LOW, a left- CLKX I X-Register Clock. X-input data and TCX are
shifted product is output, with the sign bit latched in at the rising edge of CLKX.
replicated in the LSP. FA must be HIGH for
two's complement integer, unsigned magnitude, CLKY V-Register Clock. V-input data and TCY are
and mixed mode multiplication. latched in at the rising edge of CLKY.
Output Multiplexer Control. When MSPSEL is CLKM MSP Register Clock. The most significant
LOW, the MSP is available for output at the product (MSP) is latched in at the MSP
MSP output port, and the LSP is available at Register at the rising edge of CLKM.
the Y-input/LSP output port. When MSPSEL
is HIGH, the LSP is available at both ports CLKL LSP Register Clock. The least significant
(above) and the MSP is not available. product (LSP) is latched in at the LSP Register
at the rising edge of CLKL.
RND Round Control. When RND is HIGH, a one is
added to the MSB of the LSP. This position is CY7C517 Only
dependent on the FA control; FA = HIGH CLK I Clock. All enabled registers latch in their data
means RND adds to the 2- 15 bit (PIS), at the rising edge of CLK.
FA = LOW means RND adds to the 2- 16 bit ENX X-Register Enable. When ENX is LOW, the x-
(PI4). Register is enabled. X-input data and TCX will
TCX Two's Complement Control X. X-input data are be latched in at the rising edge of CLK when
interpreted as two's complement when TCX is the register is enabled. When ENX is HIGH,
HIGH. TCX LOW means the data are the X-Register is in hold mode.
interpreted as unsigned magnitude. X-Register Enable. ENY enables the
V-Register. (See ENX.)
ENP Product Register Enable. ENP enables the
product register. Both the MSP and LSP
Sections are enabled by ENP. (See ENX.)
5-75
CY7C516
fill
I
. CY7C517 I I
~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Input Formats (All Devices)
Fractional Two's Complement Input Format

Tex, TCY = 1
Xus YIN
115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I
-20 2- 1 2- 2 2-3 2-4 2- 5 2-6 2- 7 2- 8 2-9 2- 10 2-11 2-122-132-142-15 -20 2- 1 2-2 2-3 2-4 2-5 2-6 2- 7 2-8 2-9 2-10 2-11 2-122-132-142-15
(Sign) (Sign)
Integer Two's Complement Input Format

Tex, TCY = 1
115 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I
_2 15 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 _2 15 214 213 212 211 2 10 29 28 27 26 25 24 2 3 22 21 20
(Sign) (Sign)
Unsigned Fractional Input Format

Tex, TCY =0
115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-11 2-122-132-142-152-16 2-1 2- 2 2-3 2-4 2-5 2-6 2- 7 2-8 2-9 2-10 2- 11 2-122-132-142-152-16
Unsigned Integer Input Format

Tex, TCY = 0
XIN YIN
115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 2 15 214 213 212 211 2 10 29 28 27 26 2 5 24 23 22 21 20
5-76
CY7C516
5A~~NDUcrOR =====================================================================
..
Output Formats (All Devices)

CY7C517
Fractional Two's Complement (Shifted)* Format

FA = 0
MSP LSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1
_20 2-1 2- 2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-112-12 2-13 2-142-15 -20 2-162-172-182-192-202-212-222-232-242-252-262-27 2-28 2-29 2-30
(Sign) (Sign)
Fractional Two's Complement Output

FA = 1
MSP LSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1
_21 20 2- 1 2- 2 2-3 2-4 2- 5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-13 2-14 2-152-162-172-182-192-202-212-222-232-242-252-26 2-27 2-28 2-29 2-30 ~
(Sign) .:.
Integer Two's Complement Output

FA = 1
MSP LSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 ~I1_5__1_4__13__1_2__1_1__10__9______7__6_____4___3___2_____0~1
_2 31 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
Unsigned Fractional Output

FA = 1
MSP LSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 ,-11_5_14_1_3_1_2_11_1_0_9_ _ _
7 _6_5_4_ _3_2_ _ _0--,1
Unsigned Integer Output

FA = 1
MSP LSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 ,-11_5_14_1_3_1_2_11_1_0_9_ _ _ 7 _6_5_4_ _3_2_ _ _0--,1
231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
"In this format an overflow occurs in the attempted multiplication ofthe two's complement number 1.000 ... (-1) with itself, yielding a product of 1.000
... or-1.
5-77
CY7C516
WA . .
~~UcrOR==================================================================
CY7C517

VOH Output HIGH Voltage V CC = Min., IOH = - 0.4 mA 2.4 V
VOL Output LOW Voltage Vcc=Min., IOL=4.0mA 0.4 V
VIH Input HIGH Voltage 2.0 V
10H Output HIGH Current VCC=Min., VOH=2.4V -0.4 mA
10L Output LOW Current V CC = Min., VOL = 0.4V 4.0 mA
IIX Input Leakage Current VSS ::;; VIN::;; Vcc, Vcc = Max. -10 10 p.A
10s[1] Output Short Circuit Current VCC=Max., VOUT = OV -3 -30 mA
10ZL Output OFF (Hi-Z) Current V CC = Max., OE = 2.0V -25 p.A
10ZH Output OFF (Hi-Z) Current V CC = Max., OE = 2.0V 25 p.A
Commercial (-38) GND ::;; VIN ::;; VIL or 40
Supply Current VIH ::;; VIN::;; Vcc;
ICC (Qt)[2] Military (-42) 45 mA
(Quiescent) OE = HIGH
All Others 30
Supply Current Commercial GND ::;; VIN ::;; 0.4Vor 20

Icc (Q2)[2] mA
(Quiescent) Military 3.85V::;; VIN::;; Vcc; OE = HIGH 25
Commercial Vcc = Max., fCLK = 10 MHz; 100
ICC (Max.)[2] Supply Current mA
OE = HIGH 110
Military
Capacitance [3]
pF
Vcc = 5.0V 10
COUT Output Capacitance
Notes:
1. Not more than one output should be tested at a time. Duration of the 3. Tested initally and after any design or process changes that may affect
short circuit should not be more than one second. these parameters.
2. Two quiescent figures are given for different input voltage ranges. To 4. See the last page of this specification for Group A subgroup testing
calculate Icc at any given clock frequency, use 30 mA + Icc (A.C.), information.
where Icc (A.C.) = (7 mAIMHz) X Clock Frequency for the Com-
mercial temperature range. Icc (A.C.) = (8 mAIMHz) X Clock
Frequency for the Military temperature range.
Output Loads Used for A.C. Performance Characteristics

Normal Load (Load 1) Three-State Delay Load (Load 2)
R1 TO SOO.n
1025.0. OUTPUT~
-L v,
OUTPSu~ft PIN _po
5 pr
J..
40pF I
- -
R2
817.0.
4 0054-5
0054-4
45S.n
OUTPUT ~ 2.22V
0054-6
5-78
~5n~NDUcrOR ==================================
CY7C516
I CY7C517
:1
7C51638 7C51642 7C51645 7C51655 7C51675
Test 7C51738 7C51742 7C51745 7C51755 7C51775 Units
Parameters Description
Conditions
MUC Unclocked Multiply Time 58 65 65 75 100 ns
MC Clocked Multiply Time 38 42 45 55 75 ns
S Xi, Yi, RND, TCX, TCY Set-up Time 7 8 20 20 25 ns
H Xi, Yi, RND, TCX, TCY Hold Time 3 3 3 3 3 ns
SE ENX, ENY, ENP Set-up Time (7C517 Only) 10 15 20 20 25 ns
Load 1
HE ENX, ENY, ENP Hold Time (7C517 Only) 3 3 3 3 3 ns
PWH, tpwL Clock Pulse Width (HIGH and LOW) 10 10 20 25 30 ns

PDSEL MSPSEL to Product Out 18 21 25 25 30 ns
PDP Output Clock to P 25 30 30 30 35 ns
PDY Output Clock to Y 25 30 30 30 35 ns
PHZ HIGHtoZ 15 17 25 25 30 ns
OEP Disable Time
PLZ LOWtoZ 15 17 25 25 30 ns
PZH ZtoHIGH 23 25 30 30 35 ns
OEP Enable Time
PZL ZtoLOW 23 25 30 30 35 ns
Load 2
PHZ HIGHtoZ 15 17 25 25 30 ns
OEL Disable Time
PLZ LOWtoZ 15 17 25 25 30 ns
PZH ZtoHIGH 23 25 30 30 35 ns
OEL Enable Time
PZL ZtoLOW 23 25 30 30 35 ns
Clock Low Hold Time CLKXY 0 0
HCL Load 1 0 0 0 ns
Relative to CLKMLlll
Notes:
1. To ensure that the correct product is entered in the output registers, 2. See the last page of this specification for Group A subgroup testing
new data may not be entered into the input registers before the output information.
registers have been clocked.
Test Waveforms (All Devices)

TEST Vx OUTPUT WAVEI'ORM- MEASUREMENT LEVEL
ALL tpo's Vex;

VOH~
V 1.5V
OL
tpHZ o.OV VOH~

O.OV
2.6V
~2.6V
tpLZ VOL o. V
o.OV ~VOH
1.5V
tpZH
O.OV
2.6V 2.6V~
tpzL 1.5V VOL
0054-7
Setup and Hold Time (All Devices) Pulse Width (All Devices)
'::::1@[1;::'"~~' LOW-HIG~-LOW_
PULSE 1 -1.5V= ~
;~~~~ _________ J ~~5V
TPWH ---~-I.---- TPWL
~_r~ ____________ ~ 0054-9
Notes: 0054-8
1. Diagram shown for HIGH data only. Output transition may be oppo- 2. Cross hatched area is don't care condition.
site sense.
5-79
~ CY7CS1~
~)r;~~ucr~=================================================C=Y==7=C=5=1=
Three-State Timing Diagram
VOH
3-STATE 1.5V
CONTROL
tpHZ- VOL
(DISABLE) I--tpZH-
(ENABLE) VOH
(HIGH lEVEL) VOH-0.5V 1.5V
3-STATE (HIGH It.lPEDANCE)

OUTPUT
1 VOL +0.5V 1.5V
I--tpZL- VOL
(lOW lEVEL) I--tpLZ- ENA BlE)
(DISABLE) .
0054-10
Timing Diagram
7CSt6
I---- Tpw ----l
ClKX
ClKY I I
XINYIN
TCX. TCY.
RNO
ClKl
OUTPUT
Y
ClKt.l
ClKl
t.lSPSEl
OUTPUT
P
Tt.lUC
0054-11
Timing Diagram
7CSt7
I---- Tpw ----l
ClK
I I
ENX
ENY
XIN YIN'
TCX. TCY.
RNO
ENP
OUTPUT
Y
t.lSPSEl
OUTPUT
P
Tt.lUC
0054-15
5-80
r;n
I
I
.
~~u~==================================================================
CY7C516
CY7C517
.Typical DC. and AC Characteristics

VS. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE
VS.
12~--~----~--~--~ 1.4~-------r------------' ~~--~--~~--,-----,
1.0 12
1
I-
z
25
~ ~
101
0:: 20
0::
:0 0 ;:)
I~ 101 <.>
,"~
,,~
:2
0.8
~
:2
1.0 101
<.>
0::
;:)
15
,0:: 0:: 0
,~ 0 VI
10
0.6 z 0.8 I-
;:)
V1N =5.0V 5
TA =25OC ~
;:)
0
0.4- 0.6
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.8 1.6 2.4 32

SUPPLY VOLTAGE
VS. AMBIENT TEMPERATURE
VS. VS. OUTPUT VOLTAGE
1.3 1.6.---------r------------, 35
~ ~
12 1.41------1-------1 !.
I- L ~
z 25
- 101 ",
-
0::
,.,..,.,--~
121-----"-.....,...-1-------1 0::
20 ~
;:)
1.0
", TA =25OC 1.0 I-----+-----~
<.>
~
z 15 IL Vcc =5.0V
TA =250 C-
0.9 Vcc= 5.0V
iii
I- 10 /
/
;:)
0.8
0.81------1-------1 ~
;:) 5
0.6 L..-_ _ _.....-_ _ _ _ _ _- - '
0
I{
0.7 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE(V)
NORMALIZED CURRENT DELAY NORMALIZED Icc

OUTPUT LOADING
VI. FREQUENCY
VS.
4.0 1.6
/
3.0 ./ ji
./
/'
V 12
2.5
2.0
1.5 V
~/'
Vcc= S.OV
I
z
1.0
0.8 /
V
V~
Vcc =S.5V
TA =250C-
/ TA=jSOC-
1j
V =Oj3V
1.0 0.6
o 200 400 600 800 1000 o 5 10 20
0054-17
5-81
hi
CY7.C516~
(in~~~UcrOR================================================================1
CY7C517
Ordering Information II
Speed Ordering Package Operating Speed Ordering Package Operating

(ns) Code Type Range (ns) Code Type Range
CY7C517-38PC CY7C517-55PC
CY7C516-38LC L81 CY7C516-55LC L81
CY7C517-38LC CY7C517-55LC
CY7C516-38JC J81 CY7C516-55JC J81
CY7C517-38JC CY7C517-55JC I
CY7C516-380C 030 CY7C516-550C 030

CY7C517-38DC CY7C517-550C
CY7C516-38GC G68 CY7C516-55GC 068
CY7C517-38GC CY7C517-55GC
42 CY7C516-42LMB L81 Military CY7C516-55LMB L81 Military
CY7C517-42LMB CY7C517-55LMB
CY7C516-420MB 030 CY7C516-550MB 030
CY7C517-420MB CY7C517-55DMB
CY7C516-42GMB G68 CY7C516-55GMB 068
CY7C517-42GMB CY7C517-550MB
CY7C517 -45PC CY7C517-75PC
CY7C516-45LC L81 CY7C516-75LC L81
CY7C517-45LC CY7C517-75LC
CY7C516-45JC J81 CY7C516-75JC J81
CY7C517-45JC CY7C517-75JC
CY7C516-450C 030 CY7C516-75DC 030
CY7C517-450C CY7C517-750C
CY7C516-45GC G68 CY7C516-75GC G68
CY7C517-45GC CY7C517-75GC
CY7C516-75LMB LS1 Military
CY7C517-75LMB
CY7C516-750MB 030
CY7C517-750MB
CY7C516-75GMB G68
CY7C517-75GMB
5-82
CY7C516
5A~~~UcrOR================================================================
..
CY7C517

DC Characteristics
VOH 1,2,3 Icc (Q2) 1,2,3
VOL 1,2,3 Icc (Max.) 1,2,3
VIH 1,2,3
VIL 1,2,3
IOH 1,2,3
IOL 1,2,3

IIX 1,2,3
los 1,2,3
IOZL 1,2,3
IOZH 1,2,3
ICC (Qt) 1,2,3
. Switching Characteristics
tMUC 7,8,9,10,11
tMc 7,8,9,10,11
ts 7,8,9,10,11
tH 7,8,9,10,11
tSE 7,8,9,10,11
tHE 7,8,9,10,11
tpwH, tpwL 7,8,9,10,11
tpDSEL 7,8,9,10,11
tpDP 7,8,9,10,11
tpDY 7,8,9,10,11
tpHZ 7,8,9,10,11
tpLZ 7,8,9,10,11
tpZH 7,8,9,10,11
tpZL 7,8,9,10,11
tpHZ 7,8,9,10,11
tpLZ 7,8,9,10,11
tpZH 7,8,9,10,11
tpZL 7,8,9,10,11
tHCL 7,8,9,10,11
5-83
CY7C901
CYPRESS
SEMICONDUCTOR CMOS Four-Bit Slice
Features
Fast Pin Compatible and Functional that are usually inputs from a microin-
CY7C901-23 has a 23 ns Equivalent to Am2901B, C struction register.
Read Modify-Write Cycle; The CY7C901 is expandable in 4-bit
Commercial 25% Faster Functional Description increments, has three-state data out-
than "C" Spec 2901 The CY7C901 is a high-speed, expand- puts as well as flag output, and can use
CY7C901-27 has a 27 ns able, 4-bit wide ALU that can be used either a full look ahead carry or a rip-
Read Modify-Write Cycle; to implement the arithmetic section of ple carry.
Military 15% Faster a CPU, peripheral controller, or pro-
than "C" Spec 2901 The CY7C901 is a pin compatible,
grammable controller. The instruction
functional equivalent, improved per-
Low Power set ofthe CY7C901 is basic but yet so
formance replacement for the Am2901.
70 mA (commercial) versatile that it can emulate the ALU
90 mA (military) of almost any digital computer. The CY7C901 is fabricated using an
advanced 1.2 micron CMOS process
Vee 5V 10% The CY7C901, as illustrated in the
that eliminates latchup, results in ESD
Commercial and military block diagram, consists of a 16-word
protection over 2000V and achieves su-
by 4-bit dual-port RAM register file, a
Eight Function ALU perior performance with low power
4-bit ALU and the required data ma-
dissipation.
Immitely expandable in 4-bit nipulation and control logic.
increments
The operation performed is determined
Four Status Flags: by nine input control lines (10 to Is)
Carry, overflow, negative, zero
greater than 2000V static
discharge voltage
Top View
CLOCK -----1
'A'IREADI
ADDRESS
'B'
(READIWRITEI
ADDRESS
CARRY IN
OUTPUT
0030-2
ENABLE
DATA OUT 0030-1
5-84
~ CY7C901
~~~~UcrOR=====================================================================
Selection Guide See last page for ordering information.
Read Modify-Write Cycle (Min.) in ns Operating lee (Max.) in mA Operating Range Part Number
23 80 Commercial CY7C901-23
27 90 Military CY7C901-27
31 70 Commercial CY7C901-31
32 90 Military CY7C901-32
Maximum Ratings
Power Applied .................... - 55C to + 125C Latchup Current (Outputs) .................. > 200 rnA

(Pin 10 to Pin 30) .................... - 0.5V to + 7.0V Operating Range
Range Vee
in High Z State ...................... - o. 5V to + 7.0V Temperature
Output Current into Outputs (Low) ............. 30 rnA Military [I] - 55C to + 125C 5V 10%
Note:
Pin Definitions
Signal Signal
Ao-A3 These 4 address lines select one of the registers in Q3 I/O Outputs: When the destination code on lines
the stack and output its contents on the (internal) RAM3 16,7,8 indicates a shift left (UP) operation the
A port. (Cont.) three-state outputs are enabled and the MSB of
Bo-B3 These 4 address lines select one of the registers in the Q register is output on the Q3 pin and the
the stack and output is contents on the (internal) MSB of the ALU output (F3) is output on the
B port. This can also be the destination address RAM 3 pin.
when data is written back into the register file. Inputs: When the destination code indicates a
10-18 These 9 instruction lines select the ALU data shift right (DOWN) the pins are the data inputs
sources (10,1,2), the operation to be performed to the MSB of the Q register and the MSB of the
(13, 4, 5) and what data is to be written into either RAM.
the Q register or the register file (16, 7, 8). Qo I/O These two lines are bidirectional and function in a
00-03 These are 4 data input lines that may be selected RAMo manner similar to the Q3 and RAM3 lines, except
by the 10,1, 2 lines as inputs to the ALU. that they are the LSB of the Q register and RAM.
Y0-Y3 0 These are three-state data output lines that, when Cn I The carry-in to the internal ALU.
enabled, output either the output ofthe ALU or en +4 0 The carry-out from the internal ALU.
the data in the A latches, as determined by the '0, P 0 The carry generate and the carry propagate
code on the 16, 7, 8 lines. outputs of the ALU, which may be used to
OE Output Enable. This is an active LOW input that perform a carry look-ahead operation over the 4-
controls the Y0-Y3 outputs. When this signal is bits of the ALU.
LOW the Y outputs are enabled and when it is OVR 0 Overflow. This signal is logically the exclusive-
HIGH they are in the high impedance state. OR of the carry-in and the carry-out of the MSB
CP Clock Input. The LOW level of the clock write of the ALU. This pin indicates that the result of
data to the 16 x 4 RAM. The HIGH level of the the ALU operation has exceeded the capacity of
clock writes data from the RAM to the A-port the machine. It is valid only for the sign bit and
and B-port latches. The operation of the Q assumes two's complement coding for negative
register is similar. Data is entered into the master numbers.
latch on the LOW level of the clock and F = 0 0 Open drain output that goes HIGH if the data on
transferred from master to slave when the clock is the ALU outputs (Fo, 1,2, 3) are all LOW. It
HIGH. indicates that the result of an ALU operation is
I/O These two lines are bidirectional and are zero (positive logic).
controlled by the 16, 7, 8 inputs. ~lectrically they F3 0 The most significant bit of the ALU output.
are three-state output drivers connected to the
TTL compatible CMOS inputs.
5-85
RAMo
~~
./. !- I T
1
T
~
f(.
RAM3
~
-
'-- 3-IN 3-IN 3-IN 3_~A
A WORD
A DDRESS
MUX MUX MUX MUX '" B WORD
ADDRESS
~ I I I
.~o,
~~r- ~1
Do 0, 02 03
00
~B,
1'Lf.;'N! 1=1'+1 I=Il:"'I=I'~,J~A

A, >--- 16-WORD BY 4-BIT 2-PORT RAM
A2>---
DATA OUT RAM DATA OUT -<B2
AJ>--- AO A, A2 AJ WE EN. BO 8, B2 B3 -<B3 MUX MUX MUX MUX
I
CLOCK E A LATCH I I, B LATCH
Do 0,
a REGISTER
02 03
I ALU
I~o B,
CP CP OEN
Ao A, AZA31 B2 B3 IDESTINATION
DECODE
I 00 a, Oz 03
,t
~~.
DIRE
DATA
Dz
INPUT S 0,
Do
MUX MUX MUX MUX MUX MUX MUX MUX ~

ALU ~Io
SOURCE
OPERAND :--<1,
DECODE ~Iz
3 ALU I Ro R, Rz R3 So S, S2 S3 G
a
4 FUNCTIONI ;t P
DECODE ARITHMETIC LOGIC UNIT (ALU)
Is Cn + 4
FO Fl F2 F3 OVR
I I J I
1 I I
T 1 1
Q.'~"O'"
'"""-----l I
~
F3
MUX MUX MUX MUX J NOTE: LSB IS NUMBERED "0"; MSB IS NUMBERED "3"
;V X BIDIRECTIONAL
~ , ~ UNIDIRECTIONAL
- {. ~
Yo Y,
0030-3
II~ CY7C901
'111.r.~NDUCTOR =====================================================
Functional Tables
MicroCode ALUSource MicroCode
Operands ALU
Mnemonic Octal Function Symbol
Mnemonic Octal Is 4 13 Code
12 11 10 R S
Code ADD L L L 0 RPlus S R+S
AQ L L L 0 A Q SUBR L L H 1 SMinusR S-R
AB L L H 1 A B SUBS L H L 2 RMinusS R-S
ZQ L H L 2 0 Q OR L H H 3 RORS R VS
ZB L H H 3 0 B AND H L L 4 RANDS RAS
ZA H L L 4 0 A NOTRS H L H 5 RANDS RAS
DA H L H 5 D A EXOR H H L 6 REX-ORS RS
DQ H H L 6 D Q EXNOR H H H 7 REX-NORS ~
DZ H H H 7 D 0 Figure 3. ALU Function Control
Figure 2. ALU Source Operand Control

MicroCode QReg. RAM
RAM Function Q Shifter
Mnemonic Function Y Shifter
Octal Output
Is 17 16 Code Shift Load Shift Load RAMo RAM3 Qo Q3
QREG L L L 0 X None None F~Q F X X X X
NOP L L H 1 X None X None F X X X X
RAMA L H L 2 None F~B X None A X X X X
RAMF L H H 3 None F~B X None F X X X X
RAMQD H L L 4 DOWN F/2 ~ B DOWN Q/2 ~ Q F Fo IN3 Qo IN3
RAMD H L H 5 DOWN F/2 ~ B X None F Fo I N3 Qo X
RAMQU H H L 6 UP 2F ~ B UP 2Q ~ Q F INo F3 INo Q3
RAMU H H H 7 UP 2F ~ B X None F INo F3 X Q3
x = Don't care. Electrically, the input shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
A = Register Addressed by A inputs.
B = Register Addressed by B inputs.
UP is toward MSB, DOWN is toward LSB.
Figure 4. ALU Destination Control
1210 Octal 0 1 2 3 4 5 6 7
ALU
Source
Octal ALU
1543 Function A,Q A,B O,Q O,B O,A D,A D,Q D,O
0 Cn = L A+Q A+B Q B A D+A D+Q D
Rplus S
Cn = H A+Q+l A+B+l Q+l B+l A+l O+A+l O+Q+l D+l
1 Cn = L Q-A-l B-A-l Q-l B-1 A-I A-D-l Q-O-l -0-1
SminusR
Cn = H Q-A B-A Q B A A-D Q-O -D
2 Cn = L A-Q-l A-B-l -Q-l -B-1 -A-l D-A-l D-Q-l D-l
RminusS
Cn = H A-Q A-B -Q -B -A D-A D-Q D
3 RORS AVQ AVB Q B A DVA DVQ D
4 RANDS AAQ AAB 0 0 0 DAA DAQ 0
5 RANDS AAQ AAB Q B A DAA DAQ 0
6 REXORS AQ AB Q B A DA DQ D
7 REXNORS AQ AB Q B A DA DQ D
+ = Plus; - = Minus; V = OR; A = AND; = EX-OR
Figure 5. Source Operand and ALU Function Matrix
587
5r~cx:wocroR CY7C901~
Description of Architecture
General Description 10,1,2 inputs as shown in Figure 2. This configuration of
A block diagram of the CY7C901 is shown in Figure 1. multiplexers on the ALU Rand 8 inputs enables the user
The circuit is a 4-bit slice consisting of a register file (16 x 4 to select eight pairs of combinations of A, B, D, Q and "0"
dual port RAM), the ALU, the Q register and the neces- (unse1ected) inputs as 4-bits operands to the ALU. The
sary control logic. It is expandable in 4-bit increments. logical and arithmetic operations performed by the ALU
upon the data present at its Rand 8 inputs are tabulated in
RAM Figur~}. The ALU has a carry-in (Cn) input, carry-propa-
The RAM is addressed by two 4-bit address fields (Ao-A3, gate (P) output, carry-generate (0) output, carry-out
Bo- B3) that cause the data to appear at the A or B (inter- (Cn + 4) and overflow (OVR) pins to enable the user to (1)
nal) ports. If the A and B addresses are the same, the data speed up arithmetic operations by implementing carry
at the A and B ports will be identical. look-ahead logic and (2) determine if an arithmetic over-
flow has occurred.
New data is written into the RAM location specified by the
B address when the RAM write enable (RAM EN) is ac- The ALU data outputs (Fo 1 2 3) are routed to the RAM,
tive and the clock input is LOW. Each of the four RAM the Q register inputs and the y'outputs under control of
inputs is driven by a 3-input mUltiplexer that allows the the 16, 7, 8 control signal inputs as shown in Figure 4. In
~utputs of the ALU (Fo, 1,2, 3,) to be shifted one bit posi- addition, the M8B of the ALU is output as F3 so that the
tion to the left, the right, or not to be shifted. The other user can examine the sign bit without enabling the three-
inputs to the multiplexer are from the RAM3 and RAMo state outputs. The F = 0 output, used for zero detection, is
I/O pins. HIGH when all bits of the F output are LOW. It is an
open-drain output which may be wire OR'ed across multi-
For a shift left (up) operation, the RAM3 output buffer is ple 7C901 processor slices.
enabled and the RAMo multiplexer input is enabled. For a
shift right (down) operation the RAMo output buffer is Q Register
enabled and the RAM3 multiplexer input is enabled. The Q register functions as an accumulator or temporary
The data to be written into the RAM is applied to the D storage register. Physically it is a 4-bit register implement-
inputs of the CY7C901 and is passed (unchanged) through ed with master-slave latches. The inputs to the Q register
the ALU to the RAM location addressed by the B word are driven by the outputs from four 3-input multiplexers
address. under control of the 16, 7,8 inputs. The Qo and Q31/0 pins
function in a manner similar to the RAMo and RAM3
The outputs of the RAM A and B ports drive separate 4- pins. The other inputs to the mUltiplexer enable the con-
bit latches that are enabled (follow the RAM data) when tents of the Q register to be shifted up or down, or the
the clock is HIGH. The outputs of the A latches go to outputs of the ALU to be entered into the master latches.
three multiplexers whose outputs drive the two inputs to Data is entered into the master latches when the clock is
the ALU (Ro, 1, 2, 3) and (80, I, 2, 3) and the (Yo, 1, 2, 3) chip LOW and transferred from master to slave (output) when
outputs. the clock changes from LOW to HIGH.
ALU (Arithmetic Logic Unit) ALU Source Operand and ALU Functions
The ALU can perform three arithmetic and five logical The ALU source operands and ALU function matrix is
operations on two 4-bit input words, Rand 8. The R inputs summarized in Figure 5 and separated by logic operation
are driven from four 2-input mUltiplexers whose inputs are or arithmetic operation in Figures 6 and 7, respectively.
from either the (RAM) A-port or the external data (D) The 10, 1, 2 lines select eight pairs of source operands and
inputs. The 8 inputs are driven from four 3-input multi- the 13, 4, S lines select the operation to be performed. The
plexers whose inputs are from the A-port, the B-port, or carry-in (Cn) signal affects the arithmetic result and the
the Q register. Both mUltiplexers are controlled by the internal flags; not the logical operations.
5-88
~ CY7C901
~~~NDUcrOR =====================================================================
Conventional Addition and PassIncrement/ Subtraction
Decrement Recall that in two's complement integer coding - 1 is
When the carry-in is HIGH and either a conventional ad- equal to all ones and that in one's complement integer cod-
dition or a PASS operation is performed, one (1) is added ing zero is equal to all ones. To convert a positive integer to
to the result. If the DECREMENT operation is performed its two's complement (negative) equivalent, invert (comple-
when the carry-in is LOW, the value of the operand is ment) the number and add 1 to it; i.e., TWC = ONC + 1.
reduced by one. However, when the same operation is per- In Figure 7 the symbol - Q represents the two's comple-
formed when the carry-in is HIGH, it nullifies the DEC- ment of Q so that the one's complement of Q is then
REMENT operation so that the result is equivalent to the -Q -1.
PASS operation.
Octal Cn = 0 (Low) Cn = 1 (High)
Octal 1543, 1210
Group Function Group Function Group Function
1543, 1210
00 A+Q A+Q+1
40 AND AAQ
01 A+B ADD plus A+B+1

41 AAB ADD
05 D+A one D+A+1
45 DAA
06 D+Q D+Q+1
46 DAQ
02 Q Q+1
30 OR AVQ
03 B B+1
31 AVB PASS Increment
04 A A+1
35 DVA
07 D D+1
36 DVQ
12 Q-1 Q
60 EX-OR AQ B-1
13 B
61 AB Decrement PASS
14 A-I A
65 DA D-1
27 D
66 DQ
22 -Q-1 -Q
70 EX-NOR A"VQ 23 -B-1 2's Compo -B
71 AB l's Compo -A-1
24 (Negate) -A
75 DA -D-1 -D
17
76 DVQ
10 Q-A-1 Q-A
72 INVERT Q 11 B-A-1 B-A
73 B 15 A-D-1 A-D
74 A Q-D-1 Subtract Q-D
16 Subtract
77 0 20 (l's Comp.) A-Q-1 (2's Comp.) A-Q
62 PASS Q 21 A-B-1 A-B
63 B 25 D-A-1 D-A
64 A 26 D-Q-1 D-Q
67 D Figure 7. ALU Arithmetic Mode Functions
32 PASS Q
33 B
34 A
37 D
42 "ZERO" 0
43 0
44 0
47 0
50 MASK AAQ
51 AAB
55 OAA
56 I>AQ
Figure 6. ALU Logic Mode Functions
5-89
~ CiPRESS CY7C901
~~~IOO~UcrOR==================================================================
Logic Functions for G, P, Cn + 4, and OVR Def"mitions (+ = OR)
The four signals G, P, Cn + 4, and OVR are designed to Po = Ro + So Go = RoSo
indicate carry and overflow conditions when the CY7C901 P1 = R1 + 81 Gl = R1S1
is in the add or subtract mode. The table below indicates P2 = R2 + S2 G2 = R2S2
the logic equations for these four signals for each of the P3 = R3 + S3 G3 = R3S3
eight ALU functions. The Rand S inputs are the two in C4 = G3 + P3G2 + P3P2G1 + P3 P 2GO + P3P2P1 P oCn
puts selected according to Figure 2. C3 = G2 + P2G 1 + P2 P 1G O + P2 P 1P OCn
1543 Function Ii G CN+4 OVR

0 R+S P3 P2P I PO 03 + P302 + P3P2Gl + P3 P 2P l 00 C4 C3 C4
1 S-R +- Same as R + S equations, but substitute Ri for Rj in definitions .....
2 R-S +- Same as R + S equations, but substitute Sf for Sj in definitions .....
3 RVS LOW P3P2PIPO P3P2PI PO+ Cn P3 P2P IPO+ Cn
4 RAS LOW 03+ch+Ol +00 03+02+01 +Oo+Cn 03+02+01 +Oo+Cn
5 R AS LOW +- Same as R A S equations, but substitute Ri for Rj in definitions .....
6 RS +- Same as If1TS, but substitute Ri for Rj in definitions .....
03 + P302 + P3 P 201
7 R S 03+02+01 +00 03 + P302 + P3 P 20 1+ P3 P2P IPO See note
+ P3 P2P I PO(Oo+Cn)
Notes:
[P2 + G2Pt + G2GtPO + G2GtGoCn1 [P3 + G3 P 2 + G3G2Pt + 03G2Gt P O + C1302GtC10Cn]
+ =OR
Figure 8
590
~ CY7C901
~~~DUcrOR=====================================================================
Vee = Min.
IOH = -3.4mA
Vee = Min.
VOL Output LOW Voltage IOL = 20 rnA Commercial 0.4 V
IOL = 16 rnA Military
Vss :s: VIN:S: Vee -10
IIX Input Leakage Current 10 fLA
Vee = Max.

Vee = Min.
IOH Output HIGH Current -3.4 rnA
VOH = 2.4V
Vee = Min. Commercial 20
IOL Output LOW Current rnA
VOL = 0.4V Military 16
Vee = Max. +40 fLA
Ioz Output Leakage Current
VOUT = Vss to Vee -40 fLA
Vee = Max.
Ise Output Short Circuit Current[I] -85 rnA
VOUT = OV
Commercial -31 70
lee Supply Current Vee = Max. Commercial-23 80 rnA
Military -27, -32 90
VIH ~ Vee - 1.2V, 10 MHz Commercial 26.5
lee} Supply Current rnA
VIL:S: 0.4V Military 31
Capacitance [2]
pF
COUT
Notes:
1. Not more than one output should be tested at a time. Duration of the 3. See the last page of this specification for Group A subgroup testing
short circuit should not be more than one second. information.

+5 V +5 V
~
Ti
200n 2701.
VO~
VOUT
lCC ":" ,.. " lCL

0030-4 0030-5
All outputs except open drain Open drain (F = 0)
Notes:
}. eL = 50 pF includes scope probe, wiring and stray capacitance.
2. eL = 5 pF for output disable tests.
3. Loads shown above are for commercial (20 rnA) IOL spec only.
5-91
~ CY7C901 1
~~~ucr~==================================================================
CY7C901-23 Commercial and Cycle Time and Clock Characteristics [5]
CY7C901-27 Military AC Performance CY7C901 -23 -27
Characteristics Read-Modify-Write Cycle (from 23 ns 27ns
The tables below specify the guaranteed AC performance selection of A, B registers to
end of cycle).
of these devices over the Commercial (OC to 70C) and
Military ( - 55C to + 125C) operating temperature range Maximum Clock Frequency to shift Q 43 MHz 37 MHz
with Vee varying from 4.5V to 5.5V. All times are in (50% duty cycle, I = 432 or 632)
nanoseconds and are measured between the 1.5V signal lev- Minimum Clock LOW Time 13 ns 15 ns
els. The inputs switch between OV and 3V with signal tran- Minimum Clock HIGH Time IOns 12 ns
sition rates of 1V per nanosecond. All outputs have maxi- Minimum Clock Period 23 ns 27ns
mum DC current loads. See "Electrical Characteristics"
for loading circuit information.
CY7C901-23PC CY7C901-23DC CY7C901-23LC
CY7C901-23JC CY7C901-27DMB CY7C901-27LMB
To Output y RAMo Qo
F3 Cn+4 "G,P F=O OVR
RAM3 Q3
From Input
CY7C901 23 27 23 27 23 27 23 27 23 27 23 27 23 27 23 27
A, BAddress 30 33 30 33 30 33 28 33 30 33 30 33 30 33 - -
Data 21 24 20 23 20 23 20 21 24 25 21 24 22 25 - -
en 17 18 16 17 14 14 - - 18 19 16 17 18 19 - -
1012 26 28 25 27 24 26 24 28 25 29 24 27 25 27 - -
1345 26 27 24 27 24 26 24 26 26 27 24 26 26 27 - -
1678 16 18 - - - - - - - - - - 21 21 21 21
A BypassALU
(I = 2XX) 24 26 - - - - - - - - - - - - - -
Clock JI""" 24 27 23 26 23 26 23 25 24 27 24 26 24 27 19 20

CP:
..l~
--- ~--
-,11-
Input Set-upTime Hold Time Set-upTime Hold Time

BeforeH ----+- L AfterH ----+- L BeforeL ----+- H AfterL ----+- H
CY7C901 23 27 23 I 27 23 I 27 23 1 27
A, B Source Address 10 12 0 21.10 + tPWL 0
(Note 3) (Note 4)
B Destination Address 10 12 ~ Do Not Change ----+- 0
Data - - - 16 0
en - - - 13 0
1012 - - - 19 0
1345 - - - 19 0
1678 7 9 ~ Do Not Change ----+- 0
RAMo, 3,Qo, 3 - - - 9 0
Output EnablelDisable Times [5]

Device Input Output Enable Disable to allow time to access the source data before the latches close. The A
CY7C901-23 OE y 14 16 address may then be changed. The B address could be changed if it is
CY7C901-27 OE Y 16 18 Normally A and B are not changed during the clock LOW time.
Notes: 4. The set-up time prior to the clock L -+ H transition is to allow time
1. A dash indicates a propagation delay path or set-up time constraint for data to be accessed, passed through the ALU, and returned to the
does not exist. RAM. It includes all the time from stable A and B addresses to the
2. Certain signals must be stable during the entire clock LOW time to clock L -+ H transition, regardless of when the clock H -+ L
avoid erroneous operation. This is indicated by the phrase "do not transition occurs.
change". 5. See the last page ofthis specification for Group A subgroup testing
information.
5-92
I~I~ CY7C901
'1~jr;~~UaoR==============================================================
CY7C901-31 Commercial and Cycle Time and Clock Characteristics[5]
CY7C901-32 Military AC Performance CY7C901 31 -32
Characteristics Read-Modify-Write Cycle (from 31 ns 32 ns
selection of A, B registers to
The tables below specify the guaranteed AC performance
end of cycle).
Military (- 55C to + 125C) operating temperature range Maximum Clock Frequency to shift Q 32 MHz 31 MHz
with V CC varying from 4.5V to 5.5V. All times are in (50% duty cycle, I = 432 or 632)
nanoseconds and are measured between the 1.5V signal lev- Minimum Clock LOW Time 16 ns 17 ns
els. The inputs switch between OV and 3V with signal tran- Minimum Clock HIGH Time 15 ns 15 ns
sition rates of 1V per nanosecond. All outputs have maxi- Minimum Clock Period 31 ns 32ns
mum DC current loads. See "Electrical Characteristics"
for loading circuit information. For faster performance see CY7C901-23 specification on page 9.

CY7C901-31PC CY7C901-31DC CY7C901-31LC CY7C901-31JC CY7C901-32DMB CY7C901-32LMB

To Output Y G,P F=O OVR RAMo Qo

F3 Cn+4 RAM3 Q3
From Input -31 -32 -31 -32 -31 32 31 32 -31 32 31 32 31 32 31 -32
A, BAddress 40 48 40 48 40 48 37 44 40 48 40 48 40 48 - -
D 30 37 30 37 30 37 30 34 38 40 30 37 30 37 - -
Cn 22 25 22 25 20 21 - - 25 28 22 25 25 28 - -
1012 35 40 35 40 35 40 37 44 37 44 35 40 35 40 - -
1345 35 40 35 40 35 40 35 40 38 40 35 40 35 40 - -
1678 25 29 - - - - - - - - - - 26 29 26 29
A Bypass ALU
(I = 2XX)
35 40 - - - - - - - - - - - - - -
Clock....r 35 40 35 40 35 40 35 40 35 40 35 40 35 40 28 33
CP:
-, --- --- -I-
SetupTime Hold Time Set-upTime Hold Time

Input
BeforeH ~ L AfterH ~ L BeforeL ~ H AfterL ~ H
A, B Source Address 15
0 30,15 + tPWL
(Note 3) (Note 4) 0
B Destination Address 15 +- Do Not Change ~ 0
D - - 25 0
Cn - - 20 0
1012 - - 30 0
1345 - - 30 0
1678 10 +- Do Not Change ~ 0
RAMo, 3,QO, 3 - - 12 0

3. Source addresses must be stable prior to the clock H ~ L transition
CY7C901-31 OE Y 23 23 address may then be changed. The B address could be changed ifit is
Notes: 4. The set-up time prior to the clock L ~ H transition is to allow time
2. Certain signals must be stable during the entire clock LOW time to clock L ~ H transition, regardless of when the clock H ~ L
change". 5. See the last page of this specification for Group A subgroup testing
information.
5-93
5r~cn CY7C901~
Minimum Cycle Time Calculations for 16Bit Systems
Speed used in calculations for parts other than CY7C901 are representative for MSI parts.
~--------------~CN
WIRED "OR" f=O
fROM OTHER CY7C901s
~
f=O~"""'..,
Cn +",
CY7C901
(1)
CY7C901
(4)
OVR
f3
t---"""'--..... 4
DATA
REGISTER
0030-11
Pipelined System, Add without Simultaneous Shift
Data Loop Control Loop
CY7C245 Clock to Output 12 CY7C245 Clock to Output 12
CY7C901 A,BtoG,P 28 MUX Select to Output 12
Carry Logic Go,PotoCn+z 9 CY7C910 CCtoOutput 22
CY7C901 C n to Worst Case 18 CY7C245 Access Time 20
Register Setup 4 66ns
71 ns
Minimum Clock Period = 71 ns
0030-12
Pipelined System, Simultaneous Add and Shift Down (RIGHT)
CY7C901 A,BtoG,P 28 MUX Select to Output 12
Carry Logic Go, Po to en + Z 9 CY7C91O CC to Output 22
CY7C901 C n to Worst Case 18 CY7C245 Access Time 20
XORandMUX Prop. Delay, Select 20 66ns
to Output
CY7C901 RAM3SetuP 9
96 ns
Minimum Oock Period = 96 ns
5-94
VI. SUPPLY VOLTAGE AMBIENT TEMPERATURE
VI. OUTPUT VOLTAGE
VI.
1~~---r----~--~--~ 1.4 r-------..,----------, 60
I
]: 50
Vee =5.0V
TA =25OC-
'"
I-
1.0 U ffi
~ ~ ~
~
~
0 0 ~
L&.I L&.I (.)
N
::J 0.8 ~ 1.0 lj 30
'"
<
:2
< ~
:2 ~
~ ~
0 0 0 20
~
(I)
z 0.6 z 0.8
VIN =5.0V ~
10
TA =25OC
Vee =5.5V
VIN =5.0V ~
0
0.4 0.6 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0

VI. SUPPLY VOLTAGE AMBIENT TEMPERATURE
VI. vs. OUTPUT VOLTAGE
1.3 1.6 140
~ 120
~ 1~ ~ !.
z
L&.I
z 1.4
I- L ~
-
L&.I
zL&.I 100
~
~ ~
1.1
0
L&.I
~
0
L&.I
1~
~
~
/V
-~I""'"
~ 80
""
Lo. Lo. ~
0
L&.I
N
1.0
V TA =25C
0
L&.I
N 1.0 '---
(.)
z
~
60 / Vee =5.0V
TA = 25C -
::J
<
:2
0.9 ::J
<
:2 Vee = 5.0V
in
I- 40 /
/
~
~ ~
0 0 0.8 a...
z 0.8 z I-
~ 20
0.7 0.6
0
o V
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE(OC) OUTPUT VOLTAGE (V)

v
1.6 1.1
>- t...--
:5 1.5 1.0
L&.I
/'
V
0
I-
~ 1.4 / 13
I!: / 0
L&.I 0.9
~
0
0
L&.I
1.3
V
/ N
::J
<
:2
~
O.S
V
N
1.2
::J
<
:2
~ / Vee =5.0V
0
z
0.7
IV Vee = 5.5V
TA =250C -
0 1.1 TA =25OC- 1/ VIN =OV OR 3V
z
1.0 / I o I I I
o 200 400 600 BOO 1000 o 5 10 15 20 25 30 35
0030-10
5-95
5,ri. ~~~NDUcrOR================================================================== CY7C901
Read
Pin Configuration .
Top View
Modify Package Operating
Write
Ordering Code
Type Range
~ ~~ <' <l(N <l(t') I~>-t')>-N'; >-0
Cycle (ns) 5 4 3 2 t!.l4443 424140
Is 39 HC
23 CY7C90123PC P17 Commercial
CY7C90123DC 018 Commercial 17 8 P
CY7C90123JC J67 Commercial RAM3 9 OVR
CY7C90123LC L67 Commercial RAMo Cn + 4
27 CY7C901-27DMB 018 Military Vee G

CY7C90127LMB L67 Military F=O F3
10 13 GHD
31 CY7C901-31PC P17 Commercial 11 Cn
CY7C901-31DC 018 Commercial 12 31 14
CY7C901-31JC J67 Commercial
CP 15
He 13
32 CY7C901-32DMB 018 Military 1819202122232425262728
6' cfm aJNaJt')8~~o 8~ 0030-9
596
~ CY7C901
~~~~UcrOR==================================================================
VOH 1,2,3 From C n to C n +4 7,8,9,10,11
VOL 1,2,3 From Cn to F = 7,8,9,10,11
VIH 1,2,3 From Cn to OVR 7,8,9,10,11
VILMax. 1,2,3 From Cn to RAMo, 3 7,8,9,10,11
IIX 1,2,3 From 1012 to Y 7,8,9,10,11
IOZ 1,2,3 From 1012 to F3 7,8,9,10,11
Isc 1,2,3 From 1012 to Cn +4 7,8,9,10,11
ICC 1,2,3 From 1012 to G, P 7,8,9,10,11
ICCI 1,2,3 From 1012 to F=O 7,8,9,10,11
From 1012 to OVR 7,8,9,10,11
Cycle Time and Clock Characteristics 7,8,9,10,11
From 1012 to RAMo, 3
Parameters Subgroups From 1345 to Y 7,8,9,10,11
Minimum Clock LOW Time 7,8,9,10,11 From 1345 to F3 7,8,9,10,11
Minimum Clock HIGH Time 7,8,9,10,11 7,8,9,10,11
From 1345 to Cn + 4
From 1345 to G, P 7,8,9,10,11
From 1345 to F = 7,8,9,10,11
From 1345 to OVR 7,8,9,10,11
From A, B Address to Y 7,8,9,10,11
From 1345 to RAMo, 3 7,8,9,10,11
From A, B Address to F3 7,8,9,10,11
From 1678 to Y 7,8,9,10,11
From A, B Address to Cn + 4 7,8,9,10,11
From 1678 to RAMo, 3 7,8,9,10,11
From A, B Address to G, P 7,8,9,10,11
From A, B Address to F = 7,8,9,10,11
From 1678 to Qo, 3
From A Bypass ALU to Y
7,8,9,10,11
7,8,9,10,11
From A, B Address to OVR 7,8,9,10,11 (I = 2XX)
From A, B Address to RAMo, 3 7,8,9,10,11 From Clock ....f" to Y 7,8,9,10,11
FromDtoY 7,8,9,10,11 From Clock....f" to F3 7,8,9,10,11
FromDtoF3 7,8,9,10,11 From Clock ....f" to C n + 4 7,8,9,10,11
From D to Cn +4 7,8,9,10,11 From Clock....f" to G, P 7,8,9,10,11
FromDtoG, P 7,8,9,10,11 From Clock ....f" to F = 7,8,9,10,11
FromDtoF = 7,8,9,10,11 From Clock ....f" to OVR 7,8,9,10,11
From D toOVR 7,8,9,10,11 From Clock ....f" to RAMo, 3 7,8,9,10,11
From D to RAMo, 3 7,8,9,10,11 From Clock ....f" to Qo, 3 7,8,9,10,11
FromCn toY 7,8,9,10,11
From Cn to F3 7,8,9,10,11
5-97
~ CY7C901
~~~U~R================================================================
Parameters SublP'oups Parameters SublP'oups
A, B Source Address 7,8,9,10,11 D Hold Time After L --. H 7,8,9,10,11
Set-up Time Before H --. L en Set-up Time Before L -+ H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 en Hold Time After L -+ H 7,8,9,10,11
Hold Time After H --. L
1012 Set-up Time Before L --. H 7,8,9,10,11
Set-up Time Before L --. H 1012 Hold Time After L -+ H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 1345 Set-up Time Before L -+ H 7,8,9,10,11
Hold Time After L --. H 1345 Hold Time After L -+ H 7,8,9,10,11
B Destination Address 7,8,9,10,11 1678 Set-up Time Before H -+ L 7,8,9,10,11
Set-up Time Before H -+ L
1678 Hold Time After H --. L 7,8,9,10,11
1678 Set-up Time Before L -+ H 7,8,9,10,11
l678 Hold Time After L -+ H 7,8,9,10,11
Set-up Time Before L -+ H RAMO, RAM3, Qo, Q3 7,8,9,10,11
Set-up Time Before L -+ H
Hold Time After L -+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11
Hold Time After L -+ H
D Set-up Time Before L -+ H 7,8,9,10,11
5-98
I
CY7C909
.1
CY7C911
CYPRESS
SEMICONDUCTOR . CMOS Micro Program
Sequencers
Features
Fast Capable of withstanding greater 1) a set offour external direct inputs
- CY7C909/11 has a 30 ns than 2000V static discharge (Di); 2) external data stored in an inter-
(min.) clock to output cycle voltage nal register (RD; 3) a four word deep
time; commercial and military Pin compatible and functional push/pop stack; or 4) a program coun-
equivalent to 2909A/2911A ter register (which usually contains the
Low Power
- lee (max.) = 55 mA; last address plus one). The push/pop
commercial and military Description stack includes control lines so that it
can efficiently execute nested subrou-
Vee margin The CY7C909 and CY7C911 are high- tine linkages. Each of the four outputs
- 5 V 10% speed, four-bit wide address sequencers (yD can be OR'ed with an external in-
- All parameters guaranteed intended for controlling the sequence put for conditional skip or branch in-
over commercial and military of execution of microinstructions con- structions. A ZERO input line forces
operating temperature range tained in microprogram memory. They the outputs to all zeros. The outputs
may be connected in parallel to expand are three state, controlled by the
Expandable the address width in 4 bit increments.
Infinitely expandable in 4-bit Output Enable (OE) input.
increments Both devices are implemented in high
performance CMOS for optimum The CY7C911 is an identical circuit to
speed and power. the CY7C909, except the four OR in-
puts are removed and the D and R in-
The CY7C909 can select an address puts are tied together. The CY7C911 is
from any of four sources. They are: available in a 20-pin, 300-mil package.

PUSH/POP
FILE
ENABLE
RE Vee CP PUP
R3 CP
FE Vee FE
REGISTER R2 PUP
ENABLE RE Cn+4
Rl FE:
iiE) 03 Cn
Ro Cn+4
OR3 Cn O2 OE
03 Or 01 Y3
OR 2 Y3 DO Y2
O2 Y2 GNO Y1
DIRECT
CLOCK
OR I Yl
INPUTS ZERO Yo
01 Yo
So S1
ORo SI
00 So
0042-3
GNO ZERO
0042-2
U Q.,
U Q.,
r a.:C'la.:"'Il;i! >ues ~
I~ >ues ~I~
4 3 2 1 282726
RO 5 25 FE
OR 3 6 24 e n+ 4 Cn + 4
ZERO
7 23 en C
3 n
OR 2 8 7C909 22 6E OE
9 21 Y3 Y
2 3
OR 1 10 20 Y2 Y
2
11 19 Y1
1
OUTPUT
ENABLE
12131415161718
o OQ 10 0- 0
a=:CZa::CI)(IJ>-
10 0_0-
f5VlVl>->-
o ow
N
N
OE
0042-5
0042-4
Yo Yl Y2 Y3 en en 4
0042-1
5-99
CY7C909
fin .
~NDUCIOR =============================111
CY7C911 I Ii
Maximum Ratings
Power Applied .................... - 55C to + 125C Latch-Up Current ......................... > 200 rnA
Ambient
in High Z State ...................... - 0.5V to + 7.0V Range
Temperature Vee
DC Input Voltage ................... - 3.0V to + 7.0V Commercial OC to + 70"C 5V 1O%
Output Current, into Outputs (Low) ............. 30 rnA Military [3] - 55C to + 125C 5V 10%
Electrical Characteristics Over Operating Range [4)

Output HIGH Voltage Vee = Min., IOH = - 2.6 rnA (Comm.) 2.4 V
VOH
Vee = Min., IOH = - 1.0 rnA (Mil.) 2.4 V
VIH Input High Voltage 2.0 Vee V
IIX Input Load Current GND:::;: VI:::;: Vee -10 +10 IJ-A
Output Leakage GND:::;: Vo:::;: Vee -20 +20
loz Current Output Disabled IJ-A
Output Shordll
los Circuit Current Vee = Max. VOUT = GND -30 -85 rnA
Vee Operating Vee = Max. Commercial 55

rnA
lee Supply Current lOUT = OmA Military 55
Vce Operating Vec = Max. Commercial 35
rnA
leci Supply Current VIH ;;:: 3.0V, VIL :::;: 0.4V Military 35
Capacitance [2]
CoUT
Notes:
1. Not more than I output should be shorted at one time. Duration of 3. TA is the "instant on" case temperature.

R1 R1 ALL INPUT PULSES
:3E"
n n ~
SV SV DV
OUTPUT OUTPUT GND
3. 10% 10%
~Sns - ~ Sns
SOpf R2 S pf R2
INCLUDING
JIG AND -
I _
-
INCLUDING
JIG AND -
I .._ -
Figurel
0042-7
SCOPE SCOPE
0042-6
Figure 18 Figure Ib
Commercial Military
I RI 2540 2580
I R2 1870 2160
5-100
CY7C909
'I
5n ;
~NDUcroR =====================================================================
CY7C911

7C909-30 7C909-30 7C909-40 7C909-40
Units
7C911-30 7C911-30 7C911-40 7C911-40
Commercial Military Commercial Military
Minimum Clock Low Time 15 15 20 20 ns
Minimum Clock High Time 15 15 20 20 ns
MAXIMUM COMBINATIONAL PROPAGATION DELAYS
From Input To: y CN+ 4 Y CN+ 4 Y CN+4 y CN + 4 ns
Dj 17 18 18 19 17 22 20 25 ns
So, SI 18 18 20 20 29 34 29 34 ns
ORj(7C909) 16 16 17 17 17 22 20 25 ns
- -

CN 13 - 15 - 14 16 ns
ZERO 18 18 20 20 29 34 30 35 ns
OE Low to Output 16 - 18 - 25 - 25 - 'ns
OE HIGH to HIGH Z[s] 16 - 18 - 25 - 25 - ns
Clock HIGH, SI, So = LH 20 20 22 22 39 44 45 50 ns
Clock HIGH, SI, So = LL 20 20 22 22 39 44 45 50 ns
Clock HIGH, St. So = HL 20 20 22 22 44 49 53 58 ns
MINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)
From Input Set-up Hold Set-up Hold Set-up Hold Set-up Hold
RE 11 0 12 0 19 0 19 0 ns
Rj [6] 10 0 11 0 10 0 12 0 ns
Push/Pop 12 0 13 0 25 0 27 0 ns
FE 12 0 13 0 25 0 27 0 ns
CN 10 0 11 0 18 0 18 0 ns
Dj 14 0 16 0 25 0 25 0 ns
ORj (7C909) 12 0 14 0 25 0 25 0 ns
So, SI 14 0 16 0 25 0 29 0 ns
ZERO 12 0 13 0 25 0 29 0 ns
Notes:
5. Output Loading as in Figure 1h. 7. System clock cycle time (Clock Low Time and Clock High Time)
6. Rj and Dj are internally connected on the CY7C911. Use Rj set-up cannot be less than maximum propagation delay.
and hold times when Dj inputs are used to load register.
Switching Waveforms
-MIN CLOCK LOW
CLOCK
INPUT
(EXCEPT OE)
INPUT TO OUTPU~
OUTPUT----~
:=5<.XXXXXXXXXXXXXXXXX
14-----CLOCK TO
(Y,~~T:~) ::::::::::::::::::::: 0042-8
5-101
CY7C9091II'1
fiA~~NDUcroR =====================================================================
.
CY7C911
The tables below define the control logic ofthe 7C909/911. Table 3 illustrates. the Output Control Logic of the
Table 1 contains the Multiplexer Control Logic which se- 7C909/911. The ZERO control forces the outputs to zero.
lects the address source to appear on the outputs. The OR inputs are OR'ed with the output of the multiplex-
er.
Table I. Address Source Selection Table 3. Output Control
OcrAL S1 So SOURCE FOR Y OUTPUTS ORi ZERO OE Yi
0 L L Microprogram Counter (,...PC) X X H HighZ
1 L H Address/Holding Register (AR) X L L L
2 H L Push-Pop stack (STK) H H L H
3 H H Direct inputs (DJ L H L Source selected by So SI
Control of the Push/Pop Stack is contained in Table 2. Table 4 defines the effect of So, St. FE and PUP control
FILE ENABLE (FE) enables stack operations. while signals on the 7C909. It illustrates the Address Source on
Push/Pop (PUP) controls the stack. the outputs and the contents of the Internal Registers for
every combination of these signals. The Internal Register
Table 2. Synchronous Stack Control
contents are illustrated before and after the Clock LOW to
FE PUP PUSHPOP STACK CHANGE HIGH edge.
H X No change
L H Push current PC into stack
increment stack pointer
L L pop stack, decrement stack pointer
Table 4
PRINCIPLE
CYCLE S}, So, FE, PUP ,...PC REG STKO STKI STKl STK3 YOUT COMMENT
USE
N 0000 J K Ra Rb Rc Rd J End
Pop Stack
N + 1 - J + 1 K Rb Rc Rd Ra - Loop
N 0001 J K Ra Rb Rc Rd J Set-up
Push ,...PC
N+1 - J + 1 K J Ra Rb Rc - Loop
N 001 X J K Ra Rb Rc Rd J
Continue Continue
N + 1 - J + 1 K Ra Rb Rc Rd -
N 0100 J K Ra Rb Rc Rd K Use AR for Address; End
N+1 - K + 1 K Rb Rc Rd Ra - Pop Stack Loop
N 0101 J K Ra Rb Rc Rd K Jump to Address in AR;
JSRAR
N+1 - K + 1 K J Ra Rb Rc - Push ,...PC
N 011 X J K Ra Rb Rc Rd K
Jump to Address in AR JMPAR
N + 1 - K + 1 K Ra Rb Rc Rd -
N 1000 J K Ra Rb Rc Rd Ra Jump to Address in STKO;
RTS
N + 1 - Ra + 1 K Rb Rc Rd Ra - Pop Stack
N 1001 J K Ra Rb Rc Rd Ra Jump to Address in STKO;
N + 1 - Ra + 1 K J Ra Rb Rc - Push,...PC
N 101 X J K Ra Rb Rc Rd Ra Stack Ref
Jump to Address in STKO
N+1 - Ra + 1 K Ra Rb Rc Rd - (Loop)
N 1100 J K Ra Rb Rc Rd D Jump to Address on D; End
N + 1 - D + 1 K Rb Rc Rd Ra - Pop Stack Loop
N 1101 J K Ra Rb Rc Rd D Jump to Address on D;
JSRD
N + 1 - D + 1 K J Ra Rb Rc - Push p.PC
N 111 X J K Ra Rb Rc Rd D
Jump to Address on D JMPD
N+1 - D + 1 K Ra Rb Rc Rd -
J = Contents of Microprogram Counter
K = Contents of Address Register
Ra. Rb, Re, Rtt = Contents in Stack
5-102
Two examples of Subroutine Execution appear below. Fig- "Jump to sub-routine at A". At the time T2, this instruc-
ure 3 illustrates a single subroutine while Figure 4 illus- tion is in the p.WR, and the 7C909 inputs are set-up to
trates two nested subroutines. execute the jump and save the return address. The subrou-
The instruction being executed at any given time is the one tine address A is applied to the D inputs from the p. WR
contained in the microword register (p. WR). The contents and appears on the Y outputs. The first instruction of the
of the p. WR also controls the four signals So, SI, FE, and subroutine, I(A), is accessed and is at the inputs of the
PUP. The starting address of the subroutine is applied to p. WR. On the next clock transition, I(A) is loaded into the
the D inputs of the 7C909 at the appropriate time. p. WR for execution, and the return address J + 3 is
pushed onto the stack. The return instruction is executed at
In the columns on the left is the sequence of microinstruc- Ts. Figure 4 is a similar timing chart showing one subrou-
tions to be executed. At address J + 2, the sequence con- tine linking to a second, the latter consisting of only one
trol portion of the microinstruction contains the command microinstruction.
CONTROL MEMORY
Microprogram Execute Cycle To Tl T2 T3 T& Ts T6 T, T. ~9
Execute
Cycle Address
Sequencer
Instruction
Clock
SianaIs - ILILILIL ~ ILILILILIL
JI Inputs Slo So 0 0 3 0 0 2 0 0
To 1
(from FE H H L H H L H H
Tl HI PUP X X H X X L X X
H2 JSRA "WR) D X X A X X X X X
T2
T6 H3
T7 1+4 "PC HI J+2 H3 A+I A+2 A+3 J+4 1+5
STKO H3 H3 1+3
Internal
STKI
Registers
STK2
STK3
T3 A I(A) Output Y HI H2 A A+l A+2 H3 H4 H5

T4 A+I
T, A+2 RTS ROM I(H I) ISRA I(A)
(Y) I(A+ I) RTS 1(1+3) I(H4) 1(1+5)
Output
Contents
of"WR
(Instruction "WR 1(1) I(J+l) ISRA I(A) I(A+I) RTS 1(1+3) 1(1+4)
being
executed)
0042-9
Figure 3. Subroutine Execution. en = HIGH
CONTROL MEMORY
Microproaram Execute Cycle To Tl Tz T3 T" TS T6 T, Ta T,
L -lJIL
Execute
Cycle Address
Sequencer
Instruction
Cock
SianaJ. -.j ilJIL-UilJilJIL L 0 0
11 Inputs Slo So 0 0 3 0 0 3 2 2
To 1 (from
FE H H L H H L L H L H
Tl HI PUP X X H X X H L X L X
H2 JSRA "WR) D X X A X X B X X X X
T2
T9 H3
"PC HI H2 1+3 A+I A+2 A+3 B+l A+4 A+5 H4
STKO H3 H3 1+3 A+3 H3 H3
Internal H3
STKI
Registers
STK2
T3 A STK3
T4 A+I
T, A+2 JSRB Output y HI H2 A A+I A+2 B A+3 A+4 J+3 H4
T, A+3
TS A+4 RTS ROM (Y) I(HI) ISRA I(A) I(A+I) JSRB RTS I(A+3) RTS I(H3) I(H4)
Output
Contents
of"WR
T6 B RTS (Instruction "WR I(J) I(J+ I) ISRA I(A) I(A+I) JSRB RTS I(A+3) RTS I(J+ 3)
being
executed)
0042-10
Figure 4. Two Nested Subroutines. Routine B is Only One Instruction. en = HIGH
5-103
CY7C909
(in CYPRESS
SEMICONDUCTOR ====================================
CY7C911
J'
III! II!!
Note:
II
0042-11
Rj and Dj connected together and ORj Inputs removed on CY7C911
Figure 5. Microprogram Sequencer Block Diagram
5-104
CY7C909
1.1
5A~NDUcrOR =====================================================================
.

CY7C911
Architecture loaded with the same Y output (Y - > ~PC) on the next
clock cycle.
The CY7C909 and CY7C911 are CMOS microprogram se-
I quencers for use in high speed processor applications. They Stack
are cascadable in 4-bit increments. Two devices can ad- The Stack consists of a 4 x 4 memory array and a built-in
dress 256 words of microprogram, three can address up to Stack Pointer (SP) which always points to the last word
4K words, and so on. The architecture of the written. The Stack is used to store return addresses when
CY7C909/911 is illustrated in the logic diagram in Figure executing microsubroutines.
5. The various blocks are described below.
The Stack Pointer is an up/down counter controlled by
Multiplexer File Enable (FE) and Push/Pop (PUP) inputs. The File
The Multiplexer is controlled by the So and SI inputs to Enable input allows stack operations only when it is LOW.
select the address source. It selects either the Direct Inputs The Push/Pop input controls the stack pointer position.
(OJ, the Address Register (AR), the Microprogram Coun- The PUSH operation is initiated at the beginning of a mi-
ter (,...PC), or the stack (SP) as the source of the next mi- crosubroutine. Push/Pop is set HIGH while Ftle Enable is
croinstruction address. kept LOW. The stack pointer is incremented and the mem-
Direct Inputs ory array is written with the microinstruction address fol-
lowing the subroutine jump that initiated the push.
The Direct Inputs (Di) allow addresses from an external
source to be output on the Y outputs. On the CY7C911, The POP operation is initiated at the end of a microsub-
the direct inputs are also the inputs to the Address Regis- routine to obtain the return address. Both Push/Pop and
Ftle Enable are set LOW. The return address is already
ter.
available to the multiplexer. The stack pointer is decre-
Address Register mented on the next LOW to HIGH clock transition, effec-
tively removing old information from the top of the stack.
The Address Register (AR) consists offour D-type, edge-
The stack is configured so that data will roll-over if more
triggered flip-flops which are controlled by the Regtster
than four POPs are performed, thus preventing data from
Enable (RE) input. When Register Enable is LOW, new
being lost.
data is entered into the register on the LOW to HIGH
clock transition. The contents of the memory position pointed to by the
Stack Pointer is always available to the multiplexer. Stack
Microprogram Counter reference operations can thus be performed without a push
The Microprogram Counter (,...PC) is composed of a 4-bit or a pop. Since the stack is four words deep, up to four
incrementer followed by a 4-bit register. The incrementer microsubroutines can be nested.
has a Carry-in (CN) input and a Carry-out (CN + 4) output The ZERO input resets the four Y outputs to a binary zero
to facilitate cascading. The Carry-in input controls the mi- state. The OR inputs (7C909 only) are connected to the Y
croprogram counter. When Carry-in is HIGH the incre- outputs such that any output can be set to a logical one.
menter counts sequentially. The counter register is loaded
with the current Y output plus one (Y + 1 - > ,...PC) on The Output Enable (OR) input controls the Y outputs. A
the next clock cycle. When Carry-in is LOW the incremen- HIGH on Output Enable sets the outputs into a high im-
ter does not count. The microprogram counter register is pedance state.
Definition of Terms
Name Description
INPUTS
SI, So Multiplexer Control Lines, for Access Source Selection
FE File Enable, Enables Stack Operation, Active LOW
PUP Push/Pop, Selects Stack Operation
RE Register Enable, Enables Address Register Active LOW
ZERO Forces Output to Logical Zero
OE Output Ena6le, Controls Three-State Outputs Active LOW
ORj Logic OR Input to each Address Output Line (7C909 only)
Cn Carry-In, Controls Microprogram Counter
Ri Inputs to the Internal Address Register
Di Direct Inputs to the Multiplexer
CP Clock Input
5-105
CY7C9091_
fiji
. .
. ~U~======================================================~====~====
CY7C9111~1'
Definition of Terms (Continued)

Name Description
OUTPUTS
Yi Address Outputs
CN + 4 Carry-Out from Incrementer
,
INTERNAL SIGNALS
/-tPC Contents of the Microprogram Counter
AR Contents of the Address Register
STKO-
Contents of the Push/Pop Stack
STK3
SP Contents of the Stack Pointer
EXTERNAL SIGNALS
A Address to the Counter Memory
I(A) Instruction in Control Memory at Address A
Contents of the Microword Register at the
/-tWR
Output of the Control Memory
TN Time Period (Cycle) n
5-106
CY7C909
5A ~~DUcroR ====================================~~~~~~~~~~~~~~~~~=
CY7C911

1.2 1.4.--------r------__, 60
;{
! 50
I- Yee = I.GY
u 1.0 1.2 ~-----+-------I ~ TA=25"C
.!: ~ III
a: 40
~
S
N
C
III
a:
:l
:::; N u
0.8 :::; 1.0101::::----+-------1 III 30
ct
"- ~
ct U
~ a:
a: ~ :l
0 a: 0 20
z 0
Z
11.1
0.6 0.81-----+--:-.--=----1 I-
:l
~
VIN = 5.0Y I- 10
~
:l
TA = 25'C 0
0.6 L -_ _ _ _..J-_ _ _ _ _---II
0.4 o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE rCI OUTPUT VOLTAGE (VI

1.3 1.6 140
> ;{ 120
> 1.2
.L'" ~
u u !
~ ~
-
I-
100
:l
1.1
:l
~ r
0
III S a:
a: /
~ ~ ~ 80
~ :l
C
III
N
:::;
1.0
,/' N
C
III
:::;
U
:.:
z 60
V vee 5.0 V
ct 0.9
~
TA =2lrC_ ct
~ Vee = 5.0Y
in
I-
:l 40
/ TA =25'C
a:
0
z 0.8 J a:
0
z 0.8
~
I-
:l
0 20
/
0.7 0.6 '------.&---------' o
V
4.0 4.5 5.0 5.5 6.0 -55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (VI AMBIENT TEMPERATURE (OCI OUTPUT VOLTAGE (VI

1.6 .----,_-~--r---,_-__,
1.1
1.5 ~-+--+--~-::II""':;;"'-i 1.0 ~

i 1.4 1---+---+--::1"-'1--+"--1 .!:
S
u
0.9
~/
c
III
~
1.3 I-_-+-...,~_~I-_-+-_-I
N
:::;
ct
~
a: 0.8
V' Vee = 5.IY - r--
~ 1.2 1---1---+- 0
z ~ YIN = O,3Y
z
0.7
/ TA = 2lrC
1.1 ~"""'+--+--~-+--i
200 400 600 800 1000 o0 5 10 15 20 25 30 31
CAPACITANCE (pFI FREQUENCY (MHz)
0042-12
5-107
CY7C909
5Il~~NDUcroR =====================================================================
.. CY7C911
Clock Oock
Package Operating Package Operating
Cycle Ordering Code Cycle Ordering Code
(ns)
40 CY7C909-4OPC P15 Commercial 40 CY7C911-4OPC P5 Commercial
30 CY7C909-301C 164 Commercial 30 CY7C911-301C 161 Commercial
40 CY7C909-4OLC L64 Commercial 40 CY7C911-4OLC L61 Commercial
30 CY7C909-30DMB 016 Military 30 CY7C911-300MB 06 Military
40 CY7C909-400MB 016 Military 40 CY7C911-400MB 06 Military
40 CY7C909-4OLMB L64 Military 40 CY7C911-4OLMB L61 Military
5-108
CY7C909
I
fiA~~NDUcrOR==================================================================
,
CY7C911

DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIH 1,2,3
VILMax. 1,2,3
IIX 1,2,3
IOZ 1,2,3
los 1,2,3
III
ICC 1,2,3
Icc 1 1,2,3
Minimum Clock Low Time 7,8,9,10,11 MINIMUM SET-UP AND
Minimum Clock High Time 7,8,9,10,11 HOLD TIMES
MAXIMUM COMBINATIONAL RE Set-up Time 7,8,9,10,11

PROPAGATION DELAYS REHoldTime 7,8,9,10,11
OjtoY 7,8,9,10,11 Push/Pop Set-up Time 7,8,9,10,11
OJ to CN+4 7,8,9,10,11 Push/Pop Hold Time 7,8,9,10,11
So, SI to Y 7,8,9,10,11 FE Set-up Time 7,8,9,10,11
So, SI to CN+4 7,8,9,10,11 FE Hold Time 7,8,9,10,11
ORj (7C909) to Y 7,8,9,10,11 CN Set-up Time 7,8,9,10,11
ORj (7C909) to CN+4 7,8,9,10,11 CNHoldTime 7,8,9,10,11
CNtoCN+4 7,8,9,10,11 OJ Set-up Time 7,8,9,10,11
ZEROtoCN+4 7,8,9,10,11 OJ Hold Time 7,8,9,10,11
Clock High, So, SI = LH 7,8,9,10,11 ORj (7C909) Set-up Time 7,8,9,10,11
toY ORj (7C909) Hold Time 7,8,9,10,11
Clock High, So, SI = LH 7,8,9,10,11 7,8,9,10,11
So, SI Set-up Time
to CN+4
So, SI Hold Time 7,8,9,10,11
Clock High, So, SI = LL 7,8,9,10,11
toY ZERO Set-up Time 7,8,9,10,11
Clock High, So, SI = LL 7,8,9,10,11 ZERO Hold Time 7,8,9,10,11
to CN+4
toY
to CN+4
5-109
CY7C910
CYPRESS
SEMICONDUCTOR CMOS Microprogram
Features
Controller
Fast for subroutine return address or plexer and the required data manipula-
- CY7C910-40 has a 40 ns data storage tion and control logic.
(min.) clock cycle; The operation performed is determined
ESD protection
commercial Capable of withstanding over by four input instruction lines (10-13)
- CY7C910-46 has a 46 ns 2000V static discharge voltage that in tum select the (internal) source
(min.) clock cycle; military of the next micro-instruction to be
Pin compatible and functional
Low power equivalent to AM2910A fetched. This address is output on the
- ICC (max.) = 70 mA YO-Yll pins. Two additional inputs
Functional Description (CC and CCEN) are provided that are
VCC margin SV 10%
commercial and military examined during certain instructions
The CY7C91O is a stand-alone micro- and enable the user to make the execu-
Sixteen powerful program controller that selects, stores, tion of the instruction either uncondi-
microinstructions retrieves, manipulates and tests ad- tional or dependent upon an external
dresses that control the sequence of ex- test.
Three output enable controls
for three-way branch ecution of instructions stored in an ex-
ternal memory. All addresses are 12-bit The CY7C91O is a pin compatible,
Twelve-bit address word binary values that designate an abso- functional equivalent, improved per-
lute memory location. formance replacement for the
Four sources for addresses: AM291OA.
microprogram counter (MPC), The CY7C91O, as illustrated in the
stack, branch address bus, block diagram, consists ofa 17-word The CY7C910 is fabricated using an
internal holding register by 12-bit LIFO (Last-In-First-Out) advanced 1.2 micron CMOS process
stack and SP (Stack Pointer), a 12-bit that eliminates latchup, results in ESO
12-bit internal loop counter protection of over 2000 volts and
RC (Register/Counter), a 12-bit MPC
Internal 17-word by 12-bit stack (Microprogram Counter) and incre- achieves superior performance and low
The internal stack can be used menter, a 12-bit wide by 4-input multi- power dissipation.

Y4 03
RlD
It
OL&JU')If) ..... . . . , . . . " t I ) N N -
z>c>-c>-c>-c>-c
04
Ys
Y3
O2
05 Y2
6 5 4 3 2l!J4443424140 VEcr 0,
Pi: 7 39 Y1
Pi: Y,
MAP 8 38 DO MAP DO
13 9 37 Yo 13 Yo
12 10 36 NC
12 CI
Vee 11 35 CI CP
VCC
11 12 CP
I, GNO
10 13 33 GNO 10 Of
CCEN 14 NC CCEN
cc 15 OE cc
Y"
0"
RLO 16 Y11 RLD Y,o
NC 17 29 011 FULL 0'0
1819202122232425262728 06 Y9
Y 09
6
07 Ys
Y7 Os
::::::> DATA PATH
0041-6
-CONTROlLiNES
0041-2
0041-1
Top View
Selection Guide
Clock Cycle Stack Operating Range Part Number
(Min.) inns Depth
40 17 words Commercial CY7C91O-40
46 17 words Military CY7C910-46
51 17 words Military CY7C91O-51
99 17 words Military CY7C91O-99
5-110
~"r~~ =======================C=Y=7C=91=O
Pin Definitions
Signal Signal
I/O Description I/O Description
Name Name
DO-Dll I Direct inputs to the RC (Register/ CI I Carry input to the LSB of the
Counter) and multiplexer. DO is LSB incrementer for the MPC.
and Dll is MSB. OE I Control for YO-Yll outputs. LOW to
RLD I Register load. Control input to RC that, enable; High to disable.
when LOW, loads data on the DO-Dll YO-Yll 0 Address output to microprogram
pins into RC on the LOW to HIGH memory. YO is LSB and Yll is MSB.
clock (CP) transition.
FULL 0 When LOW indicates the stack is full.
IO-I3 I Instruction inputs that select one of
sixteen instructions to be performed by PL 0 When LOW selects the pipeline register
the CY7C91O. as the direct input (DO-Dll) source.
CC I Control input that, when LOW, MAP 0 When LOW selects the Mapping
CCEN I
signifies that a test has passed.
Enable for CC input. When HIGH CC
is ignored and a pass is forced. When VECT 0
PROM (or PLA) as the direct input
source.
When LOW selects the Interrupt
Vector as the direct input source.
III
LOW the state of CC is examined.
CP I Clock input. All internal states are
changed on the LOW to HIGH clock
transitions.
5-111
~PFLSS
.nEMICONDUcrOR
CY7C910~
Architecture of the CY7C910
Introduction This permits reference to the data on the top of the stack
without having to perform a POP operation.
The CY7C910 is a high performance CMOS microprogram
controller that produces a sequence of 12-bit addresses that The SP operates as an up/down counter that is increment-
control the execution of a microprogram. The addresses ed when a PUSH operation (instructions 1, 4 or 5) iR per-
are selected from one of four sources, depending upon the formed or decremented when a POP operation (instruc-
(internal) instruction being executed (10-13), and other ex- tions 8, 10, 11, 13 or 15) is performed. The PUSH opera-
ternal inputs. The sources are (1) the (external) DO-D11 tion writes the return address on the stack and the POP
inputs, (2) the RC, (3) the stack and (4) the MPC. Twelve operation effectively removes it. The actual operation oc-
bit lines from each of these four sources are the inputs to a curs on the LOW to HIGH clock transition following the
multiplexer, as shown in Figure 1, whose outputs are ap- instruction.
plied to the inputs of the YO-Y 11 three-state output driv- The stack is initialized by executing instruction zero
ers. (JUMP TO LOCATION 0 or RESET). Every time a
"jump to subroutine" instruction (1,5) or a loop instruc-
External Inputs: DO-D11
tion (4) is executed, the return address is PUSHed onto the
The external inputs are used as the source for destination stack; and every time a "return from subroutine (or loop)"
addresses for the jump or branch type of instructions. instruction is executed, the return address is POPed off the
These are shown as Ds in the two columns in the Table of stack.
Instructions. A second use of these inputs is to load the
When one subroutine calls another or a loop occurs within
RC.
a loop (or a combination), which is called nesting, the Log-
Register Counter: RC ical depth of the stack increases. The physical stack depth
is 17 words. When this depth occurs, the FULL signal goes
The RC is implemented as 12 D-type, edge-triggered flip- LOW on the next LOW to HIGH clock transition. Any
flops that are synchronously clocked on the LOW to further PUSH operations on a full stack will cause the data
HIGH transition of the clock, CPo The data on the D in- at that location to be over-written, but will not increment
puts is synchronously loaded into the RC when the load the SP. Similarily, performing a POP operation on a empty
control input, RLD, is LOW. The output of the RC is stack will not decrement the SP and may result in non-
available to the mUltiplexer as its R input and is output on meaningful data being available at the Y outputs.
the Y outputs during certain instructions, as shown by R in
the Table of Instructions. The Microprocessor Counter: MPC
The RC is operated as a 12-bit down counter and its con- The MPC consists of a 12-bit incrementer followed by a
tents decremented and tested if zero during instructions 8, 12-bit register. The register usually holds the address of the
9 and 15. This enables micro-instructions to be repeated up instruction being fetched. When sequential instructions are
to 4096 times. The RC is arranged such that if it is loaded fetched, the carry input (CI) to the incrementer is HIGH
with a number, N, the sequence will be executed exactly and one is added to the Y outputs of the multiplexer, which
N+ 1 times. is loaded into the MPC on the next LOW to HIGH clock
transition. When the CI input is LOW, the Y outputs of
The Stack and Stack Pointer: SP the multiplexer are loaded directly into the MPC, so that
The 17-word by 12-bit stack is used to provide return ad- the same instruction is fetched and executed.
dresses from micro-subroutines or from loops. Intergal to it
is a SP, which points to (addresses) the last word written.
5-112
II~~PRESS CY7C910
~, ~ICONDUcrOR =====================================
Maximum Ratings
~Above which the useful life may be impaired. For user guidelines, not tested.)
Ambient Te~perature with (Per MIL-STD-883 Method 3015)
Power Apphed .................... - 55 C to + 125 C
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V Ambient
Range Vee
DC Voltage Applied to Outputs Temperature
:m High Z State ...................... -0.5V to + 7.0V Commercial OCto +70C SV 1O%
I DC Input Voltage ................... - 3.0V to + 7.0V Military [3] - SSC to + 12SC SV 1O%
butput Current into Outputs (Low) ............. 30 rnA
Electrical Characteristics Over Commercial and Military Operating Range, VCC Min. = 4.5V, VCC Max. = 5.5V[4]
Parameter Description Test Condition Min. Max. Units
Vee = Min. 2.4 V
VOR Output HIGH Voltage
lOR = -1.6mA
Vee = Min. V
VOL Output LOW Voltage 0.4
IOL = 12mA
Vee = Max.
IIR Input HIGH Current 10 J.LA
VIN = Vee
Vee = Max. -10
IlL Input LOW Current J.LA
VIN = Vss
Vee = Min. -1.6 rnA
lOR Output HIGH Current
VIR = 2.4V
Vee = Min. rnA
IOL Output LOW Current 12
VOL = O.4V
Vee = Max. +40 J.LA
Ioz Output Leakage Current
VOUT = VsslVec -40 J.LA
Vce = Max. -85 rnA
ISC Output Short Circuit Current
VOUT = OV
Commercial 70
Icc Supply Current Vee = Max. rnA
Military 90
Commercial 35
leci Supply Current VIR :;.:: 3.8SV, VIL ::;; O.4V rnA
Military SO
Capacitance [2]
Output Capacitance Vee = S.OV 10 pF
COUT
Notes:
short circuit should not exceed one second. 4. See the last page of this specification for Group A subgroup testing
Output Load used for AC Performance Switching Waveforms
Characteristics
All Outputs 3.0V
INPu6~
---------_1,_-----_1,_--
_ _ _ _ _ _ _ _ _-'I'-_ _ _ _ _-'I""_5_V__
+5 v HOLO TIME
~g' ie, f:
3.0V
CLOCK
OV
OUTPUTS
_______________'1'-______
Nmg, 0041-'
0041-5
1. CL = 50 pF includes scope probe, writing and stray capacitance.

2. CL = 5 pF for output disable tests.
5-113
~ CY7C9101
~~~NDUcrOR=====================================================================
Guaranteed AC Performance Characteristics
The tables below specify the guaranteed AC performance The inputs switch between OV and 3V with signal tran-
of the CY7C91O over the commercial (OC to + 70C) and sition rates of 1 Volt per nanosecond. All outputs have
the military (- 55C to + 125C) temperature ranges with maximum DC current loads.
Vcc varying from 4.5V to 5.5V. All times are in nanosec-
onds and are measured between the 1.5V signal levels.
Clock Requirements [1, 3]

Commercial Military I
CY7C910- 40 50 93 46 51 99 I
Minimum Clock LOW 20 20 50 23 25 58 i
Minimum Clock HIGH 20 20 35 23 25 42

Minimum Clock Period I = 14 40 50 93 46 51 100
Minimum Clock Period 40 50 113 46 51 114
I = 8,9, 15
Combinatorial Propagation Delays. CL = 50 pF[3]

Commercial Military
From Input Y PL, VECf, MAP FULL y PL, VECT, MAP FULL
CY7C91O- 40 50 93 40 50 93 40 50 93 46 51 99 46 51 99 46 51 99
00-011 17 20 20 - - - - - - 21 25 25 - - - - - -
IO-I3 25 35 50 20 30 51 - - - 30 40 54 25 35 58 - - -
CC 22 30 30 - - - - - - 27 36 35 - - - - - -
CCEN 22 30 30 - - - - - - 27 36 37 - - - - - -
CP
1= 8,9,15 30 40 75 - - - 25 31 60 35 46 77 - - - 30 35 67
(Note 2)
CP 30 40 55 - - - 25 31 60 35 46 61 - - - 30 35 67
All Other I
OE 21 25 35 - - - - - - 22 25 40 - - - - - -
(Note 2) 21 27 30 - - - - - - 22 30 30 - - - - - -
Minimum Set-Up and Hold Times Relative to clock LOW to HIGH Transition. CL = 50 pF[3]
Commercial Military
Input Set-Up Hold Set-Up Hold
,
CY7C91O- 40 50 93 40 50 93 46 51 99 46 51 99
01 -+ RC 13 16 24 0 0 0 13 16 28 0 0 0
01 -+ MPC 20 30 58 0 0 0 20 30 62 0 0 0
IO-I3 25 35 75 0 0 0 27 38 81 0 0 0
CC 20 24 63 0 0 0 25 35 65 0 0 0
CCEN 20 24 63 0 0 0 25 35 63 0 0 0
CI 15 18 46 0 0 0 15 18 58 0 0 0
RLO 15 19 36 0 0 0 15 20 42 0 0 0
Notes:
2. The enable/disable times are measured to a 0.5 Volt change on the
1. A dash indicates that a propagation delay path or set-up time does not output voltage level with CL = 5 pF.
exist.
information.
5-114
.Q,~ ===================================================C=Y=7=C==9=10=
Table of Instructions
Reg! Result
Cntr Fail Pass
Ia-1o Mnemonic Name Reg!
Con- CCEN = LandCC = H CCEN = HorCC = L Enable
tents y y Cntr
Stack Stack
0 JZ Jump Zero X 0 Clear 0 Clear Hold PL
1 CJS CondJSB PL X PC Hold D Push Hold PL
2 JMAP Jump Map X D Hold D Hold Hold Map
!
3 CJP CondJumpPL X PC Hold D Hold Hold PL

4 PUSH Push/Cond LD CNTR X PC Push PC Push (Note 1) PL
I
5 JSRP Cond JSB R/PL X R Push D Push Hold PL

6 CJV Cond Jump Vector X PC Hold D Hold Hold Vect

7 JRP Cond Jump R/PL X R Hold D Hold Hold PL
Repeat Loop, *0 F Hold F Hold Dec PL
8 RFCT
CNTR*O =0 PC POP PC Pop Hold PL
RepeatPL, *0 D Hold D Hold Dec PL
9 RPCT
CNTR*O =0 PC Hold PC Hold Hold PL
10 CRTN CondRTN X PC Hold F Pop Hold PL
11 CJPP Cond Jump PL & Pop X PC Hold D Pop Hold PL
12 LDCT LD Cntr & Continue X PC Hold PC Hold Load PL
13 LOOP Test End Loop X F Hold PC Pop Hold PL
14 CONT Continue X PC Hold PC Hold Hold PL
*0 F Hold PC Pop Dec PL
15 TWB Three-Way Branch
=0 D Pop PC Pop Hold PL
Notes:
1. If CCEN = Land CC = H, hold; else load. H = HIGH L=LOW X = Don't Care
5-115
5r~ CY7C910 ~
CY7C910 CMOS Microprogram Controller
CY7C910 Flow Diagrams
oJump Zero (JZ) 1 con~~St4B

PL (CJS)
2 Jump Map (JMAP)
66 68 STACK
67 40 66
65L,
68 41 67
69 42 68 85
70 43 86
3 Cond Jump PL (CJP) 4 Push/Cond LD CNTR (PUSH) 5 Cond JSB R/PL (JSRP)
6 5 k : 6 STACK
66 66
65h
67 67
65
68 25 68 COUNTER
REGISTER/
69 26
6 Cond Jump Vector (CJV) 7 Cond Jump R/PL (JRP) 30 40

31 41
65
32 42
66
66 33 43
65h 34 44
67
68 35
69 36 20 30
21 31
8 Repeat Loop, CNTR,;iO (RFCT) 9 Repeat PL, CNTR,;iO (RPCT) 10 Cond Return (CRTN)
STACK
66 (PUSH)
65 65
.5~
66 N RESISTER/ 66
COUNTER 30
67 66 67 31
68 67 68
69 32
68 69
70 33
70 34
11 Cond Jump PL & POP (CJPP) 12 LD CNTR & Continue (LDCT) 35
65 66 [~~~~) 36
66 37
67 40 .5~COUNTER
66
68 (tl--+---...... 30 41
69 31 42
67 13 Test End Loop (LOOP)
68
70 32
71 65 STACK
66 .1...-_ _..-,67 (PUSH)
14 Continue (CONT) 15 Three-Way Branch (TWB) 67

68
~
STACK
t
65 67 (PUSH) 69
66 70
66
65 N REGISTER/ 71
67 67 COUNTER
68 72 72
68
69 73
0041-9
5-116
~ CY7C910
~~~~UcrOR==================================================================
One Level Pipeline Based Architecture (Recommended)
MAP
.........--CLOCK
CY7C245
REGISTERED PROM
,.
0041-6
1-------- 72 ns CYCLE TIME --------1
CLOCK
(CLOCK TO REGISTER OUTPUT)

PIPELINE CY7C910 -----~"r7'Il~,n------------------+_
REGISTER INPUT - - - - -.....~~~JI------------------_Io-
OUTPUT -INSTRUCTION
18 ns (MUX SELECT TO OUTPUT)
(CC TO Y)
CY7C910------~~~~~~~~~~~~~~--------1--
OUTPUT _ _ _ _ _ _~~~~~~~~~~~~~~--------4__
(PROM ADDRESS SETUP TIME) ~--- 20 ns --~
0041-7
5-117
5r~ CY7C910 I

1.2 ,.-----,----.---,.----, 1.4 r - - - - - - ; - - - - - - - - , 60
~ I
.5.
t-
50
Vee = 5.0V
TA =25OC -
~
(.) 1.0 I__---+---+--_~--I 1.2 1-------+--------1 Z
~
101
...Y ~
~
40
a '~
o :)
101 0
N N
:::::i 0.8 I__---+-~<-t---I__--I :::::i 1.0 I c : - - - - - - I - - - - - - - - - - l 101 30
'~
oC oC 0
~
:2 :2 :)
~ ~
o o 0 20
''"
(/)
z 0.6 1----.fIC'-+---+---f---~
z 0.8 I__----+-~~---I t-
:)
V1N =5.0V Q. 10
t- .....
TA = 25C :)
0.4 0.6 L..-_ _ _.....J,........;,;.;_ _ _ _---I 0

L . . - _ - - ' -_ _....L..._ _.L...-_---I
o
4.0 4.5 5.0 5.5 6.0 -55 125 o 1.0 2.0 3.0 4.0

1.3 1.6.....----.....,...-------, 140
>- ~ 120
0
z
1.2 1.4 I - - - - - - - I - - - - - - - - - - l .5.
t- ./
,.,--
-
101
:) z 100
1.1
0
101 1.2 1__...3000,0;::---+------1
101
~
~
/V
~
Lo. ..,.~I'"'" :) 80
0
101
N
1.0
V TA =25OC 1.0 1-------+-----'="..,""""
0
~
z 60 / Vee = 5.0V
TA =250C-
:::::i
oC
:2
0.9 Vee = 5.0V
iii
t-
:)
40 /
~
0
z 0.8
0.8 I-------+------~ Q.
t-
:) 20 /
0.7
0.6 L..-_ _ _......L._ _ _ _ _---I
0
o V
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0

1.6 1.1
5
101
0
1.5
V
~
1.0 /
t-
:)
Q.
t-
1.4
~
/ J~
0
101 0.9
/V
/
:)
0 1.3
N
:::::i /'
0
101
N
:::::i 1.2
V oC
:2
~
0
0.8
/ Vee =5.5V
oC
:2
~
0 1.1 / Vee =5.0V
TA = 25C -
z
0.7 / TA =250C -
V1N =OVor3V
z
1.0
o
L 200 400 600
1
800 1000
o
o 5 10 15 20 25
I I
30 35
CAPACITANCE (pF') FREQUENCY (MHz)
0041-10
5-118
I~ CY7C910
1'~~~DUcrOR==================================================================
Clock
Package Operating
Cycle Ordering Code
(ns) Type Range
40 CY7C91O-40PC P17 Commercial

CY7C91O-40DC D18
CY7C910-40JC J67
CY7C91O-40LC L67
46 CY7C910-46DMB D18 Military
CY7C91O-46LMB L67
50 CY7C91O-50PC P17 Commercial
CY7C91O-50DC D18
CY7C91O-50JC J67
CY7C91O-50LC L67
51 CY7C91O-51DMB D18 Military
CY7C91O-51LMB L67
93 CY7C91O-93PC Pl7 Commercial
CY7C91O-93DC D18
CY7C91O-93JC J67
CY7C91O-93LC L67
99 CY7C910-99DMB D18 Military
CY7C91O-99LMB L67
5-119
CY7C910 I I~
DC Characteristics Minimum Set-up and Hold Times
VOR 1,2,3 DI -+ RC Set-up Time 7,8,9,10,11
VOL 1,2,3 DI -+ RC Hold Time 7,8,9,10,11
VIH 1,2,3 DI -+ MPC Set-up Time 7,8,9,10,11
VILMax. 1,2,3 DI -+ MPC Hold Time 7,8,9,10,11
IIH 1,2,3 10-I3 Set-up Time 7,8,9,10,11
IlL 1,2,3 10-I3 Hold Time 7,8,9,10,11
lOR 1,2,3 CC Set-up Time 7,8,9,10,11
IOL 1,2,3 CCHold Time 7,8,9,10,11
loz 1,2,3 CCEN Set-up Time 7,8,9,10,11
Isc 1,2,3 CCEN Hold Time 7,8,9,10,11
Icc 1,2,3 CI Set-up Time 7,8,9,10,11
ICC! 1,2,3 CIHold Time 7,8,9,10,11
RLD Set-up Time 7,8,9,10,11
Clock Requirements RLD Hold Time 7,8,9,10,11
Minimum Clock LOW 7,8,9,10,11

From DO-D11 to Y 7,8,9,10,11
From 1O-I3 to Y 7,8,9,10,11
From 1O-I3 to PL, VC'f, MAP 7,8,9,10,11
FromCCtoY 7,8,9,10,11
From CCEN to Y 7,8,9,10,11
From CP (I = 8,9,15) to FULL 7,8,9,10,11
From CP (All Other I) to Y 7,8,9,10,11
From CP (All Other I) to FULL 7,8,9,10,11
5-120
CY7C9101
CYPRESS
SEMICONDUCTOR CMOS Sixteen-Bit Slice
Features
Fast Expandable The CY7C9101, as shown in the block
- CY7C9I01-30 has a 30 ns - Infinitely expandable in diagram, consists of a 16-word by
(max.) clock cycle 16-bit increments 16-bit dual-port RAM register file, a
(commercial) 16-bit ALU, and the necessary data
Four Status Flags
- CY7C9101-35 has a 35 ns - Carry, overflow, negative, manipulation and control logic.
(max.) clock cycle (military) The function performed is determined
zero
Low Power by the nine-bit instruction word (Is to
ESD Protection
- IcC (max. at - Capable of withstanding 10) which is usually input via a micro-
10 MHz) = 60 mA greater than 2000V static instruction register.
(commercial) discharge voltage The CY7C9101 is expandable in 16-bit
- IcC (max. at
10 MHz) = 85 mA Pin compatible and functionally increments, has three-state data out-
puts as well as flag outputs, and can
5
(military) equivalent to AM29CI0l
implement either a fulliook-abead car-
Vee Margin Functional Description ry or a ripple carry.
- 5V 10% The CY7C9101 is a pin compatible,
The CY7C9101 is a high-speed, ex-
All parameters guaranteed over pandable, 16-bit wide ALU slice which functional equivalent of the Am29ClOl
commercial and military can be used to implement the arithme- with improved performance. The
operating temperature range tic section of a CPU, peripheral con- 7C9101 replaces four 2901's and in-
troller, or programmable controller. cludes on-chip carry look-ahead logic.
Replaces four 2901's with carry
look-ahead logic The instruction set of the CY7C9101 is Fabricated in an advanced 1.2 micron
basic, yet so versatile that it can emu- CMOS process, the 7C9101 eliminates
Eight Function ALU
late the ALU of almost any digital latchup, has ESD protection greater
- Performs three arithmetic
computer. than 2000V, and achieves superior per-
and five logical operations
on two 16-bit operands formance with low power dissipation.
Logic Block Diagram '8-0 Pin Configuration

Top View
D, 5-0
(DIRECT
DATA-IN)
Y,5-0
DATA OUT 0079-1
Figure 1 0079-2
5-121
~ CY7C9101
_rs~UcroR ============================== III
Selection Guide
7C9101.30 7C910140
7C910135 7C910145
Minimum Clock Commercial 30 40
Cycle (ns) Military 35 45
Current at 10 MHz (mA)
Military 85 85
Maximum Ratings
Ambient Temperature with (Per MILSTD-883 Method 3015)
Power Applied .................... - 55C to + 125C Latchup Current (Outputs) .................. > 200 rnA
Supply Voltage to Ground Operating Range
Potential ........................... -0.5V to + 7.0V
Ambient
Temperature
Commercial OCto +70C 5V 10%
DC Input Voltage ................... -3.0V to +7.0V
Note:
Pin Definitions
Signal I/O Description Signal I/O Description
Name Name
RAM Address A. This 4-bit address word selects QlS, Output Mode: When the destination code on lines
one of the 16 registers in the register file for RAMIS I/O 16,7,8 indicates a left shift (UP) operation, the
output on the (internal) A-port. (Cont.) three-state outputs are enabled and the MSB of
RAM Address B. This 4-bit address word selects the Q register is output on the QIS pin and
one ofthe 16 registers in the register file for likewise, the MSB ofthe ALU output (FlS) is
output on the (internal) B-port. When data is output on the RAM 15 pin.
written back to the register file, this is the Input Mode: When the destination code indicates
destination address. a right shift (DOWN), the pins are the data
18-0 Instruction Word. This nine-bit word is decoded inputs to the MSB of the Q register and the
to determine the ALU data sources (10,1,2), the RAM, respectively.
ALU operation (13, 4, s), and the data to be Qo, These two lines are bidirectional and function
written to the Q-register or register file (16, 7, 8). RAMo I/O similarly to the QIS and RAMIS lines. The Qo
D1S-0 Direct Data Input. This 16-bit data word may be and RAMo lines are the LSB of the Q register
selected by the 10,1, 2 lines as an input to the and the RAM.
ALU. Cn I Carry In. The carry in to the internal ALU.
y IS-0 Data Output. These are three-state data output C n + 16 0 Carry Out. The carry out from the internal ALU.
lines which, when enabled, output either the G, P 0 Carry Generate, Carry Propagate. Outputs from
ALU result or the data in the A latch, as the ALU which may be used to perform a carry
determined by the code on 16, 7, 8. look-ahead operation over the 16-bits of the
OE Output Enable. This is an active LOW input ALU.
which controls the Y IS-0 outputs. A HIGH level OVR 0 Overflow. This signal is the logical exclusive-OR
on this signal places the output drivers at the high of the carry-in and carry-out of the MSB of the
impedance state. ALU. This indicates when the result of the ALU
CP Clock. The LOW level of CP is used to write data operation exceeded the capacity of the machine's
to the RAM register file. A HIGH level of CP two's complement number range. It is valid only
writes data from the dual port RAM to the A and for the sign bit.
B latches. The operation of the Q register is F = 0 0 Zero Detec!t. Open drain output which goes
similar; data is entered into the master latch on HIGH when the data on outputs (FlS-0) are all
the LOW level of CP and transferred from master LOW. It indicates that the result of an ALU
to slave during CP = HIGH. operation is zero (positive logic assumed).
Q1S, These two lines are bidirectional and are FIS 0 Sign. The MSB ofthe ALU output.
RAMIS I/O controlled by 16, 7, 8. They are three-state output
drivers connected to the TTL compatible CMOS
inputs.
5-122
I~~ CY7C9101
~~~~~==================================================================
Top View
GGC0C0eC0@(9
~ ~ ~ ~ G ~ ~ ~
80808<9<90<9008
53 52 49 47 45 43 41 39 37 35 34
~ ~ r - - - - - - - - - - - - - , e (9
55 54 32 33
80
57 56
98 30 31
08
59 58
00 28 29
(08
61
88
~
(0~
0) G
~
60
M
08
80
88
G8
-------------~
26
n
27
~

G8888GG8eSe
68 1 3 5 7 9 11 13 15 18 19
GGGC9C9GS8e
2 4 6 8 10 12 14 16 17
0079-11
CY7C9101 Pinout for 68PGA
NC = No Connect
Top View
"' ..
J~~~~fJ~3~~~J~~~~
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
N.C. 10 60 Y,4
0 ,4 11 59 V13
013 12 58 V,2
0 12 13 57 Vll
0 14 56 V,0
0 ",0 15 55 Vg
Og 16 54 V8
08 17 53 GNO
Vee 18 52 GNO
0 7 19 Sl OE
Os 20 50 Y7
Os 21 49 Vs
0 4 22 48 Ys
0 3 23 47 Y4
O2 24 46 V3
0 , 25 45 V2
,
Do 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43"" V
~~m~~di8~~~~:~~~~
'" ...
0079-3
CY7C9101 Pinout for LCCIPLCC
NC = No Connect
5-123
~ CY7C91011
~~~NDUcrOR =====================================================================
Functional Tables
Table 1. ALU Source Operand Control Table 2. ALU Function Control
ALUSource MicroCode
MicroCode ALU Symbol
Operands Mnemonic Octal
Mnemonic Function
Octal 15 4 13 Code
12 II 10 R S
Code ADD L L L 0 RPlus S R+S
AQ L L L 0 A Q SUBR L L H 1 SMinusR S-R
AB L L H 1 A B SUBS L H L 2 RMinusS R-S
ZQ L H L 2 0 Q OR L H H 3 RORS RVS
ZB L H H 3 0 B AND H L L 4 RANDS RI\S
ZA H L L 4 0 A NOTRS H L H 5 RANDS R 1\ S
DA H L H 5 D A EXOR H H L 6 REX-ORS RVS
DQ H H L 6 D Q EXNOR H H H 7 REX-NORS RVS
DZ H H H 7 D 0
Table 3. ALU Destination Control

Q-Reg. RAM
Micro Code RAM Function Q Shifter
Function Y Shifter
Mnemonic
Octal Output
IS 17 16 Shift Load Shift Load RAMo RAMIS Qo QI5
Code
QREG L L L 0 X None None F-+Q F X X X X
NOP L L H 1 X None X None F X X X X
RAMA L H L 2 None F-+B X None A X X X X
RAMF L H H 3 None F-+B X None F X X X X
RAMQD H L L 4 DOWN F/2 -+ B DOWN Q/2 -+ Q F Fo IN15 Qo IN15
RAMD H L H 5 DOWN F/2 -+ B X None F Fo IN15 Qo X
RAMQU H H L 6 UP 2F -+ B UP 2Q -+ Q F INo F15 INo Q15
RAMU H H H 7 UP 2F -+ B X None F INo F15 X Q15
x= Don't care. Electrically, the input shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
A = Register Addressed by A inputs.
B = Register Addressed by B inputs.
UP is toward MSB, DOWN is toward LSB.
Table 4. Source Operand and ALU Function Matrix

1210 Octal 0 1 2 3 4 5 6 7
ALU
Source
Octal ALU
1543 Function A,Q A,B O,Q O,B O,A D,A D,Q D,O
0 Cn = L A+Q A+B Q B A D+A D+Q D
RplusS
Cn = H A+Q+l A+B+l Q+l B+l A+l D+A+l D+Q+l D+l
1 Cn = L Q-A-l B-A-l Q-l B-1 A-I A-D-l Q-D-l -D-l
SminusR
Cn=H Q-A B-A Q B A A-D Q-D -D
2 Cn = L A-Q-l A-B-l -Q-l -B-1 -A-l D-A-l D-Q-l D-l
RminusS
Cn = H A-Q A-B -Q -B -A D-A D-Q D
3 RORS AVQ AVB Q B A DVA DVQ D
4 RANDS AI\Q AI\B 0 0 0 DI\A DI\Q 0
5 RANDS AI\Q AI\B Q B A DI\A DI\Q 0
6 REX-ORS AVQ AVB Q B A DVA DVQ D
7 REX-NORS AVQ AVB Q B A DVA DVQ D
+ = Plus; -=Minus; V =OR; 1\ = AND; = EX-OR
5-124
I
I WnWNDUcrOR
~ CY7C9101
==================================================================
General Description while RAM write enable (RAM EN) is active and the
The 7C9101 block diagram is shown in Figure 1. Detailed clock input is LOW. RAM EN is an internal signal decod-
block diagrams show the operation of specific sections as ed from the signals 16, 7, 8. As shown below, each of the 16
described below. The device is a 16-bit slice consisting of a RAM inputs is driven by a three-input multiplexer that
register file (16-word by 16-bit dual port RAM), the ALU, allows the ALU output (FI5-0) to be shifted one bit posi-
the Q-register and the necessary control logic. It is expand- tion to the left, right, or not shifted. The RAM15 and
able in 16-bit increments. RAMo I/O pins are also inputs to the 16-bit, 3-input multi-
plexer.
Register File During the left shift (upshift) operation, the RAMlS out-
The dual port RAM is addressed by two 4-bit address put buffer and RAMo input multiplexer are enabled. For
fields (A3-0 and B3-0) which cause the data to simulta- the down shift (right) operation, the RAMo output buffer
neously appear at the A or B (internal) ports. Both the A and the RAMlS input multiplexer are enabled.
and B addresses may be identical; in this case, the same The A and B outputs of the RAM drive separate 16-bit
data will appear at both the A and B ports. latches that are enabled (track the RAM data) when the
Data to be written to RAM is applied to the 0 inputs of
the 7C9101 and is passed (unchanged) through the ALU to
the RAM location specified by the B-address word. New
clock is HIGH. The outputs of the A latch go to three
multiplexers which feed the two ALU inputs (RI5-0 and
SI5-0) and the chip output (Y 15-0). The B latch outputs
III
data is written into the RAM by specifying a B address are directed to the multiplexer which feeds the S input to
theALU.
A3
A - ADDRESS A2 ) B-ADDRESS
[ A1
Ao WE
0079-4
Figure 2. Register File
5-125
~PRFBS
.nICoNDucroR
CY7C91011'
Description of Architecture (Continued)
QRegister tiplexers, under the control OfI6 7 8). The function of the
The 9-regis~er is mainly intended for use as a separate Q-register input multiplexers is to ~l1ow the ALU output
workmg regIster for multiplication and division routines. It ~F15-0) to be either shifted left, right, or directly entered
mar also ~unction as an accumulator or temporary storage l~tO t~e !llaster latches. The Q15 and Qo pins (I/O) func-
regIster. ~lxteen master-slave latches are used to implement tion slmtlarly to the RAM15 and RAMo pins described
th~ Q-reglster. As shown below, the Qregister inputs are
earlier. Data is entered into the master latches when the
dnven by the outputs of the Q-shifter (sixteen 3-input mul clock is LOW and transferred to the slave (output) at the
clock LOW to HIGH transition.
Q-SHIFTER
_. . . . . . . . . . . .l~~ T ..........
~
IS
17
>->- ALU
DESTINATION
~:--~~--~~--:.~
3-IN 3-IN
----:-~-
3-IN
~.:-- ~.:--~f-r-~
3-IN 3-IN 3-;'1.......
.........................--...1
1
6
DECODE
-----------(;
>-..- . . . . . .-.... .
MUX MUX MUX MUX MUX MUX
;:3:1~ -M~;) ---- ---- --

;
Lt-r-rTTTTTT...----'
I 05
>- t>.
I...------IQEN
CP
014 0 13
Q-REGISTER
O2 01 Do
Q15 Q14 Q13 Q12 Q3 Q2 Q1 Qo
0079-5
Figure 3. Q.Register
5-126
~CYPRESS CY7C9101
~~~O~UcrOR==================================================================
ALU (Arithmetic Logic Unit) 7C9101, using the ALU inputs carry in (Cn) and the ALU
outputs carry propagate (P), carry generate (0), carry out
The ALU can perform three arithmetic and five logical (Cn + 16), and overflow to implement carry lookahead
operations on the two 16-bit input operands, Rand S. The arithmetic and determine if arithmetic overflow has oc-
R-input multiplexer selects between data from the RAM curred. Note that the carry in (Cn ) signal affects the arith-
A-port and data at the external data input, 015-0. The metic result and internal flags; it has no effect on the logi-
S-input multiplexer selects between data from the RAM cal operations.
A-port, the RAM B-port, and the Q-register. The Rand S
multiplexers are controlled by the 10 1 2 inputs as shown Control signals 16, 7, 8 route the ALU data output (FlS-0)
in Table 1. The Rand S input multipl~xers each have an to the RAM, the Q-register inputs, and the Y -outputs as
"inhibit capability," offering a state where no data is shown in Table 3. The ALU result MSB (FlS) is output so
passed. This is equivalent to a source operand consisting of the user may examine the sign bit without needing to en-
all zeroes. The Rand S ALU source multiplexers are con- able the three-state outputs. The F = 0 output, used for
figured to allow eight pairs of combinations of A, B, 0, Q, zero detection, is HIGH when all bits of the F output are
and "0" to be selected as ALU input operands. LOW. It is an open drain output which may be wire OR'ed

across multiple 7C9101 processor slices.
The ALU functions, which are controlled by 13, 4, 5, are
shown in Table 2. Carry lookahead logic is resident on the
0 15 014 01 DO B15 B14 B1 BO

Q15
A15 14
AU

A1
AO
12
11
10
R1 Ro S15 S14 S1 G
j5
1 6-BIT ARITHMETIC LOGIC UNIT (ALU)
Cn+16
F15 F14 F1 Fo OVR
F15(SIGN)
F=O
Cn
ALU 18
DESTINATION 17
DECODE
16
OE
Y15 Y14 Y1 Yo
0079-6
Figure 4. ALU
5-127
~ CY7C9101
~~~NDUcrOR=====================================================================
Table S. ALU Logic Mode Functions Table 6. ALU Arithmetic Mode Functions
Octal Octal Cn = o(Low) Cn = 1 (High)
Group Function
1543t 1210 1543t 1210 Group Function Group Function
40 AAQ 00 A+Q A+Q+l
41 AAB 01 A+B ADD plus A+B+1
AND ADD
45 DAA 05 D+A one D+A+1
46 DAQ 06 D+Q D+Q+1
30 AVQ 02 Q Q+l
31 AVB 03 B B+1
OR PASS Increment
35 DVA 04 A A+1
36 DVQ 07 D D+1
60 AVQ 12 Q-1 Q
61 AVB 13 B-1 B
EX-OR Decrement PASS
65 DVA 14 A-I A
66 DVQ 27 D-1 D
70 AVQ 22 -Q-1 -Q
71 AVB 23 -B-1 2'8 Compo -B
EX-NOR l's Compo
75 DVA 24 -A-1 (Negate) -A
76 DVQ 17 -D-1 -D
72 Q 10 Q-A-l Q-A
73
INVERT
B 11 B-A-1 B-A
74 A 15 A-D-1 A-D
77 0 16 Subtract Q-D-1 Subtract Q-D
62 Q 20 (l's Comp.) A-Q-l (2's Comp.) A-Q
63 B 21 A-B-l A-B
PASS D-A-l D-A
64 A 25
67 D 26 D-Q-l D-Q
32 Q Conventional Addition and Pass-Increment!
33 B Decrement
PASS
34 A
37 D When the carry-in is HIGH and either a conventional ad-
dition or a PASS operation is performed, one (1) is added
42 0 to the result. If the DECREMENT operation is performed
43 0 when the carry-in is LOW, the value of the operand is
"ZERO"
44 0 reduced by one. However, when the same operation is per-
47 0 formed when the carry-in is HIGH, it nullifies the DEC-
REMENT operation so that the result is equivalent to the
50 AAQ PASS operation. In logical operations, the carry-in (Cn)
51 AAB will not affect the ALU output.
MASK
55 OAA
56 OAQ Subtraction
Recall that in two's complement integer coding - 1 is
equal to all ones and that in one's complement integer cod-
ing zero is equal to all ones. To convert a positive integer to
its two's complement (negative) equivalentt invert (comple-
ment) the number and add 1 to it; i.e., TWC = ONC + 1.
In Table 6 the symbol - Q represents the two's comple-
ment of Q so that the one's complement of Q is then
-Q -1.
5-128
~PFESS
.nEMICONDUcrOR ===================================================================
CY7C9101

VCC = Min.
IOH = -3.4mA
VCC = Min.
IOL = 16mA
VIH Input HIGH Voltage 2.0 VCC V
VSS :s: VIN :s: Vcc
IIX Input Leakage Current -10 10 ,."A
Vcc = Max.
Vcc = Min.
IOH Output HIGH Current -3.4 mA
VOH = 2.4V
Vcc = Min.
IOL Output LOW Current 16 rnA
VOL = O.4V
Vcc = Max. +40 ,."A
VOUT = VSS to VCC -40 ,."A
Vcc = Max.
Isc Output Short Circuit Current[ll -85 rnA
VOUT = OV
Supply Current Commercial VSS :s: VIN :s: VIL or 30
ICc(Ql) [2] mA
(Quiescent) Military VIH:S: VIN:S: Vcc; OE = HIGH 35
Icc(Q2) [2]
Supply Current Commercial VSS :s: VIN :s: O.4Vor 25
rnA
(Quiescent) Military 3.85V :s: VIN :s: V cc; OE = HIGH 30
Supply Current Commercial VCC = Max., fCLK = 10 MHz; 60
Icc(Max.) [2] rnA
Military OE = HIGH 85
Capacitance [3]
pF
COUT
Notes:
1. Not more than one output should be tested at a time. Duration of the 3. Tested initially and after any design or process changes that may
short circuit should not be more than one second. affect these parameters.
2. Two quiescent figures are given for different input voltage ranges. To 4. See the last page of this specification for Group A subgroup testing
calculate Icc at any given frequency, use IcdQI) + IcdA.C.) where information.
IcdQI) is shown above and IcdA.C.) = (3 mA/MHz) X Clock
Frequency for the Commercial temperature range. IcdA.C.) = Q
(5 mA/MHz) X Clock Frequency for Military temperature range.

+5 V +5 V
VOUT
2S2n
vo~270"
17sn
lCL
0079-10
0079-9 Open Drain (F = 0)
All Outputs except Open Drain
Notes:
1. CL = 50 pF includes scope probe, wiring and stray capacitance.
5-129
~ CY7C9101
~~~NDUcrOR==================================================================
Table 7. Logic Functions for CARRY and OVERFLOW Conditions
1543 Function P G Cn +16 OVR
0 R+S G15 + P15G14 + PI5 P I4G13 +

PO-PI5 C16 C16 C15
... + PI-15 Go
1 S-R +- Same as R + S equations, but substitute Ri for Ri in definitions ~
2 R-S +- Same as R + S equ~tions, but substitute Si for Si in definitions ~
3 RVS
4 RAS
5 RAS HIGH HIGH LOW LOW
6 RS
7 RS
Definitions: + = OR
PO-15 = PIS P14 P13 P12 Pll PlO P9 Pg P7 P6 Ps P4 P3 P2 PI Po
Po = Ro + So
PI = Rl + S2
P2 = R2 + S2
P3 = R3 + S3, etc.
GO-IS = GIS G14 G13 G12 Gll GlO G9 Gg G7 G6 GS G4 G3 G2 Gl GO
Go = RoSo
Gl = Rl SI
G2 = R2 S2
G3 = R3 S3, etc.
C16 = GIS + PIS G14 + PIS P14 G13 + ... + PO-IS C n
CIS = G14 + P14 G13 + P14 P13 G12 + ... + PO-14 C n
CY7C9101-30 and CY7C9101-40 Guaranteed Cycle Time and Clock Characteristics

Commercial Range AC Performance CY7C9101- 30 40
Characteristics Read-Modify-Write Cycle (from 30ns 40ns
selection of A, B registers to
The tables below specify the guaranteed AC performance end of cycle).
Military (- 55C to + 125C) operating temperature range Maximum Clock Frequency to shift Q 33 MHz 25 MHz
with Vee varying from 4.5V to 5.5V. All times are in (50% duty cycle, I = 432 or 632)
nanoseconds and are measured between the 1.5V signal lev- Minimum Clock LOW Time 20ns 25 ns
els. The inputs switch between OV and 3V with signal tran- Minimum Clock HIGH Time 10 ns 15 ns
sition rates of 1V per nanosecond. All outputs have maxi- Minimum Clock Period 30ns 40ns
mum DC current loads. See also loading circuit informa-
tion.
CY7C9101-30PC CY7C9101-30DC CY7C9101-30LC CY7C9101-30JC CY7C9101-30GC
CY7C9101-40PC CY7C9101-40DC CY7C9101-40LC CY7C9101-40JC CY7C9101-40GC
Combinational Propagation Delays. CL = 50 pF
To Output G,P F=O OVR RAMo Qo
Y F15 Cn + 16 RAM1S
From Input Q1S
CY7C9101- 30 40 30 40 30 40 30 40 30 40 30 40 30 40 30 40
A, BAddress 37 47 36 47 35 44 32 41 35 46 32 42 32 40 - -
D 29 34 28 34 25 32 25 30 29 36 21 26 27 33 - -
Cn 22 27 22 27 20 25 - - 22 26 22 26 24 30 - -
10,1,2 32 40 32 40 30 38 28 36 34 42 26 32 27 35 - -
13,4,5 34 43 33 42 33 42 27 35 34 40 32 42 29 38 - -
16,7, g 19 22 - - - - - - - - - - 22 26 22 26
A Bypass ALU
(I = 2XX) 25 30 - - - - - - - - - - - - - -
Clock~ 31 40 30 39 30 38 27 34 28 37 27 34 27 35 20 23
5-130
II~CYPRFSS CY7C9101
~~~~u~==============================================================
Set-Up and Hold Times Relative to Clock (CP) Input[t]
CP:
.)~ -~
Input --- 1---
Set-UpTime Hold Time Set-upTime Hold Time

BeforeH ~ L After H ~ L BeforeL ~ H AfterL ~ H
I CY7C9101- 30 40 30 40 30 40 30 40
A, B Source Address 10 15 3[3] 3[3] 30[4] 40[4] 0 0
B Destination Address 10 15 ~ Do Not Change[2] ~ 0 0
D - - - - 22 28 0 0
Cn - - - - 16 22 0 0
10, 1,2 - - - - 26 35 0 0
13,4,5 - - - - 29 37 0 0
16,7,8 10 12 ~ Do Not Change[2] ~ 0 0
RAMo, RAMI5, Qo, QI5 - - - - 11 14 0 0
Output Enable/Disable Times

Output disable tests performed with CL = 5 pF and measured to O.5Y change of output voltage level.
CY7C9101-30 OE Y 18 16 address may then be changed. The B address could be changed if it is
change".
5-131
~ CY7C91011 11
~~~U~==================================================================
CY7C9101-35 and CY7C9101-45 Guaranteed Cycle Time and Clock Characteristics [5]
Military Range AC Performance CY7C9101- 35 45
Characteristics Read-Modify-Write Cycle (from 35 ns 45 ns
The tables below specify the guaranteed AC performance selection of A, B registers to
of these devices over the Military ( - 55C to + 125C) op- end of cycle).
erating temperature range with V cc varying from 4.5V to Maximum Clock Frequency to shift Q 28 MHz 22 MHz
5.5V. All times are in nanoseconds and are measured be- (50% duty cycle, I = 432 or 632)
tween the 1.5V signal levels. The inputs switch between OV Minimum Clock LOW Time 23 ns 28ns
and 3V with signal transition rates of 1V per nanosecond. Minimum Clock HIGH Time 12 ns 17 ns
All outputs have maximum DC current loads. See also
loading circuit information. Minimum Clock Period 35 ns 45 ns

CY7C9101-35DMB CY7C9101-35LMB CY7C9101-35GMB
CY7C9101-45DMB CY7C9101-45LMB CY7C9101-45GMB
Combinational Propagation Delays CL = 50 pp[5]
To Output RAMo Qo
Y F15 Cn + 16 G,P F=O OVR
RAM15 Q15
From Input
CY7C9101- 35 45 35 45 35 45 35 45 35 45 35 45 35 45 35 45
A, BAddress 41 52 40 51 38 48 37 45 40 48 36 46 36 43 - -
D 31 37 31 36 29 36 28 32 33 40 23 32 30 35 - -
Cn 2S 30 24 29 23 27 - - 24 29 23 27 26 31 - -
10,1,2 36 44 35 43 33 41 31 38 38 46 29 38 30 38 - -
13,4,5 38 48 37 47 37 46 31 38 38 45 36 45 33 41 - -
16,7,8 21 24 - - - - - - - - - - 24 28 24 28
A BypassALU
(I = 2XX)
28 33 - - - - - - - - - - - - - -
Clock...f 35 44 34 43 34 42 30 37 34 40 28 38 30 37 21 25
Set-Up and Hold Times Relative to Clock (CP) Input[l, 5]

CP:
~,... -I-
Input --- 1---
Set-UpTime Hold Time Set-UpTime Hold Time

Before H ---+ L After H ---+ L Before L ---+ H After L ---+ H
CY7C9101- 35 45 35 45 35 45 35 45
A, B Source Address 12 17 3[3] 3[3] 35[4] 45[4] 0 0
B Destination Address 12 17 ~ Do Not Change[2] ---+ 1 1
D - - - - 25 30 0 0
Cn - - - - 19 24 0 0
10,1,2 - - - - 30 37 0 0
13,4,5 - - - - 33 40 0 0
16,7,8 12 16 ~ Do Not Change[2] ---+ 0 0
RAMo, RAM15, Qo, Q15 - - - - 13 15 1 1

CY7C9101-3S OE Y 20 17 address may then be changed. The B address could be changed if it is
change". 5. See the last page of this specification for Group A subgroup testing
information.
5-132
~J~ CY7C9101
~~~~NDUcrOR =======================================================================
Applications
Minimum Cycle Time Calculations for 16-Bit Systems
Speeds used in calculations for parts other than CY7C9101 and CY7C91O are representative for available MSI parts.
F=O
Cn+ 1 6
4
CY7C9101 OVR
F15
CY7C245
Data Loop
Clock to Output
Pipelined System, Add without Simultaneous Shift
12 CY7C245
Control Loop
Clock to Output
0079-15
12

CY7C901 A, B to Y, en + 16, OVR 37 MUX Select to Output 12
Register Setup 4 CY7C91O CC to Output 22
53 ns CY7C245 Access Time 20
66ns
RAt.1 15
F 1 5 1 - - - -....---~
CY7C9101 F=O 1-_ _.... +-____.......
OVR
Cn + 16
0079-13
Pipelined System, Simultaneous Add and Shift Down (RIGHT)

CY7C9101 A, B to Y, Cn + 16, OVR 37 MUX Select to Output 12
XORandMUX Prop. Delay, Select 20 CY7C91O CCtoOutput 22
to Output CY7C245 Access Time 20
CY7C9101 RAM15 Setup 11 66ns
SOns
5-133
~~================================================C==Y=7=C9==1=O=~:
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE 60 vs. VOLTAGE
1.6 1.2~------~--------~
I
1.4 ~ 1I-
so Vcc =5.0V
TA =25OC-
~
/
1.11-----+-------1 Z
(.)
J:> ""
0::
0:: 40
""
0 1.2 ~
"":J (.)
N
L 1.0 \------""Ioio7-----__f
"" 30
'" '"
(.)
< 0::
:2l 1.0 ~
0::
0
0
z
0.8 /' ost-----+---~~__f
CIl
I-
~
20
10
/' f= 10MHz I!:
'"
~
TA =~50C 0
0.6 OB~------~--------~ o
4.0 4.5 5.0 5.5 6.0 -55 25 125 o 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE(OC) OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT NORMALIZED FREQUENCY OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE vs. AMBIENT TEMPERATURE VI. OUTPUT VOLTAGE
175 1.6 ~------~-------~ 140
<- lSO ~ 120

5 ~
. /~ JIll" ~
1.4 1 - - - - - - + - - - - - - - - 1
I- I-
z 125 z 100
w
0::
", ""0::0:: V
0::
100 / 1.2 t----300~-I-------I
80 /
:::I ~
(.)
~
z 75 / Vee = 5.0V
TA =250C-
1.0 I-----+-----=~
(.)
~
z 60 / Vee =5.0V
TA =250 C -
iii
l- so / Vee =5.0V
iii
I-
:::I
40 /
/ /
:::I
Q..
I- OB 1 - - - - - + - - - - - - - 1 I!:
:::I 25 ~ 20
0
o
V 0.6 ~------~-------~
0
o
I
o 1.0 2.0 3.0 4.0 -55 25 125 o 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE(OC) OUTPUT VOLTAGE (V)
TYPICAL OUTPUT DELAY NORMALIZED Icc

CHANGE vs. OUTPUT LOADING vs. FREQUENCY
1.6 1.1
~w 1.5
~
1.0
./
0 V
I-
:::I
Q..
I-
1.4
/
./ ~
0 os
//
:::I
0 1.3 / ""!:::!
...J
/'
<
W
N
0
::::i 1.2
V ::2l
0::
0
z
OB
V Vee =5.5V
<
::2l
0::
0 1.1
/ Vee =5.0V
TA = 25OC-
0.7 / TA =25OC-
VIN = OVor 3V
z
1.0
o
/ 200 400 600
L
800 1000
o
o 5 10 15 20 25
I
30
I
3S

0079-14
5-134
I~ CY7C9101
.~~~NDUcrOR================================================================
Ordering Code
(ns) Type Range
CY7C9101-30 LC L81
CY7C9101-30 JC J81
CY7C9101-30 DC D30
CY7C9101-30 OC 068
40 CY7C9101-4O PC P29
CY7C9101-4O LC L81
CY7C9101-4O JC J81
CY7C9101-4O DC D30
CY7C9101-4O OC 068
35 CY7C9101-35 LMB L81 Military
CY7C9101-35 DMB D30
CY7C9101-35 OMB 068
45 CY7C9101-45 LMB L81
CY7C9101-45 DMB D30
CY7C9101-450MB 068
5-135
~RESS CY7C91011~
.nEMICONDUcrOR ===============================================================
VOH 1,2,3 From Cn to F = 7,8,9,10,11
VOL 1,2,3 From C n to OVR 7,8,9,10,11
VIH 1,2,3 From Cn to RAMo, 15 7,8,9,10,11
VILMax. 1,2,3 From 1012 to Y 7,8,9,10,11
IIX 1,2,3 From 1012 to F15 7,8,9,10,11
loz 1,2,3 From 1012 to C n + 16 7,8,9,10,11
Isc 1,2,3 Froin 1012 to G, P 7,8,9,10,11
Icc (Q1) 1,2,3 From 1012 to F = 7,8,9,10,11
Icc (Q2) 1,2,3 From 1012 to OVR 7,8,9,10,11
Icc (Max.) 1,2,3 From 1012 to RAMo, 15 7,8,9,10,11
From 1345 to Y 7,8,9,10,11
From 1J45 to F15 7,8,9,10,11
Parameters Subgroups From 1345 to C n + 16 7,8,9,10,11
From A, B Address to Y 7,8,9,10,11 From 1345 to G, P 7,8,9,10,11
From A, B Address to F 15
From A, B Address to C n + 16
7,8,9,10,11
7,8,9,10,11
From 1345 to F = 7,8,9,10,11
From 1J45 to OVR 7,8,9,10,11
From A, B Address to G, P 7,8,9,10,11 7,8,9,10,11
From A, B Address to F = 7,8,9,10,11
From 1345 to RAMO, 15
From 1678 to Y 7,8,9,10,11
From A, B Address to OVR 7,8,9,10,11 7,8,9,10,11
From 1678 to RAMo, 15
From A, B Address to RAMo, 15 7,8,9,10,11 7,8,9,10,11
From 1678 to Qo, 15
FromDtoY 7,8,9,10,11 From A Bypass ALU to Y 7,8,9,10,11
FromD toF15 7,8,9,10,11 (I = 2XX)
From D to C n + 16 7,8,9,10,11 From Clock ....Jf'"' to Y 7,8,9,10,11
FromDtoG,P 7,8,9,10,11 From Clock ....Jf'"' to F15 7,8,9,10,11
FromDtoF = 7,8,9,10,11 From Clock....Jf'"' to C n + 16 7,8,9,10,11
FromDtoOVR 7,8,9,10,11 From Clock ....Jf'"' to G, P 7,8,9,10,11
From D to RAMo, 15 7,8,9,10,11 From Clock ....Jf'"' to F = 7,8,9,10,11
FromCn toY 7,8,9,10,11 From Clock ....Jf'"' to OVR 7,8,9,10,11
From Cn to F15 7,8,9,10,11 From Clock ....Jf'"' to RAMo, 15 7,8,9,10,11
From Cn to C n + 16 7,8,9,10,11 From Clock....Jf'"' to Qo, 15 7,8,9,10,11
5-136
~~~ ========================C=Y::;7::;C::;9::;1::;O=1
IISet-up and Hold Times Relative to Clock (CP) Input
A, B Source Address 7,8,9,10,11 D Hold Time After L --. H 7,8,9,10,11
Set-up Time Before H --. L Cn Set-up Time Before L --. H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 Cn Hold Time After L --. H 7,8,9,10,11
Set-up Time Before L --. H 1012 Hold Time After L --. H 7,8,9,10,11
A, B Source Address 7,8,9,10,11 1J4S Set-up Time Before L --. H 7,8,9,10,11
Hold Time After L --. H 134S Hold Time After L --. H 7,8,9,10,11
B Destination Address 7,8,9,10,11 1678 Set-up Time Before H --. L 7,8,9,10,11
Set-upTime Before H --. L
1678 Hold Time After H --. L 7,8,9,10,11
1678 Hold Time After L --. H 7,8,9,10,11
Set-upTime Before L --. H RAMO, RAM1S, Qo, Q1S 7,8,9,10,11
7,8,9,10,11 Set-up Time Before L --. H
B Destination Address
Hold Time After L --. H RAMO, RAM1S, Qo, Q1S 7,8,9,10,11
D Set-up Time Before L --. H 7,8,9,10,11 Hold Time After L --. H
5-137
I
CY7C911S1
PRELIMINARY CY7C9116/CY7C9117 ;':111
CYPRESS ~~~~~~~~~~~~II
SEMICONDUCTOR CMOS 16-Bit
Microprogrammed ALU
Features
Fast CY7C9117 separate I/O ESD protection
- 35 ns worst case propagation - One and two operand - Capable of withstanding
delay, I to Y arithmetic and logical greater than 2001V static
Low power CMOS operations discharge voltage
- Icc (max. at 10 MHz) - Bit manipulation, field Pin compatible and functionally
14S mA (commercial) insertion/extraction equivalent to 29116, 29116A,
- Icc (max. static) = 68 mA instructions 29C116, 29117, 29117A, 29C117
(commercial) - Eleven types of instructions
Immediate instruction capability Functional Description
Vee margin
- 5V 10% 16-bit barrel shifter capability The CY7C9115, CY7C9116 and
- All parameters guaranteed CY7C9117 are high speed 16-bit mi-
32-word x 16-bit register file
over commercial and military croprogrammed Arithmetic and Logic
operating temperature range 8-bit status register Units, (ALU).
- Four ALU status bits
Instruction set and architecture The architecture and instruction set of
- Link bit and three user
optimized for high speed the devices are optimized for peripheral
definable status bits
controller applications controller applications such as disk
controllers, graphics controllers, com-
munications controllers, and modems .
..-----<:1 OEy . . - - - - < l O Ey
....--.....- - - -.....--1 >-""'---"'-K)t Y0-15

..--.....----_--1 ">--_'--::> Yo-,.
0-'5
OE T
0085-4 CT
0085-5
Figure 1. CY7C9115, CY7C9116 Block Diagram Figure 2. CY7C9117 Block Diagram
Selection Guide
7C911X-35 7C911X-40/45 7C911X-65 7C911X-79
Worst Case I-Y Commercial 35 45 65
Propagation Delay (ns) Military 40 65 79
Current @ 10 MHz (mA) Military 166 166 166
5-138
CY7C9115
5A~~NDUcroR =====================================================================
-
PRELIMINARY CY7C9116/CY7C9117

When used with the CY7C517 multiplier, the CY7C9115, instructions, prioritize, Cyclic Redundancy Check (CRC),
CY7C9116 and CY7C9117 also support micropro- status, and NO-OP. Instruction execution occurs in a sin-
grammed processor applications. gle clock cycle except for Immediate Instructions, which
The CY7C9115, CY7C9116 and CY7C9117 are shown in require two clock cycles to execute.
the block diagram, consists of a 32-word by 16-bit single- The CY7C9116 and CY7C9117 are pin compatible, func-
port RAM register file, a 16-bit arithmetic unit and logic tional equivalent of the industry standard 29116, 29116A,
unit, an instruction latch and decoder, a data latch, an 29C 116, 29117, 29117 A, 29C 117 with improved perform-
accumulator register, a 16-bit barrel shifter, a priority en- ance.
coder, a status register, a condition code generator and Fabricated in an advanced 1.2 micron, two-level metal
multiplexer, and three-state output buffers. CMOS process, the CY7C9115, CY7C9116 and
The instruction set of the CY7C9115, CY7C9116 and CY7C9117 eliminates latchup, has ESD protection greater
CY7C9117 can be divided into eleven instruction types: than 2001V, and achieves superior performance with low
single-operand, two-operand, single-bit shifts, rotate and power dissipation.
merge, rotate and compare, rotate by n-bits, bit oriented
Pin Configurations CY7C9115, CY7C9116

Top View Top View
1,4
1,3
1,5
Yo >-".p>-~.;-~~~:;'~~:l-~-SJ
9 8 7 6 5 4 3 2
------
In .... tt)
1 68 67 66 65 64 63 62 61
N .... 0
Y, Y3 10 60 Ig
112
Y5 17 NC 11 59 18
111 Y2
ys Is Y. 12 58 17
1,0 Y3 GNO 15 Y5 13 57 16
19 Y4 OEy GNO Y6 14 56 15
18 Y5 Y7 Va:, GNO 15 55 GNO

Va:, 14 OEy 16 54 Vee
17 Y6
Va:, 13 Y7 17 53 14
16 GND Y8 12 Vee 18 7C911S 52 13
15 OEy Y9
Y10
11
10
Vee 19 51 '2
GND Y7 Ya 20 50 '1
DLE CP Yg 21 49 10
Vee Vee GNO iEN Y10 22 48 CP
14 Vee Y11 SRE OLE 23 47 iEN
13 Y8 GNO 24 46 ill
12 Y9 ,J.JJ:P- Ii Ii >=",.!"~ ,!' ..... ~t> Y11 25 45 CT
1, Y,0 Y12 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4 r CET

0085-3
10 DLE
7C911SPLCC
CP GND
7C9116LCC 0085-22
iEN Y PLCC
SRE "
Y,2
CT Y,3
OET Y,4
T4 Y,S
T3 NC} RESERVED
GND NC
T2 T,
0085-2
7C9116
DIP
5-139
CY7C9115
(;n~~UcrOR=====================================================================
. PRELIMINARY CY7C9116/CY7C9117
Pin Configurations CY7C9117

Top View
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
Y3 10 60 19
~ 11 59 18
Y4 12 58 17
Ys 13 57 16
Y6 14 56 Is
GNO 15 55 GNO
OEy 16 54 Vee
Y7 17 53 14
Vee 18 52 13
Vee 19 51 12
Y8 20 50 11
Y9 21 49 10
Y10 22 48 CP
OLE 23 47 iEN
GNO 24 46 SRE
Yl1 25 45 CT
44
Y12 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 OEr
0085-6
LCCIPLCC
NC = No Connect
Top View
8eeeeGee8
51 49 47 45 44 42 40 38 36
8eee88888G8
53 52 50 48 46 43 41 39 37 35 34
ee 1"-------------, G@
55 54 33 32
GG~ ~
@G ~ ~
8859 58
88 29 28
8G60 61
00 26 27
e
62 63
08 25 24
88 0e
G64 65
~ ------------- 0 822 23
88888888808
68 1 3 5 7 9 12 14 16 18 19
Ge88C0Geee
2 4 6 8 10 11 13 15 17
0085-7
CY7C9117 Pin for 68 PGA
NC = No Connect
5-140
!lfir~DUC= ===================P='R.=E='L=I=M=I=N.=~=R=Y====C=Y=7=C=9=1=16=/=~=~=i=~=:=~=~;
The CY7C9115, CY7C9116 and CY7C9117 are 16-bit mi- data at the clock LOW to HIGH transition. Word instruc-
croprogrammed arithmetic and logic units comprised of tions write into all 16 bits of the accumulator, byte instruc-
the following sections (see block diagram): tions write into the lower eight bits.
32 Word x 16-Bit Register File 16-Bit Barrel Shifter
Data Latch The barrel shifter can rotate data input to it from either the
Instruction Latch and Decoder register file, the accumulator, or the data latch from 0 to 15
Accumulator bit positions. In word mode, the barrel shifter rotates a
16-bit word; in byte mode, it only atTects the lower eight
Logic Unit with a 16-bit Barrel Shift Capability
bits. The barrel shifter is used as one of the ALU inputs.
Arithmetic Unit
Arithmetic and Logic Unit
Priority Encoder
Condition Code Generator and Multiplexer The CY7C9115, CY7C9116 and the CY7C9117 haye an

arithmetic unit and a logic unit. The arithmetic unit is ca-
Status Register pable of operating on one or two operands while the logic
Output ButTers unit is capable of operating on one, two or three operands.
The two units in parallel are able to execute the one and
32-Word x 16-Bit Register File two operand instructions such as pass, complement, two's
The 32-word x 16-bit register file is a single port RAM complement, add, subtract, AND, OR, EXOR, NAND,
with a 16-bit latch at the output. The latch is transparent NOR, and EXNOR. Three operand instructions include
while CP is HIGH and latched when CP is LOW. IfIEN is rotate/merge and rotate/masked compare. There are three
LOW and the current instruction specifies the RAM at its data types supported by the CY7C9115, CY7C9116 and
destination, data is written into the RAM while CP is CY7C9117; bit, byte, and 16-bit word.
LOW. Word instructions write into all 16-bits ofthe RAM All arithmetic and logic unit operations can be performed
word addressed; byte instructions write into only the lower in either word or byte mode, with byte instructions per-
eight bits. formed only on the lower eight bits.
Use of an external multiplexer on five of the instruction Three status output are generated by the arithmetic unit:
inputs makes it possible to select separate read and write carry (C), negative (N), and overflow (OVR). A zero flag
addresses for the same NON-IMMEDIATE instruction. (Z) detects a zero condition, though this flag is not generat-
Immediate Instructions do not allow this two-address oper- ed by the arithmetic unit or the logic unit. These flags are
ation for the 7C9115 and 7C9116. The 7C9117 does sup- generated in either word or byte mode, as appropriate.
port two-address Immediate Instructions.
The arithmetic unit uses full carry look-ahead across all 16
Data Latch bits during arithmetic operations. The carry input to the
The data latch holds the 16-bit input to the CY7C9115, arithmetic unit comes from the carry multiplexer, which
CY7C9116 and CY7C9117 from the Y (bidirectional) bus can select either zero, one, or a stored carry bit (QC) from
for the 7C9115 and 7C9116 and the data bus for the the status register. Multiprecision arithmetic uses QC as
7C9117. When DLE is HIGH, the latch is transparent, it is the carry input.
latched when DLE is LOW. Priority Encoder
Instruction Latch and Decoder The priority encoder generates a binary-weighted code
The 16-bit instruction latch is always transparent, except based on the location of the highest order ONE in its input
when Immediate Instructions are executed. The Instruc- word or byte. The operand to be prioritized may be
tion Decoder decodes the instruction inputs into the inter- AND-ed with a mask to eliminate certain bits from the
nal signals which control the CY7C9115, CY7C9116 and priority encoding. This masking is performed by the logic
CY7C9117. All instructions other than Immediate Instruc- unit.
tions execute in a single clock cycle. In word mode, the output is a binary one ifbit 15 is the
Execution of Immediate Instructions takes two clock cy- first (unmasked) HIGH encountered, a binary two if bit 14
cles. During the first clock cycle, the Instruction Decoder is the first HIGH and so on. If bit 0 is the only HIGH, the
identifies the instruction as an Immediate Instruction and output of the priority encoder is binary 16. If no bits are
the Instruction Latch captures the instruction at the in- HIGH, a binary zero is output.
struction inputs. For Immediate Instructions, the data at In byte mode, only bits 7 through 0 are examined. Bit 7
the instruction inputs during the second clock cycle is used HIGH produces a binary one, bit 6 a binary two, and so
as one of the operands for the Immediate Instruction speci- on. If bit 0 is the only HIGH, a binary eight is output; if no
fied during the first clock cycle. Upon completion of the bits are HIGH, a binary zero is output.
Immediate Instruction (the end of the second clock cycle),
the Instruction Latch again becomes transparent. Condition Code Generator and Multiplexer
Accumulator The twelve condition code test signals are generated in this
section. The multiplexer selects one of these twelve and
The accumulator is a 16-bit edge triggered register. If the places it at the CT output. The multiplexer is addressed by
lEN is LOW and the current instruction specifies the accu- either using the Test Instruction or by using the bidirec-
mulator as its destination, the accumulator accepts Y input
5-141
CY7C9115\1
fiA~UaoR================================================================
.

PRELIMINARY
Pin Definitions
CY7C9116/CY7C9117 1,1
tional T bus as an input. The test instruction specifies the

Signal I/O Description
test condition to be placed at the CT output, but it does not Name
allow an ALU operation at the same time. Using the T bus
as input, the CY7C9115, CY7C9116 and CY7C9117 may Y 15-0 I/O Data Input/Output. These bidirectional lines are
simultaneously test and execute an instruction. The test used to directly load the 16-bit data latch when
instruction lines (14-0) take precedence over T 4-1 for test- OEy is HIGH. When OEy is LOW, the arithme-
ing status. tic unit or the logic unit output data is output on
Y15-0
Status Register 115-0 Instruction Word. This 16-bit word selects the
The 8-bit status word is held by the status register. The functions performed by the 7C9116. These lines
status register is updated at the end of all instructions ex- are also used to input data when executing Imme-
cept NO-OP, Save Status, and Test Status, provided the diate Instructions.
status register enable (SRE) and instruction enable (lEN) T4-1 I/O Status Input/Output. These bidirectional pins are
are both LOW. The status register is inhibited from chang- used to output the lower four status bits (OVR,
ing if either SIrn or lEN are HIGH. N, C, and Z) when OET is HIGH. When OET is
The lower four status bits are the ALU status: OVR (over- LOW, these lines are used as inputs to generate
flow), N (negative), C (carry), and Z (zero). The upper four the conditional test (CT) output.
bits are a link bit and three user-defined status bits (Flag1, CT 0 Conditional Test. One of twelve condition code
Flag2, Flag3). signals is selected by the condition code multi-
plexer to be placed on the CT output.
As stated above, when lEN and SRE are LOW, the status CT = HIGH for a pass condition; CT = LOW
register is updated at the end of all instructions other than for a fail condition.
NO-OP, Save Status, and Test Status. The lower four
status bits are updated under the above conditions, with DLE Data Latch Enable. The 16-bit data latch is trans-
the additional exception of when lEN and SRE are LOW parent when DLE is HIGH and latched when
and the Status Set/Reset instruction is performed on the DLEisLOW.
upper four bits. When lEN and SRE are LOW, the upper lEN Instruction Enable. The following occurs with
four status bits are only changed during their correspond- lEN LOW: Data may be written into the RAM
ing Status Set/Reset instructions and during Status Load when the clock is LOW, the Accumulator can
instructions in word mode. The Link-Status bit is also up- accept data during the clock LOW to HIGH
dated after every shift instruction. transition, and the Status Register can be updated
when SRE is LOW. If lEN is HIGH, CT is dis-
The status register can be loaded via the internal Y bus; it abled as a function of the instruction inputs. lEN
can also be selected as a source for the internal Y bus. should be LOW during the first half of the first
Loading the status register in word mode updates all eight cycle of Immediate Instructions.
bits of the status register. In byte mode, only the lower four
bits are updated. SRE Status Register Enable. The Status Register is
updated at the end of all instructions except NO-
Using the status register as a source in the word mode OP, Save Status, and Test Status when SRE and
loads all eight bits into the lower byte of the destination; lEN are both LOW. The Status Register is inhib-
the upper byte is zero-filled. In byte mode, the status regis- ited from changing when either SRE or lEN are
ter loads the lower byte of the destination; however the HIGH.
upper byte is unchanged. Interrupt and subroutine process-
OEy Y Output Enable. This controls the 16-bit Y 15-0
ing is facilitated by this store/load combination, which al-
I/O port. When OEy is LOW, the Y-outputs are
lows saving and restoring the status register. The lower
enabled, when OEy is HIGH, the Y outputs are
four bits of the status register can be read directly by out-
disabled (high impedance).
putting them to the T 4-1 outputs. These outputs are en-
abled when OET is HIGH. OET T Output Enable. The four bit T outputs are en-
abled when OET is HIGH: they are disabled
Output Buffers (high impedance) when OET is LOW.
Two sets of bidirectional buses exist on the CY7C9115 and CP Clock Pulse. The RAM output latch is transpar-
CY7C9116. The bidirectional Y bus (16 bits) is controlled ent when CP is HIGH; the RAM output is
by OEy. The three state outputs are enabled when OEy is latched when CP goes LOW. IfIEN is LOW and
LOW, they are at high impedance when OEy is HIGH. the current instruction specifies the RAM as the
This will allow data to be input to the data latch from the destination, then data is written into the RAM
external world. The second bidirectional bus is the four-bit while CP is LOW. If lEN is LOW, the Accumu-
T bus. These three state buffers are enabled by a HIGH on lator and Status Register will accept data at the
OET, which will output the internal ALU status bits clock LOW to HIGH transition. The instruction
(OVR, N, C, Z). IfOET is LOW, the T outputs are at high latch becomes transparent upon exiting an Imme-
impedance, and a test condition can be input on the T bus diate Instruction during a LOW to HIGH clock
to determine the CT output. transition.
The 7C9117 has separate Y bus output and Data Input D15-0 These input lines are used to directly load the
buses. All other pins are functionally equivalent to the data latch.
7C9115 and 7C9116. Y 15-0 I/O These output lines are used to present the arith-
metic unit or the logic unit output when OEy is
LOW. (CY7C9117 Y 15-0 and output only)
5-142
CY7C9115
I5A PRELIMINARY
~~NDUcrOR =====================================================================
'Instruction Set
CY7C9116/CY7C9117
rhe instruction set of the CY7C9115, CY7C9116 and updated. Save Status and Test Status instructions do not
ICY7C9117 is optimized for peripheral controller applica- change the status register. During Test Status instructions
tions. It features: Bit Set, Bit Reset, Bit Test, Rotate and the Y-bus (or D-bus for the CY7C9117) is undefined; the
I Merge, Rotate and Compare, and Cyclic-Redundancy- result is in the CT output.
,Check (CRC) generation, in addition to standard Single- or The eleven instruction types outlined below are described
Two-Operand logical and arithmetic instructions. A single in detail on the following pages.
clock cycle will execute all but the Immediate Instructions
which take 2 clock cycles. Single-Operand Rotate and Compare
Two-Operand Prioritize
The CY7C9115, CY7C9116 and CY7C9117 can operate in Single Bit Shift CRC
three different data modes: bit, byte and word (16 bits). Rotate and Merge Status
The LSB of the word is used for Byte Mode. Also in Byte Bit-Oriented No-Op
Mode when the status register is specified as the destina- Rotate by n Bits
tion, only the LSH (OVR, N, C, Z) of the register is
Table 1. Operand Source-Destination Combinations

Instruction Type Operand Combinations (Note 1) Instruction Type Operand Combinations (Note 1)
Source (R/S) Destination Non-Rotated
Rotated
Single Operand RAM (Note 2) RAM Mask(S) Source/
Source (U)
SOR ACC ACC Destination (R)
SONR D YBus Rotate and Compare
D(OE) Status CDAI D I ACC
D(SE) ACCand CDRI D I RAM
I Status CDRA D ACC RAM
0 CRAI RAM I ACC
I
Source (R) Source (S) Destination Source (R) Mask(S) Destination
Two Operand RAM ACC RAM Prioritize (Note 3) RAM RAM RAM
TORI RAM I ACC PRTl ACC ACC ACC
TOR2 D RAM YBus PRT2 D I YBus
TONR D ACC Status PRTNR 0
ACC I ACCand Data In Destination Polynominal
D I Status
Cyclic Redun- QLINK RAM ACC
Source (U) Destination dancy Check
Single Bit Shift RAM RAM CRCF
SHFTR ACC ACC CRCR
SHFTNR ACC YBus No Operation
D RAM -
NOOP
D ACC
D YBus Bits Affected
Source(U) Destination Set Reset Status OVR,N,C,Z
SETST LINK
Rotate n Bits RAM RAM RSTST Flag I
ROTRI ACC ACC SVSTR Flag2
ROTR2 D YBus SVSTNR Flag3
ROTNR TEST
Source (R/S) Destination Source Destination
Bit Oriented RAM RAM Store Status Status RAM
BORI ACC ACC ACC
BOR2 D YBus YBus
BONR
Source (R) Source (S) Destination
Non-Rotated
R.uUd
Source (U)
I Mask(S) Source/ Status Load D
ACC
ACC
I
Status
Status and
Destination (R)
ACC
Rotate and Merge D I ACC D I
ROTM D RAM ACC
ROTC D I RAM Test Condition (CT)
D ACC RAM Test Status (NEIlOVR) + Z Z+C
ACC I RAM NEIlOVR N
RAM I ACC Z LINK
Notes: OVR Flag I
1. If there is no division between the RIS operand or SOURCE and Low Flag2
DESTINATION, the two are a given pair. If a division exists, any C Flag3
combination is possible.
2. RAM cannot be used as source when both ACC and STATUS are
designated as a DESTINATION.
3. OPERAND and MASK must be different sources.
5-143
11
CY7C9115
~ PRELIMINARY CY7C9116/CY7C911
~~~~UcrOR==================================================================~
Instruction Set (Continued)
OEy is assumed LOW for all cases, allowing ALU outputs The instruction formats shown below are unique for each
on the Y - or D-bus. category. In both cases the desired operation, controlled by:
Instructions are individually distinguished by using the instruction inputs, is performed on the source with the
OP-CODES and 2 assigned quadrant bits. Four quadrants, result either placed on the Y -bus or stored in the destina- I
oto 3, have been assigned to each instruction type in order tion or both. The functions of Extending Sign Bit (D(SE))
to ease groupings of instructions and addressing modes. and Binary Zero (D(OE)) over 16 bits in the Word Mode
are available for cases where 8-bit to 16-bit conversion is
Single Operand Instructions necessary. The functions performed using Single Operand
Each Single Operand Instruction contains four designators: instructions update the LSB of the Status Register (OVR,
1. Mode (Byte or Word) N, C, Z) but do not effect the MSB (FLAG1, FLAG2,
2.0pcode FLAG3, LINK). Single Operation instructions are limited
3. Source when both the ACC and Status Register are the destina-
4. Address or Destination tion, the source cannot be RAM.
These designators are divided into two basic categories,
those which use RAM addresses and those that do not.
Single Operand Field Definitions
15 14 13 12 9 8 5 4 0
SOR I B/W I Quadrant Opcode SRC-Dest I RAM Address I
15 14 13 12 9 8 5 4 0
SONR I B/W I Quadrant Opcode SRC Destination I
Single Operand Instruction Set
15 14 13 12 9 8 5 4 0
Instruction [1] B/W[2] Quad [3] Opcode R/S[4] Dest[4] RAM Address/Destination
1100 MOVE SRC -+ Dest 0000 SORA RAM ACC 00000 ROO RAM Reg 00
1101 COMP SRC -+ Dest 0010 SORY RAM YBus .. . . . ...
1110 INC SRC + 1 -+ Dest 0011 SORS RAM Status 11111 R31 RAM Reg 31
1111 NEG SRC + 1 -+ Dest 0100 SOAR ACC RAM
SOR O=B 10 0110 SODR D RAM
1= W 0111 SOIR I RAM
1000 SOZR 0 RAM
1001 SOZER D(OE) RAM
1010 SOSER D(SE) RAM
1011 SORR RAM RAM
Instruction B/W Quad Opcode R/S[4] Destination
1100 MOVE SRC -+ Dest 0100 SOA ACC 00000 NRY YBus
1101 COMP SRC -+ Dest 0110 SOD D 00001 NRA ACC
SONR O=B 1110 INC SRC + 1 -+ Dest 0111 SOl I 00100 NRS Status [5]
1= W 11 1111 NEG SRC + 1 -+ Dest 1000 SOZ 0 00101 NRAS ACC, Status[s]
1001 SOZE D(OE)
1010 SOSE D(SE)
Notes:
1. Instruction mnemonic. 4. R = Source; S = Source; Dest = Destination.
2. B = Byte Mode, W = Word Mode. 5. Status is destination,
3. Quadrant subdivides instuctions into categories. Status i +- Yi i = 0 to 3 (byte mode)
i = 0 to 7 (word mode)
Y Bus and Status
Instruction Opcode Description B/W Y-Bus Flag3 Flagl Flag1 LINK OVR N C Z
SOR COMP SCR-+ Dest 1= W Y-+SRC NC NC NC NC 0 U 0 U
SONR INC SCR + 1 -+ Dest O=B Y-+ SRC +1 NC NC NC NC U U U U
MOVE SCR-+ Dest Y-+SRC NC NC NC NC 0 U 0 U
NEG SCR + 1 -+ Dest Y -+ SRC +1 NC NC NC NC U U U U
SRC = Source NC = No Change 1 = Set
U = Update 0= Reset i = 0 to 15 when not specified
5-144
CY7C9115
I5n~NDucrOR =====================================================================
.
; PRELIMINARY CY7C9116/CY7C9117
lnstruction Set (Continued)

Each Two Operand Instruction is constructed of 5 fields: Functions are performed on the specified Rand S sources
1. Mode (Byte or Word) and results are stored in the specified destination and/or
l.Opcode placed on the Y -bus. Arithmetic functions update the least
3. R Source significant nibble of the Status Register (OVR, N, C, Z)
t S Source while logical functions affect only the Nand Z bits. Execu-
5. Address or Destination tion of logical functions clear the OVR and C bits of the
Status Register.
These instructions are further divided into those using
RAM addresses and those that do not. The first type uses
two formats which differ only by quadrant designator.
Two Operand Field Definitions

15 14 13 12 9 8 5 4 0

TORI B/W Quadrant SRC-SRC, Dest Opcode RAM Address
15 14 13 12 9 8 5 4 0
TOR2 B/W Quadrant SRC-SRC, Dest Opcode RAM Address
15 14 13 12 9 8 5 4 0
TONR B/W Quadrant SRC-SRC, Dest Opcode Destination
Two Operand Instruction Set

Instruction B/W Quad R[1] S[I] Desdl] Opcode RAM Address
O=B 00 0000 TORAA RAM ACC ACC 0000 SUBR SminusR 00000 ROO RAM Reg 00
1= W 0010 TORIA RAM I ACC 0001 SUBRC[2] SminusR . ..
. . ...
0011 TODRA D RAM ACC with carry 11111 R31 RAM Reg 31
1000 TORAY RAM ACC YBus 0010 SUBS RminusS
1010 TORIY RAM I YBus 0011 SUBSC[2] RminusS
1011 TODRY D RAM YBus with carry
1100 TORAR RAM ACC RAM 0100 ADD RplusS
TORI 1110 TORIR RAM I RAM 0101 ADDC Rplus S
1111 TODRR D RAM RAM with carry
0110 AND ReS
0111 NAND ReS
1000 EXOR REElS
1001 NOR 'R+S
1010 OR R+S
1011 EXNOR 'R6f"S
Instruction B/w Quad R[I] S[I] Dest[t] Opcode RAM Address
O=B 10 0001 TODAR D ACC RAM 0000 SUBR SminusR 00000 ROO RAM Reg 00
1= W 0010 TOAIR ACC I RAM 0001 SUBRC[2] SminusR ..
... .. .
0101 TODIR D I RAM with carry 11111 R31 RAM Reg 31
0010 SUBS RminusS
0011 SUBSC[2] Rminus S
with carry
0100 ADD Rplus S
TOR2 0101 ADDC Rplus S
with carry
0110 AND ReS
0111 NAND I(i'"S
REElS
I
1000 EXOR
1001 NOR If+'''S
1010 OR R+S
I
1011 EXNOR If'TS
Notes:
1. R = Source 2. For subtraction the carry is interpreted as borrow.
S = Source
Dest = Destination
5-145
CY7C911
fin~NDUcrOR ====================================================================:'~'
.. PRELIMINARY CY7C9116/CY7C911

Two Operand Instruction Set
Instruction B/W Quad R[I] 8[1] Opcode Destination
O=B 11 0001 TODA D ACC 0000 SUBR Sminus R 00000 NRY YBus
1= W 0010 TOAI ACC I 0001 SUBRC S minus R with 00001 NRA ACC
0101 TODI D I carry 00100 NRS Status [2]
0010 SUBS RminusS 00101 NRAS ACC, Status[2]
TONR 0011 SUBSC R minus S with
carry
0100 ADD R plus S
0101 ADDC Rplus Swith
carry
0110 AND ReS
0111 NAND ReS
1000 EXOR Res
1001 NOR R+S
1010 OR R+S
1011 EXNOR Res
Notes:
I. R = Source
S = Source
2. Status is destination,
Status i +- Yi, i = 0 to 3 (byte mode)
i = 0 to 7 (word mode)
3. For subtraction the carry is inverted.
Y Bus and Status Contents

Instruction Opcode Description B/W V-Bus Flag3 Flag2 Flagi LINK OVR N C Z
ADD RplusS O=B Y~R+S NC NC NC NC U U U U
ADDC R plus S with carry 1= W Y~R+S+QC NC NC NC NC U U U U
AND ReS Y~RiANDSi NC NC NC NC 0 U 0 U
EXOR Res Yi ~ Ri EXOR Si NC NC NC NC 0 U 0 U
EXNOR Res Yi ~ Ri EXNOR Si NC NC NC NC 0 0 0 U
TORI
TOR2 NAND ReS Yi ~ Ri NAND Sj NC NC NC NC 0 U 0 U
TONR NOR R+S Yi~RiNORSi NC NC NC NC 0 U 0 U
OR R+S Yi~RiORSi NC NC NC NC 0 U 0 U
SUBR SminusR Y~S+R+l NC NC NC NC U U U U
SUBRC S minus R with carry Y~S+R+QC NC NC NC NC U U U U
SUBS RminusS Y~R+S+ 1 NC NC NC NC U U U U
SUBSC R minus S with carry Y~R+S+QC NC NC NC NC U U U U
U = Update
NC = No Change
0= Reset
1 = Set
i = 0 to 15 when not specified
Single Bit Shift Instructions

Single Bit Shift Instructions are constructed of four fields: During a shift up the LSB may be loaded with a zero, one
1. Mode (Byte or Word) or with the link status bit (QLINK), while the MSB is
2. Direction (up or down) and shift linkage shifted into the QLINK bit. During a shift down, the MSB
3. Source is loaded with a zero, one, the Status Carry bit (QC), the
4. Destination Exclusive-Or of the Negative-Status bit and the Overflow-
These instructions are further divided into those using Status bit (QN e QOVR), or the Link-Status bit. The
RAM addresses and those that do not. The shift linkage Status Register's Nand Z bits are updated, while the OVR
indicator indicates what is to be loaded into the vacant bit. and C bits are reset. Shift down with QN e QOVR can be
used in Two's Complement Multiplication.
5~146
CY7C9115
'Single Bit Shift Instructions (Continued)

Single Bit Shift Field Definitions
15 14 13 12 9 8 5 4 0
SHFTR I B/W I Quadrant I
SRC-Dest I
Opcode I RAM Address I
SHFTNR I B/W I Quadrant Source Opcode I Destination I
Shift Up Function Shift Down Function
SOURCE SOURCE
o
1
MUX QC MUX
QNeQOVR
QLlNK QLlNK
DESTINATION DESTINATION
0085-8 0085-9
Single Bit Shift Instruction Set

, Instruction B/W Quad U[t] Desdll Opcode RAM AddresslDestination
SHFTR O=B 0110 SHRR RAM RAM 0000 SHUPZ Up 0 00000 ROO RAM Reg 00
1 =W 10 0111 SHDR D 1 .. .. ....
RAM 0001 SHUP1 Up
0010 SHUPL Up QLINK 11111 R31 RAM Reg 31
0100 SHDNZ Down 0
0101 SHDN1 Down 1
0110 SHDNL Down QLINK
0111 SHDNC Down QC
1000 SHDNOV Down QNe QOVR
Instruction B/W Quad U[t] Opcode Destination
SHFTNR O=B 0110 SHA ACC 0000 SHUPZ Up 0 00000 NRY V-Bus
11 0111 SHD D 1 00001 NRA ACC
1= W 0001 SHUP1 Up
0010 SHUPL Up QLINK
0100 SHDNZ Down 0
0101 SHDN1 Down 1
0110 SHDNL Down QLINK
0111 SHDNC Down QC
1000 SHDNOV Down QNe QOVR
Note:
1. U = Source
Dest = Destination
Y Bus and Status
Instruction Opcode Description B/W V-Bus Flag3 Flagl Flag1 LINK OVR N CZ
SHR SHUPZ UpO 1 = W Yi ~ SRCi-loi = 1 to 15;
NC NC NC SRClS* 0 SRC14 OU
SHNR SHUP1 Up 1 Yo ~ Shift Input
SHUPL UpQLINK Yi ~ SRCj-loi = 1 to 7;
Y0 ~ Shift Input;
O=B NC NC NC SRC7* 0 SRC6 OU
Ys ~ SRC7, Yi ~ SRCj-9
fori = 9 to 15
l=W Yi ~ SRCi + 1, i = Oto14;
SHDNZ Down 0 Shift
NC NC NC 0
SHDN1 Down 1 YlS ~ Shift Input SRCo* Input OU
SHDNL DownQLINK Yi ~ SRCi + 1, i = 0 to 6;
I
SHDNC DownQC Shift
O=B Yi ~ SRCj-7, i = 8 to 14; NC NC NC SRCo* 0 OU
I
SHCNOV Down QN e QOVR Input
Y7,IS ~ Shift Input
" IShifted output is loaded into the QLINK.
SRC = Source 0 = Reset
U = Update 1 = Set
'NC = No Change i = 0 to IS when not specified
5-147
CY7C9115'
~~aa====================P=~=E=L=1=~=1=N=~=R=Y====C=Y=7=C=9=1=16=/=C=Y=7=C=9=1==17~:
II

Bit-Oriented Instructions Reset Bit n: Forces the nth bit to ZERO without affecting
other bit positions.
Bit-Oriented Instructions are constructed from four fields:
Test Bit n: Sets the Z status bit to the state of bit n.
1. Mode (Byte or Word)
Load 20 : Loads ZERO in bit position n and sets all other
2. Operation bits.
3. Source or Destination Load 20 : Loads ONE in bit position n and clears all other
4. Bit position operated on (0 = LSB) bits.
These instructions are further divided into those using Increment 20 : Adds 2n to the operand.
RAM addresses and those that do not. The specified func- Decrement 20 : Subtracts 2n from the operand.
tion operates on the given source and the result is stored in
the specified destination and/or on the V-bus. Load, Set, Reset and Test instructions update Nand Z
status bits while forcing OVR and C bits to ZERO. Arith-
Set Bit n: Forces the nth bit to ONE without affecting metic operations affect the entire lower nibble of the Status
other bit positions. Register (OVR, C, N, and Z).
Bit Oriented Field Definitions
15 14 13 12 98 54 0
BOR1 ! B/W I Quadrant I N I Opcode I RAM Address I
15 14 1312 98 54 0
BOR2! B/W I Quadrant I N I Opcode I RAM Address I
15 14 13 12 98 54 0
BONR! B/W I Quadrant I N 1100 Opcode I
Bit Oriented Instruction Set
Instruction B/W Quadrant 0 Opcode RAM Address
1101 SETNR Set RAM, bit n 00000 ROO RAM Reg 00
O=B
BOR1
1 =W
11 oto 15 1110 RSTNR Reset RAM, bit n .. .. ....
1111 TSTNR Test RAM, bit n 11111 R31 RAM Reg 31
Instruction B/W Quadrant n Opcode RAM Address
1100 LD2NR 2n ~ RAM
00000 ROO RAM Reg 00
BOR2 O=B 1101 LDC2NR 2ii ~ RAM
1= W
10 oto 15 1110 A2NR RAM plus 2n ~ RAM
.. .. ...
11111 R31 RAM Reg 31
1111 S2NR RAM minus 2n ~ RAM
Instruction B/W Quadrant n Opcode Opcode
00000 TSTNA Test ACC, bit n
00001 RSTNA Reset ACC, bit n
00010 SETNA Set ACC, bit n
00100 A2NA ACC plus 2n ~ ACC
00101 S2NA ACC minus 2n ~ ACC
00110 LD2NA 2n ~ ACC
O=B 00111 LDC2NA 2ii ~ ACC
BONR
1= W
11 oto 15 1100
10000 TSTND Test D, bit n
10001 RSTND Reset D, bit n
10010 SETND Set D, bitn
10100 A2NDY D plus 2n ~ Y Bus
10101 S2NDY D minus 2n ~ Y Bus
10110 LS2NY 2n ~ YBus
10111 LDC2NY 2ii ~ YBus
5-148
CY7C9115
I~ PRELIMINARY CY7C9116/CY7C9117
.~~~~UCKR==============================================================
Rotate By n Bits Instructions specifies the number of bit positions the source is to be
rotated up (0 to 15), and the result is either stored in the
The Rotate by n Bits Instructions contain four indicators: specified destination or placed on the Y bus or both. An
byte or word mode, source, destination and the number of example of this instruction is given in Figure 5. In the
places the source is to be rotated. They are further subdi- Word mode, all 16-bits are rotated up; while in the Byte
vided into two types. The first type uses RAM as a source mode, only the lower 8-bits (0-7) are rotated up. In the
and/or a destination and the second type does not use Word Mode, a rotate up by n bits is equivalent to a rotate
RAM as a source or destination. The first type has two down by (16-n) bits. Similarly, in the Byte mode a rotate
different formats and the only difference is in the quadrant. up by n bits is equivalent to a rotate down by (8-n) bits.
The second type has only one format as shown in the table. The Nand Z bits of the Status Register are affected and
Under the control of instruction inputs, the n indicator OVR and C bits are forced to ZERO.
Rotate By n Bits Field Definitions
15 14 13 12 9 8 54 0
ROTR1 B/W I Quadrant I n I SRC-Dest I RAM Address I
ROTR2 I B/w I Quadrant I n I SRC-Dest I RAM Address I
ROTNRI B/W I Quadrant I n I 1100 I SRC-Dest I
Rotate by n Example
EXAMPLE: n = 4, Word Mode
Source 0001 0011 0111 1111
Destination 0011 0111 1111 0001
EXAMPLE: n = 4, Byte Mode
Source 0001 0011 0111 1111
Destination 0001 0011 1111 0111
Rotate By n Bits Instruction Set
Instruction B/w Quadrant n U[I] Dest[I] RAM Address
1100 RTRA RAM ACC 00000 ROO RAM Reg 00
O=B
ROTR1
1= W
00 oto 15 1110 RTRY RAM YBus .. .. ....
1111 RTRR RAM RAM 11111 R31 RAM Reg 31
Instruction B/w Quadrant n U[I] Dest[I] RAM Address
O=B 0000 RTAR ACC RAM
ROTR2
1= W
01 oto 15 0001 RTDR D RAM
.... .. ....
11111 R31 RAM Reg 31
Instruction B/W Quadrant n Uri! Dest[I]
11000 RTDY D YBus
O=B 11001 RTDA D ACC
ROTNR
1= W
11 oto 15 1100
11100 RTAY ACC YBus
11101 RTAA ACC ACC
Note:
1. U = Source
Dest = Destination
Y Bus and Status

Instruction Opcode B/W V-Bus Flag3 Flag2 Flagl LINK OVR N C Z
ROTR1 1- W Yi ~ SRC(i n)mod16 NC NC NC NC 0 SRC15-n 0 U
ROTR2 Yj ~ SRCj + 8 = SRC(i -n)mod8
ROTNR O=B NC NC NC NC 0 SRC6-n 0 U
fori = Oto 7
SRC = Source
U = No Change
0= Reset
1 = Set
5-149
CY7C9115 ~
5r~~ PRELIMINARY CY7C9116/CY7C9117 I,ll

Rotate and Merge Instructions The shift register rotates source U up n places. ANDing
with the mask causes any bit i to be passed from the
Each Rotate and Merge instruction consists of five fields: rotated source that corresponds to a set bit in mask posi-
1. Mode (Byte or Word) tion i. The R input is not shifted, but is masked by the
2. Rotated Source (U) compliment of mask S, so that a ZERO in mask bit i will
pass bit i of R. The ORed result is stored in register R.
3. Non-Rotated Source (R) Rotate and Merge operations update the Nand Z status
4. Mask Location (S) bits, while clearing the OVR and C bits.
5. Number of bits Rotated (n)
Rotate and Merge Function
0085-10
Rotate and Merge Field Definitions

15 14 13 12 98 54 o
ROTM B/W I I
Quadrant n I U,R,S I RAM Address I I
U 0011 0001 0101 0110
Rotated U 0001 0101 0110 0011
R 1010 1010 1010 1010
Mask (S) 0000 1111 0000 1111
Destination 1010 0101 1010 0011
Rotate and Merge Instruction Set
Instruction B/W Quadrant n U[I] RlDest[l] S[I] RAM Address
0111 MDAI D ACC I
1000 MDAR D ACC RAM 00000 ROO RAM Reg 00
O=B 1001 MDRI D RAM I
ROTM
1= W
01 Oto 15
1010 MDRA D RAM ACC
.. .. . ...
11111 R31 RAM Reg 31
1100 MARl ACC RAM I
1110 MRAI RAM ACC I
Note:
1. U = Rotated Source
RJDest = Non-Rotated SourcelDestination
S = Mask
Y Bus and Status
Instruction Opcode B/W V-Bus Flag3 Flag2 Flagl LINK OVR N C Z
1 =W Yi ~ (Non Rot Op)j* (mask)j +
NC NC NC NC 0 U 0 U
(Rot Op)(i -n)mod w(mask)j
ROTM
Yj ~ (Non Rot 0p)j* (mask)j +
O=B NC NC NC NC 0 U 0 U
(Rot 0P)Jj-ntmod 8* (mask)j
U = Update
NC = No Change
0= Reset
1 = Set
5-150
CY7C9115
IWA~~NDUcrOR =====================================================================
. . PRELIMINARY CY7C9116/CY7C9117

Rotate and Compare Function
Rotate and Compare Instructions
The five fields of the Rotate and Compare instructions are: U R
2. Rotated Source (U)
n
3. Non-Rotated Source (R)
. 4. Mask (S)
5. Number of bits Rotated (n)
Input V is rotated n bits, ANDed with the inversion of S
and compared with the input R ANDed with the inversion AND AND
of S. Thus, a zero in the mask S will allow that bit of both

inputs to be compared. The Z bit of the Status Register is
set if the comparison passes, and reset if it does not. OVR
and C bits are reset in the Status Register.
COMPARATOR
(XOR)
0085-11
Rotate and Compare Field Definitions

15 14 13 12 98 54 o
ROTC I BIW I Quadrant I n V,R,S I RAM Address I
V 0011 0001 0101 0110
Rotated V 0001 0101 0110 0011
R 0001 0101 1111 0000
Mask (S) 0001 0101 1111 1111
Z (Status) = 1
Rotate and Compare Instruction Set
Instruction B/W Quad n V[I] R[I] S[I] RAM Address
0010 CDAI D ACC I
O=B 0011 CDRI D RAM I
ROTC
1 = W
01 o to 15 0100 CDRA D RAM ACC
.. .. . ...
11111 R31 RAM Reg 31
0101 CRAI RAM ACC I
Note:
1. U = Rotated Source
R = Non-Rotated Source
S = Mask
Y Bus and Status
Instruction Opcode B/W V-Bus Flag3 Flag2 Flag! LINK OVR N C Z
Yi +- (Non Rot Op)i* (mask)i E9
1= W NC NC NC NC 0 V 0 V
(Rot Op)(i - n) mod w(mask)i
ROTC Yi +- (Non Rot 0p)i* (mask)i E9
O=B NC NC NC NC 0 V 0 V
(Rot Op)(i - n) mod s*(mask)i
III
I U = Update
NC = No Change
0= Reset
I 1 = Set
I i = 0 to 15 when not specified
5-151
CY7C9115~'
(in
. ~~UcrOR==================================================================1
Prioritize Function
Prioritize Instruction
The four fields of the Prioritize instruction are:
2. Mask Source (S)
3. Operand Source (R)
4. Destination
The inverted mask, S is ANDed with R. A "one" in S
prohibits that bit from participating in the priority encod-
ing. From the 16-bit input, the priority encoder outputs a
5-bit binary weighted code indicating the bit-position of the
highest priority active bit. If there are no active bits, the
output is zero. See Figure for operation in both word and PRIORITY
byte mode. Using Prioritize updates the Nand Z bits of the ENCODER
Status Register, and forces C and OVR to zero. This in-
struction is limited in that the operand and the mask must 5
be different sources. DESTINATION 0085-12
Prioritize Instruction Field Defmitions

1514 1312 98 54 o
RAM Address/
Mask (S)
RAM Address/
Source (R)
RAM Address/
Destination
I B/W I Quad Mask(S) Source (R) Destination
Word Mode Byte Mode

Highest Highest
Encoder Encoder
Priority Priority
Output Output
Bit Active Bit Active
None 0 None 0
15 1 7 1
14 2 6 2
'" '" '" '"
'" '" '" '"
1 15 1 7
0 16 0 8
"'Bits 8 through IS not available.
Prioritize Instruction
Instruction B/w Quad Destination Source (R) RAM Address/Mask (S)
1000 PRIA ACC 00000 ROO RAM Reg 00
O=B 0111 RPTlA ACC
PRTI
1= W
10 1010 PRIY YBus
1001 PRI0 0 . . ...
1011 PRIR RAM 11111 R31 RAM Reg 31
Instruction B/W Quad Mask(S) Destination RAM Address/Source (R)
1000 PRA ACC 00000 ROO RAM Reg 00
0= B 0000 PR2A ACC
PRT2
1= W
10 1010 PRZ 0 0010 PR2Y YBus . . ...
1011 PRI I 11111 R31 RAM Reg 31
Instruction B/w Quad Mask(S) Source (R) RAM Address/Destination
1000 PRA ACC 0011 PR3R RAM 00000 ROO RAM Reg 00
O=B
PRT3
1= W
10 1010 PRZ 0 0100 PR3A ACC . . .. ,
1011 PRI I 0110 PR30 0 11111 R31 RAM Reg 31
Instruction B/w Quad Mask(S) Source (R) Destination
1000 PRA ACC
O=B 0100 PRTA ACC 00000 NRY YBus
PRTNR 11 1010 PRZ 0
1= W 0110 PRTD 0 00001 NRA ACC
1011 PRI I
5-152
!15'r~~ ==========P=~=E='L=I=M=I=N.='A=R=Y==C=Y=7=C=9=1=16~/~~~~~i~~~~~~~~~
Y Bus and Status-Prioritize Instruction
Instruction Opcode B/W V-Bus Flag3 Flagl Flagl LINK OVR N C Z
Yi . - CODE (SCRn*maskn);
PRTl 1= W Ym . - O;i = Ot04andn = Oto 15 NC NC NC NC 0 U 0 U
PRT2 m = 5 to 15
PRT3 Yi . - CODE (SCRn*maskn);
PRTNR O=B Ym . - O;i = Ot03andn = Ot07 NC NC NC NC 0 U 0 U
m=4to15
*U
Q NK IS loaded wIth the shIfted out bit from the checksum regIster.
SRC = Source 0 = Reset
U = Update 1 = Set
NC = No Change i = 0 to 15 when not specified
CRC Instruction tions are available to the user. The process for generating
the check bits for the CRC Forward and Reverse opera-
5
The single designator for this instruction is the address of
the RAM location that is used as the check sum register. tions are illustrated in the figures below. The ACC is used
Two CRC instructions, CRC Forward and CRC Reverse, as a polynomial mask while the RAM contains the partial
are available. These instructions give the procedure for de- sum and eventually the final check sum. The serial input
termining the check bits in a CRC calculation. Since the comes from the QLINK bit of the Status Register. Status
CRC standards do not specify which data bit is transmitted Register bits OVR and C are forced to zero while LINK N
first, the MSB or the LSB, both Forward and Reverse op- and Z bits are updated. '
Cyclic-Redundancy-Check Definitions
1514 13 12 98 54 0
CRCFI 1 I I
Quadrant 0110 I 0011 I RAM Address I
CRCRI I Quadrant I 0110 I 1001 I RAM Address I
CRC Forward Function
POLYNOMIAL MASK
(ACC)
SHIFTER N =1
"This bit must be transmitted first.

0086-13
S-lS3
I
(in
. PRELIMINARY
~~UcrOR=====================================================================
CY7C9115I'
CY7C9116/CY7C9117I'

CRC Reverse Function
POLYNOMIAL MASK
(ACC)
QLINK
0085-14
"This bit must be transmitted first.
Cyclic Redundancy Check Instruction Set

Instruction B/W Quad RAM Address
CRCF 1 10 0110 0011 .. .. ....
11111 R31 RAM Reg 31
Instruction B/W Quad RAM Address
CRCR 1 10 0110 1001 .. .. . ...
11111 R31 RAM Reg 31
Y Bus and Status

Instruction Opcode B/W V-Bus Flag3 Flagl Flagl LINK OVR N C Z
Yi +- [(QLINK E9 RAMlS)" ACCi]
CRCF 1 = W E9 RAMi - 1 for i = 15 to 1 NC NC NC RAMlS" 0 U 0 U
Yo +- [(QLINK E9 RAMlS). ACCQ] E9 0
Yi +- [(QLINK E9 RAMO) ACCi]
CRCR 1= W E9 RAMi + 1 fori = 14toO NC NC NC RAMo 0 U 0 U
Y IS +- [(QLINK E9 RAMo). ACClS] E9 0
*QLINK IS loaded with the shifted out bit from the checksum register.
U = Update 0 = Reset
NC = No Change 1 = Set
i = 0 to IS when not specified
5-154
~~U~================================================================
CY7C9115
I
[nstruction Set (Continued)

,tatus Instructions The status register may also be tested via the T bus as
7 6 5 4 3210 shown below. The instruction lines II thru 14 have bus
Flag3 I Flag2 I Flag I Link I OVR I N I C I z I priority for testing the status register on the CT output.
I"--~~--=-~--~~----~--~--~--~~
,et Status: Specifies which bits in the Status Register are to
I)e set.
T4
..
0
T3
13
0
Tl
11
0
Tl
11
0
cr
(N e OVR) + Z
il"Reset Status: Specifies which bits in the Status Register are
.10 be cleared. 0 0 0 1 NeOVR
Store Status: Indicates byte or word and the destination 0 0 1 0 Z
Into which the processor status is saved. The register is 0 0 1 1 OVR
llways stored in the low byte of the destination. The high 0 1 0 0 LOW
I byte is unchanged for RAM storage and is loaded with 0 1 0 1 C
z:eroes for ACC storage.
0 1 1 0 Z+C
Load Status: Imbedded in the Single- and Two-Operand

,[nstructions. 0 1 1 1 N
, :l'est Status: Instructions specify which of the 12 possible 1 0 0 0 LINK

test conditions are to be placed on the conditional test out- 1 0 0 1 Flag 1
put. In addition to the 8 status bits, four logical functions 1 0 1 0 Flag2
may be selected: N E9 OVR, (N E9 OVR) + Z, Z + ~, 1 0 1 1 Flag3
~nd LOW. These functions are useful in testing two's com-
plement and unsigned number arithmetic operations.
Status
IS 14 13 12 98 S4 0
SETST I 0 I Quad 1011 I 1010 I Opcode I
RSTST I 0 I Quad 1010 I 10tO I Opcode I
SVSTR I I B/W Quad 0111
I 1010
I RAM Address/
Dest I
SVSTNR I B/W I Quad 0111 I 10tO I Destination I
St tus Instruction Set
Instruction BIW Quad Opcode
00011 SONCZ Set OVR, N, C, Z
00101 SL Set LINK
SETST 0 11 tOll 10tO 00110 SFI Set Flag 1
01001 SF2 Set Flag2
OtOl0 SF3 Set Flag3
Instruction BIW Quad Opcode
00011 RONCZ Reset OVR, N, C, Z
00101 RL Reset LINK
RSTST 0 11 1010 10tO 00110 RF1 Reset Flag 1
01001 RF2 Reset Flag2
01010 RF3 Reset Flag3
Instruction BIW Quad RAM Address/Destination
O=B
SVSTR
1= W
to 0111 10tO .. .. ....
11111 R31 RAM Reg 31
Instruction BIW Quad Destination
O=B 00000 NRY YBus
SVSTNR 11 0111 10tO
l=W 00001 NRA ACC
Instruction BIW Quad Opcode(Cf)
00000 TNOZ Test (NeOVR) + Z
00010 TNO Test NeOVR
00100 TZ TestZ
001 to TOVR TestOVR
01000 TLOW Test LOW
OtOl0 TC TestC
Test 0 11 1001 10 to
01100 TZC TestZ + C
01110 TN TestN
10000 TL Test LINK
10010 TFI Test Flagl
10100 TF2 Test Flag2
10110 TF3 Test Flag3
Note: mN * test status instruction has priority over TI_4 instruction.
5-155
CY7C911
fin . PRELIMINARY
~~UcrOR==============================================================~==I
CY7C91 16/CY7C911

Y Bus and Status
Instruction Opcode Description B/W V-Bus Flagl Flag2 Flagl LINK OVR N C Z
RONCZ Reset OVR, N, C, Z O=B Yi ~ ofori = Oto 15 NC NC NC NC 0 0 0 0
RL Reset LINK NC NC NC 0 NC NC NC NC
RSTST RF1 Reset Flag1 NC NC 0 NC NC NC NC Nd
RF2 Reset Flag2 NC 0 NC NC NC NC NC Nell
RF3 Reset Flag3 0 NC NC NC NC NC NC Nd
SONCZ Set OVR, N, C, Z O=B Yi ~ 1 fori = Oto 15 NC NC NC NC 1 1 1 1
SL Set LINK NC NC NC 1 NC NC NC NC ,
SETST SF1 Set Flag1 NC NC 1 NC NC NC NC NC
SF2 Set Flag2 NC 1 NC NC NC NC NC NC
SF3 Set Flag3 1 NC NC NC NC NC NC NC
SVSTR O=B Yi ~ Status for i ~ 0 to 7;
Save Status'" NC NC NC NC NC NC NC NC
SVSTNR 1 = W Yi ~ Ofor i = 8 to 15
TNOZ Test (N e OVR) +Z O=B ...... NC NC NC NC NC NC NC NC
TNO Test (N e OVR) NC NC NC NC NC NC NC NC
TZ TestZ NC NC NC NC NC NC NC NC
TOVR TestOVR NC NC NC NC NC NC NC NC
TLOW Test LOW NC NC NC NC NC NC NC NC
TC TestC NC NC NC NC NC NC NC NC
Test
TZC TestZ +C NC NC NC NC NC NC NC NC
TN TestN NC NC NC NC NC NC NC NC
TL Test LINK NC NC NC NC NC NC NC NC
I
TF1 Test Flag1 NC NC NC NC NC NC NC NC
U = Update *In byte mode only the lower byte from the Y bus IS loaded mto the
NC = No Change RAM or ACC and in word mode all 16-bits from the Y bus are loaded
0= Reset into the RAM or ACC.
1 = Set **y -Bus is Undefined.
No-Op Instruction
The No-Op Instruction does not affect any internal regis-
ters; the Status Register, RAM register and AC register are
left unchanged. The 16-bit opcode is fixed.
No Operation Field Definition

1514 13 12 98 54 o
No-Op I 0 I 11 I 1000 I 1010 I 00000
No-Op Instruction
Instruction B/W
No-Op o 1000 1010 0000
'Y-Bus is undefined.
SRC = Source
U = Update i = 0 to 15 when not specified
NC = No Change
5-156
IWA
',I . CYPRESS PRELIMINARY
CY7C9115
CY7C9116/CY7C9117
II SEMICONDUCTOR =================================
Electrical Characteristics Over Commercial and Military Operating Range V CC Min. = 4.5V, V CC Max. = 5.5V

Vcc = Min.
IOH = -1.6mA
Vcc = Min.
IOL = 16 rnA
VIH Input HIGH Voltage 2.0 VCC V
VSS::;; VIN ::;; VCC
IIX Input Leakage Current -10 + 10 JLA
Vcc = Max.
I Vcc = Max. +10 JLA

VOUT = Vss to Vcc -10
I
JLA
Output Short Vcc = Max.
Isc -85 mA
Circuit Current[1] VOUT = OV
Supply Current Commercial Vss ::;; VIN ::;; VIL or 126
Icc{Ql)[2] mA
(Quiescent) Military VIH::;; VIN::;; Vcc; OEy = HIGH 145
Commercial VIN = Vcc orGNO 68 mA
Supply Current
Icc{Q2) Military Vcc = Max.
(Static) 78 rnA
IOPER = 0 JLA
Commercial Vcc = Max., fCLK = 10 MHz 145
ICc{Max.) (2) Supply Current rnA
Military OEy = HIGH 166
Capacitance [3]
pF
Output Capacitance Vcc = 5.0V 7
COUT
Notes:
1. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second.
2. To calculate Icc at any given frequency, use IcdQt) + IcdA.C.) where Icc(Qt) is shown above and IcdA.C.) = 1.9 mA/MHz X Clock Frequency
for the Commercial temperature range. IcdA.C.) = 2.1 rnA/MHz X Clock Frequency for Military temperature range.
Output Loads Used for AC Performance Characteristics

+5V All Outputs All Input Pulses
3.0 V -------jlr!'!~--'-.I
R1 =114.Q.
VOUT~2.22V
256.0.
0085-16
VOUTo-.....- - - -... ..5 ns

0085-17
0085-15
Notes:
1. CL = 50 pF includes scope probe, wiring and stray capacitance.
5-157
CY7C9115
fM~~NOOaoR==============================================================PRELIMINARY CY7C9116/CY7C9117 ~
Commercial Switching Characteristics

Guaranteed Commercial Range A.C. Performance Characteristics
+ 70C, vee = 4.5Vto5.5V,CL = 50pF)
(TA = OCto
Combinational Propagation Delays (ns)

To Output
From Input YO-IS TI-4 cr
CY7C9116
35 45 65 35 45 65 35 45 65
CY7C9117
10-4 35 45 65 35 52 73
(ADDR)
10-15 35 45 65 35 52 73
(DATA)
10-15 35 45 65 35 52 73 20 29 30
(INST)
DLE 20 32 55 30 32 55
TI-4 15 25 27
CP 30 32 60 30 32 66 25 25 37
YO-IS 20 32 53 30 32 53
lEN 15 25 25
*DLE is guaranteed by other tests.
EnablelDisable Times (ns) (CL = 5 pF, Disable Only)

Enable Disable
From To
TpZH TpZL TpHZ TpLZ
Input Output
35 45 65 35 45 65 35 45 65 35 45 65
OOy YO-YI5 18 20 22 18 20 22 18 20 22 18 20 22
OET TI-T4 15 20 22 15 20 22 15 20 22 15 20 22
Clock and Pulse Requirements (ns)

Minimum Low Time Minimum High Time
Input
35 45 65 35 45 65
CP 15 15 20 15 15 15
DLE 15 15 15
lEN 15 15 20
5-158
I fiA . PRELIMINARY
CY7C9115
CY7C9116/CY7C9117
~DUcrOR==================================================================
Set-up and Hold Times (ns)
With High to Low Low to High
[5] Input Respect Transition Transition Comments
To
Set-up Hold Set-up Hold
CY7C9116 and CY7C9117 35 45 65 35 45 65 35 45 65 35 45 65
10-4 Single Addr
1 CP 12 13 13 0 0 0
(RAM Addr) (Source)
10-4 CP& Two Addr
2
(RAM Addr)
5 5 5 +- Do Not Change -+ 0 2 0
lEN (Destination)
10-15
3 CP 40 43 60 0 0 0
(Data)
10-4 Two Addr

4 lEN 15[1] 18[1) 24[1] 4[1] 5[1] 10[1]
(RAM Addr)[2] (Immediate)
5 10-15 15[1) 18[1) 24[1] 4[1] 5[1] 10[1]

CP 40 43 60 0 0 0
(Instr) [3]
lEN [2] Two Addr

6 CP 8 8 8
(Immediate)
7 lEN HIGH CP 5 5 5 0 1 2 Disable
8 lEN LOW CP 10 10 10 0 1 1 Enable
9 lEN LOW CP 5 5 5 1 1 0 Note 1
10 SRE CP 12 12 12 0 2 0
11 y[4] CP 32 32 42 0 0 0
12 y[4] DLE 6 6 6 5 5 5
13 DLE CP 20 25 43 0 0 0
Notes:
1. Timing for immediate instruction for first cycle.
2. CY7C9117 only.
3. CY7C9115 and CY7C9116 only.
4. Y = D for CY7C91l7.
5. tsx and tHK referenced on the waveforms are looked up on this table by x = line number on the left. Ex: tSI = 13 ns for - 53 ns devices.
Military Switching Characteristics

Guaranteed Military Range A.C. Performance Characteristics
(TA = - 55C to + 125C, V cc = 4.5V to 5.5V, CL = 50 pF)
Combinational Propagation Delays (ns)

To Output
YO-I5 TI-4 CT
From Input
CY7C9116
40 65 79 40 65 79 40 65 79
CY7C9117
10-4
40 65 79 40 65 79
(ADDR)
10-15 40 40
65 79 65 79
(DATA)
10-15 22
40 65 79 40 65 79 26 29
(lNST)
DLE* 20 52 62 30 52 62
TI-4 15 26 29
CP 30 57 67 35 65 75 33 33 39
YO-15 20 52 60 30 52 60
lEN 20 26 29
*DLE is guaranteed by other tests.
5159
CY7C9115I
~~~ PRELIMINARY CY7C9116/CY7C9117 I
Military Switching Characteristics (Continued)

EnableIDisable Times (ns) (CL = 5 pF, Disable Only)
Enable Disable
From To
TpZH TpZL TpHZ TpLZ
Input Output
40 65 79 40 65 79 40 65 79 40 65 79
OEy YO-YI5 18 22 25 18 22 25 18 18 25 18 18 25
OET TI-T4 18 18 20 18 18 20 15 15 20 15 15 20
Clock and Pulse Requirements (ns)

Minimum Low Time Minimum High Time
Input
40 65 79 40 65 79
CP 15 20 25 15 15 15
DLE 15 15 15
lEN 15 15 15
Set-up and Hold Times (ns)

With High to Low Low to High
[5] Input Respect Transition Transition Comments
To Set-up Hold Set-up Hold
CY7C9116 and CY7C9117 40 65 79 40 65 79 40 65 79 40 65 79
10-4 Single Addr
1 CP 12 12 12 0 1 1
(RAM Addr) (Source)
10-4 CP& 5 . Two Addr
2 7 7 +- Do Not Change -+ 0 0 0
(RAM Addr) lEN (Destination)
3 10-15 CP 43 56 65 0 0 0
(Data)
10-4 15[1] 27[1] 5[1] 12[1] Two Addr
4
(RAM Addr)[2]
lEN 25 12
(Immediate)
5 10-15 (Instr)[3] CP 15[1] 25 27[1] 5[1] 12 12[1] 45 56 65 0 2 2
lEN [2] Two Addr

6 CP 8 8 8
(Immediate)
7 lEN HIGH CP 5 5 5 0 2 2 Disable
8 mNLOW CP 10 10 12 0 3 3 Enable
9 mNLOW CP 7 7 7 0 3 3 Note 1
10 SIrn CP 10 10 12 0 1 1
11 y[4] CP 39 45 53 0 0 0
12 y[4] DLE 7 7 7 3 3 3
13 DLE CP 20 46 54 0 0 0
Notes:
1. Timing for immediate instruction for first cycle. 4. Y = D for CY7C9117.
2. CY7C9117 only. S. tsx and tHX referenced on the waveforms are looked up on this table
3. CY7C911S and CY7C9116 only. by x = line number on the left. Ex: tSI = 24 ns for - 79 ns devices.
5-160
CY7C9115
~PFESS
WnEMICONDUcrOR ==================================
Switching Waveforms
Single Address Access Timing
ONE CYCLE
CP I t h3 I
1
ts3
t s13 t h13 -I
XXXXXXXXxxxxx XXXXXXXXXXXXXX
\-t. 1....
iEN
DISABLE xxxxxxxxxxxxxxx IXXXXXXxxxxxxxxxx
WRITE
~
ts14 ~
t h8
iEN
ENABLE XXXXXXXxxxxxxxxxxxx ts8_ IXXXXXXxxxxxxxxxx
WRITE
th12
I' t. 12
OLE I I\\\\\\\\.\'.\.\.\. yxxxxxxx
I-t.9 _ I-th9 -j
I-
SRE I r
o XXXXXXXXXXXY
t:=..tSll t h11 -
~
(INPUT)
yxxxxxxxxxxxxxxxx
I t a10 thl0
Ifthll is satisfied, thlO need not be satisfied 0085-18
Double Address Access Timing

1 - - - - ONE CYCLE ---~
t----_
CP
----.....
0085-19
One-Address Immediate Instruction Cycle Timing
0085-20
Two-Address Immediate Instruction Timing (7C9117 Only)
0085-21
5-161
CY7C9115
PRELIMINARY CY7C9116/CY7C9117 . I
Set-up and Hold Times (Cross Ref. Table)

High to Low Low to High
[1] Transition Transition
Set-up Hold Set-up Hold
1 tSl thl
2 tS2 th2
3 tS3 th3
4 tss ths
5 tS4 th4 tS13 th13
6 th6
7 tS7 th7
8 tS8 th8
9 tS14 th14
10 tS9 th9
11 tSlO thlO
12 tSl1 thll
13 tS12 th12
Note:
1. Refer to Set-up and Hold times shown on pages 22 & 23.
35 CY7C911535JC J69 Commercial 35 CY7C911735GC G68 Commercial
45 CY7C911545JC J69 CY7C911735JC J81
65 CY7C911565JC J69 CY7C911735LC L81
45 CY7C911745GC G68
Speed Package Operating CY7C911745JC J81
Ordering Code
(ns) Type Range
CY7C9117 45LC L81
35 CY7C911635LC L69 Commercial
65 CY7C911765GC G68
CY7C911635JC J81
CY7C911765JC J81
CY7C911635DC D28
CY7C9117-65LC L81
45 CY7C911645LC L69
40 CY7C91174OGC G68 Military
CY7C911645JC J81
CY7C9117 40JC J81
CY7C911645DC D28
CY7C91174OLC L81
65 CY7C911665LC L69
65 CY7C911765GMB G68
CY7C911665JC J81
CY7C911765LMB L81
CY7C911665DC D28
79 CY7C911779GMB G68
40 CY7C911640LC L69 Military
CY7C911779LMB L81
CY7C91164OJC J81
CY7C91164ODC D28
65 CY7C911665LMB L69
CY7C9116-65DMB D28
79 CY7C911679LMB L69
CY7C911679DMB D28
5-162
CY7C9115
~p~ PRELIMINARY CY7C9116/CY7C9117
~~~O~UcrOR======================================~~~~==~~~~~~==
Military Specifications
DC Characteristics
VOH 1,2,3
VOL 1,2,3
VIR 1,2,3
VILMax. 1,2,3
IIX 1,2,3
loz 1,2,3
ISC 1,2,3
Icc(Q1) 1,2,3
IcdMax) 1,2,3
10_4(Addr) 7,8,9,10,11
10-ls(Data) 7,8,9,10,11
10-IS(lnstr) 7,8,9,10,11
DLE 7,8,9,10,11
tl-4 7,8,9,10,11
CP 7,8,9,10,11
YO-IS 7,8,9,10,11
lEN 7,8,9,10,11
OEy 7,8,9,10,11
OET 7,8,9,10,11
CP 7,8,9,10,11
5-163
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO

PLDTOOLKIT III
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
..
g
PACKAGES

15'A
1 CYPRESS Section Contents
S~IOO~U~R=;=;=;=;=;=====;=====;=====;=========;=====;=;===;=====;==========
RIse Page Number

Introduction to RISC .................................................................................... 6-1
CY7C601 32-Bit RISC Integer Unit ................................ , ....... , ............ 6-6
CY7C602 Floating-Point Unit ............................................. , ........... 6-12
CY7C604 Cache Controller and Memory Management Unit ................................ 6-13
CY7C605 Multiprocessor Cache Controller and Memory Management Unit ................... 6-17
CY7C608 Floating-Point Controller ........................................ , ........... 6-18
CY7C609 Floating-Point Processor ..................................................... 6-23
CYPRESS
SEMICONDUCTOR
Introduction to RISe
Introduction gest the same conclusion. As advances in semiconductor
technology reduce the cost of processing and memory,
This section provides an overview of the basic concepts and overly complex instruction sets become a performance lia-
advantages of RISC computer architectures in general and bility. The designers of RISC machines strive for hardware
a brief summary of the specific features of the RISC com- simplicity, with close cooperation between machine archi-
puter implemented in Cypress' CY7C600 family. tecture and compiler design. At each step, computer archi-
tects must ask: to what extent does a feature improve or
Scalable Processor Architecture degrade performance and is it worth the cost of implemen- r:IIII
The Cypress CY7C600 family implements a RISC archi- tation? Each additional feature, no matter how useful it is l:1li
tecture called SPARCTM. SPARC stands for Scalable in an isolated instance, makes all others perform more
Processor ARChitecture. It is applicable to large high per- slowly by its mere presence.
formance as well as small machines. The term "scalable" The goal of RISC architecture is to maximize the effective
refers to the size of the smallest lines on a chip. As lines speed of a design by performing infrequent functions in
become smaller, chips get faster. However, some chip de- software, including hardware-only features that yield a net
signs do not shrink well (they do not scale properly) be- performance gain. Performance gains are measured by con-
cause the architecture is too complicated. Because of its ducting detailed studies of large high-level language pro-
simplicity, the CY7C600 scales well. Consequently, grams. RISC improves performance by providing the
CY7C600 systems will become faster as better semiconduc- building blocks from which high-level functions can be
tor techniques are perfected. SPARC is an open computer synthesized without the overhead of general but complex
architecture. We believe that the intelligent and aggressive instructions.
nature of the SPARC design will make it an industry stan-
dard. The design specification is published, and other ven- RISC Architecture
dors are also producing SPARC microprocessors.
The following characteristics are typical of RISC architec-
What is RISC? tures, including the CY7C600 design:
RISC, an acronym for Reduced Instruction Set Computer, Single-cycle execution. Most instructions are executed in a
is a style of computer architecture emphasizing simplicity single machine cycle.
and efficiency. RISC designs begin with a necessary and Hardwired control with no microcode. Microcode adds a
sufficient instruction set. Typically, a few simple operations level of complexity and raises the number of cycles per
account for almost all computations. RISC machines are instruction.
about two to five times faster than machines with tradition-
al complex instruction set architectures. Also, RISC ma- Load/Store, register-to-register design. All computational
chine's simpler designs are easier to implement, resulting in instructions involve registers. Memory accesses are made
shorter design cycles. with only load and store instructions.
RISC architectures are a response to the evolution from Simple fixed-format instructions with few addressing
assembly language to high-level languages. Assembly lan- modes. All instructions are one word long (typically 32
guage programs occasionally employ elaborate machine in- bits) and have few addressing modes.
structions, whereas high-level language compilers rarely Pipelining. The instruction set design allows for the pro-
do. For example, most C compilers use only about 30% of cessing of several instructions at the same time.
the available instructions on CISC machines. Studies show High-performance memory. RISC machines have at least
that approximately 80% of a typical program's computa- 32 general-purpose registers (the 7C600 has 136) and large
tions require only about 20% of a processor's instruction cache memories.
set.
Migration of functions to software. Only those features
RISC is to hardware what the UNIX operating system is that measurably improve performance are implemented in
to software. The UNIX system proves that operating sys- hardware. Programs contain sequences of simple instruc-
tems can be both simple and useful. Hardware studies sug-
SPARCTM, Sun-4, and NFSTM are trademarks of Sun Microsystems, Inc.
UNIX is a registered trademark of AT&T Bell Laboratories.
VAX is a registered trademark of Digital Equipment Corporation.
6-1
~ Introduction to RIsel
~~~NDUcrOR=======================================================================
tions for executing complex functions rather than the com- 1
plex instructions themselves. P =
1
Simple, efficient instruction pipeline visible to compilers. I X C X-
S
For example, branches take effect after execution of the
following instruction, permitting a fetch of the next in- Compiled programs on RISC machines are somewhat larg-
struction during execution of the current instruction. er than compiled programs on traditional machines, be-
cause several simple instructions replace one complex in-
The real keys to enhanced performance are single-cycle ex- struction resulting in decreased code density. All SPARC
ecution and keeping the cycle time as short as possible. instructions are 32 bits wide, whereas some instructions on
Many characteristics of RISC architectures, such as load/ traditional machines are narrower. But the number of in-
store and register-to-register design, facilitate single-cycle structions actually executed may not be as great as the
execution. Simple fixed-format instructions, on the other increased program size would indicate. A windowed regis-
hand, permit shorter cycles by reducing decoding time. ter file, for example, often simplifies call/return sequences
Note that some of these features, particularly pipelining so that context switches become less expensive.
and high-performance memories, have been used in super-
computer designs for many years. The difference is that in CY7C600 Architecture
RISC architectures these ideas are integrated into a proces-
sor with a simple instruction set and no microcode. The SPARC CPU is composed ofa CY7C601 Integer Unit
(IU) that performs basic processing and a CY7C608 Float-
Moving functionality from run time to compile time also ing-Point Controller (FPC) interface to the CY7C609
enhances performance. Functions calculated at compile Floating-Point Processor that performs floating-point cal-
time do not require further calculating each time the pro" culations. The CY7C608/CY7C609 combination acts as a
gram runs. Furthermore, optimizing compilers can rear- SPARC compatible Floating-Point Unit (FPU). CY7C600-
range pipelined instruction sequences and arrange register- based computers typically have a memory management
to-register operations to reuse computational results. unit (MMU), a large virtual-address cache for instructions
A new set of simplified design criteria has emerged: and data, and are organized around a 32-bit data and in-
struction bus.
Instructions should be simple unless there is a good reason
for complexity. To be worthwhile, a new instruction that The integer and floating-point units operate concurrently.
increases cycle time by 10% must reduce the total number The FPU performs floating-point calculations with a set
of cycles executed by at least 10%. number of floating-point arithmetic units. The CY7C600
architecture also specifies an interface for the connection of
Microcode is generally no faster than sequences of hard- an additional coprocessor.
wired instructions. Moving software into microcode does
not make it better, it just makes it harder to modify. Instruction Categories
Fixed-format instructions and pipelined execution are The CY7C600 architecture has about 50 integer instruc-
more important than program size. As memory gets cheap- tions. CY7C600 instructions fall into seven basic catego-
er and faster, the space/time tradeoff resolves in favor of ries:
time. Reducing space no longer decreases time.
Load and store instructions (the only way to access memo-
Compiler technology should use simple instructions to gen- ry). These instructions use two registers or a register and a
erate more complex instructions. Instead of substituting a constant to calculate the memory address involved. Half-
complicated microcoded instruction for several simple in- word accesses must be aligned on 2-byte boundaries, word
structions, which compilers did in the 1970s, optimizing accesses on 4-byte boundaries, and double-word accesses
compilers can form sequences of simple, fast instructions on 8-byte boundaries. These alignment restrictions greatly
out of complex high-level code. Operands can be kept in speed up memory access.
registers to increase speed even further.
Arithmetic/logical/shift instructions. These instructions
RISC's Speed Advantage compute a result that is a function of two source operands
and then place the result in a register. They perform arith-
Using any given benchmark, the performance P of a partic- metic, logical, or shift operations.
ular computer is inversely proportional to the product of
the benchmark's instruction count (I), the average number Floating-point and coprocessor instructions. These include
of clock cycles per instruction (C), and the inverse of the floating-point calculations, operations on floating-point
clock speed (S). Assuming that a RISC machine runs at the registers, and instructions involving the optional coproces-
same clock speed as a corresponding traditional machine; S sor. Floating-point operations execute concurrently with
is identical. The number of clock cycles per instruction (C), IU instructions and with other floating-point operations
is around 1.3 to 1.7 for RISC machines, and between 4 and when necessary. This concurrency is transparent to the
10 for traditional machines. This makes the instruction ex- programmer.
ecution rate of RISC machines about 3 to 6 times faster Control-transfer instructions. These include jumps, calls,
than traditional machines. But, because traditional ma- traps, and branches. Control transfers are usually delayed
chines have more powerful instructions, RISC machines until after execution of the next instruction, so that the
must execute more instructions for the same program, typi- pipeline is not emptied every time a control transfer occurs.
cally about 10% to 30% more. Since RISC machines exe- Thus, compilers can be optimized for delayed branching.
cute 10% to 30% more instructions 3 to 6 times more
quickly, they are about 2 to 5 times faster than traditional
machines for executing typical large programs.
6-2
1'I 115)l
i '-
I
CYPRESS
SEMICONDUCI'OR ================================================================
Introduction to RISe
Read/write control register instructions. These include in- standards allow users to acquire the most cost-effective
;tructions to read and write the contents of various control hardware and software in a competitive multi-vendor mar-
registers. Generally the source or destination is implied by ketplace. Integrated circuits come from several competing
'the instruction. semiconductor vendors, while software is supplied by sys-
Artificial intelligence instructions. These include the tems vendors. This advantage is lost when users are limited
'tagged arithmetic instructions Tagged Add and Tagged by a processor with proprietary hardware and software.
Subtract. Tagged instructions are useful for implementing RISC architectures, and the CY7C600 design in particular,
artificial intelligence languages such as LISP, because tags are easy to implement because they are relatively simple.
can automatically indicate to software interpreters the data Since they have short design cycles, RISC machines can
type of arithmetic operands. absorb new technologies almost immediately, unlike more
'Multiprocessing instructions. These include two instruc- complicated computer architectures.
tions for implementing semaphores in memory: Atomic CY7C600 systems were designed to support:
Load/Store Unsigned Byte which loads a byte from memo- The C programming language and the UNIX operating
ry then sets the location to all "1 's" and SWAP which system,
exchanges the contents of a register and a memory loca-
tion. Both of these instructions are "atomic" or uninter- Numerical applications (using FORTRAN), and
ruptable. Artificial intelligence and expert system applications us-
ing Lisp and Prolog.
Register Windows
Supporting C is relatively easy; most modern hardware ar-
A unique feature contributing to the high performance of chitectures are able to do so. The one essential feature is
the CY7C600 design is its overlapping register windows. byte addressability. However, numerical applications re-
Results left in registers by a calling routine automatically quire fast floating-point operations and artificial intelli-
become available operands for the called routine, reducing gence applications require large address spaces and inter-
the need for load and store instructions to main memory. changeability of data types.
According to the architectural specification, there may be The floating-point processor, with pipelined floating-point
anywhere between 2 and 32 register windows, each window operation capabilities, achieves the high performance need-
having 24 working registers, plus 8 global registers. The ed for numerical applications.
first implementation has 8 register windows with 24 regis-
ters each (but count only 16 since 8 overlap), plus 8 global For artificial intelligence and expert system applications,
registers, for a total of 136 registers. Recent research sug- CY7C600 systems offer tagged instructions and word
gests that register windows and tagged arithmetic, found in alignment. Because languages such as Lisp and Prolog are
,CY7C600 systems, but not in other commercial RISC ma- often interpreted, word alignment makes it easier for inter-
chines, are sufficient to provide excellent performance for preters to manipulate and interchange integers and differ-
expert system development requiring AI languages such as ent types of pointers. In the tagged instructions, the two
Lisp and Smalltalk. low-order bits of an operand specify the type of operand. If
an operand is an integer, most of the time it is added to (or
Traps and Interrupts subtracted from) a register. If an operand is a pointer, most
The CY7C600 design supports a full set of traps and inter- of the time a memory reference is involved. Language in-
rupts. They are handled by a table that supports 128 hard- terpreters can leave operands in the appropriate registers,
ware and 128 software traps. Even though floating-point greatly improving the performance of exploratory pro-
instructions can execute concurrently with integer instruc- gramming environments.
tions, floating-point traps are precise because the FPU sup- The CY7C600 architecture does not dictate a memory
plies (from the table) the address of the instruction that management unit (MMU), although a high performance
failed. unit has been specified for the SPARC architecture. The
same processor will be used in different types of machines.
Protection For example, a single-user machine with embedded appli-
Some CY7C600 instructions are privileged and can only be cations does not need an MMU. By contrast, a multitask-
executed while the processor is in supervisor mode. This ing machine used for timesharing, such as a traditional
instruction execution protection ensures that user pro- UNIX workstation, needs a paging MMU. Furthermore, a
grams cannot accidentally alter the state of the machine multiprocessor such as a vector machine or hypercube re-
with respect to its peripherals. quires specialized memory management facilities. The
CY7C600 architecture can be implemented with a different
The CY7C600 design also provides memory protection, MMU configuration for each of these purposes, without
which is essential for smooth multitasking operation. affecting user software.
Memory protection makes it impossible for user programs
to corrupt the system, other user programs, or themselves. CY7C600 Machines and Other RISC
Machines
An Open Architecture The CY7C600 design has more similarities to Berkeley's
Advantages of Open Architecture RISC-II architecture than to any other RISC architecture.
Like the RISC-II architecture, it uses register windows in
The CY7C600 design is the first open RISC architecture, order to reduce the number of load/store instructions. The
and one of the few open CPU architectures. Standard prod- CY7C600 architecture allows 32 register windows, but the
ucts are more beneficial than proprietary ones, because
6-3
~ Introduction to RISC
~~~NDUcrOR ==================================================================
initial implementation has 8 windows. The tagged instruc- window. The windows are joined together in a circular
tions are derived from SOAR, the "Smalltalk On A RISC" stack where the outs of the last window are the ins of the
processor developed at Berkeley after implementing first window.
RISC-II. The IV supports a multitasking operating system by pro-
CY7C600 systems are designed for optimal floating-point viding user and supervisor modes. Some instructions are
performance, and support single-, double-, and extended- privileged and can only be executed while the processor is
precision operands and operations, as specified by the in supervisor mode. Changing from user to supervisor
ANSI/IEEE 754 floating-point standard; High floating- mode requires taking a hardware interrupt or executing a
point performance results from concurrency of the IV and trap instruction.
FPV. The integer unit loads and stores floating-point oper-
ands, while the floating-point unit performs calculations. If The IV supports both asynchronous traps (interrupts) and
an error (such as a floating-point exception) occurs, the synchronous traps (error conditions and trap instructions).
floating-point unit specifies precisely where the trap took Traps transfer control to an offset within a table. The base
place; execution is expediently resumed at the discretion of address of the table is specified by a Trap Base Register
the integer unit. Furthermore, the floating-point unit has and the offset is a function of the trap type. Traps are taken
an internal instruction queue; it can operate while the inte- before the current instruction causes any changes visible to
ger unit is processing unrelated functions. the programmer and can therefore be considered to occur
between instructions.
CY7C600 systems deliver very high levels of performance.
The flexibility of the architecture makes future systems ca- CY7C608 Floating-Point Controller
pable of delivering performance many times greater than The CY7C608 Floating-Point Controller (FPC), in combi-
the performance of the initial implementation. Moreover, nation with a CY7C609 Floating-Point Processor (FPP),
the openness of the architecture makes it possible to absorb form a SPARC compatible Floating-Point Vnit or FPU.
technological advances almost as soon as they occur. The FPV and CY7C601 IV operate concurrently. The
FPV recognizes floating-point instructions and places them
CY7C600 Product Family in a queue while the IV continues to execute non-floating-
Since the CY7C600 has been designed to offer a complete point instructions. If the FPV encounters an instruction
solution for the implementation of high performance com- which will not fit in its queue, the FPV holds the IV until
puters and controllers, the family consists of several mem- the instruction can be stored.
bers including an Integer Vnit, a Floating-Point Control- The FPV contains its own set of registers on which it oper-
ler, a Floating-Point Processor, a Cache Controller and ates. The contents of these registers are transferred to and
Memory Management Vnit, and a Cache Data RAM. from external memory under control of the IV via floating-
The SPARC processor family consists of a CY7C601 Inte- point load/store instructions. Processor interlock hardware
ger Vnit (IV) to perform all non-floating-point operations provides floating-point concurrency which guarantees that
and a CY7C608 Floating-Point Controller (FPC) which the programming model is preserved from the point of
interfaces to a CY7C609 Floating-Point Processor to per- view of the compiler or assembly language programmer. A
form floating-point arithmetic concurrent with the IV. program containing floating-point computations generates
Support is also provided for a second generic coprocessor the same results as if instructions were executed sequential-
interface. The IV communicates with external memory via ly.
a 32-bit address bus and a 32-bit data/instruction bus. In
typical data processing applications, the IV and FPV are CY7C609 Floating-Point Processor
combined with a high performance CY7C604 Cache Con- The CY7C609 combines a multiplier and an arithmetic
troller and Memory Management Vnit and a cache memo- logic unit in a single microprogrammable VLSI device. The
ry implemented with CY7Cl57 Cache RAMs. In many CY7C609 is capable of operating at the same clock rate as
dedicated controller applications the IV can function by the Cypress IV and FPC and provides on the order of 4 to
itself with high speed local memory only. 4.9 Megaflops of double precision Linpack floating-point
performance when operated at 33 MHz with these devices.
CY7C601 Integer Unit The CY7C609 is fully compatible with the IEEE standard
The IV is the basic processing engine which executes all of for binary floating-point arithmetic, STD 754-1985. The
the instruction set except for floating-point operations. The Floating-Point Processor performs both single and double
CY7C601 IV contains a large 136 x 32 triple-port register precision operations, including division and square root.
flle which is divided into 8 windows. Each window con-
tains 24 working registers and has access to the same 8 CY7C604 Cache Controller and Memory
global registers. A current window pointer (CWP) field in Management Unit
the Processor State Register keeps track of which window
is currently active. The CWP is decremented when the The CY7C604 Cache Controller and Memory Manage-
processor calls a subroutine and is incremented when the ment Vnit (CMV) provides hardware support for a de-
processor returns. mand-paged virtual memory environment for the
CY7C601 processor. The CY7C604 conforms to the stan-
The registers in each window are divided into ins, outs, and dard SPARC architecture definition for memory manage-
locals. Each window shares its ins and outs with adjacent ment. Page size is fixed at 4K bytes. The CMV translates
windows. The outs of the previous window are the ins of 32-bit virtual addresses from the processor into 36-bit
the current window, and the outs of the current window physical addresses and provides both write-through and
are the ins of the next window. The globals are equally buffered copy-back cache policies. The on-chip context reg-
available to all windows and the locals are unique to each ister allows support of up to 4096 contexts.
6-4
~ Introduction to RISe
~~~NDUcrOR =====================================================================
High speed address look-up is provided by an on-chip The CY7C604 also contains the logic required in a system
translation lookaside buffer. Each entry contains the virtu- to implement the byte and half-word write capabilities pro-
al to physical mapping of a 4K byte page. If a virtual ad- vided in the SPARC instruction set. Cache tag update is
dress match is detected in one of the TLB entries, the phys- also simplified by an automatic tag update on miss feature
ical address translation contained in that entry will be de- which eliminates the need for processor accesses during tag
livered to the outputs of the CMU. If the virtual address update.
from the processor has no corresponding entry in the
CMU, the CMU will automatically perform address trans- CY7C157 Cache Data RAM
lation for the virtual address using on-chip hardware to The CY7C157 16K x 16 static RAMs are designed to inter-
access a main memory resident three-level page table. Each face easily to and provide maximum performance for the
"matched" TLB entry is checked for protection violation CY7C600 processor. The RAM has registered address in-
automatically and violations are reported to the Integer puts and latched data inputs and outputs as well as a self-
Unit as memory exceptions. timed write pulse which greatly simplifies the design of
The CMU also provides storage for 2048 cache address cache memories for the CY7C601 Integer Unit. The device
tags for a 64K byte cache with a 32 byte line size. The tag has a single clock that controls loading of the address regis-
entries can be directly written or read by the processor. In ter, data input latches, data output latches, pipeline control
normal operation, twelve low order bits 15-5 of the virtual latch, and chip enable register. The chip enable is clocked
address from the processor are used to select one of the tag into a register and pipelined through a control register to
entries in the CY7C604 and its 16-bit contents are com- condition the output enable. This pipelined design allows a
pared on chip with the 16 high order processor address bits cache that works as an extension of the internal instruction
to determine if the cache contains the required data or
instruction. This cache hit/miss comparison is then quali-
fied by various built-in protection checks and the result is
pipeline of the CY7C601 Integer Unit thereby maximizing
performance. The write enable is edge-activated and self-
timed thereby eliminating the need for the user to generate
III

output. Pipelined accesses are supported via on-chip regis- accurate write pulses in external logic. A separate asyn-
ters which capture both address and data from the proces- chronous output enable is provided to disable outputs dur-
sor. ing a write or to allow other devices access to the bus.
CY7C608 I-- CY7C609

CY7C601
FLOATING-POINT I - - FLOATING-POINT
INTEGER UNIT
CONTROLLER I-- PROCESSOR
I I
I I
2
CY7C157s CY7C604
CACHE MMU/CACHE
64K CONTROLLER
I
MAIN MEMORY
(DYNAMIC RAM)
0132-1
Full System Block Diagram
Copyright 1989 by Cypress Semiconductor Corporation and Sun Microsystems, Inc.
6-5
PRODUCT DESCRIPTION CY7C601
CYPRESS
SEMICONDUCTOR Very High Performance
32-Bit RISe Processor!
Features Overview
Reduced Instruction Set Large virtual address space The CY7C601 Integer Unit is a high
Computer (RISC) architecture - 32bit virtual address bus speed CMOS implementation ofthe
- Simple format instructions - 8bit address space identifier SPARCTM 32-bit RISC architecture
- Most instructions execute in Hardware Pipeline Interlocks processor. This architecture makes pos-
single cycle sible the creation of a processor which
Multitasking support can execute instructions at rates ap-
Very high performance
- User/supervisor modes proaching one instruction per proces-
- 25 ns instruction cycle with - Privileged instructions
4stage pipeline sor clock. The CY7C601 supports a
- 33 Million Instructions Per Parallel processing support tightly-coupled floating-point coproc-
Second (MIPS) essor and a second implementation-de-
Artificial intelligence support finable coprocessor. The CY7C601
- 27 equivalent VAX MIPS
- 150 ns Interrupt Response High performance coprocessor SPARC processor provides the follow-
interface ing features:
Large windowed register file - Concurrent execution of
- 136 general purpose 32bit Simple Instruction Format-All in-
floatingpoint instructions structions are 32 bits wide and are
registers
- 8 overlapping windows of 24 0.8 micron CMOS technology aligned on 32-bit boundaries in memo-
registers each ry. There are only three basic instruc-
207 pin grid array package
- 4 separate register banks tion formats which feature uniform
Power 3.3 watts maximum placement of opcode and address fields.
Block Diagram Signal Diagram
DESTINATION
.... A(0-31) FP
FHOlD
ASI(o-n
FEXC
SIZE(O_J) FXACK
REGISTER FilE
136 X 32
.... MAO
DCO-31) ...
MDS
..
FCCCO-1)
FCCV
FINSI
MHOiJ)A FINS2
FPSYN
MHOlDB
BHO D
TOE
COE CY7C601
ClK SPARC INST
IRl(0_3) Integer Unit FLUSH
INTACK
i.ill(C
RF'ffi
ERROR
RD
WE
WRT CP
DFETCH CHOlD
lDSTO CEXC
INUll CXACK
_OCK CCCCO-I)
DOE CCCV
Am" CINSI
ADDRESS INSTRUCTION/DATA in' CINS2
0129-2
0129-1
Selection Guide
7C60140 7C601-33 7C601-25
Maximum Operating
Current (rnA) ICC
I Military 500
SPARCTM and SunOS are trademarks of Sun Microsystems, Inc.

VAX is a registered trademark of Digital Equipment Corporation.
Unix@ is a registered trademark of AT&T.
6-6
~ PRODUCT DESCRIPTION CY7C601
~~NDUcrOR =======================================================================
l>verview (Continued) computations generates the same results as if instructions
were executed sequentially.
~egister-Intensive Architecture-Most instructions oper-
lte on either two registers or one register and a constant,
I
Registers
md place the result in a third register. Only load and store
'nstructions access off chip memory. The CY7C601 IU contains a large 136 X 32 triple port
register file which is divided into 8 windows, each with
!\. Large "Windowed" Register File-The processor has twenty-four working registers, and each having access to
l36 on-chip 32-bit registers configured as 8 overlapping the same eight 32-bit global registers. A current window
lets of 24 registers each and 8 global registers. This scheme pointer (CWP) field in the processor state register (PSR)
lllows compilers to cache local values across subroutine keeps track of which window is currently active.
I"calls, and provides a register-based parameter passing
mechanism. The CWP is decremented when the processor executes a
call to a subroutine and is incremented when the processor
Delayed Control Transfer-The processor always fetches returns.
the next instruction after a control transfer, and either exe-
~utes it or annuls it depending on the state of a bit in the Previous Window
r(31)
~ontrol transfer instruction. This feature allows compilers
to rearrange code to place a useful instruction after a de-
layed control transfer and thereby take better advantage of

r(24)
INS
the processor's pipeline. r(:3)

Concurrent Floating Point-Floating point instructions LOCALS

r(16) Active Window
can execute concurrently with each other and with non-
r(31 )
floating point instructions.
Fast Interrupt Response-Interrupt inputs are sampled on
r(! 5)

r(8)
OUTS
r(24)
INS
every clock cycle and can be acknowledged in one to three

cycles. The first instruction of an interrupt service routine r{:3)
can be executed within 6 to 8 cycles of receiving the inter-
rupt request.

r(16)
LOCALS
Next Window
r(15) r(31 )
The 7C600 Family
r(8)
OUTS
r(24)
INS
The SPARC processor family consists of a CY7C601 Inte-

ger Unit (IU) to perform all non-floating point operations r(:3)
and a CY7C608 Floating Point Controller (FPC) which
interfaces to a CY7C608 Floating Point Processor (FPP) to

r(16)
r(15)
LOCALS

perform floating point arithmetic concurrent with the IU.
Support is also provided for a second generic coprocessor OUTS
interface. The IU communicates with external memory via r(S)
a 32-bit address bus and a 32-bit data/instruction bus. In
typical data processing applications, the IU and FPC r(7)
(FPC/FPP) are combined with a high performance : GLOBALS
CY7C604 Memory Management Unit and Cache Control- r{O)
0129-3
ler and a cache memory implemented with CY7C157 16K
x 16 Cache RAMs. In many dedicated controller applica- The registers in each window are divided into ins, outs, and
tions the IU can function by itself with high speed local locals. The eight global registers are shared by all windows
memory. and appear as registers 0-7 in each window. Registers
8-15 serve as outs, registers 16-23 as locals, and 24-31 as
Coprocessor Interface ins. Each window shares its ins and outs with adjacent
The IU is the basic processing engine which executes all of windows. The outs of a previous window are the ins of the
the instruction set except for floating point operations. The current window, and the outs of the current window are
FPC/FPP and IU operate concurrently. The FPC/FPP the ins of the next window. The globals are equally avail-
recognizes floating point instructions and places them in a able to all windows and the locals are unique to each win-
queue while the IU continues to execute non-floating point dow. The windows are joined together in a circular stack
instructions. If the FPC/FPP encounters an instruction where the outs of window 7 are the ins of window O.
which will not fit in its queue, the FPC/FPP holds the IU
until the instruction can be stored. The FPC/FPP contains Multitasking Support
its own set of registers on which it operates. The contents The IU supports a multitasking operating system by pro-
of these registers are transferred to and from external mem- viding user and supervisor modes. Some instructions are
ory under control of the IU via floating point load/store privileged and can only be executed while the processor is
instructions. Processor interlock hardware hides floating in supervisor mode. Changing from user to supervisor
point concurrency from the compiler or assembly language mode requires taking a hardware interrupt or executing a
programmer. A program containing floating point trap instruction.
6-7
~ j
~~~~NDUcrOR ====================================================================~~
Interrupts and Traps 3. Control Transfer-Control transfer instructions include I
jumps, calls, traps and branches. Control transfer is usuall)

The IV supports both asynchronous traps (interrupts) and delayed so that the instruction immediately following the I
synchronous traps (error conditions and trap instructions). control transfer (called the delay instruction) is executed
Traps transfer control to an offset within a table. The base before control is transferred to the target location. The de-
address of the table is specified by a Trap Base Register lay instruction is always fetched, however a bit in the con-
and the offset is a function of the type of trap. Traps are trol transfer instruction can cause the delay instruction to
taken before the current instruction causes any changes be nullified if the branch is not taken. This flexibility in-
visible to the programmer and therefore can be considered creases the likelihood that a useful instruction can be
to occur "between" instructions. placed after a control transfer instruction thereby filling an
otherwise unused hole in the processor's pipeline. Branch
Instruction Set Summary and call instructions use program counter relative displace-
Instructions fall into five basic categories: ments. A jump and link instruction uses a register indirect
displacement: computing its target address as either the
1. Load and Store Instructions--Load and store instruc- sum of two registers, or the sum of a register and a 13-bit
tions are the only instructions which access external mem-
signed immediate value. The branch instruction provides a
ory. They use two IV registers or one IV register and a
displacement of plus or minus 8 megabytes, and the call
signed immediate value to generate the memory address.
instructions 30-bit displacement allows transfer to almost
The instructions destination field specifies either an IV reg-
any address.
ister, a FPC register or a coprocessor register as the desti-
nation for a load or the source for a store. Integer load and 4. Read/Write Control Registers--The processor provides
store instructions support 8, 16, 32, and 64 bit accesses instructions to read and write the contents of the various
while floating point and coprocessor instructions support control registers within the machine. These registers in-
32- and 64-bit accesses. clude the MUltiply Step Register, Processor State Register,
Window Invalid Mask Register, and Trap Base Register.
2. Arithmetic/Logical/Shift-These instructions compute
An instruction is also provided to flush the processor's in-
a result that is a function of two source operands and write
ternal instruction cache.
the result into a destination register or discard it. They
perform arithmetic, tagged arithmetic, logical and shift op- 5. Floating Point and Coprocessor Operations-Floating
erations. An instruction SETHI, useful in creating a 32-bit point operations include floating point calculations and op-
constant in two instructions, writes a 22-bit constant into erations on floating point registers. These operations exe-
the high order bits of a register and zeroes the remaining cute concurrently with both IV instructions and with other
bits. The contents of any register can be shifted left or right floating point instructions whenever possible. Coprocessor
any number of bits in one clock cycle as specified by the operations are instructions which will be executed by an
instruction itself or by another register. The tagged arith- optional coprocessor.
metic instructions are useful in artificial intelligence appli- The Instruction set of the processor is summarized in Table
cations. 1.
Table 1. Instruction Set Summary

Name Operation Cycles
LDSB (LDSBA *) Load Signed Byte (from Alternate Space) 2
LDSH (LDSHA *) Load Signed Halfword (from Alternate Space) 2
LDUB (LDUBA *) Load Unsigned Byte (from Alternate Space) 2
LDUH (LDUHA *) Load Unsigned Halfword (from Alternate Space) 2
LD (LDA*) Load Word (from Alternate Space) 2
LDD(LDDA*) Load Doubleword (from Alternate Space) 3
LDF Load Floating Point 2
LDDF Load Double Floating Point 3
LDFSR Load Floating Point State Register 2
LDC Load Coprocessor 2
LDDC Load Double Coprocessor 3
LDCSR Load Coprocessor State Register 2
STB(STBA*) Store Byte (into Alternate Space) 3
STH(STHA*) Store Halfword (into Alternate Space) 3
ST(STA*) Store Word (into Alternate Space) 3
STD(STDA*) Store Doubleword (into Alternate Space) 4
6-8
~~~NDUcroR =====================================================================
Table 1. Instruction Set Summary (Continued)
STF Store Floating Point 3
STDF Store Double Floating Point 4
STFSR Store Floating Point State Register 3
STDFQ* Store Double Floating Point Queue 4
STC Store Coprocessor 3
STDC Store Double Coprocessor 4
STCSR Store Coprocessor State Register 3
STDCQ* Store Double Coprocessor Queue 4
LDSTUB (LDSTUBA *) Atomic Load/Store Unsigned Byte (in Alternate Space) 4
SWAP (SWAPA *) Swap r Register with Memory (in Alternate Space) 4
ADD (ADDcc) Add (and modify icc) 1
ADDX (ADDXcc) Add with Carry (and modify icc) 1
T ADDcc (TADDccTV) Tagged Add and modify icc (and Trap on overflow) 1
SUB (SUBcc) Subtract (and modify icc) 1
SUBX (SUBXcc) Subtract with Carry (and modify icc) 1
TSUBcc (TSUBccTV) Tagged Subtract and modify icc (and Trap on overflow) 1
MULScc Multiply Step and modify icc 1
AND (ANDcc) And (and modify icc) 1
ANDN (ANDNcc) And Not (and modify icc) 1
OR (ORcc) Inclusive Or (and modify icc) 1
ORN(ORNcc) Inclusive Or Not (and modify icc) 1
XOR(XORcc) Exclusive Or (and modify icc) 1
XNOR (XNORcc) Exclusive Nor (and modify icc) 1
SLL Shift Left Logical 1
SRL Shift Right Logical 1
SRA Shift Right Arithmetic 1
SETHI Set High 22 Bits of r Register 1
SAVE Save caller's window 1
RESTORE Restore caller's window 1
Bicc Branch on integer condition codes 1**
FBicc Branch on floating point condition codes 1**
CBccc Branch on coprocessor condition codes 1**
CALL Call 1**
JMPL Jump and Link 2**
RETT Return from Trap 2**
Ticc Trap on integer condition codes 1 (4 if Taken)
RDY Read Y Register 1
RDPSR Read Processor State Register 1
RDWIM Read Window Invalid Mask 1
RDTBR Read Trap Base Register 1
WRY Write Y Register 1
WRPSR* Write Processor State Register 1
WRWIM* Write Window Invalid Mask 1
WRTBR* Write Trap Base Register 1
UNIMP Unimplemented Instruction 1
IFLUSH Instruction Cache Flush 1
FPop Floating Point Unit Operations 1 to Launch
CPop Coprocessor Operations 1 to Launch
privileged instruction
assuming delay slot is filled with useful instruction
6-9
Table 2. Pin Table
Pin Pin Pin
Pin Name Pin Name Pin Name
Number Number Number
Ao K2 023 117 CINS2 C17
Al Kl 024 H17 CXACK C13
A2 L3 025 H15
IRLo AlO
A3 L1 026 G17
IRL1 Cll
A4 L2 027 H16
IRL2 010
A5 M2 028 G16
IRL3 B12
A6 N2 029 F16 INTACK A13
A7 Ml 030 F15 RESET A9
A8 M3 031 G15 ERROR B15
A9 PI F3
ASlo TOE C15
A10 P2 F2
ASl1 FPSYN C12
All Nl G3
ASh CLK K3
A12 N3 ASI3 G2
A13 R3 Vsso B16 F17 R5
ASI4 Gl
A14 R2 B17 H4 R14
ASIs H2
A15 R4 C3 12 Tl6
ASI6 HI
A16 T4 C4 K14 Tl7
ASI7 11
A17 T5 06 N14 U16
SIZEo E2
A18 R6 014 P4 U17
SIZE 1 02
A19 T6 Fl P6
A20 U5 MEXC 08 F4 Pll
A2l U6 MHOLOA C8 F14 P14
A22 U7 MHOLOB B8
Vcco A15 U
A23 T7 BHOLO A7
A16 M14
A24 U8 AOE P3
A17 N4
A25 T8 OOE N17
01 P8
A26 U9 COE C2
012 P12
A27 R8 MOS B7
017 P16
A28 T9 MAO E3
El P17
A29 R9 1FT C14
G4 R16
A30 TlO RO A4 K4 R17
A3l Ull WE B4 K15
00 RlO LOSTO C5
I NULL B5 VSSI A3 J3 U2
01 Tll A14 L14 UlO
02 U12 LOCK 04
OXFER 03 B2 M4
03 Tl2 B3 P5
04 U13 WRT E4
B9 P7
05 T13 FP C7 Cl Rl
06 Tl4 FCCo All C16 Rll
07 R13 FCC1 Bll 013 Tl
08 U14 FCCV ClO E15 Tl5
09 U15 FHOLO A8 H14 Ul
010 R15 FEXC A5
011 P15 CP B6 VCCI A2 R7
012 N15 CCCo A12 Bl R12
013 M15 CCCI B13 07 T2
014 M16 CCCV BlO E14 T3
015 N16 CHOLO C9 E16 U3
016 L15 CEXC A6 G14 U4
017 M17 H3
INST C6 115
018 L16
FLUSH B14 PlO
019 L17
FINS1 E17
020 K16 VSST 09 114
FINS2 016
021 K17 J4 P9
FXACK 011
022 116
CINS1 015 VCCT 05 P13
6-10

.~~~~~ucr~==========================================================
ABC 0 E F G H J K L MN P R T U
1 0000000000000000
200000000000000000
300000000000000000
400000000000000000
50000 0000
60000 0000
70000 0000
80000 0000
90000 BOTTOM VIEW 0000
100000 0000
110000 0000
120000 0000
130000 0000
1400000000000000000
1500000000000000000
1600000000000000000
1700000000000000000
0129-4
Clock
Package Operating
Frequency Ordering Code
Type Range
(MHz)
40 CY7C601-40GC G208 Commercial
40 CY7C601-4OBC B208
33 CY7C601-33GC G208
33 CY7C601-33BC B208
25 CY7C601-25GC G208
25 CY7C601-25BC B208
25 CY7C601-25GMB G208 Military
6-11
CYPRESS
SEMICONDUCTOR RIse Floating-Point Unit
Features
Combines functions of CY7C608 32 x 32 floating-point register chip floating-point solution for the
floating-point controller and file CY7C601 Integer Unit by integrating
CY7C609 floating-point the CY7C609 Floating-Point Processor
High performance coprocessor
processor in a single package interface (FPP) and CY7C608 Floating-Point
Provides SPARCTM compatible - Concurrent execution of Controller (FPC) into a single device.
floating-point arithmetic and integer and floating-point The CY7C602 provides high perform-
registers instructions ance SPARC compatible single and
- Hardware interlocks double precision floating-point arith-
Very high performance metic. The FPU performs add, sub-
- 30 ns cycle synchronize integer and
floating-point operations tract, multiply, divide, square root,
- Instructions launched in compare, and convert as well as regis-
single cycle Meets IEEE standard 754-1985 ter to register move instructions, float-
- 4.2 million double precision for single and double precision ing-point loads and stores, floating-
Unpack floating-point formats point state register, and floating-point
operations per second 144 pin grid array package queue store instructions. Instructions
3 deep floating-point queue which are unimplemented by the FPU
stores both instructions and Overview (extended precision operations) will
addresses to provide precise cause an Unimplemented FPop trap, in
The CY7C602 Floating-Point Unit which case the instruction will be emu-
exceptions (FPU) is designed to provide a single lated in software.
ADDRESS DATA
FP
t ! F"PP Results
fCC(O_I)
fCCV
fHOLD
fEXC
TEST floating-Point 64-blt

Data Pipe lined
INST Register file floating-Point
fLUSH 32 X 32 Processor
fXACK CY7C602.
fiNS 1 floating-Point
Unit
flNS 2
MHOLDA
MDS
BHOLD
DOE fPP fP Control
~ Instructlon/Controll-------------~
TOE Unit
fNULL 0159-1
~
TTTT
CHOLD CCCV CLK RESET
0159-2
Selection Guide
7C602-33 7C602-25
Maximum Operating
Commercial TBO TBO
Current (rnA) I
SPARCTM is a trademark of Sun Microsystems. Inc.
6-12
CYPRESS
SEMICONDUCTOR Cache Controller and Memory
Management Unit (CMU)
Features Introduction
Fully conforms to the SPARCTM Sparse address space support The CY7C604 comprises a Cache Tag
reference Memory Management with 3-level map and a Memory Management Unit
Unit (MMU) architecture 2048 direct mapped cache tag (CMU). It is a high speed CMOS im-
entries plementation of the SPARC reference
Supports 4096 contexts
Memory Management architecture,
Fixed 4K-byte page size Write through and copy-back Cache Tag, and Cache Controller. The
On-chip translation lookaside cache policies CY7C604 directly connects to the
buffer (TLB) - 1 32-byte read line buffer CY7C601 processor and CY7C157
- 64 fully associative entries - 1 32-byte write line buffer cache data RAM without any external
- Multi level flush and probe 32 byte cache line size circuitry.
support The CMU, when combined with two
Aliasing detection
- Lockable entries CY7C157 16K x 16 cache RAMs,
- Random replacement Byte write generation forms a complete 64K-byte direct
algorithm Scalable cache architecture mapped cache. Cache size can be
Page level protection - Cascadeable scaled. The CMU translates 32-bit vir-
tual addresses from the processor into
Large address space support 0.8 micron CMOS technology
36-bit physical addresses. The on-chip
- 32-bit virtual address 244 pin grid array package and context register allows support of
- 36-bit physical address 196 plastic quad flatpack
Hardware table walk SPARCTM is a trademark of Sun Microsystems, Inc.
Signal Diagram
ClK
RESET
tAAO(0_63)
tAAS
.
--"
CSEl tAERR
A(0-31) tAROY
l...L
ASI(0-5) tARTY
0(0-31)
SIZE(O_l) --"
CY7C604
RO Cache Controller and tABR
tAemory tAanagement Unit
WE tABG
lOSTO tABB
INUll CBWE(0_3)
FNUll ..
.. CaE
tAHOlO
tAOS CtAER
tAEXC TOE
IOE
0157-1
Selection Guide
7C60440 7C60433 7C60425
I
Maximum Operating
Current (mA)
I Military 650 600
6-13
~ PRODUCT DESCRIPTION CY7C60 '
~~~NDUCTOR ====================================================================.
Introduction (Continued) translation on the virtual address and store the new map-
ping into a TLB entry selected by a random replacement
up to 4096 contexts. High speed address translation is pro- algorithm.
vided by a 64-entry fully associative Translation Lookaside
Buffer (TLB). If the CMU processes a virtual address that TLB Entry Contents
matches one of the TLB entries, the physical address con- Each entry in the TLB contains a 20-bit Virtual Address
tained in that entry will be delivered to the outputs of the Tag, a 12-bit context field (CXT 11-0), two shorted trans-
CMU. If the virtual address from the processor has no lation indicator bits (STl, STO), a 24-bit Physical Page
corresponding entry in the TLB, the CMU will perform Number (PPN), a cacheable bit (C), a Modified bit (M),
address translation for the virtual address using a three-lev- three access permission bits (ACC 2-0) and a Valid bit
el page table map. (V).
The CMU supports lockable TLB entries and a random During a TLB look-up, the upper 20 bits of the virtual
replacement algorithm. Each matched TLB entry is address and the context number of the access are compared
checked for protection and privilege violations. If viola- with the virtual address and context number fields of each
tions occur, these are reported to the 7C601 Integer Unit as entry based on the short translation bits in each entry. The
memory exceptions. Each page can be declared as either short translation bits are included in order to provide a
cacheable or non-cacheable by using the cacheable "c" bit. linear address mapping facility of 256K, 16M, or 4G bytes
The CMU provides 2048 direct mapped cache tag entries. with a single TLB entry.
The cache tag entries and the TLB are searched concur- The 24-bit Physical Page Number field contains the higher
rently for a match with the virtual address. Both write- order bits of the physical address. This field, when concate-
through and copy-back cache policies are supported with a nated with the 12-bit byte offset from the virtual address,
32-byte line size. Address aliasing is checked each time a forms a complete 36-bit physical address.
cache tag entry is replaced. If the new virtual address is
mapped to the cache line selected for replacement, the The Modified (M) bit of an entry is set whenever the page
CMU will ignore the main memory access and modify the has been modified. During page replacement, the operating
cache tag accordingly. system uses this bit to determine whether the selected page
must be copied to secondary storage or not.
The CMU provides on-chip buffer to enhance data trans-
fers between cache memory and main memory: a 32-byte The Cacheable (C) bit determines whether an access associ-
read buffer and a set of write buffers. In copy-back mode, ated with that page is cacheable or not. The state of the C
the 32-byte write buffer is used to store the modified cache bit in a matched entry is available on the Mbus during the
line being replaced in the cache, allowing the main memory address phase of a transaction. If the cacheable bit is set
read to proceed as soon as the memory bus is acquired. The high, then the entry is cacheable. If this bit is cleared, the
read buffer stores data from main memory temporarily be- data accessed by the IU will not be written into the cache.
fore it is written into the cache memory. The write buffers The three Access Permission (ACC 2-0) bits indicate
are used in the write through mode to capture address and whether access to the page is allowed for the current trans-
data from the IU during write accesses, and allow the IU action. The Address Space Identifier (ASI) from the IU
to continue processing while the buffer contents are trans- specifies whether a given access is a data or instruction
ferred into main memory over the memory bus. reference, and whether it is performed in the supervisor or
The memory bus implements the 64-bit Mbus SPARC ref- user space. Read and write information is derived from the
erence specification. Architecturally, up to 16 CMUs can RD and WE inputs.
be used in the same system to expand the cache tag, cache Multiple Contexts
size and TLB storage. The CMU is fabricated with Cy-
press' 0.8 micron CMOS drawn process and is available in 4096 contexts are supported in the CMU via a 12-bit field
a 196-pin plastic quad flatpack and a 244-pin ceramic in the Context Register (CXR). The context is used by
PGA. both the cache tag and the TLB. For supervisor accesses,
if the "S" bit is set the context number comparison is
Memory Management Unit ignored.
Translation Look-aside Buffer Fault Reporting
The TLB contains 64 fully associative entries. All entries The CMU detects and reports the following faults:
are searched simultaneously when a virtual address is pre- Instruction access error
sented to the CMU. The virtual tag and the context field Data access error
from each entry are compared with the virtual address bits Translation access error
from the processor and the current context in the Context Bus error
Register (CXR), respectively. If a match is found in one of Privilege Violation
the entries, the physical address field of that entry will be Protection Violation
passed to the Physical Address outputs of the CMU. If no
match is found, the CMU will perform dynamic address
VAT CXT(lI-O) PPN C M ACC(2-0) ST(I-O) V

Figure 1. TLB Entry Format
6-14
,~ PRODUCT DESCRIPTION CY7C604
~~~NDUcrOR =====================================================================
Memory Management Unit (Continued) Write Buffer
The write buffers are used in the copy back mode to pro-
Linear Address Mapping vide temporary storage for the dirty cache line being re-
The 7C604 CMU provides the ability to translate a contig- placed while the new line is being transferred from main
uous virtual address space to a contiguous physical address memory. Buffering the dirty line speeds up cache miss pro-
space of equal size with a single TLB entry. This function cessing because the IU can be released as soon as the cache
is achieved by placing a page table entry (Entry Type = 2) RAMs are updated. The line buffer contents are written
in a location normally occupied by a page pointer (Entry back to main memory only when free memory bus cycles
Type = 1) such as the context table, the first level page become available. When the line buffer is full, the cache
table, or the second level page table. By replacing a page controller will wait for it to empty before processing the
pointer with a page entry, the table walk process stops as cache miss. The same write buffers are used in the write-
soon as the page table entry is encountered. Depending on through mode to store four double store data. The proces-
I where the PTE is placed, 4 mapping sizes are available: sor is allowed to continue without waiting for the main
memory update to complete. The buffer contents are writ-
PTE Location Linear Map Size ten back to main memory whenever the memory bus be-
Third Level Page Table 4Kb comes available.
Second Level Page Table 256Kb Read Buffer
First Level Page Table 16Mb
Context Table 4Gb The read buffer is 32 bytes. It is used to hold data being
retrieved from main memory. Since memory bus access be-
Flush and Probe Operations gins as soon as a miss is detected, it is likely that the cache
memory will still be busy when the first data from memory
Flushing causes the invalidation of TLB entries while prob- is returned. The read line buffer stores the information
ing returns the physical translation of virtual addresses temporarily until the cache RAM is ready to be updated.
generated by the IU. A flush is accomplished by writing to
an alternate address space recognized by the CMU. Flush- Cache Miss Processing
ing can be performed on the entire TLB, on matching any If the physical translation of the missed address is available
index level in the TLB, or on any context within the TLB. in the TLB, then miss processing will commence. Other-
A probe is accomplished by reading from the same alter- wise, the cache controller will wait for the memory man-
nate address space. Both flush and probe operation are agement section to retrieve the physical address from the
word accesses. page tables before starting its actions. The first step in miss
processing is the acquisition ofthe virtual bus by tri-stating
Cache TAG and Controller the IU outputs. Once the control of the virtual bus is
Cache Operations achieved, the cache controller is ready to process the cache
miss. If the cacheable (C) bit is set, the cache controller
The CMU supports both write-through with no write allo- will transfer data from main memory according to the pro-
cate and copy-back with write allocate modes. Two types grammed cache policy and update the cache. If the C bit is
of buffers: write buffer and read buffer are provided on- cleared, the cache controller simply transfers data between
chip to enhance cache operations. In write-through mode, the IU and main memory without updating the cache.
the write buffer is used to store four double store data. In
copy-back mode, the same write buffer is used to hold the Non-Cacheable Accesses
dirty line from cache memory when a line is replaced. A During a write operation the IU data will be written into
32-byte read buffer is provided to load data from main main memory over the Mbus. During a read operation the
memory. requested data will be read from main memory and pre-
Address Synonyms or Aliasing Detection sented to the IU via the virtual data bus. The cache tag is
not updated.
Virtual addressing allows multiple virtual addresses to map
into the same physical address. Any modification to a vir- Cacheable Accesses
tuallocation may cause data inconsistency in the cache Two cache policies are supported in the CMU. They are
because the change is not reflected in other cache locations write-through with no write allocate and copy-back with
mapped to the same physical address. Address aliasing is write allocate.
checked by the CMU whenever a cache line is replaced in
the copy back mode and during read misses in the write Write-Through with No Write Allocate
through mode. The physical address of the displaced line is In this mode, all write hits must update both the cache and
obtained by passing the virtual tag through the memory main memory. In a write miss, only the main memory is
management unit. An alias is detected if the new and the updated. No address alias checking is performed for write
displaced virtual addresses are mapped to the same physi- accesses. Protection against aliasing is achieved by invali-
cal location. If the miss was caused by a read, no cache dating the selected cache line when a write miss is detected.
updating is required because the existing line will already Upon write misses, the physical translation of the missed
contain the correct data. In this case the tag is simply up- address and the IU data are placed on the physical bus and
dated to reflect the new address. If the miss was caused by a write cycle is initiated. If the miss was caused by a read,
a write, the location addressed by the IU will be modified an alias check is performed. A new line will be loaded from
and the tag is updated to reflect the new address. main memory if no alias is detected. The physical address
6-15
Q,~ PRODUCT DESCRIPTION CY7~
Cache TAG and Controller (Continued)
of the first word in the new cache line is placed on the initiated. Each 64-bit word returning from main memory is
Mbus and a burst read cycle is init.iated. Each 64-bit word stored in the read line buffer and driven onto the virtual
returning from main memory is temporarily stored in the data lines 32 bits at a time. Cache update is activated by
read line buffer while the cache RAM is updated 32 bits at asserting the CWE3-CWEo outputs. When the last word
a time. After the last word in the line has been stored in the in the cache line is received, the cache controller will up-
cache, the cache controller will drive the missed address on date the cache tag with the dirty bit cleared if the miss was
the virtual address lines and initiate a read. Data returning a read or update the cache tag with the dirty bit set if the
from the cache is strobed into the IV via MDS. miss was a write.
Copy Back with Write Allocate Cache Tag
In this mode, a write hit only modifies the data in the The CMV provides 2048 entries of cache tag and status
cache. Main memory is updated when a cache line is re- information. Tag selection is controlled by the 11 address
placed. A write miss will cause the loading of a new line lines (As-A1S), from the IU. Each entry contains a 12-bit
from main memory into the cache RAMs. If the tag is context field, a 16-bit cache tag field, and a 3-bit status
valid, the cache controller will check for aliasing between field. The status field includes the valid (V) bit, the dirty
the cache line to be replaced and the missed address by (D) bit, and a supervisor (S) bit.
comparing the physical translations of both virtual ad- The valid bit specifies the validity of the tag entry and the
dresses. The virtual address of the displaced line is ob- dirty bit indicates whether the cache line has been modified
tained by reading the cache tag. If the selected tag entry is or not. The supervisor bit indicates that the tag entry can
invalid, no alias checking is necessary. An alias is signaled only be accessed by the supervisor.
if both physical addresses match.
If a copy back cache policy is selected, the dirty bit in the
Alias Detected tag is used by the cache controller to determine whether a
When an alias is detected, no loading from main memory is cache line should be copied back to main memory when it
necessary because the cache line selected for replacement is is replaced.
mapped to the missed address. If the miss was caused by a Main Memory Interface
read access, data originally requested by the IV is retrieved
from the cache by placing the missed address on the virtual The CMU supports a 64bit synchronous interface with
bus. Information returning on D31 - Do is strobed into the multiplexed address and df~ta for main memory access. The
IU in the following clock by the assertion of the MDS main memory interface has 36 bits of address and 64 bits of
signal. The cache tag is updated to reflect the new address data. The interface is capable of bursting information to
assignment. If the old cache line was dirty, the tag will be support fast cache line fills.
updated with the dirty bit set, otherwise the tag will be
Byte Write Generation
updated with the dirty bit cleared. If the miss was caused
by a write, the cache location originally addressed by the The CY7C601 processor is capable of accessing bytes, half-
processor will be updated with the IU data. After the write words and words. The CMU decodes the size and access
is completed, the cache is updated with the dirty bit set. direction information from the IU and generates the neces-
sary cache write enable signals.
Alias Not Detected
Multiple CMU Support
If the two virtual addresses are not mapped to the same
physical location, the state of the dirty bit in the tag entry Up to 16 CMUs can be used in a system to increase the
selected for replacement will determine whether the cache number of tags, TLB entries, and cache size. CMU config-
line should be copied back to main memory. Contents of uration information is contained in the MMU Control
the line buffer are loaded back to main memory using the Register (MCR). Multi-chip address (MCA) field is a 4-bit
burst write feature of the memory bus after the cache miss address that identifies a particular CMU. The Multi-chip
has been processed. Mask (MCM) field is a 4-bit code specifying the number of
CMUs in the system. Five configurations: 1,2,4,8, and 16
Loading the New Cache Line CMUs are supported. In order to initialize system configu-
The physical address of the first word in the new line is ration, the chip select input of each CMU must be connect
placed on the physical bus and a burst read cycle is ed to a different address line from the IU.
6-16
CYPRESS
SEMICONDUCTOR Multiprocessor Cache
Controller and Memory
Management Unit (CMU-MP)
Features Introduction
Fully compatible with SPARCTM Scaleable cache architecture The CY7C605 Multiprocessor Cache
reference Memory Management - Cascadeable: 1-16 Controller and Memory Management
Unit (MMU) architecture Unit (CMU-MP) is a high speed
Page level protection
Multiprocessor support CMOS implementation ofthe SPARC
Sparse address space support reference Memory Management archi-
- Direct data intervention with with 3-level map
and without reflectivity tecture. The CY7C605 directly con-
- Dual cache tag architecture Supports write through and nects to the CY7C601 processor and
copy-back cache policies CY7C157 cache data RAM without
Superset of CY7C604 CMU - 1 32-byte read line buffer any external circuitry to form a com-
Direct mapped cache tag entries - 1 32-byte write line buffer plete memory management and cache
- 2048 virtual tags subsystem.
- 2048 physical tags
Aliasing detection
Fixed 4K-byte page size
Multiple CY7C601, CY7C605 and
CY7C157 subsystems can be used to-
6
Automatic miss processing via
hardware table walking 32 byte cache line size gether to achieve higher performance.
The CY7C605 supports a direct data
On-chip 64 entry translation 0.8 micron CMOS technology
intervention protocol with and without
lookaside buffer (TLB) 244 pin grid array package reflectivity via the SPARC reference
Supports 4096 contexts standard 64-bit Mbus.
Signal Diagram
ClK MAO(0_63)
RESET .. MAS
CSEl .. MERR
AO- 31 MROY
ASI(0_5) .. MRTY
0(0-31) MSH
SIZE(O-1) .. MIH
... CY7C605
RO MBR
WE ... MBG
lOSTO .. MBB
INUll CBWE(0_3)
FNUll COE
MHOlO
MOS CMER
MEXC TOE
IOE
0156-1
Selection Guide
7C605-40 7C605-33 7C605-25
Maximum Operating
Current (rnA)
1 Military 650 600
6-17
PRODUCT DESCRIPTION CY7C608~
CYPRESS
SEMICONDUCTOR RISC Floating-Point Controller
Features
Provides interface between the High performance coprocessor (FPP) to the CY7C601 Integer Unit
CY7C601 Integer Unit and interface (IV). Together, the FPC and FPP pro-
CY7C609 Floating-Point Unit - Concurrent execution of vide high performance SPARC com-
Provides SPARCTM compatible Integer and Floating-Point patible single an,d double precision
Floating-Point Arithmetic and Instructions floating-point arithmetic. The FPP per-
registers - Hardware Interlocks forms add, subtract, multiply, divide,
synchronize Integer and square root, compare, and convert;
Very high performance Floating-Point Operations while the CY7C608 FPC performs reg-
- 30 ns cycle ister to register move instructions,
- Instructions launched in 1.2 micron CMOS technology
floating-point loads and stores, float-
single cycle 299 pin grid array package ing-point state register, and floating-
- 4.2 million double precision point queue store instructions. Instruc-
linpack Floating-Point Power 3.3 watts maximum
tions which are unimplemented by the
operations per second FPC (extended precision operations)
Overview
32 x 32 Floating-Point Register will cause an Unimplemented FPop
File The CY7C608 Floating-Point Control- trap, in which case the instruction will
ler (FPC) is designed to interface the be emulated in software.
3 deep floathig-point queue CY7C609 Floating-Point Processor
stores both instructions and
addresses to provide precise SPARCTM is a trademark of Sun Microsystems, Inc.
exceptions

, . . . . . - - - - FPP Status 0(0-31)
ADDRESS DATA
F'P
t ! TDA(0-31)
FPP Results FCC(O_I) TDB(0-311
FCCV TENR
FHOLD TINST(O_Sl
FEXC TSELOP(A_B)
TFAST
CHAIN TROUND(O_1)
Flootlng-Polnt
Data TSELt.4S
INST
Register File TSRCCt.4
FLUSH
32 X 32
FXACK CY7C608 THALT
FINS 1 Flootlng-Polnt TCCLK
Controller TCONFIG
FINS2
TRESET
TOUT
t.4HOLDB
t.4HOLDA CSTAT(0_2)
t.4DS OSTAT(O_S)
' - - - - - . FPP Operands
r--:=---l-------+ FPP Instruction BHOLD
1-------. FPP Control DOE

TOE
TY(0-31)
TE
0131-1 T47
FNULL
TIPRES
f f f f
CHOLD CCCV CLK RESET
0131-2
Selection Guide
7C608-33 7C608-25
Maximum Operating Current (rnA) Commercial 600 550
6-18
II~RFSS PRODUCT DESCRIPTION CY7C608
I WnrcoNDucrOR =====================================
Table 1. Floating-Point Instruction Set Summary
LDF Load Floating-Point Register 2
LDDF Load Double Floating-Point Register 3
LDFSR Load Floating-Point State Register 2
STF Store Floating-Point 3
STDF Store Double Floating-Point 4
STFSR Store Floating-Point State Register 3
STDFQ* Store Double Floating-Point Queue 4
FiTOs Convert Integer to Single Precision 8
FiTOd Convert Integer to Double Precision 8
FiTOx Convert Integer to Extended Precision #
FsTOi Convert Single Precision to Integer 8
FdTOi Convert Double Precision to Integer 8
FxTOi Convert Extended Precision to Integer #
FsTOd Convert Single Precision to Double Precision 8
FsTOx Convert Single Precision to Extended Precision #
FdTOs Convert Double Precision to Single Precision 8
FdTOx Convert Double Precision to Extended Precision #
FxTOs Convert Extended Precision to Single Precision #
FxTOd Convert Extended Precision to Double Precision #
FMOVs Move Single Precision 8
FNEGs Negate Single Precision 8
FABSs Absolute Value Single Precision 8
FSQRTs Square Root Single Precision 15
FSQRTd Square Root Double Precision 22
FSQRTx Square Root Extended Precision #
FADDs Add Single Precision 8
FADDd Add Double Precision 8
FADDx Add Extended Precision #
FSUBs Subtract Single Precision 8
FSUBd Subtract Double Precision 8
FSUBx Subtract Extended Precision #
FMULs Multiply Single Precision 8
FMULd Multiply Double Precision 9
FMULx Multiply Extended Precision #
FDIVs Divide Single Precision 13
FDIVd Divide Double Precision 18
FDIVx Divide Extended Precision #
FCMPs Compare Single Precision 8
FCMPd Compare Double Precision 8
FCMPx Compare Extended Precision #
FCMPEs Compare Single Precision with Exception if Unordered 8
FCMPEd Compare Double Precision with Exception if Unordered 8
FCMPEx Compare Extended Precision with Exception if Unordered #
privileged instruction
# currently supported via software emulation only
6-19
~ PRODUCT DESCRIPTION CY7C60SI '11
~~~NDUcrOR =====================================================================
Address Bus
.III ~
Data Bus
t Vee
~----l---~ ,~------------------------- -,
0(0-31) A(0-31)
FP
.: . :~ :~
1
1
FP
0(0-31) A(2-31)
TOA(0-31) OA(0-31)
1
FCC(O_I) FCC(O_I) TOB(0-31) OB(O-31)
FCCV
! FCCV TENR ENR(A_B)
1
FHOlO FHOlO
FEXC
: FEXC
TINST(0_8)
TSElOP(A_B)
1(0-3),1(5-9)
SElOP3, 7, 1,5
1
TFAST FAST
Vee .
y
1
I
1 ~
TROUNO(O_l) RNO(O_I)
1 TSElMS SElMS,lS
INST -'---'- INST TSRCCM SRCC
1
FLUSH FLUSH THAlT HALT
I
FXACK FXACK TCClK ClKC
1
FINS 1 FINS 1 TCONFIG CONFIG(O_I)
FINS 2
; FINS 2 TRESET RESET
1
1
CY7C601 1 CY7C608 CY7C609
IU 1 FPC FPP
1
MHOlOA, B MHOlOA,B CSTAT(0_2) UNORO, AGTB, AEQB
MOS
1-"" OENORM,OIVBYO,INEX
1 MOS OSTAT(0_8)
IVAl, OVER, STEXO, STEX 1
BHOlD BHOlD
1 UNDER,OENIN
DOE I DOE
TY(O-31) Y(0-31)
TOE TOE Vec
A--
TE
.,- FNUll
T47
Vee
l SElOP 0, 2, 4, 6
TEST (0-1)' SElST(O_I)
t E- 14,110
OEC, OES, OEY
CCCV +-- PA(O-3)
CHOlD +- NO FPP
PB(O-3)
INUll ~ TIPRES +-0 PIPES(O-2)
.1.
-
FPP ENRC
FlOWC
ClK RESET CHOlO CCCV ClK RESET
~ ~ ~
- ClK
FLOATING-POINT UNIT (FPU)

Clk --- -- -- t- - .
------------------ ------
Reset
CCCV
Vee
vee
.... y
CHOlO } COPROCESSOR
MHOlOA,B
MDS
BHOlD
DOE SYSTEM
TOE
I
......
y
I
NUll
..L
0131-3
Figure 1. Floating-Point Controller System Connections
6-20
~~~~UcrOR==============================================================
Table 2. Pin Table
Pin Pin Pin Pin Pin Pin
Name Number Name Number Name Number
A2 X13 D27 DlO TIN D18
A3 XI4 D28 ClO TIPRES X6
A4 XI5 D29 C9 TOVT D19
A5 WI5 D30 D9 TRESET TlO
A6 XI6 D31 C8 TROVNDo E9
A7 WI6 MHOLDA J17 TROVNDI E8
A8 VI6 MHOLDB J18 TSELMS ElO
A9 WI7 BHOLD H18 TSELOPA N5
AlO VI6 DOE E19 TSELOPB N4
All VI7 MDS N18 TSRCCM Ell
Al2 WI8 FNVLL L16 TYo BI8
Al3 RI7 RESET G20 TYI BI7
Al4 VI8 CLK VlO
P16 TY2 A17
Al5
FP F20 TY3 BI6
Al6 TI7
FCCo L17 TY4 A16

Al7 PI7
FCCI L18 TY5 AI5
Al8 VI9
FCCV M17 TY6 A14
Al9 TI8
FHOLD N16 TY7 B13
A20 V20
TI9 FEXC MI6 TY8 B12
A21
INST NI7 TY9 B11
A22 RI8
FLVSH MI8 TYlO BlO
A23 T20
FINSI GI9 TYII B9
A24 RI9
FINS2 HI9 TYl2 A8
A25 PI8
FXACK L19 TY13 B8
A26 R20
TYl4 A7
A27 PI9 CCCV FI9
TYl5 D8
A28 P20 CHOLD KI8
TYl6 B7
A29 NI9 CHAIN X5
TYl7 C7
A30 N20 TOE E20
TYl8 A6
A31 MI9 CSTATo RI TYl9 D7
CSTATI VI TY20 B6
Do HI7 CSTAT2 TI TY21 C6
DI G18 OSTATo D2 TY22 A5
D2 HI6 OSTATI E2 TY23 B5
D3 GI7 OSTAT2 FI TY24 C5
D4 FI8 OSTAT3 D3 TY25 B4
D5 EI8 OSTAT4 El TY26 D5
D6 GI6 OSTAT5 Gl TY27 D6
D7 E17 OSTAT6 HI TY28 C4
D8 FI7 OSTAT7 G2 TY29 E4
D9 FI6 OSTAT8 F2 TY30 C2
DIO DI5
TINSTo E7 TY31 E3
Dll EI4
Dl2 CI7 TINSTI E6 TDAo V5
D13 DI4 TINST2 F4 TDAI W4
DI6 TINST3 G5 TDA2 V7
Dl4
Dl5 CI6 TINST4 F3 TDA3 V5
CI5 TINST5 G3 TDA4 T7
Dl6
BI5 TINST6 H3 TDA5 V4
Dl7
E13 TINST7 H5 TDA6 V6
Dl8
CI4 TINST8 H4 TDA7 R4
Dl9
D20 DB T47 X7 TDA8 V3
D21 BI4 TCCLK T4 TDA9 V2
D22 DI2 TCONFIG R5 TDAlO T3
D23 C13 TE D20 TDAll T2
D24 CI2 TENR P5 TDAl2 R3
D25 CII TFAST H2 TDAl3 P4
D26 Dll THALT TIl TDAl4 R2
~~~~UaDR============================================================
Table 2. Pin Table (Continued)
Pin Pin Pin Pin Pin Pin
Name Number Name Number Name Number
TDA15 P3 TDB9 Ul2 Vss J1 NI Xl
TDA16 M5 TDBlO Vl2 J16 PI XII
TDA17 P2 TDBl1 V13 Kl6 T12 Xl7
TDA18 M4 TDB12 VII K20 VI Xl9
TDA19 N3 TDB13 W13 LI V2 X3
TDA20 M3 TDB14 UII M20 W20 X9
TDA21 L3 TDB15 Wl2
N2 Vee All DI Xl2
TDA22 TD B16 Wll
L5 A13 120 Xl8
TDA23 TDB17 WlO
M2 Al8 KI X2
TDA24 TDB18 VlO
L4 A20 L20 X20
TDA25 TDB19 W9
K5 A3 MI X4
TDA26 TDB20 V9
A9 V20 X8
TDA27 12 TDB21 W8
K3 BI WI
TDA28 TDB22 U9
J3 C20 XlO
TDA29 TDB23 T9
TDA30 J4 TDB24 V8 NO Bl9 F5 T6
TDA 31 J5 TDB25 U8 CONNECT B2 04 Ul7
TDBo T15 T DB26 W7 B3 J19 U4
TDBI Ul5 TDB27 T8 Cl8 Kl7 Vl8
TDB2 T14 TDB28 V7 Cl9 Kl9 Vl9
TDB3 Vl5 TDB29 W6 C3 K2 V3
TDB4 Ul4 T DB 30 V6 Dl7 K4 Wl9
TDB5 T13 TDB31 W5 D4 L2 W2
TDB6 Ul3 Vss AlO A2 CI El5 Rl6 W3
T DB7 Vl4 Al2 A4 El2 El6 Tl6
TDB8 Wl4 Al9 B20 H2O E5 T5
ABC 0 E F G H J K L MN P R T U VWx
@@@@@@@@@@@@@@@@@@@ 1
@@@@@@@@@@@@@@@@@@@@ 2
@@@@@@@@@@@@@@@@@@@@ 3
@@@@@@@@@@@@@@@@@@@@ 4
@@@@@@@@@@@@@@@@@@@@ 5
@@@@@ @@@@@ 6
@@@@@ @@@@@ 7
@@@@@ @@@@@ 8
@@@@@ @@@@@ 9
@@@@@ BOTTOM @@@@@ 10
@@@@@ VIEW @@@@@ 11
@@@@@ @@@@@ 12
@@@@@ @@@@@ 13
@@@@@ @@@@@ 14
@@@@@ @@@@@ 15
@@@@@@@@@@@@@@@@@@@@ 16
@@@@@@@@@@@@@@@@@@@@ 17
@@@@@@@@@@@@@@@@@@@@ 18
@@@@@@@@@@@@@@@@@@@@ 19
@@@@@@@@@@@@@@@@@@@@ W
0131-4
Oock Frequency
Ordering Code Package Type Operating Range
(MHz)
33 CY7C608-330C 0300 Commercial
25 CY7C608-250C 0300 Commercial
6-22
CYPRESS
SEMICONDUCTOR RIse Floating-Point Processor
Features Overview
Provides high performance 64-bit High performance coprocessor The CY7C609 is a high-speed double
floating-point arithmetic for interface precision Floating-Point Processor
CY7C601 RISC integer unit - Concurrent execution of (FPP) which when used in conjunction
Provides SPARCTM compatible integer and floating-point with the CY7C608 Floating-Point
floating-point arithmetic instructions Controller (FPC) provides high per-
- Hardware interlocks formance SPARC compatible single
Very high performance synchronize integer and and double precision floating-point
- Fully pipelined floating-point operations arithmetic. The FPP performs add,
- 30 ns cycle subtract, multiply, divide, square root,
- Instructions launched in Meets IEEE standard 754-1985
for single and double precision compare, and convert; while the
single cycle CY7C608 FPC performs register to
- 4.2 million double precision formats
register move instructions, floating-
linpack floating-point 1 micron CMOS technology point loads and stores, floating-point
operations per second 208 pin grid array package state register, and floating-point queue
store instructions.

ClK
ClKC
ClKMODE PIPES(0_2)
BYTEP
CONFlG(O_1) PA(0-3)
FAST PB(O-3)
RND(0_1) PY(0-3)
SRCC
ENRC PERRA
FlOWC PERRB
SElOP(0_7) MSERR
SElST(O_1)
SElMS/lS UNORD
AGTB
REGISTER REGISTER TEST(O_1) AEaB
ED
ADDER/
ROUNDER NORMALIZER DIVBYO
1(0-10) IVAl
REGISTER REGISTER INEX
OVER
ENRA
UNDER
ENRB
64 64 DENORM
OES
DEN IN
OEC
RNDCO
OEY
SRCEX
CHEX
0158-1 STEX(0_1)
DA(0_31)
NEG
INF
DB(0_31) Y(0-31)
0158-2
Selection Guide
7C60933 7C609-25
Maximum Operating Current (mA) Commercial 600 550
6-23
PRODUCT
INFORMATION
STATIC RAMS
..,.
PROMS
EPLDS
fA.
LOGIC

RISC

.:5ii! "111;r MODULES

ECL
MILITARY
,.
BRIDGEMOS
QUICKPRO

'II
PLDTOOLKIT 'ta
QUALITY AND
RELIABILITY
APPLICATION BRIEFS "I
PACKAGES
~~ ===============~S~e~c~t~i~o~n~C~o~n~t~e~n~t~s~===============
~odules
:ustom Module Capabilities .................................................................. Page Number
, ........... 7-1
CYPRESS
SEMICONDUCTOR
Custom Module Capabilities

Cypress' Multichip Products group is a leading supplier of Routing Efficiency. Due to compact module size, more
custom memory and/or logic modules. This turnkey capa- efficient routing techniques can be used. These include
bility provides Cypress customers with a fast, low-risk so- tighter line spacing, blind and buried vias, and selective
lution for designs requiring the ultimate in system perform- manual routing.
ance and density. Detailed information on our standard Pin Reduction. The reduced number of device pins
modules can be found in the Static RAM section of this which results from the use of modules allows the memo-
book (Section 2). ry system itself to be routed more efficiently.
Ceramic Substrates. Ceramic is the highest density in-
Custom Capabilities terconnect medium for surface mount packages. Thus,
Cypress' Multichip Products Division is currently support-

modules provide large density improvements, while sat-
ing custom modules with the following technical require- isfying hermeticity requirements if desired .
ments:
Module usage also improves memory system performance.
Substrate Type: Ceramic, Epoxy Laminate These performance advantages include the following:
Compo Packaging: LCC, SOl, SOIC, PLCC Interconnect capacitance is reduced by approximately
Pin Configuration: DIP, VDIP(DSIP), ZIP, SIP, 50%.
QUIP, PGA Crosstalk Characteristics are substantially improved.
Data Word Width: Up to 72 Bits Number of pins is minimized.
Pin Count: Up to 200 Pins Ceramic may be used to improve thermal characteris-
Access Time: 12 ns and up tics.
As 1989 progresses, we will be introducing new technolo-
gies which will extend each of these capabilities. Custom Module Flow
Multichip modules are typically SRAM based. However, Multichip's focus is on providing turnkey memory mod-
other types of components can be used in addition to or ules. Figure 1 illustrates the tasks performed during the
instead of SRAMs-Logic, PLDs, EPROM, Gate Arrays, development of the module.
Microprocessors, etc. Module development commences with the generation of a
detailed Objective Specification. The module is designed to
Advantages of Custom Modules this specification, and once in production it will be guaran-
teed to perform as indicated in the Objective Spec.
Custom modules provide the memory system designer with
the ultimate in flexibility and performance. For example, Components are selected while the specification is being
using a custom module it is very straightforward to imple- generated. In many cases, the spec is designed such that
ment unusual memory word widths-a capability that be- multiple sources of components can be utilized. Once the
comes critical in high speed applications such as digital spec is complete and the components are selected, a sche-
signal processing and RISC-based systems. matic for the module is generated. The netlist from the
schematic is used to drive the circuit simulator.
Custom modules are built using fully tested components,
and are rigorously tested before they are shipped. This test- During simulation; several types of analysis are performed.
ing redundancy saves time and effort during system testing A functional simulation is used to ensure that the module's
and provides an added degree of reliability. logic is designed properly. Timing simulation is run to veri-
fy that the module will function when subject to the worst
case timing delays of the components. Finally, thermal
Performance and Density Improvements analysis may be performed to determine the thermal char-
Using modules, far greater memory densities can be acteristic of the module.
achieved than even the most advanced surface mount tech-
nologies. This density can be attained for several reasons:
Orientation. Modules substrates can be oriented verti-
cally, with devices mounted on both sides.
7-1
~ Custom Module Capabilities
~~~~==============================================================
Custom Module Flow (Continued)
The layout of the module is also netlist driven. An auto-
router mayor may not be used, depending on the complex-
ity and density of the module. Design rule checks are run
to ensure that the layout does not violate any electrical or
mechanical design rules. Finally, the layout output is used
to generate the module substrate.
The layout output is also used to drive the pick and place
equipment. This ensures consistency between design and
manufacturing. While the module prototypes are being as-
sembled, the test program is generated and the test fixture
is constructed. Test program generation is largely automat-
ed, using as inputs the simulation outputs and pre-defined
test program subroutines for common configurations.
Once prototypes have been generated, the standard release
procedure is initiated. This procedure includes steps such
as bench testing, module characterization and qualifica-
tion, and fine tuning of the test program. Following cus-
tomer approval of the module, it is released to production.
Future Technologies
Cypress is committed to providing the most advanced cus-
tom module capability in the industry. This commitment
includes more than simply modularizing the most ad-
vanced Cypress memory products. As part of our commit-
ment to redefining the leading edge in module technology,
we are pioneering the use of several advanced technologies:
ECL and BiCMOS products of Cypress' Aspen Semi-
conductor subsidiary.
Advanced packaging techniques such as Tape Automat-
ed Bonding (TAB).
Advanced module package formats, such as ZIP pack-
aging and sub-one hundred mil pin spacing.
Application of design automation techniques to module
products.
Quoting Information
In order to prepare a quotation or proposal, we need as
much as possible of the following information:
Circuit Schematic
Mechanical dimensions required
Speed and power requirements
0168-1
Figure 1. Custom Module Flow Prototype and production deadlines
Production Quantity estimates
An Engineering contact to answer questions
Once the above information is received, a budgetary quota-
tion will typically be provided within one to two weeks.
7-2
,.
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS

,~.
LOGIC

RISC

MODULES

,.
BRIDGEMOS
QUICKPRO
".
PLDTOOLKIT
QUALITY AND
RELIABILITY

APPLICATION BRIEFS n
PACKAGES ..
Sin Section Contents
~~~UaDR~~~==~~~~~~~~~~~~~~~~~~~~========~====
EeL Page Number
CYlOE301 Combinatorial ECL 16P8 PLD ................................................. 8-1
CYI00E301 Combinatorial ECL 16P8 PLD ................................................. 8-1
CYlOE302 Combinatorial ECL 16P4 PLD ................................................. 8-6
CY100E302 Combinatorial ECL 16P4 PLD ................................................. 8-6
CYlOE422 256 x 4 ECL Static RAM .................................................... 8-11
CY100E422 256 x 4 ECL Static RAM .................................................... 8-11
CYlOE474 1024 x 4 ECL Static RAM ................................................... 8-16
CY100E474 1024 x 4 ECL Static RAM ...................................... , ............ 8-16
CYIOE301
ADVANCED INFORMATION CYIOOE301
CYPRESS
SEMICONDUCTOR Combinatorial ECL 16P8
Programmable Logic Device
eatures Functional Description active LOW to occur if this fuse is blown.
A security feature provides the user pro-
Standard 16P8 pinout and Cypress Semiconductor's PLD family tection for the implementation of proprie-
architecture offers the user the highest level of per- tary logic. When invoked by blowing the
- 16 inputs, 8 outputs formance in ECL Programmable Logic security fuse, the contents of the array
Devices. These PLDs are developed by cannot be accessed in the verify mode.
- User programmable output polarity
Aspen Semiconductor Corporation, a sub-
Ultra high speed/standard power The CYIOE301 and CYIOOE301 can be
sidiary of Cypress Semiconductor, using
programmed using Cypress' QuickPro or
- tPD = 3 ns (max) an advanced Bipolar process incorporating
other industry standard programming
- lEE = 240 rnA (max) proven Ti-W fuses.
equipment. Programming support infor-
Low power version The CYlOE30l is lOKH compatible and mation can be obtained from local
- tPD = 6 ns (max)
the CY1OOE30l is lOOK compatible. Cypress sales offices.
These PLDs implement the familiar sum-
- lEE = 170mA (max) of-products logic functions by selectively
Both lOKH and lOOK I/O compatible programming cell elements to configure
versions available the AND gates by disconnecting either
Enhanced test features the true or complement input term. If all
- Additional test input terms inputs are disconnected from an AND
gate, then a logical true will exist at the
- Additional test product terms output of this AND gate. An output po-
I Security fuse larity fuse is also provided to allow an
Logic Symbol and Pinout LCC and PLCC Pinout
()
I/O 0 VCC2 0 I/O () ()
z>-_
.....
4 3 2
~ 28 27 26
I/O 254 I/O

o 24 0
VCC1 23 VCC2
NC 22 NC
o 21 0
I/O 10 20 I/O
11 19
12 13 14 15 16 17 18
~
~~
C301-1 C301-2
Selection Guide
lOE301-3 lOE301-4 lOE301-6 lOE301L-6
I lOOE301-3 lOOE301-4 lOOE301L-6
Maximum Input to Output Propagation Delay Cns) 3 4 6 6
lEE (rnA)
I Commercial -240 -240 170
r Military -240
8-1
~PFSS
CYI0E3~
ADVANCED INFORMATION CYI00E3~
_~ICONDUCTOR
Maximum Ratings Operating Range Referenced to V CC at ground
(Above which the useful life may be impaired. Exposure to Range I/O Temperature VEE
absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.) Commercial lOKH OOC to +7SoC -S.2V 50/.
(Standard, "L") Ambient
Storage Temperature .................... -65C to + 150C
Ambient Temperature with Commercial lOOK OC to +8SoC -4.5V 0.3'
Power Applied (1) -S5C to + 125C
Supply Voltage VEE to VCC .............. -7.0 V to +O.SV Military lOKH -SSoC to+ 12SoC -S.2V 5~
Case
Input Voltage ............................. VEE to +0.5V
Output Current ................................... -SO rnA
Electrical Characteristics Over Operating Range (2)
lOE301 lOOE301
Parameters Description Test Conditions Temperature [1] Units
Min. Max. Min. Max.
TC= -SsoC -1110 -930 mV
1A = OC -1020 -840 mV
lOKH, RL = 50 n to -2V
VIN = VIR Min. or VIL Max. 1A = +25C -980 -810 mV
VOH Output HIGH Voltage 1A = +7SoC -920 -735 mV
TC = +l25C -830 -660 mV
lOOK, RL = SO n to -2V
TA = OC to + 8SoC -1025 -880 mV
V IN = VIR Min. or'iL Max.
TC = -SsoC -19S0 -1630 mV
1A = OC -1950 -1630 mV
lOKH, RL = SO n to -2V 1A = +2SoC -19S0 -1630 mV
VIN = VIR Min. or VIL Max.
VOL Output LOW Voltage 1A= +7SoC -19S0 -1600 mV
TC = +12SoC -19S0 -IS70 mV
lOOK, RL = SO n to -2V
VIN = VIR Min. or'iL Max. TA = OC to + 85C -1810 -1620 mV
TC= -S5C -1250 -930 mV
1A = OC -1170 -840 mV
lOKH 1A = +25C -1130 -810 mV
'iH Input HIGH Voltage
1A = +75C -1070 -735 mV
TC = +l25C -1000 -660 mV
lOOK 1A = OC to +85C -1165 -880 mV
Tc = -S5C -1950 -1480 mV
1A = OC -19S0 -1480 mV
VIL Input LOW Voltage

10KH 1A = +25C -1950 -1480 mV
1A = +75C -19S0 -1450 mV
TC = +125C -1950 -1420 mV
lOOK 1A = OC to +85C -1810 -1475 mV
IIR Input HIGH Current VIN = 'iH Max. 220 220 J.lA
IlL Input LOW Current VIN = VIL Min. (Except I/O pins) O.S 0.5 J.lA
Supply Current Commercial "L" (Low Power) -170 -170 rnA
lEE (All inputs and outputs Commercial (Standard Power) -240 -240 rnA
open) Military -240 rnA
Notes:
1. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute. Military grade is specified as case
temperature.
2. See AC Test Loads and Waveforms for test conditions.
8-2
I!'~PRESS
./~MICONDUcrOR
ADVANCED INFORMATION
CYIOE301
CYIOOE301
apacitance[3]
~arameters Description Min. Typ. Max. Units
. CIN Input Capacitance 4 10 pF
COUT Output Capacitance 6 13 pF
lte:
Tested initially and after any design or process changes that may affect these parameters.
witching Characteristics Over Operating Range [2]

lOE301-3 lOE301-4 lOE301L-6
)arameters Description lOOE301-3 lOOE301-4 lOOE301L-6 Units
tpD Input to Output Propagation Delay 3.0 4.0 6.0 ns
tr Output Rise Time 0.7 1.5 0.7 1.5 0.7 1.5 ns
tf Output Fall Time 0.7 1.5 0.7 1.5 0.7 1.5 ns
.C Test Loads and Waveforms [4.5.6,7,6,9]

GND
INPUT
rr
V1H
~%
Vcc , VCC1 ' VCC2
20%
lPUT DOUT V1l
VEE Rl Ie

tr tf
0.01 )JF J. -2.0V C301-4

VEE C301-3
Figure 1 Figure 2
lotes:
. VJL = VJL Min., \fH = VJH Max. on lOKH version. 8. tr = t f = 0.7 ns.
. VIL = -1. 7V, 'VIH = -0.9V on lOOK version. 9. All timing measurements are made from the 50% point of all
I. RL = 50 Q, C < 5 pF (includes fixture and stray capacitance). waveforms.
'. All coaxial cables should be 50 Q with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
~witching Waveforms
INPUT
. OUTPUT
C301-5
8-3
.
fin . - CYPRESS
SEMICONDUCTOR
ADVANCED INFORMATION
CY10E31
CYI00E3~
Functional Logic Diagram

INCREMENT --- 0 10 12 14 16 18 20 22 "4
&. 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 -] Vce
CD---[?~ <- 23
2
"> <J
....
22
FIRST---o
FUS E 64 32
NUMBERS
- >j)PtI
128 96 -@J I/O
192 ~:~
. 2048
3
"> <;J
256 288
320 352
384
448
416
480 ~I>i. ~ I/O
<-
2049
I
~~~ 544
>j~ ~ o
640 608
704 ~;~
2050
768
832 800
896 :~:
960 992 ~~ --0 o
2051
~~::1056
~~ -@] o
1120
1152 1184
1216
1248
2052
1280
1344 1312
~~ r---El o
1376
14081440
1472
1504
- 2053
~~~~1568
~I>i. -@] I/O
1632
1664 1696
1728
1760
<:;.
2054
I
-
~~:1824
- ~I>i.
1888
19201952
1984
2016
r---EJ I/O
... I 2055
<
<.... , 16
...
9 ;;;- < 15
-
...
10
"> < 14
11 ;;;- <- ,
- 13
C301-6
JEDEC fuse number = first fuse number + increment
8-4
:j~PRESS
CYI0E301
~"AICONDUcrOR
I
rdering Information
I
tpD lEE Package Operating

I/O (ns) (rnA) Ordering Code Type Range
lOKH 3.0 240 CYlOE301-3DC D14 Commercial
CYlOE301-3LC L64
4.0 240 CYlOE301-4DC D14 Commercial
CYlOE301-4LC L64
6.0 150 CYlOE301l.r6JC J64 Commercial
CYlOE301l.r6PC P13A
CYlOE301l.r6DC D14
6.0 240 CYlOE301-6DMB D14 Military
CYlOE301-6LMB L64
lOOK 3.0 240 CYI00E301-3DC D14 Commercial
CYI00E301-3LC L64
4.0 240 CYI00E301-4DC D14 Commercial
CYI00E301-4LC L64
6.0 159 CYI00E301l.r6JC J64 Commercial
CYlOOE301l.r6PC P13A
CYI00E301l.r6DC D14
lCument #: 38-A-OOOll
8-5
CYIOE3,J
ADVANCED INFORMATION CYIOOE3~
CYPRESS
SEMICONDUCTOR Combinatorial ECL 16F
Programmable Logic Devic
Features Functional Description active LOW to occur if this fuse is blow
A security feature provides the user pro
Standard l6P4 pinout and Cypress Semiconductor's PLD family tection for the implementation of propr
architecture offers the user the highest level of per- tary logic. When invoked by blowing the
- 16 inputs, 4 outputs formance in ECL Programmable Logic security fuse, the contents of the array
Devices. These PLDs are developed by cannot be accessed in the verify mode.
- User programmable output polarity
Aspen Semiconductor Corporation, a sub-
Ultra high speed/standard power sidiary of Cypress Semiconductor, using The CY10E302 and CY100E302 can be
programmed using Cypress' QuickPro 0
- tPD =2.5 ns (max) an advanced process incorporating proven
other industry standard programming
- lEE =220 rnA (max) Ti-W fuses.
equipment. Programming support
Low power version The CY1OE302 is 10KH compatible and information can be obtained from local
the CY100E302 is lOOK compatible.
- tPD =6 ns (max)
These PLDs implement the familiar sum-
Cypress Semiconductor sales offices.
- lEE =170mA (max) of-products logic functions by selectively
Both 10KH and lOOK I/O compatible programming cell elements to configure
versions available the AND gates by disconnecting either
Enhanced test features the true or complement input term. If all
inputs are disconnected from an AND
- Additional test input terms
gate, then a logical true will exist at the
- Additional test product terms output of this AND gate. An output po-
Security fuse larity fuse is also provided to allow an
Logic Symbol and Pinout LCC and PLCC Pinout
u 8
z>--
VCC 0 VCC2 0 4 3 2
i,
~
--
28 27 26
....
25 I
0 24 0
VCC1 23 VCC~
NC 22 NC
0 21 0
10 20
11 19
.... l!J2 14 15 16 17 18
.J
C302-1 ~~ C302
Selection Guide
10E302-2.S lOE3024 10E302h6
lOOE302-2.S lOOE302-4 lOE3026 lOOE302h6
Maximum Input to Output Propagation Delay (ns) 2.5 4 6 6
lEE (rnA)
I Commercial -220 -220 -170
I Military -220
8-6
~~=
CYI0E302
ADVANCED INFORMATION CYI00E302
!
:aximum Ratings Operating Range Referenced to V CC at ground

bove which the useful1ife may be impaired. Exposure to Range I/O Temperature VEE
solute maximum rated conditions for extended periods may
'ect device reliability. For user guidelines, not tested.) Commercial lOKH OOC to +75C -5.2V 5%
)rage Temperature .................... -65C to + 150C
nbient Temperature with Commercial lOOK OC to +85C -4.5V 0.3V
,wer Applied [1] -55C to + 125 c (Standard, "L") Ambient
pply Voltage VEE to VCC .............. -7.0 V to +0.5V Military lOKH -55C to+ 125C -5.2V 5%
Case
put Voltage ............................. VEE to +0.5V
ltput Current ................................... -50 rnA
lectrical Characteristics Over Operating Range [2]
lOE302 lOOE302
arameters Description Test Conditions Temperature [1] Units
Min. Max. Min. Max.
TC= -55C -1110 -930 mV
TA= OC -1020 -840 mV
TA = +25C -980 -810 mV
VIN = VIH Min. or VIL Max.
VOH Output HIGH Voltage TA= +75C -920 -735 mV
TC= +l25C -830 -660 mV
lOOK, RL = 50 n to -2V
TA = OC to 85C -1025 -880 mV
VIN = VIH Min. or \lL Max.
TC= -55C -1950 -1630 mV
TA= OC -1950 -1630 mV

TA= +25C -1950 -1630 mV
VIN = VIH Min. or VIL Max.
VOL Output LOW Voltage TA= +75C -1950 -1600 mV
TC= +l25C -1950 -1570 mV
lOOK, RL = 50 n to -2V
VIN = VIH Min. or \lL Max. TA = OC to 85C -1810 -1620 mV
TC= -55C -1250 -930 mV
TA= OC -1170 -840 mV
10KH TA = +25C -1130 -810 mV
\1H Input HIGH Voltage
TA = +75C -1070 -735 mV
TC= +125C -1000 -660 mV
lOOK 1A = OC to 85C -1165 -880 mV
TC= -55C -1950 -1480 mV
TA= OC -1950 -1480 mV
10KH TA= +25C -1950 -1480 mV
VIL Input LOW Voltage
TA = +75C -1950 -1450 mV
Tc= + 125C -1950 -1420 mV
lOOK TA = OC to 85C -1810 -1475 mV
IIH Input HIGH Current VIN = \1H Max. 220 220 lJA
IlL Input LOW Current VIN = VIL Min. 0.5 0.5 lJA
Supply Current Commercial "L" (Low Power) -170 -170 rnA
lEE (All inputs and outputs Commercial (Standard Power) -220 -220 rnA
open) Military -220 rnA
fotes:
. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute. Military grade is specified as case
temperature.
. See AC Test Loads and Waveforms for test conditions.
8-7
.
&n CYPRESS
SEMICONDUCTOR
ADVANCED INFORMATION CYI0E3~
CYIOOE3
I
Capacitance(3)
Parameters Description Min. Typ. Max. Units
CIN Input Capacitance 4 10 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.

lOE302-2.S lOE302-4 lOE302L-6
Parameters Description lOOE302-2.S lOOE302-4 lOOE302L-6 Units
tpD Input to Output Propagation Delay 2.5 4.0 6.0 ns
AC Test Loads and Waveforms [4.5.6,7,8.9)

GND
INPUT
: ~~~~~--~-tf-t~""------- INPUT
0.01 ~F~ -2.0V 0302

VEE C302-3
Figure 1 Figure 2
Notes:
4. \'IL = \'IL Min., 'fH = \'IH Max. on 10KH version. 8. tr = tf= 0.7 ns.
5. "IL = -1.7V, \'IH = -0.9Von lOOK version. 9. All timing measurements are made from the 50% point of al
6. RL = 500, C < 5 pF (includes fixture and stray capacitance). waveforms.
7. All coaxial cables should be 50 0 with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
Switching Waveforms
V 1H
INPUT
OUTPUT
V 1L
V OH
VOL
E,po==*
C302-
8-8
~PREBS
CYIOE302
_~ICONDUcrOR
i'unctional Logic Diagram
INCREMENT - . . 0 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 r@] Vee
...
CD--{?-
.
< 23
2
=> ~-
<-- 22
.
"> < 21
4
~-
::>
FIRST~512 544
FUS E 576
NUMBERS 640 608
704 ~~ >rI>- ----] o
2050
766
832 800
696:
- ~
960 992
----0 o
2051
1024
10881056
1152
1216
1280
1120
1184
1248
~
>-r;I>-- -@ o
2052
13441312
~1>- ---0 o
1376
1408
1440
1472
1504
- 2053
<-- 17
..
8
-=> <_..I 16
...
9
r_
2 <I 15
10
=>
- < 14
..
11
r_ "> < . 13
0302-6
JEDEC fuse number = first fuse number + increment
8-9
~PRSS ADVANCED INFORMATION
CY10E31
CYIOOE30;
WnMICONDUCTOR
tpD lEE Package Operating
I/O (ns) (mA) Ordering Code Type Range
10KH 2.5 220 CYlOE302-2.5DC D14 Commercial
CYlOE302-2.5LC L64
4.0 220 CYI0E302-4DC D14 Commercial
CYlOE302-4LC L64
6.0 150 CYlOE302-6JC J64 Commercial
CYI0E302L-6PC P13A
CYlOE302L-6DC D14
6.0 220 CYI0E302-6DMB Dl Military
CYlOE302-6LMB L64
lOOK 2.5 220 CYI00E302-2.5DC D14 Commercial
CYI00E302-2.SLC L64
4.0 220 CYlOOE302-4DC D14 Commercial
CYlOOE302-4LC 1.64
6.0 150 CYlOOE302L-6JC J64 Commercial
CYlOOE302L-6PC P13A
CYI00E302L-6DC D14
Docume\1t #: 38-A-00012
8-10
CYIOE422
CYPRESS
SEMICONDUCTOR 256 X 4 EeL
Static RAM
eatures Open emitter output for ease of compatible. The CYlOOE422 is lOOK
memory expansion compatible.
, 256 x 4 bits organization
Industry standard pinout The four independent active LOW block
. Ultra high speed/standard power select (13) inputs control memory selection
- tAA = 3 ns, tABS = 2 ns Functional Description and allow for memory expansion and re-
- lEE =220 rnA The Cypress CY10E422 and CY100E422
configuration. The read and write opera-
Low power version tions are controlled by the state of the ac-
are 256 x 4 ECL RAMs designed for
tive LOW write enable (W) input. With
- tAA = 5 ns scratch pad, control and Buffer Storage
Wand Bx LOW, the corresponding data
- lEE = 150 rnA applications. These RAMs are developed
at Dx is written into the addressed loca-
by Aspen Semiconductor Corporation, a
Both 10KH/lOK and lOOK compatible tion. To read W is held HIGH, while 13 is
subsidiary of Cypress Semiconductor.
I/O versions held LOW. Open emitter outputs allow
Both parts are fully decoded random
On chip voltage compensation for for wired-OR connection to expand or
access memories organized as 256 words
improved noise margin reconfigure the memory.
by 4 bits. The CYlOE422 is 10KH/lOK

A5 A6 A7 Vee D3
04 A4
84 A3
03 A2
83 A1
D4 Ao
D3 VEE
A4 A7
A3 A6
A2 A5
A1 W
Ao D2
C422-2 C422-3
32l!J242322
O2 4 21 03
82 5 20 'S3
D1 6 19 D4
D2 18 D3
W 17 A4
A5 9 16 A3
1011 1213 1415
C422-1
C422-4
LCC
TOP VIEW
Selection Guide
10E422-3 10E422-5 10E422-7
100E422-3 100E422-5 100E422-7
lEE Max. (rnA)

I Commercial -220 -220
I "L" (Low Power) -150 -150
8-11
~PRESS
CYIOE42
ADVANCED INFORMATION CYIOOE4~'
.nMICONDUcrOR
Maximum Ratings Operating Range referenced to VCC

(Above which the useful life may be impaired. Exposure to Ambient
absolute maximum rated conditions for extended periods may Range I/O VEE
Temperature
Commercial lOKH/lOK OOC to 7SoC -5.2V 5%
Storage Temperature ..... . .............. -6SoC to + lS00C (Standard, "L")
Commercial lOOK OOC to 85C -4.SV 0.3'
Power Applied .......... . .............. -SSoC to + 125C (Standard, "L")
Supply Voltage VEE to VCC ............... - 7.0 to +0.5V
Input Voltage ............................. VEE to +0.5V
Output Current ................................... -50 rnA
Electrical Characteristics
Parameters Description Test Conditions Temperature [1) Min. Max. Units
10E(2)RL = SO n to -2V 'fA = OC -1000 -840 mV

VEE= -5.2V TA = +25C -960 -810 mV
VIN = VIH Max. or VIL Min. TA= +75C -900 -735 mV
lOOK RL = 50 n to -2V
VEE= -4.SV TA = OC to 8SoC -1025 -880 mV
VIN = VIH Max. or VIL Min.
10ERL = 50ilto-2V TA = OC -1870 -1665 mV

VEE= -S.2V TA = +25C -18S0 -1650 mV
VIN = VIH Max. or VIL Min. TA = +75C -1830 -1625 mV
VEE= -4.SV TA = OC to 85C -1810 -1620 mV
TA = OC -1170 -840 mV
lOE
TA = +2SC -1130 -810 mV
Input HIGH Voltage VEE = -S.2V
VIH TA = +7SoC -1070 -720 mV
lOOK VEE = -4.5V TA = OC to 85C -1165 -880 mV
TA = OC -1950 -1480 mV
lOE
TA = +25C -1950 -1480 mV
VIL Input LOW Voltage VEE = -5.2V
TA = +7SoC -1950 -1450 mV
IIH Input HIGH Current VIN = VIH Max. 220 ~A
B inputs 0.5 170 ~A
IlL Input LOW Current \iN = \iL Min.
All other inputs -50 ~A
Supply Current Commercial "L" (Low Power) -150 rnA
lEE
(All inputs and outputs open) Commercial Standard -220 rnA
Notes:
1. Commercial grade is specified as ambient Temperature with transverse air flow greater than 500 linear feet per minute.
2. 10E specifications support both 10K and 10KH compatibility.
Capacitance[3)
Parameters Description Min. Typ. Max.I4] Units
CIN Input Capacitance 4 S pF
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
4. For all packages except Cerdip (D40) which has maximums of CIN = 10 pF, COUT = 12 pF.
8-12
CYIOE422
:'7l"'m=ro,
,C Test Loads and Waveforms [5,6,7,8,9,10]
GND
INPUT
V1H
~%
INPUT
0.01 ~FJ. -2.0V C422-5

V1L
tI tr t,
20%
C422-6
VEE
Figure 1 Figure 2
otes:
, \'xL = \'xL Min., \fH = \'xH Max. on lOE version. 8. All coaxial cables should be 50 n with equal lengths. The delay of the
, VJL = -1.7V, \1H = -0.9Von lOOK version. coaxial cables should be "nulled" out of the measurement.
, RL = 50 n, C < 5 pF (3 ns grade) or < 30 pF (5, 7 ns grade) 9. tr = tf = 0.7 ns.
(includes fIxture and stray capacitance). 10. All timing measurements are made from the 50% point of all
waveforms.
,witching Characteristics Over Operating Range

lOE422-3 lOE422-5 lOE422-7
:arameters Description lOOE422-3 lOOE422-5 lOOE422-7 Units
tABS Block Select to Output delay 2.0 3.0 4.0 ns
tRBS Block Select Recovery 2.0 3.0 4.0 ns
tAA Address Access Time 3.0 5.0 7.0 ns
tw Write Pulse Width 3.0 3.0 5.0 ns
tWSD Data Setup to Write 0.5 1.0 1.0 ns
tWHD Data Hold to Write 0.5 1.0 1.0 ns
tWSA Address Setup/Write 0.5 1.0 1.0 ns
tWHA Address Hold/Write 0.5 1.0 1.0 ns
tWSBS Block Select Setup/Write 0,5 1.0 1.0 ns
tWHBS Block Select Hold/Write 0.5 1.0 1.0 ns
tws Write Disable 2.0 3.0 4.0 ns
tWR Write Recovery 3.5 6.0 8.0 ns
8-13
.11
IJII'.--- CYIOE421
~~PRESS ADVANCED INFORMATION CYIOOE42
-::sJ!!!!IT' ~EMICONDUCTOR
Switching Waveforms
Read Mode
C422-
ADDRESS
C422-
Write Mode
~~ ~
~50%
ADDRESS 50%) ~ 50%} K

D 50%) ( 50%
-I tWHD
~ ~50% 50%~
E
t wsD
- tWHA -
I----- t WSA tw t WHBS
Q
t wsBS
)~
I+- tws tWR
C422-1
8-14
CYIOE422
luth Table
Inputs Outputs
iBx W Dx Qx Mode
H X X L Disabled
L L H L Write "H"
L L L L Write "L"
L H X Out Read
rdering Information
lEE tAA Package Operating
l/O (mA) (ns) Ordering Code Type Range
IE[ll] 220 3.0 CYlOE422-3LC L63 Commercial
S.O CYI0E422-SLC L63
5.0 CYlOE422-5DC D40
IE ISO S.O CYlOE422L-SLC L63 Commercial
S.O CYlOE422L-SDC D40
7.0 CYlOE422L-7LC L63
7.0 CYlOE422L-7DC D40
)OK 220 3.0 CYlOOE422-3LC L63 Commercial
S.O CYlOOE422-SLC L63
S.O CYI00E422-SDC D40
)OK ISO S.O CYlOOE422L-SLC L63 Commercial
S.O CYlOOE422L-SDC D40
7.0 CYlOOE422L-7LC L63
7.0 CYl00E422L-7DC D40
Ite:
. 10E specifications support both 10K and 10KH compatibility.
)cument #: 38-A-00002
8-15
~
I
CYIOE4
ADVANCED INFORMATION CYIOOE4.
CYPRESS
SEMICONDUCTOR 1024 x 4 Ee
Static RM
Features Open emitter output for ease of by 4 bits. The CY10E474 is lOKH/lOK
memory expansion compatible. The CY100E474 is lOOK
1024 x 4 bits organization compatible.
Industry standard pinout
Ultra high speed/standard power The active LOW chip select (8) input
- tM = 3 ns, tACS = 2 ns Functional Description controls memory selection and allows fc
- lEE = 275 rnA The CypressCY10E474 and CY1ooE474
memory expansion. The read and write
operations are controlled by the state 01
Low power version are 1K x 4 ECL RAMs designed for the active LOW write enable (W) input
- tM = 5 ns scratch pad, control and Buffer Storage With Wand S LOW, the data at D(l-4
- lEE = 190 rnA applications. These RAMs are developed is written into the addressed location. T,
by Aspen Semiconductor Corporation, a read W is held HIGH, while S is held
Both 10KH/lOK and lOOK compatible
subsidiary of Cypress Semiconductor. LOW. Open emitter outputs allow for
I/O versions
Both parts are fully decoded random wired-OR connection to expand the
On chip voltage compensation for access memories organized as 1024 words
improved noise margin memory.

A3 VCCA Vcc O2 01
03 2 03 S
4 1 04 W
Ao 04 1 A9
A1 03 2 As
A2 02 Vcc A7
A3 01 VCCA Vee
A4 S 03 A6
A5 W 4 NC
NC A9 Ao A5
Ae As A1 A4
Vee A7 A2 A3
0474-2 0474-

aa~:cro
32l!J242322
Ao 4 21 O.
A1 5 20 0:
A2 19 0;
A3 18 [).
0(1-4) A4 8 17 S
S A5 9 16 W
10 1112 131415
W ()<OW .... OOCD
zc(~c(c(c(
0(1-4) 0474-.
C474-1 LCC
TOP VIEW
Selection Guide
10E474-3 10E474-5 10E474-7
100E474-3 100E474-5 100E474-7
/ Commercial -275 -275
lEE Max. (rnA)
/ "L" -190 -190
8-16
r;r~D~
CYIOE474
I
rIaximum Ratings Operating Range referenced to VCC

\bove which the useful life may be impaired. Exposure to Ambient
bsolute maximum rated conditions for extended periods may Range I/O VEE
Temperature
ffect device reliability. For user guidelines, not tested.)
Commercial lOKH/lOK OC to 75C -5.2V 5%
torage Temperature .................... -6S o C to + 150C (Standard, "L")
.mbient Temperature with
ower Applied ......................... -55C to + 125 C Commercial lOOK OOC to 85C -4.5V 0.3V
(Standard, "L")
upply Voltage VEE to Vee ............... -7.0 to +0.5V
Iput Voltage ............................. VEE to +0.5V
lutput Current ................................... -50 mA
aectrical Characteristics
Parameters Description Test Conditions Temperature [lJ Min. Max. Units
10E[2JRL = 50 n to -2V 'fA = OC -1000 -840 mV

VEE= -5.2V TA = +25C -960 -810 mV
VIN = VIH Max. or VIL Min. TA = +75C -900 -735 mV
VEE= -4.5V TA = OC to 85C -1025 -880 mV
10E RL = 50 n to -2V TA = OC -1870 -1665 mV

VEE= -5.2V TA = +25C -1850 -1650 mV
VIN = VIH Max. or V IL Min. TA = +75C -1830 -1625 mV

VEE= -4.5V TA = OC to 85C -1810 -1620 mV
TA = OC -1170 -840 mV
10E
VEE = -5.2V TA =
+25C -1130 -810 mV
VIH Input HIGH Voltage TA = +75C -1070 -720 mV
TA = OC -1950 -1480 mV
10E TA = +25C -1950 -1480 mV
VIL Input LOW Voltage VEE = -5.2V
TA = +75C -1950 -1450 mV
IIH Input HIGH Current VIN = VIHMax. 220 pA
IlL Input LOW Current VIN = VIL Min. 10 pA
Supply Current Commercial "L" (Low Power) -190 mA
lEE (AIl inputs and outputs open) Commercial Standard -275 mA
'otes:
, Commercial grade is specified as ambient Temperature with transverse air flow greater than 500 linear feet per minute.
, 10E specifications support both 10K and rOKH compatibility.
~apacitance[3J
Parameters Description Min. Typ. Max,C4J Units
CIN Input Pin Capacitance 4 5 pF

COUT Output Pin Capacitance 6 8 pF
rotes:
, Tested initially and after any design or process changes that may affect these parameters.
. For all packages except Cerdip (D40) which has maximums of CIN = 10 pF, COUT = 12 pF.
8-17
~PFESS ADVANCED INFORMATION CYI0E47~
CYI00E41
.nEMICONDUcrOR
AC Test Loads and Waveforms [6. e. 7. 8. 9.10)

GND
INPUT II
V1H
~%
~
Vee
20%
INPUT
V1L
Dour
VEE
tf
0.01 ~F J. -2.0V 0474-5 0474-1

VEE
Figure 1 Figure 2
Notes:
5. VIL = "IL Min., 'fH = "IH Max. on 10E version. 8. All coaxial cables should be 50 a with equal lengths. The delay of the
6. ViL = -1.7V, \'IH = -0.9Von lOOK version. coaxial cables should be "nulled" out of the measurement.
7. RL = 50 a, C < 5 pF (3 ns grade) or < 30 pF (5, 7 ns grade) 9. tr = tr = 0.7 ns.
(includes fixture and stray capacitance). 10. All timing measurements are made from the 50% point of all
waveforms.
Switching Characteristics Over Operating Range

lOE4743 lOE474-S lOE4747
Parameters Description lOOE4743 lOOE474-S lOOE474-7 Units
tACS Input to Output delay 2.0 3.0 3.0 ns
tRCS Chip Select Recovery 2.0 3.0 3.0 ns
tAA Address Access Time 3.0 5.0 7.0 ns
tw Write Pulse Width 3.0 3.0 4.0 ns
tWSD Data Setup to Write 0.5 0.5 1.0 ns
tWHD Data Hold to Write 0.5 1.5 2.0 ns
twSA Address Setup/Write 0.5 0.5 1.0 ns
tWHA Address Hold/Write 0.5 1.5 2.0 ns
twscs Chip Select Setup/Write 0.5 0.5 1.0 ns
tWHCS Chip Select Hold/Write 0.5 1.5 2.0 ns
tws Write Disable 20 3.0 4.0 ns
tWR Write Recovery 3.5 6.5 9.0 ns
tr Output Rise Time 0.7 1.5 0.7 2.5 1.0 25 ns
8-18
Isr~
CYIOE474
. SEMICONDUCIOR
Switching Waveforms
Read Mode
~%
'~tRCS~ __
Q
~~tf
=====_~_-_-_-_-_~-_-_-_-_-_-tAA~=-=-~=-=-~=-=-~=-=-~=-~~-':=====
ADDRESS
0474-7
Write Mode
~~ ,;~50%
ADDRESS 50%) ( 50%) (

D 50%) ( 50%
"l tWHD
w t WSD ~~50% 50%~ It'

10--- t WHA -
t--- t WSA tw t wHoS ~
Q
twscs
)Il'
14- tws tWR
0474-8
8-19
~~~
CYI0E47J
lEE tAA Package Operating
I/O (rnA) (os) Ordering Code Type Range
10E(11) 275 3.0 CYlOE474-3LC 1..63 Commercial
S.O CY10E474-SLC 1..63
S.O CY10E474-SDC D40
10E 190 S.O CYlOE474L-SLC 1..63 Commercial
S.O CY10E474L-SDC D40
7.0 CYlOE474L-7LC 1..63
7.0 CY10E474L-7DC D40
lOOK 27S 3.0 CYlOOE474-3LC L63 Commercial
S.O CYlOOE474-SLC L63
5.0 CYlOOE474-SDC D40
lOOK 190 5.0 CY100E474L-SLC L63 Commercial
5.0 CY100E474L-SDC D40
7.0 CYlOOE474L-7LC L63
7.0 CYlOOE474L-7DC D40
Note:
11. 10E specifications support both 10K and 10KH compatibility.
Document #: 38-A-00004
8-20
~ Section Contents
'~~~U~============================================================~
~ilitary Information Page Number
~i1itary Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 9-1
~ilitary Product Selection Guide .......................................................................... 9-2
~ilitary Ordering Information ............................................................... " ........... 9-5
~~~,=================~===i=li=t=a=r=y==()==v=e=r=v=i=e=lV==================
Every final data sheet also contains detailed Group A sub-
[ntroduction group testing information. Each of the specified parameters
)uccess at any endeavor requires a high level of dedication that are tested at Group A are listed in a table at the end of
o the task. Cypress Semiconductor has demonstrated its each final data sheet, with a notation as to which specific
ledication through its corporate commitment to support Group A test subgroups apply.
he military marketplace. The commitment starts with
Jroduct design. All products are designed on our state-of- Assembly Traceability Code
:he-art CMOS, BiCMOS and Bipolar processes and they
nust meet the full - 55 to + 125 degree C operational Cypress Semiconductor marks an assembly traceability
~riteria for military use. The commitment continues with code on every military package that is large enough to con-
:he 1986 DESC certification of our automated U.S. facility tain the code. The ATC automatically provides traceability
n San Jose, California. The commitment shows in our ded- for that product to the individual wafer lot. This unique
cation to meet and exceed the stringent quality and reli- code provides Cypress with the ability to determine which
lbility requirements of MIL-STD-883 and MIL-M-3851O. operators and equipment were used in the manufacture of
[t shows in Cypress' participation in each of the military that product from start to finish.
Jrocessing programs: 883C-Compliant, SMD (Standard
Military Drawing) and JAN. Finally, our commitment Quality and Reliability
;hows in our leadership position in special packages for
lllilitary use. MIL-STD-883 and MIL-M-3851O spell out the toughest of
quality and reliability standards for military products. Cy-
press products meet all of these requirements and more.
Product Design Our in-house quality and reliability programs are being up-
Every Cypress product is designed to meet or exceed the dated regularly with tighter and tighter objectives. Please
full temperature and functional requirements of military refer to the chapter on Quality, Reliability and Process
product. This means that Cypress builds military product Flows for further details.
as a matter of course, rather than as an accidental benefit
Df favorable test yield. Designs are being carried out on our Military Product Offerings
industry-leading 0.8 micron CMOS, BiCMOS and Bipolar
Cypress offers three different levels of processing for mili-
processes. Cypress is able to offer a family of products that
are industry leaders in density, low operating and standby tary product.
current and high speed. In addition, our technology results First, all Cypress products are available with processing in
in products with very small manufacturable die sizes that full compliance with MIL-STD-883, Revision C.
,will fit into the LCC's and flatpacks so often used on mili- Secondly, selected products are available to the SMD
tary programs. (Standard Military Drawing) program supervised by
DESC. These products are not only fully 883C-compliant
DESC-Certified Facility but they are also screened to the electrical requirements of
bn May 8, 1986, the Cypress facility at 3901 North First the applicable military drawing.
Street in San Jose, California was certified by DESC for the Third, selected products are available as JAN devices.
production of JAN Level B CMOS Microcircuits. This cer- These products are processed in full accordance with MIL-
tification not cnly provided Cypress with the ability to M-3851O and they are screened to the electrical require-
qualify product for JAN use, but it also benefitted all of ments of the applicable JAN slash sheet.
our customers by acknowledging that our San Jose facility
has the necessary documentation and procedures in place Product Packaging
to manufacture product to the most stringent of quality
and reliability requirements. Our wafer fabrication facili- All packages for military product are hermetic. A look at
ties are Class 10 (San Jose) and Class 1 (Round Rock, TX) the package appendix in the back of this data book will
manufacturing environments and our assembly facility is give the reader an appreciation of the variety of packages
also a clean room. In addition, our highly automated as- offered. Included are cerdips, windowed cerdips, leadless
sembly facility is entirely located in the U.S.A. and is capa- chip carriers (LCC's), leadless chip carriers with windows
ble of handling virtually any hermetic package configura- for reprogrammable products, cerpack, windowed cerpak,
tion. bottom-brazed flatpacks and pin grid arrays. As indicated
above, all of these packages are assembled in the U.S. in
our highly automated San Jose plant.
Data Sheet Documentation
Every Cypress final data sheet is a corporate document Summary
with a revision history. The document number and revision
appears on each final data sheet. Cypress maintains a list- Cypress Semiconductor is committed to the support of the
ing of all data sheet documentation and a copy is available military marketplace. Our commitment is demonstrated by
to customers upon request. This gives a customer the abili- our product designs, our DESC-certified facility, our docu-
ty to verify the current status of any data sheet and it also mentation and traceability, our quality and reliability pro-
gives that customer the ability to obtain updated specifica- grams, our support of all levels of military processing and
tions as required. by our leadership in special packaging.
Assembly Traceability Code is a trademark of Cypress Semiconductor Corporation.
9-1
SEMICONDUcrOR
Military Product Selection Guide
Size Organization JAN/SMD IcclIsoflccDR
Pins Part Number Speed (ns)
Number (mA@ns)
SRAMs 64 16 x 4-lnverting 16 CY7C189 tAA = 25 70@25
64 16 x 4-Non-Inverting 16 CY7C190 tAA = 25 70@25
64 16 x 4-lnverting 16 CY27S03/A tAA = 25,35 100 @25
64 16 x 4-Non-Inverting 16 CY27S07/A tAA = 25,35 100 @25
64 16 x 4-lnvertingiLow Power 16 CY27LS03 tAA = 65 38@65
lK 256x4 22 CY7C122 5962-88594 tAA = 25,35 90@25
lK 256x4 24S CY7C123 tAA = 10, 12, 15 150@ 15
lK 256x4 22 CY9122191L22 5962-88594 tAA = 35,45 90@45
lK 256x4 22 CY93422A/93U22A tAA = 45, 55, 60, 75 90@ 55
4K 4K x l-CS Power Down 18 CY7C147 M38510/289 tAA = 35,45 11O/10@ 35
4K 4Kx l-CSPowerDown 18 CY2147 M38510/289 tAA = 45,55 140/25 @45
4K 4K x l-CS Power Down 18 CY7C147 5962-88587 tAA = 35,45 110/10 @35
4K 4Kx l-CS Power Down 18 CY2147 5962-88587 tAA = 45,55 140/25 @45
4K lK x 4-CS Power Down 18 CY7C148 tAA = 35,45 11O/10@ 35
4K lK x 4-CS Power Down 18 CY2148 tAA = 45,55 140/25 @45
4K lKx4 18 CY7C149 tAA = 35,45 110@ 35
4K lKx4 18 CY2149 tAA = 45,55 14O@45
4K lK x 4-Separate I/O 24S CY7C150 5962-88588 tAA = 15,25,35 1oo@ 15
8K lK x 8-Dual Port 48 CY7C130/31 5962-86875 tAA = 35,45, 55 120/4O@ 35
8K 1K x 8-Dual Port Slave 48 CY7C14O/41 5962-86875 tAA = 35,45, 55 120/4O@ 35
16K 2K x 8-CS Power Down 24S CY7C128 84036 tAA = 35, 45, 55 1OO/20@ 55
16K 2K x 8-CS Power Down 24S CY7C128A 84036 tAA = 25, 35,45, 55 125/4O@ 25
16K 2K x 8-CS Power Down 24 CY6116/7 84036 tAA = 35,45, 55 130/20@ 35
16K 16K x 1-CS Power Down 20 CY7C167 84132 tAA = 35,45 50/20@ 45
16K 16K x 1-CS Power Down 20 CY7C167A 84132 tAA = 25, 35, 45 70/20@ 25
16K 4K x 4-CS Power Down 20 CY7C168 5962-86705 tAA = 35,45 70/20@ 45
16K 4K x 4-CS Power Down 20 CY7C168A 5962-86705 tAA = 25, 35,45 80/20@ 25
16K 4Kx4 20 CY7C169 tAA = 35,40 70@4O
16K 4Kx4 20 CY7C169A tAA = 25, 35, 40 70/20 @35
16K 4K x 4-Output Enable 22S CY7C170 tAA = 35,45 120@ 35
16K 4K x 4-Output Enable 22S CY7C170A tAA = 25, 35, 45 120@ 25
16K 4K x 4-Separate I/O 24S CY7C171 tAA = 35,45 70@45
16K 4K x 4-Separate I/O 24S CY7C172 tAA = 35,45 70@45
16K 4K x 4-Separate I/O 24S CY7C171A/2A tAA = 25, 35, 45 80/20@ 25
16K 2K x 8-Dual Port 48 CY7C132136 5962-87002 tAA = 35,45, 55 170/65 @35
16K 2K x 8-Dual Port Slave 48 CY7C142146 5962-87002 tAA = 35,45, 55 120/4O@ 45
64K 8K x 8-CS Power Down 28S CY7C185/L 5962-85525 tAA = 35,45, 55 100/20/1 @45
64K 8K x 8-CS Power Down 28S CY7C185 tAA = 12,15 155/50@ 12
64K 8K x 8-CS Power Down 28 CY7C186/L 5962-85525 tAA = 35,45, 55 100/20/1 @45
64K 8K x 8-CS Power Down 28 CY7C186 tAA = 12,15 145/50@ 15
64K 16K x 4-CS Power Down 22S CY7Cl64/L 5962-86859 tAA = 35,45 70/20/1 @ 35
64K 16K x 4-CS Power Down 22S CY7Cl64 tAA = 12,15 150/50@ 12
64K 16K x 4-Output Enable 24S CY7C166/L 5962-86859 tAA = 35,45 70/20/1 @35
64K 16K x 4-Output Enable 24S CY7C166 tAA = 12,15 135/50 @ 15
64K 16K x 4-Separate I/O 28S CY7C161/L tAA = 35,45 70/20/1 @35
64K 16K x 4-Separate I/O 28S CY7CI621L tAA = 35,45 70/20/1 @ 35
64K 16K x 4-Separate I/O 28S CY7C161/2 tAA = 12,15 135/50@ 15
64K 64K x l-CS Power Down 22 CY7C187/L 5962-86015 tAA = 35,45 70/20/1 @35
256K 16K x 16-Cache RAM 44 CY7C157 tAA = 24,33 300 @24
256K 32K x 8-CS Power Down 28 CY7C198 5962-88662 tAA = 45,55 120/20@45
256K 32K x 8-CS Power Down 28S CY7C199 tAA = 45,55 120/20@45
256K 64K x 4-CS Power Down 24S CY7C194 5962-88681 tAA = 35,45 90/20@ 35
256K 64K x 4-CS Power Down + OE 28S CY7C196 tAA = 35,45 90/20@ 35
256K 64K x 4-Separate I/O 28S CY7C191 tAA = 35,45 90/20@ 35
256K 64K x 4-Separate I/O 28S CY7C192 tAA = 35,45 90/20@ 35
256K 256K x l-CS Power Down 24S CY7C197 5962-88725 tAA = 35,45 80/20@ 35
Notes: Package Codes: -(W) = Windowed Package
The Cypress facility at 3901 North First Street in San Jose, CA is D = Ceramic DIP (0) = Opaque Package
DESC-certified for JAN class B production. F = Flatpack 22S stands for 22pin 300 mil DIP.
All of the above products are available with processing to G = Pin Grid Array
MIL-STD-883C at a minimum. Many of these products are also avail 24S stands for 24pin 300 mil DIP.
able either to SMDs (Standard Military Drawings) or to JAN slash K = Cerpack 28S stands for 28pin 300 mil DIP.
sheets. L= LCC
The speed and power specifications listed above cover the full military Q = Windowed LCC
temperature range. All power supplies are Vee = 5V 10%. T = Windowed Cerpack
Modules are available with MILSTD883C components. These modules W = Windowed CERDIP
are assembled and screened to the proposed JEDEC military processing
standard for modules.
92
~ Military Product Selection Guide (Continued)
~~~NDUcrOR =======================================================================
JAN/SMD Icc/ISH
Size Organization Pins Part Number Speed (ns)
Number' (mA@ns)
PROMs 4K 512 x 8-Registered 248 CY7C225 5962-88518(0) tSA/CO = 30/15, 35/20,40/25 120 @ 30/15
8K 1K x 8-Registered 248 CY7C235 5962-88636(0) tSA/CO = 30/15,40/20 120 @ 30/15
8K 1Kx8 248 CY7C281 5962-87651(0) tAA = 45 120 @45
8K 1Kx8 24 CY7C282 5962-87651(0) tAA = 45 120 @ 45
16K 2K x 8-Registered 248 CY7C245 5962-87529(W) tSA/CO = 35/15,45/25 120 @ 35/15
16K 2K x 8-Registered 248 CY7C245 5962-88735(0) tSA/CO = 35/15,45/25 120 @ 35/15
16K 2K x 8-Registered 248 CY7C245A tSA/CO = 25/15,35/20 120 @ 25/15
16K 2K x 8-Registered 248 CY7C245A 5962-88735(0) tSA/CO = 25/15,35/20 120@ 25/15
16K 2Kx8 248 CY7C291 5962-87650(W) tAA = 35,50 120 @ 35
16K 2Kx 8 248 CY7C291 5962-88734(0) tAA = 35,50 120 @ 35
16K 2Kx 8 248 CY7C291A 5962-87650 tAA = 30, 35, 50 120 @ 30
16K 2K x 8-C8 Power Down 248 CY7C293A 5962-88680(W) tAA = 30, 35, 50 120/30 @ 35
16K 2Kx 8 24 CY7C292 5962-88734(0) tAA = 50 120 @ 50
16K 2Kx 8 24 CY7C292A tAA = 30,35,50 120@ 30
64K 8K x 8-C8 Power Down 248 CY7C261 5962-87515(W) tAA = 45,55 120/30 @ 45
64K 8Kx 8 248 CY7C263 tAA = 45,55 120 @45
64K 8Kx 8 24 CY7C264 tAA = 45,55 120 @ 45
64K 8K x 8-Registered 288 CY7C265 tSA/CO = 50/25, 60/25 120 @ 50/25
64K 8Kx 8 28 CY7C266 tAA = 55 90
64K 8K x 8-RegisteredlDiagnostic 288 CY7C269 tSA/CO = 50/25, 60/25 100 @ 60/25
64K 8K x 8-Registered/Diagnostic 32 CY7C268 tSA/CO = 50/25, 60/25 100 @ 60/25
128K 16K x 8-C8 Power Down 288 CY7C251 5962-89537 tAA = 55,65 120/35 @ 55
128K 16Kx8 28 CY7C254 5962-89538 tAA = 55,65 120 @ 55
256K 32K x 8-C8 Power Down 288 CY7C271 tAA = 55,65 130/40 @ 55
256K 32Kx8 28 CY7C274 tAA = 55 130/40 @ 55
256K 32K x 8-Registered 288 CY7C277 tSA/CO = 50/25 130/40 @ 55
256K 32K x 8-Latched 288 CY7C279 tAA = 55 130/40 @ 55
512K 64Kx8-FCA 288 CY7C285 tAA/CAA = 75/35 200 @ 35
512K 64K x 8-CE Power Down 28 CY7C286 tAA = 75 150/50 @ 75
JAN/SMD Icc
Size Organization Pins Part Number Speed (ns/MHz)
Number' (mA @ ns/MHz)
PLDs PALC20 16L8, 16R8, 16R6, 16R4 20 PALC16XX 5962-88678(W) tpD = 20, 30, 40 70@ 20
PALC20 16L8, 16R8, 16R6, 16R4 20 PALC16XX 5962-88713(0) tpD = 20, 30, 40 70@ 20
PLD20 18G8-Generic 20 PLDC18G8 tPD/S/CO = 15/15/12 110
PLDC24 22V10---Macro Cell 248 PALC22VlO 5962-87539(W) tPD/S/CO = 20/17/15 100 @ 25/20/20
PLDC24 22V10---Macro Cell 248 PALC22VlO 5962-88670(0) tPD/S/CO = 20/17/15 100 @ 25/20/20
PLDC24 20G lO-Generic 248 PLDC20GlO 5962-88637(0) tPD/S/CO = 20/17/15 80 @ 30/20/20
PLDC24 20RA 10000Asynchronous 248 PLDC20RA10 tPD/SU/CO = 25/15/25 100 @ 25/15/25
PLD 16P8-100K ECL 24 CY100E301 tpD = 6 -240 @ 6
PLD 16P8-IOKH ECL 24 CYlOE301 tpD = 6 -240 @ 6
PLD 16P4--100K ECL 24 CY100E302 tpD = 6 -220 @ 6
PLD 16P4--IOKH ECL 24 CYlOE302 tpD = 6 -220 @ 6
PLDC28 7C330---State Machine 288 CY7C330 5962-89546(W) 40,28 MHz 150@40MHz
PLDC28 7C331-Asynchronous 288 CY7C331 tPD/S/CO = 30/25/30 150 @ 30/25/30
PLDC28 7C332-Combinatorial 288 CY7C332 tICO/IS/IH = 25/5/7 150 @ 25/5/7
Notes: Package Codes: *(W) = Windowed Package
The Cypress facility at 3901 North First Street in 8an Jose, CA is D = Ceramic DIP (0) = Opaque Package
DESC-certified for JAN class B production. F = Flatpack 228 stands for 22-pin 300 mil DIP.
MIL-8TD-883C at a minimum. Many of these products are also avail- 24S stands for 24-pin 300 mil DIP.
K = Cerpack 28S stands for 28-pin 300 mil DIP.
able either to SMDs (8tandard Military Drawings) or to JAN slash
sheets. L= LCC
temperature range. All power supplies are Vcc = 5V 10%. T = Windowed Cerpack
Modules are available with MIL-STD-883C components. These modules W = Windowed CERDIP
are assembled and screened to the proposed JEDEC military processing HD = Hermetic DIP Module
9-3
"~PRF$ Military Product Selection Guide (Continued)
" SEMICONDUcrOR ===================================='"
JAN/SMD IcdIsB
Size Organization Pins Part Number Speed (ns/MHz)
Number (mA @ ns/MHz)
FIFOs 256 64 x 4---Cascadeable 16 CY3341 1.2,2.0MHz 60@2.0MHz
256 64 x 4---Cascadeable 16 CY7C401 10, 15,25 MHz 90@ 15 MHz
256 64 x 4---Cascadeable/OE 16 CY7C403 10, 15,25 MHz 90 @25MHz
320 64 x 5-Cascadeable 18 CY7C402 10,15 MHz 90@ 15 MHz
320 64 x 5-Cascadeable/OE 18 CY7C404 596286846 10, 15,25 MHz 90@ 25 MHz
512 64 x 8-Cascadeable/OE 28S CY7C408 15,25 MHz 120@ 25 MHz
576 64 x 9-Cascadeable 28S CY7C409 15,25 MHz 120@25MHz
4K 512 x 9-Cascadeable 28 CY7C420 tA = 30,40, 65 ns 120/20 @ 30
4K 512 x 9-Cascadeable 28S CY7C421 tA = 30, 40, 65 ns 120/20@ 30
9K lK x 9-Cascadeable 28 CY7C424 tA = 30, 40, 65 ns 120/20@ 30
9K IK x 9-Cascadeable 28S CY7C425 tA = 30,40, 65 ns 120/20 @ 30
18K 2K x 9-Cascadeable 28 CY7C428 596288669 tA = 30,40, 65 ns 120/20 @ 30
18K 2K x 9-Cascadeable 28S CY7C429 596288669 tA = 30, 40, 65 ns 120/20 @ 30
JAN/SMD IcdIsB
Size Organization Pins Part Number Speed (ns)
Number" (mA@ns)
LOGIC 2901-4 Bit Slice 40 CY7C901 596288535 tCLK = 27,32 90@ 27
2901-4 Bit Slice 40 CY290lC 596288535 CSpeed 180 @ 32
4 x 2901-16 Bit Slice 64 CY7C9101 596289517 tCLK = 35,45 85 @ 35
2909-Sequencer 28 CY7C909 tCLK = 30,40 55 @ 30
2911-Sequencer 20 CY7C911 tCLK = 30,40 55 @ 30
2909-Sequencer 28 CY2909A A Speed 90@40
2911-Sequencer 20 CY2911A A Speed 90@40
2910-Controller (17 Word) 40 CY7C91O 596287708 tCLK = 46,51,99 90@46
2910-Controller (9 Word) 40 CY2910A 596287708 A Speed 170@ 51
16Bit Microprogrammed ALU 52 CY7C9116 596288612 65,79,100 166@ IOMHz
16Bit Microprogrammed ALU 68 CY7C9117 65,79, 100 166@ 10 MHz
16 x 16 Multiplier 64 CY7C516 596287686 tMC = 42, 55, 75 110@ 10 MHz
16 x 16 Multiplier 64 CY7C517 596287686 tMC = 42, 55, 75 11O@ 10 MHz
16 x 16 Multiplier/Accumulator 64 CY7C510 596288733 tMC = 55, 65, 75 11O@ 10 MHz
JAN/SMD Icc
Type Organization Pins Part Number Speed (ns)
Number (mA@MHz)
RISC IU SPARC 32 Bit Integer Unit 207 CY7C601 tCYC = 33, 25 MHz TBD
I
FPU Floating Point Unit 144 CY7C602 tCYC = 25 MHz TBD
CMU Cache Controller Memory 207 CY7C604 tCYC = 33, 25 MHz TBD
Management Unit
CMUMP Cache Controller and 207 CY7C605 tCYC = 33, 25 MHz TBD
MultiProcessing Memory
Management Unit
Size Organization Pins Part Number Packages Speed (ns) ICC

(mA@ns)
Modules 256K 16K x 16-SRAM (JEDEC) 40 CYM1610 HD tAA = 35, 45, 50 330 @ 35
1M 128K x 8-SRAM (JEDEC) 32 CYM1420 HD tAA = 45,55 210@ 45
1M 64K x 16-SRAM (JEDEC) 40 CYM1620 HD tAA = 45,55 340@ 45
1M 64Kx 16-SRAM 40 CYM1621 HD tAA = 30, 35, 45 1250 @ 30
2M 64K x 32-SRAM 60 CYMI830 HD tAA = 35, 45, 55 550 @ 35
4M 256K x 16-SRAM 48 CYMI641 HD tAA = 35,45, 55 1760 @ 35
Notes: Package Codes: *(W) = Windowed Package
The Cypress facility at 3901 North First Street in San Jose, CA is D = Ceramic DIP (0) = Opaque Package
DESCcertified for JAN class B production. F = Flatpack 22S stands for 22-pin 300 mil DIP.
MILSTD883C at a minimum. Many of these products are also avail- 24S stands for 24-pin 300 mil DIP.
K = Cerpack 28S stands for 28.pin 300 mil.DIP.
able either to SMDs (Standard Military Drawings) or to JAN slash
sheets. L = LCC
temperature range. All power supplies are VCC = 5V 10%. T = Windowed Cerpack
Modules are available with MIL-STD883C components. These modules W = Windowed CERDIP
are assembled and screened to the proposed JEDEC military processing HD = Hermetic DIP Module
9-4
~RESS Military Ordering Information
l,nlcoNDucroR =============================================================
.DESC SMD (Standardized Military Drawing) Approvals[l]
Cypress [2] Package [3] Product
SMDNumber
Part Number Description Type Description
84036 09JX CY6116-45DMB 24.6 DIP D12 2Kx8SRAM
84036 09KX CY7C128-45KMB 24CP K73 2Kx8SRAM
84036 09LX CY7C128-45DMB 24.3 DIP D14 2Kx8SRAM
84036 09XX CY6117-45LMB 32RLCC L55 2Kx8SRAM
84036 09YX CY7C128-45LMB 24RLCC L53 2Kx8SRAM
84036 093X CY6116-45LMB 28 S LCC L64 2Kx8SRAM
84036 lUX CY6116-55DMB 24.6 DIP D12 2Kx8SRAM
84036 llKX CY7C128-55KMB 24CP K73 2Kx8SRAM
84036 11LX CY7C128-55DMB 24.3 DIP D14 2Kx8SRAM
84036 11XX CY6117-55LMB 32RLCC L55 2Kx8SRAM
84036 11YX CY7CI28-55LMB 24RLCC D14 2Kx8SRAM
84036 113X CY6116-55LMB 28 SLCC L64 2Kx8SRAM
84132 02RX CY7CI67-45DMB 20.3 DIP D6 16Kx 1 SRAM
84132 02SX CY7CI67-45KMB 20CP K71 16Kx 1 SRAM
84132 02YX CY7CI67-45LMB 20RLCC L51 16Kx 1 SRAM
84132 05RX CY7CI67-35DMB 20.3 DIP D6 16Kx 1 SRAM
84132 05SX CY7CI67-35KMB 20CP K71 16Kx 1 SRAM
84132 05YX CY7C167-35LMB 20RLCC L51 16Kx 1 SRAM
5962-85525 05TX CY7CI85-55KMB 28CP K74 8Kx 8 SRAM
5962-85525 05UX CY7CI85-55LMB 28R TLCC L54 8Kx 8 SRAM
5962-85525 05XX CY7CI86-55DMB 28.6 DIP D16 8Kx 8 SRAM
5962-85525 05ZX CY7CI85-55DMB 28.3 DIP D22 8Kx 8 SRAM
5962-85525 06TX CY7CI85-45KMB 28CP K74 8Kx 8 SRAM
5962-85525 06UX CY7CI85-45LMB 28 R TLCC L54 8Kx 8 SRAM
I
5962-85525 06XX CY7CI86-45DMB 28.6 DIP D16 8Kx8SRAM
5962-85525 06ZX CY7CI85-45DMB 28.3 DIP D22 8Kx8SRAM
5962-85525 07TX CY7CI85-35KMB 28CP K74 8Kx8SRAM
5962-85525 07UX CY7CI85-35LMB 28R TLCC L54 8Kx8SRAM
5962-85525 07XX CY7CI86-35DMB 28.6 DIP D16 8Kx8SRAM
5962-85525 07ZX CY7CI85-35DMB 28.3 DIP D22 8Kx8SRAM
5962-86015 01YX CY7CI87-35DMB 22.3 DIP DlO 64Kx 1 SRAM
5962-86015 01ZX CY7CI87-35LMB 22RLCC L52 64Kx 1 SRAM
5962-86015 02YX CY7CI87L-35DMB 22.3 DIP DlO 64Kx 1 SRAM
5962-86015 02ZX CY7CI87L-35LMB 22RLCC L52 64Kx 1 SRAM
5962-86015 03YX CY7CI87-45DMB 22.3 DIP DlO 64Kx 1 SRAM
5962-86015 03ZX CY7CI87-45LMB 22RLCC L52 64Kx 1 SRAM
5962-86015 04YX CY7CI87L-45DMB 22.3 DIP DlO 64Kx 1 SRAM
5962-86015 04ZX CY7CI87L-45LMB 22RLCC L52 64Kx 1 SRAM
5962-86705 12RX CY7CI68-35DMB 20.3 DIP D6 4Kx4SRAM
5962-86705 12XX CY7CI68-35LMB 20RLCC L51 4Kx4SRAM
5962-86859 15KX CY7CI66L-45KMB 24CP K73 16K x4SRAM W/OE
5962-86859 15LX CY7CI66L-45DMB 24.3 DIP D14 16K x4SRAM W/OE
5962-86859 15UX CY7CI66L-45LMB 28RLCC L54 16K x 4SRAM W/OE
5962-86859 15XX CY7CI66L-45LMB 28R TLCC L54 16K x 4 SRAM W10E
5962-86859 16KX CY7CI66-45KMB 24CP K73 16K x 4 SRAM W10E
5962-86859 16LX CY7CI66-45DMB 24.3 DIP D14 16K x 4 SRAM W10E
5962-86859 16UX CY7CI66-45LMB 28RLCC L54 16K x 4 SRAM W10E
5962-86859 16XX CY7CI66-45LMB 28R TLCC L54 16K x 4 SRAM W10E
5962-86859 17KX CY7CI66L-35KMB 24CP K73 16K x 4 SRAM W10E
5962-86859 17LX CY7CI66L-35DMB 24.3 DIP D14 16K x 4 SRAM W10E
9-5
~ Military Ordering Information (Continued) I
~~~~ucroR================================================================1
DESC SMD (Standardized Military Drawing) Approvals[t] (Continued)
SMDNumber
5962-86859 17UX CY7CI66L-35LMB 28RLCC L54 16K x 4 SRAM WIOE
5962-86859 17XX CY7CI66L-35LMB 28R TLCC L54 16K x 4 SRAM WIOE
5962-86859 18KX CY7CI66-35KMB 24CP K73 16K x 4 SRAM WIOE
5962-86859 18LX CY7CI66-35DMB 24.3 DIP D14 16K x 4 SRAM WIOE I
5962-86859 18UX CY7CI66-35LMB 28RLCC L54 16K x 4 SRAM WIOE

5962-86859 18XX CY7C166-35LMB 28R TLCC L54 16K x 4 SRAM WIOE
5962-86859 21KX CY7CI64L-45KMB 24CP K73 16Kx4SRAM
5962-86859 21YX CY7CI64L-45DMB 22.3 DIP DIO 16Kx4SRAM
5962-86859 21ZX CY7CI64L-45LMB 22RLCC L52 16Kx4SRAM
5962-86859 22KX CY7CI64-45KMB 24CP K73 16Kx4SRAM
5962-86859 22YX CY7CI64-45DMB 22.3 DIP DIO 16Kx4SRAM
5962-86859 22ZX CY7CI64-45LMB 22RLCC L52 16Kx4SRAM
5962-86859 23KX CY7CI64L-35KMB 24CP K73 16Kx4SRAM
5962-86859 23YX CY7CI64L-35DMB 22.3 DIP DIO 16Kx4SRAM
5962-86859 23ZX CY7CI64L-35LMB 22RLCC L52 16Kx4SRAM
5962-86859 24KX CY7CI64-35KMB 24CP K73 16Kx4SRAM
5962-86859 24YX CY7CI64-35DMB 22.3 DIP DIO 16Kx4SRAM
5962-86859 24ZX CY7CI64-35LMB 22RLCC L52 16Kx4SRAM
5962-86873 01XX CY7C516-42DMB 64 DIP D30 16 x 16 Multiplier
5962-86873 01YX CY7C516-42LMB 68 S LCC L81 16 x 16 Multiplier
5962-86873 01ZX CY7C516-42GMB 68PGA G68 16 x 16 Multiplier
5962-86873 02YX CY7C516-55LMB 68SLCC L8I 16 x 16 Multiplier
5962-86875 03XX CY7C130-55DMB 48.6 DIP D26 lK x 8 Dual Port SRAM
5962-86875 03YX CY7C130-55LMB 48LCC L68 lK x 8 Dual Port SRAM
5962-86875 03ZX CY7C131-55LMB 52LCC L69 lK x 8 Dual Port SRAM
5962-86875 04XX CY7C130-45DMB 48.6 DIP D26 lK x 8 Dual Port SRAM
5962-86875 04YX CY7C130-45LMB 48LCC L68 lK x 8 Dual Port SRAM
5962-86875 04ZX CY7CI31-45LMB 52LCC L69 lK x 8 Dual Port SRAM
5962-86875 llXX CY7CI40-55DMB 48.6 DIP D26 lK x 8 Dual Port SRAM
5962-86875 llYX CY7CI40-55LMB 48LCC L68 lK x 8 Dual Port SRAM
5962-86875 llZX CY7CI41-55LMB 52LCC L69 lK x 8 Dual Port SRAM
5962-86875 12XX CY7CI40-45DMB 48.6 DIP D26 lK x 8 Dual Port SRAM
5962-86875 12YX CY7CI40-45LMB 48LCC L68 lK x 8 Dual Port SRAM
5962-86875 17XX CY7C130-35DMB 48.6 DIP 026 lK x 8 Dual Port SRAM
5962-86875 18XX CY7CI40-35DMB 48.6 DIP D26 lK x 8 Dual Port SRAM
5962-87515 05KX CY7C261-45TMB 24CP T73 8K x 8 UV EPROM
5962-87515 05LX CY7C261-45WMB 24.3 DIP W14 8K x 8 UV EPROM
5962-87515 053X CY7C261-45QMB 28SLCC Q64 8K x 8 UV EPROM
5962-87515 063X CY7C261-55QMB 28 S LCC Q64 8K x 8 UV EPROM
9-6
I'~ Military Ordering Information (Continued)
l!i_r.~ucrOR ================================
DESC SMD (Standardized Military Drawing) Approvals[l] (Continued)
SMDNumber
5962-87529 01KX CY7C245-45TMB 24CP T73 2K x 8 Registered UV PROM
5962-87529 01LX CY7C245-45WMB 24.3 DIP W14 2K x 8 Registered UV PROM
5962-87529 013X CY7C245-45QMB 28 S LCC Q64 2K x 8 Registered UV PROM
5962-87529 02KX CY7C245-35TMB 24CP T73 2K x 8 Registered UV PROM
5962-87529 02LX CY7C245-35WMB 24.3 DIP W14 2K x 8 Registered UV PROM
5962-87529 023X CY7C245-35QMB 28 S LCC Q64 2K x 8 Registered UV PROM
5962-87539 01KX PALC22VlO-25TMB 24CP T73 24-Pin CMOS UV E PLD
5962-87539 01LX PALC22V10-25WMB 24.3 DIP W14 24-Pin CMOS UV E PLD
5962-87539 013X PALC22VlO-25QMB 28 S LCC Q64 24-Pin CMOS UV E PLD
5962-87539 02LX PALC22VlO-30WMB 24.3 DIP W14 24-Pin CMOS UV E PLD
5962-87539 023X PALC22VlO-3OQMB 28 S LCC Q64 24-Pin CMOS UV E PLD
5962-87539 03LX PALC22VlO-40WMB 24.3 DIP W14 24-Pin CMOS UV E PLD
5962-87539 033X PALC22VlO-4OQMB 28 S LCC Q64 24-Pin CMOS UV E PLD
5962-87650 013X CY7C291-5OQMB 28 S LCC Q64 2K x 8 UV EPROM
5962-87650 033X CY7C291-35QMB 28 S LCC Q64 2K x 8 UV EPROM
5962-87651 OIJX CY7C282-45DMB 24.6 DIP D12 1Kx 8 PROM
5962-87651 01KX CY7C281-45KMB 24CP K73 1Kx 8 PROM
5962-87651 01LX CY7C281-45DMB 24.3 DIP D14 lKx 8 PROM
5962-87651 013X CY7C281-45LMB 28 S LCC L64 1Kx 8 PROM
5962-87686 01UX CY7C517-42FMB 64QFP F78 16 x 16 Multiplier
5962-87686 02YX CY7C517-55LMB 68 SLCC L81 16 x 16 Multiplier
5962-87686 03YX CY7C517-75LMB 68 SLCC L81 16 x 16 Multiplier
5962-87518 01LX CY7C225-30DMB 24.3 DIP D14 512 x 8 Registered PROM
5962-87518 013X CY7C225-30LMB 28 S LCC L64 512 x 8 Registered PROM
5962-87518 023X CY7C225-35LMB 28 SLCC L64 512 x 8 Registered PROM
5962-87518 033X CY7C225-40LMB 28 SLCC L64 512 x 8 Registered PROM
5962-88535 01QX CY7C901-32DMB 40.6 DIP D18 4-Bit Slice
5962-88535 01XX CY7C901-32LMB 44LCC L67 4-Bit Slice
5962-88535 01YX CY7C901-32FMB 42FP F76 4-Bit Slice
5962-88535 02QX CY7C901-27DMB 40.6 DIP D18 4-Bit Slice
5962-88535 02XX CY7C901-27LMB 44LCC L67 4-Bit Slice
5962-88535 02YX CY7C901-27FMB 42FP F76 4-Bit Slice
9-7
~ Military Ordering Information
_n~NDucroR ================================:,
,II (Continued)
DESC SMD (Standardized Military Drawing) Approvals[l] (Continued)

SMDNumber
5962-88587 01VX CY7CI47-45DMB 18.3 DIP D4 4Kx 1 SRAM
5962-88587 01XX CY7CI47-45KMB 18 CP K70 4Kx 1 SRAM
5962-88587 01YX CY7CI47-45LMB 18RLCC L50 4Kx lSRAM
5962-88587 02VX CY7CI47-35DMB 18.3 DIP D4 4Kx 1 SRAM
5962-88587 02XX CY7CI47-35KMB 18 CP K70 4Kx 1 SRAM
5962-88587 02YX CY7CI47-35LMB 18 RLCC L50 4Kx 1 SRAM
5962-88588 01KX CY7CI50-35KMB 24CP K73 lK x 4 SRAM with Reset
5962-88588 01LX CY7CI50-35DMB 24.3 DIP D14 lK x 4 SRAM with Reset
5962-88588 01XX CY7CI50-35LMB 28RLCC L54 lK x 4 SRAM with Reset
5962-88588 02XX CY7C 150-25LMB 28RLCC L54 1K x 4 SRAM with Reset
5962-88588 03XX CY7C150-15LMB 28RLCC L54 lK x 4 SRAM with Reset
5962-88594 02WX CY7C122-35DMB 22.4 DIP D8 256x4SRAM
5962-88594 03WX CY7CI22-25DMB 22.4 DIP D8 256x4SRAM
5962-88612 01XX CY7C9116-99DMB 52.8 DIP D28 16-Bit Microprogrammed ALU
5962-88612 01YX CY7C9116-99FMB 64FP F78 16-Bit Microprogrammed ALU
5962-88612 01UX CY7C9116-99LMB 52S LCC L69 16-Bit Microprogrammed ALU
5962-88612 02UX CY7C9116-75LMB 52S LCC L69 16-Bit Microprogrammed ALU
5962-88612 03UX CY7C9116-65LMB 52 SLCC L69 16-Bit Microprogrammed ALU
5962-88636 01KX CY7C235-40KMB 24CP K73 lK x 8 Registered PROM
5962-88636 01LX CY7C235-40DMB 24.3 DIP D14 lK x 8 Registered PROM
5962-88636 013X CY7C235-40LMB 28 SLCC L64 lK x 8 Registered PROM
5962-88636 02KX CY7C235-30KMB 24CP K73 lK x 8 Registered PROM
5962-88636 02LX CY7C235-30DMB 24.3 DIP D14 lK x 8 Registered PROM
5962-88636 023X CY7C235-30LMB 28 SLCC L64 lK x 8 Registered PROM
5962-88637 01KX PLDC20G 10-40KMB 24CP K73 Generic CMOS PLD
5962-88637 01LX PLDC20G 10-40DMB 24.3 DIP D14 Generic CMOS PLD
5962-88637 013X PLDC20G 10-40LMB 28 S LCC L64 Generic CMOS PLD
5962-88637 02KX PLDC20G 10-30KMB 24CP K73 Generic CMOS PLD
5962-88637 02LX PLDC20G 10-30DMB 24.3 DIP D14 Generic CMOS PLD
5962-88637 023X PLDC20G 1O-30LMB 28 S LCC L64 Generic CMOS PLD
5962-88670 01KX PALC22VI0-25KMB 24CP K73 24-Pin CMOS PLD
5962-88670 01LX PALC22VI0-25DMB 24.3 DIP D14 24-Pin CMOS PLD
5962-88670 013X PALC22VI0-25LMB 28 S LCC L64 24-Pin CMOS PLD
5962-88670 02KX PALC22VI0-30KMB 24CP K73 24-Pin CMOS PLD
5962-88670 03KX PALC22V1 0-40KMB 24CP K73 24-Pin CMOS PLD
9-8
,~ Military Ordering Information (Continued)
.'. . ~~~5NDUCTOR =============================================================
)ESe SMD (Standardized Military Drawing) Approvals[l] (Continued)

SMDNumber
5962-88678 01RX PALCI6L8-40WMB 20.30IP W6 20-Pin CMOS UV E PLO
5962-88678 01XX PALCI6L8-40QMB 208 LCC Q61 20-Pin CMOS UV E PLO
5962-88678 02RX PALCI6R8-40WMB 20.30IP W6 20-Pin CMOS UV E PLO
5962-88678 02XX PALCI6R8-40QMB 20S LCC Q61 20-Pin CMOS UV E PLO
5962-88678 03XX PALCI6R6-40QMB 208 LCC Q61 20-Pin CMOS UV E PLO
5962-88678 08XX PALCI6R4-30QMB 20SLCC Q61 20-Pin CMOS UV E PLO
5962-88678 lORX PALC!6R8-20WMB 20.30IP W6 20-Pin CMOS UV E PLO
5962-88678 lOXX PALCI6R8-20QMB 20S LCC Q61 20-Pin CMOS UV E PLO
5962-88678 llRX PALCI6R6-20WMB 20.30IP W6 20-Pin CMOS UV E PLO
5962-88678 llXX PALCI6R6-20QMB 208 LCC Q61 20-Pin CMOS UV E PLO
5962-88713 01RX PALCI6L8-400MB 20.30IP 06 20-Pin CMOS PLO
5962-88713 01SX PALCI6L8-40KMB 20CP K71 20-Pin CMOS PLO
5962-88713 01XX PALCI6L8-40LMB 20S LCC L61 20-Pin CMOS PLO
5962-88713 02RX PALCI6R8-400MB 20.30IP 06 20-Pin CMOS PLO
I 5962-88713 02SX PALCI6R8-40KMB 20CP K71 20-Pin CMOS PLO
5962-88713 02XX PALCI6R8-40LMB 20S LCC L61 20-Pin CMOS PLO
5962-88713 03SX PALCI6R6-40KMB 20CP K71 20-Pin CMOS PLO
5962-88713 03XX PALCI6R6-40LMB 208 LCC L61 20-Pin CMOS PLO
5962-88713 04XX PALCI6R4-40LMB 20 S LCC L61 20-Pin CMOS PLO
5962-88713 05XX PALCI6L8-30LMB 208 LCC L61 20-Pin CMOS PLO
5962-88713 06XX PALCI6R8-30LMB 20SLCC L61 20-Pin CMOS PLO
5962-88713 07RX P ALCI6R6-300MB 20.30IP 06 20-Pin CMOS PLO
5962-88713 07XX PALCI6R6-30LMB 20S LCC L61 20-Pin CMOS PLO
5962-88713 09XX PALCI6L8-20LMB 20 S LCC L61 20-Pin CMOS PLO
5962-88713 lOSX PALCI6R8-20KMB 20CP K71 20-Pin CMOS PLO
9-9
~PRESS Military Ordering Information (Continued)
.nEMICONDucrOR =================================~
DESC SMD (Standardized Military Drawing) Approvals l1 ] (Continued)
SMDNumber
5962-88713 llRX PALCI6R6-20DMB 20.3 DIP D6 20-Pin CMOS PLD
5962-88713 llSX PALCI6R6-20KMB 20CP K71 20-Pin CMOS PLD
5962-88713 llXX PALCI6R6-20LMB 20SLCC L61 20-Pin CMOS PLD
5962-88713 12RX PALCI6R4-20DMB 20.3 DIP D6 20-Pin CMOS PLD
5962-88713 12SX PALCI6R4-20KMB 20CP K71 20-Pin CMOS PLD
5962-88713 12XX PALCI6R4-20LMB 20S LCC L61 20-Pin CMOS PLD
5962-88735 01KX CY7C245-45KMB 24CP K73 2K x 8 Registered PROM
5962-88735 01LX CY7C245-45DMB 24.3 DIP D14 2K x 8 Registered PROM
5962-88735 013X CY7C245-45LMB 28 S LCC L64 2K x 8 Registered PROM
5962-88735 02KX CY7C245-35KMB 24CP K73 2K x 8 Registered PROM
5962-88735 02LX CY7C245-35DMB 24.3 DIP D14 2K x 8 Registered PROM
5962-88735 023X CY7C245-35LMB 28 SLCC L64 2K x 8 Registered PROM
5962-88735 03KX CY7C245A-35KMB 24CP K73 2K x 8 Registered PROM
5962-88735 03LX CY7C245A-35DMB 24.3 DIP D14 2K x 8 Registered PROM
5962-88735 033X CY7C245A-35LMB 28 S LCC L64 2K x 8 Registered PROM
5962-88735 04KX CY7C245A-25KMB 24CP K73 2K x 8 Registered PROM
5962-88735 04LX CY7C245A-25DMB 24.3 DIP D14 2K x 8 Registered PROM
5962-88735 043X CY7C245A-25LMB 28 S LCC L64 2K x 8 Registered PROM
Notes:
1. SMD approvals are continually being updated. Contact your local Cypress representative for the latest update.
2. Use the SMD part number as the ordering code.
3. Package: 24.3 DIP = 24-pin O.3()()" DIP; 24.6 DIP = 24-pin O.6()()" DIP
28 R LCC = 28 terminal Rectangular LCC; S = Square LCC; TLCC = Thin LCC
24 CP = 24-pin Ceramic flatpack (Configuration 1); FP = Brazed flatpack
PGA = Pin Grid Array
9-10
~ Military Ordering Information (Continued)
.n~b~DucrOR =============================================================
SMD Ordering Information

:962 8XXXX 01 LX
LLEAD FINISH
A Solder Dip
B TinPlate
C Gold
X Don't Care (The letter "X" will not be marked on the device, but will be replaced with
the applicable lead finish designation,)
PACKAGE TYPE (Not a complete list)
V = 18-pin 0.300 DIP J = 24-pin 0.600 DIP
R = 20-pin 0.300 DIP Q = 40-pin 0.600 DIP
S = 20-pin Cerpack K = 24-pin Cerpack
W = 22-pin 0.400 DIP 2 = 20-pin SQ LCC
L = 24-pin 0.300 DIP 3 = 28-pin SQ LCC
X, Y, Z, U, T, N = Non-dedicated package designations and will vary per drawing.
'----DEVICE TYPE
01 = 7CXXX XX ns
02 = 7CXXX XX ns
'-------DRAWING NUMBER
'----------DRAWING PREFIX
5962 = Microcircuits (Pre-1985 drawings do not have this prefix.)
9-11
PRODUCT~~~~~~~~~~~~
INFORMATION
STATIC RAMS ~~~~~==========~
PLD TOOLKIT ~~~~==~~~:::~~:IfII
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
'&-
~================~~
011
PACKAGES~:::~::~~~_
I~ Section Contents
'111"I_r~UcroR =========================================================
BridgeMOS Page Number
BridgeMOS Overview .................................................................................. 10-1

CY8C150 BridgeMOS 1024 x 4 Static RAM Separate I/O .................................. 10-1
CY8C245 BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
CY8C291 BridgeMOS Reprogrammable 2048 x 8 PROM .................................. 10-1
CY8C901 BridgeMOS 4-Bit Slice ....................................................... 10-1
BridgeMOS
CYPRESS
SEMICONDUCTOR
[features Overview
May be driven by CMOS or The BridgeMOSTM product line from BridgeMOS, Cypress has designed an
TTL Cypress Semiconductor provides an output driver which boosts the output
Drives fully loaded TTL electrical bridge between CMOS and voltage sufficiently to drive the inputs
- Inputs switch at 1.SV TTL or TTL and CMOS devices. of a device to greater than 3.85 volts,
BridgeMOS devices may be driven by thus guaranteeing that the input con-
Can drive CMOS to full input either TTL or CMOS devices and in verter will draw minimum power. The
levels turn can drive either fully loaded TTL output drivers source 20 microamps at
- VOL = 0.2V @ IOL = 20 or CMOS to full input levels. As a re- their rated BridgeMOS levels. They
J-LA sult, any combination of TTL and/or will also source and drive normal TTL
- VOH = 0.9 Vcc @ IOH = CMOS may be interfaced to Cypress loads. Therefore, they are capable of
-20 J-LA BridgeMOS products. driving other non-BridgeMOS loads
SRAM, PROM, LOGIC All devices in the BridgeMOS product and normal TTL loads at the same
line are specified at a 2.0V (Vcd time.
2.0V (Vcd Data Retention on
all devices standby mode of operation. This allows Although the TTL to CMOS input
the device to be powered at 2.0 volts converters power down as described
and maintain the integrity of the data above, they switch at TTL levels and
in any volatile storage element. all timing is referenced to 1.5 volts. The
The output drivers in the 7CXXX Cy- device will operate at normal TTL lev-
press products are designed for TTL els with no AC performance degrada-
signals and pull up to 2.4 volts. For tion.
CY8C150 Selection Guide

8C150-15 8C150-25 8C150-35
I
Time (ns) Military 25 35

8C245-35 8C245-45
Maximum Operating
Current (mA)
I Commercial 45 45
I Military 80 80

8C291-35 8C291-50
Maximum Operating
Current (mA)
I Commercial 45 45
1 Military 80 80
10-1
~ Bri.d e. o1,
g M
~~~~NDUcrOR================================================================= __=I
Read ModifyWrite Cycle (min.) in ns Operating Icc (max.) in mA Operating Range Part Number
31 26.5 Commercial 8C901-31
32 31.0 Military 8C901-32
CY8C909/8C911 Selection Guide

8C90930 8C90940
8C911-30 8C91140
Minimum Clock to Output Cycle Time (ns) 30 40
Maximum Operating Current (rnA) 15 15
10-2
PRODUCT
INFORMATION
STATIC RAMS

PROMS
EPLDS

,~.
LOGIC
'.
RISC
MODULES

ECL
MILITARY
BRIDGEMOS
QUICKPRO
I'.
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES
~ Section Contents
;_n~ucrOR ==========================================================
QuickPro
Ilevice Number Description Page Number
:;Y3000 Combined PROM, PLD, and EPROM Programmer .............................. 11-1
CY3000
QuickPro
Features Description
Combined PROM, PLD, and Compatible with the IBM PC QuickPro is a development tool for
EPROM programmer family of computers and plug present and future CMOS PROM and
Programs Cypress CMOS PLDs compatibles PLD devices, and is used within the
and PROMs Programs 24- and 28-pin NMOS IBM PC and compatible environment.
and CMOS EPROMs Older generation bipolar PLDs and
Reads bipolar PLDs and PROMs required special programming
PROMs One long slot and 256K bytes of voltages and current difficult to gener-
memory required ate within the IBM PC.
Easy to use, menu-driven
software Designed for present and future QuickPro is designed for new genera-
New device updates via floppy NMOS and CMOS devices tion of CMOS PLDs and PROMs
disk Optional LCC, PLCC, SOIC which obsolete the older technology,
socket adapters and use a programming technique
IBM-PC plug-in card format,
external ZIF-DIP socket

0095-1
QuickPro is a trademark of Cypress Semiconductor Corporation.
IBM and IBM PC are registered trademarks of International Business Machines Corporation.
ABELTM is a registered trademark of Data I/O Corporation.
CUPLTM is a registered trademark of Assisted Technology.
P ALASMTM is a registered trademark of Monolithic Memories Inc.
Intellec 86 is a trademark of Intel Corporation.
11-1
~ CY3000
~~~~UcrOR==================================================================
Description (Continued) Memory
which is more compatible with low cost programming 256K bytes of total memory is sufficient to operate Quick-
methods. Pro.
QuickPro can also program standard NMOS and CMOS Devices Supported
EPROMs in packages up to 28 pins. And QuickPro is fast;
intelligent programming is used to reduce programming Cypress CMOS PROMs:
time to a minimum. CY7C225, CY7C235, CY7C245, CY7C245A,
CY7C251, CY7C254, CY7C261, CY7C263,
QuickPro is future oriented. Each I/O pin is fully pro- CY7C264, CY7C268, CY7C269, CY7C271,
grammable, allowing the parameters and timing of each CY7C274, CY7C277, CY7C279, CY7C281,
device to be handled via software. As new devices become CY7C282, CY7C291, CY7C291A, CY7C292,
available, they will be supported by QuickPro. Updates are CY7C292A, CY7C293A
managed by a simple exchange of floppy disks.
Cypress CMOS PLDs:
QuickPro includes a comprehensive set of commands to
PALCI6L8, PALCI6R4, PALCI6R6, PALCI6R8,
make programming PLDs and PROMs as easy as possible.
PALC22VI0, PLDC20GI0, PLDC20RAI0, CY7C330,
For PLDs, QuickPro uses the JEDEC standard data for- CY7C331, CY7C332
mat, so present and future logic design tools such as
ABELTM, CUPLTM, and PALASMTM can be used. QuickPro can read 20 and 24 pin Bipolar PLDs, for con-
version to Cypress PLDs.
QuickPro avoids serial download problems from a PC to a
stand-alone programmer. For PROMs, QuickPro reads EPROMs: (NMOS and CMOS)
Intellec 86, Motorola S, TEK and space format files. 2716, 2732, 2732A,2764, 2764A, 27128,27256,27512
QuickPro also reads and writes PROM PCDOS binary
files for use with assemblers and compilers. QuickPro is Ordering Information
low cost. Each workstation can have one, eliminating the
CY3000 QuickPro System ($995.00) contains:
inconvenience of sharing one expensive programmer. All
actions are menu-driven, with complete explanations pro- CY300 1 QuickPro Board
vided on-screen, in clear text. There is no need to look up CY3002 QuickPro Pod
manufacturer's codes in a table.
CY3OO3 QuickPro System Disc
QuickPro Commands Quick Pro Manual
Program device Write disk file Optional QuickPro Package Adaptors Include:
Select device type Verify device CY3004 (CY3006) 28 Lead Square (P)LCC:*
Edit memory Blank check device 7C225, 7C235, 7C245, 7C261, 7C263, 7C264, 7C281,
7C282, 7C291, 7C292, PALC22VI0
Display memory Program security fuse
CY3OO5 (CY3007) 20 Lead Square (P)LCC:
Change PROM Fill memory 16L8, 16R4, 16R6, 16R8
memory location
Convert PLD type CY3008 (CY3OO9) 28 Lead Square (P)LCC:
Read device Summary display 7C269, 7C271, 7C330, 7C331, 7C332
Test PLD device
CY3010 (CY3011) 28 Lead Square (P)LCC:
Read disk file PLDC20GI0
Technical Information CY3012 (CY3013) 32 Lead Rectangular (P)LCC:
7C268
Size
CY3014 28 Pin SOIC:
IBM PC standard full length card. Selectable port address-
es 3OO-31F, 320-33F, 340-35F, 360-37F hex. 7C225, 7C235, 7C245, 7C251, 7C254, 7C261, 7C263,
7C264, 7C269, 7C271, 7C281; 7C282, 7C291, 7C292
Power CY3015 32 Pin SOIC:
+5V 1.0 amp 7C268
+ 12V 1.0 amp (peak) 0.4 amp average CY3016 32 Pin DIP:
-12V 0.05 amp 7C268
Socket Pod CY3017 (CY3018) 28 Lead Square (P)LCC:
7C251,7C254
This is the external socket for connection to the device to
be programmed or read. It provides a 28-pin 300/600 mil *Switch Settings
socket for compatibility with a wide range of devices. Oth- A = PALC22VlO, B = PROMs
er adapters for leadless packages are also available. Five
filter switches are located on the pod for bypass capacitors
according to manufacturers' published programming speci-
fications.
11-2
PRODUCT
INFORMATION
..,.
STATIC RAMS
PROMS

EPLDS

LOGIC

RISC

MODULES
,.
ECL
MILITARY ,.
BRIDGEMOS
QUICKPRO
I'.
QUALITY AND ~~~~~~~~~~~
RELIABILITY
APPLICATION BRIEFS ~~:::::=IJ.~.
I
~ Section Contents
~)r;~~U~R==========================================================
PLDToolKit Page Number
CY3101 Programmable Logic Design Tool ............................................. 12-1
CY3101
CYPRESS
SEMICONDUCTOR PLD ToolKit
Features Description
Logic Assembler, Reverse The Cypress PLD ToolKit is a sophis- compatibility. Command line control is
Assembler ticated programmable logic design tool provided for assembly from a source
for supporting the Cypress family of file to JEDEC file or disassembly of a
Concise easy to use syntax
programmable logic products. The JEDEC file to a source file.
JEDEC read/write capability ToolKit includes the ability to assem- The language contains syntax that al-
Integrated Waveform Logic ble a logic source file, interactively per- lows the management of programmable
Simulator form logic simulation on the result, and logic device macrocells in all possible .
write a standard JEDEC output file for configurations, as well as default condl-
Mouse Driven Simulation Editor programming the PLD. In addition, tions that provide concise source files.
Integrated menu oriented user JEDEC files may be read, simulated In addition, there are language con-
interface and reverse assembled, creating source structs called connectives that provide
files that may be modified and re- expressions for connecting any product
Mouse, keyboard, command line
assembled. term to a macrocell.
interface
The PLD ToolKit runs on any stan- The ToolKit Simulator features wave-
CGA, EGA, VGA, Hercules dard IBM PC, AT, 386 or compati-
support form entry, multiple views and multi-
ble Personal Computer with a CGA,
segment simulatio~ .. The Simu~at~r. .
Supports all Cypress PLDs EGA, VGA or Hercules display. The provides the capablhty to speclfy lmtlal
ToolKit features mouse, keyboard or design conditions, and "View Nodes"
command line interface and supports may be created and used to probe inter-
Logitech and Microsoft mouse nal nodes in the device.
0160-1
IBM and IBM PC, AT are registered trademarks of International Business Machines Corporation.
Logitech is a trademark of Logitech, Inc.
Microsoft@ is a registered trademark of Microsoft Corporation.
12-1
SPil
~ ~~NDUaOR =======================================================================
CY3101
PLD ToolKit Command Menus

Mouse Test Options
If no response, then check Provides the ability Simulation Colors Selects Simulation Colors
mouse installation to test Mouse Interface Menu
I,'
Supports Menu Colors Selects Menu Color Men~
Logitech and Microsoft JEDEC Brief/Annotate Toggles JEDEC Annotat-
ESCAPE ed or Brief Listing
Command Menu G Fuse (JEDEC Security): Toggles Security Fuse
ON/OFF
Assemble Invokes Assembles
Working Directory Path ( ) Sets Path to Working Di-
Disassemble Invokes Disassembler rectory
WriteJEDEC Writes JEDEC Output File ESCAPE
ReadJEDEC Reads JEDEC File into PLD
ToolKit Simulation Colors
Simulate Invokes Simulator Background Allows the selection 01
Input Trace colors for the Simulator
Options Selects Option Menu Display
Information Selects System Information Output Trace
Menu Name of Pin or Node
Clear Resets ToolKit Pin or Node Background
ESCAPE Trace Selected
Information Selected Trace Back-
ground
Release Number Information about the PLD
Release Date ToolKit for registration pur- Memory
poses S12K bytes of total memory is required to operate the PLD
Serial Number
ToolKit.
Free Memory
Screen Size Devices Supported
Colors CYPAL16R8, CYPAL16R6, CYPAL16R4, CYPAL16L8,
CYPAL22VlO, CYPLD20GlO, CY7C330, CY7C331
ESCAPE
CY3l0l Cypress PLD ToolKit Levell contains:
Two S'/4" Floppy Disks
One 3%" Floppy Disk
One Manual
One Registration Card
12-2
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS HI
QUICKPRO
PLDTOOLKIT &II
QUALITY AND
RELIABILITY

APPLICATION BRIEFS
PACKAGES
-
,.
.~ =:;;;;================S==e=c=t=i=O=D==C=O=D==t=e=D=t=S==================
Quality and Reliability Page Number
Quality, Reliability and Process Flows ..................................................................... 13-1
CYPRESS
SEMICONDUCTOR
I Quality, Reliability and Process Flows

4) SMD (Standard Military Drawing) approved product;
Corporate Views on Quality and Military operating range: - 55C to + 125C, electrical-
Reliability ly tested per the applicable Military Drawing.
:ypress believes in product excellence. Excellence can only 5) JAN qualified product; Military operating range:
)e defined by how the users perceive both our product - 55C to + 125C, electrically tested per MIL-M-
luality and reliability. If you, the user, are not satisfied 38510 slash sheet requirements.
with every device that is shipped, then product excellence Category 1, 2, and 3 are available on all products offered
las not been achieved. by Cypress Semiconductor. Category 4 and 5 are offered
Product excellence does not occur by following the indus- on a more limited basis, dependent upon the specific part
:ry norms. It begins by being better than one's competitors, type in question.
with better designs, processes, controls and materials.
fherefore, product quality and reliability are built into ev- Commercial Product Assurance Categories
~ry Cypress product from the start. Commercial grade devices are offered with two different
-Some of the techniques used to insure product excellence classes of product assurance. Every device shipped, as a
are the following: minimum, meets the processing and screening require-
ments of level 1.
Product Reliability starts at the initial design inception.
It is built into every product design from the very start. Levell: For commercial or industrial systems where the
demand for quality and reliability is high, but
Product Quality is built into every step of the manufac- where field service and device replacement can be
turing process through stringent inspections of incom- reasonably accomplished.
ing materials and conformance checks after critical pro-
cess steps. Level 2: For enhanced reliability applications and commer-
cial or industrial systems where maintenance is
Stringent inspections and reliability conformance difficult and/or expensive and reliability is para-
checks are done on finished product to insure the fin- mount.
ished product quality requirements are met.
Devices are upgraded from Level 1 to Level 2 by
Field data test results are encouraged and tracked so
additional testing and a burn-in to MIL-STD-883,
that accelerated testing can be correlated to actual use
experiences. Method 1015.
Table 1 lists the 100% screening and quality conformance
Product Assurance Documents testing performed by Cypress Semiconductor in order to
meet the requirements of these programs.
Cypress Semiconductor uses MIL-STD-883C and MIL-M-
'38510H as baseline documents to determine our Test Military Product Assurance Categories
Methods, Procedures and General Specifications for semi-
Only one standard product assurance category exists for
conductors.
JAN, SMD and Military grade products. Cypress' military
Customers using our Commercial and Industrial grade
product receive the benefit of a military patterned process
flow at no additional charge.
grade devices are processed per MIL-STD-883C using
methods 5004 and 5005 to define our screening and quality
conformance procedures. The processing performed by
II
Cypress results in a product that meets the class B screen-
Product Testing Categories ing requirements as called out by these methods. Every
Five different testing categories are offered by Cypress: device shipped, as a minimum, meets these requirements.
1) Commercial operating range product: OC to + 70C. JAN, SMD and Military grade devices supplied by Cypress
are processed for applications where maintainance is diffi-
2) Industrial operating range product: - 40C to + 85C. cult or expensive and reliability is paramount. Tables 2
3) Military Grade product processed to MIL-STD-883C; through 6 list the screening and quality conformance test-
Military operating range: - 55C to + 125C. ing that is performed in order to meet the processing re-
quirements required by MIL-STD-883C and MIL-M-
38510.
13-1
~ Quality, Reliability and Process Flow
~~~NDUcroR ====================================================================
Table 1. Cypress Commercial and Industrial Product Screening Flows-Components
Product Temperature Ranges
Screen MIL-STD-883 Method

Commercial OC to + 70C; Industrial - 40C to + 85C
Levell Level 2
Plastic Hermetic Plastic Hermetic
VisuallMechanical
Internal Visual 2010 0.4% AQL 100% 0.4% AQL 100%
High Temperature Storage 1008, Cond C Not Performed 100% Not Performed 100%
Temperature Cycle 1010, Cond C Not Performed Not Performed Not Performed Not Performed
Constant Acceleration 2001, Cond E,Yl
Does Not Apply Not Performed Does Not Apply Not Performed
Orientation
Hermeticity Check: 10 14, Cond A & B; Fine Leak LTPD = 5; LTPD = 5;
Does Not Apply Does Not Apply
Fine/Gross Leak Cond C; Gross Leak 77(1,2) 77(1,2)
Burn-in I
Pre-Burn-in Electrical Per Device Specification Does Not Apply Does Not Apply 100% 100%
Bum-in 1015 Does Not Apply Does Not Apply 100%[2] 100%[2]
Post-Burn-In Electrical Per Device Specification Does Not Apply Does Not Apply 100% 100%
Percent Defective 5% (max)[1] 5% (max)[l]
Allowable (PDA)
Final Electrical Per Device Specification
Functional, Switching, 1) At 25C and Power 100%[1] 100%[1]
Supply Extremes Not Performed Not Performed
Dynamic (AC) and
Static (DC) Tests 2) At Hot Temperature and
100% 100% 100% 100%
Power Supply Extremes
Cypress Quality
Lot Acceptance
External Visual 2009 [3] [3] [3] [3]
Final Electrical
Cypress Method 17-00064 [3] [3] [3] [3]
Conformance
Fine & Gross Leak 1014, Cond A & B; Fine Leak LTPD = 5; LTPD = 5;
Conformance Cond C; Gross Leak 77(1,2) 77(1,2)
Table la. Cypress Commercial and Industrial Product Screening Flows-Modules

Product Temperature Ranges
Screen MIL-STD-883 Method Commercial OC to + 70C; Industrial - 40C to + 85C
Levell Level 2
Burn-in
Pre-Burn-in Electrical Per Device Specification Does Not Apply 100%
Bum-in 1015 Does Not Apply 100%
Post-Burn-In Electrical Per Device Specification Does Not Apply 100%
Percent Defective
Does Not Apply 15%
Allowable (PDA)
Final Electrical Per Device Specification
Functional, Switching, 1) At 25C and Power
Not Performed 100%
Dynamic (AC) and Supply Extremes
Static (DC) Tests 2) At Hot Temperature and
100% 100%
Power Supply Extremes
Cypress Quality
Lot Acceptance
External Visual 2009 Per Cypress Module Specification Per Cypress Module Specification
Final Electrical
Cypress Method 17-00064 [3] [3]
Conformance
Fine & Gross Leak 1014; Cond A & B; Fine Leak
Conformance Cond C; Gross Leak
Notes:
1) Electrical Test is performed after bum-in. Results of this are used to 3) Lot acceptance testing is performed on every lot to guarantee 200
determine PDA percentage. PPM average outgoing quality.
2) Bum-in is performed as a standard for 12 hours at lSOC.
13-2
II'~ Quality, Reliability and Process Flows
1~~~~UaDR ==================================================================
Table 2. Cypress JAN/SMD/MiIitary Product Screening Flows
Screening Per Product Temperature Range: - 55C to + 125C

Screen Method 5004 of SMDlMilitary Military Grade
MIL-STD-883C JAN
Product Module
VisuallMechanical
Internal Visual Method 2010, Cond B 100% 100% N/A
Stabilization Bake Method 1008,24 Hrs
100% 100% N/A
(No End Pt. Electricals) Cond C, Minimum
I Temperature Cycling Method 1010, Cond C 100% 100% Optional
I
Constant Acceleration Method 2001, Cond E (Min),

100% 100% N/A
!
Yl Orientation Only
Hermeticity
-Fine Leak Method 1014, Cond A & B 100% 100% N/A
-Gross Leak Method 1014, Cond C 100% 100% N/A
Burn-in
Initial (Pre-Bum-in) Per Applicable Device
100% 100% 100%
Electrical Parameters Specification
Burn-in Test Method 1015, 160 Hrs
at 125C Min or 100% 100% 100%
80 hours at 150C (48 Hours at 125C)
Interim (Post-Bum-in) Per Applicable Device
Electrical Parameters, Specification
100% 100% 100%
Percent Defective Maximum PDA, for
(PDA 10%)
Allowable (PDA) All Lots, 5%
Final Electrical Tests
Static Tests Method 5005, Table 1, 100% Test to 100% Test to 100% Test to
Subgroups 1, 2 and 3 Slash Sheet Applicable Device Applicable
Specification Specification
Dynamic and Switching Method 5005, Table 1, 100% Test to 100% Test to 100% Test to
Tests Subgroups 4, 5, 6, 9, Slash Sheet Applicable Device Applicable
Wand 11 Specification Specification
Functional Tests Method 5005, Table 1, 100% Test to 100% Test to 100% Test to
Subgroups 7 and 8 Slash Sheet Applicable Device Applicable
Specification Specification
Quality Conformance Tests
Group A Method 5005, See Sample Sample Sample
GroupB Table 3-6 for Sample Sample Sample
GroupC Details Sample Sample Sample
GroupD Sample Sample Sample
13-3
~ CYPRESS Quality, Reliability and Process Flows
~~~~u~======================================================~~==~
Table 3. Group A Test Descriptions Group C tests for SMD and Military products are per
Cypress uses an LTPD sampling plan that was developed formed on one device type from one inspection lot repre
senting each technology. Sample tests are performed per,
by the Military to assure product quality. Testing is per-
formed to the subgroups found to be appropriate for the MILSTD883 from each twelve months production of de~
particular device type. All Military products have a Group vices, which is based upon the lot inspection identification
(or date) codes. \
A sample test performed as outlined by the particular
screen flow. End-point electrical tests and parameters are performed
per detailed device specification.
Sub Sample Size/Accept No.
Description
group Sub LTPD
Components Modules Description
group Components Modules
1 Static Tests at 25C 116/0 77/1
2 Static Tests at 1 Steady State Life Test, End
116/0 55/1 5 15/2
Maximum Rated Point Electricals, Method 1005
Operating Temperature Method
2 Temp Cycling 1010
3 Static Tests at 116/0 55/1
Minimum Rated Constant Acceleration 2001
Operating Temperature Hermeticity Fine 1014 N/A 15/2
Visual Inspection M+l
4 Dynamic Tests at 25C 116/0 77/1 End Point Electrical M+I
5 Dynamic Tests at 116/0 55/1
Minimum Rated Table 6. Group D Quality Tests (Package Related)
Operating Temperature Group D tests for JAN product are performed per MIL-
6 Dynamic Tests at 116/0 55/1 M-38510 on each package type from each six months of
Minimum Rated production, based on the lot inspection identification (or
Operating Temperature date) codes.
Group D tests for SMD and Military product are per-
7 Functional Tests at 25C 116/0 77/1
formed per MIL-STD-883 on each package type from each
8 Functional Tests at 116/0 55/1 twelve months of production, based on the lot inspection
Minimum and Maximum identification (or date) codes.
Temperatures End-point electrical tests and parameters are performed
9 Switching Tests at 25C 116/0 77/1 per detailed device specification.
10 Switching Tests at 116/0 55/1 Quantity/Accept #
Maximum Temperature Sub
Description orLTPD
group
11 Switching Tests at 116/0 55/1 Components Modules
Minimum Temperature
1 Physical Dimensions, 15 15/2
Table 4. Group B Quality Tests Method 2016
Group B testing is performed for each inspection lot. An 2 Lead Integrity, Seal: 15 15/2
inspection lot is defined as a group of material of the same Fine & Gross Leak,
device type, package type and lead finish built within a six Methods 2004 & 1014
week seal period and submitted to Group B testing at the 3 Thermal Shock, Temp 15 15/2
same time. Cycling, Moisture
Quality/Accept # or LTPD Resistance, Seal: Fine
Sub
Description & Gross Leak, Visual
group Components Modules Examination, End-Point
2 Resistance to Solvents, 4/0 4/0 Electricals, Methods
Method 2015 1011, 1010, 1004 & 1014
3 Solderability, 10 10/0 4 Mechanical Shock, 15 15/2
Method 2003 Vibration - Variable
Frequency, Constant
5 Bond Strength, 15 N/A Acceleration, Seal:
Method 2011 Fine & Gross Leak,
Visual Examination,
Table 5. Group C Quality Tests End-Point Electricals,
Group C tests for JAN product are performed on one de- Methods 2002, 2007,
vice type from one inspection lot representing each tech- 2001 & 1014
nology. Sample tests are performed per MIL-M-38510
from each three months production of devices, which is
based upon the lot inspection identification (or date) codes.
13-4
I~'~ Quality, Reliability and Process Flows
~~~~ucr~==================================================================
Table 6. Group D Quality Tests (Package Related) Military Product
(Continued)
Product processed per MIL-STD-883C, method 5004
Quantity/Accept # product test flows
Sub-
Description orLTPD Military grade devices electrically tested to:
group
Components Modules - Cypress datasheet specifications
5 Salt Atmosphere, 15 15/2 OR
Seal: Fine & Gross - SMD (Standard Military Drawing) devices electrical-
Leak, Visual Exam- ly tested to military drawing specifications
ination, Methods
1009 & 1014 OR
6 Internal Water-Vapor - JAN devices electrically tested to slash sheet specifi-
3/0 or 5/1 N/A
cations
Content; 5000 ppm
maximum @ 100C. All devices supplied in Hermetic packages
Method 1018 Quality conformance assured: Method 5005, Groups A,
7 Adhesion of Lead 15 15/2 B, C and D performed as part of the standard process
Finish,[l] flow
Method 2025 Bum-in performed on all devices
8 Lid Torque, 5/0 N/A - Cypress detailed circuit specification for non-JAN de-
Method 2024[2] vices
Notes: OR
I) Does not apply to leadless chip carriers.
- Slash sheet requirements for JAN products
2) Applies only to packages with glass seals.
AC, DC, Functionally and Dynamically tested at 25C
Product Screening Summary as well as temperature and power supply extremes on
100% of the product in every lot
Commercial and Industrial Product JAN product manufactured in a DESC certified facility
Screened to either Level 1 or Level 2 product assurance Ordering Information
flows
JAN Product:
Hermetic and Molded packages available
Order per Military document
Incoming Mechanical and Electrical performance guar-
anteed: Marked per Military document
Ex: JM3851O/28901BVA
- 0.1 % AQL Electrical Sample test performed on every
lot prior to shipment SMD Product:
- 0.65% AQL External Visual Sample inspection Order per Military document
Electrically tested to Cypress datasheet Marked per Military document
Ordering Information Ex: 5962-8684601EA
Product Assurance Grade: Level 1 Military Grade Product:
Order Standard Cypress part number Order per Cypress standard Military part number
Parts marked the same as ordered part number Marked the same as ordered part number
Ex: CY7CI22-15PC, PALC22VIO-25PI Ex: CY7C122-25DMB
Product Assurance Grade: Level 2
Military Modules
Bum-in performed on all devices to Cypress detailed cir-
cuit specification
Add "B" Suffix to Cypress standard part number when
ordering to designate Bum-in option
Military Temperature Grade Modules are designated
with a 'M' suffix only. These modules are screened to
standard combined flows and tested at both Military
temperature extremes.
III
Parts marked the same as ordered part number
MIL-883C Equivalent Modules are processed to pro-
Ex: CY7C122-15PCB, PALC22VlO-25PIB posed JEDEC standard flows for MIL-883C compliant
modules. All 883C equivalent modules are fully compli-
ant 883C components.
13-5
~ Quality, Reliability and Process FlOw~
~~~UaoR=================================================================='
Product Quality Assurance Flow-Components
AREA PROCESS T PROCESS DETAILS
QC INCOMING MATERIALS ALL INCOMING MATERIALS ARE INSPECTED TO DOCUMENTED PROCEDURES COVERING
INSPECTION THE HANDLING, INSPECTION, STORAGE, AND RELEASE OF RAW MATERIALS USED IN
THE MANUFACTURE OF CYPRESS PRODUCTS. MATERIALS INSPECTED ARE: WAFERS,
MASKS, LEADFRAMES, CERAMIC PACKAGES AND/OR PIECE PARTS, MOLDING
COMPOUNDS, GASES, CHEMICALS, ETC.
FAB DIFFUSION / ION SHEET RESISTANCE, IMPLANT DOSE, SPECIES AND CV CHARACTERISTICS ARE
IMPLANTATION MEASURED FOR ALL CRITICAL IMPLANTS AND ON EVERY PRODUCT RUN. TEST
WAFERS MAY BE USED TO COLLECT THIS DATA INSTEAD OF ACTUAL PRODUCTION
WAFERS. IF THIS IS DONE, THEY ARE PROCESSED WITH THE STANDARD PRODUCT
PRIOR TO COLLECTING SPECIFIC DATA. THIS ASSURES ACCURATE CORRELATION
BETWEEN THE ACTUAL PRODUCT AND THE WAFERS USED TO MONITOR IMPLANTATION.
FAB OXIDATION SAMPLE WAFERS AND SAMPLE SITES ARE INSPECTED ON EACH RUN FROM VARIOUS
POSITIONS OF THE FURNACE LOAD TO INSPECT FOR OXIDE THICKNESS. AUTOMATED
EQUIPMENT IS USED TO MONITOR PIN HOLE COUNTS FOR VARIOUS OXIDATIONS IN
THE PROCESS. IN ADDITION, AN APPEARANCE INSPECTION IS PERFORMED BY THE
OPERATOR TO FURTHER MONITOR THE OXIDATION PROCESS.
FAB PHOTOLITHOGRAPHY / APPEARANCE OF RESIST IS CHECKED BY THE OPERATOR AFTER THE SPIN OPERATION.
ETCHING ALSO, AFTER THE FILM IS DEVELOPED, BOTH DIMENSIONS AND APPEARANCE ARE
CHECKED BY THE OPERATOR ON A SAMPLE OF WAFERS AND LOCATIONS UPON EACH
WAFER. FINAL CD'S AND ALIGNMENT ARE ALSO SAMPLE INSPECTED ON SEVERAL
WAFERS AND SITES ON EACH WAFER ON EVERY PRODUCT RUN.
FAB METALIZATION FILM THICKNESS IS MONITORED ON EVERY RUN. STEP COVERAGE CROSS-SECTIONS
ARE PERFORMED ON A PERIODIC BASIS TO INSURE COVERAGE.
FAB PASSIVATION AN OUTGOING VISUAL INSPECTION IS PERFORMED ON 100% OF THE WAFERS IN A

LOT TO INSPECT FOR SCRATCHES, PARTICLES, BUBBLES, ETC. FILM THICKNESS IS
VERIFIED ON A SAMPLE OF WAFERS AND LOCATIONS WITHIN EACH GIVEN WAFER ON
EACH RUN. PINHOLES ARE MONITORED ON A SAMPLE BASIS WEEKLY.
FAB QC VISUAL OF
WAFERS
FAB E-TEST SAMPLE ELECTRICAL TEST IS PERFORMED FOR FINAL PROCESS ELECTRICAL
CHARACTERISITICS ON EVERY RUN.
FAB QC MONITOR OF WEEKLY REVIEW OF ALL DATA TRENDS; RUNNING AVERAGES, MINIMUMS,
E-TEST DATA MAXIMUMS, ETC. ARE REVIEWED WITH PROCESS CONTROL MANAGER
TEST WAFER PROBE / SORT VERIFY FUNCTIONALITY, ELECTRICAL

CHARACTERISTICS, STRESS TEST DEVICES
TEST QC CHECK PASS/FAIL LOT BASED ON YIELD,

PROBING AND CORRECT PROBE PLACEMENT
ELECTRICAL TEST
RESULTS TO ASSEMBLY
AND TEST 0032-1
(Continued)
13-6
~,~ Quality, Reliability and Process Flows
11!\_r~NDucroR ============================================================
Product Quality Assurance Flow-Components (Continued)
PLASTIC HERMETIC
ASSEMBLY ASSEMBLY
FLOW FLOW
WAFER PREP / MOUNT / SAW

INSPECT FOR ACCURATE SAWING OF
SCRIBELINE AND 100% SAW THRU
PERIODIC QC MONITOR - WAFER SAW

PERFORM MONITOR OF MOUNTING, SAWING
AND POST SAW CLEAN OPERATIONS
DIE VISUAL INSPECTION

INSPECT DIE PER CYPRESS EQUIVALENT TO
MIL-STD-883, METHOD 2010
QC VISUAL LOT ACCEPTANCE

SAMPLE INSPECT DIE; 1.0% AQL
DIE ATTACH
ATTACH PER CYPRESS DETAILED SPECIFICATION
QC PROCESS MONITOR
INSPECT FOR DIE POSITION, QUALITY AND
UNIFORMITY OF DIE ATTACH AND ATTACHMENT
STRENGTH, MIL-STD-883, METHOD 2010, CRITERIA
WIRE BOND
BOND PER CYPRESS DETAILED SPECIFICATION
QC PROCESS MONITOR - WIRE BONDING

MONITOR BOND STRENGTH AND
FAILURE MODE
INTERNAL VISUAL INSPECTION

LOW POWER (30X) INSPECTION OF WORKMANSHIP
MIL-STD-883, METHOD 2010, CRITERIA
QC LOT ACCEPTANCE
SAMPLE INSPECT LOT TO VERIFY WORKMANSHIP,
MIL-STD-883, METHOD 2010, CRITERIA; 0.4% AQL
DIE COAT
COATING APPLIED TO SELECTED PRODUCTS
MOLD / ENCAPSULATE PLASTIC DEVICES
SEAL HERMETIC DEVICES
PERIODIC QC MONITOR, LID-TORQUE

SHEAR STRENGTH OF GLASS-FRIT
SEAL TESTED TO MIL-STD-883, METHOD 2024
0032-2
(Continued)
13-7
~ Quality, Reliability and Process Flow~
~~~U~================================================================
Product Quality Assurance Flow-Components (Continued)
POST MOLD CURE

PER CYPRESS METHOD
FOR MOLDING COMPOUND STABILIZATION BAKE
METHOD 1008, COND C
TEMPERATURE CYCLE(l)
METHOD 1010, COND C
CENTRIFUGE( 1)
METHOD 2001, COND E, Y1 ORIENTATION
FINE AND GROSS LEAK TEST(2)

PER METHODS EQUIVALENT TO METHOD
1014, COND A OR B; FINE LEAK
METHOD 1014, COND C; GROSS LEAK
LEAD TRIM / FORM

LEAD TRIM AND FORM FOR PLASTIC DEVICES, LEAD
TRIM FOR HERMETIC DEVICES (WHERE APPLICABLE)
LOT ID - PLASTIC DEVICES

MARK WAFER LOT ON DEVICES; LASER MARK ON
PLASTIC DEVICES
LEAD PREP / FINISH (SOLDER DIP)

PREPARE LEADS FOR SOLDER DIP, SOLDER DIP DEVICES
AND INSPECT FOR UNIFORM SOLDER COVERAGE
QC PROCESS MONITOR
VERIFY WORKMANSHIP AND SOLDER COVERAGE
LOT ID - HERMETIC DEVICES

MARK WAFER LOT ON DEVICES
FINE AND GROSS LEAK SAMPLE TESr<2)

METHOD 1014, COND A OR B; FINE LEAK
METHOD 1014, COND C; GROSS LEAK
EXTERNAL VISUAL INSPECTION

INSPECT FOR WORKMANSHIP, CONSTRUCTION, CRACKED
OR BROKEN DEVICES, BENT LEADS, CRAZING, CASTELLATION
ALIGNMENT AND SOLDER COVERAGE.
MIL-STD-883, METHOD 2009
0032-3
(Continued)
13-8
~~ Quality, Reliability and Process Flows
.:_Ts~NDUCI'OR =============================
Product Quality Assurance Fiow-Components (Continued)
OPTIONAL BURNIN PROCESSING FOR LEVEL 2

(STANDARD FOR JAN/MILITARY DEVICES)
o I
I
PRE - BURNIN ELECTRICAL TEST
o I
I
o I
I
BURNIN: METHOD 1015
o
I
o
I I
o
I I
QC MONITOR - BURNIN DOCUMENTS/RESULTS

I I
I I
o I
INTERIM (POST-BURNIN) ELECTRICALS

PER APPLICABLE DEVICE SPECIFICATION
o
I
I
I
I I
I I
I I
~ ~
QC INSPECTION
PDA VERIFIED WITHIN LIMITS
I I
I
:.
FINAL ELECTRICAL TEST
100% TEST LOT; DC. AC. FUNCTIONAL AND DYNAMIC
TESTS PERFORMED PER APPLICABLE DEVICE SPECIFICATION
FINAL DEVICE MARKING
FINAL VISUAL INSPECTION

INSPECT FOR BENT LEADS. MARKING.
SOLDER COVERAGE. ETC.
IQC LOT ACCEPTANCE I

VIS L SAMPLE INSPECTION
METHOD 2009 -0.65% AQL
ELECTRICAL SAMPLE TEST

TO GUARANTEE 200 PPM
INSPECTION - PRE-SHIPMENT
CONFIRM PART TYPE. COUNT. PACKAGE. CHECK
FOR COMPLETENESS OF PROCESSING
REQUIREMENTS. CONFIRM SUPPORTING
DOCUMENTATION IS SENT. IF REQUIRED
PACK / SHIP ORDER
0032-4
Key
o PRODUCTION PROCESS
o TEST / INSPECTION DI
IQI PRODUCTION PROCESS AND TEST INSPECTION
o QC SAMPLE GATE AND INSPECTION

0032-5
Notes:
1. Temp Cycle and Centrifuge performed per Applicable Product Screening Flow.
2. JAN/SMD/Military grade products are 100% Fine and Gross Leak tested and sample tested after wafer lot J.D. Commercial grade devices received
sample test only. Sample size is per Commercial Product Screening Flow.
13-9
~ Quality, Reliability and Process Flow
~~~~UaoR================================================================~
Product Quality Assurance Flow-Modules
ALL INCOMING MATERIALS ARE INSPECTED TO DOCUMENTED PRO-
INCOMING MATERIALS CEDURES COVERING THE HANDLING, INSPECTION, STORAGE, AND
INSPECTION RELEASE Of RAW MATERIALS USED IN THE MANUfACTURE Of CYPRESS
PRODUCTS. MATERIALS INSPECTED ARE: SUBSTRATES, ACTIVE DEVICE
PACKAGES, CHIP CAPACITORS, LEAD fRAMES, SOLDER PASTE, INKS,
CHEMICALS, ETC.
KIT PICKED
COMPLIANCE VERifiED, DOCUMENTED,
AND TRACEABILITY ESTABLISHED
CLEAN
PREASSEMBlEY CLEANING Of
COMPONENTS
SOLDER PASTE DEPOSITION

SCREEN PRINTED AND/OR DISPENSED
PER DETAilED SPECifiCATION
COMPONENT PLACEMENT
ROBOTIC AND/OR MANUAL PER DETAilED
SPECifiCATION
SOLDER REflOW
MICROPROCESSOR CONTROllED INfRARED
REflOW OVEN
CLEAN
DATA lOGGING
(OPTIONAL)
0 --
flUX REMOVAL BY VAPOR PHASE PER

DETAilED SPECifiCATION
DOUBLE SIDED ASSEMBLY

2-SIDED REPEAT PROCESS fOR SIDE 2 2-SIDED
--., r --
AQl VISUAL 100% VISUAL
l-SIDED
0I
SOLDER PASTE DEPOSITION
0 I
1-SIDED
[]
I
COMPONENT PLACEMENT []
I
0 I
SOLDER REflOW
0 I
0 CLEAN
0
I
--! -- <> AQl VISUAL

INSPECT 100% VISUAL 0 --! -- I
ELECTRICAL TEST
(PRE-BURNIN TEST)
0032-6
13-10
I~~ Quality, Reliability and Process Flows
~_r~NDucroR ==============================
Product Quality Assurance Flow-Modules (Continued)
OPTIONAL BURNIN PROCESSING FOR

LEVEL 2 (STANDARD FOR MIL DEVICES)
,,
o,,,
BURNIN: METHOD 1015
o,,
QC MONITOR - BURN IN DOCUMENTS/RESULTS
,
o,, INTERIM (POST - BURN IN) ELECTRICALS
PER APPLICABLE DEVICE SPECIFICATION
____ J--O QC INSPECTION

PDA VERIFIED
WITHIN LIMITS
FINAL ELECTRICAL TEST
100% TEST LOT; DC, AC, FUNCTIONAL AND
DYNAMIC TESTS PERFORMED PER APPLICABLE
DEVICE SPECIFICATION
FINAL DEVICE MARKING
FINAL VISUAL INSPECTION

CONFIRM PART TYPE, COUNT, PACKAGE, CHECK
FOR COMPLETENESS OF PROCESSING RE-
QUIREMENTS, CONFIRM SUPPORTING DOCU-
MENTATION IS SENT, IF REQUIRED
QA ELECTRICAL TEST
(ROOM TEMP)
INSPECTION - PRE-SHIPMENT
PACK/SHIP ORDER
0032-7
Key:
o PRODUCTION PROCESS
o TEST / INSPECTION
IQI PRODUCTION PROCESS AND TEST INSPECTION
o QC SAMPLE GATE AND INSPECTION

0032-5
II
13-11
~ Quality, Reliability and Process Flows
~~~U~==================================================================
Reliability Monitor Program
The Reliability Monitor Program is a documented Cypress Cypress customers. The Reliability Monitor Program is de
procedure that is described in Cypress specification signed to monitor key products within each generic process
# 25-00008 which is available to Cypress customers upon family. This procedure requires that detailed failure analy
request. This specification describes a procedure that pro- sis be performed on all test rejects and the corrective ac-
vides for periodic reliability monitors to insure that all tions be taken as indicated by the analysis. A summary oi
Cypress products comply with established goals for reli- the Reliability Monitor Program test and sampling plan is
ability improvement and to minimize reliability risks for shown below.
Reliability Monitor Program Sampling Plan

Sample Frequency[l]
Test Description Duration
Size
Early Failure Rate (EFR)
150CHTOL 12 Hours 200 Weekly
125CHTOL 80 Hours 200 Bi-weekly
Latent Failure Rate (LFR)
150CHTOL 1000 Hours 200 Monthly
125CHTOL 2000 Hours 200 Monthly
High Temp Steady State Life (HTSSL)
150CHTOL 168 Hours 100 Weekly
150C HTOL (llot/quarter extended) 1000 Hours 100 Quarterly
Plastic Package Data Retention (DRET)
165C Bake 1000 Hours 55 Bi-weekly
Hermetic Package Data Retention (DRET)
250C Bake 1000 Hours 55 Monthly
Pressure Cooker (PCT)
121C/l00% R.H. 288 Hours 55 Weekly
Pre-conditioned Temperature-Humidity Life (PCTH)
96 Hrs. PCT + Biased 85C/85% R.H. 1000 Hours 55 Every 6 Weeks
High-Acceleration Saturation (HAST)
Biased 121C/85% R.H. 200 Hours 55 Every 6 Weeks
Temperature Cycle (TIC)
- 65C to + 150C 15 Cycles 55 Weekly
-65C to + 150C (llot/quarter extended) 1000 Cycles 55 Quarterly
Note:
1) Maximum period between samples is listed. More frequent sampling may occur.
13-12
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO

I,.
PLDTOOLKIT III
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
g
PACKAGES FLW
I
5?l Section Contents
~NDUcrOR ;;;;;;;:=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=::=:==
~pplication Briefs Page Number
:AM Input and Output Characteristics .................................................................... 14-1
'ower Characteristics of Cypress Products ................................................................. 14-8
'in-Out Compatibility Considerations ofSRAMs and PROMs ................................................ 14-15
CYPRESS
SEMICONDUCTOR
Application Briefs
RAM Input Output Characteristics
Introduction to Cypress RAMs PRODUCT DESCRIPTION
Cypress Semiconductor Corporation uses a speed opti- The five parts in Figure 1 constitute three basic devices of
mized CMOS technology to manufacture high speed static 64, 1024 and 4096 bits respectively. The 7C189 and 7C190
RAMs which meet and exceed the performance of compet- feature inverting and non-inverting outputs respectively in
itive bipolar devices while consuming significantly less a 16 x 4 bit organization. Four address lines address the 16
power and providing superior reliability characteristics. words, which are written to and read from over separate
While providing identical functionality, these devices ex- input and output lines. Both of these 64 bit devices have
hibit slightly differing input and output characteristics separate active LOW select and write enable signals. The
which provide the designer opportunities to improve over- 256 x 4 7C122 is packaged in a 22 pin DIP, and features
all system performance. The balance of this application separate input and output lines, both active LOW and ac-
- note describes the devices, their functionality and specifi- tive HIGH select lines, eight address lines, an active LOW
cally their I/O characteristics. output enable, and an active LOW write enable. Both the
~----------~~Oo r-------------<l~oo
01
Ao Ao
00 00
A, A,
0, 0,
Az Oz Az Oz
03 03
A3 A3
CI cs
m
0027-1 0027-2
7C189 7C190
Figure 1. RAM Block Diagrams
14-1
~ RAM Input/Output Characteristics
~~NDUcrOR =======================================================================
A9' 1/00
As
A7 1/01
As
1/02
A5
A4
1/03
cs
0027-3
WE
0027-4
7C122 7C148/9
Figure 1. RAM Block Diagrams (Continued)
7C148 and 7C149 are organized 1024 x 4 bits and feature VIR values of 0.8 and 2.0V referenced above are valid. In
common pins for the input and output of data. Both parts consideration of noise margin however, driving the input of
have 10 address lines, a single active LOW chip select and the next stage to the required VIL or VIR is not sufficient.
an active LOW write enable. The 7C148 features automatic Noise margins of 200 to 400 mV are considered more than
power down whenever the device is not selected, while the adequate, and therefore the VOH we deal with is 2.4V while
7C149 has a high speed, 15 ns, chip select for applications the VOL is O.4V, providing a noise margin of 400 mY.
which do not require power control. This family of high Since the driven node consists of both a resistive and a
speed static RAMs is available with access times of 15 to capacitive component, output characteristics are specified
45 ns with power in the 300 to 500 mW range. They are such that the output driver is capable of sinking IOL at the
designed from a common core approach, and share the specified VOL, and capable of sourcing lOR at VOR. Since
same memory cell, input structures and many other char- the values of 10L and lOR differ depending on the device,
acteristics. The outputs are similar, with the exception of these values are shown in Table 1. Outputs have one other
output drive, and the common I/O optimization for the characteristic that we need to be concerned with, Output
7C148 and 7C149. For more detailed information on these Short Circuit Current or los. This is the maximum current
products, refer to the available data sheets. that the output will source when driving a logic "I" into
Vss. We need to be concerned for two reasons. First, the
GENERIC I/O CHARACfERISTICS output should be capable of supplying this current for some
Input and output characteristics fall generally into two cat- reasonable period of time without damage, and second, this
egories, when the area of operation falls within the normal is the current that charges the capacitive load when switch-
limits of Vee and Vss plus or minus approximately ing the output from a "0" to a "1" and will control the
600 mY, and abnormal circumstances, when these limits output rise time.
are exceeded. Inputs under normal operating conditions Since memories such as these are often tied together, we
are voltages that switch between logic "0" and logic "1". are also concerned about the output characteristics of the
We will consider operation in a positive true environment devices when they are. deselected. All of the devices in this
and therefore a logic "I" is more positive than a logic "0". family feature three state outputs such that in addition to
The I/O characteristics of the devices we are concerned their active conditions when selected, when deselected, the
with are what is considered to be TTL compatible. There- outputs are in a high impedance condition which does not
fore a logic "I" is 2.0V, while a logic "0" is 0.8V. The source or sink any current. In this condition, as long as the
input of a device must be driven greater than 2.0V, not to input is driven in its normal operating mode, it appears as
exceed Vee + 0.6V to be considered a logic "I" and, to an open, with less than 10 IJ-A of leakage. Thus to any
less than 0.8V, but not less than Vss - 0.6V, to be consid- other device driving this node, it is non-existent.
ered a logic "0".
Output characteristics represent a signal that will drive the
input of the next device in the system. Since the levels we
are dealing with are TTL, we may assume that the VIL and
14-2
~~RFSS RAM Input/Output Characteristics
_'~ICONDUcrOR ======================================================================
I
,rECHNOLOGY DEPENDENCIES AND I/O Parameters

,IENEFITS
CMOS/NMOS/BIPOLAR INPUT
lome of the products in this application note were original-
V produced in a BIPOLAR technology, some have since CHARACTERISTICS
leen re-engineered in NMOS technology and Cypress has Although NMOS, CMOS and BIPOLAR technologies dif-
'.ow produced them in a speed optimized CMOS technolo- fer widely, the I/O characteristics tend to fall into two
iy. There are both technology dependencies and benefits areas. The traditional characteristics are the TTL deriva-
~lative to the design of input and output structures that tives that have been covered above, and are documented in
,Ire associated with each technology. The designer who Table 1. With the exception of the differences in input im-
lses these products should be knowledgeable of these char- pedance between MOS and BIPOLAR devices all three
:cteristics and how they can benefit or impede a design technologies are used to produce TTL compatible prod-
!ffort. One of the most obvious is that both NMOS and ucts. The second camp is the true CMOS interface where
I~MOS device inputs are high impedance, with less than 10 signals swing from Vss to Vee. These interface specifica-
LA of input leakage. Bipolar devices, however, require that tions define a "1" as greater than Vee - 1. 5V and a "0" as
he driver of an input sink current when driving to VIL, but less than Vss + 1.5V. In addition, loads are primarily
.ppear as high impedance at VIH levels. This is due to the capacitive. Only devices produced in a CMOS technology
act that the input of a bipolar device is the emitter of a are capable of behaving in this manner. CMOS devices can,
lipolar NPN type device with its base biased positive. The however, handle both TTL and CMOS inputs. Devices
lias is what establishes the point at which the input chang- such as the ones described in this application note have
:s from requiring current to be sourced to high impedance input characteristics depicted in Figure 2.
~nd is 1.5V. This switching level is the reason that AC
neasurements are done at the 1.5V level. Although NMOS
~nd CMOS device inputs do not change from low to high 3.5
mpedance, great care is taken to balance their switching
hreshold at 1.5V. To a system designer this allows fanout 3.0
o consider only capacitive loading with MOS devices
vhile bipolar has both a capacitive and DC component. 2.5
-rhe other input characteristic which differs from bipolar to
vlOS is the clamp diode structure. This structure exists in
E
2.0 r ---- .......
')oth MOS and bipolar, however in MOS that uses BIAS I
/ \
,
u 1.5
CTENERATOR techniques, all high speed MOS devices, ::
the diode does not become forward biased until the input
~oes more negative than the substrate bias generator plus
1.0
I
/ \
~ne diode drop. Since the bias generator is usually about 0.5 J
- 3V this has the effect of removing the clamping effect.
/
o
0.0 1.0 2.0 3.0
INPUT VOLTAGE - V '"

4.0 5.0 6.0
0027-5
Figure 2. Input Voltage vs. Current
Table 1. DC Parameters
7C122 7Cl48/9 7C189/90
VOH Output High Voltage Vee = Min., IOH = - 5.2 rnA 2.4 2.4 2.4 V
VOL Output Low Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 V
VIH Input High Voltage 2.1 Vee 2.0 Vee 2.0 Vee V
VIL Input Low Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 V
IlL Input Low Current Vee = Max., VIN = Vss 10 10 p.A 10

IIH Input High Current Vee = Max., VIN = Vee 10 10 10 p.A
'IOFF Output Current (High Z) VOL < VOUT < VOH, TA = Max. -10 +10 -10 +10 -10 +10 p.A
Output Short Vee = Max.,OC < TA < 70C -70 -90 -275 rnA
lOS Circuit Current VOUT = VSS, -55C < TA < 125C -80 -90 -350 rnA
14-3
~ RAM Input/Output Characteristic!
~~~NDUcrOR====================================================================
When operated in the TTL range, they perform normally. than normal, the change will occur more quickly, allowini
Operated in full CMOS mode, an additional benefit of a more accurate determination of entry into the high im
power savings is realized as the current consumed in the pedance state.
input converter decreases as the input voltage rises above
3.OV, or falls below 1.5V. Since the input signal is in the 1.5 SWITCHING THRESHOLD VARIATION~
to 3.0V range only when transitioning between logic states, Switching threshold variations along with input rise anc
the power savings in a large array with true CMOS inputs fall times can have an effect on the performance of an:
can be significant. With input signals on over half of the device. Input rise and fall times are under the control of tb
pins of a device, significant savings in a large system can be designer, and are primarily affected by capacitive loading
realized by using CMOS input voltage swings even in TTL the driver and bus termination techniques. SwitchinJ
systems. threshold is affected by process variations, changes in V c(
and temperature. Compensation of these va:iables is thl
Switching Characteristics territory of the manufacturer, both at the deSIgn stage ani
the manufacturing of the device. Combined threshold shift l
Although this application note does not directly deal with

over full military temperature ranges and process varia
the AC characteristics of high speed RAMs, the input and
output characteristics of these devices have a great deal to tions average less than 100 mY. This translates directly t~
VIL and VIH variations which track well within the noisl
do with the actual AC specifications. Conventionally, all
margins of normal system design particularly since tht
AC measurements associated with high speed devices are
VOL and VOH changes track to the same 100 mY. I
done at 1.5V and assume a maximum rise and fall time.
This eliminates the variations associated with the various
configurations that the device will be used in (as a figure of Input Protection Mechanisms
merit when testing the device) but, does not mean that the
designer can ignore these influences when designing a sys- THE ELECTROSTATIC DISCHARGE
tem. Maximum rise and fall time is usually found in the PHENOMENON
notes included on every data sheet. For the products re- Because of their extremely high input impedance and rela
ferred to in this application note, a 10 ns maximum rise tively low (approximately 30Y) breakdown voltage, MO~
and fall time is specified for all devices with access times devices have always suffered from destruction caused b~
equal to or greater than 25 ns and a 5 ns maximum rise and ESD (Electro Static Discharge). This has caused two ac
fall time for all devices with access times less than 25 ns. tions. First, major efforts to design input protection circuit~
The AC load and its Thevenin equivalent in Figure 3 repre- without impeding performance has resulted in MOS de.
sent the resistive and capacitive components of load which vices that are now superior to bipolar devices. Second, can
the devices are specified to drive. With either of these in handling semiconductors is now common practice. In;
loads the device will be required to source or sink its rated terestingly enough, bipolar products that once did not suf
outP~t current at its specified output voltage. The capaci- fer from ESD have now suddenly become sensitive to the
tance stresses the ability of the device output to source or phenomenon, primarily because new processing technologj
sink sufficient current to slew the outputs at a high enough involving shallow junctions is in itself sensitive. MOS de
rate to meet the AC specifications. The high impedance vices are in many cases now superior to bipolar products
load is a convenience to testing when trying to determine A sampling of competitive BIPOLAR and NMOS 64 bit
how rapidly the output enters a high impedance condition. IK bit and 4K bit products reveals breakdown voltages a!
Once the output enters a high impedance mode, the resis- low as 150V to greater than 2001V magnitudes. Th(
tive divider will charge the capacitance until equilibrium is circuit in Figure 4 is used to protect Cypress product!
reached. Allowing for noise margin, testing for a 500 m V against ESD. It consists of tW? thick oxide ~eld ~ransist(:m
change is normal. By using a smaller capacitance wrapped around an input reSIstor and a thm OXIde deVIC(
ACLoad High Impedance Load
R14700 R14700
5V 0----"'"""""'--, Thevenin Equivalent
5Vo-------JV~_,
OUTPUT O---~t--------t OUTPUT O----t---------.

1520
OUTPUT ~1.62V
1 30 R2 R2
2240 0027-7 2240
"
0027-6 0027-8
Figure 3. Test Loads
14-4
!il~ RAM Input/Output Characteristics
~J'~~~UcrOR =====================================================================
Rp
TTL TO
~--'-----~~----~~--~J~--~~--------~---------------'----~CMOS
CONVERTER
THIN OXIDE
TRANSISTOR
:Thick Oxide Field Transistor

'Substrate Diode VSUB
0027-9
Figure 4. Input Protection Circuit
rith a relatively low breakdown voltage of approximately from ground through RSUB forward biasing the lower tran-
l2V. Large input voltages cause the field transistors to tum sistor in the effective SCR. If this current is sufficient to
m discharging the ESD current harmlessly to ground. The tum on the transistor, the upper PNP transistor is forward
,hin oxide transistor breaks down when the voltage across biased, the SCR turns on and normally destroys the device.
t exceeds the 12V level and it is protected from destruction Several solutions are obvious, decreasing the substrate re-
)y the current limiting of Rp. The combination of these sistance, or adding a substrate bias generator are two. The
:wo structures provides ESD protection greater than bias generator technique has several additional benefits,
~250V, the limit of the testing equipment available. In ad- however, such as threshold voltage control which increases
iition, repeated applications of this stress do not cause a device performance and is employed in all Cypress prod-
iegradation that could lead to eventual device failure as ucts, along with guard rings which effectively isolate input
~bserved in functionally equivalent devices. and output structures from the core of the device and thus
effectively decrease the substrate resistance by short cir-
~CMOS Latchup cuiting the current paths. Latchup can potentially be in-
duced at either the inputs or outputs. In true CMOS output
[he parasitic bipolar transistors shown in Figure 5 result in structures as discussed above, the output driver has a
~ built-in silicon controlled rectifier illustrated in Figure 6. PMOS pullup which creates additional vertical bipolar
Under normal circumstances the substrate resistor RSUB is PNP transistors compounding the latchup problem. Addi-
;onnected to ground. Therefore, whenever the signal on tonal isolation using the guard ring technique can be used
~he pin goes below ground by one diode drop, current flows to solve this problem, at the expense of additional silicon
Output Driver CMOS Inverter
n-MOS
PULL-DOWN n-MOS
DEVICE
'n OUTPUT 1..r
/PULL-UP
DEVICE Vee OUTPUT INPUT
n+ DIFFUSION AND
n- WELL GUARD RING
p+ DIFFUSION
GUARD RING
LATERAL npn BIPOLAR
TRANSISTOR
PARASITIC
RESISTANCE
Figure S. CMOS Cross Section and Parasitic Circuits

VERTICAL pnp BIPOLAR
TRANSISTOR
0027-10

14-5
II
~ RAM Input/Output Characteristic;l,

~~~UcrOR====================================================================!~
Substrate Bias Generator latchup. The Cypress devices covered in this document car
sustain greater than 200 rnA without incurring latchup, fal
Vee more than is possible to encounter in any reasonable sys
tern environment.
Elimination of Latchup in Cypress
c~
RAMs
Since the latchup characteristic is one that inherently exist!
in any CMOS device, rather than change the laws of phys
ics, we design to minimize its effects over the operatin~
environment that the device must endure. These includt
temperature, power supply and signal levels as well as pro
cess variations. There are several techniques employed t(
eliminate the latchup phenomenon. Two of them involvt
moving the trigger threshold outside the operating range a!
to make it impossible to ever encounter it. These are eithel
0027-11
using low impedance, epitaxial, substrates and/or a sub-
strate bias generator. The use of a low impedance substratt
has the effect of increasing the undershoot voltage requirec
Figure 6. Parasitic SCR and Bias Generator to generate the required trigger current that causes latch
area. Since all of the devices of concern here require TTL up. A substrate bias generator has two effects which help tc
outputs, the problem is totally eliminated through the use eliminate latchup. First, by biasing the substrate at a nega
of an NMOS pullup. tive, - 3.0V, voltage, the parasitic diodes can not be for
ward biased unless the undershoot exceeds the - 3V by at
LATCHUP CHARACTERISTICS least one diode drop. Second, if undershoot is this severe!
Inducing Latchup for Testing Purposes the impedance of the bias generator itself is sufficient tc
deter sufficent trigger from being generated. The bias gen
Care needs to be exercised in testing for latchup since it is erator has one additional noticeable characteristic, it effec
normally a destructive phenomena. The normal method is tively removes the input clamp diode. This is due to th~
to power the device under test with a supply that can be anode of the diode connecting to the substrate which is at
current limited, such that when latchup is induced, insuffi- - 3.0V. Therefore, even though the diode exists as shown
cient current exists to destroy the device. Once this setup in Figure 4, DC signals of - 3.0V do not forward bias the
exists, driving the inputs or outputs with a current, and diode and exhibit the clamp condition. The benefits of this
measuring the point at which the power supply collapses are apparent in higher noise tolerance as substrate currents
will allow non-destructive measurement of the latchup due to input undershoot do not occur.
characteristics of the devices under question. In actual test-
ing, with the device under power, individual inputs and
outputs are driven positive and negative with a voltage and 10
the current measured at which the device latches up. This
provides the DC latchup data for each pin on the device as
1.0
a function of trigger current.
~
:--- ~
Measurement of Latchup Susceptibility 0.1

/
Actually measuring the latchup characteristics of devices <2:
E
/
should encompass ranges of reasonable positive and nega- I 0.01
tive currents for trigger sources. Depending on the device,
latchup can occur as low as a few rnA to as high as several
hundred rnA of sink or source current. Devices which latch
ca
.!P
0.001 I
I
at trigger currents of less than 20 to 30 rnA are in danger of 0.000 1

encountering system conditions that will cause latchup fail-
ure.
0.0000 1
Competitive Devices -5.0 -4.0 -3.0 -2.0 -1.0 o
Although there are few devices directly competitive with Vaa -V
the Cypress devices covered in this application note, the 0027-12
latchup characteristics of the closest functionally similar
devices were measured. The results show devices that Figure 7. Bias Generator Characteristics
latchup at as low as 10 rnA all the way to devices that can
sustain greater than 100 rnA of trigger current without
14-6
,Qcrmss
, SEMICONDUCTOR
RAM Input/Output Characteristics
======================================================================
0.0 0.0
-1.0 I -1.0
/
W
I-
0
z -2.0
w
~ w
! -2.0 ~
-3.0 / ~
!
~
-3.0
-4.0
-4.0
I
/ Vee =S.OV
-S.O
Vee =S.OV
-6.0 0.0 6.0 12.0 -6.0 0.0 6.0 12.0
VINPUT (VOLTS) 0027-13 VINPUT (VOLTS) 0027-14

Note: Output is in a High Impedance Condition.
Figure 8. Input V/1 Characteristics Figure 9. Output V/1 Characteristics

Pigures 8 and 9 represent the voltage and current charac- slope of the curve is set by the value of Rp. As the input
teristics of the devices discussed in this application brief. voltage goes positive, only leakage current flows. The out-
Pigure 8 is characteristic of an input pin, and Figure 9 an put characteristics in Figure 9 show the same phenomenon,
:mtput pin in a high impedance state. In Figure 8, the input with the exception that, since this is not an input, no pro-
-fovers + 12V to - 6V, well outside the + 7V to - 3V spec- tection circuit exists, and therefore no Rp exists. An equiv-
lfication. Referring to Figure 4 to understand these charac- alent thin film device acts as a clamp diode which limits
teristics, when the input voltage goes negative, the thin the output voltage to approximately - 1V at - 5 mAo
bxide transistor acts as a forward biased diode and the
II
14-7
CYPRESS
SEMICONDUCTOR
Power Characteristics of
Cypress Products
Introduction when CMOS circuits drive either bipolar circuits or DC
loads, external DC power is dissipated. It is standard prac
SCOPE AND PURPOSE tice in the semiconductor industry to NOT include the cur
rent from a DC load in the device Icc specification.
This document presents and analyzes the power dissipation Cypress supports this practice. It is also standard practice
characteristics. of Cypress products. The purpose of this to NOT include the current required to charge and dis
document is to provide the user with the knowledge and charge capacitive loads in the data sheet Icc specification.
the tools to manage power when using Cypress CMOS Cypress also supports this standard practice.
products.
Frequency Dependent Power
DESIGN PHILOSOPHY CMOS integrated circuits inherently dissipate significantl~
The design philosophy for all Cypress products is to less power than either bipolar or NMOS circuits. In the
achieve superior performance at reasonable power dissipa- ideal digital CMOS circuit there is no direct current pat}]
tion levels. The CMOS technology, the circuit design tech- between Ycc and Yss; in circuits using other technologie~
niques, architecture and the topology have been carefully such paths exist and DC power is dissipated while the de
combined in order to optimize the speed/power ratio. vice is in a static state.
The principal component of power dissipation in a power
SOURCES OF POWER DISSIPATION optimized CMOS circuit is the transient power required tc
Power is dissipated within the integrated circuit as well as charge and discharge the capacitances associated with the
external to it. Both internal and external power have a inputs, outputs, and internal nodes. This component is
quiescent (or DC) component and a frequency dependent commonly called Cy2f power and is directly proportional
component. The relative magnitudes of each depend upon to the operating frequency, f. The corresponding current is
the circuit design objectives. In circuits designed to mini- given by the formula
mize power dissipation at low to moderate performance, Icdt) = CYf.
the internal frequency dependent component is significant-
ly greater than the DC component. In the high perform- The primary sources of frequency dependent power are due
ance circuits designed and manufactured by Cypress, the to the capacitances associated with the internal nodes and
internal frequency dependent power component is much the output pins. For "regular" logic structures, such as
less than the DC component. The reason for this is that a RAMs, PROMs and FIFOs the internal capacitances are
large percentage of the internal power is dissipated in linear "balanced" so that the same delay and, therefore, the same
circuits such as sense amplifiers, bias generators and volt- frequency dependent power is dissipated independent of
age/current references that are required for high perform- the location that is addressed. This is not true for program-
ance. mable devices such as PALs because the capacitive loading
of the internal nodes is a function of the logic implemented
External Power Dissipatio~ by the device. In addition, PALs and other types of logic
The input impedance of CMOS circuits is extremely high. devices may contain sequential circuits so the input fre-
As a result, the DC input current is essentially zero (10 tJ-A quency and the output frequency may be different.
or less). When CMOS circuits drive other CMOS circuits The capacitance of each input pin is typically 5 pF, so its
there is practically no DC output current. However, contribution to the total power is usually insignificant.
Note:
The Cypress Power/Speed Program, which implements the equations in this application note, is available from Cypress for your use on personal
computers.
PAL~ is a registered trademark of Monolithic Memories.
14-8
~n Power Characteristics
~~NDUcrOR=======================================================================
lntroduction (Continued)
Ilerivation of Applicable Equations at the same time. This means that there is no direct current
fhe charge, Q, stored on a capacitor, C, that is charged to path between Vcc and ground, so that the quiescent power
1 voltage, V, is given by the equation; is very nearly zero. In the real world, when the input signal
makes the transition through the linear region (i.e., be-
Q=CV. EQ.1 tween logic levels) both the N-channel and the P-channel
Dividing both sides of equation 1 by the time required to transistors are partially turned ON. This creates a low im-
;harge and discharge the capacitor (one period or T) pedance path between Vcc and Vss, whose resistance is
vields; the sum of the N-channel and P-channel resistances. These
gates are used internally in Cypress products.
EQ.2 DC or Static Power
In addition to the conventional gates there are sense ampli-
By definition, current (I) is the charge per unit time and fiers, input buffers and output buffers, bias generators and
1 reference generators that all dissipate power. The RAMs
f= -. and FIFOs also have memory cells that dissipate standby
T
power whether the IC is selected or not. The PROM and
Therefore, PAL products have EPROM memory cells that do not
1= CVf. EQ.3 dissipate as much standby power as a RAM cell.
The power (P = VI) required to charge and discharge the Power Down Options
capacitor is obtained by multiplying both sides of equation Many of the Cypress static RAMs have power down op-
3 by V. tions that enable the user to reduce the power dissipation of
P = VI = CV2f EQ.4 these devices by approximately an order of magnitude
when they are not accessed. The technique used is to dis-
It is standard practice to make the assumption that the able or turn-off the input buffers and the sense amplifiers.
capacitor is charged to the supply voltage (Vcd so that
Worst Case Device Power Specifications
P = VccI = C [Vcc]2f EQ.5
All Cypress products are specified with Icc under worst,
The total power consumption for a CMOS integrated cir- worst, worst case conditions. This means that the Vcc
cuit is dependent upon: voltage is at its maximum (5.5V), the operating tempera-
the static (quiescent or DC) power consumption. ture is at its minimum, which is OC for commercial prod-
uct and - 55C for military product and all inputs are at
the internal frequency of operation VIN = 1.5V.
the internal equivalent (device) capacitance Icc TEMPERATURE DEPENDENCE
the number of inputs, their associated capacitance, and For all Cypress products operating under all conditions,
the frequency at which they are changing the Icc current increases as the temperature decreases. The
the number of outputs, their associated capacitance, Icc temperature coefficient is -0.12% per C. To calcu-
and the frequency at which they are changing late the percentage change in ICC from one temperature to
another, this temperature coefficient is multiplied by the
In equation form: temperature difference.
Po = [(CIN) (FIN) + (CINT) (FINT) + (CLOAO) (FLOAO)] If, for example, it is required to calculate the expected re-
[Vcc]2 + ICC (quiescent) Vcc. EQ. 6 duction in ICC if either a commercial or a military grade
The first three terms are frequency dependent and the last Cypress IC is operated at room temperature (25C), the
is not. This equation can be used to describe the power calculations are:
dissipation of every IC in the system. The total system For commercial products
power dissipation is then the algebraic sum of the individu- [0 - 25] X [-0.12%] = 3% less Icc at room tempera-
al components. ture than at OC.
The relative magnitudes of the various terms in the equa- For military products
tion are device dependent. Note that equation 6 must be
modified if all of the inputs, internal nodes or all of the [-55 - (25)] X [-0.12%] 9.6% less Icc at room
outputs are not switching at the same frequency. In the temperature than at - 55C.
general case, each of the terms is of the form C 1 F 1 + Procedure
C2 F2 + C3 F3 + ... Cn Fn. In practical reality the
terms are estimated using an equivalent capacitance and The procedure will be to develop a general purpose power
frequency. dissipation model that applies to all of the Cypress CMOS
products and to then present tables so that users can esti-
Transient Power: Input Buffers and Internal mate typical and worst case power dissipations for each
In the N-well CMOS inverter, the P-channel pullup tran- product. The data will be presented in chart form as func-
sistor and the N-channel pulldown transistor (which are in tions of product type and capacitance, that is: SRAM,
series with each other between Vee and Vss) are never on PROM, PAL or Logic; including FIFOs.
14-9
~ Power Characteristic~
~~~~NDUcrOR =======================================================================
n m
CORE
INPUT OUTPUT I
INPUTS ;
':t ~
BUFFERS ..L BUFFERS '..L
OUTPUTS
~CIN ~CINT ~CL
0059-:
Figure 1. Power Dissipation Model
Power Dissipation Model

A general purpose power dissipation model for all Cypress (except for type A) when VIN is 4V or more. In othel
integrated circuits is shown in Figure 1. words, if the inputs are driven "rail to rail" the Band (
The procedure will be to isolate the four components of input buffers will dissipate power only during the inpu1
power dissipation described by equation 6 by controlling signal transitions.
the inputs to the IC. The quiescent (Icd current is mea- To reach these levels the input pins should be either drivell
sured with the inputs to the IC at 0.4V or less. Under this by a CMOS driver or by a TTL driver whose output doe!
condition the input buffers and output buffers (unloaded not drive any other TTL inputs.
DC wise) draw only leakage currents. All other direct cur- When the inputs are driven by the minimum TTL level!
rents are due to the substrate bias generator, sense amplifi- (VJH = 2V, VIL = 0.8Y) each input buffer draws 20%
ers, other internal voltage or current references and NMOS more Icc current than if it were driven rail to rail.
memory circuits.
At VIN = 1.5V the input buffers draw maximum Icc cur-
rent. The total current is measured and the quiescent cur-
rent subtracted to find the total input buffer Icc current.
The current per input buffer is then calculated by dividing
the total input buffer current by the number of input buff-
ers. VOUT
INPUT BUFFERS
Three different types of input buffers are used in Cypress
products. For purposes of illustration they are referred to
0059-3
as types A, Band C. Table 1 lists the maximum ICCs.
Figure 2A
Table 1. Types of Input Buffers
Buffer Icc 1.3
Type (max. in mA)
A 1.3
B 0.8
C 0.6
The schematics and input characteristics for the three

types of buffers are illustrated in Figure 2. A circle on the
gate of a transistor means that it is a P-channel device.
As can be seen from the figure, the input buffers draw
essentially zero Icc current when VIN is 0.4V or less or o----~~----~----
o 0.6 2.0
VIN (V)
0059-4
Figure 2"
Type A
14-10
I!~~ Power Characteristics
~~~~UcrOR=====================================================================
flower Dissipation Model (Continued)
[)UTY CYCLE CONSIDERATIONS
0.6
rhe input characteristics of the type B (Figure 2D) and the
ype C (Figure 2F) buffers may be approximated by trian-
~les symmetric about the VIN = 1.5V points, whose ampli-
udes are 0.8 rnA and 0.6 rnA, respectively. Therefore, be-
ween the VIN = 0.5V and VIN = 3.5V points the average
:urrent is one-half the peak current, or 0.4 rnA and
>.3 rnA, respectively. In most systems the input signal slew
'ates are two volts per nanosecond or greater so the input
:ransitions occur quickly. Under these conditions the duty
:ycle of the input buffers must be considered.
I
O-~'------'-------'~-
o 0.5 1.5 35
VIN (V)
0059-8
Figure2F
TypeC
For example, if the CY7C167-35 RAM were used with
input signals having a slew rate of two volts per nanosec-
ond it would take
1
[3.5V - 0.5V] X - - = 1.5 ns
2V/ns
0059-5 for the input signals to go through the 3V transition. Dur-
Figure 2C ing the transition each input buffer would be drawing
0.3 rnA of current from the lee supply. However, this time
0.8 is only 1.5 ns/35 ns = 0.0429 or 4.29% of the access cycle.
Therefore, the actual input buffer transient current is only
0.0429 X 0.3 rnA = 0.01287 rnA. It will be shown that
this is insignificant in most power calculations.
INPUT BUFFER FREQUENCY
DEPENDENT CURRENT
This is the current required to charge and discharge the
capacitance associated with each input buffer. The capaci-
tance is typically 5 pF and the voltage swing is typically
O"~~--~----~--~
4V.
o 0.5 1.5 3.5 4.0 Using equation 3; 1= CVf
VIN (V) ledt) = 5 X 10- 12 X 4 X f.
0059-6
ledt) = 20 X lO- 12f.
Figure2D
TypeD CORE AND OUTPUT BUFFERS
vee The memory array will have a standby power dissipation
due to the substrate bias generator, reference generators,
sense amplifiers, and polyload RAM cells or EPROM
cells. This current is measured with VIN = OV, so that the
input buffers draw no current. Under these conditions the
output buffers will draw only leakage current and dissipate
1
essentially no power.
The output buffers have N-channel pullup devices that
cause the output voltage level to reach VOH = Vee - IV.
v,. The capacitance of the output buffers, including stray ca-
pacitance, is typically lO pF.
0059-7 IfCL = lOpF, VOH ~ 4V.
Figure 2E Again, using equation 3, ledt) = 40 X 10- 12f for the
output buffers.
14-11
~ Power CbaracteristiJ
~~~NDUcrOR==================================================================~~
Current Measurement Table 2 (Continued)
Buffer No. No. CINT Icc(Q) ICC (Max.
INSTANTANEOUS CURRENT Part No.
Type Inputs Outputs (pF) (mA) (mA)
Figure 3 illustrates the instantaneous current drawn by a CY7C161/162 B 22 4 300 13 70
Cypress RAM. The instantaneous power is calculated by CY7Cl64 B 20 4 300 13 70
multiplying this current times the constant supply voltage, CY7C166 B 21 4 300 13 70
vee. Most of the power is dissipated in the time corre- CY7C167 C 17 1 75 25 70
sponding to the access time. This is also true for PROMs CY7C168/169 C 18 4 75 50 70
and PALs. CY7C170 B 18 4 50 33 90
I
CY7C171/172 B 18 4 100 27 70
ADDRESS/DATA CY7C185/186 B 25 8 330 13 100
CY7C187 B 19 1 150 7 100
CY7C189/190 B 10 4 21 32 90
PROMs
Table 3
ICC Buffer No. No.* CINT Icc(Q) ICC(Max.
Part No.
CY7C225 B 12 8 32 35 90
CY7C235 B 13 8 35 35 90
~-------~--------~ CY7C245 B 13 8 35 50 90
~--------- TCY -----------+1 CY7C251 C 18 8 43 9.5 100
11 = Quiescent ICC 0059-2 CY7C254 C 18 8 43 35 100
12 = Average Icc CY7C261/3/4 C 14 8 60 45 100
i(t) = Instantaneous Icc CY7C268 C 19 1/8 60 60 100
Figure 3. RAM Icc CY7C269 C 17 1/8 60 60 100
CY7C281/282 B 14 8 35 35 100
AVERAGE CURRENT CY7C291/292 B 14 8 35 50 100
The current measurement unit in an automatic tester inte- *IBidirectional pins
grates the instantaneous current over the measurement cy-
cle and arrives at an equivalent average current. In other PALs
words, the average current, 12, during time TCY is equal to For the 16L8, 16R8, 16R6 and 16R4 the number of inputs
the area between the instantaneous current, i (t), and the X and outputs is, within limits, user configurable. All use
axis during TCY. Therefore, when the frequency is de- type B buffers.
creased, the "current pulse" is (figuratively) spread over a
longer time, so the average current is proportionately less. Table 4
CINT Icc(Q) Icc(Max.)
Part No.
DC Load Current (pF) (mA) (mA)
Note that the preceding calculations have not accounted PALC16L8/R8/R6/R4 40 25 45

for any DC loads. The user must calculate these separately. PLDC20G10 50 30 55
PALC22V10 50 40 80
PLDCY7C330 300 42 120
Product Characteristic Tables
The following tables are listed to enable the user to calcu- LOGIC PRODUCTS
late the current requirements for Cypress products. CINT is
the equivalent device internal capacitance, Icc (Q) is the Table 5
quiescent or DC current and ICC(MAX) is the maximum Buffer No. No.* CINT Icc(Q) ICC(Max.)
Icc current (as specified on the data sheet) for the com- Part No.
mercial operating temperature range. Conditions are Vee
= 5V and TA = 25C. CY7C401 B 6 6 53 30 75
CY7C402 B 7 7 53 30 75
STATIC RAMs CY7C403 B 7 6 53 30 75
Table 2 CY7C404 B 8 7 53 30 75
CY7C408 B 11 12 100 42 135
Buffer No. No. CINT Icc(Q) ICC (Max.) CY7C409 B 11 13 100 42 135
Part No.
Type Inputs Outputs (pF) (mA) (mA) CY7C428/9 C 14 12 190 18 80
CY7C1221123 A 16 4 24 50 90 CY7C510 C 24 19/16 60 30 100
CY7C128 B 14 8 27 59 120 CY7C516 C 28 16/16 60 30 100
CY7C147 B 15 1 34 28 90 CY7C517 C 28 16/16 60 30 100
CY7C148/149 B 12 1 32 45 90 CY3341 B 6 6 53 30 45
CY7C150 B 18 4 20 44 90 CY7C601 C 25 19/64 950 89 600
14-12
I~ Power Characteristics
~, ~NDUcrOR ===========================================================
~roduct Characteristic Tables (Continued) Output CVf Current
1= CVf COUT = lOpF
Table 5 (Continued)
I = 1.15 rnA V = 4V
Buffer No. No.* CINT Icc(Q) ICc(Max.)
Part No. f = 1/35 ns
:;Y7C901 C 24 10/4 160 25 80 Total = 4 X 1.15 = 4.6 rnA
:;Y7C909 C 21 5 80 25 55
:;Y7C91O C 22 16 150 2.6 70 The Quiescent Current is 50 rnA
:;Y7C911 C 13 5 80 25 55
The Total Current At TCY = 35 ns is;
:;Y7C9101 C 36 22/4 70 30 60
:;Y7C9116 C 22 1/20 1000 35 150 Input Transient 0.31 rnA
:;Y7C9117 C 38 1/4 1000 35 150 Input CVf 10.28 rnA
Internal CVf 10.71 rnA
IBidirectional pins
Output CVf 4.6 rnA
Quiescent 50 rnA
itatic RAM Example Total Icc 75.9 rnA (all inputs/outputs changing)
['0 illustrate how to use the preceding tables and perform
he required calculations the following example is provid-
:d. Note that the worst case transient current is 25.9 rnA.
If one-half of the inputs and outputs change this is reduced
!stimate the typical Icc current for the CY7C169-35
to 12.95 rnA, which gives a total current of 63 rnA (typical
tAM at room temperature (TA = 25C) and Vec = 5V.
~ssume the duty cycle is 100% at the specified access time. led
:::alculate typical and worst case Icc (all inputs and out- If the duty cycle is 10% the transient current is reduced to
mts changing) with output loading of 10 pF. 1.3 rnA, which results in a total current of 51.3 rnA.
"rom the RAM product characteristic table; Note also that the Input CVf current and the output CVf
# inputs = 18 current would have the same values for a bipolar device.
# outputs = 4 WORST, WORST, WORST CASE Icc

Next, let's estimate the Icc for worst case Vee and low
CINT = 75 pF
temperature, in addition to all inputs and outputs changing
Icc (Q) = 50 rnA and compare it with the Icc specified on the data sheet.
fRANSIENT INPUT BUFFER CURRENT The Icc current will be greater at high Vce, which is 5.5V
or 1.1 X the nominal 5V Vee. The increase in Icc due to
rhe input buffers on the CY7C169 are type C, so the aver- the lower temperature is 3%, so the total increase is 13%.
1ge current is 0.3 rnA. If the input signal level transitions These factors apply to the internal CVf current (10.71
lre 4V and the transition times are 2 VIns, the transition rnA), the output CVf current (4.6 rnA), and the quiescent
:ime is: current (50 rnA), (total 65.31 rnA).
4V Total Icc = Input Transient Icc + Input CVf Icc +
Tt = - - = 2ns.
2 V/ns [lnternaICVf+ OutputCVf+ ICC (Q)] X 1.13
fhe duty cycle is then; Icc = 0.31 + 10.28 + [65.31] X 1.13 = 84.4 rnA.
2 ns/35 ns = 0.057. This is approximately 94% of the 90 rnA specified on the
fherefore, each input buffer draws data sheet.
0.3 rnA X 0.057 = 0.0171 rnA. Note, however, that the data sheet Icc maximum does
NOT include the output CVf current.
[f all inputs change, the total transient input buffer current
is
I
18 X 0.0171 = 0.31 rnA.
Typical ICC Versus Frequency
CVf Input Buffer Current
Characteristic
The Icc versus frequency curves for all Cypress products
I = CVf CIN = 5 pF have the same basic shape, which is illustrated by the
I = 0.57 rnA V = 4V PAL 16R8 curve of Figure 4. The current remains essen-
tially constant at the quiescent Icc value until the frequen-
Total = 18 X 0.57 = 10.28 rnA
Internal CVf Current
f = 1/35 ns
cy increases to the point where the capacitances begin to
cause appreciable currents. This point depends upon the
capacitances (input, internal, and output), the number of
III
~
inputs and outputs, the rate at which they change, and the
I = CVf CINT = 75 pF voltage levels that they are switched between. For Cypress
I = 10.71 rnA V = 5V products this point is in the 1-10 MHz range.
f = 1/35 ns
14-13
~ Power Characteristicl
~~~NDUcroR ==================================================================~
Typical ICC Versus Frequency Characteristic (Continued)
The PAL 16R8 devices that were tested to obtain the data Point C is approximately 5.6 MHz.. This gives the user a
for the curve were exercised such that al1 inputs and al1 easy to use approximate formula to calculate the Icc CUl
outputs changed every cycle. Curve A shows the total Icc rent.
current for a 50 pF load on each of the eight outputs. For frequencies less than 5.6 MHz
Curve B shows the total Icc current when the outputs are
disabled. The B curve results from the input and the inter- Icc = Icc (Q) = 25 rnA
nal capacitances. In most applications the actual operation For frequencies greater than 5.6 MHz
of the device will be somewhere between the A and B
curves. Icc = ICC (Q) + 3.5 rnA per MHz (al1 outputs changing)
The A and B curves may be extrapolated backwards until or,
they intersect the quiescent current (point C in Figure 4). Icc = ICC (Q) + 0.5 rnA per MHz (no outputs changing)
Frequency in Hertz
I TYPICAL
Icc VS f
I Icd VS FREQUENCY FOR PAL l6RS
ALL INPUTS/OUTPUTS CHANGE
Vcc =5V, TA=250 C, V1L=0.8V, V1H =2V j
120
)f
<I(
E
3;;
u
100
80 !
,.".
V~ (OUTPUTS
CL=50pF
ENABLED)
.J:)
60 A~ _I I
40
~
II'
,
~~
o.~\~
1(0)
~
~
100' ~:-CL=OpF
.11
25
20
--- ct;t B (OUTPUTS
DISABLED)
111"1
0
10KHz 100KHz 1 MHz 10MHz 100 MHz
FREOUENCY IN HERTZ
0059-!
Figure 4. Typical Icc vs f
14-14
Pin-Out Compatibility Considerations
of SRAMs and PROMs
When looking for pin compatible replacements for Brand "X" Board
PROMs, there are a number of key parameters that must
be met. This application brief discusses the non-electrical }-'P---A2--------102
02 3--------02---}-'P
parameters of pin-out and programming involved in find-
}-'P---Al--------2 A1 01 4--------01---}-'P
ing socket compatible second sources for PROMs. Com-
parison with the selection of a socket compatible SRAM 0163-2
second source is provided. Additionally, an example of a Brand "X" Board with Cypress 2 x 4
verified conversion from the Motorola 68764 to the Cy-
press CY7C264, a PROM conversion that is not address
line compatible, is presented. }-'P---A2--------101
01 3--------02---}-'P
}-'P---Al--------2 A2 024--------01---}-'P
Ignoring the AC/DC characteristics, finding a second
- source for an SRAM is relatively simple. As long as the 0163-3
power, ground, control (chip select, read, write), address,
Figure 2. Example System with 2 x 4 SRAMs
and data lines are on the same pins the devices should be
compatible. Specifically, on SRAMs, the address and data the same as data written to the same location earlier. With
lines need not be numbered identically between the two the SRAM, any inconsistency between the Address and
devices being compared for them to function identically in Data line numbering does not really matter because the
the same socket. As an example, on several Cypress data read will be the same as the data previously written.
SRAMs, the address pin numbering is not the same as This occasionally causes some concern with customers who
some of our competitors. Let's look at a simplified example have not seen this before. To illustrate our point, suppose
that illustrates why this is not a problem. Let's assume that that we write a value of 1 (,..,P:D2,D 1 = 0,1) at location 2
we have a new device, the 2 bit x 4 location SRAM: (JLP:A2,Al = 1,0). If we read location 2, we will obtain
the value 1 that was written, because the address presented
Cypress Brand "X" to the SRAM during the read is the same as the address for
2x4 2x4 the previous write. Similarly, the data read will be in the
same bit order as presented during the previous write to the
101 013 102 023 location. As far as our system is concerned, the two SRAM
2A2 024 2 A1 01 4 devices are compatible. The only difference, which is not
significant to our system, is where the data was physically
0163-1 stored inside the SRAM. In the Cypress device, the JLP
Figure 1. Example 2 x 4 Simplified SRAMs address of 2 (JLP:A2,Al = 1,0) actually stored the data at
Note that the inferior pin-out chosen by the Brand "X" 2 x SRAM location 2 (Cypress:A2,Al = 0,1). In the brand X
4 assigns Address line 2 (A2) to pin 1 whereas the superior RAM, the data is physically stored in location 1. However,
pin-out used by the Cypress device has Al at pin 1, etc. It the address translation is transparent to the JLP. Since the
is our assertion that these simplified devices are pin com- same location is accessed for the subsequent reads, the dif-
patible. Let's assume that our engineering staff designed an ference in address numbering between the two devices
infrared scanning pattern recognizing toaster oven with the doesn't really matter to our system. Similarly, any number-
ing difference on the data lines doesn't matter either. The
Brand "X" data sheet. Just as your company is about to
ramp into volume production, Brand "X" sends out an
End Of Life notice on their 2 x 4, because they are convert-
ing all of their capacity to making DRAM memories. At
point that is of primary importance here is that for
SRAMs, all writes and reads are generated in your system,
and so long as the address and data lines are on the same
III

, this point, you have no desire to layout a new PC board, so pins, differences in the numbering don't matter.
let's take a look at how these devices would look in your For PROMs, the scenario becomes slightly more complex.
design. Since PROMs are programmed using a programmer that is
In this case, JLP is a microprocessor interfacing to the separate from the system in which they are used, it be-
SRAM. What is of key importance is that the data read comes more difficult to substitute a PROM with a device
from a given address generated by the microprocessor is that does not have the same address and/or data pin
14-15
~ Pin-Out Compatibility Considerations of SRAMs and PROM
~~~UaoR==================================================================I
numbering. Let's assume that our Hi-Tek toaster oven's 2 x swapped again due to the difference in numbering betwee
4 are now PROMs. If we programmed each location with the Cypress part and the board layout, and the ILP will get
data, we would find that the Cypress device would not the data in the correct order.
work properly when used in the Brand "X" designed sock- The second problem that exists is the difference in address
et. In this case our programmer put the data at location 2, line numbering. This problem can be resolved in exactly
and board would read this data when the microprocessor the same manner as the data swap problem. By simply
requested the data at location 1. Additionally, the data bits setting the programmer to the Cypress device type, reading
will be swapped on this read. What a messl It becomes the Brand "X" part, then programming the Cypress part,
apparent that it is easiest to replace this PROM with a any addressing differences will be solved allowing the use
. device that has the same address and data line numbering. of the Cypress device. The difference here is that the loca-
There are still methods that we can use that will allow us to tion of data words will be swapped to allow for the differ-
use the Cypress 2 x 4 PROM in this socket. ence in pin-outs, just as the bits were swapped in the data
The objective in trying to make the Cypress PROM work line mismatch case.
in the foreign pin-out socket is to have the data read by the Many programmers will allow you to read a device differ-
system be the same as the data read when the Brand "X" ent than the part selected, complaining only during a pro-
device is used. In our 2 x 4 example, there are two prob- gram if the device types do not match. With such a pro-
lems-address line numbering mismatch and Data line grammer, carrying out the above procedures to convert a
numbering mismatch. Let's first address the data line mis- PROM should not present a problem. However, there are
match. As it stands, data that was written in as bitl,bit2 is some programmers that will not allow the user to read a
read as bit2,bit1 or swapped. Ifwe were able to change our device if it is different from the part selected. These pro-
PC Board layout, we could fix this problem by swapping grammers will prevent our method from working. Fortu-
the printed traces for D1 and D2. Unfortunately, this nately, the Cypress' CY3000 QuickPro programmer will
would prevent the use of the Brand "X" device on our allow this approach to solving our problem. Cypress Field
board. We can internally swap the data bits in the Cypress Applications Engineers, Sales Offices and Distributors can
device, then they would be in the correct order. This swap- use their QuickPro to generate a Cypress master PROM
ping of the data bits in the Cypress device can be achieved that can be used as a source for copying with un-coopera-
through several means. First, we might modify our pro- tive programmers.
gramming adapter such that D2 and D 1 are swapped from
the normal order when programming the part. Then when As an example of such a conversion, the Motorola 68764
the device is read, we would get the bits in the same order 8K x 8 PROM has a similar pin-out to the Cypress 7C264
as presented by the Brand "X" device. This is not a recom- with the exception of address lines 10, 11, and 12.
mended method of solving the problem, because modifying
programmers tends to make the manufacturer of the pro- Pin Cypress 7C264 Motorola 68764
grammer unhappy. A second method of solving this prob- 21 A10 A12
lem is to alter the binary image of the PROM contents 19 All A10
such that bits D 1 and D2 are swapped in a file on your 18 A12 All
computer's disk, then using this altered binary image file to
program the Cypress PROM. This is less likely to cause Figure 4. Cypress 7C264 vs. Motorola 68764 PinOut
damage than modifying a programmer, but requires some The following procedure will program a Cypress 7C264
skill in altering the binary file. Finally, the easiest solution such that it will work properly in a socket designed to
to this problem is to trick the PROM programmer into accept Motorola device.
swapping the bits for you. If you set your programmer for 1) Invoke the Cypress QuickPro (or other usable program-
the Cypress device type, read a programmed Brand "X" mer) and select the Cypress 7C264 as the device to be pro-
device into memory, then program the Cypress part with grammed.
the image in programmer memory, the bits will have been
swapped for you. Let's look at how this works. 2) Place the Motorola part in the programmer adapter
socket and read the device. Optionally write the device
1) Brand "X" 2 x 4 :Bit 2, Bit 1 contents to a disk file.
2) Programmer (Cypress) :Bit 1, Bit 2 3) Place a Cypress 7C264 into the programmer adapter
3) Cypress 2 x 4 :Bit 1, Bit 2 socket and program the part. Optionally the contents of the
4) System Board ,""P :Bit 2, Bit 1 disk file may be read as the source for programming.
Figure 3. PROM Bit Swapping with Programmer The programmed device will now work in the Motorola
designed socket.
From the diagram above, we can see that the bits in the
Brand "X" device are stored in the order Bit2,Bit 1. This is
the same order that the ILP will read them on our board. Summary
When we set the programmer to read the Cypress part, the If the pins used for power, ground, control, address, and
data lines are logically swapped from the Brand "X" order- data line numbering are the same for two devices, they may
ing. Thus when we read the Brand "X" part, the data bits be used in the same socket if the other electrical parameters
will be swapped as shown. When the Brand "X" part is are compatible. Differences in Address and Data line num
removed from the .socket, and the Cypress device is bering are of no consequence in SRAM use. Differences in
plugged in and programmed, the bits will be programmed Address and Data line numbering in a PROM device can
into the Cypress part in this same 'reversed' order. When be compensated for by using a simple programming proce
we place the Cypress part into our board, the bits will be dure.
1416
PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS IIII
QUICKPRO
PLDTOOLKIT FfII
QUALITY AND
RELIABILITY
DII
APPLICATION BRIEFS
PACKAGES ,.
DI
~ Section Contents
~)r;~NooaoR============================================================~
~ackages Page Number
~hermal Management and Component Reliability ........................................................... 15-1
'ackage Diagrams ..................................................................................... 15-6
CYPRESS
SEMICONDUCTOR
Thermal Management and

Component Reliability
One of the key variables determining the long-term reliabil- ical reactions. The slope of the logarithmic plots is given by
ity of an integrated circuit is the junction temperature of the activation energy of the failure mechanisms causing
the device during operation. Long-term reliability of the thermally activated wear out of the device (Figure 1).
semiconductor chip degrades proportionally with increas- Typical activation energies for commonly observed failure
ing temperatures following an exponential function de- mechanism in CMOS devices are shown in Table 2.
scribed by the Arrhenius equation of the kinetics of chem-
I
I f
L /
~ ~
_ ~0'f
~'
~!J ...//
I
1 L
If f
4 I /
~ 10
:::i I I
iii I I
f ./
:::i
lLI I I(
/
~0~
0:::
103
lLI
>
~ u
N-
.....
C).
, ~
J J ~0~ 1/
...J
lLI
0:::
102
I / C\I
=~
>-
_U
I'-
t7 -
C)7 ./
C\I =. . . C).~e~
~ -0)
I I ~ -" JtfI'
I If 0)/ ./ .JIIII'
i""""
101 li / "/ . /
0:::
IIL~ .JI' -
...J-(/)
-
- (/)
II"~~ 0_0 _0
." 9:: ::E ::E
CD'- z- U
200175 150 125 100 75 50 25
TEMPERATURE (C)
0064-1
Figure 1. Arrhenius plot, which assumes a failure rate proportional to EXP ( - EA/kT)
where EA is the activation energy for the particular failure mechanism
15-1
~ Thermal Managemen1
~~~U~==================================================================
Table 2. Failure Mechanisms and Thermal Performance Data of Cypress
Activation Energies in CMOS Devices
Approximate
Component Packages
Failure Mode The thermal performance of a semiconductor device in it~
Activation Energy (EQ)
package is determined by many factors, including package
Oxide Defects 0.3 eV design and construction, packaging materials, chip size,
Silicon Defects 0.3eV chip thickness, chip attachment process and materials,
package size, etc.
Electromigration 0.6eV
Contact Metallurgy 0.9 eV Thermal Resistance (8 JA, 8 JC)
Surface Charge 0.5-1.0 eV For a packaged semiconductor device, heat generated near
the junction of the powered chip causes the junction tem-
Slow Trapping 1.0eV perature to rise above the ambient temperature. The total
Plastic Chemistry 1.0eV thermal resistance is defined as,
Polarization 1.0eV TJ - TA
OJA=---
Microcracks 1.3 eV
P
and OJA physically represents the temperature differential
Contamination 1.4eV between the die junction and the surrounding ambient at a
To reduce thermally-activated reliability failures, Cypress power dissipation of 1 watt.
Semiconductor has optimized both their low power gener- The junction temperature is given by the equation:
ating 1.2,... CMOS device fabrication process and their high
heat dissipation packaging capabilities. Table 3 demon- TJ = TA +P [OJA] = TA +P [OJC + OCA]
strates this optimized thermal performance by comparing where:
bipolar, NMOS and Cypress high speed lK SRAM CMOS TJ - Tc Tc - TA
devices in their respective plastic packaging environments OJC = - - - and OCA = ---"'-----"-"
under standard operating conditions. P P
T A = Ambient temperature at which the device is operated;
Table 3. Thermal Performance of Most common standard temperature of operation
Fast lK SRAMS in Plastic Packages equals 70C
Cypress TJ = Junction temperature of the IC chip
Technology Bipolar NMOS
CMOS
TC = Temperature of the case (package)
Device Number 93422 9122 7C122
P = Power at which the device operates
Speed (ns) 30 25 25
OJC = Junction to case thermal resistance
ICC(mA) 150 110 60 OJA = Junction to ambient thermal resistance
Vcc(V) 5.0 5.0 5.0 OCA = Case to ambient thermal resistance
PMAX(MW) 750 550 300 The junction-to-ambient environment is a still-air environ-
Package RTH (JA) eC/W) 120 120 70 ment where the device is inserted into a low-cost standard
device socket and mounted on a standard .062" GIO PC
Junction Temperature eC) 160 136 91 board. For junction-to-case measurements, the same as-
at Data Sheet PMAX* sembly is immersed into a constant temperature liquid res-
Tambient = 70C ervoir approaching infinite heat sinking for the heat dissi-
The Cypress 7Cl22 device, during its normal operation, pated from the package surface.
experiences a 91C junction temperature, whereas competi- The thermal resistance values of Cypress standard pack-
tive devices in their respective packaging environments see ages are graphically illustrated in Figures 4 through 7.
a 45C and 69C higher junction temperature. In terms of Each envelope represents a spread of typical Cypress inte-
relative reliability life expectancy, assuming a 1.0 eV acti- grated circuit chip sizes (upper boundary = 5000 Mils2,
vation energy failure mechanisms, this translates into an lower boundary = 30,000 Mils2) in their thermally opti-
improvement in excess of two orders of magnitude (IOOX) mized packaging environment.
over the bipolar 93422 device and more than one order of All thermal characteristics are measured using the TSP
magnitude (30X) over the NMOS 9122 device. (Temperature Sensitive Parameter) test method described
in MIL STD 883C, Method 1012.1. A thermal silicon test
chip, containing a 25.0 diffused resistor to heat the chip
and a calibrated TSP diode to measure the junction tem-
perature, is used for all characterizations.
15-2
~Wr~c= Thermal Management
...-... 100
I- DIE SIZE
~ 90 :--f--+--+--+ - - - 5,000 sa MILS.
~ --30,000 sa MILS.
80
"
u
0
'-/ 70
W
u 60
z JA

l-
50
V)
V) 40
w JC
a::: 30
....J
20
~
a::: 10
w
:r:
I- 0
16 20 24 28 32 36 40
t LEAD COUNT ~
0064-2
Figure 4. Thermal Resistance of Cypress Plastic DIP Packages
100 DIE SIZE

90 r-+--+---+---+--+--+ - - - 5,000 sa MILS.
--30,000 sa MILS.
80
70
w
U 60
z

l-
50 JA
V)
V) 40
w
a::: 30
....J
20 JC
~
a::: 10
w
:r:
l- o
16 20 24 28 32 36 40
t LEAD COUNT ~
0064-3
Figure 5. Thermal Resistance of Cypress Cerdip Packages
15-3
Wr~ Thermal Management
,...........
I-
100 DIE SIZE
~ 90 - 5,000 sa MILS.
~ -30,000 sa MILS.
"u
0
'-"
80
70
UJ
u 60
z

I-
50
(f) JA
(f) 40
UJ
a::: 30
-.J
20
::E JC
a::: 10
UJ
:c
I- 0
16 20 24 28 32 36 40
t LEAD COUNT ----.
0064-4
Figure 6. Thermal Resistance of Cypress Hermetic Chip Carriers (HLCC)
100
~
g 90
80
~ 70
10.1
u 60
z
~ 50
!!! 40
en
10.1
~ 30
..J
~ 20
:2
~
10.1 10
~ 0
16 20 24 28 32 36 40
LEAD COUNT--
0064-5
Figure 7. Thermal Resistance of Cypress SOICs
15-4
~ Thermal Management
~~~~~UcrOR==============================================================
i Packaging Materials
CYPRESS PLASTIC PACKAGES CYPRESS CERDIP PACKAGES
INCORPORATE: INCORPORATE:
High thermal conductivity copper lead frame. High conductivity Alumina substrates.
Molding compound with high thermal conductivity. Silver filled glass as die attach material.
Silver filled conductive epoxy as die attach material. Alloy 42 lead frame.
Gold bond wires. Aluminum bond wires.
15-5

CYPRESS
SEMICONDUCTOR
Package Diagrams
-__
16 Lead (300 MIL) Cerdip D2 18 Lead (300 MIL) Cerdip D4
0005 MIN. lor--~PIN 1 MILM38510D'2CONFIG.1

0.005~ t- ::]PINI
I MILM38510D6CONFIG.1
Jl0
~:~!~ -I I- ~SEATING
1
0230
DIMENSIONS IN INCHES
MIN.
MAX
C
r--- ~::~~ - - j ~:~;~
~~~
1
0245
0
SEATING PLANE
MIN.
MAX.
II--~----l
" ---I I--- PLANE
C 0.320 :::J I
I c: 0'155g~~~m-t
0.745 0.140 0.290
I 0.785 I 0.175 0.320:;1
0.200 .Jl __
~:~: fJmiW1El / ~ I~
i
0.125
0200
I
I
I
I-
~ ~ 0.~15 J_~ ~~*' II
--II--
0.060 1- 0.012
I--- 0 .330_
1
~:~~ I
- ~:~;~I--
I J L __~~060
0.050
D.065
0.015
0,015
0.020
. --I 0.045 0.Q15 0.390

0.090 0.065 0.020
Q.iTO
20 Lead (300 MIL) Cerdip D6 22 Lead (400 MIL) Cerdip D8

MIl. M 38510 08 CONFIG. 1 MIL M38510 D-7 CONFIG. 1
r--
oa rr
0.005 M~ PIN 1
0005~ r- _-:lPINl
MIN. I
. .1
o. 245 DIMENSIONS IN INCHES
:~.
0.310 MAX.
--.-l [
~
SEATING
g:gj~ --J PLANE
0.930
0.970
0.140
0.175
~
0.320
~ ~:~!: -I '-- SEATING PLANE
0.155 .----r---....,~Ii ~
I - - - 1.050 - - - I 0.140
I _:110 I 0.175 1cD.42ii::;1
0.390
:~~~J::m~ .~~~
0.200 ~~ 0.015
0.009.2:..
0.012 15
-J11l.-~ -J
,. " ~ ~ ij
0 065 o.OeO 1 - 0 330
0.090 0.015-11- . 0.390
0.110 0Mii II'''' I " " .I
0200 I I --I j.- I+-0.420--l
. --I I-- 0.045 0.015 0.490
0.090 0.065 0.020
0.110
15-6
Package n lagrams o
(600 MIL) Cerdip D12

24 Lead MILM3851
0 D-3 CONFIG. 1
PIN 1
DIt.lENSIONS IN INCHES
t.lIN.
t.lAX.
MIN.
MAx:
0.090
0.110
24 Lead (300 MIL) Cerdip D14 Lead (600 MIL) Cerdip D16
28 MIL-M-38510 Dl0CONFIG.l
-
PIN 1
MIN.
MAX.
SEATING MIN.
PLANE MAx.
SEATING PLANE
0.155
0.200
15-7
Package Dia~
40 Lead (600 MIL) Cerdip D18
MIL M 38510 0-5 CONFIG. 1
MIN.
MAX.
SEATING PLANE
j- 2.030 ~
2.100 0.140
0.175
1- 0.590:j
0620
.
~:~~:=ll~1 ~11~
l' ,
0.200
~.Q.
ru_I L
0.040
0.060
u-:: \:::
0.015
L
II
0.630
0.690
-J
~
0 *-
0.110 0.020
MIN.
MAX.
0.090 0.045 0_015

1-- -1 0 . 630
0.690
o.ITO 0.065 0.020
11
0.005 MIN.
//PIN1
DO
~5 0.310
OIMENSIONS IN INCHES
MIN
MAx'
-.l SEATING
PLANE
~ ~
0'065
0.095
1.430 0.140 0.290
1.485 0.175 r-0.320~
~m?~-tIL!t
0.200
~
JJ.
~
0.200
I I
I I 111111
0.009
00i2
a-
15-
~
f
0.015
~CO'045
D.ii65 ~:~!~ L' j 0.330
0.390
0.110 0.020
15-8
'i~ Package Diagrams
~~~~============================================================
48 Lead (600 MIL) Sidebraze DIP D26

0.005 MIN PIN 1
1 r-
1 DIMENSIONS
IN INCHES
(
I
JO
0.5 50
0.6
MIN.
MAX.
2.370
0.
020
Q.08o
-i [ 0.100
SEATING
PLANE
~1---------2.430 0.200
~~~
I-
..-.l.~ ~
0.090-1
0.110
0.040
0.060
0.015-11.-
0.022
0.125~
0.160
, 0.070 I 0.012 I
\--0.590-1
0.620
52 Lead (900 MIL) Bottombraze DIP D28

0.005 MIN PIN 1
1r- DIMENSIONS
IN INCHES
-1 0.7S0
MIN.
MAX.
0075
0.S20 X= 0-:-10-0
J
1
'c1'l:l'l::n:::::n:::::ln:::::rlr:::::n::::n:::n::::ral::::n:::n::I1:I'I::n::n::::II'I:I'I::n:::::n:::::ln:::::rlr:::::n::::n::rr
y=o.oso
O. 11 0
_ 2.560
~:~:~-i ~SEATING . PLANE
I
lJ
2.640 ~ _ _ __
g:~~~ M
D.090
0.110
--I I- 0.0'0
0.060
~~ 0.015
0.020
--II- 0.125
0.160
=r 1':.1I ~:~:;
0.009 O.SSO
0.012 --Ii 0.920
15-9
~ Package Diagraml
~~~UcrOR================================================================~_
64 Lead (900 MIL) Bottombraze DIP D30

0.005 MIN
PIN 1
1r- DIMENSIONS
IN INCHES
MIN.
1
0.780
MAX.
0075
0.820 X= -0:-10-0
"I::r1:l'l:::2Cn::::naw:::n:::I~:n::rr:::::rI:l'l::n::n::::naw:::n:::I~:n::rr:::::rI:l'l:::2Cn::::naw:::n:::I~;r11 J
y=0.080
0.11 0
3.160
~:~~~-i V , - .
SEATING
PLANE
I 3.240 ~
g:~~ ~ 0 !~I~~J\
0.090
0.110
---1 ~ 0.040
0.060
~~ 0.015
0.020
---1~ 0.1253
0.160 0.009
151
/
g:g:~
0.880
0.012 --Ii 0.920

PIN 1
I 0.245
0.310
~~~~~~~~--!
I
g:~~~~ I
0.125 I
0.200
I I
I. 0.090
~ ~0.110 I
1--- 0.330 _ _-+-II
0 390
15-tO
,~~CYPRESS Package Diagrams
'~~aflCO~ucr~==========================================================

PIN 1
I 0.580
0.610
~--~~~~~~~--!
SEATING PLANE
\ ~
I I
I. 0.090
-l ~0.110 I 0.630 _ _-,.\
1--- 0 . 690

PIN 1
15-11
~
~ Package Diagraml
~~~~UcrOR=================================================================I~
16 Lead Rectangular Flatpack F69 18 Lead Rectangular Flatpack F70

(MIL-M-38510 F"-5 CONF"IG 2) 0.045 PIN 1, DIMENSIONS IN INCHES ~~
0.045 PIN 1 DIMENSIONS IN INCHES ~~~ 0. 055 1 -==---.~
~
0. 055 1_
~ ~ 0.015 T-
D~g::~;
Dt:::==::a~:r
0.019L
t
0.012
0. 045 1_
0.012
0. 020 1_
!il
t
t
g:~~g I g:~~~ J
~
l
1Q.003
g:~;~g g:~:;J
0.030
0.050 t1 I--
~~~J~~~==~=~~~0.~090
I.- 0.155 -..l 0.005 ]
4
t
------'- 0.045
~
l
1Q.004
0.007
0.030
0.050
-l.J:-
.q. .Ioj.---fJ"'----~--g-:....L..~~g
\.1.--,P10~.2==0=0==0=.0=2~6:::!J~~t
0.250 0.040
0.006 0.175 0.015
20 Lead Rectangular Flatpack F71 24 Lead Rectangular Flatpack F73

(MIL-M-38510 F"-6 CONF"IG 2)
~~~
0.045
0. 055
PIN 1""\
1 -=-1
0.045 PIN 1""\ DIMENSIONS IN INCHES m:
~
0. 055 1_ 1
0.480
0.520 0.015
'-----'~
0.019L
t
t
g:~~~ Ig:~~~J
~
l
1Q.004
0.007
0.
050
0.070
-l.J=
t1"'~; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;.JfJl.I. ----J--g-:g-'-~~
I.- 0.224 -..l
0.236
0.010]
0.030
t
15-12
:II~ Package Diagrams
'~~~~'-~UaoR===================================================
42 Lead Rectangular Fiatpack F76
0.045 PIN 11
0.055
1 -t-
t
0.018
0. 022 1
T
D 1.070
MAX.
0.012
0.045
1
0.100
MAX. J
L
I " .
I .I " i I =.l
0.630 ----I- 0.275 -l t l
G.007
0.010 I--- 0.650 0.325
0.040
0.060
48 Lead Quad Flatpack F78

(Preliminary)
0.089
0750 MAX 0.108
0.079
0.550 esc ~ 0.096
~ 0.100 REF 0.058
0.073
0.350 0.350
0.450 0.450
0.350
0.450
I :1 0.050 ~
r- esc
T
8
~
0 .750
MAX
0.550
esc f 0.630
I Of MAX MAX
~
j f l
II.. ~ 0.018
f 0.022
I
PIN"O~ 0.350
0.450
l II 0.009
110.012
II
15-13
IIIII
~ Package Diagram I
~~~U~ ================================================================~I
64 Lead Quad Flatpack F90
(Preliminary)
0885 0.070
0.090
0.915
0.060
~
0.750 BSC
0.078
- 0.075 REF
0.350
I 0.350
0.030
0.045
0.450 0.450
0.350
0.450
r- l-
0.050
~
BSC
I ~
T
o.885
0--
.915
0.750
BSC
LL REF
f
Ie"
8 0.535
~
T
~
1
0.016
0.020
0.505
0.530
~
I
PIN1ID~ 0.350
0.450
l II 0.009
-'10.012
68 Pin Grid Array Package G68
Index Markl:t1Bc!mi00<:;n;~)ffiil---r
MIN
MAX
BOTTOM
0.090
0.105
SEATING
PLANE
O.OM)
0.060
0.077
0.093
1
TOP
SIDE
1.089
1:IT1
PIN#1 I 1.089
1.111
-I
J LO.175
0.185
15-14
~ Package Diagrams
~~~UcrOR============================================================
207 Pin Grid Array G207

1 - - - - - - - ;:~~~ - - - - -.... 1
' - - - - - ;:~!; ------+-I
000000000000000
00000000000000000
00000000000000000
00000000000000000
0000 0000
0 0
0000 0 0 0 0000
0000 SIDE
1.780
0000 0000 1.752
_J
0000 0000 1.615 0.100
0000
0000
0000
0000
1.585 -t
0000 0000
0000 0000
00000000000000000
===t 207 X 0.018
00000000000000000 _t
00000000000000000 --t 4 X 0.050
~000000000000000
I .0.100
BOTTOM VIEW r- 0.120
0.040
207 X 0.070 0.060
I-
299 Pin Grid Array G299

(Preliminary)
1 - - - - - - - - 2.070 --------1
1 . - - - - - 1.90 BSCO - - - - - - I
000000000000000000
00000000000000000000
00000000000000000000
00000000000000000000
00000000000000000000
00000 00000
00000 00000
00000 00000
00000 00000 2.070
00000 00000 SIDE
00000 00000
00000 00000 1.900 -~
0.100
00000 00000 -f
00000 00000
00000 00000 _t
00000000000000000000 ---r 20 x 0.Q18
00000000000000000000
00000000000000000000
00000000000000000000
000000000000000000
BOTTOM VIEW
15-15
5'n
i
CYPRFSS Package Diagram~
~~============~~~
28 Pin Windowed Leaded Chip Carrier H64

RIGHT SIDE
VIEW
0.040 x 45 0 BOTTOt.l VIEW
SEE~ "
DETAIL "P" '..;'
GLASS WINDOW TOP VIEW

0.150R TYP.
DETAIL "P"
15-16
RIGHT SIDE
(MIL-M-38510 C-J1)
0.040x45 VIEW
BOnOt.4 VIEW
SEE~ "
DETAIL "P" ,,'

0.280R TYP.
0.035 x 45 0
0.008
~r- I r - -........~-
-++4-+----- + ____-+-_+-1--'- 0.642

0.658
TIl
0.695
0.685
0.032
0.026
DETAIL "P"
~
EO. ~I 5.
0.642
_ _ _ _ _ _ _ 0.695
0.685
ILl
15-17
(MIL-M-38510 C-J2) RIGHT SIDE
0.040x45 VIEW
Bonot.! VIEW
DETAIL ~~~~,:
- -_ _ _ _ _ _-+=::9.... 0.800
REF.
0.0.983090

0.280R TYP.
- - - - t - - - - - + l 1 = I - g::!~
0.0.999585
DETAIL "P"
:000000
g_::_!_~~-0-.9-95--------II.1
I
1
t+-_ _ _ _ _ _ _ _
0.985 _______ --l
..
15-18
.~ Package Diagrams
~~~~abUcrOR=====================================================================
20 Lead Plastic Leadless Chip Carrier J61 28 Lead Plastic Leadless Chip Carrier J64
DIt.iENSIONS IN INCHES DIt.iENSIONS IN INCHES
t.iIN.
~
t.iAX. t.iAX.
PIN 1 PIN 1
01.1,1
I q
0.395 ~t 1
0.021
0.350 0.290
I!
0.356 0.330
~ 0'09~0'020
0.350 ~ t.iIN.
0.356
0.120
1 - - - - ~:~:; 0.165
0.180
32 Lead Plastic Leadless Chip Carrier J65 44 Lead Plastic Leadless Chip Carrier J67
MIN.
MAX.
PIN 1
10.490
0.530
~-----.l
1 0.065 0.110
0.140
0.095
1-11- 0:021
0 013

0.390 ----I
I t t t
0.015 MIN.
0.430
15-19
I
[,
Package Diagram~
52 Lead Plastic Leadless Chip Carrier J69

Mtth
MAX.
PIN 1
t- 0.750
0.756
0.785
0.795
,I
68 Lead Plastic Leadless Chip Carrier J81

.M!.Ii,.
MAX.
PIN 1
0.985
0.995
15-20
,~ Package Diagrams
~~~~~UcrOR==============================================================
16 Lead Rectangular Cerpack K69 18 Lead Rectangular Cerpack K70

(MIL-M-38510 F-5 CONFIG 1) (MIL-M-38510 F-10 CONFIG 1)
PIN 1 1.0. ,..-______________ ------.i.
0.045
0.055
TOP VIEW TOP VIEW
0.085 MAX.
.~~==J=========~
~:~~~ I
______':2= 0.004
~0.009
~==]::=======IL_ ~ 0.009
0.004
~t~==:1I===0='=24=6==j::r==+LL 0.026 SEATING

0.280 0.040 PLANE
~:;j5I
T 0250 I 250
I ,:2=
I 0.250 l L 0.026 SEATING
0.250 0:350 I------ ~:300 - - - - i 0.350 0.040 PLANE
0.350
20 Lead Rectangular Cerpack K71 24 Lead Rectangular Cerpack K73

(MIL-M-38510 F-9 CON FIG 1) (MIL-M-38510 F-8 CONFIG 1)
PIN 1 1.0. __ 1 0 .320 MAX. ~ PIN 1 1.0.
.__--------------. ------.i.
0.005 ~ L 0.005 MIN.
0.G15 I~ ::::: 0.045

0.055
0.480
0.520 TOP VIEW
0.590
1I"------'~
0.620
0.045 MAX.
~:ajl
______
~~==J=========~
I ':2=
0.004
~0.009
0.004
T I I 0.250 l L 0.026 SEATING
~:;~~ I------ ~:;~~ - - - i 0.350 ~==]::=======IL-_~0.009
0.040 PLANE
~:~jOI
T I
I
I
1:2=
II L 0.026 SEATING
~:;~~ I------ ~:!g~ - - - - i ~:;~~ 0.040 PLANE
15-21
28 Lead Rectangular Cerpack K74
(MIL-M-38510 f-ll CONflG 1)
PIN 1 10
L ~-
i
-~ 'L
, 0.005 MIN.
0.005J
0.015
L - ----
L - --~ 0.045
L 0.055
o.740 I
MAX. L
I
,1..
I
,L 0.015
0.022
,
,
,
- --;r 0.045 MAX.
0.003
0.~04~5~==f======t-- 0.009
O'rj' 0250 I 0340
'.370 1----=-----.1 .250
l o l:=2=
L 0.026 SEATING
0 0.380 0.370 0.040 PLANE
15-22
~~======================================~p~a~Ck~a~g~e~D~i~a~gr~a~m~s
196 Lead Quad Flatpack Package K196
o____-------
;~ m~ ~ ~ ij~ ~ij~ijijijij
1.475 S-'-Q._ _ _ _ _ _ _-I
;;, I I
0.025 t.4IN.
0.0045
L
f E3
DATUt.4
PLANE
TOP VIEW
LEAD FORM DETAIL
SIDE VIEW
15-23
~
~~~~u~================================================================~~
Package Diagra!
18 Pin Rectangular Leadless Chip Carrier LSO 20 Pin Rectangular Leadless Chip Carrier LSI
(MIL-M-385l0 C-l0A) (MIL-M-385l0C-13)
0.008R BOTTOM I 0.045

~0.055
r
18 PLCS
MIN.
MAX.
16PLCS
DIMENSIONS IN INCHE~ II
--t---It. MIN. I
MAX.
n
It.
I-
0.060
0.075
n
fl
TOP SIDE
0.420
TOP SIDE 0.435
0.417
0.433
c,.wjl
c=,~Jl 0.300
~ I. . 0.050
0.066
0.300 ~ \.- 0.050

0.066
22 Pin Rectangular Leadless Chip Carrier LS2 24 Pin Rectangular Leadless Chip Carrier LS3
DIMENSIONS IN INCHES MIN.
MIN. MAX.
0_045 MAX.
0_055 ,--~3--- --I::::--<l
0.020
-.l 0.022 0.030
to. 028
0.008 R
24 PLACES I- 0.062
n
I 0.078
I-- 0.060
I 0.075
TOP SIDE
TOP SIDE
0.392
0.408
t=~jJ
0.308
-I \.- 0.050
0.063
0.050
0.066
15-24
:L~ Package Diagrams
~~~~================================================================
28 Pin Rectangular Leadless Chip Carrier LS4 32 Pin Rectangular Leadless Chip Carrier LSS
(MIL-M-38510 C-llA) (MIL-M-38510 C-12)
DIMENSIONS IN INCHES DIMENSIONS IN INCHES
MIN. MIN.
MAX. MAX.
0.045
0.055.-----!E1-- ---BE- ct.
..l. 0.022
til.02ii
,-0.06-4
n
' - 0.060 I 0.090
I 0.075 ,..-------
TOP SIDE
TOP SIDE
0.5-40
0.560
I 0.054
1--0 063
~J 0.-4-42
0.-458
\.- 0.050
0.080
20 Pin Square Leadless Chip Carrier L61 24 Pin Square Leadless Chip Carrier L63
(MIL-M-38510 C-2A)
0.045
0.055
0.0-45
MIN.
0.045 + MAX. 0.055 t
0.055 ....~3---
..l.0.015
,0.025
0.008 R.
2-4 PLACES ,-0.060
of]
' - 0.060 I 0.100
I 0.075
TOP SIDE
SIDE
TOP
~0.054
0.066
~J 0.-410
I.- 0.050
0.088
15-25
~ Package Diagram
==============================================================~I
crmss
WnICONDucrOR
28 Pin Square Leadless Chip Carrier L64
(MIL-M-38510 C-4)
0.045
MIN.
0.055 -r-~~-- --~<t. MAX.
-1 0.022
t 0.028
i - 0.064
I 0.078
TOP
LL SIDE
D
~~~u0.458
I~ 0.458
I 0.045
1-- 0 .066

(MIL-M-38510 C-5)
_ 0.045
0.055
,-~~~~~~~~~~~~ 1
MIN.
MAX.
0.045
0.055 .----E:J----- + <t.
-*- 0.022
to.028
r O 064
n
0.100
TOP SIDE
0.640
~0.054
1_----- 0.640 _ _ _ _ _.j
0.660 -I 0.088
15-26
~,l~ Package Diagrams
~~~~u~==================================================================
48 Pin Square Leadless Chip Carrier L68 52 Pin Square Leadless Chip Carrier L69
f" :::~
...J0'066~
I I
I
I
IN NO.1
INDEX--""";
---j---- ----------.----------
I
I
i
BOTTOM
0.740
0.761 lo.086
0.100 ~
I 0.072 ____1
0.088 I
n
0.740
0.761
I
I
----------.---------
l
I
I
0.0075 R REF".
(3 CORNERS)
TOP SIDE
15-27
1III
~ Package Diagraml
~~~U~R================================================================~.
(tolIL-tol-38510 C-7)
OltolENSIONS IN INCHES
toliN.
tolAX.
0.045
0.055,......-EJ-------
TOP
1 - - - - - - - - ~::::--------
16 Lead (300 MIL) Molded DIP PI 18 Lead (300 MIL) Molded DIP P3
[
_-::d~~PINl DIMENSIONS IN INCHES
MIN.
0.240 MAx.
0.270
--
~ .I.-~ SEATING PLANE
SEATING PLANE
r-
wg
~':~~~ ~::!~ Ie
0.280 ---j
~I
rt ~ r~
0.325
::n:n:rmj
O.
140
t --WI V- 1S3~
+~ ~~
~::: J~ ~0:;:
0.190
""1= 0.125 I
i i
---I I-- 0.055 0.016
~0.310 I
0.385 --l
--l
0.200 ~
0.090
0.110
0.065 0.020
0.090
0.110
15-28
iJ1~NDucrOR ===================================================================== Package Diagrams
20 Lead (300 MIL) Molded DIP PS
-' /PINI
- 22 Lead (400 MIL) Molded DIP P7

PIN 1
00 C
DIMENSIONS IN INCHES MIN.
~
~ MIN.
i~ ~ ~ .'" ~'j" r, ::::~':'

--I .
MAX
d
~ ~:'"
'~~~~~
i ~::~
~::~~=~ .
:t~ ~ :::~b.~ L:~-.J
0.110
0.200 I
--l I.--
I
J
];1 1 illI-- --II--
II l.:
0.055 0.015
1:~~, ~w
~ 0485
.
---I
0.090 0.065 0.020
0.110
22 Lead (300 MIL) Molded DIP P9 24 Lead (600 MIL) Molded DIP PH
PIN 1
I:::::::::~t
OIWENSIONS IN INCHES
WIN.
WAX.
MIN.
MAx.
0.065
o
150
-i0.090t-
0.110
15-29

d
l
~ Package Diagr
~~~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===~==1_
24 Lead (300 MIL) Molded DIP PI3/PI3A 28 Lead (600 MIL) Molded DIP PIS
/"Nl PIN 1
OO
~ DIMENSIONS IN INCHES
T MIN.
~ MAx.
0.270
---*- MIN.
MAX.
m
NOTEB-./. f i j S E A T I N G PLANE
0.280
'" . NOTE A 0.120 r,0.325J
0"80"T~l:'
JJd
0.190 ~~--.U
~:~: ~ [0.015 ~:~ ~ ~
T

1989 Cmos Bicmos Data Book

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1989 Cmos Bicmos Data Book

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Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.

Published February 1, 1989

BridgeMOSTM is a trademark of Cypress Semiconductor Corporation.

Static RAMs (Random Access Memory)

PROMs (Programmable Read Only Memory)

CY7C271 32,768 x 8 Reprogrammable Power Switched PROM ............................. 3-99

EPLDs (Eraseable Programmable Logic Devices)

Quality and Reliability

7C401 Cascadeable 64 x 4 FIFO .................................................... 5-; l

7C404 Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-:,

BM PC is a registered trademark of International Business Corporation.

2901--4 Bit Slice

RAM, PROM, FIFO, JJ.P ,ECL

~--- SPEED (ns or MHz)

i.e. CY7C128-35PC, PALC16R8L-25PC

" ' - - - SPEED

Cypress FSCM # 65786

2l4755M 2l4745M 54Sl89M 27S03M 7Cl6835C 7Cl6825C 7C254-65M 7C25455M

214845M 214835M 74S189C 27S03C 7C17045M 7C170-35M 7C26335C 7C26335C

214935C 7C14935C 7C12835M 7C12835M 7C186L45M 7C18645M 7C264-45C 7C26435C

2l4955C 21L4955C 7C\3Q.45M 7C13045M 7C19445C 7C194-35C+ 7C26860M 7C26850M+

21L4935C 7C14925C 7C\3155M 7C13145M 7Cl9745C 7C19735C+ 7C28245M 7C28245M

27S03C 27S03AC 7C13645C 7C13635C 7C19955C 7C19945C+ 7C291A35M 7C291 A30M

27S07C 27S07AC 7C14135C 7C14125C 7C23540C 7C2353OC 7C291L50C 7C291L-35C

2909AM 7C90940M 7C14825C 7C14825C 7C245A35M 7C245A25M 7C293A35M 7C293A30M I

7C404-15C 7C404-25C 7C910-93C 7C91O-50C PREFIX:Am PREFIX:CY 21L47-55C 7C147-45C

7C409-15M 7C409-25M 9122-25C 7C122-15C SUFFIX:P SUFFIX:P 21L49-55C 21L49-55C

7C421-4OC 7C421-3OC 91L22-35C 7C122-35C 2147-45M 2147-45M 27C191-35C 7C292AL-35C

7C424-65C 7C424-40C 93422M 93422AM 214S-35M 214S-35M 27C291A-30M 7C291A-30M

7C42S-40C 7C42S-30C 93L422M 93L422AM 214S-70M 214S-55M 27LS291M 7C291-35M

7C429-65C 7C429-40C PALC16R4-25C PALC16R4L-25C 2149-7OC 2149-55C 27PS191AM 7C292-50M+

.: 7C51O-75M 7C51O-65M PALC16R6-30M PALC16R6-20M 2167-55C 7C167-45C 27PS2S1M 7C2S1-45M+

27S07C 27S07C 2909AM 2909AM 3341C 3341C 99C641-3SC 7C187-3SC

27S191AC 7C292-3SC 2910AM 2910AM 9122-3SM 7C122-3SM 99C641-70M 7C187-4SM

27S2SAM 7C225-3SM 29116M 7C9116AM 9128-200M 6116-S5M 99C68-70C 7C168-4SC*

27S2S1AM 7C281-45M 2911M 2911M 9150-35C 7C150-35C 99C88H-55M 7C1S6-55M

27S291M 7C291-50M 29517AC 7CS17-3SC 91L22-45C 91L22-45C 99CL68-55C 7C168-45C*

27S35M 7C235-40M 29703M 27S03M 93422AC 93422AC PAL16LSAC PALC16LS-25C

27S45AM 7C245-45M 29COIBA 7C901-32M 93422C 93422C PAL16L8ALM PALC16L8-30M I

27S45C 7C245-45C 29COlBC 7C901-31C 93422M 93422M PAL 16L8AM PALC16LS-30M

27S45SAM 7C245A-25M - 29CIO-IC 7C91O-4OC 93L422C 93L422C PAL16L8LC PALC16LS-35C

27S51C 7C254-55C 29C116C 7C9116AC 99C164-55M 7Cl64-45M + PAL16R4A-4M PALC16R4-40M

PAL16R6BM PALCI6R620M 16X17-45C 1611HV45C 1601C55 7C18745C 93Z565AM 7C26455M

PAL16R6QM PALCI6R640M 4128885C 1421HD85C 1622C35 7CI6635C+ 93Z665M 7C26445M

PAL16R8AM PALCI6R830M 8M65635C 161OHD35C 16P8A PALCI6L825C- PREFIX:MBM PREFIX:CY

PAL16R8QC PALCI6R8L35 816H16C35 1611HV35C 16R8A PALCI6R825C 100422AC 100E4227C

H816HI6C-45CC 1611HV45C 16RP8A PALCI6R825C 10422A7C IOE4227C

SUFFIX:F SUFFIX:F I8M8128C6OCC 1420HD55C 54S189M 54S189M 2147H35 214735C

.101OT 7C51O75M + PREFIX:F PREFIX:CY 74S189 74S189C 214945 2149-45C

7138ESK 7C2915OC PREFIX:4 SUFFIX:L l00422C lOOE4227C 626735 7CI6735C+

7144E 7C264-55C 16RC48 PALCI6R4-4OM 104748C 10E4747C 628770 7C187-45C

7232RA20 7C2353OC 16RC88 PALCI6R84OM 48472 214745C 678825 7CI6425C

816770W 7C167-45M 676161B5 7C29135C 6116AS15 611655C+ SUFFIX:P SUFFIX:P

817155 7C187-45 65162B5 611655C* 6147H55 7CI4745C+ 1203M35 7CI4735M+

81C6855W 7C168-45M + 65162S9 611655M* 6148H45 7CI4845C+ 1223M45 7CI4845M+

81C7525 7C16625C 65262S9 7CI6745M* 61676 7CI6745C+ 14OOM70 7C16745M

81C84-45 7C194-45C 766415 7C26455C 6167L6 7CI6745C* 1403M35 7CI6735M+

1423-40 7CI68-45C+ 1820-45 7C19445C 6116S120B 611655M + 6167SA55 7CI67-45C+

143345 7C128-45C+ SUFFIX:D SUFFIX:D 6116S90 611655C+ 6168L55B 7CI6845M*

160045 7C18745C 39C01CM 2901CM+ 6116SA35T 7CI2835C+ 6168LA35 7CI6835C*