DSA00126992

SYM53C810A
PCI-SCSI I/O Processor
Data Manual
Version 2.0
. I N C R E A S I N G S C S I R E L I A B I L I T Y
TolerANT
A C T I V E N E G A T I O N T E C H N O L O G Y
®
T07962I
The products described in this publication are product s of Symbios Logic Inc.
SCRIPTS is a trademark and TolerANT is a registered trademark of Symbios Logic

Inc.
It is the policy of Symbios Logic to improve products as new technology,

components, software, and firmware become available. Symbios Logic, therefore,
reserves the right to change specifications without notice.
The products in this manual are not intended for use in life-support appliances,
devices, or systems. Use of these products in such applications without the written
consent of the appropriate Symbios Logic officer is prohibited
Copyright ©1995, 1996

By Symbios Logic Inc.
All Rights Reserved
Printed in U.S.A.
We use comments from our readers to improve Symbios product literature. Please
e-mail any comments regarding technical documentation to pubs@symbios.com.
Preface
Preface
SCSI and PCI Reference

Information
This manual assumes some prior knowledge of current and proposed SCSI and PCI standards. For back-
ground information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800)-854-7179 or (303) 792-2181 (outside U.S.)
Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia
Prentice Hall
Englewood Cliffs, NJ 07632
(201) 767-5937
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface
Symbios Logic Electronic Bulletin Board
(719) 573-3562
SCSI Electronic Bulletin Board
(719) 533-7950
Symbios Logic Internet Anonymous FTP Site
ftp.symbios.com (204.131.200.1)
Server:Bastion
Directory: /pub/symchips/scsi
Symbios Logic World-Wide Web Home Page
http://www.symbios.com
PCI Special Interest Group
P.O. Box 10470
Portland, OR 97214
(800) 433-5177; (503) 797-4201 (International); FAX (503) 234-6762
Symbios Logic PCI-SCSI Programming Guide
SYM56C810A Data Manual i

Document History
Document History
Page No. Date Remarks
n/a 6/95 Rev 1.0
1-1,1-3, 1-5, 2-1—2- 7/96 Version 2.0

4, 2-10, 2-11, 2-13,
3-2, 3-4, 3-6, 3-7, 3-
9, 3-10, 4-1, 4-4, 4-
6, 4-7, 5-1, 5-10, 5-
12, 5-13—5-16, 5-
21, 5-31, 5-35, 5-50,
6-23—6-25, 7-1, 7-2,
7-9, 7-13, 7-24
ii SYM56C810A Data Manual

Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
SCSI and PCI Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Chapter 1
Introduction
What is Covered in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
SYM53C810A Benefits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
SCSI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
PCI Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Functional Description
SCSI Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
DMA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SCRIPTS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SDMS: The Total SCSI Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Prefetching SCRIPTS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Op Code Fetch Burst Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Load/Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3.3 Volt/5 Volt PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Parity Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
DMA FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Asynchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Synchronous SCSI Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Asynchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Synchronous SCSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
SYM53C810A Data Manual iii

Contents
SCSI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Terminator Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
(Re)Select During (Re)Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Determining the Data Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SCNTL3 Register, bits 6–4 (SCF2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SCNTL3 Register, bits 2–0 (CCF2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SXFER Register, bits 7–5 (TP2–0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Achieving Optimal SCSI Send Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Polling and Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
ISTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
SIST0 and SIST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
SIEN0 and SIEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
DIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
DCNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Fatal vs. Non-Fatal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Stacked Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Halting in an Orderly Fashion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Sample Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Chapter 3
PCI Functional Description
PCI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PCI Bus Commands and Functions Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PCI Cache Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Support for PCI Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Selection of Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
MMOV Misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Memory Write and Invalidate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Multiple Cache Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI Target Retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PCI Target Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Memory Read Line Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Memory Read Multiple Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Burst Size Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Read Multiple with Read Line Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Unsupported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
iv SYM53C810A Data Manual

Contents
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Register 00h
Vendor ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 02h
Device ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 04h
Command
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Register 06h
Status
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Register 08h
Revision ID
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 09h
Class Code
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Ch
Cache Line Size
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Dh
Latency Timer
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 0Eh
Header Type
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 10h
Base Address Zero (I/O)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 14h
Base Address One (Memory)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Ch
Interrupt Line
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Dh
Interrupt Pin
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Eh
Min_Gnt
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3Fh
Max_Lat
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
SYM53C810A Data Manual v

Contents
Chapter 4
Signal Descriptions
Chapter 5
Operating Registers
Register 00 (80)
SCSI Control Zero (SCNTL0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 01 (81)
SCSI Control One (SCNTL1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 02 (82)
SCSI Control Two (SCNTL2)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 03 (83)
SCSI Control Three (SCNTL3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 04 (84)
SCSI Chip ID (SCID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 05 (85)
SCSI Transfer (SXFER)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 06 (86)
SCSI Destination ID (SDID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 07 (87)
General Purpose (GPREG)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 09 (89)
SCSI Output Control Latch (SOCL)
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 0A (8A)
SCSI Selector ID (SSID)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 0B (8B)
SCSI Bus Control Lines (SBCL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Register 0C (8C)
DMA Status (DSTAT)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Register 0D (8D)
SCSI Status Zero (SSTAT0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Register 0E (8E)
SCSI Status One (SSTAT1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
vi SYM53C810A Data Manual

Contents
Register 0F (8F)
SCSI Status Two (SSTAT2)
(Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Registers 10-13 (90-93)
Data Structure Address (DSA)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Register 14 (94)
Interrupt Status (ISTAT)
(Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Register 18 (98)
Chip Test Zero (CTEST0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Register 19 (99)
Chip Test One (CTEST1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Register 1A (9A)
Chip Test Two (CTEST2)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Register 1B (9B)
Chip Test Three (CTEST3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Registers 1C-1F (9C-9F)
Temporary (TEMP)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Register 21 (A1)
Chip Test Four (CTEST4)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Register 22 (A2)
Chip Test Five (CTEST5)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Register 23 (A3)
Chip Test Six (CTEST6)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Registers 24-26 (A4-A6)
DMA Byte Counter (DBC)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Register 27 (A7)
DMA Command (DCMD)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Registers 28-2B (A8-AB)
DMA Next Address (DNAD)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Registers 2C-2F (AC-AF)
DMA SCRIPTS Pointer (DSP)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Registers 30-33 (B0-B3)
DMA SCRIPTS Pointer Save (DSPS)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
SYM53C810A Data Manual vii

Contents
Registers 34-37 (B4-B7)

Scratch Register A (SCRATCH A)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Register 38 (B8)
DMA Mode (DMODE)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Register 39 (B9)
DMA Interrupt Enable (DIEN)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Register 3A (BA)
Scratch Byte Register (SBR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Register 3B (BB)
DMA Control (DCNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Register 3C-3F (BC-BF)
Adder Sum Output (ADDER)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Register 40 (C0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Register 41 (C1)
SCSI Interrupt Enable One (SIEN1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Register 42 (C2)
SCSI Interrupt Status Zero (SIST0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Register 43 (C3)
SCSI Interrupt Status One (SIST1)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
Register 46 (C6)
Memory Access Control (MACNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Register 47 (C7)
General Purpose Pin Control (GPCNTL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Register 48 (C8)
SCSI Timer Zero (STIME0)
Read /Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Register 49 (C9)
SCSI Timer One (STIME1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Register 4A (CA)
Response ID (RESPID)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Register 4C (CC)
SCSI Test Zero (STEST0)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
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Contents
Register 4D (CD)
SCSI Test One (STEST1)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
Register 4E (CE)
SCSI Test Two (STEST2)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
Registers 5C-5F (DC-DF)
Scratch Register B (SCRATCHB)
(Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
Chapter 6
Instruction Set of the I/O Processor
SCSI SCRIPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Sample Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Block Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Read-Modify-Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Move to/from
SFBR Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Transfer Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Memory Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Third Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Read/Write System Memory from a SCRIPTS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
First Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Second Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
SYM53C810A Data Manual ix

Contents
Chapter 7
Electrical Characteristics
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
TolerANT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
PCI Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Target Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Initiator Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
SCSI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Initiator Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Initiator Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Target Asynchronous Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Target Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Appendix A
Register Summary
Appendix B
Mechanical Drawing
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
x SYM53C810A Data Manual

List of Figures
List of Figures
Figure 1-1: SYM53C810A System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-2: SYM53C810A Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 2-1: DMA FIFO Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-2: SYM Host Interface Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-3: Active or Regulated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-4: Determining the Synchronous Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 3-1: PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-2: Command Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-3: Status Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 4-1: SYM53C810A Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2: Functional Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 5-1: SYM53C810A Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Figure 6-1: SCRIPTS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Figure 6-2: Block Move Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6-3: I/O Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-4: Read/Write Register Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6-5: Transfer Control Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-6: Memory to Memory Move Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-7: Load and Store Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Figure 7-1: Rise and Fall Time Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-2: SCSI Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-3: Hysteresis of SCSI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-4: Input Current as a Function of Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-5: Output Current as a Function of Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-6: Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Figure 7-7: Reset Input Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-8: Interrupt Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-9: PCI Configuration Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-10: PCI Configuration Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Figure 7-11: Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-12: Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
SYM53C810A Data Manual xi

List of Figures
Figure 7-13: Op Code Fetch, non-burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Figure 7-14: Burst Op Code Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Figure 7-15: Back to Back Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Figure 7-16: Back to Back Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Figure 7-17: Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Figure 7-18: Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Figure 7-19: Initiator Asynchronous Send Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Figure 7-20: Initiator Asynchronous Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Figure 7-21: Target Asynchronous Send Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Figure 7-22: Target Asynchronous Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Figure 7-23: Initiator and Target Synchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
xii SYM53C810A Data Manual

List of Tables
List of Tables
Table 2-1: Bits Used for Parity Control and Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Table 2-2: SCSI Parity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3: SCSI Parity Errors and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 3-1: PCI Bus Commands and Encoding Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 4-1: Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2: System Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-3: Address and Data Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-4: Interface Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-5: Arbitration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-6: Error Reporting Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-7: SCSI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-8: Additional Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Table 5-1: Operating Register Addresses and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table 5-2: Synchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-3: Asynchronous Clock Conversion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1 . . . . . . . . . . . . . 5-12
Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI . . . . . . . . . . . 5-12
Table 5-6: SCSI Synchronous Offset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Table 6-1: Read/Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Table 7-1: Absolute Maximum Stress Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Table 7-2: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/. . . . . . . . . . . 7-3
Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN . . . . . . . . . . . . . . . . . 7-3
Table 7-6: Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-7: Output Signal - MAC/_TESTOUT, REQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-8: Output Signal - IRQ/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-9: Output Signal - SERR/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-10: Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/,
DEVSEL/, STOP/, PERR/, PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SYM53C810A Data Manual xiii

List of Tables
Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/ . . . . . . . . . . . . . . . . 7-5

Table 7-12: TolerANT Active Negation Technology Electrical Characteristics. . . . . . . . . . . . . 7-6
Table 7-13: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-14: Reset Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-15: Interrupt Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-16: SYM53C810A PCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Table 7-17: Initiator Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Table 7-18: Initiator Asynchronous Receive Timings (5MB/s) . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Table 7-19: Target Asynchronous Send Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Table 7-20: Target Asynchronous Receive Timings (5 MB/s). . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock) . . . . . . . . . . 7-28
Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock) . . . . . . . . . . 7-28
xiv SYM53C810A Data Manual

Introduction
What is Covered in This Manual
Chapter 1
Introduction
What is Covered in This General Description

Manual The SYM53C810A PCI-SCSI I/O Processor
brings high-performance I/O solutions to host
This manual provides reference information on the adapter, workstation, and general computer
SYM53C810A PCI- SCSI I/O Processor. It is designs, making it easy to add SCSI to any PCI
intended for system designers and programmers system.
who are using this device to design a SCSI port for
PCI-based personal computers, workstations, or The SYM53C810A is a pin-for-pin replacement
embedded applications. for the SYM53C810 PCI-SCSI I/O processor. It
performs Fast SCSI transfers in single-ended
This chapter includes general information about mode, and improves performance by optimizing
the SYM53C810A and other members of the PCI bus utilization. A system diagram showing the
SYM53C8XX family of PCI-SCSI I/O Processors. connections of the SYM53C810A in a PCI system
Chapter 2 describes the main functional areas of is pictured in Figure 1-1. A block diagram of the
the chip in more detail, including the interfaces to SYM53C810A is pictured in Figure 1-2.
the SCSI bus. Chapter 3 describes the chip’s con-
nection to the PCI bus, including the PCI com- The SYM53C810A integrates a high-perfor-
mands and configuration registers supported. mance SCSI core, a PCI bus master DMA core,
Chapter 4 contains the pin diagrams and defini- and the Symbios Logic SCSI SCRIPTS™ proces-
tions of each signal. Chapter 5 describes each bit sor to meet the flexibility requirements of SCSI-1,
in the operating registers, organized by address. SCSI-2, and future SCSI standards. It is designed
Chapter 6 defines all of the SCSI SCRIPTS to implement multi-threaded I/O algorithms with a
instructions that are supported by the minimum of processor intervention, solving the
SYM53C810A. Chapter 7 contains the electrical protocol overhead problems of previous intelligent
characteristics and AC timings for the chip. The and non-intelligent adapter designs.
appendixes contain a register summary and a The SYM53C810A is fully supported by the
mechanical drawing of the SYM53C810A. Symbios Logic SCSI Device Management System
This data manual assumes the user is familiar with (SDMS™), a software package that supports the
the current and proposed standards for SCSI and Advanced SCSI Protocol Interface (ASPI). SDMS
PCI. For additional background information on provides BIOS and driver support for hard disk,
these topics, please refer to the list of reference tape, removable media products, and CD-ROM
materials provided in the Preface of this docu- under the major PC operating systems.
ment. The SYM53C810A is packaged in a compact rect-
angular 100-pin PQFP package to minimize board
space requirements. It operates the SCSI bus at 5
MB/s asynchronously or 10 MB/s synchronously,
and bursts data to the host at full PCI speeds. The
SYM53C810A Data Manual 1-1

Introduction
TolerANT Technology
SYM53C810A increases SCRIPTS performance

and reduces PCI bus overhead by allowing instruc- TolerANT Technology
tion prefetches of four or eight dwords.
All Symbios Logic Fast-SCSI devices feature Tol-
Software development tools are available to devel-
erANT® technology, which includes active nega-
opers who use the SCSI SCRIPTS language to
tion on the SCSI drivers and input signal filtering
create customized SCSI software applications. The
on the SCSI receivers. Active negation causes the
SYM53C810A allows easy firmware upgrades and
SCSI Request, Acknowledge, Data, and Parity sig-
is supported by advanced SCRIPTS commands.
nals to be actively driven high rather than passively
pulled up by terminators. Active negation is
enabled by setting bit 7 in the STEST3 register in
the SYM53C8XX family products.
TolerANT receiver technology improves data
integrity in unreliable cabling environments, where
other devices would be subject to data corruption.
TolerANT receivers filter the SCSI bus signals to
eliminate unwanted transitions, without the long
signal delay associated with RC-type input filters.
This improved driver and receiver technology
helps eliminate double clocking of data, the single
biggest reliability issue with SCSI operations.
TolerANT input signal filtering is a built in feature
of all Symbios Logic fast SCSI devices. On the
SYM53C8XX family products, the user may select
a filtering period of 30 or 60 ns, with bit 1 in the
STEST2 register.
The benefits of TolerANT include increased
immunity to noise when the signal is going high,
better performance due to balanced duty cycles,
and improved fast SCSI transfer rates. In addition,
TolerANT SCSI devices do not cause glitches on
the SCSI bus at power up or power down, so other
devices on the bus are also protected from data
corruption. TolerANT is compatible with both the
Alternative One and Alternative Two termination
schemes proposed by the American National Stan-
dards Institute.
1-2 SYM53C810A Data Manual

Introduction
SYM53C810A Benefits Summary
SYM53C810A Benefits PCI Performance

Summary ■ Bursts 2, 4, 8, or 16 dwords across PCI bus
with 80-byte DMA FIFO
■ Pre-fetches up to 8 dwords of SCRIPTS
SCSI Performance instructions
■ Complies with PCI 2.1 specification ■ Supports 32-bit word data bursts with variable
burst lengths.
■ Supports variable block size and scatter/gather
data transfers ■ Bursts SCRIPTS op code fetches across the
PCI bus
■ Minimizes SCSI I/O start latency
■ Performs zero wait-state bus master data bursts
■ Performs complex bus sequences without
faster than 110 MB/s (@ 33 MHz)
interrupts, including restore data pointers
■ Supports PCI Cache Line Size Register
■ Reduces ISR overhead through a unique
interrupt status reporting method
■ Performs Fast SCSI bus transfers in single- Integration
ended mode ■ 3.3V/5 V PCI Interface
■ up to 7 MB/s asynchronous ■ Full 32-bit PCI DMA bus master
■ 10 MB/s synchronous ■ DMA controller using Memory to Memory
■ New Load and Store SCRIPTS instruction Move instructions
increases performance of data transfers to and ■ High performance SCSI core
from the chip registers
■ Integrated SCRIPTS processor
■ Support for target to disconnect and later
reselect with no interrupt to the system ■ Compact 100-pin PQFP packaging
processor ■ Ease of Use Direct PCI-to-SCSI connection
■ Supports execution of multi-threaded I/O ■ Reduced SCSI development effort
algorithms in SCSI SCRIPTS with fast I/O
context switching ■ Support for the Advanced SCSI Protocol
Interface (ASPI) software standard via SDMS
software
■ Compatibility with existing SYM53C7XX and
53C8XX family SCRIPTS
■ Direct connection to PCI, and SCSI single-
ended bus
■ Development tools and sample SCSI
SCRIPTS
■ Maskable and pollable interrupts

Introduction
■ Three programmable SCSI timers: Select/

Reselect, Handshake-to-Handshake, and Reliability
General Purpose. The time-out period is ■ 2 KV ESD protection on SCSI signals
programmable from 100 µs to greater than 1.6
seconds ■ Typical 300 mV SCSI bus hysteresis
■ SDMS software for complete PC-based ■ Average operating supply current of 50 mA

operating system support ■ Protection against bus reflections due to
■ Support for relative jump impedance mismatches
■ New SCSI Selected As ID bits for use when ■ Controlled bus assertion times (reduces RFI,
responding with multiple IDs improves reliability, and eases FCC
certification)
■ Latch-up protection greater than 150 mA
Flexibility
■ Voltage feed through protection (minimum
■ High level programming interface (SCSI
leakage current through SCSI pads)
SCRIPTS)
■ 25% of pins power and ground
■ Support for execution of tailored SCSI
sequences from main system RAM ■ Power and ground isolation of I/O pads and
internal chip logic
■ Flexible programming interface to tune I/O
performance or to adapt to unique SCSI ■ Symbios Logic TolerANT technology with:
devices ■ Active negation of SCSI Data, Parity,
■ Flexibility to accommodate changes in the Request, and Acknowledge signals for
logical I/O interface definition improved fast SCSI transfer rates.
■ Low level access to all registers and all SCSI ■ Input signal filtering on SCSI receivers
bus signals improves data integrity, even in noisy
cabling environments.
■ Fetch, Master, and Memory Access control
pins
■ Support for indirect fetching of DMA address Testability
and byte counts so that SCRIPTS can be ■ Access to all SCSI signals through
placed in a PROM programmed I/O
■ Separate SCSI and system clocks ■ SCSI loopback diagnostics
■ Selectable IRQ pin disable bit ■ SCSI bus signal continuity checking
■ Ability to route system clock to SCSI clock ■ Single-step mode operation
■ Test mode (AND tree) to check pin continuity
to the board

Introduction
SCSI Term Connection

SCSI Connection
Vdd Vss
SCSI Bus
PCI SYM53C810A
Bus
SCLK Peripheral
40 MHz Oscillator or
Optional Bulkhead
Internal Connection
to PCI Bus Clock
CPU Baseboard
CPU Box
Figure 1-1: SYM53C810A System Diagram
PCI
PCI Master and Slave Control Block
Data SCSI Operating Config

FIFO SCRIPTS Registers Registers
80 Bytes
SCSI FIFO and SCSI Control Block
TolerANT Technology Drivers and Receivers
Single-Ended SCSI Bus
Figure 1-2: SYM53C810A Chip Block Diagram

Introduction

SCSI Core
Chapter 2
The SYM53C810A contains three functional

blocks: the SCSI Core, the DMA Core, and the DMA Core
SCRIPTS Processor. The SYM53C810A is fully
supported by the SCSI Device Management Sys- The DMA core is a bus master DMA device that
tem (SDMS), a complete software package that attaches directly to the industry standard PCI Bus.
supports the Symbios Logic product line of SCSI The DMA core is tightly coupled to the SCSI core
processors and controllers. through the SCRIPTS processor, which supports
uninterrupted scatter/gather memory operations.
The SYM53C810A supports 32-bit memory and
SCSI Core automatically supports misaligned DMA transfers.
An 80-byte FIFO allows two, four, eight, or six-
The SCSI core supports , synchronous transfer
teen dword bursts across the PCI bus interface to
rates up to 10 MB/s, and asynchronous transfer
run efficiently without throttling the bus during
rates up to 7 MB/s on an 8-bit SCSI bus. The
PCI bus latency.
SCSI core can be programmed with SCSI
SCRIPTS, making it easy to fine tune the system
for specific mass storage devices or advanced SCSI
requirements.
SCRIPTS Processor
The SCSI core offers low-level register access or a The SCSI SCRIPTS processor allows both DMA
high-level control interface. Like first generation and SCSI commands to be fetched from host
SCSI devices, the SYM53C810A SCSI core can memory. Algorithms written in SCSI SCRIPTS
be accessed as a register-oriented device. The abil- control the actions of the SCSI and DMA cores
ity to sample and/or assert any signal on the SCSI and are executed from 32-bit system RAM. The
bus can be used in error recovery and diagnostic SCRIPTS processor executes complex SCSI bus
procedures. In support of loopback diagnostics, sequences independently of the host CPU.
the SCSI core can perform a self-selection and
The SCRIPTS processor can begin a SCSI I/O
operate as both an initiator and a target.
operation in approximately 500 ns. This compares
The SCSI core is controlled by the integrated with 2-8 ms required for traditional intelligent host
SCRIPTS processor through a high-level logical adapters. Algorithms may be designed to tune
interface. Commands controlling the SCSI core SCSI bus performance, to adjust to new bus device
are fetched out of the main host memory or local types (such as scanners, communication gateways,
memory. These commands instruct the SCSI core etc.), or to incorporate changes in the SCSI-2 or
to Select, Reselect, Disconnect, Wait for a Discon- SCSI-3 logical bus definitions without sacrificing
nect, Transfer Information, Change Bus Phases I/O performance. SCSI SCRIPTS are hardware
and, in general, implement all aspects of the SCSI independent, so they can be used interchangeably
protocol. The SCRIPTS processor is a special on any host or CPU system bus.
high-speed processor optimized for SCSI protocol.
A complete set of development tools is available for
writing custom drivers with SCSI SCRIPTS. For
more information on SCSI SCRIPTS instructions
supported by the SYM53C810A, see Chapter 6.

SDMS: The Total SCSI Solution
all recent modifications, the prefetch unit

SDMS: The Total SCSI flushes its contents and loads the modified
code every time a MMOV instruction is issued.
Solution To avoid inadvertently flushing the prefetch
unit contents, use the No Flush Memory to
For users who do not need to develop custom driv- Memory Move (NFMMOV) instruction for all
ers, Symbios Logic provides a total SCSI solution MMOV operations that do not modify code
in PC environments with the SCSI Device Man- within the next 4 to 8 dwords. For more
agement System (SDMS). SDMS provides BIOS information on this instruction, refer to
and driver support for hard disk, tape, and remov- Chapter 6.
able media peripherals for the major PC-based
operating systems. 2. On every Store instruction. The Store
instruction may also be used to place modified
SDMS includes a SCSI BIOS to manage all SCSI code directly into memory. To avoid
functions related to the device. It also provides a inadvertently flushing the prefetch unit
series of SCSI device drivers that support most contents, use the No Flush option for all Store
major operating systems. SDMS supports a multi- operations that do not modify code within the
threaded I/O application programming interface next 8 dwords.
(API) for user-developed SCSI applications.
SDMS supports both the ASPI and CAM SCSI 3. On every write to the DSP register.
software specifications. 4. On all Transfer Control instructions when the
transfer conditions are met. This is necessary
because the next instruction to be executed is
Prefetching SCRIPTS not the sequential next instruction in the
Instructions prefetch unit.
5. When the Pre-Fetch Flush bit (DCNTL bit 5)
When enabled (by setting the Prefetch Enable bit is set. The unit flushes whenever this bit is set.
in the DCNTL register), the prefetch logic in the The bit is self-clearing.
SYM53C810A fetches 4 or 8 dwords of instruc-
tions. The prefetch logic automatically determines
the maximum burst size that it can perform, based Op Code Fetch
on the burst length as determined by the values in Burst Capability
the DMODE register and the PCI Cache Line Size
register (if cache mode is enabled). If the unit can- Setting the Burst Op Code Fetch Enable bit in the
not perform bursts of at least four dwords, it will DMODE register (38h) causes the SYM53C810A
disable itself. to burst in the first two dwords of all instruction
fetches. If the instruction is a memory-to-memory
The SYM53C810A may flush the contents of the move, the third dword will be accessed in a sepa-
prefetch unit under certain conditions, listed rate ownership. If the instruction is an indirect
below, to ensure that the chip always operates from type, the additional dword will be accessed in a
the most current version of the software. When one subsequent bus ownership. If the instruction is a
of these conditions apply, the contents of the table indirect Block Move, the SYM53C810A will
prefetch unit are flushed automatically. use two accesses to obtain the four dwords
1. On every Memory Move instruction. The required, in two bursts of two dwords each.
Memory Move (MMOV) instruction is often Note: this feature can only be used if SCRIPTS
used to place modified code directly into pre-fetching is disabled.
memory. To make sure that the chip executes

PCI Cache Mode
PCI Cache Mode Parity Options

The SYM53C810A supports the PCI specification The SYM53C810A implements a flexible parity
for an 8-bit Cache Line Size register located in scheme that allows control of the parity sense,
PCI configuration space. The Cache Line Size reg- allows parity checking to be turned on or off, and
ister provides the ability to sense and react to non- has the ability to deliberately send a byte with bad
aligned addresses corresponding to cache line parity over the SCSI bus to test parity error recov-
boundaries. In conjunction with the Cache Line ery procedures. Table 2-1 defines the bits that are
Size register, the PCI commands Read Line, Read involved in parity control and observation.
Multiple, and Write and Invalidate are each soft- Table 2-2 describes the parity control function of
ware enabled or disabled to allow the user full flex- the Enable Parity Checking and Assert SCSI Even
ibility in using these commands. For more Parity bits in the SCNTL0 register. Table 2-3
information on PCI cache mode operations, refer describes the options available when a parity error
to Chapter 3. occurs.
Load/Store Instructions
The SYM53C810A supports the Load/Store
instruction type, which simplifies the movement of
data between memory and the internal chip regis-
ters. It also enables the SYM53C810A to transfer
bytes to addresses relative to the DSA register. For
more information on the Load and Store instruc-
tions, refer to Chapter 6.
3.3 Volt/5 Volt PCI Interface

The SYM53C810A can attach directly to a 3.3.
Volt or a 5 Volt PCI interface, due to separate VDD
pins for the PCI bus drivers. This allows the
devices to be used on the universal board recom-
mended by the PCI Special Interest Group.
Loopback Mode
The SYM53C810A loopback mode allows testing
of both initiator and target functions and, in effect,
lets the chip communicate with itself. When the
Loopback Enable bit is set in the STEST1 register,
the SYM53C810A allows control of all SCSI sig-
nals, whether it is operating in initiator or target
mode. For more information on this mode of oper-
ation, refer to the SYM53C8XX Family Program-
ming Guide.

Parity Options
Table 2-1: Bits Used for Parity Control and Observation
BIt Name Location Description

Assert SATN/ on SCNTL0, Bit 1 Causes the SYM53C810A to automatically assert SATN/ when
Parity Errors it detects a parity error while operating on the SCSI bus as an
initiator.
Enable Parity SCNTL0, Bit 3 Enables the SYM53C810A to check for parity errors on the
Checking SCSI bus. The SYM53C810A checks for odd parity.
Assert Even SCSI SCNTL1, Bit 2 Determines the SCSI parity sense generated by the
Parity SYM53C810A to the SCSI bus.
Disable Halt on SCNTL1, Bit 5 Causes the SYM53C810A not to halt operations when a SCSI
SATN/ or a Parity parity error is detected in target mode.
Error (Target Mode
Only)
Enable Parity Error SIEN0, Bit 0 Determines whether the SYM53C810A will generate an inter-
Interrupt rupt when it detects a SCSI parity error.
Parity Error SIST0, Bit 0 This status bit is set whenever the SYM53C810A has detected a
parity error on the SCSI bus.
Status of SCSI SSTAT0, Bit 0 This status bit represents the live SCSI Parity Signal (SDP).
Parity Signal
Latched SCSI Parity SSTAT1, Bit 3 This bit reflects the SCSI odd parity signal corresponding to the
data latched into the SIDL register
Master Parity Error CTEST4, Bit 3 Enables PCI parity checking during master data phases.
Enable
Master Data Parity DSTAT, Bit 6 Set when the SYM53C810A as a PCI master detects that a tar-
Error get device has signalled a parity error during a data phase.
Master Data Parity DIEN, Bit 6 By clearing this bit, a Master Data Parity Error will not cause
Error Interrupt IRQ/ to be asserted, but the status bit will be set in the DSTAT
Enable register.

Parity Options
Table 2-2: SCSI Parity Control
EPC AESP Description

0 0 Will not check for parity errors. Parity is generated when send-
ing SCSI data. Asserts odd parity when sending SCSI data.
0 1 Will not check for parity errors. Parity is generated when send-
ing SCSI data. Asserts even parity when sending SCSI data.
1 0 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts odd parity when sending SCSI
data.
1 1 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts even parity when sending
SCSI data.
Key:
EPC = Enable Parity Checking (bit 3 SCNTL0)
ASEP = Assert SCSI Even Parity (bit 2 SCNTL1)
Table 2-3: SCSI Parity Errors and Interrupts
DHP PAR Description

0 0 Will halt when a parity error occurs in target or initiator mode
and will NOT generate an interrupt.
0 1 Will halt when a parity error occurs in target mode and will gen-
erate an interrupt in target or initiator mode.
1 0 Will not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will not be generated.
1 1 Will not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will be generated.
Key: DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCNTL1) PAR = Parity Error (bit 0 SIEN0)
This table only applies when the Enable Parity Checking bit is set.

DMA FIFO
DMA FIFO
The DMA FIFO is divided into four sections, each one byte wide and 20 transfers deep. The DMA FIFO
is illustrated in Figure 2-1.
32 Bits Wide
20
Bytes
Deep
8 Bits 8 Bits 8 Bits 8 Bits

Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0
Figure 2-1: DMA FIFO Sections

DMA FIFO
Asynchronous SCSI Receive

Data Paths
1. Look at the DFIFO and DBC registers and
The data path through the SYM53C810A is calculate if there are bytes left in the DMA
dependent on whether data is being moved into or FIFO. To make this calculation, subtract the
out of the chip, and whether SCSI data is being seven least significant bits of the DBC register
transferred asynchronously or synchronously. from the 7-bit value of the DFIFO register.
Figure 2-2 shows how data is moved to/from the AND the result with 7Fh for a byte count
SCSI bus in each of the different modes. between 0 and 80.
The following steps determine if any bytes remain 2. Read bit 7 in the SSTAT0 register to
in the data path when the chip halts an operation: determine if any bytes are left in the SIDL
register. If bit 7 is set in SSTAT0, then the
Asynchronous SCSI Send SIDL register is full.
1. Look at the DFIFO and DBC registers and Synchronous SCSI Receive
calculate if there are bytes left in the DMA
FIFO. To make this calculation, subtract the 1. Subtract the seven least significant bits of the
seven least significant bits of the DBC register DBC register from the 7-bit value of the
from the 7-bit value of the DFIFO register. DFIFO register. AND the result with 7Fh for a
AND the result with 7Fh for a byte count byte count between 0 and 80.
between zero and 80. 2. Read the SSTAT1 register and examine bits 7-
2. Read bit 5 in the SSTAT0 register to 4, the binary representation of the number of
determine if any bytes are left in the SODL valid bytes in the SCSI FIFO, to determine if
register. If bit 5 is set in SSTAT0, then the any bytes are left in the SCSI FIFO.
SODL register is full.
Synchronous SCSI Send

1. Look at the DFIFO and DBC registers and
calculate if there are bytes left in the DMA
FIFO. To make this calculation, subtract the
seven least significant bits of the DBC register
from the 7-bit value of the DFIFO register.
AND the result with 7Fh for a byte count
between zero and 80.
2. Read bit 5 in the SSTAT0 register to
determine if any bytes are left in the SODL
SODL register is full.
3. Read bit 6 in the SSTAT0 register to
determine if any bytes are left in the SODR
SODR register is full.

DMA FIFO
PCI Interface PCI Interface PCI Interface PCI Interface
DMA FIFO DMA FIFO DMA FIFO DMA FIFO

(4 bytes x 20) (4 bytes x 20) (4 bytes x 20) (4 bytes x 20)
SODL Register SIDL Register SODL Register

SCSI FIFO
SCSI Interface SCSI Interface SODR Register

SCSI Interface
SCSI Interface
Asynchronous Asynchronous Synchronous Synchronous

SCSI Send SCSI Receive SCSI Send SCSI Receive
Figure 2-2: SYM53C810A Host Interface Data Paths

SCSI Bus Interface
SCSI Bus Interface (Re)Select During

(Re)Selection
The SYM53C810A supports single-ended opera- In multi-threaded SCSI I/O environments, it is not
tion only. All SCSI signals are active low. The uncommon to be selected or reselected while try-
SYM53C810A contains the single-ended output ing to perform selection/reselection. This situation
drivers and can be connected directly to the SCSI may occur when a SCSI controller (operating in
bus. Each output is isolated from the power supply initiator mode) tries to select a target and is rese-
to ensure that a powered-down SYM53C810A has lected by another. The Select SCRIPTS instruc-
no effect on an active SCSI bus (CMOS “voltage tion has an alternate address to which the
feed-through” phenomena). TolerANT technol- SCRIPTS will jump when this situation occurs.
ogy provides signal filtering at the inputs of SREQ/ The analogous situation for target devices is being
and SACK/ to increase immunity to signal reflec- selected while trying to perform a reselection.
tions.
Once a change in operating mode occurs, the initi-
ator SCRIPTS should start with a Set Initiator
Terminator instruction or the target SCRIPTS should start
Networks with a Set Target instruction. The Selection and
Reselection Enable bits (SCID bits 5 and 6,
The terminator networks provide the biasing
respectively) should both be set so that the
needed to pull signals to an inactive voltage level,
SYM53C810A may respond as an initiator or as a
and to match the impedance seen at the end of the
target. If only selection is enabled, the
cable with the characteristic impedance of the
SYM53C810A cannot be reselected as an initiator.
cable. Terminators must be installed at the extreme
There are also status and interrupt bits in the
ends of the SCSI chain, and only at the ends; no
SIST0 and SIEN0 registers, respectively, indicat-
system should ever have more or less than two ter-
ing that the SYM53C810A has been selected (bit
minators installed and active. SCSI host adapters
5) or reselected (bit 4).
should provide a means of accommodating termi-
nators. The terminators should be socketed, so
that if not needed they may be removed, or there
should be a means of disabling them with software.
Single-ended cables can use a 220 Ω pull-up to the
terminator power supply (Term-Power) line and a
330 Ω pull-down to Ground. Symbios recom-
mends active or regulated termination (also known
as Alt-2 or Alternative Two termination) to maxi-
mize the high performance of the SYM53C810A.
Figure 2-3 shows a Unitrode active terminator for
regulated termination. For additional information,
refer to the SCSI-2 Specification. TolerANT active
negation can be used with any ANSI-approved ter-
mination network.

SCSI Bus Interface
UC5601QP
2 20 SD0 (J1.2)
2.85V TERML1
REG_OUT 21 SD1 (J1.4)
TERML2
22 SD2 (J1.6)
TERML3
C1 C2 23 SD3 (J1.8)
TERML4
24 SD4 (J1.10)
TERML5
25 SD5 (J1.12)
TERML6
26 SD6 (J1.14)
TERML7
27 SD7 (J1.16)
TERML8
28 SD8 (J1.18)
TERML9
3 ATN (J1.32)
TERML10
4 BSY (J1.36)
TERML11
5 ACK (J1.38)
TERML12
6 RST (J1.40)
TERML13
7 MSG (J1.42)
TERML14
8 SEL (J1.44)
19 TERML15
DISCONNECT 9 C/D (J1.46)
TERML16
10 REQ (J1.48)
TERML17
11 I/O (J1.50)
TERML18
Key
C1 10 µF SMT
C2 0.1 µF SMT
J1 68-pin, high density “P” connector
Figure 2-3: Active or Regulated Termination

Synchronous Operation
For synchronous send, the output of the SCF

Synchronous Operation divider is divided by the transfer period (XFERP)
bits in the SCSI Transfer (SXFER) register. For
The SYM53C810A can transfer synchronous valid combinations of the SCF and the XFERP,
SCSI data in both initiator and target modes. The see Table 5-4 and Table 5-5, under the description
SXFER register controls both the synchronous off- of the XFERP bits 7-5 in the SXFER register.
set and the transfer period. It may be loaded by the
CPU before SCRIPTS execution begins, from SCNTL3 Register, bits 2–0 (CCF2–0)
within SCRIPTS via a Table Indirect I/O instruc-
tion, or with a Read-Modify-Write instruction. The CCF2-0 bits select the frequency of the
SCLK for asynchronous SCSI operations. To meet
The SYM53C810A can receive data from the the SCSI timings as defined by the ANSI specifica-
SCSI bus at a synchronous transfer period as short tion, these bits need to be set properly.
as 80 ns or 160 ns (with a 50 MHz clock), regard-
less of the transfer period used to send data. The SXFER Register, bits 7–5 (TP2–0)
SYM53C810A can receive data at one-fourth of
the divided SCLK frequency. Depending on the The TP2-0 divider (XFERP) bits determine the
SCLK frequency, the negotiated transfer period, SCSI synchronous send rate in either initiator or
and the synchronous clock divider, the target mode. This value further divides the output
SYM53C810A can send synchronous data at from the SCF divider.
intervals as short as 100 ns for fast SCSI-2 and
200 ns for SCSI-1. Achieving Optimal SCSI Send Rates
To achieve optimal synchronous SCSI send tim-
ings, the SCF divisor value should be set high, to
Determining the divide the clock as much as possible before pre-
Data Transfer Rate senting the clock to the TP divider bits in the
Synchronous data transfer rates are controlled by SXFER register. The TP2-0 divider value should
bits in two different registers of the be as low as possible. For example, with 40 MHz
SYM53C810A. A brief description of the bits is clock to achieve a 5 MB/s send rate, the SCF bits
provided below. Figure 2-4 illustrates the clock can be set to divide by 1 and the TP bits to divide
division factors used in each register, and the role by 8; or the SCF bits can be set to divide by 2 and
of the register bits in determining the transfer rate. the TP bits set to divide by 4. Use the second
option to achieve optimal SCSI timings.
SCNTL3 Register, bits 6–4 (SCF2–0)
The SCF2-0 bits select the factor by which the fre-
quency of SCLK is divided before being presented
to the synchronous SCSI control logic. The output
from this divider controls the rate at which data
can be received; this rate must not exceed 50
MHz. The receive rate is 1/4 of the divider output.
For example, if SCLK is 40MHz and the SCF
value is set to divide by one, then the maximum
rate at which data can be received is 10 MB/s (40/
(1*4) = 10).

Synchronous Operation
SCF XFERP
SCF2 SCF1 SCF0 TP2 TP1 TP0
Divisor Divisor
0 0 1 1 0 0 0 4
0 1 0 1.5 0 0 1 5
0 1 1 2 0 1 0 6
1 0 0 3 0 1 1 7
0 0 0 3 1 0 0 8
1 0 1 9
1 1 0 10
1 1 1 11
Divide by 4 Receive
This point- Clock
SCF must not Synchronous Send Clock
Divider exceed 50 Divider (to SCSI bus)
SCLK MHz
CCF Asynchronous
Divider SCSI Logic
SCSI Clock
CCF2 CCF1 CCF0
(MHz)
0 0 0 50.1-66.00 Example:
0 0 1 16.67-25.00
SCLK= 40 MHz, SCF=1(/1), XFERP=0(/4),
0 1 0 25.01-37.50 CCF=3(37.51-50.00 MHz)
0 1 1 37.51-50.00 Synchronous send rate=(SCLK/SCF)/XFERP=
1 0 0 50.01-66.00 (40/1)/4= 10 MB/s
Synchronous receive rate=(SCLK/SCF) / 4=(40/1)/4= 10 MB/s
Figure 2-4: Determining the Synchronous Transfer Rate

Interrupt Handling
ISTAT register is set, then a SCSI-type interrupt

Interrupt Handling has occurred and the SIST0 and SIST1 registers
should be read. If the DIP bit in the ISTAT regis-
The SCRIPTS processor in the SYM53C810A ter is set, then a DMA-type interrupt has occurred
performs most functions independently of the host and the DSTAT register should be read. SCSI-
microprocessor. However, certain interrupt situa- type and DMA-type interrupts may occur simulta-
tions must be handled by the external micropro- neously, so in some cases both SIP and DIP may
cessor. This section explains all aspects of be set.
interrupts as they apply to the SYM53C810A.
SIST0 and SIST1
Polling and The SIST0 and SIST1 registers contain the SCSI-
Hardware Interrupts type interrupt bits. Reading these registers will
determine which condition or conditions caused
The external microprocessor is informed of an the SCSI-type interrupt, and will clear that SCSI
interrupt condition by polling or hardware inter- interrupt condition. If the SYM53C810A is receiv-
rupts. Polling means that the microprocessor must ing data from the SCSI bus and a fatal interrupt
continually loop and read a register until it detects condition occurs, the SYM53C810A will attempt
a bit set that indicates an interrupt. This method is to send the contents of the DMA FIFO to memory
the fastest, but it wastes CPU time that could be before generating the interrupt. If the
used for other system tasks. The preferred method SYM53C810A is sending data to the SCSI bus
of detecting interrupts in most systems is hardware and a fatal SCSI interrupt condition occurs, data
interrupts. In this case, the SYM53C810A will could be left in the DMA FIFO. Because of this
assert the Interrupt Request (IRQ/) line that will the DMA FIFO Empty (DFE) bit in DSTAT
interrupt the microprocessor, causing the micro- should be checked. If this bit is clear, set the CLF
processor to execute an interrupt service routine. A (Clear DMA FIFO) and CSF (Clear SCSI FIFO)
hybrid approach would use hardware interrupts for bits before continuing. The CLF bit is bit 2 in
long waits, and use polling for short waits. CTEST3. The CSF bit is bit 1 in STEST3.
DSTAT
Registers
The DSTAT register contains the DMA-type
The registers in the SYM53C810A that are used
interrupt bits. Reading this register will determine
for detecting or defining interrupts are the ISTAT,
which condition or conditions caused the DMA-
SIST0, SIST1, DSTAT, SIEN0, SIEN1,
type interrupt, and will clear that DMA interrupt
DCNTL, and DIEN.
condition. The DFE bit, bit 7 in DSTAT, is purely
a status bit; it will not generate an interrupt under
ISTAT any circumstances and will not be cleared when
The ISTAT is the only register that can be read. DMA interrupts will flush neither the DMA
accessed as a slave during SCRIPTS operation, nor SCSI FIFOs before generating the interrupt,
therefore it is the register that is polled when so the DFE bit in the DSTAT register should be
polled interrupts are used. It is also the first regis- checked after any DMA interrupt. If the DFE bit
ter that should be read when the IRQ/ pin has been is clear, then the FIFOs must be cleared by setting
asserted in association with a hardware interrupt. the CLF (Clear DMA FIFO) and CSF (Clear
The INTF (Interrupt on the Fly) bit should be the SCSI FIFO) bits, or flushed by setting the FLF
first interrupt serviced. It must be written to one to (Flush DMA FIFO) bit.
be cleared. This interrupt must be cleared before
servicing any other interrupts. If the SIP bit in the

Interrupt Handling
SIEN0 and SIEN1 configure the chip’s behavior when the SATN/
interrupt is enabled during target role operation.
The SIEN0 and SIEN1 registers are the interrupt
The Interrupt on the Fly interrupt is also non-
enable registers for the SCSI interrupts in SIST0
fatal, since SCRIPTS can continue when it occurs.
and SIST1.
The reason for non-fatal interrupts is to prevent
DIEN SCRIPTS from stopping when an interrupt occurs
that does not require service from the CPU. This
The DIEN register is the interrupt enable register
prevents an interrupt when arbitration is complete
for DMA interrupts in DSTAT.
(CMP set), when the SYM53C810A has been
selected or reselected (SEL or RSL set), when the
DCNTL initiator has asserted ATN (target mode: SATN/
When bit 1 in this register is set, the IRQ/ pin will active), or when the General Purpose or Hand-
not be asserted when an interrupt condition shake to Handshake timers expire. These inter-
occurs. The interrupt is not lost or ignored, but rupts do not require CPU intervention during
merely masked at the pin. Clearing this bit when high-level SCRIPTS operation.
an interrupt is pending will immediately cause the
IRQ/ pin to assert. As with any register other than
ISTAT, this register cannot be accessed except by a Masking
SCRIPTS instruction during SCRIPTS execution. Masking an interrupt means disabling or ignoring
that interrupt. Interrupts can be masked by clear-
ing bits in the SIEN0 and SIEN1 (for SCSI inter-
Fatal vs. Non-Fatal rupts) registers or the DIEN (for DMA interrupts)
Interrupts register. How the chip will respond to masked
A fatal interrupt, as the name implies, always interrupts depends on: whether polling or hard-
causes SCRIPTS to stop running. All non-fatal ware interrupts are being used; whether the inter-
interrupts become fatal when they are enabled by rupt is fatal or non-fatal; and whether the chip is
setting the appropriate interrupt enable bit. For operating in initiator or target role.
more information on interrupt masking, see the If a non-fatal interrupt is masked and that condi-
discussion on masking later in this section. All tion occurs, SCRIPTS will not stop, the appropri-
DMA interrupts (indicated by the DIP bit in ate bit in the SIST0 or SIST1 will still be set, the
ISTAT and one or more bits in DSTAT being set) SIP bit in the ISTAT will not be set, and the IRQ/
are fatal. pin will not be asserted. See the section on non-
Some SCSI interrupts (indicated by the SIP bit in fatal vs. fatal interrupts for a list of the non-fatal
the ISTAT and one or more bits in SIST0 or interrupts.
SIST1 being set) are non-fatal. When the If a fatal interrupt is masked and that condition
SYM53C810A is operating in initiator role, only occurs, then SCRIPTS will still stop, the appropri-
the Function Complete (CMP), Selected (SEL), ate bit in the DSTAT, SIST0, or SIST1 register
Reselected (RSL), General Purpose Timer Expired will be set, and the SIP or DIP bits in the ISTAT
(GEN), and Handshake to Handshake Timer will be set, but the IRQ/ pin will not be asserted.
Expired (HTH) interrupts are non-fatal. When
operating in target role CMP, SEL, RSL, Target When the chip is initialized, enable all fatal inter-
mode: SATN/ active (M/A), GEN, and HTH are rupts if you are using hardware interrupts. If a fatal
non-fatal. Refer to the description for the Disable interrupt is disabled and that interrupt condition
Halt on a Parity Error or SATN/ active (Target
Mode Only) (DHP) bit in the SCNTL1 register to

Interrupt Handling
occurs, SCRIPTS will halt and the system will set, there is a small timing window in which multi-
never know it unless it times out and checks the ple interrupts can occur but will not be stacked.
ISTAT after a certain period of inactivity. These could be multiple SCSI interrupts (SIP set),
multiple DMA interrupts (DIP set), or multiple
If you are polling the ISTAT instead of using hard-
SCSI and multiple DMA interrupts (both SIP and
ware interrupts, then masking a fatal interrupt will
DIP set).
make no difference since the SIP and DIP bits in
the ISTAT inform the system of interrupts, not the As previously mentioned, DMA interrupts will not
IRQ/ pin. attempt to flush the FIFOs before generating the
interrupt. It is important to set the Clear DMA
Masking an interrupt after IRQ/ is asserted will not
FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a
cause IRQ/ to be deasserted.
DMA interrupt occurs and the DMA FIFO Empty
(DFE) bit is not set. This is because any future
Stacked Interrupts SCSI interrupts will not be posted until the DMA
FIFO is clear of data. These ‘locked out’ SCSI
The SYM53C810A stacks interrupts if they occur interrupts will be posted as soon as the DMA
one after another. If the SIP or DIP bits in the FIFO is empty.
ISTAT register are set (first level), then there is
already at least one pending interrupt, and any
future interrupts will be stacked in extra registers Halting in an
behind the SIST0, SIST1, and DSTAT registers Orderly Fashion
(second level). When two interrupts have occurred
and the two levels of the stack are full, any further When an interrupt occurs, the SYM53C810A will
interrupts will set additional bits in the extra regis- attempt to halt in an orderly fashion.
ters behind SIST0, SIST1, and DSTAT. When the ■ If the interrupt occurs in the middle of an
first level of interrupts are cleared, all the inter- instruction fetch, the fetch will be completed,
rupts that came in afterward will move into the except in the case of a Bus Fault. Execution
SIST0, SIST1, and DSTAT. After the first inter- will not begin, but the DSP will point to the
rupt is cleared by reading the appropriate register, next instruction since it is updated when the
the IRQ/ pin will be deasserted for a minimum of current instruction is fetched.
three CLKs; the stacked interrupt(s) will move
into the SIST0, SIST1, or DSTAT; and the IRQ/ ■ If the DMA direction is a write to memory and
pin will be asserted once again. a SCSI interrupt occurs, the SYM53C810A
will attempt to flush the DMA FIFO to
Since a masked non-fatal interrupt will not set the memory before halting. Under any other
SIP or DIP bits, interrupt stacking will not occur. circumstances only the current cycle will be
A masked, non-fatal interrupt will still post the completed before halting, so the DFE bit in
interrupt in SIST0, but will not assert the IRQ/ DSTAT should be checked to see if any data
pin. Since no interrupt is generated, future inter- remains in the DMA FIFO.
rupts will move right into the SIST0 or SIST1
instead of being stacked behind another interrupt. ■ SCSI SREQ/SACK handshakes that have
When another condition occurs that generates an begun will be completed before halting.
interrupt, the bit corresponding to the earlier ■ The SYM53C810A will attempt to clean up
masked non-fatal interrupt will still be set. any outstanding synchronous offset before
A related situation to interrupt stacking is when halting.
two interrupts occur simultaneously. Since stack- ■ In the case of Transfer Control Instructions,
ing does not occur until the SIP or DIP bits are once instruction execution begins it will
continue to completion before halting.

Interrupt Handling
■ If the instruction is a JUMP/CALL WHEN/IF 6. When using polled interrupts, go back to step
<phase>, the DSP will be updated to the 1 before leaving the interrupt service routine,
transfer address before halting. in case any stacked interrupts moved in when
the first interrupt was cleared. When using
■ All other instructions may halt before
hardware interrupts, the IRQ/ pin will be
completion.
asserted again if there are any stacked
interrupts. This should cause the system to re-
Sample Interrupt enter the interrupt service routine.
Service Routine
The following is a sample of an interrupt service
routine for the SYM53C810A. It can be repeated
if polling is used, or should be called when the
IRQ/ pin is asserted if hardware interrupts are
used.
1. Read ISTAT.
2. If the INTF bit is set, it must be written to a
one to clear this status.
3. If only the SIP bit is set, read SIST0 and
SIST1 to clear the SCSI interrupt condition
and get the SCSI interrupt status. The bits in
the SIST0 and SIST1 tell which SCSI
interrupt(s) occurred and determine what
action is required to service the interrupt(s).
4. If only the DIP bit is set, read the DSTAT to
clear the interrupt condition and get the DMA
interrupt status. The bits in the DSTAT will
tell which DMA interrupt(s) occurred and
determine what action is required to service
the interrupt(s).
5. If both the SIP and DIP bits are set, read
SIST0, SIST1, and DSTAT to clear the SCSI
and DMA interrupt condition and get the
interrupt status. If using 8-bit reads of the
SIST0, SIST1, and DSTAT registers to clear
interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts
clear properly. Both the SCSI and DMA
interrupt conditions should be handled before
leaving the ISR. It is recommended that the
DMA interrupt be serviced before the SCSI
interrupt, because a serious DMA interrupt
condition could influence how the SCSI
interrupt is acted upon.

PCI Addressing
Chapter 3
SYM53C810A compares its assigned base

PCI Addressing addresses with the value on the Address/Data bus
during the PCI address phase. If there is a match
There are three types of PCI-defined address of the upper 24 bits, the access is for the
space: SYM53C810A and the low order eight bits define
the register to be accessed. A decode of C_BE/ (3-
■ Configuration space
0) determines which registers and what type of
■ Memory space access is to be performed.
■ I/O space PCI defines memory space as a contiguous 32-bit
memory address that is shared by all system
Configuration space is a contiguous 256-byte set of
resources, including the SYM53C810A. Base
addresses dedicated to each “slot” or “stub” on the
Address Register One determines which 256-byte
bus. Decoding C_BE/(3-0) determines if a PCI
memory area this device will occupy.
cycle is intended to access configuration register
space. The IDSEL bus signal is a chip select that PCI defines I/O space as a contiguous 32-bit I/O
allows access to the configuration register space address that is shared by all system resources,
only. Any attempt to access configuration space including the SYM53C810A. Base Address Regis-
will be ignored unless IDSEL is asserted. The eight ter Zero determines which 256-byte I/O area this
lower order address lines and byte enables are used device will occupy.
to select a specific 8-bit register. The host proces-
sor uses this configuration space to initialize the
SYM53C810A. Figure 3-1 contains a list of the PCI Bus Commands and
PCI configuration registers supported in the
SYM53C810A. Functions Supported
The lower 128 bytes of the SYM53C810A config- Bus commands indicate to the target the type of
uration space hold system parameters while the transaction the master is requesting. Bus com-
upper 128 bytes map into the SYM53C810A mands are encoded on the C_BE/(3-0) lines dur-
operating registers. For all PCI cycles except con- ing the address phase. PCI bus command
figuration cycles, the SYM53C810A registers are encoding and types appear in Table 3-1.
located on the 256-byte block boundary defined by
the base address assigned through the configured The I/O Read command is used to read data from
register. The SYM53C810A operating registers are an agent mapped in I/O address space. All 32
available in both the upper and lower 128-byte address bits are decoded.
portions of the 256-byte space selected. The I/O Write command is used to write data to an
At initialization time, each PCI device is assigned a agent when mapped in I/O address space. All 32
base address (in the case of the SYM53C810A, the address bits are decoded.
upper 24 bits of the address are used) for memory
accesses and I/O accesses. On every access, the

PCI Cache Mode
The Memory Read, Memory Read Multiple, and Note: the SYM53C810A will not automatically
Memory Read Line commands are used to read use the value in the PCI Cache Line Size
data from an agent mapped in memory address register as the cache line size value. The
space. All 32 address bits are decoded. chip scales the value of the Cache Line Size
register down to the nearest binary burst
The Memory Write and Memory Write and Invali-
size allowed by the chip (2, 4, 8 or 16),
date commands are used to write data to an agent
compares this value to the DMODE burst
when mapped in memory address space. All 32
size, then selects the smallest as the value
address bits are decoded.
for the cache line size. The SYM53C810A
will use this value for all burst data
transfers.
PCI Cache Mode
The SYM53C810A supports the PCI specification Alignment
for an 8-bit Cache Line Size register located in
PCI configuration space. The Cache Line Size reg- The SYM53C810A uses the calculated burst size
ister provides the ability to sense and react to non- value to monitor the current address for alignment
aligned addresses corresponding to cache line to the cache line size. When it is not aligned the
boundaries. In conjunction with the Cache Line chip disables bursting, allowing only single dword
Size register, the PCI commands Read Line, Read transfers until a cache line boundary is reached.
Multiple, and Write and Invalidate are each soft- When the chip is aligned, bursting is re-enabled it
ware enabled or disabled to allow the user full flex- will burst in increments specified by the Cache
ibility in using these commands. Line Size register as explained above. If the Cache
Line Size register is not set (default = 00h), the
DMODE burst size is automatically used as the
Support for PCI cache line size.
Cache Line Size Register
The SYM3C810A supports the PCI specification MMOV
for an 8-bit Cache Line Size register in PCI config- Misalignment
uration space; it can sense and react to non-aligned
addresses corresponding to cache line boundaries. The SYM53C810A will not operate in a cache
alignment mode when a MMOV instruction is
issued and the read and write addresses are differ-
Selection of Cache ent distances from the nearest cache line bound-
Line Size ary. For example, if the read address is 0x21F and
the write address is 0x42F, and the cache line size
The cache logic will select a cache line size based is eight (8), the addresses are byte aligned, but they
on the values for the burst size in the DMODE are not the same distance from the nearest cache
register and the PCI Cache Line Size register. boundary. The read address is 1 byte from the
cache boundary 0x220 and the write address is 17
bytes from the cache boundary 0x440. In this situ-
ation, the chip will not align to cache boundaries
and will operate as an SYM53C810.

PCI Cache Mode
Multiple Cache Transfers

Memory Write
When multiple cache lines of data have been
and Invalidate Command
read in during a MMOV instruction (See the
The Memory Write and Invalidate command is description for the Read Multiple command),
identical to the Memory Write command, except the SYM53C810A will issue a Write and Inval-
that it additionally guarantees a minimum transfer idate command using the burst size necessary
of one complete cache line; i.e., the master intends to transfer all the data in one transfer. For
to write all bytes within the addressed cache line in example, if the cache line size is 4, and the chip
a single PCI transaction unless interrupted by the read in 16 dwords of data using a Read Multi-
target. This command requires implementation of ple command, the chip will switch the burst
the PCI Cache Line Size register at address 0Ch in size to 16, and issue a Write and Invalidate to
PCI configuration space. The SYM53C810A transfer all 16 dwords in one bus ownership.
enables Memory Write and Invalidate cycles when
bit 0 in the CTEST3 register (WRIE) and bit 4 in Latency
the PCI Command register are set. This will cause
Memory Write and Invalidate commands to be In accordance with the PCI specification, the
issued when the following conditions are met: chip's latency timer will be ignored when issuing a
Write and Invalidate command such that when a
1. The CLSE bit, WRIE bit, and PCI Config latency time-out has occurred, the SYM53C810A
Command register, bit 4 must be set. will continue to transfer up until a cache line
2. The cache line size register must contain a boundary. At that point, the chip will relinquish
legal burst size (2, 4, 8 or 16) value AND that the bus, and finish the transfer at a later time using
value must be less than or equal to the another bus ownership. If the chip is transferring
DMODE burst size. multiple cache lines it will continue to transfer
until the next cache boundary is reached.
3. The chip must have enough bytes in the DMA
FIFO to complete at least one full cache line PCI Target Retries
burst.
During a Write and Invalidate transfer, if the target
4. The chip must be aligned to a cache line device issues a retry (STOP with no TRDY, indi-
boundary. cating that no data was transferred), the
When these conditions have been met, the SYM53C810A will relinquish the bus and imme-
SYM53C810A will issue a Write and Invalidate diately try to finish the transfer on another bus
command instead of a Memory Write command ownership. The chip will issue another Write and
during all PCI write cycles. Invalidate command on the next ownership, in
accordance with the PCI specification.
PCI Target Disconnect

During a Write and Invalidate transfer, if the target
device issues a disconnect the SYM53C810A will
relinquish the bus and immediately try to finish the
transfer on another bus ownership. The chip will
not issue another Write and Invalidate command
on the next ownership.

PCI Cache Mode
4. The chip must be aligned to a cache line

Memory Read boundary.
Line Command When these conditions have been met, the chip
This command is identical to the Memory Read will issue a Read Line command instead of a
command, except that it additionally indicates that Memory Read during all PCI read cycles. Other-
the master intends to fetch a complete cache line. wise, it will issue a normal Memory Read com-
This command is intended to be used with bulk mand.
sequential data transfers where the memory system
and the requesting master might gain some perfor-
mance advantage by reading up to a cache line Memory Read
boundary rather than a single memory cycle.The Multiple Command
Read Line Mode function that exists in the previ- This command is identical to the Memory read
ous SYM53C8XX chips has been modified in the command except that it additionally indicates that
SYM53C810A to reflect the PCI cache line size the master may intend to fetch more than one
register specifications. The functionality of the cache line before disconnecting. The
Enable Read Line bit (bit 3 in DMODE) has been SYM53C810A supports PCI Read Multiple func-
modified to more resemble the Write and Invali- tionality and will issue Read Multiple commands
date mode in terms of conditions that must be met on the PCI bus when the Read Multiple Mode is
before a Read Line command will be issued. How- enabled. This mode is enabled by setting bit 2 of
ever, the Read Line option will operate exactly like the DMODE register (ERMP). The command will
the previous SYM53C8XX chips when cache be issued when certain conditions have been met.
mode has been disabled by a CLSE bit reset or
when certain conditions exist in the chip If cache mode has been enabled, a Read Multiple
(explained below). command will be issued on all read cycles, except
op code fetches, when the following conditions
The Read Line mode is enabled by setting bit 3 in have been met:
the DMODE register. If cache mode is disabled,
Read Line commands will be issued on every read 1. The CLSE and ERMP bits must be set.
data transfer, except op code fetches, as in previ- 2. The Cache Line Size register must contain a
ous SYM53C8XX chips. legal burst size value (2, 4, 8 or 16) AND that
If cache mode has been enabled, a Read Line com- value must be less than or equal to the
mand will be issued on all read cycles, except op DMODE burst size.
code fetches, when the following conditions have 3. The number of bytes to be transferred at the
been met: time a cache boundary has been reached must
1. The CLSE and Enable Read Line bits must be be equal to or greater than the DMODE burst
set. size.
2. The Cache Line Size register must contain a 4. The chip must be aligned to a cache line
legal burst size value (2, 4, 8 or 16) AND that boundary.
value must be less than or equal to the When these conditions have been met, the chip
DMODE burst size. will issue a Read Multiple command instead of a
Memory Read during all PCI read cycles.
3. The number of bytes to be transferred at the
time a cache boundary has been reached must
be equal to or greater than a full cache line
size.

PCI Cache Mode
Burst Size Selection met. Instead, a Read Multiple command will be

issued, even though the conditions for Read Line
The Read Multiple command reads in multiple
have been met.
cache lines of data in a single bus ownership. The
number of cache lines to be read is determined by If the Read Multiple mode is enabled and the Read
the DMODE burst size bits. In other words, the Line mode has been disabled, Read Multiple com-
chip will switch its normal operating burst size to mands will still be issued if the Read Multiple con-
reflect the DMODE burst size settings for the ditions are met.
Read Multiple command. For example, if the
cache line size is 4, and the DMODE burst size is
16, the chip will switch the current burst size from Unsupported PCI
4 to 16, and issue a Read Multiple. After the trans- Commands
fer, the chip will then switch the burst size back to
The SYM53C810A does not respond to reserved
the normal operating burst size of 4.
commands, special cycle, dual address cycle, or
interrupt acknowledge commands as a slave. It will
Read Multiple with Read Line Enabled never generate these commands as a master.
When both the Read Multiple and Read Line
modes have been enabled, the Read Line com-
mand will not be issued if the above conditions are
Table 3-1: PCI Bus Commands and Encoding Types
C_BE(3-0) Command Type Supported as Master Supported as Slave

0000 Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Cycle Yes Yes
0011 I/O Write Cycle Yes Yes
0100 Reserved n/a
0101 Reserved n/a
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved n/a
1001 Reserved n/a
1010 Configuration Read No Yes
1011 Configuration Write No Yes
1100 Memory Read Multiple Yes No (defaults to 0110)
1101 Dual Address Cycle No No
1110 Memory Read Line Yes No (defaults to 0110)
1111 Memory Write and Invalidate Yes No (defaults to 0111)

Configuration Registers
For detailed information, refer to the PCI Specifi-

Configuration Registers cation.
Figure 3-1 shows the PCI configuration registers
The Configuration registers are accessible only by
implemented by the SYM53C810A. Addresses
system BIOS during PCI configuration cycles, and
40h through 7Fh are not defined.
are not available to the user at any time. No other
cycles, including SCRIPTS operations, can access All PCI-compliant devices, such as the
these registers. SYM53C810A, must support the Vendor ID,
Device ID, Command, and Status Registers. Sup-
The lower 128 bytes hold configuration data while
port of other PCI-compliant registers is optional.
the upper 128 bytes hold the SYM53C810A oper-
In the SYM53C810A, registers that are not sup-
ating registers, which are described in Chapter
ported are not writable and return all zeroes when
Five, “Operating Registers.” The operating regis-
read. Only those registers and bits that are cur-
ters can be accessed by SCRIPTS or the host pro-
rently supported by the SYM53C810A are
cessor.
described in this chapter. For more detailed infor-
Note: the configuration register descriptions are mation on PCI registers, please see the PCI Speci-
provided for general information only, to fication.
indicate which PCI configuration addresses
are supported in the SYM53C810A.
31 16 15 0
Device ID = 0001h Vendor ID = 1000h 00h
Status Command 04h
Class Code = 010000h Rev ID=01h 08h
Not Supported Header Type Latency Timer Cache Line Size 0Ch
Base Address Zero (I/O)* 10h
Base Address One (Memory)** 14h
Not Supported 18h
Not Supported 1Ch
Not Supported 20h
Not Supported 24h
Reserved 28h
Reserved 2Ch
Reserved 30h
Reserved 34h
Reserved 38h
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch
Figure 3-1: PCI Configuration Register Map

*I/O Base is supported
**Memory Base is supported
Note: Addresses 40h to 7Fh are not defined. All unsupported registers are not writable and will return all zeroes when read. Reserved
registers will also return zeroes when read.

more information on these conditions, refer to

Register 00h the section "Memory Write and Invalidate
Vendor ID Command" To enable Write and Invalidate
Read Only Mode, bit 0 in the CTEST3 register (Operat-
ing registers) must also be set.
This field identifies the manufacturer of the device.
Symbios Logic Vendor ID is 1000h. Bit 2 Enable Bus Mastering
This bit controls the SYM53C810A’s ability to
act as a master on the PCI bus. A value of zero
Register 02h disables the device from generating PCI bus
Device ID master accesses. A value of one allows the
Read Only SYM53C810A to behave as a bus master.
This field identifies the particular device. The The SYM53C810A must be a bus master in
SYM53C810A device ID is 0001h. order to fetch SCRIPTS instructions and
transfer data.
Bit 1 Enable Memory Space
Register 04h
This bit controls the SYM53C810A’s response
Command to memory space accesses. A value of zero dis-
Read/Write ables the device response. A value of one allows
The Command Register, illustrated in Figure 3-2, the SYM53C810A to respond to memory
provides coarse control over a device’s ability to space accesses at the address specified by Base
generate and respond to PCI cycles. When a zero is Address One .
written to this register, the SYM53C810A is logi- Bit 0 Enable I/O Space
cally disconnected from the PCI bus for all
This bit controls the SYM53C810A’s response
accesses except configuration accesses.
to I/O space accesses. A value of zero disables
In the SYM53C810A, bits 3, 5, 7, and 9 are not the response. A value of one allows the
implemented. Bits 10 through 15 are reserved. SYM53C810A to respond to I/O space
accesses at the address specified in Base
Bits 15-10 Reserved
Address Zero.
Bit 8 SERR/ Enable
This bit enables the SERR/ driver. SERR/ is
disabled when this bit is clear. The default
value of this bit is zero. This bit and bit 6 must
be set to report address parity errors.
Bit 6 Enable Parity Error Response
This bit allows the SYM53C810A to detect
parity errors on the PCI bus and report these
errors to the system. Only data parity checking
is enabled. The SYM53C810A always gener-
ates parity for the PCI bus.
Bit 4 Write and Invalidate Mode
This bit, when set, will cause Memory Write
and Invalidate cycles to be issued on the PCI
bus after certain conditions have been met. For

15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Not Implemented
SERR/ Enable
Not Implemented
Enable Parity Response
Not Implemented
Write and Invalidate Mode
Not Implemented
Enable Bus Mastering
Enable Memory Space
Enable I/O Space
Figure 3-2: Command Register Layout
Bit 14 Signaled System Error

Register 06h This bit is set whenever a device asserts the
Status SERR/ signal.
Read/Write
Bit 13 Master Abort (from Master)
The Status Register, illustrated in Figure 3-3, is
This bit should be set by a master device when-
used to record status information for PCI bus-
ever its transaction (except for Special Cycle) is
related events.
terminated with master-abort. All master
In the SYM53C810A, bits 0 through 4 are devices should implement this bit.
reserved and bits 5, 6, 7, and 11 are not imple-
Bit 12 Received Target Abort (from
mented by the SYM53C810A.
Master)
Reads to this register behave normally. Writes are This bit should be set by a master device when-
slightly different in that bits can be reset, but not ever its transaction is terminated with a target
set. A bit is reset whenever the register is written, abort. All master devices should implement
and the data in the corresponding bit location is a this bit.
one. For instance, to clear bit 15 and not affect any
other bits, write the value 8000h to the register.
Bit 15 Detected Parity Error (from Slave)
This bit will be set by the SYM53C810A
whenever it detects a data parity error, even if
parity error handling is disabled.

Bits 10-9 DEVSEL/ Timing Bit 8 Data Parity Reported

These bits encode the timing of DEVSEL/. This bit is set when the following three condi-
These are encoded as 00b for fast, 01b for tions are met: 1) The bus agent asserted
medium, 10b for slow, and 11b reserved. PERR/ itself or observed PERR/ asserted; 2)
These bits are read only and should indicate The agent setting this bit acted as the bus mas-
the slowest time that a device asserts DEVSEL/ ter for the operation in which the error
for any bus command except Configuration occurred; and 3) The Parity Error Response bit
Read and Configuration Write. The in the Command register is set.
SYM53C810A supports 01b.
Bits 7-6 Not Implemented
Bits 5-0 Reserved
15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
Detected Parity Error (from Slave)
Signaled System Error
Received Master Abort (from Master)
Received Target Abort (from Master)
Not Implemented
DEVSEL timing
00 = fast, 01 = medium, 10 = slow
Data Parity Reported
Not Implemented
Not Implemented
Not Implemented
Reserved
Reserved
Reserved
Reserved
Reserved
Figure 3-3: Status Register Layout

Register 08h Register 0Dh

Revision ID Latency Timer
Read Only Read/Write
This register specifies device and revision identifi- The Latency Timer register specifies, in units of
ers. In the SYM53C810A, the upper nibble is PCI bus clocks, the value of the Latency Timer for
0001b. The lower nibble represents the current this PCI bus master. The SYM53C810A supports
revision level of the device. It should have the same this timer. All eight bits are writable, allowing
value as the Chip Revision Level bits in the latency values of 0-255 PCI clocks. Use the follow-
CTEST3 register. ing equation to calculate an optimum latency value
for the SYM53C810A:
Register 09h Latency = 2 + (Burst Size * (typical wait states +1)).

Class Code Values greater than optimum are also acceptable.
Read Only
This register is used to identify the generic func-
tion of the device. The upper byte of this register is
a base class code, the middle byte is a subclass
code, and the lower byte identifies a specific regis-
ter-level programming interface. The value of this
register is 010000h, which indicates a SCSI con-
troller.
Register 0Ch
Cache Line Size
Read/Write
This register specifies the system cache line size in
units of 32-bit words. Cache mode is enabled and
disabled by the Cache Line Size Enable (CLSE)
bit, bit 7 in the DCNTL register. Setting this bit
causes the SYM53C810A to align to cache line
boundaries before allowing any bursting, except
during MMOVs in which the read and write
addresses are Burst Size boundary misaligned. For
more information, see “Support for PCI Cache
Line Size Register” on page 3-2.

Register 0Eh Register 3Dh

Header Type Interrupt Pin
Read Only Read Only
This register identifies the layout of bytes 10h This register tells which interrupt pin the device
through 3Fh in configuration space and also uses. Its value is set to 01h, for the INTA/ signal.
whether or not the device contains multiple func-
tions. The value of this register is 00h.
Register 3Eh
Min_Gnt
Register 10h Read Only
Base Address Zero (I/O)
Read/Write Register 3Fh
This 32-bit register has bit zero hardwired to one. Max_Lat
Bit 1 is reserved and must return a zero on all Read Only
reads, and the other bits are used to map the
These registers are used to specify the desired set-
device into I/O space.
tings for Latency Timer values. Min_Gnt is used to
specify how long a burst period the device needs.
Register 14h Max_Lat is used to specify how often the device
needs to gain access to the PCI bus. The value
Base Address One (Memory)
specified in these registers is in units of 0.25
Read/Write microseconds. Values of zero indicate that the
This register has bit 0 hardwired to zero. For device has no major requirements for the settings
detailed information on the operation of this regis- of Latency Timers. The SYM53C810A sets the
ter, refer to the PCI Specification. Min_Gnt register to 11h and the Max_Lat register
to 40h.
Register 3Ch
Interrupt Line
Read/Write
This register is used to communicate interrupt line
routing information. POST software will write the
routing information into this register as it initiates
and configures the system. The value in this regis-
ter tells which input of the system interrupt con-
troller(s) has been connected to the device’s
interrupt pin. Values in this register are specified by
system architecture.


Signal Descriptions
Chapter 4
Signal Descriptions
This chapter presents the SYM53C810A pin configuration and signal definitions using tables and
illustrations. Figure 4-1 is the pin diagram and Figure 4-2 is a functional signal grouping. The pin def-
initions are presented in Table 4-1 through Table 4-8. The SYM53C810A is pin-for-pin compatible
with the SYM53C810.
V DD -C
C_BE3/
IDSEL
Vss-C
V DD- I
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Vss-I
Vss-I
Vss-I
REQ/
GNT/
99 97 95 93 91 89 87 85 83 81
AD21 1 80 CLK
AD20 2 79 RST/
V DD- I 3 78 SERR/
AD19 4 77 V DD -S
V SS- I 5 76 SD0/
AD18 6 75 SD1/
AD17 7 74 SD2/
AD16 8 73 Vss-S
Vss-I 9 72 SD3/
C_BE2/ 10 71 SD4/
FRAME/ 11 70 SD5/
IRDY/ 12 69 SD6/
Vss-I 13 68 Vss-S
TRDY/ 14 67 SD7/
DEVSEL/ 15 SYM53C810A 66 SDP/
SATN/
V DD- I
STOP/
16
17
100-Pin QFP 65
64 SBSY/
V SS-I 18 63 Vss-S
PERR/ 19 62 SACK/
PAR 20 61 SRST/
C_BE1/ 21 60 SMSG/
V SS- I 22 59 SSEL/
AD15 23 58 Vss-S
AD14 24 57 SCD/
AD13 25 56 SREQ/
V SS-I 26 55 SIO/
AD12 27 54 V DD -S
V DD-I 28 53 MAC/_TESTOUT
AD11 29 52 TESTIN
AD10 30 51 SCLK
32 34 36 38 40 42 44 46 48 50
VSS -C
AD9
Vss-I
AD8
C_BE0/
AD7
AD6
Vss-I
AD5
AD4
AD3
AD2
Vss-I
AD1
AD0
VDD -C
IRQ/
GPIO0_FETCH/
GPIO1_MASTER/
VDD- I
Figure 4-1: SYM53C810A Pin Diagram
The decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. Capac-
itor values between 0.01 and 0.1µF should provide adequate noise isolation. Because of the number of high current drivers on the
SYM53C810A, a multi-layer PC board with power and ground planes is required.

Signal Descriptions
The PCI/SCSI pin definitions are organized into

the following functional groups: Power and
Ground, System, Address/Data, Interface Control,
Arbitration, Error Reporting, SCSI, and Optional
Interface. A slash (/) at the end of the signal name
indicates that the active state occurs when the sig-
nal is at a low voltage. When the slash is absent, the
signal is active at a high voltage.
There are four signal type definitions:
I Input, a standard input-only signal
O Totem Pole Output, a standard out-
put driver
T/S Tri-State, a bi-directional, tri-state
input/output pin
S/T/S Sustained Tri-state, an active low
tri-state signal owned and driven by
one and only one agent at a time
Table 4-1: Power and Ground Pins
Symbol Pin No. Description

VSS-I 5, 9, 13, 18, 22, 26, Power supplies to the PCI I/O pins
32, 37, 43, 87, 93, 99
VDD-I* 3, 16, 28, 40, 90 Power supplies to the PCI I/O pins
VSS-S 58, 63, 68, 73 Power supplies to the SCSI bus I/O pins
VDD-S 54, 77 Power supplies to the SCSI bus I/O pins
VSS-C 50, 81 Power supplies to the internal logic core
VDD-C 46, 84 Power supplies to the internal logic core
*These pins can accept a VDD source of 3.3 or 5 Volts. All other VDD pins must be supplied 5 Volts.

Signal Descriptions
SCLK
CLK
System SD7-0
SDP
RST SCSI
SCTRL/
AD31-0
Address and Data C_BE/3-0
PAR
FRAME/
TRDY/
Interface Control IRDY/

GPIO0_FETCH/
STOP/
DEVSEL/ GPIO1_MASTER/
IDSEL
REQ/
MAC/_TESTOUT Additional Interface
Arbitration
GNT/
IRQ/
TESTIN/
SERR/
Error Reporting PERR/
Figure 4-2: Functional Signal Grouping

Signal Descriptions
Table 4-2: System Pins
Symbol Pin No. Type Description

CLK 80 I Clock. Clock provides timing for all transactions on the PCI bus
and is an input to every PCI device. All other PCI signals are
sampled on the rising edge of CLK, and other timing parame-
ters are defined with respect to this edge. This clock can option-
ally be used as the SCSI core clock; however, the
SYM53C810A will not achieve fast SCSI transfer rates.
RST/ 79 I Reset. Reset forces the PCI sequencer of each device to a known
state. All t/s and s/t/s signals are forced to a high impedance
state, and all internal logic is reset. The RST/ input is synchro-
nized internally to the rising edge of CLK. The CLK input must
be active while RST/ is active to properly reset the device.
Table 4-3: Address and Data Pins

AD(31-0) 85, 86, 88, T/S Address/Data. Physical dword address and data are multiplexed
89, 91, 92, on the same PCI pins. During the first clock of a transaction,
94, 95, 98, AD(31-0) contain a physical byte address. During subsequent
100, 1, 2, 4, clocks, AD(31-0) contain data. A bus transaction consists of an
6, 7, 8, 23, address phase, followed by one or more data phases. PCI sup-
24, 25, 27, ports both read and write bursts. AD(7-0) define the least sig-
29, 30, 31, nificant byte, and AD(31-24) define the most significant byte.
33, 35, 36,
38, 39, 41,
42, 44, 45
C_BE/(3-0) 96, 10, 21, T/S Command/Byte Enable. Bus command and byte enables are mul-
34 tiplexed on the same PCI pins. During the address phase of a
transaction, C_BE(3-0)/ define the bus command. During the
data phase, C_BE(3-0)/ are used as byte enables. The byte
enables determine which byte lanes carry meaningful data.
C_BE/(0) applies to byte lane 0, and C_BE/(3) to byte lane 3.
PAR 20 T/S Parity. Parity is the even parity bit that protects the AD(31-0)
and C_BE/(3-0) lines. During address phase, both the address
and command bits are covered. During data phase, both data
and byte enables are covered.

Signal Descriptions
Table 4-4: Interface Control Pins

FRAME/ 11 S/T/S Cycle Frame. Cycle Frame is driven by the current master to indi-
cate the beginning and duration of an access. FRAME/ is asserted
to indicate a bus transaction is beginning. While FRAME/ is
asserted, data transfers continue. When FRAME/ is deasserted, the
transaction is in the final data phase or the bus is idle.
TRDY/ 14 S/T/S Target Ready. Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the transac-
tion. TRDY/ is used with IRDY/. A data phase is completed on any
clock when both TRDY/ and IRDY/ are sampled asserted. During a
read, TRDY/ indicates that valid data is present on AD(31-0). Dur-
ing a write, it indicates the target is prepared to accept data. Wait
cycles are inserted until both IRDY/ and TRDY/ are asserted
together.
IRDY/ 12 S/T/S Initiator Ready. Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the transac-
tion. This signal is used with TRDY/. A data phase is completed on
any clock when both IRDY/ and TRDY/ are sampled asserted. Dur-
ing a write, IRDY/ indicates that valid data is present on AD(31-0).
During a read, it indicates the master is prepared to accept data.
Wait cycles are inserted until both IRDY/ and TRDY/ are asserted
together.
STOP/ 17 S/T/S Stop. Stop indicates that the selected target is requesting the master
to stop the current transaction.
DEVSEL/ 15 S/T/S Device Select. Device Select indicates that the driving device has
decoded its address as the target of the current access. As an input,
it indicates to a master whether any device on the bus has been
selected.
IDSEL 97 I Initialization Device Select. Initialization Device Select is used as a
chip select in place of the upper 24 address lines during configura-
tion read and write transactions.
Table 4-5: Arbitration Pins

REQ/ 83 O Request. Request indicates to the arbiter that this agent desires to
use the PCI bus. This is a point-to-point signal. Every master has its
own REQ/.
GNT/ 82 I Grant. Grant indicates to the agent that access to the PCI bus has
been granted. This is a point-to-point signal. Every master has its
own GNT/.

Signal Descriptions
Table 4-6: Error Reporting Pins

PERR/ 19 S/T/S Parity Error. Parity Error may be pulsed active by an agent that
detects a parity error. PERR/ can be used by any agent to signal
data corruptions. However, on detection of a PERR/ pulse, the cen-
tral resource may generate a non-maskable interrupt to the host
CPU, which often implies the system will be unable to continue
operation once error processing is complete.
SERR/ 78 O System Error. This open drain output pin is used to report address
parity errors.
Table 4-7: SCSI Pins

SCLK 51 I SCSI Clock. SCLK is used to derive all SCSI-related timings. The
speed of this clock is determined by the application’s requirements;
in some applications SCLK may be sourced internally from the
PCI bus clock (CLK). If SCLK is internally sourced, then the
SCLK pin should be tied low.
SD(7-0), 67, 69, 70,71,72, I/O SCSI Data. SCSI Data includes the following data lines and parity
SDP 74, 75, 76, 66 signals: SD(7-0) (8-bit SCSI data bus), and SDP (SCSI data par-
ity bit).
SCTRL/ 57, 55, 60, 56, I/O SCSI Control. SCSI Control includes the following signals:
62, 64, 65, 61, 59 SCD/ SCSI phase line, command/data
SIO/ SCSI phase line, input/output
SMSG/ SCSI phase line, message
SREQ/ Data handshake signal from target device
SACK/ Data handshake signal from initiator device
SBSY/ SCSI bus arbitration signal, busy
SATN/ SCSI Attention, the initiator is requesting a message
out phase
SRST/ SCSI bus reset
SSEL/ SCSI bus arbitration signal, select device

Signal Descriptions
Table 4-8: Additional Interface Pins

TESTIN/ 52 I Test In. When this pin is driven low, the SYM53C810A connects all
inputs and outputs to an “AND tree.” The SCSI control signals
and data lines are not connected to the “AND tree.” The output of
the “AND tree” is connected to the Test Out pin. This allows man-
ufacturers to verify chip connectivity and determine exactly which
pins are not properly attached. When the TESTIN pin is driven
low, internal pull-ups are enabled on all input, output, and bidirec-
tional pins, all outputs and bidirectional signals will be tri-stated,
and the MAC/_TESTOUT pin will be enabled. Connectivity can
be tested by driving one of the SYM53C810A pins low. The MAC/
_TESTOUT pin should respond by also driving low.
GPIO0_ 48 I/O General Purpose I/O pin. Optionally, when driven low, indicates that
FETCH/ the next bus request will be for an op code fetch. This pin powers
up as a general purpose input.
This pin has two specific purposes in the Symbios Logic SDMS
software. SDMS uses it to toggle SCSI device LEDs, turning on
the LED whenever the SYM53C810A is on the SCSI bus. SDMS
drives this pin low to turn on the LED, or drives it high to turn off
the LED. This signal can also be used as data I/O for serial
EEPROM access. In this case it is used with the GPIO0 pin, which
serves as a clock. The pin can be controlled from PCI configuration
register 35h or observed from the GPREG operating register, at
address 07h.
GPIO1_ 49 I/O General Purpose I/O pin. Optionally, when driven low, indicates that
MASTER/ the SYM53C810A is bus master. This pin powers up as a general
purpose input.
Symbios Logic SDMS software supports use of this signal in serial
EPROM applications, when enabled, in combination with the
GPIO0 pin. When this signal is used as a clock for serial EEPROM
access, the GPIO1 pin serves as data, and the pin is controlled
from PCI configuration register 35h.
MAC_ 53 T/S Memory Access Control/Test Out. This pin can be programmed to
TESTOUT indicate local or system memory accesses (non-PCI applications).
It is also used to test the connectivity of the SYM53C810A signals
using an “AND tree” scheme. The MAC/_TESTOUT pin is only
driven as the Test Out function when the TESTIN/ pin is driven
low.
IRQ/ 47 O Interrupt. This signal, when asserted low, indicates that an inter-
rupting condition has occurred and that service is required from
the host CPU. The output drive of this pin is programmed as either
open drain with an internal weak pull-up or, optionally, as a totem
pole driver. Refer to the description of DCNTL Register, bit 3, for
additional information.

Signal Descriptions

Operating Registers
Chapter 5
Operating Registers
This section contains descriptions of all Note: the only register that the host CPU can
SYM53C810A operating registers. Table 5-1 sum- access while the SYM53C810A is
marizes the SYM53C810A operating register set. executing SCRIPTS is the ISTAT register;
Figure 5-1, the register map, lists registers by oper- attempts to access other registers will
ating and configuration addresses. The terms “set” interfere with the operation of the chip.
and “assert” are used to refer to bits that are pro- However, all operating registers are
grammed to a binary one. Similarly, the terms accessible with SCRIPTS. All read data is
“deassert,” “clear” and “reset” are used to refer to synchronized and stable when presented to
bits that are programmed to a binary zero. Any bits the PCI bus.
marked as reserved should always be written to ze-
Note: the SYM53C810A cannot fetch SCRIPTS
ro; mask all information read from them. Reserved
instructions from the operating register
bit functions may be changed at any time. Unless
space. Instructions must be fetched from
otherwise indicated, all bits in registers are active
system memory.
high, that is, the feature is enabled by setting the
bit. The bottom row of every register diagram
shows the default register values, which are enabled
after the chip is powered on or reset.
Table 5-1: Operating Register Addresses and Descriptions
Memory
PCI
or I/O
Configuration Read/Write Label Description
Address
Address
Offset
00 80 R/W SCNTL0 SCSI Control 0
04 84 R/W SCID SCSI Chip ID
05 85 R/W SXFER SCSI Transfer
06 86 R/W SDID SCSI Destination ID
07 87 R/W GPREG General Purpose Bits
08 88 R/W SFBR SCSI First Byte Received
09 89 R/W SOCL SCSI Output Control Latch
0A 8A R SSID SCSI Selector ID

Operating Registers
Table 5-1: Operating Register Addresses and Descriptions (Continued)
Memory
PCI
or I/O
Address
Address
Offset
0B 8B R/W SBCL SCSI Bus Control Lines
0C 8C R DSTAT DMA Status
0D 8D R SSTAT0 SCSI Status 0
0E 8E R SSTAT1 SCSI Status 1
0F 8F R SSTAT2 SCSI Status 2
10-13 90-93 R/W DSA Data Structure Address
14 94 R/W ISTAT Interrupt Status
15-17 95-97 Reserved
18 98 R/W CTEST0 Reserved
19 99 R/W CTEST1 Chip Test 1
1A 9A R CTEST2 Chip Test 2
1B 9B R CTEST3 Chip Test 3
1C-1F 9C-9F R/W TEMP Temporary Stack
20 A0 R/W DFIFO DMA FIFO
21 A1 R/W CTEST4 Chip Test 4
22 A2 R/W CTEST5 Chip Text 5
23 A3 R/W CTEST6 Chip Test 6
24-26 A4-A6 R/W DBC DMA Byte Counter
27 A7 R/W DCMD DMA Command
28-2B A8-AB R/W DNAD DMA Next Address for Data
2C-2F AC-AF R/W DSP DMA SCRIPTS Pointer
30-33 B0-B3 R/W DSPS DMA SCRIPTS Pointer Save
34-37 B4-B7 R/W SCRATCHA General Purpose Scratch Pad A
38 B8 R/W DMODE DMA Mode
39 B9 R/W DIEN DMA Interrupt Enable
3A BA R/W SBR Scratch Byte Register
3B BB R/W DCNTL DMA Control
3C-3F BC-BF R ADDER Sum output of internal adder
40 C0 R/W SIEN0 SCSI Interrupt Enable 0
41 C1 R/W SIEN1 SCSI Interrupt Enable 1
42 C2 R SIST0 SCSI Interrupt Status 0
43 C3 R SIST1 SCSI Interrupt Status 1
44 C4 R/W SLPAR SCSI Longitudinal Parity

Operating Registers
Table 5-1: Operating Register Addresses and Descriptions (Continued)
Memory
PCI
or I/O
Address
Address
Offset
45 C5 Reserved
46 C6 R/W MACNTL Memory Access Control
47 C7 R/W GPCNTL General Purpose Control
48 C8 R/W STIME0 SCSI Timer 0
49 C9 R/W STIME1 SCSI Timer 1
4A CA R/W RESPID Response ID
4B CB Reserved
4C CC R STEST0 SCSI Test 0
4D CD R STEST1 SCSI Test 1
4E CE R/W STEST2 SCSI Test 2
4F CF R/W STEST3 SCSI Test 3
50 D0 R SIDL SCSI Input Data Latch
51-53 D1-D3 Reserved
54 D4 R/W SODL SCSI Output Data Latch
55-57 D5-D7 Reserved
58 D8 R SBDL SCSI Bus Data Lines
59-5B D9-DB Reserved
5C-5F DC-DF R/W SCRATCHB General Purpose Scratch Pad B

Operating Registers
Mem I/O Config

SCNTL3 SCNTL2 SCNTL1 SCNTL0 00 80
GPREG SDID SXFER SCID 04 84
SBCL SSID SOCL SFBR 08 88
SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 8C
DSA 10 90
RESERVED ISTAT 14 94
CTEST3 CTEST2 CTEST1 RESERVED 18 98
TEMP 1C 9C
CTEST6 CTEST5 CTEST4 DFIFO 20 A0
DCMD DBC 24 A4
DNAD 28 A8
DSP 2C AC
DSPS 30 B0
SCRATCH A 34 B4
DCNTL SBR DIEN DMODE 38 B8
ADDER 3C BC
SIST1 SIST0 SIEN1 SIEN0 40 C0
GPCNTL MACNTL RESERVED SLPAR 44 C4
RESERVED RESPID STIME1 STIME0 48 C8
STEST3 STEST2 STEST1 STEST0 4C CC
RESERVED SIDL 50 D0
RESERVED SODL 54 D4
RESERVED SBDL 58 D8
SCRATCH B 5C DC
Figure 5-1: SYM53C810A Register Address Map

Operating Registers
Full Arbitration, Selection/Reselection

Register 00 (80)
1. The SYM53C810A waits for a bus free
SCSI Control Zero (SCNTL0)
condition.
Read/Write
2. It asserts SBSY/ and its SCSI ID (stored in
ARB1 ARB0 START WATN EPC RES AAP TRG
7 6 5 4 3 2 1 0
the SCID register) onto the SCSI bus.
Default>>>
3. If the SSEL/ signal is asserted by another
1 1 0 0 0 X 0 0
SCSI device or if the SYM53C810A
detects a higher priority ID, the
Bit 7 ARB1 (Arbitration mode bit 1) SYM53C810A will deassert BSY, deassert
its ID, and wait until the next bus free state
Bit 6 ARB0 (Arbitration mode bit 0) to try arbitration again.
4. The SYM53C810A repeats arbitration
until it wins control of the SCSI bus. When
ARB1 ARB0 Arbitration Mode
it has won, the Won Arbitration bit is set in
0 0 Simple arbitration the SSTAT0 register, bit 2.
0 1 Reserved
5. The SYM53C810A performs selection by
1 0 Reserved asserting the following onto the SCSI bus:
1 1 Full arbitration, selection/reselection SSEL/, the target’s ID (stored in the SDID
register), and the SYM53C810A’s ID
Simple Arbitration (stored in the SCID register).
1. The SYM53C810A waits for a bus free 6. After a selection is complete, the Function
condition to occur. Complete bit is set in the SIST0 register,
bit 6.
2. It asserts SBSY/ and its SCSI ID
(contained in the SCID register) onto the 7. If a selection time-out occurs, the Selection
SCSI bus. If the SSEL/ signal is asserted by Time-Out bit is set in the SIST1 register,
another SCSI device, the SYM53C810A bit 2.
will deassert SBSY/, deassert its ID and set
the Lost Arbitration bit (bit 3) in the Bit 5 START (Start sequence)
SSTAT0 register. When this bit is set, the SYM53C810A will
start the arbitration sequence indicated by the
3. After an arbitration delay, the CPU should Arbitration Mode bits. The Start Sequence bit
read the SBDL register to check if a higher is accessed directly in low-level mode; during
priority SCSI ID is present. If no higher SCSI SCRIPTS operations, this bit is con-
priority ID bit is set, and the Lost trolled by the SCRIPTS processor. An arbitra-
Arbitration bit is not set, the tion sequence should not be started if the
SYM53C810A has won arbitration. connected (CON) bit in the SCNTL1 register,
4. Once the SYM53C810A has won bit 4, indicates that the SYM53C810A is
arbitration, SSEL/ must be asserted via the already connected to the SCSI bus. This bit is
SOCL for a bus clear plus a bus settle delay automatically cleared when the arbitration
(1.2 µs) before a low level selection can be sequence is complete. If a sequence is aborted,
performed. bit 4 in the SCNTL1 register should be
checked to verify that the SYM53C810A did
not connect to the SCSI bus.

Operating Registers
Bit 4 WATN (Select with SATN/ on a start If the Assert SATN/ on Parity Error bit is
sequence) cleared or the Enable Parity Checking bit is
When this bit is set and the SYM53C810A is cleared, SATN/ will not be automatically
in initiator mode, the SATN/ signal will be asserted on the SCSI bus when a parity error is
asserted during SYM53C810A selection of a received.
SCSI target device. This is to inform the target
that the SYM53C810A has a message to send. Bit 0 TRG (Target role)
If a selection time-out occurs while attempting This bit determines the default operating role
to select a target device, SATN/ will be deas- of the SYM53C810A. The user must manually
serted at the same time SSEL/ is deasserted. set target or initiator role. This can be done
When this bit is clear, the SATN/ signal will using the SCRIPTS language (SET TARGET
not be asserted during selection. When execut- or CLEAR TARGET). When this bit is set, the
ing SCSI SCRIPTS, this bit is controlled by chip is a target device by default. When this bit
the SCRIPTS processor, but it may be set is cleared, the SYM53C810A is an initiator
manually in low level mode. device by default.
CAUTION:
Bit 3 EPC (Enable parity checking)
When this bit is set, the SCSI data bus is Writing this bit while not connected may cause the
checked for odd parity when data is received loss of a selection or reselection due to the chang-
from the SCSI bus in either initiator or target ing of target or initiator roles.
mode. If a parity error is detected, bit 0 of the
SIST0 register is set and an interrupt may be
generated.
If the SYM53C810A is operating in initiator
mode and a parity error is detected, SATN/
can optionally be asserted, but the transfer
continues until the target changes phase. When
this bit is cleared, parity errors are not
reported.
Bit 2 Reserved
Bit 1 AAP (Assert SATN/ on parity error)

When this bit is set, the SYM53C810A auto-
matically asserts the SATN/ signal upon detec-
tion of a parity error. SATN/ is only asserted in
initiator mode. The SATN/ signal is asserted
before deasserting SACK/ during the byte
transfer with the parity error. The Enable Par-
ity Checking bit must also be set for the
SYM53C810A to assert SATN/ in this man-
ner. A parity error is detected on data received
from the SCSI bus.

Operating Registers
between internal core cells. During synchro-

Register 01 (81) nous operation, the SYM53C810A transfers
SCSI Control One (SCNTL1) data until there are no outstanding synchro-
Read/Write nous offsets. If the SYM53C810A is receiving
EXC ADB DHP CON RST AESP IARB SST
data, any data residing in the DMA FIFO is
7 6 5 4 3 2 1 0 sent to memory before halting.
Default>>>
0 0 0 0 0 0 0 0
When this bit is set, the SYM53C810A does
not halt the SCSI transfer when SATN/ or a
parity error is received.
Bit 7 EXC (Extra clock cycle of data
setup)
Bit 4 CON (Connected)
When this bit is set, an extra clock period of
This bit is automatically set any time the
data setup is added to each SCSI data send
SYM53C810A is connected to the SCSI bus
transfer. The extra data setup time can provide
as an initiator or as a target. It is set after the
additional system design margin, though it will
SYM53C810A successfully completes arbitra-
affect the SCSI transfer rates. Clearing this bit
tion or when it has responded to a bus initiated
disables the extra clock cycle of data setup
selection or reselection. This bit is also set after
time. Setting this bit only affects SCSI send
the chip wins simple arbitration when operat-
operations.
ing in low level mode. When this bit is clear,
the SYM53C810A is not connected to the
Bit 6 ADB (Assert SCSI data bus)
SCSI bus.
When this bit is set, the SYM53C810A drives
the contents of the SCSI Output Data Latch The CPU can force a connected or discon-
Register (SODL) onto the SCSI data bus. nected condition by setting or clearing this bit.
When the SYM53C810A is an initiator, the This feature would be used primarily during
SCSI I/O signal must be inactive to assert the loopback mode.
SODL contents onto the SCSI bus. When the
SYM53C810A is a target, the SCSI I/O signal Bit 3 RST (Assert SCSI RST/ signal)
must be active for the SODL contents to be Setting this bit asserts the SRST/ signal. The
asserted onto the SCSI bus. The contents of SRST/ output remains asserted until this bit is
the SODL register can be asserted at any time, cleared. The 25 µs minimum assertion time
even before the SYM53C810A is connected to defined in the SCSI specification must be
the SCSI bus. This bit should be cleared when timed out by the controlling microprocessor or
executing SCSI SCRIPTS. It is normally used a SCRIPTS loop.
only for diagnostics testing or operation in low
level mode. Bit 2 AESP (Assert even SCSI parity
(force bad parity))
Bit 5 DHP (Disable Halt on Parity Error When this bit is set, the SYM53C810A asserts
or ATN) (Target Only) even parity. It forces a SCSI parity error on
The DHP bit is only defined for target role. each byte sent to the SCSI bus from the
When this bit is cleared, the SYM53C810A SYM53C810A. If parity checking is enabled,
halts the SCSI data transfer when a parity error then the SYM53C810A checks data received
is detected or when the SATN/ signal is for odd parity. This bit is used for diagnostic
asserted. If SATN/ or a parity error is received testing and should be clear for normal opera-
in the middle of a data transfer, the tion. It can be used to generate parity errors to
SYM53C810A may transfer up to three addi- test error handling functions.
tional bytes before halting to synchronize

Operating Registers
Bit 1 IARB (Immediate Arbitration) Bit 0 SST (Start SCSI Transfer)

Setting this bit causes the SCSI core to imme- This bit is automatically set during SCRIPTS
diately begin arbitration once a Bus Free phase execution, and should not be used. It causes
is detected following an expected SCSI discon- the SCSI core to begin a SCSI transfer, includ-
nect. This bit is useful for multi-threaded appli- ing SREQ/SACK handshaking. The determi-
cations. The ARB1-0 bits in SCNTL0 should nation of whether the transfer is a send or
be set for full arbitration and selection before receive is made according to the value written
setting this bit. to the I/O bit in SOCL. This bit is self-reset-
ting. It should not be set for low level opera-
Arbitration will be re-tried until won. At that
tion.
point, the SYM53C810A will hold BSY and
SEL asserted, and wait for a select or reselect CAUTION:
sequence to be requested. The Immediate
Writing to this register while not connected may
Arbitration bit will be reset automatically when
cause the loss of a selection/reselection by resetting
the selection or reselection sequence is com-
the Connected bit.
pleted, or times out. Interrupts will not occur
until after this bit is reset.
An unexpected disconnect condition will clear
IARB without attempting arbitration. See the
SCSI Disconnect Unexpected bit (SCNTL2,
bit 7) for more information on expected versus
unexpected disconnects.
An immediate arbitration sequence can be
aborted. First, the Abort bit in the ISTAT reg-
ister should be set. Then one of two things will
eventually happen:
1. The Won Arbitration bit (SSTAT0 bit 2)
will be set. In this case, the Immediate
Arbitration bit needs to be reset. This will
complete the abort sequence and
disconnect the SYM53C810A from the
SCSI bus. If it is not acceptable to go to
Bus Free phase immediately following the
arbitration phase, a low level selection may
be performed instead.
2. The abort will complete because the
SYM53C810A loses arbitration. This can
be detected by the Immediate Arbitration
bit being cleared. The Lost Arbitration bit
(SSTAT0 bit 3) should not be used to
detect this condition. No further action
needs to be taken in this case.

Operating Registers
Register 02 (82) Register 03 (83)

SCSI Control Two (SCNTL2) SCSI Control Three (SCNTL3)
Read/Write Read/Write
SDU RES RES RES RES RES RES RES RES SCF2 SCF1 SCF0 RES CCF2 CCF1 CCF0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Default>>> Default>>>
0 X X X X X X X X 0 0 0 X 0 0 0
Bit 7 SDU (SCSI Disconnect Unexpected) Bit 7 Reserved

This bit is valid in initiator mode only. When
this bit is set, the SCSI core is not expecting Bits 6-4 SCF2-0 (Synchronous Clock
the SCSI bus to enter the Bus Free phase. If it Conversion Factor)
does, an unexpected disconnect error will be These bits select the factor by which the fre-
generated (see the Unexpected Disconnect bit quency of SCLK is divided before being pre-
in the SIST0 register, bit 2). During normal sented to the synchronous SCSI control logic.
SCRIPTS mode operation, this bit is set auto- The bits are encoded as per Table 5-2, “Syn-
matically whenever the SCSI core is reselected, chronous Clock Conversion Factor,” on
or successfully selects another SCSI device. page 5-10. For synchronous receive, the output
The SDU bit should be reset with a register of this divider is always divided by 4 and that
write (MOVE 0X7f & SCNTL2 TO SCNTL2) value determines the transfer rate. For exam-
before the SCSI core expects a disconnect to ple, if SCLK is 40 MHz and the SCF value is
occur, normally prior to sending an Abort, set to divide by one, then the maximum syn-
Abort Tag, Bus Device Reset, Clear Queue or chronous receive rate is 10 Mb/s
Release Recovery message, or before deassert- ( 〈 40 ⁄ 1 ) ⁄ 4 = 10〉 .
ing SACK/ after receiving a Disconnect com-
For synchronous send, the output of this
mand or Command Complete message.
divider gets divided by the transfer period
(XFERP) bits in the SCSI Transfer (SXFER)
Bits 6-0 Reserved
register, and that value determines the transfer

Operating Registers
rate. For valid combinations of the SCF and

XFERP, see Table 5-4 and Table 5-5. Table 5-3: Asynchronous Clock Conversion
Factor
Table 5-2: Synchronous Clock Conversion
Factor CCF2 CCF1 CCF0 SCSI Clock (MHz)
SCF2 SCF1 SCF0 Factor Frequency 0 0 0 50.01-66.00
0 0 0 SCLK/3 0 0 1 16.67-25.00
0 0 1 SCLK/1 0 1 0 25.01-37.50
0 1 0 SCLK/1.5 0 1 1 37.51-50.00
0 1 1 SCLK/2 1 0 0 50.01-66.00
1 0 0 SCLK/3 1 0 1 Reserved
1 0 1 Reserved 1 1 0 Reserved
1 1 0 Reserved 1 1 1 Reserved
1 1 1 Reserved
Note: for additional information on how the

synchronous transfer rate is determined,
see “Synchronous Operation” on page 2-
11.
Bit 3 Reserved
Bits 2-0 CCF2-0 (Clock Conversion Factor

These bits select the frequency of the SCLK
for asynchronous SCSI operations. The bits are
encoded as per the following table. All other
combinations are reserved and should never be
used.

Operating Registers

SCSI Chip ID (SCID) SCSI Transfer (SXFER)
RES RRE SRE RES RES ENC2 ENC1 ENC0 TP2 TP1 TP0 RES MO3 MO2 MO1 MO0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X 0 0 X X 0 0 0 0 0 0 X 0 0 0 0
Note: when using Table Indirect I/O commands,

Bit 7 Reserved bits 7-0 of this register will be loaded from
the I/O data structure.
Bit 6 RRE (Enable Response to
Reselection) Note: for additional information on how the
When this bit is set, the SYM53C810A is synchronous transfer rate is determined,
enabled to respond to bus-initiated reselection refer to Chapter 2, “Functional
at the chip ID in the RESPID register. Note Description.”
that the SYM53C810A will not automatically
reconfigure itself to initiator mode as a result of Bits 7-5 TP2-0 (SCSI Synchronous Transfer
being reselected. Period)
These bits determine the SCSI synchronous
Bit 5 SRE (Enable Response to Selection) transfer period (XFERP) used by the
When this bit is set, the SYM53C810A is able SYM53C810A when sending synchronous
to respond to bus-initiated selection at the chip SCSI data in either initiator or target mode.
ID in the RESPID register. Note that the These bits control the programmable dividers
SYM53C810A will not automatically reconfig- in the chip.
ure itself to target mode as a result of being
selected.
TP2 TP1 TP0 XFERP
Bit 4-3 Reserved
0 0 0 4
Bits 2-0 Encoded SYM53C810A Chip SCSI 0 0 1 5
ID, bits 2-0 0 1 0 6
These bits are used to store the SYM53C810A 0 1 1 7
encoded SCSI ID. This is the ID which the
1 0 0 8
chip will assert when arbitrating for the SCSI
bus. The IDs that the SYM53C810A will 1 0 1 9
respond to when being selected or reselected 1 1 0 10
are configured in the RESPID register. The 1 1 1 11
priority of the 8 possible IDs, in descending
order is: Use the following formula to calculate the syn-
Highest Lowest chronous send and receive rates. Table 5-4 and
7 6 5 4 3 2 1 0 Table 5-5 show examples of possible bit com-
binations.

Operating Registers
Synchronous Send Rate = (SCLK/SCF)/XFERP

Synchronous Receive Rate = (SCLK/SCF) / 4
Key:
SCLK = SCLK
SCF = Synchronous Clock Conversion Factor, SCNTL3 bits
6-4
XFERP = Transfer period, SXFER register bits 7-5
Table 5-4: Examples of Synchronous Transfer Periods and Rates for SCSI-1
Synch
SCF (SCNTL3 XFERP (SXFER Sync Send Sync Send Sync Receive
SCLK (MHz) Receive
bits 6-4) bits 7-5) Rate (MB/s) Period (ns) Rate (MB/s)
Period (ns)
66.67 ÷3 4 5.55 180 5.55 180
66.67 ÷3 5 4.44 225 5.55 180
50 ÷2 4 6.25 160 6.25 160
50 ÷2 5 5 200 6.25 160
40 ÷2 4 5 200 5 200
37.50 ÷ 1.5 4 6.25 160 6.25 160
33.33 ÷ 1.5 4 5.55 180 5.55 180
25 ÷1 4 6.25 160 6.25 160
20 ÷1 4 5 200 5 200
16.67 ÷1 4 4.17 240 4.17 240
Table 5-5: Examples of Synchronous Transfer Periods and Rates for Fast SCSI
Synch
SCF (SCNTL3 XFERP (SXFER Sync Send Sync Send Sync Receive
SCLK (MHz) Receive
bits 6-4) bits 7-5) Rate (MB/s) Period (ns) Rate (MB/s)
Period (ns)
66.67 ÷ 1.5 4 11.11 90 11.11 90
66.67 ÷1 5 8.88 112.5 11.11 90
50 ÷1 4 12.5 80 12.5 80
50 ÷1 5 10 100 12.5 80
40 ÷1 4 10 100 10 100
37.50 ÷1 4 9.375 106.67 9.375 106.67
33.33 ÷1 4 8.33 120 8.33 120
25 ÷1 4 6.25 160 6.25 160
20 ÷1 4 5 200 5 200
16.67 ÷1 4 4.17 240 4.17 240

Operating Registers
Bit 4 Reserved
Register 06 (86)
Bits 3-0 MO4-MO0 (Max SCSI Synchronous SCSI Destination ID (SDID)
Offset) Read/Write
These bits describe the maximum SCSI syn- RES RES RES RES RES ENC2 ENC1 ENC0
chronous offset used by the SYM53C810A 7 6 5 4 3 2 1 0
when transferring synchronous SCSI data in Default>>>
either initiator or target mode. The following X X X X X 0 0 0
table describes the possible combinations and

their relationship to the synchronous data off- Bits 7-3 Reserved
set used by the SYM53C810A. These bits
determine the SYM53C810A’s method of Bits 2-0 Encoded destination SCSI ID
transfer for Data In and Data Out phases only; Writing these bits sets the SCSI ID of the
all other information transfers will occur asyn- intended initiator or target during SCSI rese-
chronously. lection or selection phases, respectively. When
executing SCRIPTS, the SCRIPTS processor
writes the destination SCSI ID to this register.
Table 5-6: SCSI Synchronous Offset Values The SCSI ID is defined by the user in a
SCRIPTS SELECT or RESELECT instruc-
Synchronous tion. The value written should be the binary-
MO3 MO2 MO1 MO0
Offset encoded ID value. The priority of the 8 possi-
0 0 0 0 0-Asynchronous ble IDs, in descending order, is:
0 0 0 1 1 Highest Lowest
7 6 5 4 3 2 1 0
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 X X 1 Reserved
1 X 1 X Reserved
1 1 X X Reserved

Operating Registers

General Purpose (GPREG) SCSI First Byte Received (SFBR)
RES RES RES RES RES RES GPIO1 GPIO0 1B7 1B6 1B5 1B4 1B3 1B2 1B1 1B0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X X X X X X 0 0 0 0 0 0 0 0 0 0
This register contains the first byte received in any

Bits 7-2 Reserved asynchronous information transfer phase. For ex-
ample, when the SYM53C810A is operating in ini-
Bits 1-0 GPIO1-GPIO0 (General Purpose) tiator role, this register contains the first byte
These bits can be programmed through the received in Message In, Status Phase, Reserved In
GPCNTL Register to become inputs, outputs, and Data In.
or, special functions. These signals can also be
programmed as live inputs and sensed through When a Block Move instruction is executed for a
a SCRIPTS Register to Register Move Instruc- particular phase, the first byte received is stored in
tion. GPIO(1-0) default as inputs. When con- this register—even if the present phase is the same
figured as inputs, an internal pull-up is as the last phase. The first byte-received value for a
enabled. particular input phase is not valid until after a
MOVE instruction is executed.
The Symbios Logic SDMS software uses the
GPIO 0 pin to toggle SCSI device LEDs, turn- This register is also the accumulator for register
ing on the LED whenever the SYM53C810A read-modify-writes with the SFBR as the destina-
is connected to the SCSI bus. SDMS drives tion. This allows bit testing after an operation.
this pin low to turn on the LED, or drives it The SFBR can not be written to via the CPU, and
high to turn off the LED. therefore not by a Memory Move. Additionally, the
The GPIO 1-0 pins are used in SDMS to Load instruction cannot be used to write to this reg-
access serial NVRAM. When used for access- ister. However, the SFBR can be loaded via
ing serial NVRAM, GPIO 1 is used as a clock SCRIPTS Read/Write operations. To load the
with the GPIO 0 pin serving as data. SFBR with a byte stored in system memory, the
byte must first be moved to an intermediate
SYM53C810A register (such as the SCRATCH
register), and then to the SFBR.
This register will also contain the state of the lower
eight bits of the SCSI data bus during the selection
phase if the COM bit in the DCNTL register is
clear.

Operating Registers
Register 09 (89) Register 0A (8A)

SCSI Output Control Latch (SOCL) SCSI Selector ID (SSID)
Read /Write Read Only
REQ ACK BSY SEL ATN MSG C/D I/O VAL RES RES RES RES ENID2 ENID1 ENID0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 X X X X 0 0 0
Bit 7 REQ(Assert SCSI REQ/ signal) Bit 7 VAL (SCSI Valid Bit)
If VAL is asserted, the two SCSI IDs were
Bit 6 ACK(Assert SCSI ACK/ signal) detected on the bus during a bus-initiated
selection or reselection, and the encoded desti-
Bit 5 BSY(Assert SCSI BSY/ signal) nation SCSI ID bits below are valid. If VAL is
deasserted, only one ID was present and the
Bit 4 SEL(Assert SCSI SEL/ signal) contents of the encoded destination ID are
meaningless.
Bit 3 ATN(Assert SCSI ATN/ signal)
Bits 6-3 Reserved
Bit 2 MSG(Assert SCSI MSG/ signal)
Bits 2-0 Encoded Destination SCSI ID
Bit 1 C/D(Assert SCSI C_D/ signal) Reading the SSID register immediately after
the SYM53C810A has been selected or rese-
Bit 0 I/O(Assert SCSI I_O/ signal) lected returns the binary-encoded SCSI ID of
This register is used primarily for diagnostic testing the device that performed the operation. These
or programmed I/O operation. It is controlled by bits are invalid for targets that are selected
the SCRIPTS processor when executing SCSI under the single initiator option of the SCSI-1
SCRIPTS. SOCL should only be used when trans- specification. This condition can be detected
ferring data via programmed I/O. Some bits are set by examining the VAL bit above.
(1) or reset (0) when executing SCSI SCRIPTS.
Do not write to the register once the
SYM53C810A starts executing normal SCSI
SCRIPTS.

Operating Registers
Register 0B (8B) Register 0C (8C)

SCSI Bus Control Lines (SBCL) DMA Status (DSTAT)
Read Only Read Only
REQ ACK BSY SEL ATN MSG C/D I/O DFE MDPE BF ABRT SSI SIR RES IID
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X X X X X X X X 1 0 0 0 0 0 X 0
Reading this register will clear any bits that are set
Bit 7 REQ (SREQ/ status) at the time the register is read, but will not neces-
sarily clear the register because additional inter-
Bit 6 ACK (SACK/ status) rupts may be pending (the SYM53C810A stacks
interrupts). The DIP bit in the ISTAT register will
Bit 5 BSY (SBSY/ status) also be cleared. DMA interrupt conditions may be
individually masked through the DIEN register.
Bit 4 SEL (SSEL/ status)
When performing consecutive 8-bit reads of the
DSTAT, SIST0 and SIST1 registers (in any or-
Bit 3 ATN SATN/ status)
der), insert a delay equivalent to 12 CLK periods
between the reads to ensure that the interrupts clear
Bit 2 MSG (SMSG/ status)
properly. See Chapter 2, “Functional Description,”
for more information on interrupts.
Bit 1 C/D (SC_D/ status)
Bit 7 DFE (DMA FIFO empty)
Bit 0 I/O (SI_O/ status) This status bit is set when the DMA FIFO is
When read, this register returns the SCSI control empty. It may be used to determine if any data
line status. A bit will be set when the corresponding resides in the FIFO when an error occurs and
SCSI control line is asserted. These bits are not an interrupt is generated. This bit is a pure sta-
latched; they are a true representation of what is on tus bit and will not cause an interrupt.
the SCSI bus at the time the register is read. The re-
sulting read data is synchronized before being pre-
Bit 6 MDPE (Master Data Parity Error)
sented to the PCI bus to prevent parity errors from
This bit is set when the SYM53C810A as a
being passed to the system. This register can be
master detects a data parity error, or a target
used for diagnostics testing or operation in low level
device signals a parity error during a data
mode.
phase. This bit is completely disabled by the
Master Parity Error Enable bit (bit 3 of
CTEST4).
Bit 5 BF (Bus fault)

This bit is set when a PCI bus fault condition
is detected. A PCI bus fault can only occur
when the SYM53C810A is bus master. A PCI
bus fault occurs when a cycle ends with a Bad
Address or Target Abort Condition.

Operating Registers
Bit 4 ABRT (Aborted)

This bit is set when an abort condition occurs. Register 0D (8D)
An abort condition occurs when a software SCSI Status Zero (SSTAT0)
abort command is issued by setting bit 7 of the Read Only
ISTAT register. ILF ORF OLF AIP LOA WOA RST SDP0/
7 6 5 4 3 2 1 0
Bit 3 SSI (Single step interrupt) Default>>>
If the Single-Step Mode bit in the DCNTL 0 0 0 0 0 0 0 0
register is set, this bit will be set and an inter-

rupt generated after successful execution of Bit 7 ILF (SIDL full)
each SCRIPTS instruction. This bit is set when the SCSI Input Data Latch
register (SIDL) contains data. Data is trans-
Bit 2 SIR (SCRIPTS interrupt ferred from the SCSI bus to the SCSI Input
instruction received) Data Latch register before being sent to the
This status bit is set whenever an Interrupt DMA FIFO and then to the host bus. The
instruction is evaluated as true. SIDL register contains SCSI data received
asynchronously. Synchronous data received
Bit 1 Reserved does not flow through this register.
Bit 0 IID (Illegal instruction detected) Bit 6 ORF (SODR full)

This status bit is set any time an illegal instruc- This bit is set when the SCSI Output Data
tion is detected, whether the SYM53C810A is Register (SODR, a hidden buffer register
operating in single-step mode or automatically which is not accessible) contains data. The
executing SCSI SCRIPTS. This bit will also be SODR register is used by the SCSI logic as a
set if one of the following conditions occurs: second storage register when sending data syn-
chronously. It cannot be read or written by the
1. If the SYM53C810A is executing a Wait user. This bit can be used to determine how
Disconnect instruction and the SCSI REQ many bytes reside in the chip when an error
line is asserted without a disconnect occurs.
occurring.
2. If a Move, Chained Move, or Memory Bit 5 OLF (SODL full)
Move command with a byte count of zero This bit is set when SCSI Output Data Latch
is fetched. (SODL) contains data. The SODL register is
the interface between the DMA logic and the
3. If a Load/Store memory address maps back
SCSI bus. In synchronous mode, data is trans-
into chip register space.
ferred from the host bus to the SODL register,
and then to the SCSI Output Data Register
(SODR, a hidden buffer register which is not
accessible) before being sent to the SCSI bus.
In asynchronous mode, data is transferred
from the host bus to the SODL register, and
then to the SCSI bus. The SODR buffer regis-
ter is not used for asynchronous transfers. This
bit can be used to determine how many bytes
reside in the chip when an error occurs.

Operating Registers
Bit 4 AIP (Arbitration in progress)

Arbitration in Progress (AIP = 1) indicates that Register 0E (8E)
the SYM53C810A has detected a Bus Free SCSI Status One (SSTAT1)
condition, asserted BSY, and asserted its SCSI Read Only
ID onto the SCSI bus. FF3 FF2 FF1 FF0 SDP0L MSG C/D I/O
7 6 5 4 3 2 1 0
Bit 3 LOA (Lost arbitration) Default>>>
When set, LOA indicates that the 0 0 0 0 X X X X
SYM53C810A has detected a bus free condi-

tion, arbitrated for the SCSI bus, and lost arbi- Bits 7-4 FF3-FF0 (FIFO flags)
tration due to another SCSI device asserting
the SEL/ signal. Bytes in the
FF3 FF2 FF1 FF0
SCSI FIFO
Bit 2 WOA (Won arbitration) 0 0 0 0 0
When set, WOA indicates that the
0 0 0 1 1
SYM53C810A has detected a Bus Free condi-
tion, arbitrated for the SCSI bus and won arbi- 0 0 1 0 2
tration. The arbitration mode selected in the 0 0 1 1 3
SCNTL0 register must be full arbitration and 0 1 0 0 4
selection for this bit to be set.
0 1 0 1 5
0 1 1 0 6
Bit 1 RST/ (SCSI RST/ signal)
This bit reports the current status of the SCSI 0 1 1 1 7
RST/ signal, and the SRST bit (bit 6) in the 1 0 0 0 8
ISTAT register. 1 0 0 1 9
Bit 0 SDP/ (SCSI SDP/ parity signal) These four bits define the number of bytes that
This bit represents the active high current sta- currently reside in the SYM53C810A’s SCSI
tus of the SCSI SDP/ parity signal. synchronous data FIFO. These bits are not
latched and they will change as data moves
through the FIFO. Because the FIFO can only
hold nine bytes, values over nine will not occur.
Bit 3 SDPL (Latched SCSI parity)

This bit reflects the SCSI parity signal
(SDP/), corresponding to the data latched in
the SCSI Input Data Latch register (SIDL). It
changes when a new byte is latched into the
SIDL register. This bit is active high, in other
words, it is set when the parity signal is active.

Operating Registers
Bit 2 MSG (SCSI MSG/ signal)

Register 0F (8F)
Bit 1 C/D (SCSI C_D/ signal) SCSI Status Two (SSTAT2)
(Read Only)
Bit 0 I/O (SCSI I_O/ signal) RES RES RES RES RES RES LDSC RES
These SCSI phase status bits are latched on the as- 7 6 5 4 3 2 1 0
serting edge of SREQ/ when operating in either ini- Default>>>
tiator or target mode. These bits are set when the X X X X X X 1 X
corresponding signal is active. They are useful

when operating in low level mode. Bits 7-2 Reserved
Bit 1 LDSC (Last Disconnect)

This bit is used in conjunction with the Con-
nected (CON) bit in SCNTL1. It allows the
user to detect the case in which a target device
disconnects, and then some SCSI device
selects or reselects the SYM53C810A. If the
Connected bit is asserted and the LDSC bit is
asserted, a disconnect has occurred. This bit is
set when the Connected bit in SCNTL1 is
clear. This bit is cleared when a Block Move
instruction executes while the Connected bit in
SCNTL1 is on.
Bit 0 Reserved

Operating Registers
Registers 10-13 (90-93) Register 14 (94)

Data Structure Address (DSA) Interrupt Status (ISTAT)
Read/Write (Read/Write)
This 32-bit register contains the base address used ABRT SRST SIGP SEM CON INTF SIP DIP
7 6 5 4 3 2 1 0
for all table indirect calculations. The DSA register
Default>>>
is usually loaded prior to starting an I/O, but it is 0 0 0 0 0 0 0 0
possible for a SCRIPTS Memory Move to load the
DSA during the I/O. This is the only register that can be accessed by the
host CPU while the SYM53C810A is executing
During any Memory-to-Memory Move operation, SCRIPTS (without interfering in the operation of
the contents of this register are preserved. The the SYM53C810A). It may be used to poll for in-
power-up value of this register is indeterminate. terrupts if hardware interrupts are disabled. There
may be stacked interrupts pending; read this regis-
ter after servicing an interrupt to check for stacked
interrupts. For more information on interrupt han-
dling refer to Chapter 2, “Functional Description.”
Bit 7 ABRT (Abort operation)

Setting this bit aborts the current operation
being executed by the SYM53C810A. If this
bit is set and an interrupt is received, reset this
bit before reading the DSTAT register to pre-
vent further aborted interrupts from being gen-
erated. The sequence to abort any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the ISTAT register.
4. If the SCSI Interrupt Pending bit is set,
then read the SIST0 or SIST1 register to
determine the cause of the SCSI Interrupt
and go back to Step 2.
5. If the SCSI Interrupt Pending bit is clear,
and the DMA Interrupt Pending bit is set,
then write 00h value to this register.
6. Read the DSTAT register to verify the
aborted interrupt and to see if any other
interrupting conditions have occurred.
Bit 6 SRST (Software reset)

Setting this bit resets the SYM53C810A. All
operating registers are cleared to their default
values and all SCSI signals are deasserted. Set-

Operating Registers
ting this bit does not cause the SCSI RST/ sig- Bit 3 CON (Connected)
nal to be asserted. This reset will not clear the This bit is automatically set any time the
53C700 compatibility bit or any of the PCI SYM53C810A is connected to the SCSI bus
configuration registers. This bit is not self- as an initiator or as a target. It will be set after
clearing; it must be cleared to clear the reset successfully completing selection or when the
condition (a hardware reset will also clear this SYM53C810A has responded to a bus-initi-
bit). ated selection or reselection. It will also be set
after the SYM53C810A wins arbitration when
Bit 5 SIGP (Signal process) operating in low level mode. When this bit is
SIGP is a R/W bit that can be written at any clear, the SYM53C810A is not connected to
time, and polled and reset via CTEST2. The the SCSI bus.
SIGP bit can be used in various ways to pass a
flag to or from a running SCRIPTS instruc- Bit 2 INTF (Interrupt on the Fly)
tion. This bit is asserted by an INTFLY instruction
during SCRIPTS execution. SCRIPTS pro-
The only SCRIPTS instruction directly
grams will not halt when the interrupt occurs.
affected by the SIGP bit is Wait For Selection/
This bit can be used to notify a service routine,
Reselection. Setting this bit causes that
running on the main processor while the
instruction to jump to the alternate address
SCRIPTS processor is still executing a
immediately. The instructions at the alternate
SCRIPTS program. If this bit is set, when the
jump address should check the status of SIGP
ISTAT register is read it will not automatically
to determine the cause of the jump. The SIGP
be cleared. To clear this bit, it must be written
bit may be used at any time and is not
to a one. The reset operation is self-clearing.
restricted to the wait for selection/ reselection
condition. Note: if the INTF bit is set but SIP or DIP is not
set, do not attempt to read the other chip
Bit 4 SEM (Semaphore) status registers. An interrupt-on-the-fly
This bit can be set by the SCRIPTS processor interrupt must be cleared before servicing
using a SCRIPTS register write instruction. any other interrupts indicated by SIP or
The bit may also be set by an external proces- DIP.
sor while the SYM53C810A is executing a
Note: this bit must be written to one in order to
SCRIPTS operation. This bit enables the
clear it after it has been set.
SYM53C810A to notify an external processor
of a predefined condition while SCRIPTS are
running. The external processor may also
notify the SYM53C810A of a predefined con-
dition and the SCRIPTS processor may take
action while SCRIPTS are executing.

Operating Registers
Bit 1 SIP (SCSI interrupt pending)

This status bit is set when an interrupt condi- Register 18 (98)
tion is detected in the SCSI portion of the Chip Test Zero (CTEST0)
SYM53C810A. The following conditions will Read/Write
cause a SCSI interrupt.
This was a general purpose read/write register in
■ A phase mismatch occurs (initiator mode) previous SYM53C8XX family chips. Although it is
or SATN/ becomes active (target mode) still a read/write register, Symbios reserves the right
to use these bits for future 53C8XX family en-
■ An arbitration sequence completes
hancements.
■ A selection or reselection time-out occurs
■ The SYM53C810A was selected
■ The SYM53C810A was reselected
■ A SCSI gross error occurs
■ An unexpected disconnect occurs
■ A SCSI reset occurs
■ A parity error is detected
■ The handshake-to-handshake timer is
expired
■ The general purpose timer is expired
To determine exactly which condition(s)
caused the interrupt, read the SIST0 and
SIST1 registers.
Bit 0 DIP (DMA interrupt pending)

This status bit is set when an interrupt condi-
tion is detected in the DMA portion of the
SYM53C810A. The following conditions will
cause a DMA interrupt.
■ A PCI parity error is detected
■ A bus fault is detected
■ An abort condition is detected
■ A SCRIPTS instruction is executed in
single-step mode
■ A SCRIPTS interrupt instruction is
executed
■ An illegal instruction is detected
To determine exactly which condition(s)
caused the interrupt, read the DSTAT register.

Operating Registers
Register 19 (99) Register 1A (9A)

Chip Test One (CTEST1) Chip Test Two (CTEST2)
Read Only Read Only
FMT3 FMT2 FMT1 FMT0 FFL3 FFL2 FFL1 FFL0 DDIR SIGP CIO CM RES TEOP DREQ DACK
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 0 0 0 X X 0 0 0 1
Bits 7-4 FMT3-0 (Byte empty in DMA FIFO) Bit 7 DDIR (Data transfer direction)
These bits identify the bottom bytes in the This status bit indicates which direction data is
DMA FIFO that are empty. Each bit corre- being transferred. When this bit is set, the data
sponds to a byte lane in the DMA FIFO. For will be transferred from the SCSI bus to the
example, if byte lane three is empty, then host bus. When this bit is clear, the data will be
FMT3 will be set. Since the FMT flags indi- transferred from the host bus to the SCSI bus.
cate the status of bytes at the bottom of the
FIFO, if all FMT bits are set, the DMA FIFO Bit 6 SIGP (Signal process)
is empty. This bit is a copy of the SIGP bit in the ISTAT
register (bit 5). The SIGP bit is used to signal a
Bits 3-0 FFL3-0 (Byte full in DMA FIFO) running SCRIPTS instruction. When this reg-
These status bits identify the top bytes in the ister is read, the SIGP bit in the ISTAT register
DMA FIFO that are full. Each bit corresponds is cleared.
to a byte lane in the DMA FIFO. For example,
if byte lane three is full then FFL3 will be set. Bit 5 CIO (Configured as I/O)
Since the FFL flags indicate the status of bytes This bit is defined as the Configuration I/O
at the top of the FIFO, if all FFL bits are set, Enable Status bit. This read-only bit indicates
the DMA FIFO is full. if the chip is currently enabled as I/O space.
Note: both bits 4 and 5 may be set if the chip is
dual-mapped.
Bit 4 CM (Configured as memory)

This bit is defined as the configuration mem-
ory enable status bit. This read-only bit indi-
cates if the chip is currently enabled as
memory space.
Note: both bits 4 and 5 may be set if the chip is
dual-mapped.
Bit 3 Reserved

Operating Registers
Bit 2 TEOP (SCSI true end of process)

This bit indicates the status of the Register 1B (9B)
SYM53C810A’s internal TEOP signal. The Chip Test Three (CTEST3)
TEOP signal acknowledges the completion of Read/Write
a transfer through the SCSI portion of the V3 V2 V1 V0 FLF CLF FM WRIE
SYM53C810A. When this bit is set, TEOP is 7 6 5 4 3 2 1 0
active. When this bit is clear, TEOP is inactive. Default>>>
X X X X 0 0 0 0
Bit 1 DREQ (Data request status)

This bit indicates the status of the Bits 7-4 V3-V0 (Chip revision level)
SYM53C810A’s internal Data Request signal These bits identify the chip revision level for
(DREQ). When this bit is set, DREQ is active. software purposes.
When this bit is clear, DREQ is inactive.
Bit 3 FLF (Flush DMA FIFO)
Bit 0 DACK (Data acknowledge status) When this bit is set, data residing in the DMA
This bit indicates the status of the FIFO is transferred to memory, starting at the
SYM53C810A’s internal Data Acknowledge address in the DNAD register. The internal
signal (DACK/). When this bit is set, DACK/ is DMAWR signal, controlled by the CTEST5
inactive. When this bit is clear, DACK/ is register, determines the direction of the trans-
active. fer. This bit is not self clearing; once the
SYM53C810A has successfully transferred
the data, this bit should be reset.
Note: polling of FIFO flags is allowed during
flush operations.
Bit 2 CLF (Clear DMA FIFO)

When this bit is set, all data pointers for the
DMA FIFO are cleared. Any data in the FIFO
is lost. This bit automatically resets after the
SYM53C810A has successfully cleared the
appropriate FIFO pointers and registers.
Note: this bit does not clear the data visible at the
bottom of the FIFO.
Bit 1 FM (Fetch pin mode)

When set, this bit causes the FETCH/ pin to
deassert during indirect and table indirect read
operations. FETCH/ will only be active during
the op code portion of an instruction fetch.
This allows SCRIPTS to be stored in a PROM
while data tables are stored in RAM.
If this bit is not set, FETCH/ will be asserted
for all bus cycles during instruction fetches.

Operating Registers
Bit 0 WRIE (Write and Invalidate Enable)

This bit, when set, causes Memory Write and Registers 1C-1F (9C-9F)
Invalidate commands to be issued on the PCI Temporary (TEMP)
bus after certain conditions have been met. Read/Write
These conditions are described in more detail
This 32-bit register stores the Return instruction
in Chapter 3.
address pointer from the Call instruction. The ad-
dress pointer stored in this register is loaded into
the DSP register when a Return instruction is exe-
cuted. This address points to the next instruction to
be executed. Do not write to this register while the
SYM53C810A is executing SCRIPTS.
During any Memory-to-Memory Move operation,
the contents of this register are preserved. The
power-up value of this register is indeterminate.

Operating Registers
Register 20 (A0) Register 21 (A1)

DMA FIFO (DFIFO) Chip Test Four (CTEST4)
RES BO6 BO5 BO4 Bo3 BO2 BO1 BO0 BDIS ZMOD ZSD SRTM MPEE FBL2 FBL1 FBL0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 7 Reserved Bit 7 BDIS (Burst Disable)

When set, this bit will cause the
Bits 6-0 BO6-BO0 (Byte offset counter) SYM53C810A to perform back to back cycles
These bits indicate the amount of data trans- for all transfers. When reset, the
ferred between the SCSI core and the DMA SYM53C810A performs back to back transfers
core. It may be used to determine the number for op code fetches and burst transfers for data
of bytes in the DMA FIFO when an interrupt moves.The handling of op code fetches is
occurs. These bits are unstable while data is dependent on the setting of the Burst Op Code
being transferred between the two cores; once Fetch bit in the DMODE register.
the chip has stopped transferring data, these
bits are stable. Bit 6 ZMOD (High impedance mode)
Setting this bit causes the SYM53C810A to
Since the DFIFO register counts the number
place all output and bidirectional pins into a
of bytes transferred between the DMA core
high-impedance state. In order to read data out
and the SCSI core, and the DBC register
of the SYM53C810A, this bit must be cleared.
counts the number of bytes transferred across
This bit is intended for board-level testing only.
the host bus, the difference between these two
Do not set this bit during normal system oper-
counters represents the number of bytes
ation.
remaining in the DMA FIFO.
The following steps will determine how many Bit 5 ZSD (SCSI Data High Impedance)
bytes are left in the DMA FIFO when an error Setting this bit causes the SYM53C810A to
occurs, regardless of the direction of the trans- place the SCSI data bus SD(7-0) and the par-
fer: ity line (SDP) in a high-impedance state. In
order to transfer data on the SCSI bus, this bit
1. Subtract the seven least significant bits of
must be cleared.
the DBC register from the 7-bit value of
the DFIFO register.
Bit 4 SRTM (Shadow Register Test Mode)
2. AND the result with 7Fh for a byte count Setting this bit allows access to the shadow reg-
between zero and 64. isters used by Memory-to-Memory Move
Note: to calculate the total number of bytes in operations. When this bit is set, register
both the DMA FIFO and SCSI logic, see accesses to the TEMP and DSA registers are
the section on Data Paths in Chapter Two, directed to the shadow copies STEMP
“Functional Description.” (Shadow TEMP) and SDSA (Shadow DSA).
The registers are shadowed to prevent them
from being overwritten during a Memory-to-
Memory Move operation. The DSA and
TEMP registers contain the base address used

Operating Registers
for table indirect calculations, and the address

pointer for a call or return instruction, respec- Register 22 (A2)
tively. This bit is intended for manufacturing Chip Test Five (CTEST5)
diagnostics only and should not be set during Read/Write
normal operations. ADCK BBCK RES MASR DDIR RES RES RES
7 6 5 4 3 2 1 0
Bit 3 MPEE (Master Parity Error Enable) Default>>>
Setting this bit enables parity checking during 0 0 X 0 0 X X X
master data phases. A parity error during a bus

master read is detected by the SYM53C810A. Bit 7 ADCK (Clock address incrementor)
A parity error during a bus master write is Setting this bit increments the address pointer
detected by the target, and the SYM53C810A contained in the DNAD register. The DNAD
is informed of the error by the PERR/ pin register is incremented based on the DNAD
being asserted by the target. When this bit is contents and the current DBC value. This bit
reset, the SYM53C810A will not interrupt if a automatically clears itself after incrementing
master parity error occurs. This bit is reset at the DNAD register.
power up.
Bit 6 BBCK (Clock byte counter)
Bits 2-0 FBL2-FBL0 (FIFO byte control) Setting this bit decrements the byte count con-
tained in the 24-bit DBC register. It is decre-
mented based on the DBC contents and the
DMA FIFO current DNAD value. This bit automatically
FBL2 FBL1 FBL0 Pins clears itself after decrementing the DBC regis-
Byte lane
ter.
0 X X Disabled n/a
1 0 0 0 D(7-0) Bit 5 Reserved
1 0 1 1 D(15-8)
1 1 0 2 D(23-16) Bit 4 MASR (Master control for set or
1 1 1 3 D(31-24) reset pulses)
This bit controls the operation of bit 3. When
this bit is set, bit 3 asserts the corresponding
These bits steer the contents of the CTEST6
signals. When this bit is reset, bit 3 deasserts
register to the appropriate byte lane of the 32-
the corresponding signals. This bit and bit 3
bit DMA FIFO. If the FBL2 bit is set, then
should not be changed in the same write cycle.
FBL1 and FBL0 determine which of four byte
lanes can be read or written. When cleared, the
byte lane read or written is determined by the Bit 3 DDIR (DMA direction)
current contents of the DNAD and DBC regis- Setting this bit either asserts or deasserts the
ters. Each of the four bytes that make up the internal DMA Write (DMAWR) direction sig-
32-bit DMA FIFO can be accessed by writing nal depending on the current status of the
these bits to the proper value. For normal MASR bit in this register. Asserting the
operation, FBL2 must equal zero. DMAWR signal indicates that data will be
transferred from the SCSI bus to the host bus.
Deasserting the DMAWR signal transfers data
from the host bus to the SCSI bus.
Bits 2-0 Reserved

Operating Registers
Register 23 (A3) Registers 24-26 (A4-A6)

Chip Test Six (CTEST6) DMA Byte Counter (DBC)
DF7 DF6 DF5 DF4 DF3 DF2 DF1 DF0 This 24-bit register determines the number of bytes
7 6 5 4 3 2 1 0
to be transferred in a Block Move instruction.
Default>>>
0 0 0 0 0 0 0 0
While sending data to the SCSI bus, the counter is
decremented as data is moved into the DMA FIFO
from memory. While receiving data from the SCSI
Bits 7-0 DF7-DF0 (DMA FIFO)
bus, the counter is decremented as data is written
Writing to this register writes data to the
to memory from the SYM53C810A. The DBC
appropriate byte lane of the DMA FIFO as
counter is decremented each time that data is trans-
determined by the FBL bits in the CTEST4
ferred on the PCI bus. It is decremented by an
register. Reading this register unloads data
amount equal to the number of bytes that were
from the appropriate byte lane of the DMA
transferred.
FIFO as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is The maximum number of bytes that can be trans-
loaded into the top of the FIFO. Data read out ferred in any one Block Move command is
of the FIFO is taken from the bottom. To pre- 16,777,215 bytes. The maximum value that can be
vent DMA data from being corrupted, this reg- loaded into the DBC register is FFFFFFh. If the
ister should not be accessed before starting or instruction is a Block Move and a value of 000000h
restarting SCRIPTS operation. This register is loaded into the DBC register, an illegal instruc-
should only be written when testing the DMA tion interrupt will occur if the SYM53C810A is not
FIFO using the CTEST4 register. Writes to in target role, Command phase.
this register while the test mode is not enabled
The DBC register is also used to hold the least sig-
will have unexpected results.
nificant 24 bits of the first dword of a SCRIPTS
fetch, and to hold the offset value during table indi-
rect I/O SCRIPTS. For a complete description, see
Chapter Six, “Instruction Set of the I/O Proces-
sor.” The power-up value of this register is indeter-
minate.

Operating Registers
Register 27 (A7) Registers 28-2B (A8-AB)

DMA Command (DCMD) DMA Next Address (DNAD)
This 8-bit register determines the instruction for This 32-bit register contains the general purpose
the SYM53C810A to execute. This register has a address pointer. At the start of some SCRIPTS op-
different format for each instruction. For a com- erations, its value is copied from the DSPS register.
plete description, see Chapter Six, “Instruction Set Its value may not be valid except in certain abort
of the I/O Processor.” conditions. The default value of this register is zero.

Operating Registers
Registers 2C-2F (AC-AF) Registers 30-33 (B0-B3)

DMA SCRIPTS Pointer (DSP) DMA SCRIPTS Pointer Save (DSPS)
The CPU writes the address of the first SCRIPTS This register contains the second dword of a
instruction to this register to begin SCSI SCRIPTS SCRIPTS instruction. It is overwritten each time a
operation. In normal SCRIPTS operation, once the SCRIPTS instruction is fetched. When a
starting address of the first SCRIPTS instruction is SCRIPTS interrupt instruction is executed, this
written to this register, SCRIPTS instructions are register holds the interrupt vector. The power-up
automatically fetched and executed until an inter- value of this register is indeterminate.
rupt condition occurs.
In single-step mode, there is a single step interrupt
after each instruction is executed. The DSP register
does not need to be written with the next address,
but the Start DMA bit (bit 2, DCNTL register)
must be set each time the step interrupt occurs to
fetch and execute the next SCRIPTS command.
When writing this register eight bits at a time, writ-
ing the upper eight bits begins execution of the
SCSI SCRIPTS. The default value of this register
is zero.

Operating Registers
Registers 34-37 (B4-B7) Register 38 (B8)

Scratch Register A (SCRATCH A) DMA Mode (DMODE)
This is a general purpose, user-definable scratch BL1 BL0 SIOM DIOM ERL ERMP BOF MAN
7 6 5 4 3 2 1 0
pad register. Apart from CPU access, only Register
Default>>>
Read/Write and Memory Moves into the 0 0 0 0 0 0 0 0
SCRATCH register will alter its contents. The
power-up value of this register is indeterminate.
Bit 7-6 BL1-BL0 (Burst length)
The SYM53C810A cannot fetch SCRIPTS in-
structions from this location. BL1 BL0 Burst Length
0 0 2- transfer burst
0 1 4- transfer burst
1 0 8-transfer burst
1 1 16-transfer burst
These bits control the maximum number of

transfers performed per bus ownership, regard-
less of whether the transfers are back-to-back,
burst, or a combination of both. The
SYM53C810A asserts the Bus Request (REQ/
) output when the DMA FIFO can accommo-
date a transfer of at least one burst size of data.
Bus Request (REQ/) is also asserted during
start-of-transfer and end-of-transfer cleanup
and alignment, even though less than a full
burst of transfers may be performed. The
SYM53C810A inserts a “fairness delay” of
four CLKs between burst-length transfers (as
set in BL1-0) during normal operation. The
fairness delay is not inserted during PCI retry
cycles. This gives the CPU and other bus mas-
ter devices the opportunity to access the PCI
bus between bursts.
Bit 5 SIOM (Source I/O-Memory Enable)

This bit is defined as an I/O Memory Enable
bit for the source address of a Memory Move
or Block Move Command. If this bit is set,
then the source address is in I/O space; and if
reset, then the source address is in memory
space.

Operating Registers
This function is useful for register-to-memory accessed in a subsequent bus ownership. If the
operations using the Memory Move instruc- instruction is a table indirect block move type,
tion when the SYM53C810A is I/O mapped. the chip will access the remaining two dwords
Bits 4 and 5 of the CTEST2 register can be in a subsequent bus ownership, thereby fetch-
used to determine the configuration status of ing the four dwords required in two bursts of
the SYM53C810A. two dwords each.
Bit 4 DIOM (Destination I/O-Memory Bit 0 MAN (Manual Start Mode)

Enable) Setting this bit prevents the SYM53C810A
This bit is defined as an I/O Memory Enable from automatically fetching and executing
bit for the destination address of a Memory SCSI SCRIPTS when the DSP register is writ-
Move or Block Move Command. If this bit is ten. When this bit is set, the Start DMA bit in
set, then the destination address is in I/O the DCNTL register must be set to begin
space; and if reset, then the destination address SCRIPTS execution. Clearing this bit causes
is in memory space. the SYM53C810A to automatically begin
fetching and executing SCSI SCRIPTS when
This function is useful for memory–to–register
the DSP register is written. This bit is not nor-
operations using the Memory Move instruc-
mally used for SCSI SCRIPTS operations.
tion when the SYM53C810A is I/O mapped.
Bits 4 and 5 of the CTEST2 register can be
used to determine the configuration status of
the SYM53C810A.
Bit 3 ERL (Enable Read Line)

This bit enables a PCI Read Line command. If
PCI cache mode is enabled by setting bits in
the PCI Cache Line Size register, the chip
issues a Read Line command on all read cycles
if other conditions are met. For more informa-
tion on these conditions, refer to Chapter 3.
ERMP (Enable Read Multiple)

This bit, when set, will cause Read Multiple
commands to be issued on the PCI bus after
certain conditions have been met. These condi-
tions are described in Chapter 3.
Bit 1 BOF (Burst Op Code Fetch Enable)

Setting this bit causes the SYM53C810A to
fetch instructions in burst mode, if the Burst
Disable bit (CTEST4, bit7) is cleared. Specifi-
cally, the chip will burst in the first two dwords
of all instructions using a single bus ownership.
If the instruction is a memory-to-memory
move type, the third dword will be accessed in
a subsequent bus ownership. If the instruction
is an indirect type, the additional dword will be

Operating Registers
Register 39 (B9) Register 3A (BA)

DMA Interrupt Enable (DIEN) Scratch Byte Register (SBR)
RES MDPE BF ABRT SSI SIR RES IID This is a general purpose register. Apart from CPU
7 6 5 4 3 2 1 0
access, only Register Read/Write and Memory
Default>>>
X 0 0 0 0 0 X 0
Moves into this register will alter its contents. The
default value of this register is zero. This register
This register contains the interrupt mask bits corre- was called the DMA Watchdog Timer on previous
sponding to the interrupting conditions described SYM53C8XX family products.
in the DSTAT register. An interrupt is masked by
clearing the appropriate mask bit. Masking an in-
terrupt prevents IRQ/ from being asserted for the
corresponding interrupt, but the status bit will still
be set in the DSTAT register. Masking an interrupt
will not prevent the ISTAT DIP from being set. All
DMA interrupts are considered fatal, therefore
SCRIPTS will stop running when a DMA interrupt
occurs, whether or not the interrupt is masked. Set-
ting a mask bit enables the assertion of IRQ/ for the
corresponding interrupt. (A masked non-fatal in-
terrupt will not prevent un-masked or fatal inter-
rupts from getting through; interrupt stacking
begins when either the ISTAT SIP or DIP bit is
set.)
The SYM53C810A IRQ/ output is latched; once
asserted, it will remain asserted until the interrupt
is cleared by reading the appropriate status register.
Masking an interrupt after the IRQ/ output is as-
serted will not cause IRQ/ to be deasserted.
For more information on interrupts, see Chapter
Two, “Functional Description.”
Bit 7 Reserved
Bit 4 ABRT (Aborted)
Bit 3 SSI (Single step interrupt)
Bit 2 SIR (SCRIPTS interrupt
instruction received
Bit 1 Reserved
Bit 0 IID (Illegal instruction detected)

Operating Registers
Bit 3 IRQM (IRQ Mode)

Register 3B (BB) When set, this bit enables a totem pole driver
DMA Control (DCNTL) for the IRQ pin. When reset, this bit enables an
Read/Write open drain driver for the IRQ pin with a inter-
CLSE PFF PFEN SSM IRQM STD IRQD COM
nal weak pull-up. This bit is reset at power up.
7 6 5 4 3 2 1 0
Default>>> Bit 2 STD (Start DMA operation)
0 0 0 0 0 0 0 0 The SYM53C810A fetches a SCSI SCRIPTS
instruction from the address contained in the
Bit 7 CLSE (Cache Line Size Enable) DSP register when this bit is set. This bit is
Setting this bit enables the SYM53C810A to required if the SYM53C810A is in one of the
sense and react to cache line boundaries set up following modes:
by the DMODE or PCI Cache Line Size regis-
1. Manual start mode – Bit 0 in the DMODE
ter, whichever contains the smaller value.
register is set
Clearing this bit disables the cache line size
logic and the SYM53C810A monitors the 2. Single-step mode – Bit 4 in the DCNTL
cache line size via the DMODE register. register is set
When the SYM53C810A is executing
Bit 6 PFF (Pre-Fetch Flush)
SCRIPTS in manual start mode, the Start
Setting this bit will cause the pre-fetch unit to
DMA bit needs to be set to start instruction
flush its contents. The bit will reset after the
fetches. This bit will remain set until an inter-
flush is complete.
rupt occurs. When the SYM53C810A is in sin-
gle-step mode, the Start DMA bit needs to be
Bit 5 PFEN (Pre-fetch Enable) set to restart execution of SCRIPTS after a sin-
Setting this bit enables the pre-fetch unit if the gle-step interrupt.
burst size is equal to or greater than four. For
more information on SCRIPTS instruction
Bit 1 IRQD (IRQ Disable)
prefetching, see Chapter 2.
Setting this bit tristates the IRQ pin; clearing
the bit enables normal operation. When bit 1 in
Bit 4 SSM (Single-step mode) this register is set, the IRQ/ pin will not be
Setting this bit causes the SYM53C810A to asserted when an interrupt condition occurs.
stop after executing each SCRIPTS instruc- The interrupt is not lost or ignored, but merely
tion, and generate a single step interrupt. masked at the pin. Clearing this bit when an
When this bit is clear the SYM53C810A will interrupt is pending will immediately cause the
not stop after each instruction; instead it con- IRQ/ pin to assert. As with any register other
tinues fetching and executing instructions until than ISTAT, this register cannot be accessed
an interrupt condition occurs. This bit should except by a SCRIPTS instruction during
be clear for normal SCSI SCRIPTS operation. SCRIPTS execution.
To restart the SYM53C810A after it generates
a SCRIPTS Step interrupt, read the ISTAT
and DSTAT registers to recognize and clear
the interrupt; then set the START DMA bit in
this register.

Operating Registers
Bit 0 COM (53C700 compatibility)

When this bit is clear, the SYM53C810A will Register 3C-3F (BC-BF)
behave in a manner compatible with the Adder Sum Output (ADDER)
SYM53C700; selection/reselection IDs will be Read Only
stored in both the SSID and SFBR registers.
This register contains the output of the internal
When this bit is set, the ID will be stored only adder, and is used primarily for test purposes. The
in the SSID register, protecting the SFBR from power-up value for this register is indeterminate.
being overwritten if a selection/reselection
occurs during a DMA register-to-register oper-
ation.
This bit is not affected by a software reset.

Operating Registers
Bit 4 RSL (Reselected)

Register 40 (C0) This bit controls whether an interrupt occurs
SCSI Interrupt Enable Zero (SIEN0) when the SYM53C810A has been reselected
Read/Write by a SCSI initiator device. The Enable
M/A CMP SEL RSL SGE UDC RST PAR
Response to Reselection bit in the SCID regis-
7 6 5 4 3 2 1 0 ter must be set for this to occur.
Default>>>
0 0 0 0 0 0 0 0 Bit 3 SGE (SCSI Gross Error)
This register contains the interrupt mask bits that This bit controls whether an interrupt occurs
correspond to the interrupting conditions described when the SYM53C810A detects a SCSI Gross
in the SIST0 register. An interrupt is masked by Error. The following conditions are considered
clearing the appropriate mask bit. For more infor- SCSI Gross Errors:
mation on interrupts, see Chapter 2. 1. Data underflow - the SCSI FIFO was read
when no data was present.
Bit 7 M/A (SCSI Phase Mismatch -
2. Data overflow - the SCSI FIFO was
Initiator Mode; SCSI ATN
written to while full.
Condition - Target Mode)
In initiator mode, this bit controls whether an 3. Offset underflow - in target mode, a
interrupt occurs when the SCSI phase asserted SACK/ pulse was received before the
by the target and sampled during SREQ/ does corresponding SREQ/ was sent.
not match the expected phase in the SOCL
4. Offset overflow - in initiator mode, an
register. This expected phase is automatically
SREQ/ pulse was received which caused
written by the SCSI SCRIPTS program. In
the maximum offset (Defined by the
target mode, this bit is set when the initiator
MO3-0 bits in the SXFER register) to be
has asserted SATN/. See the Disable Halt on
exceeded.
Parity Error or SATN/ Condition bit in the
SCNTL1 register for more information on 5. In initiator mode, a phase change occurred
when this status is actually raised. with an outstanding SREQ/SACK offset.
6. Residual data in SCSI FIFO - a transfer
Bit 6 CMP (Function Complete)
other than synchronous data receive was
This bit controls whether an interrupt occurs
started with data left in the SCSI
when full arbitration and selection sequence
synchronous receive FIFO.
has completed.
Bit 2 UDC (Unexpected Disconnect)
Bit 5 SEL (Selected)
in the case of an unexpected disconnect. This
when the SYM53C810A has been selected by
condition only occurs in initiator mode. It hap-
a SCSI target device. The Enable Response to
pens when the target to which the
Selection bit in the SCID register must be set
SYM53C810A is connected disconnects from
for this to occur.
the SCSI bus unexpectedly. See the SCSI Dis-
connect Unexpected bit in the SCNTL2 regis-
ter for more information on expected versus
unexpected disconnects. Any disconnect in low
level mode causes this condition.

Operating Registers
Bit 1 RST (SCSI Reset Condition)

This bit controls whether an interrupt occurs Register 41 (C1)
when the SRST/ signal has been asserted by SCSI Interrupt Enable One (SIEN1)
the SYM53C810A or any other SCSI device. Read/Write
Note that this condition is edge-triggered, so RES RES RES RES RES STO GEN HTH
that multiple interrupts cannot occur because 7 6 5 4 3 2 1 0
of a single SRST/ pulse. Default>>>
X X X X X 0 0 0
Bit 0 PAR (SCSI Parity Error) This register contains the interrupt mask bits corre-
This bit controls whether an interrupt occurs sponding to the interrupting conditions described
when the SYM53C810A detects a parity error in the SIST1 register. An interrupt is masked by
while receiving or sending SCSI data. See the clearing the appropriate mask bit. For more infor-
Disable Halt on Parity Error or SATN/ Condi- mation on interrupts, refer to Chapter 2, “Func-
tion bits in the SCNTL1 register for more tional Description.”
information on when this condition will actu-
ally be raised.
Bits 7-3 Reserved
Bit 2 STO (Selection or Reselection Time-

out)
when the SCSI device which the
SYM53C810A was attempting to select or
reselect did not respond within the pro-
grammed time-out period. See the description
of the STIME0 register bits 3-0 for more infor-
mation on the time-out timer.
Bit 1 GEN (General Purpose Timer

Expired)
when the general purpose timer has expired.
The time measured is the time between
enabling and disabling of the timer. See the
description of the STIME1 register, bits 3-0,
for more information on the general purpose
timer.

Operating Registers
Bit 0 HTH (Handshake to Handshake

timer Expired) Register 42 (C2)
This bit controls whether an interrupt occurs SCSI Interrupt Status Zero (SIST0)
when the handshake-to-handshake timer has Read Only
expired. The time measured is the SCSI M/A CMP SEL RSL SGE UDC RST PAR
Request to Request (target) or Acknowledge to 7 6 5 4 3 2 1 0
Acknowledge (initiator) period. See the Default>>>
description of the STIME0 register, bits 7-4, 0 0 0 0 0 0 0 0
for more information on the handshake-to-

Reading the SIST0 register returns the status of the
handshake timer.
various interrupt conditions, whether or not they
are enabled in the SIEN0 register. Each bit set in-
dicates that the corresponding condition has oc-
curred. Reading the SIST0 will clear the interrupt
status.
Reading this register will clear any bits that are set
at the time the register is read, but will not neces-
sarily clear the register because additional inter-
rupts may be pending (the SYM53C810A stacks
interrupts). SCSI interrupt conditions may be indi-
vidually masked through the SIEN0 register.
When performing consecutive 8-bit reads of the
DSTAT, SIST0, and SIST1 registers (in any or-
der), insert a delay equivalent to 12 CLK periods
between the reads to ensure the interrupts clear
properly. Also, if reading the registers when both
the ISTAT SIP and DIP bits may not be set, the
SIST0 and SIST1 registers should be read before
the DSTAT register to avoid missing a SCSI inter-
rupt. For more information on interrupts, refer to
Chapter 2, “Functional Description.”
Bit 7 M/A (Initiator Mode: Phase Mis-

match; Target Mode: SATN/ Active)
In initiator mode, this bit is set if the SCSI
phase asserted by the target does not match the
instruction. The phase is sampled when SREQ/
is asserted by the target. In target mode, this
bit is set when the SATN/ signal is asserted by
the initiator.
Bit 6 CMP (Function Complete)

This bit is set when an arbitration only or full
arbitration sequence has completed.

Operating Registers
Bit 5 SEL (Selected) 6. Residual data in the Synchronous data

This bit is set when the SYM53C810A is FIFO - a transfer other than synchronous
selected by another SCSI device. The Enable data receive was started with data left in the
Response to Selection bit must have been set in synchronous data FIFO.
the SCID register (and the RESPID register
must hold the chip’s ID) for the Bit 2 UDC (Unexpected Disconnect)
SYM53C810A to respond to selection This bit is set when the SYM53C810A is oper-
attempts. ating in initiator mode and the target device
unexpectedly disconnects from the SCSI bus.
Bit 4 RSL (Reselected) This bit is only valid when the SYM53C810A
This bit is set when the SYM53C810A is rese- operates in the initiator mode. When the
lected by another SCSI device. The Enable SYM53C810A operates in low level mode, any
Response to Reselection bit must have been set disconnect will cause an interrupt, even a valid
in the SCID register (and the RESPID register SCSI disconnect. This bit will also be set if a
must hold the chip’s ID) for the selection time-out occurs (it may occur before,
SYM53C810A to respond to reselection at the same time, or stacked after the STO
attempts. interrupt, since this is not considered an
expected disconnect).
Bit 3 SGE (SCSI Gross Error)
This bit is set when the SYM53C810A Bit 1 RST (SCSI RST/ Received)
encounters a SCSI Gross Error Condition. This bit is set when the SYM53C810A detects
The following conditions can result in a SCSI an active SRST/ signal, whether the reset was
Gross Error Condition: generated external to the chip or caused by the
Assert SRST/ bit in the SCNTL1 register. This
1. Data Underflow - the SCSI FIFO register
SYM53C810A SCSI reset detection logic is
was read when no data was present.
edge-sensitive, so that multiple interrupts will
2. Data Overflow - too many bytes were not be generated for a single assertion of the
written to the SCSI FIFO or the SRST/ signal.
synchronous offset caused the SCSI FIFO
to be overwritten. Bit 0 PAR (Parity Error)
3. Offset Underflow - the SYM53C810A is This bit is set when the SYM53C810A detects
operating in target mode and a SACK/ a parity error while receiving SCSI data. The
pulse is received when the outstanding Enable Parity Checking bit (bit 3 in the
offset is zero. SCNTL0 register) must be set for this bit to
become active. The SYM53C810A always gen-
4. Offset Overflow - the other SCSI device erates parity when sending SCSI data.
sent a SREQ/ or SACK/ pulse with data
which exceeded the maximum
synchronous offset defined by the SXFER
register.
5. A phase change occurred with an
outstanding synchronous offset when the
SYM53C810A was operating as an
initiator.

Operating Registers
Register 43 (C3) Register 44 (C4)

SCSI Interrupt Status One (SIST1) SCSI Longitudinal Parity (SLPAR)
Read Only Read/Write
RES RES RES RES RES STO GEN HTH This register performs a bytewise longitudinal par-
7 6 5 4 3 2 1 0
ity check on all SCSI data received or sent through
Default>>>
X X X X X 0 0 0
the SCSI core. If one of the bytes received or sent
(usually the last) is the set of correct even parity
Reading the SIST1 register returns the status of the bits, SLPAR should go to zero (assuming it started
various interrupt conditions, whether or not they at zero). As an example, suppose that the following
are enabled in the SIEN1 register. Each bit that is three data bytes and one check byte are received
set indicates the corresponding condition has oc- from the SCSI bus (all signals are shown active
curred. high):
Reading the SIST1 register will clear the interrupt
condition.
Data Bytes Running SLPAR
Bits 7-3 Reserved --- 00000000
1. 11001100 11001100 (XOR of word 1)
Bit 2 STO (Selection or Reselection
2. 01010101 10011001 (XOR of word 1 and 2)
Time-out)
This bit is set when the SCSI device which the 3. 00001111 10010110 (XOR of word 1, 2 and 3)
SYM53C810A53C810A was attempting to Even Parity >>>10010110
select or reselect did not respond within the 4. 10010110 00000000
programmed time-out period. See the descrip-
tion of the STIME0 register, bits 3-0, for more A one in any bit position of the final SLPAR value
information on the time-out timer. would indicate a transmission error.
The SLPAR register can also be used to generate
Bit 1 GEN (General Purpose Timer
the check bytes for SCSI send operations. If the
Expired)
SLPAR register contains all zeros prior to sending
This bit is set when the general purpose timer
a block move, it will contain the appropriate check
has expired. The time measured is the time
byte at the end of the block move. This byte must
between enabling and disabling of the timer.
then be sent across the SCSI bus.
See the description of the STIME1 register,
bits 3-0, for more information on the general Note: writing any value to this register resets it to
purpose timer. zero.
The longitudinal parity checks are meant to provide
Bit 0 HTH (Handshake-to-Handshake an added measure of SCSI data integrity and are
Timer Expired) entirely optional. This register does not latch SCSI
This bit is set when the handshake-to-hand- selection/reselection IDs under any circumstances.
shake timer has expired. The time measured is The default value of this register is zero.
the SCSI Request to Request (target) or
Acknowledge to Acknowledge (initiator)
period. See the description of the STIME0
register, bits 7-4, for more information on the
handshake-to-handshake timer.

Operating Registers
Register 46 (C6) Register 47 (C7)

Memory Access Control (MACNTL) General Purpose Pin Control (GPCNTL)
TYP3 TYP2 TYP1 TYP0 DWR DRD PSCPT SCPTS ME FE RES RES RES RES GPIO1 GPIO0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0 X 0 1 1 1 1
This register is used to determine if the pins con-

Bits 7-4 TYP3-0 (Chip Type) trolled by the General Purpose register (GPREG)
These bits identify the chip type for software are inputs or outputs. Bits 1-0 in GPCNTL corre-
purposes. spond to bits 1-0 in the GPREG register. When the
Bits 3 through 0 of this register are used to deter- bits are enabled as inputs, an internal pull-up is also
mine if an external bus master access is to local or enabled.
far memory. When bits 3 through 0 are set, the cor-
responding access is considered local and the Bit 7 Master Enable
MAC/_TESTOUT pin is driven high. When these The internal bus master signal will be pre-
bits are clear, the corresponding access is to far sented on GPIO1 if this bit is set, regardless of
memory and the MAC/_TESTOUT pin is driven the state of Bit 1 (GPIO1_EN).
low. This function is enabled after a Transfer Con-
trol SCRIPTS instruction is executed. Bit 6 Fetch Enable
The internal op code fetch signal will be pre-
Bit 3 DWR (DataWR) sented on GPIO0 if this bit is set, regardless of
This bit is used to define if a data write is con- the state of Bit 0 (GPIO0_EN).
sidered local memory access.
Bit 5 Reserved
Bit 2 DRD (DataRD)
This bit is used to define if a data read is con- Bits 1-0 GPIO1_EN– GPIO0_EN (GPIO
sidered local memory access. Enable)
These bits power up set, causing the GPIO1
Bit 1 PSCPT (Pointer SCRIPTS) and GPIO0 pins to become inputs. Resetting
This bit is used to define if a pointer to a these bits causes GPIO1-0 to become outputs.
SCRIPTS indirect or table indirect fetch is
considered local memory access.
Bit 0 SCPTS (SCRIPTS)

This bit is used to define if a SCRIPTS fetch is
considered local memory access.

Operating Registers
Register 48 (C8)
SCSI Timer Zero (STIME0)
HTH 7-4, SEL 3-0, Minimum Time-out
Read /Write GEN 3-0
HTH HTH HTH HRH SEL SEL SEL SEL 40 MHz 50 MHz
7 6 5 4 3 2 1 0
Default>>>
0000 Disabled Disabled
0 0 0 0 0 0 0 0 0001 125 µs 100 µs
0010 250 µs 200 µs
Bits 7-4 HTH (Handshake-to-Handshake
0011 500 µs 400 µs
Timer Period)
These bits select the handshake-to-handshake 0100 1 ms 800 µs
time-out period, the maximum time between 0101 2 ms 1.6 ms
SCSI handshakes (SREQ/ to SREQ/ in target 0110 4 ms 3.2 ms
mode, or SACK/ to SACK/ in initiator mode). 0111 8 ms 6.4 ms
When this timing is exceeded, an interrupt is
1000 16 ms 12.8 ms
generated and the HTH bit in the SIST1 regis-
ter is set. The following table contains time-out 1001 32 ms 25.6 ms
periods for the Handshake-to-Handshake 1010 64 ms 51.2 ms
Timer, the Selection/Reselection Timer (bits 3- 1011 128 ms 102.4 ms
0), and the General Purpose Timer (STIME1
1100 256 ms 204.8 ms
bits 3-0). For a more detailed explanation of
interrupts, refer to Chapter 2, “Functional 1101 512 ms 409.6 ms
Description.” 1110 1.024 sec 819.2 ms
1111 2.048 sec 1.6384 sec
These values will be correct if the CCF bits in the SCNTL3
register are set according to the valid combinations in the bit
description.
Bits 3-0 SEL (Selection Time-Out)

These bits select the SCSI selection/reselection
time-out period. When this timing (plus the
200 µs selection abort time) is exceeded, the
STO bit in the SIST1 register is set. For a
more detailed explanation of interrupts, refer
to Chapter 2, “Functional Description.”

Operating Registers
Register 49 (C9) Register 4A (CA)

SCSI Timer One (STIME1) Response ID (RESPID)
RES RES RES RES GEN3 GEN2 GEN1 GEN0 This register contains the IDs that the chip re-
7 6 5 4 3 2 1 0
sponds to on the SCSI bus. Each bit represents one
Default>>>
X X X X 0 0 0 0
possible ID with the most significant bit represent-
ing ID 7 and the least significant bit representing
ID 0. The SCID register still contains the chip ID
Bits 7-4 Reserved
used during arbitration. The chip can respond to
more than one ID because more than one bit can be
Bits 3-0 GEN3-0 (General Purpose Timer set in the RESPID register. However, the chip can
Period) arbitrate with only one ID value in the SCID regis-
These bits select the period of the general pur- ter.
pose timer. The time measured is the time
between enabling and disabling of the timer.
When this timing is exceeded, the GEN bit in
the SIST1 register is set. Refer to the table
under STIME0, bits 3-0, for the available
time-out periods.
Note: to reset a timer before it has expired and to
obtain repeatable delays, the time value
must be written to zero first, and then
written back to the desired value. This is
also required when changing from one time
value to another. See Chapter 2,
“Functional Description,” for an
explanation of how interrupts are
generated when the timers expire.

Operating Registers
Bit 1 SOZ (SCSI Synchronous Offset

Register 4C (CC) Zero)
SCSI Test Zero (STEST0) This bit indicates that the current synchronous
Read Only SREQ/SACK offset is zero. This bit is not
SSAID SSAID SSAID
latched and may change at any time. It is used
RES SLT ART SOZ SOM
2 1 0 in low level synchronous SCSI operations.
7 6 5 4 3 2 1 0 When this bit is set, the SYM53C810A, as an
Default>>> initiator, is waiting for the target to request
X X X X 0 X 1 1
data transfers. If the SYM53C810A is a target,
then the initiator has sent the offset number of
Bit 7 Reserved acknowledges.
Bits 6-4 SSAID (SCSI Selected As ID) Bit 0 SOM (SCSI Synchronous Offset
These bits contain the encoded value of the Maximum)
SCSI ID that the SYM53C810A was selected This bit indicates that the current synchronous
or reselected as during a SCSI selection or SREQ/SACK offset is the maximum specified
reselection phase. These bits are read only and by bits 3-0 in the SCSI Transfer register. This
contain the encoded value of 0-7 possible IDs bit is not latched and may change at any time.
that could be used to select the It is used in low level synchronous SCSI opera-
SYM53C810A. During a SCSI selection or tions. When this bit is set, the SYM53C810A,
reselection phase when a valid ID has been put as a target, is waiting for the initiator to
on the bus, and the 53C810A responds to that acknowledge the data transfers. If the
ID, the “selected as” ID is written into these SYM53C810A is an initiator, then the target
bits. has sent the offset number of requests.
Bit 3 SLT (Selection response logic test)

This bit is set when the SYM53C810A is ready
to be selected or reselected. This does not take
into account the bus settle delay of 400 ns.
This bit is used for functional test and fault
purposes.
Bit 2 ART (Arbitration Priority Encoder

Test)
This bit will always be set when the
SYM53C810A exhibits the highest priority ID
asserted on the SCSI bus during arbitration. It
is primarily used for chip level testing, but it
may be used during low level mode operation
to determine if the SYM53C810A has won
arbitration.

Operating Registers
Register 4D (CD) Register 4E (CE)

SCSI Test One (STEST1) SCSI Test Two (STEST2)
SCLK SISO RES RES RES RES RES RES SCE ROF RES SLB SZM RES EXT LOW
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 X X X X X X 0 0 X 0 0 X 0 0
Bit 7 SCLK Bit 7 SCE (SCSI Control Enable)

This bit, when set, disables the external SCLK This bit, when set, allows all SCSI control and
(SCSI Clock) pin, and causes the chip to use data lines to be asserted through the SOCL
the PCI clock as the internal SCSI clock. If a and SODL registers regardless of whether the
transfer rate of 10 MB/s is to be achieved on SYM53C810A is configured as a target or ini-
the SCSI bus, this bit must be cleared and the tiator.
chip must be connected to at least a 40 MHz
Note: this bit should not be set during normal
external SCLK.
operation, since it could cause contention
on the SCSI bus. It is included for
Bit 6 SISO (SCSI Isolation Mode) diagnostic purposes only.
This bit allows the SYM53C810A to put the
SCSI bi-directional and input pins into a low
Bit 6 ROF (Reset SCSI Offset)
power mode when the SCSI bus is not in use.
Setting this bit clears any outstanding synchro-
When this bit is set, the SCSI bus inputs are
nous SREQ/SACK offset. This bit should be
logically isolated from the SCSI bus.
set if a SCSI gross error condition occurs, to
clear the offset when a synchronous transfer
Bits 5-0 Reserved does not complete successfully. The bit auto-
matically clears itself after resetting the syn-
chronous offset.
Bit 5 Reserved
Bit 4 SLB (SCSI Loopback Mode)

Setting this bit allows the SYM53C810A to
perform SCSI loopback diagnostics. That is, it
enables the SCSI core to simultaneously per-
form as both initiator and target.
Bit 3 SZM (SCSI High-Impedance Mode)

Setting this bit places all the open-drain
48 mA SCSI drivers into a high-impedance
state. This is to allow internal loopback mode
operation without affecting the SCSI bus.
Bit 2 Reserved

Operating Registers
Bit 1 EXT( Extend SREQ/SACK

filtering) Register 4F (CF)
Symbios Logic TolerANT SCSI receiver tech- SCSI Test Three (STEST3)
nology includes a special digital filter on the Read/Write
SREQ/ and SACK/ pins which will cause TE STR HSC DSI RES TTM CSF STW
glitches on deasserting edges to be disregarded. 7 6 5 4 3 2 1 0
Setting this bit will increase the filtering period Default>>>
from 30ns to 60ns on the deasserting edge of 0 0 0 0 X 0 0 0
the SREQ/ and SACK/ signals.

Bit 7 TE (TolerANT Enable)
Note: this bit must never be set during fast SCSI
Setting this bit enables the active negation por-
(greater than 5M transfers per second)
tion of TolerANT technology. Active negation
operations, because a valid assertion could
causes the SCSI Request, Acknowledge, Data,
be treated as a glitch.
and Parity signals to be actively deasserted,
instead of relying on external pull-ups, when
Bit 0 LOW (SCSI Low level Mode)
the SYM53C810A is driving these signals.
Setting this bit places the SYM53C810A in
Active deassertion of these signals will occur
low level mode. In this mode, no DMA opera-
only when the SYM53C810A is in an informa-
tions occur, and no SCRIPTS execute. Arbi-
tion transfer phase. TolerANT active negation
tration and selection may be performed by
should be enabled to improve setup and deas-
setting the start sequence bit as described in
sertion times at fast SCSI timings. Active nega-
the SCNTL0 register. SCSI bus transfers are
tion is disabled after reset or when this bit is
performed by manually asserting and polling
cleared. For more information on TolerANT
SCSI signals. Clearing this bit allows instruc-
technology, refer to Chapter 1.
tions to be executed in SCSI SCRIPTS mode.
Note: it is not necessary to set this bit for access Bit 6 STR (SCSI FIFO Test Read)
to the SCSI bit-level registers (SODL, Setting this bit places the SCSI core into a test
SBCL, and input registers). mode in which the SCSI FIFO can be easily
read. Reading the SODL register will cause the
FIFO to unload.
Bit 5 HSC (Halt SCSI Clock)

Asserting this bit causes the internal divided
SCSI clock to come to a stop in a glitchless
manner. This bit may be used for test purposes
or to lower IDD during a power down mode.

Operating Registers
Bit 4 DSI (Disable Single Initiator

Response) Register 50 (D0)
If this bit is set, the SYM53C810A will ignore SCSI Input Data Latch (SIDL)
all bus-initiated selection attempts that employ Read Only
the single-initiator option from SCSI-1. In
This register is used primarily for diagnostic testing,
order to select the SYM53C810A while this bit
programmed I/O operation or error recovery. Data
is set, the SYM53C810A’s SCSI ID and the
received from the SCSI bus can be read from this
initiator’s SCSI ID must both be asserted. This
register. Data can be written to the SODL register
bit should be asserted in SCSI-2 systems so
and then read back into the SYM53C810A by
that a single bit error on the SCSI bus will not
reading this register to allow loopback testing.
be interpreted as a single initiator response.
When receiving SCSI data, the data will flow into
this register and out to the host FIFO. This register
Bit 3 Reserved
differs from the SBDL register; SIDL contains
latched data and the SBDL always contains exactly
Bit 2 TTM (Timer Test Mode) what is currently on the SCSI data bus. Reading
Setting this bit facilitates testing of the selec- this register causes the SCSI parity bit to be
tion time-out, general purpose, and hand- checked, and will cause a parity error interrupt if
shake-to-handshake timers by greatly reducing the data is not valid. The power-up values are inde-
all three time-out periods. Setting this bit starts terminate.
all three timers and, if the respective bits in the
SIEN1 register are set, causes the
SYM53C810A to generate interrupts at time-
out. This bit is intended for internal manufac-
turing diagnosis and should not be used.
Bit 1 CSF (Clear SCSI FIFO)

Setting this bit will cause the “full flags” for the
SCSI FIFO to be cleared. This empties the
FIFO. This bit is self-resetting. In addition, the
SCSI FIFO pointers, the SIDL, SODL, and
SODR Full bits in the SSTAT0 register are
cleared.
Bit 0 STW (SCSI FIFO Test Write)

Setting this bit places the SCSI core into a test
mode in which the FIFO can easily be written.
While this bit is set, writes to the SODL regis-
ter will cause the entire word contained in this
register to be loaded into the FIFO. Writing the
least significant byte of the SODL register will
cause the FIFO to load.

Operating Registers
Registers 54 (D4) Registers 58 (D8)

SCSI Output Data Latch (SODL) SCSI Bus Data Lines (SBDL)
Read/Write Read Only
This register is used primarily for diagnostic testing This register contains the SCSI data bus status.
or programmed I/O operation. Data written to this Even though the SCSI data bus is active low, these
register is asserted onto the SCSI data bus by set- bits are active high. The signal status is not latched
ting the Assert Data Bus bit in the SCNTL1 regis- and is a true representation of exactly what is on the
ter. This register is used to send data via data bus at the time the register is read. This regis-
programmed I/O. Data flows through this register ter is used when receiving data via programmed
when sending data in any mode. It is also used to I/O. This register can also be used for diagnostic
write to the synchronous data FIFO when testing testing or in low level mode. The power-up value of
the chip. The power-up value of this register is in- this register is indeterminate.
determinate.

Operating Registers

(Read/Write)
This is a general purpose user definable scratch pad
register. Apart from CPU access, only Register
Read/Write and Memory Moves directed at the
SCRATCH register will alter its contents. The
power-up values are indeterminate.
The SYM53C810A cannot fetch SCRIPTS in-
structions from this location.

Operating Registers

SCSI SCRIPTS
Chapter 6
After power up and initialization of the instruction may be written to the DMA SCRIPTS
SYM53C810A, the chip can operate in the low Pointer register to restart the automatic fetching
level register interface mode, or using SCSI and execution of instructions.
SCRIPTS. The SCSI SCRIPTS mode of execution allows the
With the low level register interface, the user has SYM53C810A to make decisions based on the sta-
access to the DMA control logic and the SCSI bus tus of the SCSI bus, so that the microprocessor
control logic. An external processor has access to does not have to service all of the interrupts inher-
the SCSI bus signals and the low level DMA sig- ent in I/O operations.
nals, which allows creation of complicated board Given the rich set of SCSI-oriented features
level test algorithms. The low level interface is use- included in the instruction set, and the ability to
ful for backward compatibility with SCSI devices re-enter the SCSI algorithm at any point, this high
that require certain unique timings or bus level interface is all that is required for both normal
sequences to operate properly. Another feature and exception conditions. There is no need to
allowed at the low level is loopback testing. In switch to low level mode for error recovery.
loopback mode, the SCSI core can be directed to
Five types of SCRIPTS instructions are imple-
talk to the DMA core to test internal data paths all
mented in the SYM53C810A:
the way out to the chip’s pins.
■ Block Move—used to move data between the
SCSI bus and memory
SCSI SCRIPTS ■ I/O or Read/Write—causes the SYM53C810A
to trigger common SCSI hardware sequences,
To operate in the SCSI SCRIPTS mode, the or to move registers
SYM53C810A requires only a SCRIPTS start
address. The start address must be at a dword ■ Transfer Control— allows SCRIPTS
(four byte) boundary. This aligns the following instructions to make decisions based on real
SCRIPTS at a dword boundary, since all time SCSI bus conditions
SCRIPTS are 8 or 12 bytes long. All instructions ■ Memory Move— causes the SYM53C810A to
are fetched from external memory. The execute block moves between different parts of
SYM53C810A fetches and executes its own main memory
instructions by becoming a bus master on the host
bus and fetching two or three 32-bit words into its ■ Load and Store—provides a more efficient way
registers. Instructions are fetched until an inter- to move data to/from memory from/to an
rupt instruction is encountered, or until an unex- internal register in the chip without using the
pected event (such as a hardware error) causes an Memory Move instruction.
interrupt to the external processor. Each instruction consists of two or three 32-bit
Once an interrupt is generated, the SYM53C810A words. The first 32-bit word is always loaded into
halts all operations until the interrupt is serviced. the DCMD and DBC registers, the second into
Then, the start address of the next SCRIPTS the DSPS register. The third word, used only by
Memory Move instructions, is loaded into the
TEMP shadow register. In an indirect I/O or Move
instruction, the first two 32-bit op code fetches will
be followed by one or two more 32-bit fetch cycles.
SCSI SCRIPTS
The process repeats until the internally stored byte

Sample Operation count has reached zero. The SYM53C810A
The following example describes execution of a releases the PCI bus and then requests use of the
SCRIPTS instruction. This sample operation is for PCI bus again for another SCRIPTS instruction
a Block Move instruction. Figure 6-1 illustrates a fetch cycle, using the incremented stored address
SCRIPTS Initiator Write operation, which uses maintained in the DMA SCRIPTS Pointer regis-
several Block Move instructions. ter. Execution of SCRIPTS instructions continues
until an error condition occurs or an interrupt
1. The host CPU, through programmed I/O, SCRIPTS instruction is received. At this point, the
gives the DMA SCRIPTS Pointer (DSP) SYM53C810A interrupts the host CPU and waits
register (in the Operating Register file) the for further servicing by the host system. It can exe-
starting address in main memory that points to cute independent Block Move instructions, speci-
a SCSI SCRIPTS program for execution. fying new byte counts and starting locations in
2. Loading the DSP register causes the main memory. In this manner, the SYM53C810A
SYM53C810A to request use of the PCI bus performs scatter/gather operations on data without
to fetch its first instruction from main memory requiring help from the host program, generating a
at the address just loaded. host interrupt, or requiring an external DMA con-
troller to be programmed.
3. The SYM53C810A typically fetches two
dwords (64 bits) and decodes the high order
byte of the first dword as a SCRIPTS
instruction. If the instruction is a Block Move,
the lower three bytes of the first dword are
stored and interpreted as the number of bytes
to be moved. The second dword is stored and
interpreted as the 32-bit beginning address in
main memory to which the move is directed.
4. For a SCSI send operation, the SYM53C810A
waits until there is enough space in the DMA
FIFO to transfer a programmable size block of
data. For a SCSI receive operation, it waits
until enough data is collected in the DMA
FIFO for transfer to memory.
5. SYM53C810A requests use of the PCI bus
again, this time for data transfers.
6. When the SYM53C810A is again granted the
PCI bus, it will execute (as a bus master) a
burst transfer (programmable size) of data,
decrement the internally stored remaining byte
count, increment the address pointer, and then
release the PCI bus. The SYM53C810A stays
off the PCI bus until the FIFO can again hold
(for a write) or has collected (for a read)
enough data to repeat the process.

SCSI SCRIPTS
System Processor
S Write DSP
System Memory y
SCSI Initiator Write Example
s
• select ATN 0, alt_addr t Fetch
• move 1, identify_msg_buf, when MSG_OUT SCRIPTS
• move 6, cmd_buf, when CMD e
•
•
move 512, data_buf, when DATA_OUT
move 1, stat_in_buf, when STATUS m SYM53C810A SCSI
•
•
move 1, msg_in_buf, when MSG_IN
move SCNTL2 & 7F to SCNTL2
Bus
• clear ACK
•
•
wait disconnect alt2
int 10
B
Data
u
Data Structure
Message Buffer s
Command Buffer
Data Buffer
Status Buffer
Figure 6-1: SCRIPTS Overview

Block Move Instructions
Indirect
Block Move Instructions Use the fetched byte count, but fetch the data
address from the address in the instruction.
The Block Move SCRIPTS instruction is used to
move data between the SCSI bus and memory. For Command Byte Count
a Block Move instruction, the SYM53C810A
operates much like a chaining DMA device with a Address of Pointer to Data
SCSI controller attached. Figure 6-2 illustrates the
register bit values that represent a Block Move Once the data pointer address is loaded, it is
instruction. In Block Move instructions, bits 5 and executed as when the chip operates in the
4 (SIOM and DIOM) in the DMODE register direct mode. This indirect feature allows a
determine whether the source/destination address table of data buffer addresses to be specified.
resides in memory or I/O space. When data is Using the SCSI SCRIPTS assembler, the table
being moved onto the SCSI bus, SIOM controls offset is placed in the SCRIPTS file when the
whether that data comes from I/O or memory program is assembled. Then at the actual data
space. When data is being moved off of the SCSI transfer time, the offsets are added to the base
bus, DIOM controls whether that data goes to I/O address of the data address table by the exter-
or memory space. nal processor. The logical I/O driver builds a
structure of addresses for an I/O rather than
treating each address individually. This feature
First Dword makes it possible to locate SCSI SCRIPTS in a
Bits 31-30 Instruction Type-Block Move PROM.
Bit 29 Indirect Addressing Note: indirect and table indirect addressing
cannot be used simultaneously; only one
When this bit is cleared, user data is moved to
addressing method can be used at a time.
or from the 32-bit data start address for the
Block Move instruction. The value is loaded Bit 28 Table Indirect
into the chip’s address register and incre- When this bit is set, the 24-bit signed value in
mented as data is transferred. The address of the start address of the move is treated as a rel-
data to be moved is in the second dword of this ative displacement from the value in the DSA
instruction. register. Both the transfer count and the
When set, the 32-bit user data start address for source/destination address are fetched from
the Block Move is the address of a pointer to this address.
the actual data buffer address. The value at the
32-bit start address is loaded into the chip’s Command Not Used
DNAD register via a third dword fetch (4-byte Don’t Care Table Offset
transfer across the host computer bus).
Use the signed integer offset in bits 23-0 of the
Direct
second four bytes of the instruction, added to
The byte count and absolute address are as
the value in the DSA register, to fetch first the
follows.
byte count and then the data address. The
signed value is combined with the data struc-
Command Byte Count ture base address to generate the physical
Address of Data address used to fetch values from the data
structure. Sign-extended values of all ones for
negative values are allowed, but bits 31-24 are
ignored.

DCMD Register DBC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I/O
C/D 24-bit Block Move byte counter
MSG/
Op Code
Table Indirect Addressing
Indirect Addressing (53C700 compatible)
0 - Instruction Type - Block Move
0 - Instruction Type - Block Move
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-2: Block Move Instruction Register

Prior to the start of an I/O, the Data Structure Target Mode

Base Address register (DSA) should be loaded
with the base address of the I/O data structure. OPC Instruction Defined
The address may be any address on a long
0 MOVE
word boundary.
1 Reserved
After a Table Indirect op code is fetched, the
DSA is added to the 24-bit signed offset value
from the op code to generate the address of the 1. The SYM53C810A verifies that it is connected
required data; both positive and negative off- to the SCSI bus as a target before executing
sets are allowed. A subsequent fetch from that this instruction.
address brings the data values into the chip. 2. The SYM53C810A asserts the SCSI phase
For a MOVE instruction, the 24-bit byte count signals (SMSG/, SC_D/, and SI_O/) as defined
is fetched from system memory. Then the 32- by the Phase Field bits in the instruction.
bit physical address is brought into the 3. If the instruction is for the command phase,
SYM53C810A. Execution of the move begins the SYM53C810A receives the first command
at this point. byte and decodes its SCSI Group Code.
SCRIPTS can directly execute operating sys-
a) If the SCSI Group Code is either Group 0,
tem I/O data structures, saving time at the
Group 1, Group 2, or Group 5, then the
beginning of an I/O operation. The I/O data
SYM53C810A overwrites the DBC
structure can begin on any dword boundary
register with the length of the Command
and may cross system segment boundaries.
Descriptor Block: 6, 10, or 12 bytes.
There are two restrictions on the placement of
pointer data in system memory: the eight bytes b) If any other Group Code is received, the
of data in the MOVE instruction must be con- DBC register is not modified and the
tiguous, as shown below; and indirect data SYM53C810A will request the number of
fetches are not available during execution of a bytes specified in the DBC register. If the
Memory-to-Memory DMA operation. DBC register contains 000000h, an illegal
instruction interrupt is generated.
00 Byte Count 4. The SYM53C810A transfers the number of
bytes specified in the DBC register starting at
Physical Data Address
the address specified in the DNAD register.
Bit 27 Op Code 5. If the SATN/ signal is asserted by the initiator

or a parity error occurred during the transfer,
This 1-bit field defines the instruction to be
the transfer can optionally be halted and an
executed as a block move (MOVE).
interrupt generated. The Disable Halt on
Parity Error or ATN bit in the SCNTL1
register controls whether the SYM53C810A
will halt on these conditions immediately, or
wait until completion of the current Move.

Initiator Mode Bits 26-24 SCSI Phase

This 3-bit field defines the desired SCSI infor-
OPC Instruction Defined mation transfer phase. When the
0 Reserved SYM53C810A operates in initiator mode,
these bits are compared with the latched SCSI
1 MOVE
phase bits in the SSTAT1 register. When the
SYM53C810A operates in target mode, the
1. The SYM53C810A verifies that it is connected SYM53C810A asserts the phase defined in this
to the SCSI bus as an initiator before executing field. The following table describes the possible
this instruction. combinations and the corresponding SCSI
2. The SYM53C810A waits for an unserviced phase.
phase to occur. An unserviced phase is defined
as any phase (with SREQ/ asserted) for which
the SYM53C810A has not yet transferred data MSG C/D I/O SCSI Phase
by responding with a SACK/.
0 0 0 Data out
3. The SYM53C810A compares the SCSI phase
0 0 1 Data in
bits in the DCMD register with the latched
SCSI phase lines stored in the SSTAT1 0 1 0 Command
register. These phase lines are latched when 0 1 1 Status
SREQ/ is asserted. 1 0 0 Reserved out
4. If the SCSI phase bits match the value stored 1 0 1 Reserved in
in the SSTAT1 register, the SYM53C810A 1 1 0 Message out
will transfer the number of bytes specified in 1 1 1 Message in
the DBC register starting at the address
pointed to by the DNAD register.
Bits 23-0 Transfer Counter
5. If the SCSI phase bits do not match the value This 24-bit field specifies the number of data
stored in the SSTAT1 register, the bytes to be moved between the SYM53C810A
SYM53C810A generates a phase mismatch and system memory. The field is stored in the
interrupt and the instruction is not executed. DBC register. When the SYM53C810A trans-
6. During a Message Out phase, after the fers data to/from memory, the DBC register is
SYM53C810A has performed a Select with decremented by the number of bytes trans-
Attention (or SATN/ has been manually ferred. In addition, the DNAD register is
asserted with a Set ATN instruction), the incremented by the number of bytes trans-
SYM53C810A will deassert SATN/ during the ferred. This process is repeated until the DBC
final SREQ/SACK handshake of the first move register has been decremented to zero. At that
of Message Out bytes after SATN/ was set. time, the SYM53C810A fetches the next
instruction.
7. When the SYM53C810A is performing a block
move for Message In phase, it will not deassert If bit 28 is set, indicating table indirect
the SACK/ signal for the last SREQ/SACK addressing, this field is not used. The byte
handshake. The SACK signal must be cleared count is instead fetched from a table pointed to
using the Clear SACK I/O instruction. by the DSA register.

I/O Instructions
Second Dword I/O Instructions

Bits 31-0 Start Address
The I/O SCRIPTS instruction causes the
This 32-bit field specifies the starting address
SYM53C810A to trigger common SCSI hardware
of the data to be moved to/from memory. This
sequences such as Set/Clear ACK, Set/Clear ATN,
field is copied to the DNAD register. When the
Set/Clear Target Mode, Select With ATN, or Wait
SYM53C810A transfers data to or from mem-
for Reselect. Figure 6-3 illustrates the register bit
ory, the DNAD register is incremented by the
values that represent an I/O instruction.
number of bytes transferred.
When bit 29 is set, indicating indirect address-
ing, this address is a pointer to an address in First Dword
memory that points to the data location. When
Bits 31-30 Instruction Type - I/O Instruction
bit 28 is set, indicating table indirect address-
ing, the value in this field is an offset into a Bits 29-27 Op Code
table pointed to by the DSA. The table entry The following Op Code bits have different
contains byte count and address information. meanings, depending on whether the
SYM53C810A is operating in initiator or tar-
get mode. Note: Op Code selections 101-111
are considered Read/Write instructions, and
are described in that section.
Target Mode
OPC2 OPC1 OPC0 Instruction Defined

0 0 0 Reselect
0 0 1 Disconnect
0 1 0 Wait Select
0 1 1 Set
1 0 0 Clear
Reselect Instruction
1. The SYM53C810A arbitrates for the SCSI bus
by asserting the SCSI ID stored in the SCID
register. If the SYM53C810A loses arbitration,
then it tries again during the next available
arbitration cycle without reporting any lost
arbitration status.
2. If the SYM53C810A wins arbitration, it
attempts to reselect the SCSI device whose ID
is defined in the destination ID field of the
instruction. Once the SYM53C810A has won
arbitration, it fetches the next instruction from
the address pointed to by the DSP register.

I/O Instructions
3. Therefore, the SCRIPTS can move on to the

next instructions before the reselection has
completed. It will continue executing
SCRIPTS until a SCRIPTS instruction that
requires a response from the initiator is
encountered.
4. If the SYM53C810A is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register. The SYM53C810A should manually
be set to initiator mode if it is reselected, or to
target mode if it is selected.
Disconnect Instruction
The SYM53C810A disconnects from the SCSI
bus by deasserting all SCSI signal outputs.
Wait Select Instruction
1. If the SYM53C810A is selected, it fetches the
next instruction from the address pointed to by
the DSP register.
2. If reselected, the SYM53C810A fetches the
next instruction from the address pointed to by
the 32-bit jump address field stored in the
DNAD register. The SYM53C810A should
manually be set to initiator mode when
reselected.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C810A will abort the Wait
Select instruction and fetch the next
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corre-
sponding bits in the SOCL register are set. SACK/
or SATN/ should not be set except for testing pur-
poses. When the target bit is set, the corresponding
bit in the SCNTL0 register is also set. When the
carry bit is set, the corresponding bit in the Arith-
metic Logic Unit (ALU) is set.
Note: none of the signals are set on the SCSI bus
in target mode.

I/O Instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES RES RES RES
Set/Clear ATN/
Set/Clear ACK/
Set/Clear Target Mode

Set/Clear Carry
Encoded Destination ID 0
Reserved
Reserved
Reserved
Reserved
Reserved
Select with ATN/
Table Indirect Mode
Relative Address Mode
Op Code bit 0
Op Code bit 1
Op Code bit 2
1 - Instruction Type - I/O
0 - Instruction Type - I/O
Second 32-bit word of the I/O instruction

DSPSRegister
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-bit Jump Address
Figure 6-3: I/O Instruction Register

I/O Instructions
Clear Instruction 32-bit jump address field stored in the DNAD

When the SACK/ or SATN/ bits are set, the corre- register. The SYM53C810A should manually
sponding bits are cleared in the SOCL register. be set to initiator mode if it is reselected, or to
SACK/ or SATN/ should not be set except for test- target mode if it is selected.
ing purposes. When the target bit is set, the corre- 4. If the Select with SATN/ field is set, the
sponding bit in the SCNTL0 register is cleared. SATN/ signal is asserted during the selection
When the carry bit is set, the corresponding bit in phase.
the ALU is cleared.
Wait Disconnect Instruction
Note: none of the signals are reset on the SCSI
bus in target mode. 1. The SYM53C810A waits for the target to
perform a “legal” disconnect from the SCSI
Initiator Mode bus. A “legal” disconnect occurs when SBSY/
and SSEL/ are inactive for a minimum of one
Bus Free delay (400 ns), after the
SYM53C810A has received a Disconnect
OPC2 OPC1 OPC0 Instruction Defined Message or a Command Complete Message.
0 0 0 Select Wait Reselect Instruction
0 0 1 Wait Disconnect 1. If the SYM53C810A is selected before being
0 1 0 Wait Reselect reselected, it fetches the next instruction from
0 1 1 Set the address pointed to by the 32-bit jump
1 0 0 Clear
address field stored in the DNAD register. The
SYM53C810A should be manually set to
target mode when selected.
Select Instruction
2. If the SYM53C810A is reselected, it fetches
1. The SYM53C810A arbitrates for the SCSI bus
the next instruction from the address pointed
by asserting the SCSI ID stored in the SCID
to by the DSP register.
register. If the SYM53C810A loses arbitration,
it tries again during the next available 3. If the CPU sets the SIGP bit in the ISTAT
arbitration cycle without reporting any lost register, the SYM53C810A will abort the Wait
arbitration status. Reselect instruction and fetch the next
2. If the SYM53C810A wins arbitration, it
attempts to select the SCSI device whose ID is
register.
defined in the destination ID field of the
instruction. Once the SYM53C810A has won Set Instruction
arbitration, it fetches the next instruction from When the SACK/ or SATN/ bits are set, the corre-
the address pointed to by the DSP register. sponding bits in the SOCL register are set. When
Therefore, the SCRIPTS program can move to the Target bit is set, the corresponding bit in the
the next instruction before the selection has SCNTL0 register is also set. When the Carry bit is
completed. It will continue executing set, the corresponding bit in the ALU is set.
SCRIPTS until a SCRIPTS instruction that Clear Instruction
requires a response from the target is When the SACK/or SATN/ bits are set, the corre-
encountered. sponding bits are cleared in the SOCL register.
3. If the SYM53C810A is selected or reselected When the Target bit is set, the corresponding bit in
before winning arbitration, it fetches the next

I/O Instructions
the SCNTL0 register is cleared. When the Carry 2. An I/O command structure must have all four
bit is set, the corresponding bit in the ALU is bytes contiguous in system memory, as shown
cleared. below. The offset/period bits are ordered as in
Bit 26 Relative Addressing Mode the SXFER register. The configuration bits are
ordered as in the SCNTL3 register.
When this bit is set, the 24-bit signed value in
the DNAD register is used as a relative dis-
Config ID Offset/ (00)
placement from the current DSP address. This period
bit should only be used in conjunction with the
Select, Reselect, Wait Select, and Wait Reselect
This bit should only be used in conjunction
instructions. The Select and Reselect instruc-
with the Select, Reselect, Wait Select, and Wait
tions can contain an absolute alternate jump
Reselect instructions. Bits 25 and 26 may be
address or a relative transfer address.
set individually or in combination:
Bit 25 Table Indirect Mode
When this bit is set, the 24-bit signed value in Bit 25 Bit 26
the DBC register is added to the value in the
Direct 0 0
DSA register, used as an offset relative to the
value in the Data Structure Base Address Table Indirect 0 1
(DSA) register. The SCNTL3 value, SCSI ID, Relative 1 0
synchronous offset and synchronous period are Table Relative 1 1
loaded from this address. Prior to the start of
an I/O, the DSA should be loaded with the
Direct
base address of the I/O data structure. The
Uses the device ID and physical address in the
address may be any address on a dword bound-
instruction.
ary. After a Table Indirect op code is fetched,
the DSA is added to the 24-bit signed offset
value from the op code to generate the address
of the required data; both positive and negative Command ID Not Used Not Used
offsets are allowed. A subsequent fetch from
Absolute Alternate Address
that address brings the data values into the
chip.
SCRIPTS can directly execute operating sys- Table Indirect
tem I/O data structures, saving time at the Uses the physical jump address, but fetches data
beginning of an I/O operation. The I/O data using the table indirect method.
structure can begin on any dword boundary
and may cross system segment boundaries. Command Table Offset
There are two restrictions on the placement of Absolute Alternate Address
data in system memory:
1. The I/O data structure must lie within the 8 Relative
MB above or below the base address. Uses the device ID in the instruction, but treats
the alternate address as a relative jump.
Command ID Not Used Not Used
Alternate Jump Offset

I/O Instructions
Table Relative Bit 6 Set/Clear SACK/

Treats the alternate jump address as a relative Bit 3 Set/Clear SATN/
jump and fetches the device ID, synchronous off-
These two bits are used in conjunction with a
set, and synchronous period indirectly. Adds the
Set or Clear instruction to assert or deassert
value in bits 23-0 of the first four bytes of the
the corresponding SCSI control signal. Bit 6
SCRIPTS instruction to the data structure base
controls the SCSI SACK/ signal; bit 3 controls
address to form the fetch address.
the SCSI SATN/ signal.
Setting either of these bits will set or reset the
Command Table Offset
corresponding bit in the SOCL register,
Alternate Jump Offset depending on the instruction used. The Set
instruction is used to assert SACK/ and/or
Bit 24 Select with ATN/ SATN/ on the SCSI bus. The Clear instruction
is used to deassert SACK/ and/or SATN/ on
This bit specifies whether SATN/ will be
the SCSI bus.
asserted during the selection phase when the
SYM53C810A is executing a Select instruc- Since SACK/ and SATN/ are initiator signals,
tion. When operating in initiator mode, set this they will not be asserted on the SCSI bus
bit for the Select instruction. If this bit is set on unless the SYM53C810A is operating as an
any other I/O instruction, an illegal instruction initiator or the SCSI Loopback Enable bit is
interrupt is generated. set in the STEST2 register.
Bits 18-16 Encoded SCSI Destination ID The Set/Clear SCSI ACK/ATN instruction
would be used after message phase Block Move
This 3-bit field specifies the destination SCSI
operations to give the initiator the opportunity
ID for an I/O instruction.
to assert attention before acknowledging the
Bit 10 Set/Clear Carry last message byte. For example, if the initiator
This bit is used in conjunction with a Set or wishes to reject a message, an Assert SCSI
Clear instruction to set or clear the Carry bit. ATN instruction would be issued before a
Setting this bit with a Set instruction asserts Clear SCSI ACK instruction.
the Carry bit in the ALU. Setting this bit with a Bits 2-0 Reserved
Clear instruction deasserts the Carry bit in the
ALU.
Bit 9 Set/Clear Target Mode Second Dword
This bit is used in conjunction with a Set or Bits 31-0 Start Address
Clear instruction to set or clear target mode. This 32-bit field contains the memory address
Setting this bit with a Set instruction config- to fetch the next instruction if the selection or
ures the SYM53C810A as a target device (this reselection fails.
sets bit 0 of the SCNTL0 register). Clearing
If relative or table relative addressing is used,
this bit with a Clear instruction configures the
this value is a 24-bit signed offset relative to the
SYM53C810A as an initiator device (this
current DSP register value.
clears bit 0 of the SCNTL0 register).

Read/Write Instructions
Read/Write Instructions Second Dword

Bits 31-0 Destination Address
The Read/Write Instruction type moves the con-
This field contains the 32-bit destination
tents of one register to another, or performs arith-
address where the data is to be moved.
metic operations such as AND, OR, XOR,
Addition, and Shift. Figure 6-4 illustrates the reg-
ister bit values that represent a Read/Write instruc- Read-Modify-Write
tion.
Cycles
During these cycles the register is read, the
First Dword selected operation is performed, and the result is
Bits 31-30 Instruction Type - Read/Write written back to the source register.
Instruction The Add operation can be used to increment or
The Read/Write instruction uses operator bits decrement register values (or memory values if
26 through 24 in conjunction with the op code used in conjunction with a Memory-to-Register
bits to determine which instruction is currently Move operation) for use as loop counters.
selected.
Bits 29-27 Op Code Move to/from
The combinations of these bits determine if the SFBR Cycles
instruction is a Read/Write or an I/O instruc-
tion. Op codes 000 through 100 are considered All operations are read-modify-writes. However,
I/O instructions. Refer to Table 6-1 for field two registers are involved, one of which is always
definitions. the SFBR. The possible functions of this instruc-
tion are:
Bits 26-24 Operator
These bits are used in conjunction with the op ■ Write one byte (value contained within the
code bits to determine which instruction is SCRIPTS instruction) into any chip register.
currently selected. Refer to Table 6-1 for field ■ Move to/from the SFBR from/to any other
definitions. register.
Bits 22-16 Register Address - A(6-0) ■ Alter the value of a register with AND/OR/
Register values may be changed from ADD/XOR/SHIFT LEFT/SHIFT RIGHT
SCRIPTS in read-modify-write cycles or move operators.
to/from SFBR cycles. A(6-0) select an 8-bit
■ After moving values to the SFBR, the compare
source/destination register within the
and jump, call, or similar instructions may be
SYM53C810A.
used to check the value.
■ A Move-to-SFBR followed by a Move-from-
SFBR can be used to perform a register to
register move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Immediate Data Reserved

(must be 0)
A0
A1
A2 Register
A3 Address
A4
A5
A6
0 (Reserved)
Operator 0
Operator 1
Operator 2
Op Code bit 0
Op Code bit 1
Op Code bit 2
1 - Instruction Type - R/W
0 - Instruction Type - R/W
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-4: Read/Write Register Instruction

Table 6-1: Read/Write Instructions
Op Code 111 Op Code 110 Op Code 101

Operator
Read Modify Write Move to SFBR Move from SFBR
000 Move data into register. Move data into SFBR regis- Move data into register.
Syntax: “Move data8 to ter. Syntax: “Move data8 to Syntax: “Move data8 to
RegA” SFBR” RegA”
001* Shift register one bit to the Shift register one bit to the Shift the SFBR register one
left and place the result in left and place the result in bit to the left and place the
the same register. Syntax: the SFBR register. Syntax: result in the register. Syntax:
“Move RegA SHL RegA” “Move RegA SHL SFBR” “Move SFBR SHL RegA”
010 OR data with register and OR data with register and OR data with SFBR and
place the result in the same place the result in the SFBR place the result in the regis-
register. Syntax: “Move register. Syntax: “Move ter. Syntax: “Move SFBR |
RegA | data8 to RegA” RegA | data8 to SFBR” data8 to RegA”
011 XOR data with register and XOR data with register and XOR data with SFBR and
register. Syntax: “Move register. Syntax: “Move ter. Syntax: “Move SFBR
RegA XOR data8 to RegA” RegA XOR data8 to SFBR” XOR data8 to RegA”
100 AND data with register and AND data with register and AND data with SFBR and
register. Syntax: “Move register. Syntax: “Move ter. Syntax: “Move SFBR &
RegA & data8 to RegA” RegA & data8 to SFBR” data8 to RegA”
101* Shift register one bit to the Shift register one bit to the Shift the SFBR register one
right and place the result in right and place the result in bit to the right and place the
the same register. Syntax: the SFBR register. Syntax: result in the register. Syntax:
“Move RegA SHR RegA” “Move RegA SHR SFBR” “Move SFBR SHR RegA”
110 Add data to register without Add data to register without Add data to SFBR without
carry and place the result in carry and place the result in carry and place the result in
the same register. Syntax: the SFBR register. Syntax: the register. Syntax: “Move
“Move RegA + data8 to “Move RegA + data8 to SFBR + data8 to RegA”
RegA” SFBR”
111 Add data to register with Add data to register with Add data to SFBR with
carry and place the result in carry and place the result in carry and place the result in
the same register. Syntax: the SFBR register. Syntax: the register. Syntax: “Move
“Move RegA + data8 to “Move RegA + data8 to SFBR + data8 to RegA with
RegA with carry” SFBR with carry” carry”
Notes:
1. Substitute the desired register name or address for “RegA” in the syntax examples
2. data8 indicates eight bits of data
* Data is shifted through the Carry bit and the Carry bit is shifted into the data byte

Transfer Control Instructions
instruction.
Transfer Control 2. If the comparisons are false, the
Instructions SYM53C810A fetches the next instruction
from the address pointed to by the DSP
The Transfer Control, or Conditional Jump, register, leaving the instruction pointer
instruction allows you to write SCRIPTS that unchanged.
make decisions based on real time conditions on
the SCSI bus, such as phase or data. This instruc- Call Instruction
tion type includes Jump, Call, Return, and Inter- 1. The SYM53C810A can do a true/false
rupt instructions. Figure 6-5 illustrates the register comparison of the ALU carry bit, or compare
bit values that represent a Transfer Control the phase and/or data as defined by the Phase
instruction. Compare, Data Compare, and True/False bit
fields. If the comparisons are true, the
SYM53C810A loads the DSP register with the
First Dword
contents of the DSPS register and that address
Bits 31-30 Instruction Type - Transfer Control value becomes the address of the next
Instruction instruction.
Bits 29-27 Op Code When the SYM53C810A executes a Call
This 3-bit field specifies the type of transfer instruction, the instruction pointer contained
control instruction to be executed. All transfer in the DSP register is stored in the TEMP reg-
control instructions can be conditional. They ister. Since the TEMP register is not a stack
can be dependent on a true/false comparison and can only hold one dword, nested call
of the ALU Carry bit or a comparison of the instructions are not allowed.
SCSI information transfer phase with the 2. If the comparisons are false, the
Phase field, and/or a comparison of the First SYM53C810A fetches the next instruction
Byte Received with the Data Compare field. from the address pointed to by the DSP
Each instruction can operate in initiator or tar- register and the instruction pointer is not
get mode. modified.
Return Instruction
OPC2 OPC1 OPC0 Instruction Defined
1. The SYM53C810A can do a true/false
0 0 0 Jump comparison of the ALU carry bit, or compare
0 0 1 Call the phase and/or data as defined by the Phase
0 1 0 Return
Compare, Data Compare, and True/False bit
fields. If the comparisons are true, then the
0 1 1 Interrupt SYM53C810A loads the DSP register with the
1 X X Reserved contents of the DSPS register. That address
value becomes the address of the next
Jump Instruction instruction.
1. The SYM53C810Acan do a true/false When a Return instruction is executed, the
comparison of the ALU carry bit, or compare value stored in the TEMP register is returned
the phase and/or data as defined by the Phase to the DSP register. The SYM53C810A does
Compare, Data Compare and True/False bit not check to see whether the Call instruction
fields. If the comparisons are true, the has already been executed. It will not generate
SYM53C810A loads the DSP register with the an interrupt if a Return instruction is executed
contents of the DSPS register. The DSP without previously executing a Call instruc-
register now contains the address of the next tion.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mask for compare Data to be compared

with the SCSI First
Byte Received
Wait for Valid Phase
Compare Phase
Compare Data
Jump if: True=1, False=0
Interrupt on the Fly
Carry Test
0 (Reserved)
Relative addressing mode
I/O
C/D
MSG
Op Code bit 0
Op Code bit 1
Op Code bit 2
0 - Instruction Type - Transfer Control
1- Instruction Type - Transfer Control
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-5: Transfer Control Instruction

2. If the comparisons are false, then the ing SCSI phase. These bits are only valid when
SYM53C810A fetches the next instruction the SYM53C810A is operating in initiator
from the address pointed to by the DSP mode; when the SYM53C810A is operating in
register and the instruction pointer will not be the target mode, these bits should be cleared.
modified.
Interrupt Instructions MSG C/D I/O SCSI Phase

Interrupt
0 0 0 Data out
a) The SYM53C810A can do a true/false 0 0 1 Data in
comparison of the ALU carry bit, or
compare the phase and/or data as defined 0 1 0 Command
by the Phase Compare, Data Compare, 0 1 1 Status
and True/False bit fields. If the 1 0 0 Reserved out
comparisons are true, then the 1 0 1 Reserved in
SYM53C810A generates an interrupt by
1 1 0 Message out
asserting the IRQ/ signal.
1 1 1 Message in
b) The 32-bit address field stored in the
DSPS register (not DNAD as in 53C700)
Bit 23 Relative Addressing Mode
can contain a unique interrupt service
vector. When servicing the interrupt, this When this bit is set, the 24-bit signed value in
unique status code allows the ISR to the DSPS register is used as a relative offset
quickly identify the point at which the from the current DSP address (which is point-
interrupt occurred. ing to the next instruction, not the one cur-
rently executing). Relative mode does not
c) The SYM53C810A halts and the DSP apply to Return and Interrupt SCRIPTS.
register must be written to start any further
operation. Jump/Call an Absolute Address
Interrupt on-the-Fly Start execution at the new absolute address.
a) The SYM53C810A can do a true/false
Command Condition Codes
comparison of the ALU carry bit or
Absolute Alternate Address
compare the phase and/or data as defined
by the Phase Compare, Data Compare,
and True/False bit fields. If the Jump/Call a Relative Address
comparisons are true, and the Interrupt on Start execution at the current address plus (or
the Fly bit is set (bit 20), the minus) the relative offset.
SYM53C810A will assert the Interrupt on
the Fly bit (ISTAT bit 2). Command Condition Codes
Don’t Care Alternate Jump Offset
Bits 26-24 SCSI Phase
This 3-bit field corresponds to the three SCSI The SCRIPTS program counter is a 32-bit
bus phase signals which are compared with the value pointing to the SCRIPTS instruction
phase lines latched when SREQ/ is asserted. currently being executed by the
Comparisons can be performed to determine SYM53C810A. The next address is formed by
the SCSI phase actually being driven on the adding the 32-bit program counter to the 24-
SCSI bus. The following table describes the bit signed value of the last 24 bits of the Jump
possible combinations and their correspond-

or Call instruction. Because it is signed (twos must be true to branch on a true condition.
compliment), the jump can be forward or Both compares must be false to branch on a
backward. false condition.
A relative transfer can be to any address within
a 16-MB segment. The program counter is Result of
Bit 19 Action
combined with the 24-bit signed offset (using Compare
addition or subtraction) to form the new exe- 0 False Jump Taken
cution address. 0 True No Jump
SCRIPTS programs may contain a mixture of 1 False No Jump
direct jumps and relative jumps to provide
maximum versatility when writing SCRIPTS. 1 True Jump Taken
For example, major sections of code can be
accessed with far calls using the 32-bit physical Bit 18 Compare Data
address, then local labels can be called using When this bit is set, the first byte received from
relative transfers. If a SCRIPTS instruction the SCSI data bus (contained in SFBR regis-
uses only relative transfers it would not require ter) is compared with the Data to be Com-
any run time alteration of physical addresses, pared Field in the Transfer Control instruction.
and could be stored in and executed from a The Wait for Valid Phase bit controls when this
PROM. compare will occur. The Jump if True/False bit
Bit 21 Carry Test determines the condition (true or false) to
branch on.
When this bit is set, decisions based on the
ALU carry bit can be made. True/False com- Bit 17 Compare Phase
parisons are legal, but Data Compare and When the SYM53C810A is in initiator mode,
Phase Compare are illegal. this bit controls phase compare operations.
Bit 20 Interrupt on the Fly When this bit is set, the SCSI phase signals
(latched by SREQ/) are compared to the Phase
When this bit is set, the Interrupt instruction
Field in the Transfer Control instruction; if
will not halt the SCRIPTS processor. Once the
they match, the comparison is true. The Wait
interrupt occurs, the Interrupt on the Fly bit
for Valid Phase bit controls when the compare
(ISTAT bit 2) will be asserted.
will occur. When the SYM53C810A is operat-
Bit 19 Jump If True/False ing in target mode this bit, when set, tests for
This bit determines whether the an active SCSI SATN/ signal.
SYM53C810A should branch when a compar- Bit 16 Wait For Valid Phase
ison is true or when a comparison is false. This
If the Wait for Valid Phase bit is set, the
bit applies to phase compares, data compares,
SYM53C810A waits for a previously unser-
and carry tests. If both the Phase Compare and
viced phase before comparing the SCSI phase
Data Compare bits are set, then both compares
and data. If the Wait for Valid Phase bit is clear,
the SYM53C810A compares the SCSI phase
and data immediately.

Memory Move Instructions
Bits 15-8 Data Compare Mask

The Data Compare Mask allows a SCRIPTS Memory Move Instructions
instruction to test certain bits within a data
byte. During the data compare, any mask bits This SCRIPTS Instruction allows the
that are set cause the corresponding bit in the SYM53C810A to execute high performance block
SFBR data byte to be ignored. For instance, a moves of 32-bit data from one part of main mem-
mask of 01111111b and data compare value of ory to another. In this mode, the SYM53C810A is
1XXXXXXXb allows the SCRIPTS proces- an independent, high performance DMA control-
sor to determine whether or not the high order ler irrespective of SCSI operations. Since the regis-
bit is set while ignoring the remaining bits. ters of the SYM53C810A can be mapped into
system memory, this SCRIPTS instruction also
Bits 7-0 Data Compare Value
moves an SYM53C810A register to or from mem-
This 8-bit field is the data to be compared ory or another SYM53C810A register. Figure 6-6
against the SCSI First Byte Received (SFBR) illustrates the register bit values that represent a
register. These bits are used in conjunction Memory Move instruction.
with the Data Compare Mask Field to test for
For Memory Move instructions, bits 5 and 4
a particular data value.
(SIOM and DIOM) in the DMODE register
determine whether the source or destination
Second Dword addresses reside in memory or I/O space. By set-
ting these bits appropriately, data may be moved
Bits 31-0 Jump Address within memory space, within I/O space, or
This 32-bit field contains the address of the between the two address spaces.
next instruction to fetch when a jump is taken. The Memory Move instruction is used to copy the
Once the SYM53C810A has fetched the specified number of bytes from the source address
instruction from the address pointed to by to the destination address.
these 32 bits, this address is incremented by 4,
Allowing the SYM53C810A to perform memory
loaded into the DSP register and becomes the
moves frees the system processor for other tasks
current instruction pointer.
and moves data at higher speeds than available
from current DMA controllers. Up to 16 MB may
be transferred with one instruction. There are two
restrictions:
1. Both the source and destination addresses
must start with the same address alignment
(A(1-0) must be the same). If source and
destination are not aligned, then an illegal
instruction interrupt will occur.
2. Indirect addresses are not allowed. A burst of
data is fetched from the source address, put
into the DMA FIFO and then written out to
the destination address. The move continues
until the byte count decrements to zero, then
another SCRIPTS instruction is fetched from
system memory.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 - No Flush
0 (Reserved) 24-bit Memory Move byte counter
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
1 - Instruction Type - Memory Move
1 - Instruction Type - Memory Move
DSPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-6: Memory to Memory Move Instruction

The DSPS and DSA registers are additional hold-

ing registers used during the Memory Move; how- Read/Write System
ever, the contents of the DSA register are Memory from a SCRIPTS Instruction
preserved. By using the Memory Move instruction, single or
multiple register values may be transferred to or
from system memory.
First Dword
Because the SYM53C810A will respond to
Bits 31-30 Instruction Type - Memory Move addresses as defined in the Base I/O or Base Mem-
Instruction ory registers, it could be accessed during a Mem-
Bits 29-25 Reserved ory Move operation if the source or destination
These bits are reserved and must be zero. If address decodes to within the chip’s register space.
any of these bits is set, an illegal instruction If this occurs, the register indicated by the lower
interrupt will occur. seven bits of the address is taken to be the data
Bit 24 No Flush source or destination. In this way, register values
can be saved to system memory and later restored,
Note: this bit has no effect unless the Pre-fetch and SCRIPTS can make decisions based on data
Enable bit in the DCNTL register is set. values in system memory.
For information on SCRIPTS instruction
prefetching, see Chapter 2. The SFBR is not writable via the CPU, and there-
fore not by a Memory Move. However, it can be
When this bit is set, the SYM53C810A per- loaded via SCRIPTS Read/Write operations. To
forms a Memory Move (MMOV) without load the SFBR with a byte stored in system mem-
flushing the prefetch unit (NFMMOV). When ory, the byte must first be moved to an intermedi-
this bit is clear, the Memory Move instruction ate SYM53C810A register (for example, a
automatically flushes the prefetch unit. NFM- SCRATCH register), and then to the SFBR.
MOV should be used if the source and destina-
tion are not within four instructions of the The same address alignment restrictions apply to
current MMOV instruction. register access operations as to normal mem-
ory-to-memory transfers.
Bits 23-0 Transfer Count
The number of bytes to be transferred is stored
in the lower 24 bits of the first instruction
word.
Second Dword
Bits 31-0, DSPS Register
These bits contain the source address of the
Memory Move.
Third Dword
Bits 31-0, TEMP Register
These bits contain the destination address for
the Memory Move.

Load and Store Instructions
Bit 28, DSA Relative

Load and Store When this bit is clear, the value in the DSPS is
Instructions the actual 32-bit memory address to perform
the load/store to/from. When this bit is set, the
The Load and Store instruction provides a more chip determines the memory address to per-
efficient way to move data from/to memory to/from form the load/store to/from by adding the 24-
an internal register in the chip without using the bit signed offset value in the DSPS to the DSA.
normal memory move instruction. Bits 27-26, Reserved
The load and store instructions are represented by Bit 25, No Flush (Store instruction only)
two-dword op codes. The first dword contains the Note: this bit has no effect unless the Pre-fetch
DCMD and DBC register values. The second Enable bit in the DCNTL register is set.
dword contains the DSPS value. This is either the For information on SCRIPTS instruction
actual memory location of where to load or store, prefetching, see Chapter 2.
or the offset from the DSA, depending on the When this bit is set, the SYM53C810A per-
value of Bit 28 (DSA Relative). forms a Store without flushing the prefetch
A maximum of 4 bytes may be moved with these unit. When this bit is clear, the Store instruc-
instructions. The register address and memory tion automatically flushes the prefetch unit. No
address must have the same byte alignment, and Flush should be used if the source and destina-
the count set such that it does not cross dword tion are not within four instructions of the cur-
boundaries. The destination memory address in rent Store instruction.
the Store instruction and the source address in the Bit 24, Load/Store
Load instruction may not map back to the operat- When this bit is set, the instruction is a Load.
ing register set of the chip. If it does, a PCI illegal When cleared, it is a Store.
read/write cycle will occur, and the chip will issue Bit 23, Reserved
an interrupt (Illegal Instruction Detected) imme-
Bits 22-16, Register Address
diately following.
A6-A0 select the register to load/store to/from
Number of bytes allowed to load/ within the SYM053C810A.
Bits A1, A0
store Note: It is not possible to load the SFBR register,
00 One, two, three or four although the SFBR contents may be stored
in another location.
01 One, two, or three.
Bits 15-3, Reserved
10 One or two
Bits 2-0, Byte Count
11 One This value is the number of bytes to load/store.
The SIOM and DIOM bits in the DMODE regis-
ter determine whether the destination or source
Second Dword
address of the instruction is in Memory space or I/
O space. The Load/Store utilizes the PCI com- Bits 31-0, Memory/IO Address / DSA Offset
mands for I/O READ and I/O WRITE to access This is the actual memory location of where to
the I/O space. load or store, or the offset from the DSA register
value.
First Dword
Bit 31-29, Instruction Type
These bits should be 111, indicating the Load and
Store instruction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Byte Count

(must be 0) (Number of bytes
to load/store)
A0
A1
A2 Register
A3 Address
A4
A5
A6
0 (Reserved)
Load/Store
1 - No Flush
0 - Reserved
0 - Reserved
X - DSA Relative
1
1 Instruction Type - Load and Store
1
DSPS Register - Memory/ I/O Address/DSA Offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 6-7: Load and Store Instruction Format


DC Characteristics
Chapter 7
This chapter presents electrical and timing information for the SYM53C810A, using tables and timing
diagrams. Table 7-1 through Table 7-11 list the stress ratings, operating conditions, and DC characteris-
tics of the SYM53C810A. Table 7-12 and Figure 7-1 through Figure 7-5 show the effect of TolerANT
technology on the DC characteristics of the chip.The following section of this chapter presents the AC
characteristics of the SYM53C810A . The chip timings are presented in two sections. The first is the PCI
and external memory interface, followed by the SCSI interface timings.
DC Characteristics
Table 7-1: Absolute Maximum Stress Ratings
Symbol Parameter Min Max Unit Test Conditions
TSTG Storage temperature -55 150 °C -
VDD Supply voltage -0.5 7.0 V -
VIN Input Voltage VSS - 0.5 VDD + 0.5 V -
ILP* Latch-up current ± 150 - mA -
ESD** Electrostatic discharge - 2K V MIL-STD 883C,

Method 3015.7
Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied.
* -2V < VPIN < 8V
** SCSI pins only

DC Characteristics
Table 7-2: Operating Conditions
VDD Supply voltage 4.75 5.25 V -
IDD* Supply current (dynamic) - 130 mA -

Supply current (static) - 1 mA -
TA Operating free air 0 70 °C -
θJA Thermal resistance - 67 °C/W -

(junction to ambient air)
Conditions that exceed the operating limits may cause the device to function incorrectly
*Average operating supply current is 50 mA.
Table 7-3: SCSI Signals - SD(7-0)/, SDP/, SREQ/ SACK/
VIH Input high voltage 2.0 VDD + 0.5 V -
VIL Input low voltage VSS - 0.5 0.8 V -
VOH* Output high voltage 2.5 3.5 V 2.5 mA
VOL Output low voltage VSS 0.5 V 48 mA
IIN Input leakage -10 10 µA -
IOZ Tristate leakage -10 10 µA -
*TolerANT active negation enabled

DC Characteristics
Table 7-4: SCSI Signals - SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
IIN Input leakage -10 +10 µA -

(SRST/ only) -500 -50 µA
Table 7-5: Input Signals - CLK, SCLK, GNT/, IDSEL, RST/, TESTIN
IIN Input leakage -1.0 1.0 µA -
Note: CLK, SCLK, GNT/, and IDSEL have 100 µA pull-ups that are enabled when TESTIN is low. TESTIN has a 100 µA
pull-up that is always enabled.
Table 7-6: Capacitance
CI Input capacitance of - 7 pF -
input pads
CIO Input capacitance of I/O - 10 pF -

pads

DC Characteristics
Table 7-7: Output Signal - MAC/_TESTOUT, REQ/
VOH Output high voltage 2.4 VDD V -16 mA
IOH Output high current -8 - mA VDD - 0.5 V
IOL Output low current 16 - mA 0.4 V
Note: REQ/ has a 100 µA pull-up that is enabled when TESTIN is low
Table 7-8: Output Signal - IRQ/
IOH Output high current -4 - mA VDD - 0.5 V
Note: IRQ/ has a 100 µA pull-up that is enabled when TESTIN is low. IRQ/ can be enabled with a register bit as an open drain out-
put with an internal 100 µA pull-up.
Table 7-9: Output Signal - SERR/

DC Characteristics
Table 7-10: Bidirectional Signals - AD(31-0), C_BE/(3-0), FRAME, IRDY/, TRDY/, DEVSEL/, STOP/,
PERR/, PAR
VOH Output high voltage 2.4 VDD V 16 mA
IOH Output high current -8 - mA VDD - 0.5
IIN Input leakage -10 10 µA VSS < VIN < VDD
Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low
Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/
IOH Output high current -8 - mA 2.4V
IIN Input leakage -10 10 µA -
Note: All the signals in this table have 100 µA pull-ups that are enabled when TESTIN is low

TolerANT Technology
TolerANT Technology
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics
Symbol Parameter Min Max Units Test Conditions
VOH1 Output high voltage 2.5 3.5 V IOH = 2.5 mA
VOL Output low voltage 0.1 0.5 V IOL = 48 mA
VIH Input high voltage 2.0 7.0 V -
VIL Input low voltage -0.5 0.8 V Referenced to VSS
VIK Input clamp voltage -0.66 -0.77 V VDD = 4.75;

II = -20 mA
VTH Threshold, high to low 1.1 1.3 V -
VTL Threshold, low to high 1.5 1.7 V -
VTH- Hysteresis 200 400 mV -

VTL
IOH1 Output high current 2.5 24 mA VOH = 2.5 V
IOL Output low current 100 200 mA VOL = 0.5 V
IOSH1 Short-circuit output - 625 mA Output driving low,

high current pin shorted to VDD
supply2
IOSL Short-circuit output low - 95 mA Output driving

current high, pin shorted to
VSS supply
ILH Input high leakage - 10 µA -0.5 < VDD < 5.25

VPIN = 2.7 V
ILL Input low leakage - -10 µA -0.5 < VDD < 5.25
VPIN = 0.5 V
RI Input resistance 20 - MΩ SCSI pins3
CP Capacitance per pin - 10 pF PQFP
tR1 Rise time, 10% to 90% 9.7 18.5 ns Figure 7-1
Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 kΩ pull-up resistor

TolerANT Technology
Table 7-12: TolerANT Active Negation Technology Electrical Characteristics (Continued)
Symbol Parameter Min Max Units Test Conditions
tF Fall time, 90% to 10% 5.2 14.7 ns Figure 7-1
dVH/dt Slew rate, low to high 0.15 0.49 V/ns Figure 7-1
dVL/dt Slew rate, high to low 0.19 0.52 V/ns Figure 7-1
ESD Electrostatic discharge 2 - KV MIL-STD-883C;

3015-7
Latch-up 100 - mA -
Filter delay 20 30 ns Figure 7-2
Extended filter delay 40 60 ns Figure 7-2
Note: These values are guaranteed by periodic characterization; they are not 100% tested on every device.
1 Active negation outputs only: Data, Parity, SREQ/, SACK/
2Single pin only; irreversible damage may occur if sustained for one second
3SCSI RESET pin has 10 kΩ pull-up resistor
47 Ω
20 pF +
2.5 V
-
Figure 7-1: Rise and Fall Time Test Conditions
t1
REQ/ or ACK/ Input

VTH
*t1 is the input filtering period
Figure 7-2: SCSI Input Filtering

TolerANT Technology
1.1 1.3
Received Logic Level

0
1.5 1.7
Input Voltage (Volts)
Figure 7-3: Hysteresis of SCSI Receiver
+40
INPUT CURRENT (milliAmperes)
+20
14.4 V
8.2 V
0
-0.7 V
-20 HI-Z
OUTPUT
ACTIVE
-40
-4 0 4 8 12 16
INPUT VOLTAGE (Volts)
Figure 7-4: Input Current as a Function of Input Voltage

OUTPUT SOURCE CURRENT (milliAmperes)
0 100
OUTPUT SINK CURRENT (milliAmperes)
80
-200
60
-400
40
-600
20
-800 0
0 1 2 3 4 5 0 1 2 3 4 5
OUTPUT VOLTAGE (Volts) OUTPUT VOLTAGE (Volts)
Figure 7-5: Output Current as a Function of Output Voltage

AC Characteristics
AC Characteristics
The AC characteristics described in this section apply over the entire range of operating conditions (refer
to the DC Characteristics section), Chip timings are based on simulation at worst case voltage, tempera-
ture, and processing. Timings were developed with a load capacitance of 50 pF.
t1
t3
CLK/SCLK
t4
t2
Figure 7-6: Clock Timing Waveform
Table 7-13: Clock Timing
Symbol Parameter Min Max Units
t1 Bus clock cycle time 30 DC ns
SCSI clock cycle time (SCLK)* 25 60 ns
t2 CLK low time** 12 - ns
SCLK low time** 10 33 ns
t3 CLK high time** 12 - ns
SCLK high time** 10 33 ns
t4 CLK slew rate 1 - V/ns
SCLK slew rate 1 - V/ns
* This parameter must be met to insure SCSI timings are within specification
**Duty cycle not to exceed 60/40

AC Characteristics
CLK
t2
t1
RST/
Figure 7-7: Reset Input Waveforms
Table 7-14: Reset Input Timings
t1 Reset pulse width 10 - tCLK
t2 Reset deasserted setup to CLK high 0 - ns
t2 t3 t1
IRQ/
CLK
Figure 7-8: Interrupt Output Waveforms
Table 7-15: Interrupt Output Timings
t1 CLK high to IRQ/ low - 20 ns
t2 CLK high to IRQ/ high - 40 ns
t3 IRQ/ deassertion time 3 - CLKs

PCI Interface Timing Diagrams

Figure 7-9 through Figure 7-18 represent signal activity when the SYM53C810A accesses the PCI bus.
The timings for the PCI bus interface are listed on page 7-22. The following timing diagrams are included
in this section:
Target Cycles
■ PCI configuration register read
■ PCI configuration register write
■ Target read
■ Target write
■
Initiator Cycles
■ Op code fetch, non-burst
■ Burst op code fetch
■ Back-to-back read
■ Back-to-back write
■ Burst read
■ Burst write

1 2 3 4 5
CLK
(Driven by System)
FRAME/ t1
(Driven by System)
t
2
t1 t3
AD/
Addr Data Out
(Driven by Master-Addr; In
53C810A-Data) t2
t1
C_BE/ CMD t
Byte Enable 2
(Driven by Master)
t2
t1 t3
PAR
(Driven by Master-Addr; In Out
53C810A-Data)
t2
IRDY/
t1 t
(Driven by Master) 2
TRDY/
(Driven by 53C810A) t
3
STOP/
(Driven by 53C810A)
t
3
DEVSEL/
(Driven by 53C810A)
t3
t1
IDSEL
(Driven by Master) t2
Figure 7-9: PCI Configuration Register Read

1 2 3 4 5
CLK
(Driven by System)
FRAME/ t
1
(Driven by Master)
t2 t2
t t1
1
AD/ Addr
(Driven by Master) In Data In
t2 t
t1 2
C_BE/ CMD Byte Enable

(Driven by Master) t2
t
PAR/ 1
(Driven by Master)
t
2
t1
IRDY/
(Driven by Master) t
2
TRDY/
3
STOP/
(Driven by 53C810A)
t
3
DEVSEL/
(Driven by 53C810A)
t1 t
3
t2
IDSEL
(Driven by Master)
Figure 7-10: PCI Configuration Register Write

1 2 3 4 5 6 7 8 9
CLK
(Driven by System)
t1
FRAME/ t2
(Driven by Master)
t1 t
3
AD Addr Data
53C810A-Data) t2
t1
C_BE/ CMD Byte Enable

(Driven by Master) t2 t2
t1 t
PAR 3
53C810A-Data) t
2
t1
IRDY/
t
TRDY t
3
(Driven by 53C810A)
t
STOP/ 3
(Driven by 53C810A)
DEVSEL/
(Driven by 53C810A)
t3
Figure 7-11: Target Read

1 2 3 4 5 6 7 8 9
CLK
(Driven by System)
t
1
FRAME/
t
t1 t
t1 2
AD/ Addr
(Driven by Master) In Data In
t
2
t
1
C_BE/
CMD Byte Enable
(Driven by Master)
t
2 t2
t1 t1
PAR/
(Driven by Master) t t
2 2
IRDY/
(Driven by Master) t1 t2
t
3
TRDY/
(Driven by 53C810A)
t
STOP/ 3
(Driven by 53C810A)
DEVSEL/
(Driven by 53C810A)
t3
Figure 7-12: Target Write

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
(Driven by System)
t
8
t7
GPIO0_FETCH/
(Driven by 53C810A)*
t
t 10
9
GPIO1_MASTER/
t
6
REQ/
(Driven by 53C810A)
t
4
GNT/
(Driven by Arbiter)
t
5
FRAME/
3 t
1
Data Data
In In
AD/ Addr Out Addr Out
(Driven by
t2
53C810A-Addr;
t
Target-Data) 3
CMD BE CMD BE
C_BE/
t
(Driven by 53C810A) 3 t
3 t
1
PAR/
(Driven by
53C810A-Addr; t t2
Target-Data) 3
IRDY/
t
(Driven by 53C810A) 3
t
1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target) t2
t
1
DEVSEL/
(Driven by Target)
Figure 7-13: Op Code Fetch, non-burst

1 2 3 4 5 6 7 9 10 11 12
CLK
(Driven by System)
t
8
t7
GPIO0_FETCH/
t
t 10
9
GPIO1_MASTER/
t
6
REQ/
(Driven by 53C810A)
t
GNT/ 4
(Driven by Arbiter)
t
5
FRAME/
3
t1
t Data
3 Data In
In
AD/ Addr Out
(Driven by
t2
53C810A-Addr;
t
Target-Data) 3
CMD BE CMD
C_BE/
t
(Driven by 53C810A) 3 t
3 t
1
PAR/ In In
Out
(Driven by
53C810A-Addr; t t2
Target-Data) 3
IRDY/
3
t
1
TRDY/
(Driven by Target)
t2
STOP/
t1
DEVSEL/
(Driven by Target)
Figure 7-14: Burst Op Code Fetch

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLK
(Driven by System)
GPIO0_FETCH/
t9 t10
GPIO1_MASTER/
(Driven by 53C810A)
REQ/
(Driven by 53C810A)
t t
6 5
GNT/
(Driven by Arbiter)
t
4
t
3
FRAME/
1
t
3 Data In Data In
AD/
Addr Addr
(Driven by Out Out
53C810A-Addr;
Target-Data) t2
t3
C_BE/
(Driven by 53C810A) CMD BE CMD BE
t1
t3
PAR/ Out In Out In
(Driven by
53C810A-Addr; t2
Target-Data)
t
3
IRDY/
(Driven by 53C810A)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1 t2
DEVSEL/
(Driven by Target)
Figure 7-15: Back to Back Read

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
(Driven by System)
GPIO0_FETCH/
t t
9 10
GPIO1_MASTER/
REQ/ t
6
(Driven by 53C810A)
t
4
GNT/
(Driven by Arbiter)
t
5
t3
FRAME/
(Driven by 53C810A)
t3 t3
AD/ Addr Data Data
Addr
(Driven by 53C810A) Out Out Out Out
t3
t3
C_BE/
(Driven by 53C810A) CMD BE CMD BE
t3 t3
PAR/
(Driven by 53C810A)
t3
IRDY/
(Driven by 53C810A)
t1
TRDY/
STOP/
(Driven by Target)
t1 t2
DEVSEL/
(Driven by Target)
Figure 7-16: Back to Back Write

7-20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
(Driven by System)
GPIO0_
FETCH/
(Driven by 53C810A)
t9 t 10
GPIO1_
MASTER/
(Driven by 53C810A) t6
REQ/
(Driven by 53C810A)
t5
GNT/ t4
(Driven by Arbiter)
t3
FRAME
(Driven by 53C810A)
t3 t3
AD Data Out
Addr Out Data Out Addr Out Data Out Addr Out Data Out
(Driven by 53C810A)
t3 t3
C_BE/ CMD BE CMD BE CMD BE
Figure 7-17: Burst Read

(Driven by 53C8150A
t3
t3
PAR
(Driven by 53C810A)
t3
IRDY/
(Driven by 53C810A)
t1 t2
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
t1 t2
DEVSEL/
(Driven by Target)
SYM53C810A Data Manual

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
(Driven by System)
SYM53C810A Data Manual

GPIO0_
FETCH/
(Driven by 53C810A)
t9 t 10
GPIO1_
MASTER/
(Driven by 53C810A) t6
REQ/
(Driven by 53C810A)
t5
GNT/ t4
(Driven by Arbiter)
t3
FRAME
(Driven by 53C810A)
t3 t3
AD Data Out
Addr Out Data Out Addr Out Data Out Addr Out Data Out
(Driven by 53C810A)
t3 t3
C_BE/ CMD BE CMD BE CMD BE

(Driven by 53C810A)
t3
Figure 7-18: Burst Write

t3
PAR
(Driven by 53C810A)
t3
IRDY/
(Driven by 53C810A)
t1 t2
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
t1 t2
DEVSEL/
(Driven by Target)
7-21
PCI Interface Timings
PCI Interface Timings
Table 7-16: SYM53C810A PCI Timings
Symbol Parameter Min Max Unit
t1 Shared signal input setup time 7 - ns
t2 Shared signal input hold time 0 - ns
t3 CLK to shared signal output valid - 11 ns
t4 Side signal input setup time 10 - ns
t5 Side signal input hold time 0 - ns
t6 CLK to side signal output valid - 12 ns
t7 CLK high to FETCH/ low - 20 ns
t8 CLK high to FETCH/ high - 20 ns
t9 CLK high to MASTER/ low - 20 ns
t10 CLK high to MASTER/ high - 20 ns

SCSI Timings
SCSI Timings
Initiator
Asynchronous Send
SREQ/ n n+1
t2
t1
SACK/ n n+1
t3 t4
SD7-SD0,
Valid n Valid n+1
SDP/
Figure 7-19: Initiator Asynchronous Send Waveforms
Table 7-17: Initiator Asynchronous Send Timings (5 MB/s)
t1 SACK/asserted from SREQ/ asserted 10 - ns
t2 SACK/deasserted from SREQ/ deasserted 10 - ns
t3 Data setup to SACK/asserted 55 - ns
t4 Data hold from SSREQ/deasserted 20 - ns

SCSI Timings
Initiator
Asynchronous Receive
SREQ/ n n+1
t1 t2
SACK/ n n+1
t3 t4
SD7-SD0,
Valid n Valid n+1
SDP/
Figure 7-20: Initiator Asynchronous Receive Waveforms
Table 7-18: Initiator Asynchronous Receive Timings (5MB/s)
t1 SACK/asserted from SREQ/asserted 10 - ns
t2 SACK/deasserted from SREQ/deasserted 10 - ns
t3 Data setup to SREQ/asserted 0 - ns
t4 Data hold from SACK/asserted 0 - ns

SCSI Timings
Target
Asynchronous Send
SREQ/ n n+1
t1 t2
SACK/ n n+1
t3 t4
SD7-SD0, Valid n Valid n+1
SDP/
Figure 7-21: Target Asynchronous Send Waveforms
Table 7-19: Target Asynchronous Send Timings (5 MB/s)
t1 SREQ/ deasserted from SACK/ asserted 10 - ns
t2 SREQ/ asserted from SACK/ deasserted 10 - ns
t3 Data setup to SREQ/ asserted 55 - ns
t4 Data hold from SACK/ asserted 20 - ns

SCSI Timings
Target
Asynchronous Receive
SREQ/ n n+1
t1 t2
SACK/ n n+1
t3 t4
SD15-SD0,
Valid n Valid n+1
SDP1/, SDP0/
Figure 7-22: Target Asynchronous Receive Waveforms
Table 7-20: Target Asynchronous Receive Timings (5 MB/s)
t1 SREQ/ deasserted from SACK/ asserted 10 - ns
t2 SREQ/ asserted from SACK/ deasserted 10 - ns
t3 Data setup to SACK/ asserted 0 - ns
t4 Data hold from SREQ/ deasserted 0 - ns

SCSI Timings
Initiator and
Target Synchronous Transfers
t1 t2
SREQ/ n n+1
or SACK/
t3 t4
Send Data
Valid n Valid n+1
SD7-SD0, SDP/
t5 t6
Receive Data
SD15-SD0, Valid n Valid n+1
SDP1/, SDP0/
Figure 7-23: Initiator and Target Synchronous Transfers
Table 7-21: SCSI-1 Transfers (Single-Ended, 5.0 MB/s)
t1 Send SREQ/ or SACK/ assertion pulse width 90 - ns
t2 Send SREQ/ or SACK/ deassertion pulse width 90 - ns
t1 Receive SREQ/ or SACK/ assertion pulse width 90 - ns
t2 Receive SREQ/ or SACK/ deassertion pulse width 90 - ns
t3 Send data setup to SREQ/ or SACK/ asserted 55 - ns
t4 Send data hold from SREQ/ or SACK/ asserted 100 - ns
t5 Receive data setup to SREQ/ or SACK/ asserted 0 - ns
t6 Receive data hold from SREQ/ or SACK/ asserted 45 - ns

SCSI Timings
Table 7-22: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 40 MHz clock)
Table 7-23: SCSI-2 Fast Transfers (10.0 MB/s (8-bit transfers), 50 MHz clock)
* Transfer period bits (bits 6-4 in the SXFER register) are set to zero and the Extra Clock cycle of Data Setup bit (bit 7 in
SCNTL1) is set.
* * Analysis of system configuration is recommended due to reduced driver skew margin in differential systems.
Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in STEST3).

Register Summary
Appendix A
Register Summary

SCSI Control Zero (SCNTL0) SCSI Control Two (SCNTL2)
Read/Write
Read/Write
SDU RES RES RES RES RES RES RES
ARB1 ARB0 START WATN EPC RES AAP TRG
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Default>>>
Default>>>
0 X X X X X X X
1 1 0 0 0 X 0 0
Bit 7 SDU (SCSI Disconnect Unexpected)
Bit 7 ARB1 (Arbitration mode bit 1) Bits 6-0 Reserved
Bit 6 ARB0 (Arbitration mode bit 0)
Bit 5 START (Start sequence)
Bit 4 WATN (Select with SATN/ on a start sequence) Register 03 (83)
Bit 3 EPC (Enable parity checking)
Bit 2 Reserved
SCSI Control Three (SCNTL3)
Bit 1 AAP (Assert SATN/ on parity error) Read/Write
Bit 0 TRG (Target role) RES SCF2 SCF1 SCF0 RES CCF2 CCF1 CCF0
7 6 5 4 3 2 1 0
Default>>>
Register 01 (81)
X 0 0 0 X 0 0 0
SCSI Control One (SCNTL1)
Read/Write Bit 7 Reserved
Bits 6-4 SCF2-0 (Synchronous Clock
EXC ADB DHP CON RST AESP IARB SST
Bit 3 Reserved
7 6 5 4 3 2 1 0 Bits 2-0 CCF2-0 (Clock Conversion Factor)
Default>>>
0 0 0 0 0 0 0 0
Bit 7 EXC (Extra clock cycle of data setup)

Bit 6 ADB (Assert SCSI data bus)
Bit 5 DHP (Disable Halt on Parity Error or ATN) (Tar-
get Only)
Bit 3 RST (Assert SCSI RST/ signal)
Bit 2 AESP (Assert even SCSI parity (force bad parity))
Bit 1 IARB (Immediate Arbitration)
Bit 0 SST (Start SCSI Transfer)
SYM53C810A Data Manual A-1

Register Summary

SCSI Chip ID (SCID) SCSI Transfer (SXFER)
RES RRE SRE RES RES ENC2 ENC1 ENC0 TP2 TP1 TP0 RES MO3 MO2 MO1 MO0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X 0 0 X X 0 0 0 0 0 0 X 0 0 0 0
Bit 7 Reserved Bits 7-5 TP2-0 (SCSI Synchronous Transfer Period)

Bit 6 RRE (Enable Response to Bit 4 Reserved
Reselection) Bits 3-0 MO3-MO0 (Max SCSI synchronous offset)
Bit 5 SRE (Enable Response to Selection)
Bit 4-3 Reserved
Bits 2-0 Encoded SYM53C810A Chip SCSI ID, bits 2-0 Register 06 (86)
SCSI Destination ID (SDID)
Read/Write
RES RES RES RES RES ENC2 ENC1 ENC0
7 6 5 4 3 2 1 0
Default>>>
X X X X X 0 0 0
Bits 7-3 Reserved

Bits 2-0 Encoded destination SCSI ID
Register 07 (87)
General Purpose (GPREG)
Read/Write
RES RES RES RES RES RES GPIO1 GPIO0
7 6 5 4 3 2 1 0
Default>>>
X X X X X X 0 0
Bits 7-2 Reserved

Bits 1-0 GPIO1-GPIO0 (General Purpose)
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write
1B7 1B6 1B5 1B4 1B3 1B2 1B1 1B0
7 6 5 4 3 2 1 0
Default>>>
0 0 0 0 0 0 0 0
A-2 SYM53C810A Data Manual

Register Summary
Register 09 (89) Register 0C (8C)

SCSI Output Control Latch (SOCL) DMA Status (DSTAT)
Read /Write Read Only
REQ ACK BSY SEL ATN MSG C/D I/O DFE MDPE BF ABRT SSI SIR RES IID
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 X 0
Bit 7 REQ(Assert SCSI REQ/ signal) Bit 7 DFE (DMA FIFO empty)
Bit 6 ACK(Assert SCSI ACK/ signal) Bit 6 MDPE (Master Data Parity Error)
Bit 5 BSY(Assert SCSI BSY/ signal) Bit 5 BF (Bus fault)
Bit 4 SEL(Assert SCSI SEL/ signal) Bit 4 ABRT (Aborted)
Bit 3 ATN(Assert SCSI ATN/ signal) Bit 3 SSI (Single step interrupt)
Bit 2 MSG(Assert SCSI MSG/ signal) Bit 2 SIR (SCRIPTS interrupt
Bit 1 C/D(Assert SCSI C_D/ signal) instruction received)
Bit 0 I/O(Assert SCSI I_O/ signal) Bit 1 Reserved
Register 0A (8A)
SCSI Selector ID (SSID) Register 0D (8D)
Read Only SCSI Status Zero (SSTAT0)
Read Only
VAL RES RES RES RES ENID2 ENID1 ENID0
7 6 5 4 3 2 1 0 ILF ORF OLF AIP LOA WOA RST SDP0/
Default>>> 7 6 5 4 3 2 1 0
0 X X X X 0 0 0 Default>>>
0 0 0 0 0 0 0 0
Bit 7 VAL (SCSI Valid Bit)
Bits 6-3 Reserved Bit 7 ILF (SIDL full)
Bits 2-0 Encoded Destination SCSI ID Bit 6 ORF (SODR full)
Bit 5 OLF (SODL full)
Bit 4 AIP (Arbitration in progress)
Register 0B (8B) Bit 3 LOA (Lost arbitration)
SCSI Bus Control Lines (SBCL) Bit 2 WOA (Won arbitration)
Bit 1 RST/ (SCSI RST/ signal)
Read Only
Bit 0 SDP/ (SCSI SDP/ parity signal)
REQ ACK BSY SEL ATN MSG C/D I/O
7 6 5 4 3 2 1 0
Default>>> Register 0E (8E)
X X X X X X X X SCSI Status One (SSTAT1)
Read Only
Bit 7 REQ (SREQ/ status)
Bit 6 ACK (SACK/ status) FF3 FF2 FF1 FF0 SDP0L MSG C/D I/O
Bit 5 BSY (SBSY/ status) 7 6 5 4 3 2 1 0
Bit 4 SEL (SSEL/ status) Default>>>
Bit 3 ATN SATN/ status) 0 0 0 0 X X X X
Bit 2 MSG (SMSG/ status)
Bit 1 C/D (SC_D/ status) Bits 7-4 FF3-FF0 (FIFO flags)
Bit 0 I/O (SI_O/ status) Bit 3 SDPL (Latched SCSI parity)
Bit 2 MSG (SCSI MSG/ signal)
Bit 1 C/D (SCSI C_D/ signal)
Bit 0 I/O (SCSI I_O/ signal)

Register Summary
Register 0F (8F) Register 1A (9A)

SCSI Status Two (SSTAT2) Chip Test Two (CTEST2)
(Read Only) Read Only
RES RES RES RES RES RES LDSC RES DDIR SIGP CIO CM RES TEOP DREQ DACK
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X X X X X X 1 X 0 0 X X 0 0 0 1
Bits 7-2 Reserved Bit 7 DDIR (Data transfer direction)

Bit 1 LDSC (Last Disconnect) Bit 6 SIGP (Signal process)
Bit 0 Reserved Bit 5 CIO (Configured as I/O)
Bit 4 CM (Configured as memory)
Bit 3 Reserved
Registers 10-13 (90-93) Bit 2 TEOP (SCSI true end of process)
Data Structure Address (DSA) Bit 1 DREQ (Data request status)
Bit 0 DACK (Data acknowledge status)
Read/Write
Register 1B (9B)
Register 14 (94)
Chip Test Three (CTEST3)
Interrupt Status (ISTAT)
Read/Write
(Read/Write)
V3 V2 V1 V0 FLF CLF FM WRIE
ABRT SRST SIGP SEM CON INTF SIP DIP
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Default>>>
Default>>>
X X X X 0 0 0 0
0 0 0 0 0 0 0 0
Bits 7-4 V3-V0 (Chip revision level)
Bit 7 ABRT (Abort operation)
Bit 3 FLF (Flush DMA FIFO)
Bit 6 SRST (Software reset)
Bit 2 CLF (Clear DMA FIFO)
Bit 5 SIGP (Signal process)
Bit 1 FM (Fetch pin mode)
Bit 4 SEM (Semaphore)
Bit 0 WRIE (Write and Invalidate Enable)
Bit 2 INTF (Interrupt on the Fly)
Bit 1 SIP (SCSI interrupt pending)
Bit 0 DIP (DMA interrupt pending)
Registers 1C-1F (9C-9F)
Temporary (TEMP)
Read/Write
Register 18 (98)
Chip Test Zero (CTEST0)
Read/Write Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write
Register 19 (99) RES BO6 BO5 BO4 Bo3 BO2 BO1 BO0
Chip Test One (CTEST1) 7 6 5 4 3 2 1 0
Read Only Default>>>
FMT3 FMT2 FMT1 FMT0 FFL3 FFL2 FFL1 FFL0 X 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit 7 Reserved
Default>>> Bits 6-0 BO6-BO0 (Byte offset counter)
1 1 1 1 0 0 0 0
Bits 7-4 FMT3-0 (Byte empty in DMA FIFO)

Bits 3-0 FFL3-0 (Byte full in DMA FIFO)

Register Summary
Register 21 (A1) Registers 28-2B (A8-AB)

Chip Test Four (CTEST4) DMA Next Address (DNAD)
BDIS ZMOD ZSD SRTM MPEE FBL2 FBL1 FBL0
7 6 5 4 3 2 1 0
Registers 2C-2F (AC-AF)
Default>>>
DMA SCRIPTS Pointer (DSP)
0 0 0 0 0 0 0 0
Read/Write
Bit 7 BDIS (Burst Disable)
Bit 6 ZMOD (High impedance mode)
Bit 5 ZSD (SCSI Data High Impedance) Registers 30-33 (B0-B3)
Bit 4 SRTM (Shadow Register Test Mode) DMA SCRIPTS Pointer Save (DSPS)
Bit 3 MPEE (Master Parity Error Enable)
Read/Write
Bits 2-0 FBL2-FBL0 (FIFO byte control)
Register 22 (A2) Registers 34-37 (B4-B7)

Chip Test Five (CTEST5) Scratch Register A (SCRATCH A)
ADCK BBCK RES MASR DDIR RES RES RES

7 6 5 4 3 2 1 0 Register 38 (B8)
Default>>> DMA Mode (DMODE)
0 0 X 0 0 X X X Read/Write
Bit 7 ADCK (Clock address incrementor) BL1 BL0 SIOM DIOM ERL ERMP BOF MAN
Bit 6 BBCK (Clock byte counter) 7 6 5 4 3 2 1 0
Bit 5 Reserved Default>>>
Bit 4 MASR (Master control for set or reset pulses) 0 0 0 0 0 0 0 0
Bit 3 DDIR (DMA direction)
Bits 2-0 Reserved Bit 7-6 BL1-BL0 (Burst length)
Bit 5 SIOM (Source I/O-Memory Enable)
Bit 4 DIOM (Destination I/O-Memory Enable)
Register 23 (A3) Bit 3 ERL (Enable Read Line)
Chip Test Six (CTEST6) Bit 2 ERMP (Enable Read Multiple)
Bit 1 BOF (Burst Op Code Fetch Enable)
Read/Write
Bit 0 MAN (Manual Start Mode)
DF7 DF6 DF5 DF4 DF3 DF2 DF1 DF0
7 6 5 4 3 2 1 0
Default>>> Register 39 (B9)
0 0 0 0 0 0 0 0 DMA Interrupt Enable (DIEN)
Read/Write
Bits 7-0 DF7-DF0 (DMA FIFO)
RES MDPE BF ABRT SSI SIR RES IID
7 6 5 4 3 2 1 0
Registers 24-26 (A4-A6) Default>>>
DMA Byte Counter (DBC) X 0 0 0 0 0 X 0
Read/Write
Bit 7 Reserved
Register 27 (A7) Bit 4 ABRT (Aborted)
DMA Command (DCMD) Bit 3 SSI (Single step interrupt)
Read/Write Bit 2 SIR (SCRIPTS interrupt
instruction received
Bit 1 Reserved

Register Summary
Register 3A (BA) Register 41 (C1)

Scratch Byte Register (SBR) SCSI Interrupt Enable One (SIEN1)
RES RES RES RES RES STO GEN HTH
7 6 5 4 3 2 1 0
Register 3B (BB)
Default>>>
DMA Control (DCNTL)
X X X X X 0 0 0
Read/Write
Bits 7-3 Reserved
CLSE PFF PFEN SSM IRQM STD IRQD COM
Bit 2 STO (Selection or Reselection Time-out)
7 6 5 4 3 2 1 0
Bit 1 GEN (General Purpose Timer Expired)
Default>>> Bit 0 HTH (Handshake to Handshake timer Expired)
0 0 0 0 0 0 0 0
Bit 7 CLSE (Cache Line Size Enable)

Bit 6 PFF (Pre-Fetch Flush)
Register 42 (C2)
Bit 5 PFEN (Pre-fetch Enable) SCSI Interrupt Status Zero (SIST0)
Bit 4 SSM (Single-step mode) Read Only
Bit 3 IRQM (IRQ Mode)
Bit 2 STD (Start DMA operation)
7 6 5 4 3 2 1 0
Bit 1 IRQD (IRQ Disable)
Bit 0 COM (53C700 compatibility) Default>>>
0 0 0 0 0 0 0 0
Bit 7 M/A (Initiator Mode: Phase Mismatch; Target

Register 3C-3F (BC-BF)
Mode: SATN/ Active)
Adder Sum Output (ADDER) Bit 6 CMP (Function Complete)
Read Only Bit 5 SEL (Selected)
Bit 4 RSL (Reselected)
Bit 3 SGE (SCSI Gross Error)
Register 40 (C0) Bit 2 UDC (Unexpected Disconnect)
SCSI Interrupt Enable Zero (SIEN0) Bit 1 RST (SCSI RST/ Received)
Bit 0 PAR (Parity Error)
Read/Write
7 6 5 4 3 2 1 0 Register 43 (C3)
Default>>> SCSI Interrupt Status One (SIST1)
0 0 0 0 0 0 0 0 Read Only
Bit 7 M/A (SCSI Phase Mismatch - RES RES RES RES RES STO GEN HTH
Initiator Mode; SCSI ATN 7 6 5 4 3 2 1 0
Condition - Target Mode) Default>>>
Bit 6 CMP (Function Complete) X X X X X 0 0 0
Bit 5 SEL (Selected)
Bit 4 RSL (Reselected) Bits 7-3 Reserved
Bit 3 SGE (SCSI Gross Error) Bit 2 STO (Selection or Reselection Time-out)
Bit 2 UDC (Unexpected Disconnect) Bit 1 GEN (General Purpose Timer Expired)
Bit 1 RST (SCSI Reset Condition) Bit 0 HTH (Handshake-to-Handshake Timer Expired)
Bit 0 PAR (SCSI Parity Error)
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write

Register Summary
Register 46 (C6) Register 4A (CA)

Memory Access Control (MACNTL) Response ID (RESPID)
TYP3 TYP2 TYP1 TYP0 DWR DRD PSCPT SCPTS
7 6 5 4 3 2 1 0
Register 4C (CC)
Default>>>
SCSI Test Zero (STEST0)
0 1 0 0 0 0 0 0
Read Only
Bits 7-4 TYP3-0 (Chip Type)
SSAID SSAID SSAID
Bit 3 DWR (DataWR) RES SLT ART SOZ SOM
2 1 0
Bit 2 DRD (DataRD)
7 6 5 4 3 2 1 0
Bit 1 PSCPT (Pointer SCRIPTS)
Default>>>
Bit 0 SCPTS (SCRIPTS)
X X X X 0 X 1 1
Bit 7 Reserved
Register 47 (C7) Bits 6-4 SSAID (SCSI Selected As ID)
General Purpose Pin Control (GPCNTL) Bit 3 SLT (Selection response logic test)
Read/Write Bit 2 ART (Arbitration Priority Encoder Test)
Bit 1 SOZ (SCSI Synchronous Offset Zero)
ME FE RES RES RES RES GPIO1 GPIO0
Bit 0 SOM (SCSI Synchronous Offset Maximum)
7 6 5 4 3 2 1 0
Default>>>
0 0 X 0 1 1 1 1 Register 4D (CD)
Bit 7 Master Enable
SCSI Test One (STEST1)
Bit 6 Fetch Enable Read/Write
Bit 5 Reserved SCLK SISO RES RES RES RES RES RES
Bits 1-0 GPIO1_EN– GPIO0_EN (GPIO Enable)
7 6 5 4 3 2 1 0
Default>>>
0 0 X X X X X X
Register 48 (C8)
SCSI Timer Zero (STIME0) Bit 7 SCLK
Read /Write Bit 6 SISO (SCSI Isolation Mode)
Bits 5-0 Reserved
HTH HTH HTH HRH SEL SEL SEL SEL
7 6 5 4 3 2 1 0
Default>>> Register 4E (CE)
0 0 0 0 0 0 0 0
SCSI Test Two (STEST2)
Bits 7-4 HTH (Handshake-to-Handshake Timer Period) Read/Write
Bits 3-0 SEL (Selection Time-Out) SCE ROF RES SLB SZM RES EXT LOW
7 6 5 4 3 2 1 0
Default>>>
Register 49 (C9)
0 0 X 0 0 X 0 0
SCSI Timer One (STIME1)
Read/Write Bit 7 SCE (SCSI Control Enable)
Bit 6 ROF (Reset SCSI Offset)
RES RES RES RES GEN3 GEN2 GEN1 GEN0
Bit 5 Reserved
7 6 5 4 3 2 1 0 Bit 4 SLB (SCSI Loopback Mode)
Default>>> Bit 3 SZM (SCSI High-Impedance Mode)
X X X X 0 0 0 0 Bit 2 Reserved
Bit 1 EXT( Extend SREQ/SACK
Bits 7-4 Reserved filtering)
Bits 3-0 GEN3-0 (General Purpose Timer Period) Bit 0 LOW (SCSI Low level Mode)

Register Summary
Register 4F (CF)
SCSI Test Three (STEST3)
Read/Write
TE STR HSC DSI RES TTM CSF STW
7 6 5 4 3 2 1 0
Default>>>
0 0 0 0 X 0 0 0
Bit 7 TE (TolerANT Enable)

Bit 6 STR (SCSI FIFO Test Read)
Bit 5 HSC (Halt SCSI Clock)
Bit 4 DSI (Disable Single Initiator Response)
Bit 3 Reserved
Bit 2 TTM (Timer Test Mode)
Bit 1 CSF (Clear SCSI FIFO)
Bit 0 STW (SCSI FIFO Test Write)
Register 50 (D0)
SCSI Input Data Latch (SIDL)
Read Only
Registers 54 (D4)
SCSI Output Data Latch (SODL)
Read/Write
Registers 58 (D8)
SCSI Bus Data Lines (SBDL)
Read Only

(Read/Write)

Mechanical Drawing
Appendix B
Mechanical Drawing
23.9 ± 0.25
20.0 ± 0.10
18.85
0.22 min
0.38 max
Pin 81
Pin 51
17.9 14.0 12.35 100-Pin Quad Flat Pack

± 0.25 ± 0.1
0.65
Pin 31
Pin 1
min
2.8
0.13
± 0.025
1.3
± 0.025
0 0 7
0.8 ± 0.15
SYM53C810A Data Manual B-1

Mechanical Drawing
B-2 SYM53C810A Data Manual

Index
Index
Numerics Assert SATN/ on parity error bit 5-6

3.3/5 Volt PCI interface 2-3 Assert SCSI ACK bit 5-15
53C700 compatibility bit 5-35 Assert SCSI ATN/ bit 5-15
Assert SCSI BSY/ bit 5-15
A
Assert SCSI C_D/ bit 5-15
AAP bit 5-6
Assert SCSI data bus bit 5-7
Abort operation bit 5-20
Assert SCSI I_O/ bit 5-15
Aborted bit 5-17, 5-33
Assert SCSI MSG/ bit 5-15
ABRT bit 5-17, 5-20, 5-33
Assert SCSI REQ/ signal bit 5-15
absolute maximum stress ratings 7-1
Assert SCSI RST/ signal bit 5-7
AC characteristics 7-9–7-10
clock timing 7-9 Assert SCSI SEL/ bit 5-15
interrupt output 7-10 ATN bit 5-15, 5-16
ACK bit 5-15, 5-16 B
active negation. See TolerANT BBCK bit 5-27
ADB bit 5-7 BDIS bit 5-26
ADCK bit 5-27 benefits summary 1-3
ADDER register 5-35 BF bit 5-16, 5-33
Adder Sum Output register 5-35 bidirectional signals 7-5–??
Additional Interface Pins 4-7 BL1-BL0 bits 5-31
Address and Data Pins 4-4 Block Move Instructions 6-4
AESP bit 5-7 BO6-BO0 bits 5-26
AIP bit 5-18 BOF bit 5-32
ARB1-0 bits 5-5 BSY bit 5-15, 5-16
arbitration Burst Disable bit 5-26
arbitration mode bits 5-5 Burst length bits 5-31
arbitration pins 4-5 Burst Mode Fetch Enable bit 5-32
Arbitration in progress bit 5-18 Bus fault bit 5-16, 5-33
Arbitration mode bits 5-5 Byte empty in DMA FIFO bits 5-23
Arbitration Priority Encoder Test bit 5-44 Byte full in DMA FIFO bits 5-23
ART bit 5-44 Byte offset counter bits 5-26
Assert even SCSI parity (force bad parity) bit 5-7
SYM53C810A Data Manual I-1

Index
C CTEST4 register 5-26

C_D bit 5-15, 5-16, 5-19 CTEST5 register 5-27
Cache Line Size Enable bit 5-34, A-6 CTEST6 register 5-28
cache mode, see PCI cache mode 3-2 D
capacitance 7-3 DACK bit 5-24
CCF2-0 bits 5-10 Data acknowledge status bit 5-24
chip block diagram 1-5 data path 2-7
chip revision level bits 5-24 Data request status bit 5-24
Chip Test Five register 5-27 Data Structure Address register 5-20
Chip Test Four register 5-26 Data transfer direction bit 5-23
Chip Test One register 5-23 DataRD bit 5-41
Chip Test Six register 5-28 DataWR bit
Chip Test Two register 5-23 DWR bit 5-41
Chip Test Zero register 5-22 DBC register 5-28
Chip Type bits 5-41 DC characteristics 7-1
CIO bit 5-23 absolute maximum stress ratings 7-1
Clear SCSI FIFO bit 5-47 bidirectional signals 7-5
Clock address incrementor bit 5-27 capacitance 7-3
Clock byte counter bit 5-27 input signals 7-3
Clock Conversion Factor bits 5-10 operating conditions 7-2
CLSE bit 5-34, A-6 output signals 7-4
CM bit 5-23 SCSI signals 7-2
CMP bit 5-36, 5-38 DCMD register 5-29
COM bit 5-35 DCNTL register 5-34
CON bit 5-7, 5-21 DDIR bit 5-23, 5-27
configuration registers. See PCI configuration reg- Destination I/O-Memory Enable bit 5-32
isters determining the data transfer rate 2-11
Configured as I/O bit 5-23 DF7-DF0 bits 5-28
Configured as memory bit 5-23 DFE bit 5-16
Connected bit 5-7, 5-21 DFIFO register 5-26
CSF bit 5-47 DHP bit 5-7
CTEST0 register 5-22 DIEN register 5-33
CTEST1 register 5-23 DIOM bit 5-32
CTEST2 register 5-23 DIP bit 5-22
Disable Halt on Parity Error or ATN bit 5-7
Disable Single Initiator Response bit 5-47
I-2 SYM53C810A Data Manual

Index
DMA Byte Counter register 5-28 ERL bit 5-32

DMA Command register 5-29 Error Reporting Pins 4-6
DMA Control register 5-34 EXC bit 5-7
DMA core 2-1 EXT bit 5-46
DMA direction bit 5-27 Extend SREQ/SACK filtering bit 5-46
DMA FIFO 2-6 Extra clock cycle of data setup bit 5-7
DMA FIFO bits 5-28 F
DMA FIFO empty bit 5-16 FBL2-FBL0 bits 5-27
DMA FIFO register 5-26 Fetch Enable bit 5-41
DMA Interrupt Enable register 5-33 fetch op code bursting 2-3
DMA interrupt pending bit 5-22 FF3-FF0 bits 5-18
DMA Mode register 5-31 FFL3-0 bits 5-23
DMA Next Address register 5-29 FIFO byte control bits 5-27
DMA SCRIPTS Pointer register 5-30 FIFO flags bits 5-18
DMA SCRIPTS Pointer Save register 5-30 FMT3-0 bits 5-23
DMA Status register 5-16 Function Complete bit 5-36, 5-38
DMODE register 5-31
G
DNAD register 5-29
GEN bit 5-37, 5-40
DRD bit 5-41
GEN3-0 bits 5-43
DREQ bit 5-24
general description 1-1
DSA register 5-20
General purpose bits 5-14
DSI bit 5-47
General Purpose Pin Control register 5-41
DSP register 5-30
General Purpose register 5-14
DSPS register 5-30
General Purpose Timer Expired bit 5-37, 5-40
DSTAT register 5-16
General Purpose Timer Period bits 5-43
E GPCNTL register 5-41
ease of use 1-3 GPIO Enable bits 5-41
Enable parity checking bit 5-6 GPIO1-0 bits 5-14
Enable Read Line bit 5-32 GPIO1EN_GPIO0EN bits 5-41
Enable Read Multiple bit 5-32, A-5 GPREG register 5-14
Enable Response to Reselection bit 5-11
H
Enable Response to Selection bit 5-11
Halt SCSI Clock bit
Encoded Chip SCSI ID, bits 2-0 5-11
HSC bit 5-46
Encoded Destination SCSI ID bits 5-15
Handshake to Handshake timer Expired bit 5-38
Encoded destination SCSI ID bits 5-13
Handshake-to-Handshake Timer Expired bit 5-40
EPC bit 5-6

Index
Handshake-to-Handshake Timer Period bits 5-42 IRQ Disable bit 5-34, A-6
High impedance mode bit 5-26 IRQ Mode bit 5-34
HTH bit 5-38, 5-40 IRQD bit 5-34, A-6
I IRQM bit 5-34
I/O bit 5-19 ISTAT register 5-20
I/O Instructions 6-8 L

I_O bit 5-15 Last Disconnect bit 5-19
IARB bit 5-8 Latched SCSI parity bit 5-18
IID bit 5-17, 5-33 LDSC bit 5-19
Illegal instruction detected bit 5-17, 5-33 LOA bit 5-18
Immediate arbitration bit 5-8 Load and Store instructions
Initiator Mode no flush option 6-24
Phase Mismatch 5-38 prefetch unit and Store instructions 2-2, 6-24
input signals 7-3 load and store instructions 6-24
instruction prefetch. See SCRIPTS instruction Lost arbitration bit 5-18
prefetching LOW bit 5-46
instruction set 6-1–6-25
M
instructions
M/A bit 5-36, 5-38
block move 6-4
MACNTL register 5-41
I/O 6-8
MAN bit 5-32
load and store 6-24
memory move 6-21 Manual Start Mode bit 5-32
read/write 6-14 MASR bit 5-27
transfer control 6-17 Master control for set or reset pulses bit 5-27
Interface Control Pins 4-5 Master Data Parity Error bit 5-16
Interrupt on the Fly bit 5-21 MDPE bit 5-33
interrupt output timings 7-10 Master Enable bit 5-41
Interrupt Status register 5-20 Master Parity Error Enable bit 5-27
interrupts Max SCSI Synchronous Offset bits 5-13
fatal vs. non-fatal interrupts 2-14 MDPE bit 5-16
halting 2-15 Memory Access Control register 5-41
IRQ Disable bit 2-14, 5-34, A-6 Memory Move Instructions 6-21
masking 2-14 Memory Move instructions
polling vs. hardware 2-13 and SCRIPTS instruction prefetching 2-2
registers 2-13 No Flush option 6-23
stacked interrupts 2-15 Memory Read Line command 3-4
INTF bit 5-21 Memory Read Multiple command 3-4

Index
Memory Write and Invalidate command 3-3 Memory Access Control 5-41
Write and Invalidate Mode bit 3-7 register address map 5-4
move to/from SFBR cycles 6-14 Response ID Zero 5-43
MPEE bit 5-27 Scratch Register A 5-31
MSG bit 5-15, 5-16, 5-19 Scratch Register B 5-49
SCSI Bus Control Lines 5-16
N
SCSI Bus Data Lines 5-48
NFMMOV instruction 6-23
SCSI Chip ID 5-11
No Flush Memory-to-Memory Move 6-23 SCSI Control One register 5-7
O SCSI Control Register Two 5-9
OLF bit 5-17 SCSI Control Three 5-9
op code fetch bursting 2-2 SCSI Control Zero 5-5
operating conditions 7-2 SCSI Destination ID 5-13
operating registers SCSI First Byte Received 5-14
Adder Sum Output 5-35 SCSI Input Data Latch 5-47
Chip Test Five 5-27 SCSI Interrupt Enable One 5-37
Chip Test Four 5-26 SCSI Interrupt Enable Zero 5-36
Chip Test One 5-23 SCSI Interrupt Status One 5-40
Chip Test Six 5-28 SCSI Interrupt Status Zero 5-38
Chip Test Three 5-24 SCSI Longitudinal Parity 5-40
Chip Test Two 5-23 SCSI Output Control Latch 5-15
Chip Test Zero 5-22 SCSI Output Data Latch 5-48
Data Structure Address 5-20 SCSI Selector ID 5-15
DMA Byte Counter 5-28 SCSI Status One 5-18
DMA Command 5-29 SCSI Status Two 5-19
DMA Control 5-34 SCSI Status Zero 5-17
DMA FIFO 5-26 SCSI Test One 5-45
DMA Interrupt Enable 5-33 SCSI Test Three 5-46
DMA Mode 5-31 SCSI Test Two 5-45
DMA Next Address 5-29 SCSI Test Zero 5-44
DMA SCRIPTS Pointer 5-30 SCSI Timer One 5-43
DMA SCRIPTS Pointer Save 5-30 SCSI Timer Zero 5-42
DMA Status 5-16 SCSI Transfer 5-11
DMA Watchdog Timer 5-33 Temporary Stack 5-25
general information 5-1 ORF bit 5-17
General Purpose 5-14 output signals 7-4
General Purpose Pin Control 5-41
Interrupt Status 5-20

Index
P Latency Timer 3-10

PAR bit 5-37, 5-39 Max_Lat 3-11
Parity 2-3–2-5 Min_Gnt 3-11
Assert even SCSI parity bit 5-7 Revision ID 3-10
Assert SATN/ on parity error bit 5-6 Status 3-8
Disable Halt on Parity Error bit 5-7 Vendor ID 3-7
Enable parity checking bit 5-6 PCI configuration space 3-1
Master Data Parity Error bit 5-33 PCI I/O space 3-1
Master Parity Error Enable bit 5-27 PCI memory space 3-1
Parity Error bit 5-39 PFEN bit 5-34, A-6
SCSI Parity Error bit 5-37 PFF bit 5-34, A-6
Parity Error bit 5-39 Phase Mismatch bit 5-38
PCI pins
addressing 3-1 additional interface pins 4-7
bus commands and functions supported 3-1 address and data pins 4-4
PCI addressing 3-1 arbitration pins 4-5
PCI bus commands and functions supported 3-1 error reporting pins 4-6
PCI cache mode 2-3, 3-2 interface control pins 4-5
Cache Line Size Enable bit 5-34, A-6 SCSI pins 4-6
Cache Line Size register 3-10 system pins 4-4
Enable Read Line bit 5-32 Pointer SCRIPTS bit
Enable Read Multiple bit 5-32, A-5 PSCPT bit 5-41
Memory Read Line command 3-4 Power and Ground Pins 4-2
Memory Read Multiple command 3-4 Pre-fetch Enable bit 5-34, A-6
Memory Write and Invalidate command 3-3 Pre-Fetch Flush bit 5-34, A-6
Write and Invalidate Mode bit 3-7
prefetching
Write and Invalidate Enable bit 5-25, A-4
prefetching. See SCRIPTS instruction
PCI commands 3-1
PCI configuration registers 3-6–3-11 R
Base Address One (Memory) 3-11 Read Multiple commands
Base Address Zero (I/O) 3-11 Enable Read Multiple bit 5-32, A-5
Cache Line Size 3-10 Read/Write Instructions 6-14
Class Code 3-10 read-modify-write cycles 6-14
Command 3-7 register addresses
Device ID 3-7 operating registers
Header Type 3-11 00h 5-5
Interrupt Line 3-11 01h 5-7
Interrupt Pin 3-11

Index
02h 5-9 48h 5-42

03h 5-9 49h 5-43
04h 5-11 4Ah 5-43
05h 5-11 4Ch 5-44
06h 5-13 4Dh 5-45
07h 5-14 4Eh 5-45
08h 5-14 4Fh 5-46
09h 5-15 50h 5-47
0Ah 5-15 54h 5-48
0Bh 5-16 58h 5-48
0Ch 5-16 5Ch-5Fh 5-49
0Dh 5-17 PCI configuration registers
0Eh 5-18 00h 3-7
0Fh 5-19 02h 3-7
10h-13h 5-20 04h 3-7
14h 5-20 06h 3-8
18 5-22 08h 3-10
19h 5-23 09h 3-10
1Ah 5-23 0Ch 3-10
1Ch-1Fh 5-25 0Dh 3-10
20h 5-26 0Eh 3-11
21h 5-26 10h 3-11
22h 5-27 14h 3-11
23h 5-28 3Ch 3-11
24h-26h 5-28 3Dh 3-11
27h 5-29 3Eh 3-11
28h-2Bh 5-29 3Fh 3-11
2Ch-2Fh 5-30 register bits
30h-33h 5-30
53C700 compatibility 5-35
34h-37h 5-31
38h 5-31 Abort operation 5-20
39h 5-33 Aborted 5-17, 5-33
3Ah 5-33 Arbitration in progress 5-18
3Bh 5-34 Arbitration mode 5-5
3Ch-3Fh 5-35 Arbitration Priority Encoder Test 5-44
40h 5-36 Assert even SCSI parity 5-7
41h 5-37
Assert SATN/ on parity error 5-6
42h 5-38
43h 5-40 Assert SCSI ACK 5-15
44h 5-40 Assert SCSI ATN/ 5-15
46h 5-41 Assert SCSI BSY/ 5-15
47h 5-41

Index
Assert SCSI C_D/ 5-15 Enable Read Line 5-32

Assert SCSI data bus 5-7 Enable Read Multiple 5-32, A-5
Assert SCSI I_O/ 5-15 Enable Response to Reselection 5-11
Assert SCSI MSG/ 5-15 Enable Response to Selection 5-11
Assert SCSI REQ/ signal 5-15 Encoded Chip SCSI ID, bits 2-0 5-11
Assert SCSI RST/ signal 5-7 Encoded destination ID 5-13
Assert SCSI SEL/ 5-15 Encoded Destination SCSI ID 5-15
Burst Disable 5-26 Encoded NCR 53C810A Chip SCSI ID, bits
Burst length 5-31 2-0 5-11, A-2
Burst Mode Fetch Enable 5-32 Extend SREQ/SACK filtering 5-46
Bus fault 5-33 Extra clock cycle of data setup 5-7
Byte Empty in DMA FIFO 5-23 Fetch Enable 5-41
Byte full in DMA FIFO 5-23 Fetch pin mode 5-24
Byte offset counter 5-26 FIFO byte control 5-27
Cache Line Size Enable 5-34, A-6 FIFO flags 5-18
Chip revision level 5-24 Flush DMA FIFO 5-24
Chip Type 5-41 Function Complete 5-36, 5-38
Clear DMA FIFO 5-24 General Purpose Timer Expired 5-37, 5-40
Clear SCSI FIFO 5-47 General Purpose Timer Period 5-43
Clock address incrementor 5-27 GPIO Enable 5-41
Clock byte counter 5-27 GPIO1-GPIO0 5-14, A-2
Clock Conversion Factor 5-10 Halt SCSI Clock 5-46
Configured as I/O 5-23 Handshake to Handshake timer Expired 5-38
Configured as memory 5-23 Handshake-to-Handshake Timer Expired 5-40
Connected 5-7, 5-21 Handshake-to-Handshake Timer Period 5-42
DACK 5-24 High impedance mode 5-26
Data transfer direction 5-23 Illegal instruction detected 5-17, 5-33
DataRD 5-41 Immediate arbitration 5-8
DataWR 5-41 Interrupt on the Fly 5-21
Destination I/O-Memory Enable 5-32 IRQ disable 5-34, A-6
Disable Halt on Parity Error 5-7 IRQ Mode 5-34
Disable Single Initiator Response 5-47 Last Disconnect 5-19
DMA direction 5-27 Latched SCSI parity 5-18
DMA FIFO 5-28 Lost arbitration 5-18
DMA FIFO empty bit 5-16 Manual Start Mode 5-32
DMA interrupt pending 5-22 Master control for set or reset pulses 5-27
DREQ 5-24 Master Data Parity Error 5-16, 5-33
Enable parity checking 5-6 Master Enable 5-41

Index
Master Parity Error Enable 5-27 SCSI Selected As ID 5-44, A-7

Max SCSI Synchronous Offset 5-13 SCSI Synchrnous Offset Zero 5-44
Parity Error 5-39 SCSI Synchronous Offset Maximum 5-44
Phase Mismatch or SATN/ Active 5-38 SCSI Synchronous Transfer Period 5-11
Pointer SCRIPTS 5-41 SCSI true end of process 5-24
Pre-Fetch Enable 5-34, A-6 SCSI Valid 5-15
Pre-Fetch Flush 5-34, A-6 Select with SATN/ on a start sequence 5-6
Reselected 5-36, 5-39 Selected 5-36, 5-39
Reset SCSI Offset 5-45 Selection or Reselection Time-Out 5-37
SACK/ status 5-16 Selection or Reselection Time-out 5-40
SATN/ status 5-16 Selection response logic test 5-44
SBSY/ status 5-16 Selection Time-Out 5-42
SC_D/ status 5-16 Semaphore 5-21
SCLK 5-45 Shadow Register Test Mode 5-26
SCRIPTS 5-41 SI_O/ status 5-16
SCRIPTS interrupt instruction received 5-17, SIDL full 5-17
5-33 Signal process 5-21, 5-23
SCSI C_D/ signal 5-19 Single step interrupt 5-17, 5-33
SCSI Control Enable 5-45 Single-step mode 5-34
SCSI Data High Impedance 5-26 SMSG/ status 5-16
SCSI Disconnect Unexpected 5-9 SODL full 5-17
SCSI FIFO Test Read 5-46 SODR full 5-17
SCSI FIFO Test Write 5-47 Software reset 5-20
SCSI Gross Error 5-36, 5-39 Source I/O-Memory Enable 5-31
SCSI High-Impedance Mode 5-45 SREQ/ status 5-16
SCSI I_O/ signal 5-19 SSEL/ status 5-16
SCSI interrupt pending 5-22 Start DMA operation 5-34
SCSI Isolation 5-45, A-7 Start SCSI transfer 5-8
SCSI Loopback Mode 5-45 Start sequence 5-5
SCSI Low level Mode 5-46 Synchronous Clock Conversion Factor bits 5-9
SCSI MSG/ signal 5-19 Target mode 5-6
SCSI Parity Error 5-37 Unexpected Disconnect 5-36, 5-39
SCSI Phase Mismatch or SCSI ATN Condi- WATN 5-6
tion 5-36
Won arbitration 5-18
SCSI Reset Condition 5-37
Write and Invalidate Enable 5-25, A-4
SCSI RST/ Received 5-39
Registers
SCSI RST/ signal 5-18
see operating registers
SCSI SDP/ signal 5-18
reliability 1-4

Index
REQ bit 5-15, 5-16 sample operation 6-2

reselect SCRIPTS bit 5-41
during reselection 2-9 SCRIPTS instruction prefetching
response to 2-9 No Flush Memory Move instruction 6-23
Reselected bit 5-36, 5-39 Pre-fetch Enable bit 5-34, A-6
Reset SCSI Offset bit 5-45 Pre-Fetch Flush bit 5-34, A-6
RESPID0 register 5-43 SCRIPTS interrupt instruction received bit 5-17,
Response ID Zero register 5-43 5-33
revision level bits 5-24 SCRIPTS processor 2-1
performance 2-1
ROF bit 5-45
SCSI
RRE bit 5-11
pins 4-6
RSL bit 5-36, 5-39
termination 2-9
RST bit 5-7, 5-37, 5-39
SCSI ATN Condition - Target Mode 5-36
RST/ bit 5-18
SCSI Bus Control Lines register 5-16
S SCSI Bus Data Lines register 5-48
SACK/ status bit 5-16 SCSI bus interface 2-9
SATN/ active bit 5-38 SCSI C_D/ signal 5-19
SATN/ status bit 5-16 SCSI Chip ID register 5-11
SBCL register 5-16 SCSI clock rates 5-10
SBDL register 5-48 SCSI Control Enable bit 5-45
SBR register 5-33 SCSI Control One register 5-7
SBSY/ status bit 5-16 SCSI Control Three register 5-9
SC_D/ status bit 5-16 SCSI Control Two register 5-9
SCE bit 5-45 SCSI Control Zero register 5-5
SCF2-0 bits 5-9 SCSI core 2-1
SCID register 5-11 SCSI Data High Impedance bit 5-26
SCLK bit 5-45 SCSI Destination ID register 5-13
SCNTL0 register 5-5 SCSI Device Management System (SDMS) 2-2
SCNTL1 register 5-7 SCSI Disconnect Unexpected bit 5-9
SCNTL2 register 5-9 SCSI FIFO Test Read bit 5-46
SCNTL3 register 5-9 SCSI FIFO Test Write bit 5-47
SCPTS bit 5-41 SCSI First Byte Received register 5-14
Scratch Byte register 5-33 SCSI Gross Error bit 5-36, 5-39
SCRATCHA register 5-31 SCSI High-Impedance Mode bit 5-45
SCRATCHB register 5-49 SCSI I_O/ bit 5-19
SCRIPTS

Index
SCSI Input Data Latch register 5-47 SCSI Test Three register 5-46
SCSI instructions SCSI Test Two register 5-45
block move 6-4 SCSI Test Zero register 5-44
I/O 6-8 SCSI Timer One register 5-43
load/store 6-24 SCSI Timer Zero register 5-42
memory move 6-21 SCSI timings 7-23–7-28
read/write 6-14 SCSI Transfer register 5-11
SCSI Interrupt Enable One register 5-37 SCSI true end of process bit 5-24
SCSI Interrupt Enable Zero register 5-36 SCSI Valid Bit 5-15
SCSI interrupt pending bit 5-22 SDID register 5-13
SCSI Interrupt Status One register 5-40 SDP/ bit 5-18
SCSI Interrupt Status Zero register 5-38 SDPL bit 5-18
SCSI Isolation bit 5-45, A-7 SDU bit 5-9
SCSI Longitudinal Parity register 5-40 SEL bit 5-15, 5-16, 5-36, 5-39
SCSI Loopback Mode bit 5-45 SEL bits 5-42
SCSI Low level Mode 5-46 Select with SATN/ on a start sequence bit 5-6
SCSI MSG/ bit 5-19 Selected bit 5-36, 5-39
SCSI Output Control Latch register 5-15 selection
SCSI Output Data Latch register 5-48 during reselection 2-9
SCSI Parity Error bit 5-37 during selection 2-9
SCSI Phase Mismatch - Initiator Mode bit 5-36 response to 2-9
SCSI Reset Condition bit 5-37 Selection or Reselection Time-out bit 5-37
SCSI RST/ Received bit 5-39 STO bit 5-40
SCSI RST/ signal bit 5-18 Selection response logic test bit 5-44
SCSI SCRIPTS operation 6-1 Selection Time-Out bits 5-42
SCSI SDP0/ parity signal bit 5-18 SEM bit 5-21
SCSI Selected As ID bits 5-44, A-7 Semaphore bit 5-21
SCSI Selector ID register 5-15 SFBR register 5-14
SCSI signals 7-2 SGE bit 5-36, 5-39
SCSI Status One register 5-18 Shadow Register Test Mode bit 5-26
SCSI Status Two register 5-19 SI_O bit 5-16
SCSI Status Zero register 5-17 SI_O/ status bit 5-16
SCSI Synchronous Offset Maximum bit 5-44 SIDL bit 5-17
SCSI Synchronous Offset Zero bit 5-44 SIDL least significant byte full bit 5-17
SCSI Synchronous Transfer Period bits 5-11 SIDL register 5-47
SCSI Test One register 5-45 SIEN0 register 5-36

Index
SIEN1 register 5-37 SSTAT2 register 5-19

Signal process bit 5-21, 5-23 stacked interrupts 2-15
SIGP bit 5-21, 5-23 START bit 5-5
Single step interrupt bit 5-17, 5-33 Start DMA operation bit 5-34
single-ended operation 2-9 Start SCSI Transfer bit 5-8
Single-step mode bit 5-34 Start sequence bit 5-5
SIOM bit 5-31 STD bit 5-34
SIP bit 5-22 STEST0 register 5-44
SIR bit 5-17, 5-33 STEST1 register 5-45
SISO bit 5-45, A-7 STEST2 register 5-45
SIST0 register 5-38 STEST3 register 5-46
SIST1 register 5-40 STIME0 register 5-42
SLB bit 5-45 STIME1 register 5-43
SLPAR register 5-40 STO bit 5-37
SLT bit 5-44 STR bit 5-46
SMSG/ status bit 5-16 STW bit 5-47
SOCL register 5-15 SXFER register 5-11
SODL least significant byte full bit 5-17 SYM53C810A
SODL register 5-48 ease of use 1-3
SODR least significant byte full bit 5-17 flexibility 1-4
Software reset bit 5-20 integration 1-3
SOM bit 5-44 performance 1-3
Source I/O-Memory Enable bit 5-31 reliability 1-4
testability 1-4
SOZ bit 5-44
SYMTolerANT Technology
SRE bit 5-11
electrical characteristics 7-6
SREQ/ status bit 5-16
Synchronous Clock Conversion Factor bits 5-9
SRST bit 5-20
synchronous data transfer rate 2-11
SRTM bit 5-26
synchronous operation 2-11
SSAID bits 5-44, A-7
system diagram 1-5
SSEL/ status bit 5-16
System Pins 4-4
SSI bit 5-17, 5-33
SZM bit 5-45
SSID register 5-15
SSM bit 5-34 T
SST bit 5-8 Target Mode
SSTAT0 register 5-17 SATN/ Active 5-38
SSTAT1 register 5-18 Target mode bit 5-6

Index
TE bit 5-46 W
TEMP register 5-25 WATN bit 5-6
Temporary register 5-25 what is covered in this manual 1-1
TEOP bit 5-24 WOA bit 5-18
termination 2-9 Won arbitration bit 5-18
testability 1-4 Write and Invalidate command
Timer Test Mode bit 5-47 Write and Invalidate Enable bit 5-25, A-4
timing diagrams 7-11–7-27 Z
interrupt output 7-10
ZMOD bit 5-26
PCI interface 7-22
ZSD bit 5-26
SCSI 7-28
SCSI timings 7-23
timings
clock 7-9
PCI 7-22
reset input 7-10
SCSI 7-23
TolerANT 1-2
Extend SREQ/SACK filtering bit 5-46
TolerANT Enable bit 5-46
TolerANT Enable bit 5-46
TP2-0 bits 5-11
transfer control instructions 6-17
prefetch unit flushing 2-2
transfer rate 1-3
Clock conversion factor bits 5-10
synchronous 2-11
Synchronous clock conversion factor bits 5-9
TRG bit 5-6
TTM bit 5-47
TYP3-0 bits 5-41
U
UDC bit 5-36, 5-39
Unexpected Disconnect bit 5-36, 5-39
V
VAL bit 5-15

Index

Symbios Logic
Sales Locations
For literature on any Symbios Logic product or

service, call our hotline toll-free 1-800-856-3093
North American Sales Locations International Sales Locations

Western Sales Area European Sales Headquarters
1731 Technology Drive, Suite 610 Westendstrasse 193\III
San Jose, CA 95110 80686 Muenchen
(408) 441-1080 Germany
011-49-89-547470-0
3300 Irvine Avenue, Suite 255
Newport Beach, CA 92660 Asia/Pacific Sales Headquarters
(714) 474-7095 37th Floor, Room 3702, Lippo Tower
Lippo Centre, 89 Queensway
Hong Kong
Eastern Sales Area 011-852-253-00727
8000 Townline Avenue, Suite 209
Bloomington, MN 55438-1000
(612) 941-7075
12377 Merit Dr.

Dallas, TX 75251
(972) 503-3205
92 Montvale Avenue, Suite 3500

Stoneham, MA 02180-3623
(617) 438-0043
30 Mansell Court, Suite 220

Roswell, GA 30076
(404) 641-8001
© Symbios Logic Inc.
Printed in the U.S.A.
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SYM53C810A

PCI-SCSI I/O Processor

SCRIPTS is a trademark and TolerANT is a registered trademark of Symbios Logic

It is the policy of Symbios Logic to improve products as new technology,

Copyright ©1995, 1996

SCSI and PCI Reference

Symbios Logic PCI-SCSI Programming Guide

SYM56C810A Data Manual i

Page No. Date Remarks

n/a 6/95 Rev 1.0

1-1,1-3, 1-5, 2-1—2- 7/96 Version 2.0

ii SYM56C810A Data Manual

SYM53C810A Data Manual iii

SCSI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

iv SYM53C810A Data Manual

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

SYM53C810A Data Manual v

vi SYM53C810A Data Manual

SYM53C810A Data Manual vii

Registers 34-37 (B4-B7)

viii SYM53C810A Data Manual

SYM53C810A Data Manual ix

x SYM53C810A Data Manual

Figure 1-1: SYM53C810A System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

SYM53C810A Data Manual xi

Figure 7-13: Op Code Fetch, non-burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

xii SYM53C810A Data Manual

SYM53C810A Data Manual xiii

Table 7-11: Bidirectional Signals - GPIO0_FETCH/, GPIO1_MASTER/ . . . . . . . . . . . . . . . . 7-5

xiv SYM53C810A Data Manual

What is Covered in This General Description

SYM53C810A Data Manual 1-1

SYM53C810A increases SCRIPTS performance

1-2 SYM53C810A Data Manual

SYM53C810A Benefits PCI Performance

SYM53C810A Data Manual 1-3

■ Three programmable SCSI timers: Select/

■ SDMS software for complete PC-based ■ Average operating supply current of 50 mA

1-4 SYM53C810A Data Manual

SCSI Term Connection

Figure 1-1: SYM53C810A System Diagram

PCI Master and Slave Control Block

Data SCSI Operating Config

SCSI FIFO and SCSI Control Block

TolerANT Technology Drivers and Receivers

Single-Ended SCSI Bus

Figure 1-2: SYM53C810A Chip Block Diagram

SYM53C810A Data Manual 1-5

1-6 SYM53C810A Data Manual

The SYM53C810A contains three functional

SYM53C810A Data Manual 2-1

all recent modifications, the prefetch unit

2-2 SYM53C810A Data Manual

PCI Cache Mode Parity Options

3.3 Volt/5 Volt PCI Interface

SYM53C810A Data Manual 2-3

Table 2-1: Bits Used for Parity Control and Observation

BIt Name Location Description

2-4 SYM53C810A Data Manual

Table 2-2: SCSI Parity Control