Onver e C Er (J : 9.9.2 The Dual-Slope Converter

930 ~ CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS
distinct values: positive when the differenc input signal is po 'tive, and negative WI
the difference input signal is negative. We shall study comparator circui· ill Chapter 13 1011
up/down counter is simply a counter that can count either up or down depending on' All
binary level applied at its up/down control tel-minal. Becau.e the A/D converter of Fig lhe
employs a DAC in its feedback loop it is usually 'alled a feedback-type A/D onver~e ,.43
operates as follows: With a 0 count in the counter, the D/A c nverter output Va, wil] be I. It
and the output of the comparator will be high, in trueting tbe ounter t COUnL the c~er(j
pulses in the up direction. As the count increase, tbe output of th DAC ri e . The proc ck
continues until the DAC output reaches the value of the analog input ignal, at whicb p ~~~
the comparator switches and stops the counter. The counter output will then be th digital
equivalent of the input analog voltage.
Operation of the converter of Fig. 9.43 is slow if it starts from zero. This converter how_
ever, tracks incremental changes in the input signal quite rapidly.
9.9.2 The Dual-Slope AID Converter

A very popular high-resolution (12- to 14-bit) (but slow) AID conversion scheme is illus-
trated in Fig. 9.44. To see how it operates, refer to Fig. 9.44 and assume that the analog
input signal VA is negative. Prior to the start of the conversion cycle, switch 52 is closed
thus discharging capacitor C and setting VI :::= O. The conversion cycle begins with openin~
52 and connecting the integrator input through switch 51 to the analog input signal. Since VA
is negative, a current 1:::= vAIR will flow through R in the direc;tion away from the integrator.
Thus VI rises linearly with a slope of IIC :::= vAIRC, as indicated in Fig. 9.44(b). Simulta-
neously; the counter is enabled and it counts the pulses from a fixed-frequency clock. This
phase of the conversion process continues for a fixed duration T,. It ends when the counter
has accumulated a fixed count denoted nREF' Usually, for an N-bit converter, nREF :::= 2N.
Denoting the peak voltage at the output of the integrator as VPEAK , we can write with reference
to Fig. 9.44(b)
(9.115)
At the end of this phase, the counter is reset to zero.

Phase II of the conversion begins at t :::= T] by connecting the integrator input through
switch 51 to the positive reference voltage VREF . The current into the integrator reverses
direction and is equal to VREFIR. Thus VI decreases linearly with a slope of (VREF/RC). Simul-
taneously the counter is enabled and it counts the pulses from the fixed-frequency clock.
When VI reaches zero volts, the comparator signals the control logic to stop the counter.
Denoting the duration of phase II by T2> we can write, by reference to Fig. 9.44(b),
V PEAK
--:::=--
V REF (9. Il6)
T2 RC
Equations (9.115) and (9.116) can be combined to yield
T2 :::= T] (~) (9.117)

VREF
Since the counter reading, nREF, at the end of T[ is proportional to T I and the reading, n, at
the end of T2 is proportional to T2, we have
(9.11 8)
9.9 AID CONVERTER CIRCUITS t;·~~ 931
c
S
t'A ~Sl R
+VREFO~
hi
bz
Control
Counter Output
logic
hN
Start/Stop 0 I
JUl...-
Clock
(a)
VI
variable} = ~
slope RC
VPEAK
o
Time
J
~
Phase I Phase II
Fixed interval (T I ) Variable interval (Tz )
(b)
J:1GtJRE 9.44 The dual-slope AID conversion method. Note that VA is assumed to be negative.
932 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS
Analog 0--_--0---3'"1 Bit I

input
Digital
Logic
output
BitN
FIGURE 9.45 Parallel, simultaneous, or fiash AID conversion.
Thus the content of the counter,S /1, at the end of the conversion process is the digital equiv-
alent of VA-
The dual-slope converter features high accuracy, since its performance is independenl of
the exact values of Rand e. There exist many commercial implementations of the dual-
slope method, some of which utilize CMOS technology.
9.9.3 The Parallel or Flash Converter

The fastest AID conversion scheme is the simultaneous, parallel, or flash conversion process
illustrated in Fig. 9.45. Conceptually, flash conversion is very simple. It utilizes 2 N - 1
N
comparators to compare the input signal level with each of the 2 - I possible quantization
levels. The outputs of the comparators are processed by an encoding-logic block to provide
the N bits of the output digital word. Note that a complete conversion can be obtained within
one clock cycle.
Although flash conversion is very fast, the price paid is a rather complex circuit imple-
mentation. Variations on the basic technique have been successfully employed in the design
of IC converters.
9.9.4 The Charge-Redistribution Converter

The last AID conversion technique that we shall discuss is particularly suited for CMOS
implementation. As shown in Fig. 9.46, the circuit utilizes a binary-weighted capacitor
array, a voltage comparator, and analog switches; control logic (not shown in Fig. 9.4fJ) is
also required. The circuit shown is for a 5-bit converter; capacitor CT serves the purpose
of terminating the capacitor array, making the total capacitance equal to the desired value
of2e.
Operation of the converter can be divided into three distinct phases, as illustrated in
Fig. 9.46. In the sample phase (Fig. 9.46a) switch Sa is closed, thus connecting the lOp plate
of all capacitors to ground and setting V() to zero. Meanwhile, switch SA is connected to the
analog input voltage Vi\' Thus the voltage Vii appears across the total capacitance of 2[,
resulting ina stored charge of 2Cv;\' Thus, during this phase, a sample of V" is taken and a
proportional amount of charge is stored on the capacitor array.
-:-----------------------------------
5 Note that is /lol a continuous function of
/l as might be inferred from Eq. (9.1 18). Rather. takes
V;\' /l
on discrete values corresponding to one of the 2N quantized levels of VI\'

Onver e C Er (J : 9.9.2 The Dual-Slope Converter

Uploaded by

Copyright:

Available Formats

Onver e C Er (J : 9.9.2 The Dual-Slope Converter

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Onver e C Er (J : 9.9.2 The Dual-Slope Converter

Uploaded by

Copyright:

Available Formats

930 ~ CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

9.9.2 The Dual-Slope AID Converter

At the end of this phase, the counter is reset to zero.

T2 :::= T] (~) (9.117)

Analog 0--_--0---3'"1 Bit I

FIGURE 9.45 Parallel, simultaneous, or fiash AID conversion.

9.9.3 The Parallel or Flash Converter

9.9.4 The Charge-Redistribution Converter

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.