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    Step-1: Open: ISE Design Suite Step-2: Create New Project From File Tab

    Uploaded by

    Buvanesh Kanth
    The document outlines steps for designing a project in ISE Design Suite, including opening a new project, selecting a device, creating Verilog modules and files, performing simulation and behavioral modeling, and implementing the design on an FPGA board through synthesis, planning I/O pins, generating programming files, and programming the device.

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    © All Rights Reserved
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    Step-1: Open: ISE Design Suite Step-2: Create New Project From File Tab

    Uploaded by

    Buvanesh Kanth
    36 views9 pages
    The document outlines steps for designing a project in ISE Design Suite, including opening a new project, selecting a device, creating Verilog modules and files, performing simulation and behavioral modeling, and implementing the design on an FPGA board through synthesis, planning I/O pins, generating programming files, and programming the device.

    Original Description:

    FPGA

    Original Title

    Lab-intro-1

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    The document outlines steps for designing a project in ISE Design Suite, including opening a new project, selecting a device, creating Verilog modules and files, performing simulation and behavioral modeling, and implementing the design on an FPGA board through synthesis, planning I/O pins, generating programming files, and programming the device.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    36 views9 pages

    Step-1: Open: ISE Design Suite Step-2: Create New Project From File Tab

    Uploaded by

    Buvanesh Kanth
    The document outlines steps for designing a project in ISE Design Suite, including opening a new project, selecting a device, creating Verilog modules and files, performing simulation and behavioral modeling, and implementing the design on an FPGA board through synthesis, planning I/O pins, generating programming files, and programming the device.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 9

    Step-1:

    ● Open: ISE Design Suite


    Step-2:
    ● Create new project from File tab

    Step-3:
    ● Select the device as (For simulation device selection is not required.)
    spartan-3 3s250E for BASYS2 kit: package CP132
    Data-sheet: https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

    Spartan-6 XC6SLX45 for ANVYL Kit:

    Data-sheet: https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

    ● Select the prefered language as Verilog


    Step-4:
    ● Create a source file from Project tab -> new Source..

    ● Select verilog module and file-name (module name)

    ● Input / output ports can be created in the next tab or in the code
    Simulation:
    Step-1:
    Select the simulation mode

    Step-2:
    ● Compilation: first select the .v file then expand
    the Isim simulator and press double click on the
    Behavioral Check Syntax

    Step-3:
    ● Press double click on the Simulate Behavioral Model

    Step-4:
    ● Create a input perton for each input: it could be force constant or force clock
    ● Give appropriate parameters in the required field based on the problem

    Implementation
    Step-1:
    Make sure you have selected the appropriate device and select the option for
    implementation instead simulation.
    Step-2: Compile the project:

    Step-3: double click on I/O pin plan -pre-synthesis


    That will launch a PlanAhead software

    Step-4: Plan the pin connections/assignment


    Step-5: Do synthesize again

    Step-6: Do Implement Design

    Step-7: Generate Program File

    Step-8: Do Configure Target Device


    Step-9: Do -> Boundary Scan

    Step-10: Do -> cable setup:

    Select Digilent USB JTAG Cable

    Step-11: Again right click choose and choose source file ----.bit file file name is module name.
    Step-12: Do programming the device:

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