Basic Logic Gates: Expt - No: Date

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Expt.

No: BASIC LOGIC GATES


Date :

AIM:

To write a Verilog HDL program for Basic Logic Gates and verify output using Xilinx ISE
13.2 version. To download the bit file in FPGA Kit and verify the output.

APPARATUS REQUIRED:
1.Xilinx Spartan-3 Trainer Kit(XC3S400-PQ208)
2.PC with Windows XP OS
3.Xilinx ISE 13.2

PROCEDURE:

1. Start the Xilinx Project Navigator by using the desktop shortcut or by using the
Start Programs Xilinx ISE (13.2).

2. Create a new project. In window go to FILE NEW PROJECT.


Specify the project name and location and say NEXT.

3. Select the family as Spartan 3, the device as XC3S400, package as PQ208 and
speed as -4.

4. Creating a verilog file. Click on the symbol of FPGA device and then right
Click Click on new source Verilog module and give the file
name and say next.

5. Define ports. i1 and i2 are the input ports defined as in .out is output port defined as out.
After this say next twice and then finish.

6. Write the verilog code in verilog editor.

7. Check syntax. Run the Check syntax Process window Synthesize


check syntax, and remove errors if present.

8. Creating a test bench file. Click the symbol of FPGA device and then right click
Click on new source Test Bench Waveform and give the name Select
Entity Finish.

9. Select the desired parameters for simulating your design. In this case combinational
Circuit and simulation time.
10. Simulate the code. Click on test bench file. Test bench file will open in main window. Assign
all the signals and save file. From the source of process window .Click on simulate
Behavioral model in process window.

11. Verify your design in wave window by seeing Behaviour of output signal with respect to
input signal. Close ISE simulator window.

12. Synthesize the design using XST. For synthesizing your design, from the source window
select, synthesis/Implementation from the drop-down menu. Highlight file in the sources in
Project window. To run synthesis, right click on synthesize, and the run option or double-
click on synthesize in the processes for current source window.

13. Check the synthesis report. If there are any error correct it and rerun synthesis.

14. Create constraints file(UCF). Click on the symbol of FPGA device and then right
Click Click on new source Implementation Constraints file and give the
Name Select entity Finish .Click on user constraint and in that double
click on assign package pins option in process window. Xilinx PACE window opens. Enter
all the pins assignments in PACE, depending upon target device and number of inputs and
outputs used in your design.

15. Implementing a design,once synthesis is complete,use the Xilinx constraints editor to add
timing and location constraints for the implementation of your design.This procedure runs
you through the basic flow for implementation.

16. Generating programming file. Right click on generate programming file ,choose the run
option,or double left click on generate programming file.This will generate the bit stream.

17. Downloading in boundary scan mode and Verify the output.

Note:
Xilinx provides 2-tools for downloading purpose
IMPACT-is a command line and GUI based tool
PROM file formatter

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