International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 14: Adding ILA and VIO Cores for Remote Monitoring
and Control

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L) Page 73

 Adding ILA and VIO Cores for Remote Monitoring
and Control
1. Objective
This lab exercise is designed to understand the ILA and VIO core with Chipscope and
implement it on FPGA on Spartan 3E or Spartan 2 kit.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 2 or Spartan 3E board

3. Introduction
This lab comprises four primary steps: You will configure the design by using the ChipScope Pro
analyzer tool; use the Core Generator to add ILA and VIO cores to the design; modify the clock
design in order to add the cores; and, finally, configure and control the design.

Note: You can download the lab files for this module from the Xilinx FTP site at
ftp://ftp.xilinx.com/pub/documentation/education/chipscope-9-rev1-print.zip.

Before beginning, verify that your software is properly installed.

• ChipScope Pro software: Select Start → Programs → ChipScope Pro 9.2i → ChipScope
Pro Analyzer. Select Help → About to verify version 9.2i
• Project Navigator in the ISE software: Select Start → Programs → Xilinx ISE 9.2i →
Project Navigator. Select Help → About to verify version 9.2i

Verify that the hardware is set up properly by checking the following settings.
• Digilentinc parallel configuration cable is connected to the parallel port of your machine and
the J7 JTAG connection on the Spartan-3 FPGA starter board.
• Board is powered and turned on.

Configuring the Design Step 1

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4:

Configurin Adding Modifying Configurin
g the Cores the Clock g/
Design Design Controlling
the Design

This is a simple clock design that is now working properly. The design uses one of the available
pushbuttons to reset the clock to zero. In addition to using the
7-segment display, the design uses eight LEDs to reflect activity. The board is slated for
environmental testing to confirm the proper operation of the FPGA in various environments.

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 To facilitate the testing, you will add an ILA and VIO core to this design to allow remote control
and monitoring of the design and board.

Open the design (clock_part2.ise) located in the C:\training\chipscope_pro\labs\vhdl\lab2

(VHDL users) or C:\training\chipscope_pro\labs\verilog\lab2 (Verilog users) folder.

 Select Start → Programs → Xilinx ISE → Project Navigator to open the Project
Navigator in the ISE software

 From the Project Navigator, select File → Open Project

 Verilog users: Browse to C:\training\chipscope_pro\labs\verilog\lab2

 Select clock_ part2.ise and click Open

Download the bitstream to the device and verify its functionality.

 In the Sources window, select clock_part2.vhd\.v

 In the Processes window, double-click Generate Programming File

 In the Processes window, double-click Analyze Design Using ChipScope

 Select JTAG Chain → Xilinx Parallel Cable

 In the dialog box that opens, select Auto Detect Cable Type, leave the other settings at their
default values, and click OK

A new dialog box opens, confirming the JTAG devices for the Spartan-3 FPGA starter board.

 Click OK. Right-click the XC3S200 device in the New Project pane and select Configure

 Click Select New File from the dialog box that opens

 VHDL users: Browse to C:\training\chipscope_pro\labs\vhdl\lab2

 Verilog users: Browse to C:\training\chipscope_pro\labs\verilog\lab2

 Select clock_part2.bit and click Open. Click OK

Observe the configuration status bar in the lower-right corner of the ChipScope Pro analyzer
display. Close the ChipScope Pro analyzer window

Observe the correct operation of the timer design on the Spartan-3 FPGA starter board

 Exit the ChipScope Pro software. Do not save any changes

Digital System Design Lab (EE-319L) Page 75

Adding Cores Step 2

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4:

Configurin Adding Modifying Configurin
g the Cores the Clock g/
Design Design Controlling
the Design

You can use an ILA core to monitor signals within the design and a VIO core to control
the reset and show board activity.

To accomplish this, use the ICON, ILA, and VIO cores. The ILA and VIO cores require
the following parameters.

ILA core:

o Define one trigger port with nine inputs: eight for LEDs and one for reset

VIO core:

o Define eight inputs for LEDs and one input to monitor reset
o Define two outputs: one as a reset and the other as a VIO console/board select,
allowing you to control the board from either the VIO console or the board

Using the Core Generator, generate an ICON core to use in this design.

 Select Start → Programs → ChipScope Pro 9.2i → ChipScope Pro Core Generator

 Select ICON (Integrated Controller) and click Next

 In the Design Files Output Netlist dialog box:

 Verilog users: Browse to C:\training\chipscope_pro\labs\verilogl\lab2\CS

 Click Save

 Select Spartan3 for the device family

 In the ICON Parameters dialog box, define the number of control ports as 2. Leave the rest of the
options at their default. Click Next

 In the Example and Template Options dialog box, set the following:

 Generate HDL Example File: Checked

 HDL Language

Digital System Design Lab (EE-319L) Page 76

  Verilog users: Verilog

 Synthesis Tool: Xilinx XST

 Generate Batch Mode Argument Example File: Checked

 Click Generate Core

Using the Core Generator, generate an ILA core to use in this design.

 After the ICON core has been generated, click Start Over

 Select ILA (Integrated Logic Analyzer) and click Next

Notice that the Output Netlist location is already defined, as is the device type.

 Select Sample on Rising Edge of Clock and click Next

 For the Trigger Port Options, set the following:

 Number of Input Trigger Ports: 1

 Trigger Width: 9

 Leave the rest of the options at their default

 Click Next

 Select 1024 as the sample data depth and select Data Same as Trigger. Click Next

 In the Example and Template Options dialog box, set the following:

 Generate HDL Example File: Checked

 HDL Language

 Synthesis Tool: Xilinx XST

 Generate Bus/Signal Name Example File (.cdc): Checked

 Generate Batch Mode Argument Example File: Checked

 Click Generate Core

Using the Core Generator, generate a VIO core to use in this design.
 After the ILA core has been generated, click Start Over

 Select VIO (Virtual Input/Output Core) and click Next

 Confirm that the Output Netlist location and device family are correct

 Select Enable Synchronous Input Port (do not use Asynchronous) and define a width of 9 bits

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  Select Enable Synchronous Output Port (do not use Asynchronous) and define a width of 2 bits

 Click Next

 In the Example and Template Options dialog box, set the following:

 Generate HDL Example File: Checked

 HDL Language

 Verilog users: Verilog

 Synthesis Tool: Xilinx XST

 Generate Batch Mode Argument Example File: Checked

 Click Generate Core

 Close the ChipScope Pro Core Generator dialog box

Modifying the Clock Design (Verilog)

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4:

Configurin Adding Modifying Configurin
g the Cores the Clock g/
Design Design Controlling
the Design

Verilog users: Copy the ICON, ILA, and VIO modules into clock_part2.v.

 From the Project Navigator in the ISE software, double-click clock_part2.v in the Sources window

 In the Project Navigator, select File → Open. Browse to

C:\training\chipscope_pro\labs\verilog\lab2\CS

 Select All Files from the Files of Type drop-down list

 Select icon_xst_example.v and click Open

 Scroll to the bottom of the file. Copy the ICON core module declaration to the clipboard

 Select the clock_part2.v file already opened. Above the clock_part2 module, paste the ICON core
module declaration into this file

Look for the comment “Paste ChipScope Pro Core Modules here”

 Repeat detailed steps 2 through 6 for the ILA and VIO cores

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  ILA Verilog filename: ila_xst_example.v

 VIO Verilog filename: vio_xst_example.v

 Save clock_part2.v

Copy the ICON, ILA, and VIO wire declarations and core instances into clock_part2.v.
Modify the clock design in order to add the ChipScope Pro software cores that you have
defined using the Core Generator. Perform the appropriate signal associations.

 Select the icon_xst_example.v file. Copy the ICON core wire declarations and ICON core instance

 Select the clock_part2.v file. Scroll down to the comment “Paste ChipScope Pro Core Instances here”

 Paste the ICON core wire declarations and ICON core instance here

 Repeat detailed steps 1 through 3 for the ILA and VIO core wire declarations and core instances

 In clock_part2.v, for the ILA and VIO core wire declarations sections, delete the control and clk wire
declarations because they have already been defined as part of the ICON core

 In the port map for the ILA core instance, tie the control port to control0 and tie the clk port to clk50

 In the port map for the VIO core instance, tie the control port to control1 and tie the clk port to clk50

Add the appropriate connections to and from the ILA and VIO cores. Generate the
programming file.

 In the clock_part2.v file, directly below the last core instance, un-comment the following lines of code

assign trig0[7:0] = led;

assign trig0[8] = rst;
assign sync_in[7:0] = led;
assign sync_in[8] = rst;

These were the signals that you had defined for the trigger inputs and VIO inputs and outputs above.

 Comment out the following line

assign rst = pb[0];

 Un-comment the following line

assign rst = sync_out[0] ? pb[0] : sync_out[1];

 Save clock_part2.v

 Select clock_part2.v in the Sources window. In the Processes window, expand Implement Design,
right-click Translate, and select Properties

 In the Macro Search Path Options, click the button, browse to

C:\training\chipscope_pro\labs\verilog\lab2\CS, and click OK

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  Click OK in the Translate Properties dialog box

 In the Processes window, double-click Generate Programming File

Configuring and Controlling the Design Step 4

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4:

Configurin Adding Modifying Configurin
g the Cores the Clock g/
Design Design Controlling
the Design

Configure the FPGA.

 Double-click Analyze Design Using ChipScope in the Processes window

 Select JTAG Chain → Xilinx Parallel Cable

 In the dialog box that opens, click OK

A new dialog box opens, confirming the JTAG devices for the Spartan-3 FPGA starter board.

 Click OK

 Right-click the XC3S200 device in the New Project pane and select Configure

 Click Select New File from the dialog box that opens

 VHDL users: Browse to C:\training\chipscope_pro\labs\vhdl\lab2

 Verilog users: Browse to C:\training\chipscope_pro\labs\verilog\lab2

 Select clock_part2.bit and click Open. Click OK

After successful configuration, observe normal operation of the clock LEDs and 7-segment display on
the board.

Observe that the ChipScope Pro analyzer has found two cores, Unit0: (ILA) and Unit1: (VIO), and that
the waveform display is populated with the defined trigger inputs.

 Click the Run button and capture data within the waveform display

DataPort[0-7] represent LED0 through LED7 on the Spartan-3 FPGA board. Because you are
capturing the LED signals, there is a minimal amount of activity on a few channels, reflecting the state
at the time of capture.

Set up the VIO Console with LEDs for the output signals and buttons for the inputs.

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  In the New Project pane (upper-left corner), click DEV, click UNIT:1 MyVIO1 (VIO), and double-
click VIO Console

Notice the arrows within the value field associated with the blue input signals—these are the LEDs that
are operating.

Also observe that the green signals represent outputs and the blue signals represent inputs. Familiarize
yourself with the different controls available in the horizontal toolbar, such as Sampling Period

 In the VIO Console window, right-click SyncIn[0] and select Type → LED → RED → High

Notice that the value now displays a red LED.

 Right-click SyncIn[0] and select Rename. Enter LED[0] and click OK

 Repeat detailed steps 2 and 3 for SyncIn[1-8]

 Observe that SyncIn[8] is tied to reset. Rename it to RST

 Right-click SyncOut[0] and select Rename. Enter VIO\BoardSelect and click OK

 Right-click VIO\BoardSelect and select Type → Toggle Button

 Right-click SyncOut[1] and select Rename. Enter VIO\RST and click OK

 Right-click VIO\RST and select Type → Pushbutton → High

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