Cs6211 / It6211 Digital Lab Manual (Common For II Semester CSE/IT)

ANJALAI AMMAL - MAHALINGAM ENGINEERING COLLEGE
KOVILVENNI - 614 403.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.,
CS6211 / IT6211 DIGITAL LAB MANUAL

(Common For II Semester CSE/IT)
SYLLABUS -LIST OF EXPERIMENTS
1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
• 4 – bit binary adder / subtractor
• Parity generator / checker
• Magnitude Comparator
• Application using multiplexers
4. Design and implementation of sequential circuits:
• Shift–registers
• Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).
1
LIST OF CYCLE - I EXPERIMENTS:
1. Study of Logic Gates.

2. Verify Boolean Theorems using basic logic gates (using AOI gates.)
3. Design and implementation of Adder/Subtractor.
4. Design and implementation of code converters.
5. Design and implementation 4-bit parallel Adder and Subtractor.
6. Design and implementation of Parity generator / Checker.
7. Design and implementation of Magnitude comparator.
8. Design and implementation of Multiplexer & Demultiplexer using logic gates and study of
IC 74150 & IC 74154.
LIST OF CYCLE - II EXPERIMENTS:
9. Design implementation of Encoder and Decoder.

10. Design implementation of Shift registers.
11. Design implementation of Counters.
12. Verilog code to realize all logic gates.
13. Verilog code to realize Combinational circuits.
14. Verilog code to realize Flip-Flops.
15. Verilog code to SIPO Shift registers.
16. Verilog code to binary up Counter.
2
EXPT NO: 1 STUDY OF LOGIC GATES
DATE:
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
S. No. Component Specification Quantity
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE IC 7400 1
5. NOR GATE IC 7402 1
6. EX-OR GATE IC 7486 1
7. IC TRAINER KIT - 1
8. PATCH CORD - As required
THEORY:
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low when any one of the inputs is
low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low when both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.
3
AND Gate:
OR Gate:
NOT Gate:
4
NAND Gate:
NOR Gate:
EX-OR Gate:
5
PROCEDURE:
 Connections are given as per the circuit diagram.

 For the entire ICs 7th Pin is grounded and 14th Pin is given to +5V supply (VCC).
 Apply the inputs and verify the truth table for all gates.
RESULT:
Thus the truth tables of all the logic gates are verified.
EXPT NO : 2 VERIFICATION OF BOOLEAN THEOREMS USING BASIC GATES

DATE:
AIM:
To verify Boolean theorems using AOI (AND/OR/INVERTER) logic gates.
 Commutative law / Associative law / Distributive law /Absorption law
 Idempotent law /De Margon’s Theorem
 Involution law / Complementary law
APPARATUS REQUIRED:
4. IC TRAINER KIT 1
THEORY:
1.Commutative Law
The binary operator OR, AND is said to be commutative if,
i.
ii.
1.
2. Associative Law
The binary operator OR, AND is said to be associative if,
i.
ii.
3.Distributive Law
The binary operator OR, AND is said to be distributive if,
i.
ii.
4.Absorption Law
i.
ii.
5.Idempotent Law
i.
ii.
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6.Involution
̿
7.De Morgan’s Theorem

 The complement of the sum is equal to the sum of the product of the individual
complements.
i. ̅̅̅̅̅̅̅̅ ̅ ̅
 The complement of the product is equal to the sum of the individual complements.
ii. ̅̅̅̅̅ ̅ ̅
8.Complementary Law
i. ̅
ii. ̅
DESIGN:
1. Commutative Law
i.
Truth Table:
ii.
Truth Table:
2.
7
2. Associative Law
i.
Truth Table:
ii.
Truth Table:
8
3. Distributive Law
i.
Truth Table:
ii.
Truth Table:
9
4. Absorption Law
i.
ii.
5. Idempotent Law
i.
ii.
6. Involution
̿
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7. De Morgan’s Theorem
i. ̅̅̅̅̅̅̅̅ ̅ ̅
ii. ̅̅̅̅̅ ̅ ̅
8. Complementary Law
i. ̅
ii. ̅
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PROCEDURE:
 Apply the inputs and verify the truth table for all Boolean theorems.
RESULT:
Thus the above stated Boolean laws are verified.
EXPT NO : 3 DESIGN AND IMPLEMENTATION OF ADDER/ SUBTRACTOR

DATE:
AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits
and verify the truth table using logic gates.
APPARATUS REQUIRED:
1. X-OR GATE IC 7486 1
5. IC TRAINER KIT 1
THEORY:
ADDER:
The most basic operation is the addition of two binary digits. This simple addition
consists of four possible elementary operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 102
The first three operations produce a sum whose length is one digit, but when the last
operation is performed sum is two digits. The higher significant bit of this result is called a carry,
and lower significant bit is called sum.
Half Adder:
A combinational circuit which performs the addition of two bits is called half adder. The
input variables designate the augend and addednd bit, whereas the output variables produce the
sum and carry bits.
Full Adder:
A combinational circuit which performs the arithmetic sum of three bits is called
fulladder. Three bits include two significant bits and a previous carry bit. A full adder circuit can
be implemented with two half adders and one OR gate.
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SUBTRACTOR:
The subtraction consists of four possible elementary operations ,namely,
0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of
second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. Just
as there are half and full-adders, there are half and full-subtractors.
Half Subtractor:
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and subtrahend bit, whereas the output
variables produce the difference and borrow bits.
Full Subtractor:
A combinational circuit which performs the subtraction of three bits is called full
subtractor . Three bits include two significant bits and a previous borrow bit. A full adder circuit
can be implemented with two half subtractors and one OR gate.
CIRCUIT DESIGN:
Half Adder:
Full Adder:
13
Half Subtractor:
14
Full Subtractor:
PROCEDURE:
 Apply the inputs and verify the truth table for adder and subtractor.
RESULT:
Thus the truth table for half adder, full adder, half subtractor and full subtractor are
verified.
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EXPT NO : 4 DESIGN AND IMPLEMENTATION OF CODE CONVERTERS
DATE:
AIM:
To design and implement 4-bit
i. Binary to gray code converter and Vice versa
ii. BCD to excess-3 code converter and Vice versa
APPARATUS REQUIRED:
5. 3- i/p AND GATE IC 7411 1
THEORY:
The availability of large different types of codes for the same discrete elements of
information results in the use of different codes by different digital systems. Sometimes, it may
happen that the use of output of one number system as the input to another number system.
Hence it is necessary to design a conversion circuit and insert it between the two systems. Thus
a code converter is a circuit, which accepts the input information in one binary code, converts it
and produces an output into another binary code i.e., which makes the two systems compatible,
even though each uses a different binary code. To convert from binary code x to binary code y,
the input lines must supply the bit of combination of elements as specified by code x and the
output lines must generate the corresponding bit combination of code y. A combinational circuit
performs this transformation by means of logic gates. There are a wide variety of binary codes
used in digital systems. Some of these codes are BCD, EX-3, gray and so on.
Binary to GrayConverter:
Binary to Gray:
The MSB of the binary code alone remains unchanged in the gray code. The remaining
bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in
the binary code. The gray code is often used in digital systems because it has the advantage that
only one bit in the numerical representation changes between successive numbers.
Gray to Binary:
The MSB of the gray code alone remains unchanged in the binary code. The remaining
bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous output
binary bit.
BCD to Excess – 3 Converter:

Excess-3 code is a modified form of a BCD number. The Excess -3 code can be derived
from the natural BCD code by adding 3 to each coded number.
16
Binary to Gray:
Circuit Diagram:
Truth Table:
K Map:
17
Gray to Binary:
Circuit Diagram:
Truth Table:
18
K Map:
19
BCD to Excess -3:
Circuit Diagram:
Truth Table:
20
K Map:
Excess -3 to BCD:
Circuit Diagram:
21
Truth Table:
K Map:
PROCEDURE:
 Apply the inputs and verify the observed logic output with the truth table given.
RESULT:
Thus the code converter using logic gates are designed and its performance is verified by
its truth table.
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EXPT NO : 5 DESIGN AND IMPLEMENTATION OF 4 BIT PARALLEL ADDER /
DATE: SUBTRACTOR
AIM:
To design and implement the 4-bit adder/subtractor using IC 7483.
APPARATUS REQUIRED:
2. 4- BIT BINARY PARALLEL ADDER IC 7483 1
THEORY:
4-Bit binary adder/ subtractor:
The 4-bit binary adder/ subtractor circuit performs the operation of both addition and
subtraction. It has two 4-bit inputs A0, A1, A2, A3 and B0, B1, B2, B3. The mode input controls the
operation of the circuit. When , the circuit is an adder and when , the circuit
becomes a subtractor. Each exclusive-OR gate receives input M and one of the inputs of B.
When , the operation is . The full adders receive the value of B and the
input carry is 0, and the circuit performs the addition operation, When , the
operation is ̅ and . The B inputs are all complemented and a is added through
the input carry. Thus the circuit performs the subtraction operation,
i.e.,
IC 7483 4- BIT BINARY PARALLEL ADDER
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Circuit Diagram:
Verification Table:
Input data A Input data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
PROCEDURE:
 For IC 7483, 5th Pin is given to +5V supply (VCC) and 12th Pin is grounded.
RESULT:
Thus the 4-bit adder/subtractor using IC 7483 is designed and its performance is verified
by its truth table.
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EXPT NO : 6 DESIGN AND IMPLEMENTATION OF PARITY GENERATOR/CHECKER
DATE:
AIM:
To design and implement
i. 3–bit parity odd/ even generator /checker using logic gates.
ii. 16 –bit parity odd/ even generator /checker using IC 74180.
APPARATUS REQUIRED:
3. PARITY GENERATOR /CHECKER IC 74180 2
THEORY:
3–bit odd/ even parity generator /checker:
A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the number of
1’s either odd or even. The message including the parity bit is transmitted and then checked at
the receiving end for errors.An error is detected if the checked parity does not correspond with
the one transmitted.
The circuit that generates the parity bit in the transmitter is called a parity generator and
the circuit that checks the parity in the receiver is called a parity checker.In even parity the
added parity bit will make the total number of 1’s an even amount and in odd parity the added
parity bit will make the total number of 1’s an odd amount. In a three bit odd parity generator
the three bits in the message together with the parity bit are transmitted to their destination,
where they are applied to the parity checker circuit. The parity checker circuit checks for
possible errors in the transmission.
Since the information was transmitted with odd parity (or even parity) the four bits
received must have an odd number (or even number) of 1’s. An error occurs during the
transmission if the four bits received have an even number (or odd number) of 1’s, indicating
that one bit has changed during transmission. The output of the parity checker is denoted by
PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received
has an even number (or odd number)of 1’s.
16–bit odd/ even parity generator /checker:

The IC 74180 is a 9-bit parity generator or checker commonly used to detect errors in
high speed data transmission or data retrieval systems. Both even and odd parity enable inputs
and parity outputs are available for generating or checking parity on 8-bits.
As shown in the function table, true active-HIGH or true active-LOW parity can be
generated at both the Even or Odd outputs. True active-HIGH parity is established with Even
parity enable input (PE) set HIGH and the Odd parity enable input (PO) set LOW. True active LOW
25
parity is established when PE is LOW and PO is HIGH. When both are enable inputs are at the
same logic level, both outputs will be forced to the opposite logic level.
Expansion to larger word sizes is accomplished by serially cascading the 74180 in 8-bit
increments. The Even and Odd parity outputs of the first stages are connected to the
corresponding PE and PO inputs, respectively, of the succeeding stage, as shown in the Fig.
3-BIT ODD/EVEN PARITY GENERATOR/ CHECKER:

PARITY GENERAOTOR:
Truth Table
PARITY CHECKER:
26
Truth Table:
16-BIT ODD/EVEN PARITY GENERATOR/ CHECKER:

27
Pin Diagram: Function Table:
PARITY GENERATOR:
Verification Table:
Active ⅀E ⅀O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
PARITY CHECKER:
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Verification Table:
Active ⅀E ⅀O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
PROCEDURE:
 For the entire ICs including IC 74180, 7th Pin is grounded and 14th Pin is given to +5V
supply (VCC).
RESULT:
Thus the 3–bit /16 –bit parity odd/even generator/checker using logic gates are designed
and its performance is verified by its truth table.
EXPT NO : 7 DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

DATE:
AIM:
i. 2–bit magnitude comparator using basic gates.
ii. 8 –bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
5. NOR GATE IC 7402 1
6. 4-BIT MAGNITUDE COMPARATOR IC 7485 2
7. IC TRAINER KIT 1
THEORY:
The comparison of two numbers is an operation that determines if one number isgreater
than, less than, or equal to the other number. A magnitude comparator is a combinational circuit
that compares the two numbers, A and B, and determines their relative magnitude. The circuit
for comparing two bit numbers has entries in the truth table and becomes too
cumbersome even with . On the other hand comparator circuits possess a certain amount
of regularity.
Equality : Consider two numbers, A and B, with four digits each .

The two numbers are equal if all pairs of significant digits are equal: , ,
29
and . When the numbers are binary, the digits are either 0 or 1, and the equality relation
of each pair of bits can be expressed logically with an EX-NOR function,
̅ ̅ for
if and are equal.
So the quality condition of A and B can be implemented using the AND operation as ;
The binary variable is 1 only if all pairs of digits of the two numbers are equal.
Inequality: In order to manually determine the greater of two binary numbers, we inspect the
relative magnitudes of pairs of significant digits, starting from the most significant bit, gradually
proceeding towards lower significant bits until an inequality is found. When an inequality is
found, if the corresponding bit of is and that of is then we conclude that .
This sequential comparison can be expressed logically as:
̅ ̅ ̅ ̅
̅ ̅ ̅ ̅
and are output binary variables, which are equal to 1 when or
respectively.
2–BIT MAGNITUDE COMPARATOR:

Circuit Diagram:
30
Truth Table:
K-Map:
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ ̅ ̅ ̅ ̅
̅ ̅
̅ ̅ ̅ ̅
̅ ̅
̅ ̅ ̅ ̅
(̅̅̅̅̅̅̅̅̅̅̅) ̅̅̅̅̅̅̅̅̅̅̅
31
8–BIT MAGNITUDE COMPARATOR:
Pin Diagram IC 7485:
Logic Diagram:
Verification Table:
PROCEDURE:
 For the entire ICs, 7th Pin is grounded and 14th Pin is given to +5V supply (VCC) , except for
IC 7485 , 16th Pin is grounded and 8th Pin is given to +5V supply (VCC).
RESULT:
Thus the 2–bit and 8 –bit magnitude comparator are designed and its performance is
verified by its truth table.
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EXPT NO : 8 DESIGN AND IMPLEMENTION OF MULTIPLEXER & DEMULTIPLEXER
DATE: USING LOGIC GATES AND STUDY OF IC 74150 & IC 74154.
AIM:
To design and implement multiplexer and demultiplexer using logic gates and to study IC
74150 and IC 74154.
APPARATUS REQUIRED:
1. 3 i/p AND GATE IC 7411 2
5. 16:1 MULTIPLEXER IC IC 74150 1
6. 1:16 DEMULTIPLEXER IC IC 74154 1
THEORY:
MULTIPLEXER:
A multiplexer (MUX) is a device that allows digital information from several sources to be
routed onto a single output line. The basic multiplexer has several data-input lines and a single
output line. The selection of a particular input line is controlled by a set of selection lines.
Normally, there are input lines and selection lines whose bit combinations determine which
input is selected. Therefore, multiplexer is 'many into one' and it provides the digital equivalent
of an analog selector switch.Multiplexers are also known as data selectors.
DEMULTIPLEXER:
A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of possible output lines. The selection of specific output line is controlled
by the values of selection lines. The function of demultiplexer is in contrast to multiplexer
function. It takes information from one line and distributes it to a given number of output lines.
For this reason, the demultiplexer is also known as a data distributor.
MULTIPLEXER:
Circuit Diagram: Truth Table:
Select Lines Output
0 0
0 1
1 0
1 1
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DEMULTIPLEXER:

Select Output
Lines
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
MULTIPLEXER:
Pin Diagram: Truth Table:

Select Lines Enable Output
̅
x x x x 1 1
0 0 0 0 0 ̅
0 0 0 1 0 ̅
0 0 1 0 0 ̅
0 0 1 1 0 ̅
0 1 0 0 0 ̅
0 1 0 1 0 ̅
0 1 1 0 0 ̅
0 1 1 1 0 ̅
1 0 0 0 0 ̅
1 0 0 1 0 ̅
1 0 1 0 0 ̅
1 0 1 1 0 ̅
1 1 0 0 0 ̅
1 1 0 1 0 ̅
1 1 1 0 0 ̅
1 1 1 1 0 ̅
34
DEMULTIPLEXER:
Pin Diagram: Logic Diagram:
Truth Table:
Select Lines Input Output
̅̅̅̅̅̅̅
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
x x x x 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x x x x 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PROCEDURE:
 For the entire ICs, 7th Pin is grounded and 14th Pin is given to +5V supply (VCC).
35
RESULT:
Thus the multiplexer and demultiplexer are designed using logic gates and its
performance is verified by its truth table and also IC 74150& IC 74154 are studied.
EXPT NO : 9 DESIGN AND IMPLEMENTION OF ENCODER AND DECODER

DATE:
AIM:
To design and implement encoder and decoder using logic gates.
APPARATUS REQUIRED:
4. IC TRAINER KIT 1
THEORY:
ENCODER:
An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has (or fewer) input lines and output lines. In encoder the output lines generate
the binary codecorresponding to the input value.
DECODER:
A decoder is a combinational logic circuit that converts binary information from input
lines to a maximum of unique outputs. A binary decoder is used when it is necessary to
activate exactly one of outputs based on an -bit input value. In decoder, 2 inputs are
decoded into four outputs, each output representing one of the minterms of the 2 input
variables. The two inverters provide the complement of the inputs, and each one of four AND
gates generate one of the minterms.
ENCODER:

Inputs Outputs
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Expressions:
36
DECODER:

Inputs Outputs
EN
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
PROCEDURE:
 For the entire ICs, 7th Pin is grounded and 14th Pin is given to +5V supply (VCC).
RESULT:
Thus the encoder and decoder are designed using logic gates and its performance is
verified by its truth table.
EXPT NO : 10 DESIGN AND IMPLEMENTION OF SHIFT REGISTERS

DATE:
AIM:
i. Serial in serial out shift register
ii. Serial in parallel out shift register
iii. Parallel in serial out shift register
iv. Parallel in parallel out shift register
APPARATUS REQUIRED:
1. D FLIP FLOP IC 7474 2
37
THEORY:
A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to right.Shift
registers are classified into four types,
1. Serial-in Serial-out (SISO)
2. Serial-in Parallel-out (SIPO)
3. Parallel-in Serial-out (PISO)
4. Parallel-in Parallel-out (PIPO)
Serial-in Serial-out (SISO):

This type of shift registers accepts data serially, i.e., one bit at a time on a single input line.
It produces the stored information on its single output and the output also in serial form. Data
may be shifted left (from low to high order bits) using shift-left register or shifted right (from
high to low order bits) using shift-right register.
Serial-in Parallel-out (SIPO):
It consists of one serial input, and outputs are taken from all the flip-flop simultaneously
in parallel. In this register, data is shifted in serially but shifted out in parallel. In order to shift
the data out in parallel, it is necessary to have all the data available at the outputs at the same
time. Once the data is stored, each bit appears on its respective output line and all the bits are
available simultaneously, rather than on a bit by bit basis as with the serial output.
Parallel-in Serial-out (PISO):
This type of shift register accepts data parallel, i.e., the bits are entered simultaneously
into their respective flip-flopsrather than a bit-by-bit basis on one line.
Parallel-in Parallel-out (PIPO):
In this type of register, data inputs can be shifted either in or out of the register in
parallel.
IC 7474 D FLIP FLOP:
CIRCUIT DIAGRAM:
38
Serial-in Serial-out (SISO):
Truth Table:
Clock Input
Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 x 0
6 x 0
7 x 1
Serial-in Parallel-out (SIPO):
Truth Table:
Clock Input
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 1 0 0 1
5 x 1 0 0
6 x x 1 0
7 x x x 1
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Parallel-in Serial-out (PISO):
Truth Table:
Clock Input
1 1 0 0 1 1
2 0 0 0 0 0
3 0 0 0 0 0
4 0 0 0 0 1
Parallel-in Parallel-out (PIPO):
Truth Table:
Clock Input
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
40
PROCEDURE:
 For IC 7474 ( ), 7th Pin is grounded and 14th Pin is given to +5V supply (VCC).
RESULT:
Thus the shift registers using D flip-flop are implemented and studied their operation in 4
different modes.
EXPT NO : 11 DESIGN AND IMPLEMENTATION OF COUNTERS

DATE:
AIM:
1. Asynchronous/ripple 4-bit binary up and down counter
2. Mod‐10 counter
3. Synchronous/parallel 4-bit binary up counter
4. 3-bit synchronous up/down counter
APPARATUS REQUIRED:
1. JK FLIP FLOP IC 7476 2
5. XOR GATE IC 7486 1
7. IC TRAINER KIT 1
THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived.
Asynchronous Counter:
An asynchronous counter, each flip-flop is triggered by the output from the previous flip-
flop which limits its speed of operation. The settling time in asynchronous counters, is the
cumulative sum of the individual settling times of flip-flops. It is also called a serial counter.
The asynchronous counter is the simplest in terms of logical operations, and is therefore
the easiest to design. In this counter, all the flip-flops are not under the control of a single clock.
Here, the clock pulse is applied to the first flip-flop, i.e. the least significant bit stage of the
counter, and the successive flip-flop is triggered by the output is constructed using clocked JK
flip-flops.
Synchronous Counter:
A Synchronous counter is also called parallel counter. In this counter the clock inputs of
all the flip-flops are connected together so that the input clock signal is applied simultaneously
41
to each flip-flop, i.e., clock signal is connected in parallel to clock inputs of all the flip-flops. But
the output of first stage is used to drive the J and K inputs of the second stage.
IC 7476 JK FLIP FLOP:
4-BIT BINARY (RIPPLE) UP COUNTER:

Verification Table
Circuit Diagram:
42
4-BIT BINARY (RIPPLE) DOWN COUNTER:
Verification Table:
Circuit Diagram:
MOD-10 COUNTER:
Verification Table:
Clock
Q3 Q2 Q1 Q0
Pulse
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 0 1
43
Circuit Diagram:
Waveform for MOD-10:
4-BIT SYNCHRONOUS UP COUNTER:

Circuit Diagram:
44
3-BIT SYNCHRONOUS BINARY UP/DOWN COUNTER:
Circuit Diagram:
Verification Table:
Clock
Up Down
Pulse
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
PROCEDURE:
 For IC 7476 (JK ), 13th Pin is grounded and 5th Pin is given to +5V supply (VCC).
RESULT:
Thus the 4-bit binary (Asynchronous) up and down counter , Mod‐10 and 3-bit
synchronous up/down counter using JK flip-flop are implemented and its output is verified.
45
EXPT NO : 12 VERILOG CODE TO REALIZE ALL LOGIC GATES
DATE:
AIM:
To write a program to realize all logic gates using Verilog and obtain its RTL schematic
and necessary simulation waveforms.
APPARATUS REQUIRED:
PC with Xilinx- ISE 9.2 i software.
VERILOG CODE TO REALIZE ALL LOGIC GATES:

//////// Data flow modeling
RTL SCHEMATIC:
module All_Gates(a,b,c);
input a,b;
output [6:0] c;
assign c[0]=a&b;
assign c[1]=a|b;
assign c[2]=~a;
assign c[3]=~(a&b);
assign c[4]=~(a|b);
assign c[5]=a^b;
assign c[6]=~(a^b);
endmodule
BLACK BOX:
TEST BENCH WAVEFORM:
RESULT
Thus the program for all logic gates using Verilog is developed and checked its RTL
schematic with its simulation waveforms.
46
EXPT NO : 13 VERILOG CODE TO REALIZE COMBINATIONAL CIRCUITS
DATE:
AIM:
To write a program to realize the following combinational circuits using Verilog and
obtain its RTL schematic with necessary simulation waveforms.
 Half adder / Full Adder
 Half Subtractor / Full Subtractor
 Multiplexer / Demultiplexer
 Encoder / Decoder
APPARATUS REQUIRED:
VERILOG CODE TO REALIZE HALF ADDER:
VERILOG CODE: BLACK BOX:

module Half_Adder(a, b, sum, carry);

input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
RTL SCHEMATIC
47
VERILOG CODE TO REALIZE FULL ADDER:
VERILOG CODE: DESIGN:

//////// Structural modeling
module Full_Adder(a, b ,c_in, sum, c_out);

input a, b, c_in;
output sum, c_out;
wire e, f, g;
xor x1 (sum,a,b,c_in);
and x2 (e,a,b);
and x3 (f,b,c_in);
and x4 (g,a,c_in);
or x5 (c_out,e,f,g);
endmodule
BLACK BOX:
RTL SCHEMATIC
48
VERILOG CODE TO REALIZE HALF SUBTRACTOR:

module Half_Sub(a, b, diff, borrow);

input a, b;
output diff, borrow;
assign diff = a ^ b;
assign borrow = (~a)& b;
endmodule
RTL SCHEMATIC
VERILOG CODE TO REALIZE FULL SUBTRACTOR:

module Full_Sub(a, b, b_in, diff, b_out);

input a, b,b_in;
output diff, b_out;
assign diff = a ^ b ^ b_in;
assign b_out = ((~a)&b_in) | ((~a)& b) | (b &b_in);
endmodule
RTL SCHEMATIC
49
VERILOG CODE TO REALIZE MULTIPLEXER:

//////// Behavioural modeling
module Mux4_1(d0,d1,d2,d3,s0,s1, y);

input d0,d1,d2,d3,s0,s1;
output y;
reg y;
always @(d0,d1,d2,d3,s0,s1)
begin
case ({s0,s1})
2'b00 : y=d0;
2'b01 : y=d1;
2'b10 : y=d2;
2'b11 : y=d3;
endcase
end
endmodule
RTL SCHEMATIC
50
VERILOG CODE TO REALIZE DEMULIPLEXER:
VERILOG CODE: DESIGN:

//////// Structural modeling
module demux1_4 (din, s0,s1,y0,y1,y2,y3);

input din, s0,s1;
output y0,y1,y2,y3;
wire e, f ;
not x1 (e,s1);
not x2 (f,s0);
and x3 (y0,din,e,f);
and x4 (y1,din,e,s0);
and x5 (y2,din,s1,f);
and x6 (y3,din,s1,s0);
endmodule
BLACK BOX:
RTL SCHEMATIC
51
VERILOG CODE TO REALIZE ENCODER:

module encoder4_2 ( d3,d2,d1,d0,a,b );

input d3,d2,d1,d0;
output a,b ;
assign a = d2 | d3;
assign b = d1 | d3;
endmodule
RTL SCHEMATIC
52
VERILOG CODE TO REALIZE DECODER:

module decoder2_4 ( a ,b , en,y0,y1,y2,y3);

input a,b ,en ;
output y0,y1,y2,y3;
assign y0 = (~a) & (~b)& en;
assign y1 = (~a) & b & en;
assign y2 = a & (~b) & en;
assign y3 = a & b & en;
endmodule
RTL SCHEMATIC
RESULT
Thus the program for all combinational circuits using Verilog is developed and checked
its RTL schematic with its simulation waveforms.
53
EXPT NO : 14 VERILOG CODE TO REALIZE FLIP-FLOPS
DATE:
AIM:
To write a program to realize the following Flip-flops using Verilog and obtain its RTL
schematic with necessary simulation waveforms.
 JK FF
 T FF
 D FF
APPARATUS REQUIRED:
VERILOG CODE TO REALIZE JK-FF:

module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ; Truth Table:
input reset ;
wire reset ;
always @ (posedge (clk)) begin

if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end
endmodule
54
RTL SCHEMATIC
55
VERILOG CODE TO REALIZE T-FF:

module T_flip_flop ( t ,clk ,reset ,dout );
output dout ;
reg dout ;
input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0; Truth Table:

if (reset)
dout <= 0;
else begin
if (t)
dout <= ~dout; ̅
end
end
endmodule
RTL SCHEMATIC
56
VERILOG CODE TO REALIZE D-FF:

module d_flip_flop ( din ,clk ,reset ,dout );
output dout ;
reg dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin Truth Table:

if (reset)
dout <= 0;
else
dout <= din ;
end
endmodule
RTL SCHEMATIC
RESULT
Thus the program for Flip-Flops using Verilog is developed and checked its RTL
57
EXPT NO: 15. a VERILOG CODE TO REALIZE SERIAL IN PARALLEL OUT SHIFT
DATE: REGISTER (SIPO)
AIM:
To write a program to realize SIPO shift register using Verilog and obtain its RTL
schematic and necessary simulation waveforms.
APPARATUS REQUIRED:

module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s; Truth Table:
always @ (posedge (clk))
begin clk
if (reset)
s <= 0; 1 1 0 0 0
else begin 2 0 1 0 0
s[3] <= din; 3 0 0 1 0
s[2] <= s[3]; 4 1 0 0 1
s[1] <= s[2]; 5 x 1 0 0
s[0] <= s[1]; 6 x x 1 0
end 7 x x x 1
end
assign dout = s;
endmodule
RTL SCHEMATIC
58
RESULT
Thus the program for SIPO shift register using Verilog is developed and checked its RTL
EXPT NO: 15. b VERILOG CODE TO REALIZE BINARY UP COUNTER

DATE:
AIM:
To write a program to realize 4 bit binary up counter using Verilog and obtain its RTL
schematic and necessary simulation waveforms.
APPARATUS REQUIRED:

module Counter(clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;

if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
59
RTL SCHEMATIC
RESULT
Thus the program for 4 bit binary up counter using Verilog is developed and checked its
RTL schematic with its simulation waveforms.
60

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ANJALAI AMMAL - MAHALINGAM ENGINEERING COLLEGE

KOVILVENNI - 614 403.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.,

CS6211 / IT6211 DIGITAL LAB MANUAL

SYLLABUS -LIST OF EXPERIMENTS

1. Verification of Boolean Theorems using basic gates.

1. Study of Logic Gates.

LIST OF CYCLE - II EXPERIMENTS:

9. Design implementation of Encoder and Decoder.

 Connections are given as per the circuit diagram.

EXPT NO : 2 VERIFICATION OF BOOLEAN THEOREMS USING BASIC GATES

7.De Morgan’s Theorem

EXPT NO : 3 DESIGN AND IMPLEMENTATION OF ADDER/ SUBTRACTOR

BCD to Excess – 3 Converter:

IC 7483 4- BIT BINARY PARALLEL ADDER

Input data A Input data B Addition Subtraction

16–bit odd/ even parity generator /checker:

3-BIT ODD/EVEN PARITY GENERATOR/ CHECKER:

16-BIT ODD/EVEN PARITY GENERATOR/ CHECKER:

EXPT NO : 7 DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

Equality : Consider two numbers, A and B, with four digits each .

if and are equal.

2–BIT MAGNITUDE COMPARATOR:

Circuit Diagram: Truth Table:

Pin Diagram: Truth Table:

Pin Diagram: Logic Diagram:

EXPT NO : 9 DESIGN AND IMPLEMENTION OF ENCODER AND DECODER

Circuit Diagram: Truth Table:

Circuit Diagram: Truth Table:

EXPT NO : 10 DESIGN AND IMPLEMENTION OF SHIFT REGISTERS

Serial-in Serial-out (SISO):

IC 7474 D FLIP FLOP:

Serial-in Parallel-out (SIPO):

Parallel-in Parallel-out (PIPO):

EXPT NO : 11 DESIGN AND IMPLEMENTATION OF COUNTERS

4-BIT BINARY (RIPPLE) UP COUNTER:

Waveform for MOD-10:

4-BIT SYNCHRONOUS UP COUNTER:

VERILOG CODE TO REALIZE ALL LOGIC GATES:

TEST BENCH WAVEFORM:

VERILOG CODE TO REALIZE HALF ADDER:

VERILOG CODE: BLACK BOX:

module Half_Adder(a, b, sum, carry);

TEST BENCH WAVEFORM:

VERILOG CODE: DESIGN:

module Full_Adder(a, b ,c_in, sum, c_out);

TEST BENCH WAVEFORM:

VERILOG CODE: BLACK BOX:

module Half_Sub(a, b, diff, borrow);

TEST BENCH WAVEFORM:

VERILOG CODE TO REALIZE FULL SUBTRACTOR:

VERILOG CODE: BLACK BOX:

module Full_Sub(a, b, b_in, diff, b_out);

VERILOG CODE TO REALIZE MULTIPLEXER:

VERILOG CODE: BLACK BOX:

module Mux4_1(d0,d1,d2,d3,s0,s1, y);

TEST BENCH WAVEFORM:

VERILOG CODE: DESIGN: