CS 8382 / DIGITAL SYSTEMS

LABORATORY

LAB MANUAL
(REGULATION – 2017)

NAME :
REGISTER NUMBER :
YEAR/BRANCH : CSE
SEMESTER : III SEM (ODD)
ACADEMIC YEAR :

1
 CS 8382 /DIGITAL SYSTEMS LABORATORY

LAB MANUAL

SYLLABUS

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary functions, code converters.
3. Design and implementation of combinational circuits using MSI devices:
 4 – Bit binary adder / subtractor
 Parity generator / checker
 Magnitude Comparator
 Application using multiplexers
4. Design and implementation of sequential circuits:
 Shift –registers
 Synchronous and asynchronous counters
5. Coding combinational / sequential circuits using HDL.
6. Design and implementation of a simple digital system (Mini Project).

LIST OF EXPERIMENTS
1. (a) Study of logic gates.
(b) Verification of Boolean theorems using basic gates.
2. Design and implementation of adders and subtractors using logic gates.
3. Design and implementation of code converters using logic gates.
4. Design and implementation of 4-bit binary adder/subtractor and BCD adder using IC 7483.
5. Design and implementation of 8-bit magnitude comparator using IC 7485.
6. Design and implementation of 8-bit odd/even parity checker/ generator using IC 74180.
7. Design and implementation of multiplexer and demultiplexer using logic gates.
8. Design and implementation of encoder and decoder using logic gates.
9. Construction and verification of 4-bit ripple counter.
10. Design and implementation of 3-bit synchronous up/down counter.
11. Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops.
12. Coding combinational / sequential circuits using HDL.
 Half adder and Full adder
 Half subtractor and Full subtractor
 Synchronous counter
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 INDEX

PAGE
S.NO DATE NAME OF THE EXPERIMENT MARKS SIGNATURE
NO

3
EXP NO.: 1 (A)
DATE :
STUDY OF LOGIC GATES
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and
only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these
gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The output is high when
both the inputs are high. The output is low level when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high when any one
of the inputs is high. The output is low level when both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is low when the
input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the
input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when
one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs are low and both
the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
4
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

NOT GATE:
SYMBOL: PIN DIAGRAM:

5
X-OR GATE :
SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

6
NOR GATE:

RESULT:
Thus the Logic Gates were studied and the Truth Table were verified.

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EXP NO.:1(B)
DATE:
VERIFICATION OF BOOLEAN ALGEBRA
AIM
1. To verify the rules and regulations of Boolean algebra.
2. To simplify and modify Boolean logic functions by means of Demorgan’s theorem.
3. To design and implement a logic circuit.
BACKGROUND
Boolean algebra is a deductive mathematical system closed over the values zero and one (false and true). A binary
operator defined over this set of values accepts a pair of Boolean inputs and produces a single Boolean value.
We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no identity element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is, A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B)
• (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1. This value is the logical complement (or
NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C). You can prove all other theorems
in boolean algebra using these postulates.
Laws of Boolean algebra
• Commutative Laws
• Associative Laws
• Distributive Law6

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THEORY:
1. A+0 = A
2. A+1 = 1
3. A .0 = 0
4. A .1 = A
5. A+A = A
6. A+A’ = 1
7. A.A = A
8. A.A’ = 0
9. (A’)’ = A
10. A+AB = A
11. A+A’B = A+B
12. (A+B)(A+C) = A+BC
13. A’. B’ = (A+B)’
14. A’+B’ = (A.B)’
PRELAB:
1. Refer to your text book, understand the concepts of Boolean Algebra.
2. Draw truth table, logic diagram and pin diagram for each part in THEORY.
PROCEDURES:
Part I:
a) Connect these circuits and verify their
operations

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Part II: Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’ respectively. Show that for all
combinations of A and B, the two circuits give identical results. Connect these circuits and verify their operations.

b) Proof of equation (2)

Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B, respectively. Show that, for all
combinations of A and B, the two circuits give identical results. Connect these circuits and verify their operations.

RESULT:
Thus the rules & regulation of Boolean Algebra are implemented and verified successfully.

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EXP. NO: 2 IMPLEMENTATION OF ADDER AND SUBTRACTOR
DATE: a. HALF ADDER AND FULL ADDER
AIM:
To design and verify the truth table of the Half Adder & Full Adder circuits.
REFERENCE BOOKS:
1. Raj Kamal, ‘Digital systems-Principles and Design’, Pearson education 2nd edition, 2007.
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
S.NO. NAME OF THE APPARATUS RANGE QUANTITY
1 Digital IC trainer kit 1
2 AND gate IC 7408 1
3 OR gate IC 7432 1
4 NOT gate IC 7404 1
5 EX-OR gate IC 7486 1
6 Connecting wires As required
THEORY:
The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary
operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 102
The first three operations produce a sum of whose length is one digit, but when the last operation is performed the
sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum.
HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder. The input variables designate
the augend and the addend bit, whereas the output variables produce the sum and carry bits.
FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input
bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and
one OR gate.
From the truth table the expression for sum and carry bits of the output can be obtained as,
SUM = A’B’C + A’BC’ + AB’C’ + ABC
CARRY = A’BC + AB’C + ABC’ +ABC
HALF ADDER
TRUTH TABLE:

11
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM: CARRY:

CIRCUIT DIAGRAM:

12
PROCEDURE
1. Connections are given as per the circuit diagrams.
2. For all the Ics 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
RESULT:
The design of the half adder and full adder circuits was done and their truth tables were verified.
*************************************
b. HALF SUBTRACTOR AND FULL SUBTRACTOR
AIM:
To design and verify the truth table of the Half Subtractor & Full Subtractor circuits.
REFERENCE BOOKS:
1. Raj Kamal,‘Digital systems-Principles and Design’, Pearson education 2nd edition, 2007
2. M. Morris Mano, ‘Digital Design’, Pearson Education, 2006
APPARATUS REQUIRED:
S.NO. NAME OF THE APPARATUS RANGE QUANTITY
1 Digital IC trainer kit 1
2 AND gate IC 7408 1
3 OR gate IC 7432 1
4 NOT gate IC 7404 1
5 EX-OR gate IC 7486 1
6 Connecting wires As required
THEORY:
The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,
0-0=0
0 - 1 = 1 with 1 borrow 1 - 0 = 1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the
minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables
designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits.
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input
bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half
subtractors and one OR gate. From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC
Borrow, BORR = A’BC + AB’C + ABC’ +ABC
HALF SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S.No.
A B DIFF. BORR.
1 0 0 0 0
2 0 1 1 1
3 1 0 1 0
4 1 1 0 0

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 From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A B
Borrow, BORR = A’. B
CIRCUIT DIAGRAM:

2. FULL SUBTRACTOR
INPUT OUTPUT
S.No.
A B C DIFF. BORR.
1 0 0 0 0 0
2 0 0 1 1 1
3 0 1 0 1 1
4 0 1 1 0 1
5 1 0 0 1 0
6 1 0 1 0 0
7 1 1 0 0 0
8 1 1 1 1 1

Using Karnaugh maps the reduced expression for the output bits can be obtained as,
DIFFERENCE BORROW

DIFF = A’B’C + A’BC’ + AB’C’ + A BC = A B C

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CIRCUIT DIAGRAM:

PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.
DISCUSSION QUESTIONS:
1. What is combinational circuit?
2. What is different between combinational and sequential circuit?
3. What are the gates involved for binary adder?
4. List the properties of Ex-Nor gate?
5. What is expression for sum and carry?

RESULT:
The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.

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EXP NO.: 3
DATE :
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of information results in the use of
different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different
codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each
uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal
digit. There are four inputs and four outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co.
from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output
variable.
A code converter is a circuit that makes the two systems compatible even though each uses a different binary
code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are
various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has
been used to implement partially each of three outputs.
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

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K-Map for G3: K-Map for G2:

G3 = B3
K-Map for G1: K-Map for G0:

TRUTH TABLE:
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
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 1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

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TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

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TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

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TRUTH TABLE:
| Excess – 3 Input | BCD Output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT: Thus the Code Convertors were designed and the Truth Table were verified.
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EXP NO.: 4
DATE :
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40
THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed
with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full
adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left,
with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input
carry to the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data input ‘B’ and the
corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one common binary adder. The
mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage.
Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry.
The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the
input carry, are first added in the top 4 bit adder to produce the binary sum.
PIN DIAGRAM OF IC 7483:

22
LOGIC DIAGRAM:
4-BIT BINARY ADDER

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

23
TRUTH TABLE:
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
LOGIC DIAGRAM:
BCD ADDER

KMAP

Y = S4 (S3 + S2)
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TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:
Thus the 4-bit Binary Adder/Subtractor were designed and the truth table were verified.

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EXP NO.: 5
DATE :
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30
THEORY:
The comparison of two numbers is an operator that determine one number is greater than, less than (or) equal to
the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine
their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B,
A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from
most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
PIN DIAGRAM OF IC 7485:

26
LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the Magnitude Comparators were designed and the Truth Table were verified.

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EXP NO.: 6
DATE :
16 BIT ODD/EVEN PARITY CHECKER /GENERATOR
AIM:
To design and implement 16 bit odd/even parity checker generator using IC 74180.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. NOT GATE IC 7404 1
1. IC 74180 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30
THEORY:
A parity bit is used for detecting errors during transmission of binary information. A parity bit is an extra bit
included with a binary message to make the number is either even or odd. The message including the parity bit is
transmitted and then checked at the receiver ends for errors. An error is detected if the checked parity bit doesn’t
correspond to the one transmitted. The circuit that generates the parity bit in the transmitter is called a ‘parity generator’
and the circuit that checks the parity in the receiver is called a ‘parity checker’.
In even parity, the added parity bit will make the total number is even amount. In odd parity, the added parity bit
will make the total number is odd amount. The parity checker circuit checks for possible errors in the transmission. If the
information is passed in even parity, then the bits required must have an even number of 1’s. An error occur during
transmission, if the received bits have an odd number of 1’s indicating that one bit has changed in value during
transmission.
PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS OUTPUTS
Number of High Data
PE PO ∑E ∑O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1

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LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATORS

TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the Parity Checker/Generator circuits were designed and the truth table were verified.
29
EXP NO.: 7
DATE :
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A
digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to
a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n
input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and
distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor.
Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only
one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

30
LOGIC DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

31
LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150: PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the Multiplexer and De-multiplexer circuits were designed and the truth table were verified.

32
EXP NO.: 8 DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
DATE :
AIM:
To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27
THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n input lines and n
output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary
encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In
encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has
an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where
input and output codes are different. The input code generally has fewer bits than the output code. Each input code word
produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram
of decoder circuit the encoded information is present as n input producing 2 n possible outputs. 2n output values are from 0
through out 2n – 1.
PIN DIAGRAM FOR IC 7445: PIN DIAGRAM FOR IC 74147:
BCD TO DECIMAL DECODER:

LOGIC DIAGRAM FOR ENCODER:

33
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the Encoder and Decoder circuits were designed and the truth table were verified.
34
EXP NO.: 9 CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12
RIPPLE COUNTER
DATE :
AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30
THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents
the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference
between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common
clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip
flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage.
Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous
operation.
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

35
TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

36
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the Ripple Counter circuits were designed and the truth table were verified.

37
EXP NO.: 10
DATE :
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35
THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents
the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or
decreasing order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/down
operation of the counter is controlled by up/down signal. When this signal is high counter goes through up sequence and
when up/down signal is low counter follows reverse sequence.
K MAP

STATE DIAGRAM:

38
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LOGIC DIAGRAM:

TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA Q B QC QA+1 Q B+1 QC+1 JA K A JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the Synchronous Counter circuits were designed and the truth table were verified.
39
EXP NO.: 11
DATE :
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35
THEORY:
A register is capable of shifting its binary information in one or both directions is known as shift register. The
logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of
next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of
next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

40
TRUTH TABLE:
CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

41
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the Shift Registers were designed and the truth tables were verified.
42
EXP. NO: 12
DATE:
DESIGN OF COMBINATIONAL CIRCUIT & SEQUENTIAL CIRCUIT USING VERILOG HDL
AIM:
To write a HDL program for the following sequential circuit and simulated ley using ISE simulator Half adder &
Full adder, Multiplexers, Shift Register.
APPARATUS REQUIRED:
PC with Xlinx ISE 9.21 software.
PROCEDURE:
Click Start  All programs  x linx ISE921  project navigator.
Go to the file menu click new project wizard will open.
New project wizard. Enter a name location of the project and select the type of top level source for the project as
HDL click next.
In device properties of the new project wizard select ISE simulator and verilog as periffered language click next in
create new source select verilog module and type the name click next and click finish.
Type the program and serve it. In the left side of window select source tale and expand implement design option
and synthesis by double clicking the synthesis xst click for errors and view RTL schematic and synthgesis reoprt.
For simulation, choose behaviour simulation is the source list box and doubvle clocking create a new source
option in process tab.
Check test bench waveform and type the filename and click next.
Select the source with which to associate the new information and clock finish.
Set the input values of input variable and save it. The simulate ley using XLINC ISE simulator in the process tab.
HALF ADDER
Program:
module HA1(sum, carry,a,b);
input a; input b;
output sum; output carry;
xor (sum,a,b);
and (carry,a,b);
endmodule

FULL ADDER
module FA(sum, carry, a, b, c);
input a,b,c;
output sum; output carry;
43
 wire x1,x2,x3;
and (x1,a,b);
and (x2,b,c);
and (x3,c,a);
xor (sum,a,b,c);
or (carry,x1,x2,x3);
endmodule

HALF SUBTRACTOR
module hs1(difference, borrow,a,b);
input a; input b;
output difference, borrow;
wire a1;
xor (difference,a,b);
not (a1,a);
and (borrow,a,b);
endmodule

FULL SUBTRACTOR
module fs1 (difference, borrow, a, b, c);
input a,b,c; output difference, borrow;
wire x1,x2,x3,x4;
not (x1,a);
and (x2,x1,b);
and (x3,b,c);
and (x4,c, x1);
xor (difference,a,b,c);
or (borrow,x2,x3,x4);
44
 endmodule

Asynchronous counter
module counter(clock, clear, out);
input clock;
input clear;
output out;
reg[1:0]out;
always@(posedge clock,negedge clear)
if((~clear)||(out>=4))out=2'b00;
else out=out+1;
endmodule

VERILOG TEXT FIXTURE PROGRAM

module ftfjfmjh_v;
// Inputs
reg clock;
reg clear;

// Outputs
wire [1:0] out;

// Instantiate the Unit Under Test (UUT)

counter uut (
.clock(clock),
.clear(clear),
.out(out)
);
initial begin
// Initialize Inputs
$display("\t\t.......");
$display("\t\tclock\t\tclear\t\toutput[2]");
$display("\t\t....");
$monitor("\t\t %b\t\t %b\t\t %b",clock,clear,out);
#28$display("\t\t.........");
end
always
#1clock=~clock;
initial
begin
clock=0;clear=0;
#10clear=1;
#16clear=0;
#2$stop;
45
 end
// Wait 100 ns for global reset to finish
endmodule

//synchronous counter
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock ; input reset ; input enable ;
//-------------Output Ports----------------------------
output [3:0] counter_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ; wire reset ; wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;
//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block Name
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset == 1'b1) begin
counter_out <= #1 4'b0000;
end
// If enable is active, then we increment the counter
else if (enable == 1'b1) begin
counter_out <= #1 counter_out + 1;
end
end // End of Block COUNTER
endmodule

//VERILOG TEXT FIXTURE PROGRAM

`timescale 1ns / 1ps
46
 ////////////////////////////////////////////////////////////////////////////////
`include "first_counter.v"
module first_counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;
// Initialize all variables
initial begin
$display ("time\t clk reset enable counter");
$monitor ("%g\t %b %b %b %b",
$time, clock, reset, enable, counter_out);
clock = 1; // initial value of clock
reset = 0; // initial value of reset
enable = 0; // initial value of enable
#3 reset = 1; // Assert the reset
#5 reset = 0; // De-assert the reset
#5 enable = 1; // Assert enable
#105 enable = 0; // De-assert enable
#3 $finish; // Terminate simulation
end
// Clock generator
always begin
#3 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
first_counter U_counter (
clock, reset,enable,counter_out );
endmodule

RESULT:
Thus the program was executed successfully and the output is verified.
47