Microprocessor Systems (Μp 2) : Goal: PC Hardware Study
Microprocessor Systems (Μp 2) : Goal: PC Hardware Study
Microprocessor Systems (Μp 2) : Goal: PC Hardware Study
GOAL :
PC Hardware Study:
- 8086,Pentium
- Memory (Main, Cache)
-Programmable Interfaces (Timer, PIC, DMAC, PIO)
(architecture, programming, applications)
- SPP/EPP/ECP, COM, USB, I2C/SPI
- Buses (ISA, PCI)
1
REFERENCES
-Lupu, E. , Mesaroş, A. , Suciu, A.F. MICROPROCESSORS. Architectures and Applications
Ed. RISOPRINT Cluj-Napoca 2002
-Lupu, E. SISTEME CU MICROPROCESOARE. Resurse hardware. Prezentare, programare şi
aplicaţii. Ed. Albastră Cluj Napoca 2004, ISBN 973-650-109-4
-Tischer M., Jennerich B. “LA BIBLE PC” PROGRAMMATION SYSTEME. MICRO Application 2003
-N. Mathivanan Microprocessors, PC Hardware and Interfacing PHI Learning Pvt. Ltd., 2003
ISBN 8120323173, 9788120323179 .....
- SLIDES: http://users.utcluj.ro/~elupu/Curs/index.php
2
Evaluation:
Final Mark
- 70% exam (theory + problems) > 4.5
- 30 % laboratory tests >4.5
BONUS:
- Course attendance >50% roundup final mark else rounddown
- Homework +PRJ
3
" Life is hard, especially if you're stupid. " John Wayne
C1
8086/88 MIN/MAX MODES
OUTLINE
Year 1978 1979 1982 1985 1989 1992 1995 1997 1999 2001 2004
3200-
CLK (MHz) 5-10 5-8 6-16 16-33 25-50 60/ 66 150 400 800 1700
3400
Transistors
29 k 2k 130 k 275 k 1.2 M 3.1 M 5.5 M 7.5 M 28 M 42 M 55M
no.
Physical
Memory 1 Mo 1 Mo 16 Mo 4 Go 4 Go 4 Go 64 Go 64 Go 64 Go 64 Go
Internal Data
16 16 16 32 32 32 32 32 32 32
Bus
External Data
16 8 16 32 32 64 64 64 64 64
Bus
8,16,
Data Type 8, 16 8, 16 8, 16 8, 16, 32 8,16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
32
16 ko L1 32 ko L1 32 ko L1
20 ko L1
Cache -- -- -- -- 8 ko L1 16 ko L1 256/512ko 256/512ko 256/512ko + 2Mo
512ko L2
Memory L2 L2 L2 L3
MIPS~ 0.8 0.8 2.7 6 20 100 440 440 700 3000 13000
7
8
9
10
8086 Pinout Signals
11
12
13
14
15
16
8284 – CLOCK GENERATION
17
18
Block diagram of the 8284
19
+5V
+5V
MN/MX 0
U4 U30
A19-A16 3X
OE
MN/
CLK
RES READY BHE
RESET ALE Adre ss bus A19-A0
8284 BHE STB
8086 AD15-AD0 Latches
MPU 8282
Clock
RD
generator
DT/R
DEN
WR
0 MI/O
D15-D0
I/O
Memory
peripheral
T
Buffers 2X
8286
OE
Data Bus
(D15-D0)
AL E
+5 V
xM X 0
U4
STB
MN/ BHE BHE
CL K Adre ss bus A19-A0
RES REA DY A19-A16
RES ET
8284
S0 Latches
8086 S1 X3
Clock S2
gen erator MPU AD0-AD15
I/O
0 8282 Memory
peripheral