Datasheet - HK Tmp86cm29lug 4125677

8 Bit Microcontroller
TLCS-870/C Series
TMP86CM29LUG
TMP86CM29LUG
The information contained herein is subject to change without notice. 021023 _ D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products
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060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
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For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2006 TOSHIBA CORPORATION

All Rights Reserved
Page 2
TMP86CM29LUG
The Functional Differences on Products basis: TMP86CM29L, TMP86Cx29B, TMP86CH21

and TMP86Cx20
TMP86C829B
TMP86CH21 TMP86C420
Products name TMP86CM29L TMP86CH29B
TMP86CH21A TMP86C820
TMP86CM29B
C829: 8K bytes
C420: 4K bytes
ROM 32 K bytes CH29: 16K bytes 16K bytes
C820: 8K bytes
CM29: 32K bytes
C829: 512bytes
RAM 1.5K bytes CH29: 1.5K bytes 512bytes 256bytes
CM29: 1.5K bytes
I/O port 39 pins
Minumum command
0.25µsec at 16MHz
execution time
1.8V to 3.6V at 8.0MHz/

32.768kHz 1.8V to 5.5V at 4.2MHz/32.768kHz
Supply Voltage 2.7V to 3.6V at 16MHz/ 2.7V to 5.5V at 8.0MHz/32.768kHz
32.768kHz 4.5V to 5.5V at 16MHz/32.768kHz
(Note4)
1ch 1ch
18-bit Timer counter
(ECIN input is both edge or single edge) (ECIN input is single edge)
8-bit Timer counter 4ch 2ch
Time base timer 1ch
Watch dog timer 1ch
UART/SIO 1ch (Note1) N.A.
SIO N.A 1ch
Key-on wakeup 4ch
A/D converter 10-bit A/D: 8ch 8-bit A/D: 8ch
LCD driver 32SEG x 4COM
Operating Temperature -40 to 85 ℃ -40 to 85 ℃ (Note2) -40 to 85 ℃
QFP64(14x14mm)
Package(Body size) LQFP64(10x10mm)
LQFP64(10x10mm)
TMP86C829BFG
Package TMP86C420FG
N.A TMP86CH29BFG TMP86CH21FG
(P-QFP64-1010-0.80C) TMP86C820FG
TMP86CM29BFG
TMP86C829BUG
Package TMP86C420UG
N.A TMP86CH29BUG TMP86CH21UG
(P-LQFP64-1010-0.50E) TMP86C820UG
TMP86CM29BUG
Package
TMP86CM29LUG N.A. TMP86CH21AUG N.A.
(P-LQFP64-1010-0.50D)
Note 1: UART and SIO can not use function synchronously because each function pins are shared.
Note 2: With TMP86CH21AUG the operating temperature (Topr) is -20 ℃ to 85 ℃ when the supply voltage VDD is less than 2.0V.
Note 3: TMP86C820/420 don’t have the timer/counter-6 input/output and UART input/output.
Note 4: The electrial characteristics of TMP86CM29LUG are different from that of TMP86C829/CH29/CM29B, TMP86CH21/
CH21A and TMP86C420/C820. For details, please refer to "Electrical Characteristics" in data sheet of TMP86CM29LUG.
Note 5: The operating temperature (Topr) of AD characteristics of all products (TMP86C420/C820/CH21/CH21A/C829B/CH29B/
CM29B/CM29L) is -10 ℃ to 85 ℃ when the supply voltage VDD is less than 2.0V. For details, please refer to "AD Conver-
sion Characteristics" in data sheet of each product.
Note 6: The characteristic of power supply current differs in each product. For details, please refer to "Electirical Characteristics"
in data sheet of each product.
Page 3
TMP86CM29LUG
The Functional Differences on Products basis: TMP86C829B/CH29B/CM29B/PM29A/

PM29B/FM29/CM29L.
TMP86PM29A
Products name TMP86C829B TMP86CH29B TMP86CM29B TMP86FM29 TMP86CM29L
TMP86PM29B
8K bytes 16K bytes 32K bytes 32K bytes 32K bytes 32K bytes
ROM
(MASK) (MASK) (MASK) (OTP) (FLASH) (MASK)
RAM 512 bytes 1.5K bytes
128 bytes
128 bytes
DBR (Flash memory control/status registers
(Flash memory control/status registers <EEPCR, EEPSR> are non-available.)
<EEPCR, EEPSR> are available.)
I/O port 39 pins
Large current output 4 pins (Sink-open-drain output) 4 pins (Sink-open-drain output)

(Nch) port 20 mA (Typ) 6 mA (Typ)
Interrupt sources External: 5 Internal: 14
18bit Timer/Counter: 1ch

Timer/Counter
8bit Timer/Counter: 4ch
UART/SIO 1ch (Note1)
Key-on wakeup 4ch
AD converter 10bit x 8ch (Note3)
LCD driver 32SEG x 4COM
VDD No Protection VDD

Diode (VDD side)
R R R
Circuitry of TEST pin
RIN No Pull down RIN
Resistor
Feedback resistor in
High- frequency circuit Rf = 1.2 M Ω(Typ) Rf = 3 M Ω(Typ)
(Note4)
Feedback resistor in
Low- frequency circuit Rf = 6 M Ω(Typ) Rf = 20 M Ω(Typ)
(Note4)
Emulation Chip
TMP86C929AXB
(Note2)
P-QFP64-1414-0.80C P-LQFP64-1010-
Package
P-LQFP64-1010-0.50E 0.50D
1.8V to 5.5V at 4.2MHz/32.768kHz 1.8V to 3.6V at 8.0MHz/32.768kHz

Operating voltage
2.7V to 5.5V at 8.0MHz/32.768kHz 2.7V to 3.6V at 16MHz/32.768kHz
(Note 5)
4.5V to 5.5V at 16MHz/32.768kHz (Note 6)
Note 1: UART and SIO can not use function synchronously because each function pins are shared.
Note 2: An emulation chip (TMP86C929AXB) can’t emulate the Flash memory functions, CPU wait and serial PROM mode.
Therefore, if the software which includes Flash memory function or CPU wait is executed in TMP86C929AXB, the opera-
tion might be different from TMP86FM29/CM29L.
Note 3: The operating temperature (Topr) of AD characteristics of all products (TMP86C829B/CH29B/CM29B/PM29A/PM29B/
FM29/CM29L) is -10℃ to 85℃ when the supply voltage VDD is less than 2.0V. For details, please refer to "AD Conversion
Characteristics" in data sheet of each product.
Note 4: The typical value of high and low frequency feedback resistor in TMP86FM29/CM29L are different from that of the other
products. For details, please refer to "Input/Output Circuitry" in data sheet of each product.
Note 5: The characteristic of power supply current differs in each product. For details, please refer to "Electirical Characteristics"
in data sheet of each product.
Note 6: The recommended operating condition of serial PROM mode in TMP86FM29 is different from MCU mode. Fore details,
please refer to "Electirical Characteristics" in data sheet of each product.
TMP86CM29LUG
Halt/Operate
Condition Wait Time‘
CPU Peripherals
After reset release 10 Halt Halt

2 /fc [s]
Changing from STOP mode to NORMAL mode

210/fc [s] Halt Operate
(at EEPCR<MNPWDW>="1"
Changing from STOP mode to SLOW mode

(at EEPCR<MNPWDW>="1")
Changing from IDLE0/1/2 mode to NORMAL mode

Changing from SLEEP0/1/2 mode to SLOW mode

Note 1: TMP86FM29 has a CPU wait function which is a warming up (CPU halt) of CPU for stabilizing of power supply of
Flash memory. Even though TMP86CM29L doesn’t have a Flash memory, the CPU wait function is inserted to
keep the compatibility with Flash product (TMP86FM29). During the CPU wait period except RESET, CPU is
halted but peripheral functions are not halted. Therefore, if the interrupt occurs during the CPU wait period, the
interrupt latch (IL) is set and when IMF has been set to "1", the interrupt service routine might be executed after
CPU wait period . For details, please refer to "Flash Memory" in TMP86FM29 data sheet. TMP86FM29 (Flash
product) should be used as non-volatile product to confirm the software of TMP86CM29L because of the above
reason. And TMP86PM29A/PM29B (OTP product) should be used as non-volatile product to confirm the software
of TMP86C829B/CH29B/CM29B.
Type-1 Type-2 Type-3 Type-4 Type-5

(Reference pin =V1) (Reference pin =V1) (Reference pin =V2) (Reference pin =V3) (Reference pin =V3)
VDD VDD VDD VDD
V3 V3 V3 V3 VDD
C C C
V2 V2 V2 V2 V3
C C C C
V1 V1 V1 V1 V2
C C C
Reference Reference Reference Reference V1
Voltage C C Voltage Voltage Voltage C
C1 C1 C1 C1
C C C C
C0 C0 C0 C0 C1
VSS VSS VSS VSS C
C0
VSS
Note 1: TMP86FM29/CM29L can't use LCD panel which is driven by 5V because the maximum recommended voltage is
3.6V. Therefore, the voltage level of V3 pin always should be under 3.6V.
Note 2: The operating temperature of TMP86FM29/CM29L in Type-1 and Type-2 is -10 ℃ to 85 ℃ . For details, please
refer to "LCD Driver" and "Electrical Characteristics" in data sheet.
Note 3: The operating temperature of TMP86C829B/CH29B/CM29B in all Types (Type 1 to 5) is -40 ℃ to 85 ℃ . However,
there is a voltage level limitation of V3 and VDD pin in each type. For details, please refer to "LCD Driver" and
"Electrical Characteristics" in data sheet.
Page 5
TMP86CM29LUG
Revision History
Date Revision
2006/10/18 1 First Release
Table of Contents
TMP86CM29LUG
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Operational Description
2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Memory Address Map............................................................................................................................... 9
2.1.2 Program Memory (MaskROM).................................................................................................................. 9
2.1.3 Data Memory (RAM) ................................................................................................................................. 9
2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Clock Generator...................................................................................................................................... 10
2.2.2 Timing Generator .................................................................................................................................... 12
2.2.2.1 Configuration of timing generator
2.2.2.2 Machine cycle
2.2.3 Operation Mode Control Circuit .............................................................................................................. 13
2.2.3.1 Single-clock mode
2.2.3.2 Dual-clock mode
2.2.3.3 STOP mode
2.2.4 Operating Mode Control ......................................................................................................................... 19
2.2.4.1 STOP mode
2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode
2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
2.2.4.4 SLOW mode
2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.1 External Reset Input ............................................................................................................................... 34
2.3.2 Address trap reset .................................................................................................................................. 35
2.3.3 Watchdog timer reset.............................................................................................................................. 35
2.3.4 System clock reset.................................................................................................................................. 35
3. Interrupt Control Circuit
3.1 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 38
3.2.2 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 38
3.3 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.1 Interrupt acceptance processing is packaged as follows........................................................................ 41
3.4.2 Saving/restoring general-purpose registers ............................................................................................ 42
3.4.2.1 Using PUSH and POP instructions
i
3.4.2.2 Using data transfer instructions
3.4.3 Interrupt return ........................................................................................................................................ 44
3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.5.1 Address error detection .......................................................................................................................... 45
3.5.2 Debugging .............................................................................................................................................. 45
3.6 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4. Special Function Register (SFR)
4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5. I/O Ports
5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2 Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3 Port P3 (P33 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4 Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.5 Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6 Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6. Watchdog Timer (WDT)
6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2.1 Malfunction Detection Methods Using the Watchdog Timer ................................................................... 62
6.2.2 Watchdog Timer Enable ......................................................................................................................... 63
6.2.3 Watchdog Timer Disable ........................................................................................................................ 64
6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 64
6.2.5 Watchdog Timer Reset ........................................................................................................................... 65
6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.1 Selection of Address Trap in Internal RAM (ATAS) ................................................................................ 66
6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 66
6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 66
6.3.4 Address Trap Reset ................................................................................................................................ 67
7. Time Base Timer (TBT)
7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.1.1 Configuration .......................................................................................................................................... 69
7.1.2 Control .................................................................................................................................................... 69
7.1.3 Function .................................................................................................................................................. 70
7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2.1 Configuration .......................................................................................................................................... 71
7.2.2 Control .................................................................................................................................................... 71
8. 18-Bit Timer/Counter (TC1)
ii
8.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.3.1 Timer mode............................................................................................................................................. 77
8.3.2 Event Counter mode ............................................................................................................................... 78
8.3.3 Pulse Width Measurement mode............................................................................................................ 79
8.3.4 Frequency Measurement mode .............................................................................................................. 80
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.3.1 8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 89
9.3.2 8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 90
9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 90
9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 93
9.3.5 16-Bit Timer Mode (TC3 and 4) .............................................................................................................. 95
9.3.6 16-Bit Event Counter Mode (TC3 and 4) ................................................................................................ 96
9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4).......................................................... 96
9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................... 99
9.3.9 Warm-Up Counter Mode....................................................................................................................... 101
9.3.9.1 Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
9.3.9.2 High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
10.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.3 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.3.1 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 108
10.3.2 8-Bit Event Counter Mode (TC6) ........................................................................................................ 109
10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC6)..................................................................... 109
10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6).................................................................. 112
10.3.5 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 114
10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 115
10.3.7 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... 118
10.3.8 Warm-Up Counter Mode..................................................................................................................... 120
11. Asynchronous Serial interface (UART )
11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.3 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.4 Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.5 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.6 STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.7 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.8 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.8.1 Data Transmit Operation .................................................................................................................... 128
iii
11.8.2 Data Receive Operation ..................................................................................................................... 128
11.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.9.1 Parity Error.......................................................................................................................................... 129
11.9.2 Framing Error...................................................................................................................................... 129
11.9.3 Overrun Error ...................................................................................................................................... 129
11.9.4 Receive Data Buffer Full..................................................................................................................... 130
11.9.5 Transmit Data Buffer Empty ............................................................................................................... 130
11.9.6 Transmit End Flag .............................................................................................................................. 131
12. Synchronous Serial Interface (SIO)
12.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.3 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.3.1 Clock source ....................................................................................................................................... 135
12.3.1.1 Internal clock
12.3.1.2 External clock
12.3.2 Shift edge............................................................................................................................................ 137
12.3.2.1 Leading edge
12.3.2.2 Trailing edge
12.4 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.5 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.6 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 138
12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 140
12.6.3 8-bit transfer / receive mode ............................................................................................................... 141
13. 10-bit AD Converter (ADC)
13.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.2 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
13.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
13.3.1 Software Start Mode ........................................................................................................................... 147
13.3.2 Repeat Mode ...................................................................................................................................... 147
13.3.3 Register Setting ................................................................................................................................ 148
13.4 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.5 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 150
13.6 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
13.6.1 Analog input pin voltage range ........................................................................................................... 151
13.6.2 Analog input shared pins .................................................................................................................... 151
13.6.3 Noise Countermeasure ....................................................................................................................... 151
14. Key-on Wakeup (KWU)
14.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

14.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.3 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15. LCD Driver
15.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.2.1 LCD driving methods .......................................................................................................................... 157
iv
15.2.2 Frame frequency................................................................................................................................. 158
15.2.3 Driving method for LCD driver ............................................................................................................ 159
15.2.3.1 When using the booster circuit (LCDCR<BRES>="1")
15.2.3.2 When using an external resistor divider (LCDCR<BRES>="0")
15.3 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.3.1 Display data setting ............................................................................................................................ 161
15.3.2 Blanking .............................................................................................................................................. 162
15.4 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.4.1 Initial setting ........................................................................................................................................ 163
15.4.2 Store of display data ........................................................................................................................... 163
15.4.3 Example of LCD drive output .............................................................................................................. 166
16. Input/Ouput Circuitry
16.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

16.2 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
17. Electrical Characteristics
17.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

17.2 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
17.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17.4 AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
17.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.6 Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.6 .............................................................. 178
17.6 ............................................................................................................................................................... 178
17.6 ............................................................................................................................................................... 178
17.7 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.8 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
18. Package Dimension
This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).
v
vi
TMP86CM29LUG
CMOS 8-Bit Microcontroller
TMP86CM29LUG
ROM
Product No. RAM Package FLASH MCU Emulation Chip
(MaskROM)
32768 1536
TMP86CM29LUG P-LQFP64-1010-0.50D TMP86FM29UG TMP86C929XB
bytes bytes
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 19interrupt sources (External : 5 Internal : 14)
3. Input / Output ports (39 pins)
4. Watchdog Timer
5. Prescaler
- Time base timer
- Divider output function
6. 18-bit Timer/Counter : 1ch
- Timer Mode
- Event Counter Mode
- Pulse Width Measurement Mode
- Frequency Measurement Mode
7. 8-bit timer counter : 4 ch
- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
Programmable pulse generation (PPG) modes
8. 8-bit UART/SIO : 1 ch
060116EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equip-
ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instru-
ments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli-
cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
Page 1
1.1 Features
TMP86CM29LUG
9. 10-bit successive approximation type AD converter

- Analog input: 8 ch
10. Key-on wakeup : 4 ch
11. LCD driver/controller
Built-in voltage booster for LCD driver With display memory
LCD direct drive capability (MAX 32 seg × 4 com)
1/4,1/3,1/2duties or static drive are programmably selectable
12. Clock operation
Single clock mode
Dual clock mode
13. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-
quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-
puts(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-
ruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-
quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-
put.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by
interruput.
14. Wide operation voltage:
2.7 V to 3.6 V at 16MHz /32.768 kHz
1.8 V to 3.6 V at 8 MHz /32.768 kHz
Page 2
TMP86CM29LUG
1.2 Pin Assignment
P73 (SEG12)
P72 (SEG13)
P71 (SEG14)
P70 (SEG15)
P57 (SEG16)
P56 (SEG17)
P55 (SEG18)
P75 (SEG10)
P74 (SEG11)
P77 (SEG8)
P76 (SEG9)
SEG3
SEG4
SEG5
SEG6
SEG7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG2 49 32 P54(SEG19)
SEG1 50 31 P53(SEG20)
SEG0 51 30 P52(SEG21)
COM3 52 29 P51(SEG22)
COM2 53 28 P50(SEG23)
COM1 54 27 P17(SEG24/SCK)
COM0 55 26 P16(SEG25/TXD/SO)
V3 56 25 P15(SEG26/RXD/SI)
V2 57 24 P14(SEG27/INT3)
V1 58 23 P13(SEG28/INT2)
C1 59 22 P12(SEG29/INT1)
C0 60 21 P11(SEG30)
(DVO) P30 61 20 P10(SEG31)
(TC3/PDO3/PWM3) P31 62 19 AVDD
(TC4/PDO4/PWM4/PPG4) P32 63 18 VAREF
(TC6/PDO6/PWM6/PPG6) P33 64 17 P67(AIN7/STOP5)
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
TEST
RESET
XIN
XOUT
VDD
(XTIN) P21
(ECNT/AIN2) P62
(INT0/AIN3) P63
(STOP2/AIN4) P64
(STOP3/AIN5) P65
(STOP4/AIN6) P66
VSS
(XTOUT) P22
(STOP/INT5) P20
(AIN0) P60
(ECIN/AIN1) P61
Figure 1-1 Pin Assignment
Page 3
1.3 Block Diagram
TMP86CM29LUG
1.3 Block Diagram
Figure 1-2 Block Diagram
Page 4
TMP86CM29LUG
1.4 Pin Names and Functions
Table 1-1 Pin Names and Functions(1/3)
Pin Name Pin Number Input/Output Functions
P17 IO PORT17
SEG24 27 O LCD segment output 24
SCK IO Serial Clock I/O
P16 IO PORT16
SEG25 O LCD segment output 25
26
TXD O UART data output
SO O Serial Data Output
P15 IO PORT15
25
RXD I UART data input
SI I Serial Data Input
P14 IO PORT14
INT3 I External interrupt 3 input
P13 IO PORT13
SEG28 23 I LCD segment output 28
P12 IO PORT12
P11 IO PORT11
21
P10 IO PORT10
20
PORT22
P22 IO
7 Resonator connecting pins(32.768kHz) for inputting external
XTOUT O
clock
PORT21
P21 IO
6 Resonator connecting pins(32.768kHz) for inputting external
XTIN I
clock
P20 IO PORT20
INT5 9 I External interrupt 5 input
STOP I STOP mode release signal input
P33 IO PORT33
PDO6/PWM6/PPG6 64 O PDO6/PWM6/PPG6 output
TC6 I TC6 input
P32 IO PORT32
PDO4/PWM4/PPG4 63 O PDO4/PWM4/PPG4 output
TC4 I TC4 input
P31 IO PORT31
PDO3/PWM3 62 O PDO3/PWM3 output
TC3 I TC3 input
P30 IO PORT30
61
DVO O Divider Output
P57 IO PORT57
35
P56 IO PORT56
34
Page 5
TMP86CM29LUG
P55 IO PORT55
33
P54 IO PORT54
32
P53 IO PORT53
31
P52 IO PORT52
30
P51 IO PORT51
29
P50 IO PORT50
28
P67 IO PORT67
AIN7 17 I Analog Input7
STOP5 I STOP5 input
P66 IO PORT66
STOP4 I STOP4 input
P65 IO PORT65
STOP3 I STOP3 input
P64 IO PORT64
STOP2 I STOP2 input
P63 IO PORT63
P62 IO PORT62
ECNT I ECNT input
P61 IO PORT61
ECIN I ECIN input
P60 IO PORT60
10
AIN0 I Analog Input0
P77 IO PORT77
43
P76 IO PORT76
42
P75 IO PORT75
41
P74 IO PORT74
40
P73 IO PORT73
39
P72 IO PORT72
38
P71 IO PORT71
37
Page 6
TMP86CM29LUG
P70 IO PORT70
36
COM3 52 O LCD common output 3
V3 56 I LCD voltage booster pin
C1 59 I LCD voltage booster pin
C0 60 I LCD voltage booster pin
XIN 2 I Resonator connecting pins for high-frequency clock
XOUT 3 O Resonator connecting pins for high-frequency clock
RESET 8 IO Reset signal
TEST 4 I Test pin for out-going test. Normally, be fixed to low.
VAREF 18 I Analog Base Voltage Input Pin for A/D Conversion
AVDD 19 I Analog Power Supply
VDD 5 I Power Supply
VSS 1 I 0(GND)
Page 7
TMP86CM29LUG
Page 8
TMP86CM29LUG
2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1 Memory Address Map

The TMP86CM29LUG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Spe-
cial function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CM29LUG
memory address map.
0000H SFR: Special function register includes:

SFR 64 bytes I/O ports
003FH Peripheral control registers
0040H Peripheral status registers
System control registers
1536 Program status word
RAM Random access memory includes:
bytes RAM:
Data memory
063FH Stack
0F80H DBR: Data buffer register includes:

128 Peripheral control registers
DBR
bytes Peripheral status registers
0FFFH LCD display memory
8000H MaskROM: Program memory
32768
MaskROM
bytes
FFC0H
Vector table for vector call instructions
FFDFH (32 bytes)
FFE0H
Vector table for interrupts
FFFFH (32 bytes)
Figure 2-1 Memory Address Map
2.1.2 Program Memory (MaskROM)

The TMP86CM29LUG has a 32768 bytes (Address 8000H to FFFFH) of program memory (MaskROM ).
2.1.3 Data Memory (RAM)

The TMP86CM29LUG has 1536bytes (Address 0040H to 063FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.
Page 9
2.2 System Clock Controller
TMP86CM29LUG
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86CM29LUG)

LD HL, 0040H ; Start address setup
LD A, H ; Initial value (00H) setup
LD BC, 05FFH
SRAMCLR: LD (HL), A
INC HL
DEC BC
JRS F, SRAMCLR

The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register

TBTCR
Clock
0036H
generator
XIN fc
High-frequency Timing Standby controller
clock oscillator generator
XOUT 0038H 0039H
XTIN SYSCR1 SYSCR2
fs
Low-frequency System control registers
clock oscillator System clocks
XTOUT
Clock generator control
Figure 2-2 System Colck Control
2.2.1 Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 10
TMP86CM29LUG
High-frequency clock Low-frequency clock
XIN XOUT XIN XOUT XTIN XTOUT XTIN XTOUT
(Open) (Open)
(a) Crystal/Ceramic (b) External oscillator (c) Crystal (d) External oscillator
resonator
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis-
abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjust-
ment in advance.
Page 11
TMP86CM29LUG
2.2.2 Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock

2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
7. Generation of base clocks for LCD
2.2.2.1 Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
Main system clock generator fc or fs Machine cycle counters
SYSCK
DV7CK
S Divider
A
High-frequency fc/4 Y
1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
clock fc B
Low-frequency Multi- S Multiplexer

clock fs plexer B0
B1
A0 Y0
A1 Y1 Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
Page 12
TMP86CM29LUG
Timing Generator Control Register
TBTCR 7 6 5 4 3 2 1 0
(0036H) (DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000)
Selection of input to the 7th stage 0: fc/28 [Hz]

DV7CK R/W
of the divider 1: fs
Note 1: In single clock mode, do not set DV7CK to “1”.

Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2 Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State S0 S1 S2 S3 S0 S1 S2 S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3 Operation Mode Control Circuit

The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). To keep compatibility with flash produc, even though the TMP86CM29LUG doesn’t have flash
memory, it has flash memory control register which applies CPU wait period for stability of power supply. Fig-
ure 2-6 shows the operating mode transition diagram.
Note 1: When the IDLE0/1/2 and SLEEP0/1/2 modes are started with the EEPCR<ATPWDW> = "0", the CPU wait
period for stabilizing of the power supply of Flash control circuit is executed after being released from these
mode.
Note 2: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for stablizing of
the power supply of flash control circuit is executed after the STOP warm-up time. This function is also
included in masked ROM product (TMP86CM29LUG) for keeping compatibility with flash product. For
details, please refer to a data sheet of flash product.
Page 13
TMP86CM29LUG
2.2.3.1 Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1) NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86CM29LUG is placed in this mode after reset.
(2) IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3) IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-
cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2 Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the low-
frequency oscillator should be turned on at the start of a program.
(1) NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
Page 14
TMP86CM29LUG
(2) SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hard-
ware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3) SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-fre-
quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4) IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5) SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how-
ever, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releas-
ing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6) SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-
frequency clock.
(7) SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-
cessing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
Page 15
TMP86CM29LUG
2.2.3.3 STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
IDLE0
mode Reset release RESET
SYSCR2<TGHALT> = "1" Note 2

SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1"
IDLE1 NORMAL1
mode mode
Interrupt STOP pin input
(a) Single-clock mode SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1"

IDLE2 NORMAL2
mode mode
SYSCR2<SYSCK> = "0" SYSCR2<SYSCK> = "1"
STOP
SYSCR2<IDLE> = "1"
SLEEP2 SLOW2
mode mode
Interrupt
SYSCR2<XEN> = "1" SYSCR2<XEN> = "0"

SLEEP1 SLOW1
mode mode
(b) Dual-clock mode
Note 2 SYSCR2<TGHALT> = "1"
SLEEP0
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Page 16
TMP86CM29LUG
Table 2-1 Operating Mode and Conditions

Oscillator
Other Machine Cycle
Operating Mode High Low CPU Core TBT
Peripherals Time
Frequency Frequency
RESET Reset Reset Reset
NORMAL1 Operate
Oscillation Operate 4/fc [s]
Single clock IDLE1 Stop Operate
IDLE0 Halt
Halt
STOP Stop Halt –
Operate with
NORMAL2
high frequency 4/fc [s]
IDLE2 Halt
Oscillation
Operate with
SLOW2
low frequency Operate
Oscillation Operate
Dual clock SLEEP2 Halt
Operate with 4/fs [s]

SLOW1
low frequency
SLEEP1 Stop
SLEEP0 Halt
Halt
STOP Stop Halt –
Page 17
TMP86CM29LUG
System Control Register 1

SYSCR1 7 6 5 4 3 2 1 0
(0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 00**)
0: CPU core and peripherals remain active

STOP STOP mode start R/W
1: CPU core and peripherals are halted (Start STOP mode)
Release method for STOP 0: Edge-sensitive release

RELM R/W
mode 1: Level-sensitive release
Operating mode after STOP 0: Return to NORMAL1/2 mode

RETM R/W
mode 1: Return to SLOW1 mode
0: High impedance
OUTEN Port output during STOP mode R/W
1: Output kept
Return to NORMAL mode Return to SLOW mode
00 3 x 216/fc + (210/fc) 3 x 213/fs + (23/fs)

Warm-up time at releasing
WUT 01 216/fc + (210/fc) 213/fs + (23/fs) R/W
STOP mode
10 3 x 214/fc + (210/fc) 3 x 26/fs + (23/fs)
11 214/fc + (210/fc) 26/fs + (23/fs)
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
Note 9: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for stabilizing of the power sup-
ply of flash control circuit is executed after the STOP warm-up time. This CPU wait function is included in masked ROM
product (TMP86CM29LUG) for keeping compatibility with flash product. (The CPU wait period for FLASH is shown in
parentheses)
System Control Register 2
SYSCR2 7 6 5 4 3 2 1 0
(0039H) XEN XTEN SYSCK IDLE TGHALT (Initial value: 1000 *0**)
0: Turn off oscillation

XEN High-frequency oscillator control
1: Turn on oscillation
0: Turn off oscillation

XTEN Low-frequency oscillator control
1: Turn on oscillation R/W
Main system clock select

0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
SYSCK (Write)/main system clock moni-
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
tor (Read)
CPU and watchdog timer control 0: CPU and watchdog timer remain active
IDLE
(IDLE1/2 and SLEEP1/2 modes) 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
0: Feeding clock to all peripherals from TG R/W

TG control (IDLE0 and SLEEP0
TGHALT 1: Stop feeding clock to peripherals except TBT from TG.
modes)
(Start IDLE0 and SLEEP0 modes)
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Page 18
TMP86CM29LUG
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
2.2.4 Operating Mode Control
2.2.4.1 STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releas-
ing STOP mode in edge-sensitive mode.
When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait for stabilizing of
the power supply of flash control circuit is executed after the STOP warm-up time. This CPU wait func-
tion is also included in masked ROM product (TMP86CM29LUG) for keeping compatibility with flash
product.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).
However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1) Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2
pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main
power supply is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5
to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immedi-
ately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to
first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two
methods can be used for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Page 19
TMP86CM29LUG
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode
SSTOPH: TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level
JRS F, SSTOPH
DI ; IMF ← 0
SET (SYSCR1). 7 ; Starts STOP mode
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if
JRS F, SINT5 port P20 is at high
LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode.
DI ; IMF ← 0
SET (SYSCR1). 7 ; Starts STOP mode
SINT5: RETI
Only when EEPCR<MNPWDW> is “1”.

(The CPU wait period is added.)
VIH
STOP pin
XOUT pin
NORMAL operation STOP operation Warm up CPU NORMAL operation

Confirm by program that the Wait
STOP pin input is low and start STOP mode is released by the hardware.
STOP mode. Always released if the STOP
pin input is high.
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
Note 3: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for
stablizing of the power supply of flash control circuit is executed after the STOP warm-up time.
This function is also included in masked ROM product (TMP86CM29LUG) for keeping compati-
bility with flash product.
(2) Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in appli-
cations where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.
Example :Starting STOP mode from NORMAL mode

DI ; IMF ← 0
LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode
Page 20
TMP86CM29LUG
Only when EEPCR<MNPWDW> is “1”.

(The CPU wait period is added.)
STOP pin VIH
XOUT pin
NORMAL operation STOP operation Warm up CPU NORMAL STOP operation

Wait operation
STOP mode started
by the program.
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 2-8 Edge-sensitive Release Mode
Note 1: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for
stablizing of the power supply of flash control circuit is executed after the STOP warm-up time.
This function is also included in masked ROM product (TMP86CM29LUG) for keeping compati-
bility with flash product.
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low-
frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low-
frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the EEPCR<MNPWDW> is "1", the CPU wait period is inserted to stabilize the
power supply of flash control circuit. During CPU wait, though CPU operations remain
halted, the peripheral function operation is resumed, and the counting of the timing genera-
tor is restarted. After the CPU wait is finished, normal operation resumes with the instruc-
tion following the STOP mode start instruction.
4. When the EEPCR<MNPWDW> is "0", normal operation resumes with the instruction fol-
lowing the STOP mode start instruction after the STOP warm up.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms]

WUT
Return to NORMAL Mode Return to SLOW Mode
00 12.288 + (0.064) 750 + (0.244)

01 4.096 + (0.064) 250 + (0.244)
10 3.072 + (0.064) 5.85 + (0.244)
11 1.024 + (0.064) 1.95 + (0.244)
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Page 21
Turn off
Oscillator
circuit Turn on
Main
system
clock
Program
counter a+2 a+3
Instruction Halt
execution SET (SYSCR1). 7
Divider n n+1 n+2 n+3 n+4 0
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
Warm up
Page 22
STOP pin
input
Oscillator Turn off Turn on

circuit
Main
system
Note 2: The CPU wait period for FLASH is shown in parentheses.
clock
Program a+3 a+4 a+5 a+6
counter
Halt
Instruction Instruction address a + 2 Instruction address a + 3 Instruction address a + 4
execution
0 Count up 0 1 2 3
Divider
(b) STOP mode release
Figure 2-9 STOP Mode Start/Release (when EEPCR<MNPWDW> = "0")

TMP86CM29LUG
Turn off
Oscillator
circuit Turn on
Main
system
clock
Program
counter a+2 a+3
Instruction Halt
Divider n n+1 n+2 n+3 n+4 0
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
Page 23
Warm up CPU Wait
STOP pin
input
Oscillator Turn off Turn on

circuit
Main
system
clock
Program a+3 a+4 a+5
counter
Halt
Instruction Instruction address a + 2 Instruction address a + 3
execution
0 Count up 0 1 m m+1 m+2

Divider
The counting of divider is restarted.
Figure 2-10 STOP Mode Start/Release (when EEPCR<MNPWDW> = "1")

(b) STOP mode release
TMP86CM29LUG
TMP86CM29LUG
2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and

SLEEP1/2 modes by
instruction
CPU and WDT are halted
Yes
Reset input Reset
No
No
Interrupt request
Yes
“1”
EEPCR<ATPWDW>
“0”
CPU Wait
“0”
IMF
Normal “1” (Interrupt release mode)

release mode
Interrupt processing
Execution of the instruc-

tion which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-11 IDLE1/2 and SLEEP1/2 Modes
Note 1: EEPCR<ATPWDW> is a bit1 in EEPCR, which is a control bit of the power supply circuit for flash.
Note 2: During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed.
Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until
the CPU wait is finished.
Page 24
TMP86CM29LUG
• Start the IDLE1/2 and SLEEP1/2 modes

After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes

IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
When the IDLE1/2 and SLEEP1/2 modes are started with the EEPCR<ATPWDW> = "0", the
CPU wait period for stabilizing of the power supply of flash control circuit is added before the
operation mode is returned to the preceding modes. The CPU wait time of IDLE1/2 is 210/fc [s]
and that of SLEEP1/2 mode is 23/fs [s].
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
(1) Normal release mode (IMF = “0”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual
interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the
instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt
latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.
(2) Interrupt release mode (IMF = “1”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2
and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
Page 25
Main
system
clock
Interrupt
request
Program a+3
counter a+2
Instruction Halt
SET (SYSCR2). 4
execution
Watchdog Operate
timer
(a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a)
Main
system
clock
Interrupt
request
Program
counter a+3 a+4
Instruction Halt
Instruction address a + 2
Page 26
execution
Watchdog Halt
timer Operate
㽲㩷Normal release mode
Main
system
clock
Interrupt
request
Program a+3
counter
Halt
Instruction Acceptance of interrupt
execution
Watchdog Halt
Operate
Operate
timer
㽳㩷Interrupt release mode
(b) IDLE1/2 and SLEEP1/2 modes release

TMP86CM29LUG
Figure 2-12 IDLE1/2 and SLEEP1/2 Modes Start/Release (when EEPCR<ATPWDW> = "1")
TMP86CM29LUG
2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
1. Timing generator stops feeding clock to peripherals except TBT.

2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before IDLE0 and SLEEP0 modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
Page 27
TMP86CM29LUG
Stopping peripherals
by instruction
Starting IDLE0, SLEEP0

modes by instruction
CPU and WDT are halted
Yes
Reset input Reset
No
TBT
No source clock
falling
edge
Yes
“1”
EEPCR<ATPWDW>
“0”
CPU Wait
No TBTCR<TBTEN>
= "1"
Yes
No TBT interrupt
enable
Yes
(Normal release mode)
“0”
IMF
“1” (Interrupt release mode)
Interrupt processing
Execution of the instruction

which follows the IDLE0,
SLEEP0 modes start
instruction
Figure 2-13 IDLE0 and SLEEP0 Modes
Note 1: EEPCR<ATPWDW> is a bit1 in EEPCR, which is a control bit of the power supply circuit for flash.
Note 2: During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed.
Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until
the CPU wait is finished.
Page 28
TMP86CM29LUG
• Start the IDLE0 and SLEEP0 modes

Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes

IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag
of TBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”,
INTTBT interrupt latch is set to “1”.
When the IDLE0 and SLEEP0 modes are started with the EEPCR<ATPWDW> = "0", the CPU
wait period for stabilizing of the power supply of flash control circuit is added before the oper-
ation mode is returned to the preceding modes. The CPU wait time of IDLE0 is 210/fc [s] and
that of SLEEP0 mode is 23/fs [s].
IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting.
(1) Normal release mode (IMF•EF6•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the
instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
(2) Interrupt release mode (IMF•EF6•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchro-
nous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period set-
ting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is
started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be
started.
Page 29
Main
system
clock
Interrupt
request
Program
a+2 a+3
counter
Instruction Halt
Watchdog
timer Operate
(a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a
Main
system
clock
TBT clock
Program
counter a+3 a+4
Instruction Halt
Page 30
execution Instruction address a + 2
Watchdog Halt
timer Operate
㽲㩷Normal release mode
Main
system
clock
TBT clock
Program a+3
counter
Instruction Halt
Acceptance of interrupt
execution
Watchdog Halt
timer Operate
㽳㩷Interrupt release mode

TMP86CM29LUG
(b) IDLE and SLEEP0 modes release
Figure 2-14 IDLE0 and SLEEP0 Modes Start/Release (when EEPCR<ATPWDW> = "1")
TMP86CM29LUG
2.2.4.4 SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).

The following is the methods to switch the mode with the warm-up counter.
(1) Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for
SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before per-
forming the above operations. The timer/counter (TC4,TC3) can conveniently be used to confirm
that low-frequency clock oscillation has stabilized.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.

SET (SYSCR2). 5 ; SYSCR2<SYSCK> ← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR (SYSCR2). 7 ; SYSCR2<XEN> ← 0

(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET (SYSCR2). 6 ; SYSCR2<XTEN> ← 1
LD (TC3CR), 43H ; Sets mode for TC4, 3 (16-bit mode, fs for source)
LD (TC4CR), 05H ; Sets warming-up counter mode
LDW (TTREG3), 8000H ; Sets warm-up time (Depend on oscillator accompanied)
DI ; IMF ← 0
SET (EIRH). 3 ; Enables INTTC4
EI ; IMF ← 1
SET (TC4CR). 3 ; Starts TC4, 3
PINTTC4: CLR (TC4CR). 3 ; Stops TC4, 3
SET (SYSCR2). 5 ; SYSCR2<SYSCK> ← 1

(Switches the main system clock to the low-frequency clock)
CLR (SYSCR2). 7 ; SYSCR2<XEN> ← 0

(Turns off high-frequency oscillation)
RETI
VINTTC4: DW PINTTC4 ; INTTC4 vector table
Page 31
TMP86CM29LUG
(2) Switching from SLOW1 mode to NORMAL2 mode
First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization
(Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the
main system clock to the high-frequency clock.
SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the
operation mode is started from NORMAL1 mode.
Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock
for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
SET (SYSCR2). 7 ; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation)
LD (TC3CR), 63H ; Sets mode for TC4, 3 (16-bit mode, fc for source)
LD (TC4CR), 05H ; Sets warming-up counter mode
LD (TTREG4), 0F8H ; Sets warm-up time
DI ; IMF ← 0
SET (EIRH). 3 ; Enables INTTC4
EI ; IMF ← 1
SET (TC4CR). 3 ; Starts TC4, 3
PINTTC4: CLR (TC4CR). 3 ; Stops TC4, 3
CLR (SYSCR2). 5 ; SYSCR2<SYSCK> ← 0

(Switches the main system clock to the high-frequency clock)
RETI
VINTTC4: DW PINTTC4 ; INTTC4 vector table
Page 32
High-
frequency Turn off
clock
Low-
frequency
clock
Main
system
clock
SYSCK
XEN
Instruction CLR (SYSCR2). 7

SLOW2 mode
NORMAL2 SLOW1 mode
mode
(a) Switching to the SLOW mode
Page 33
High-
frequency
clock
Low-
frequency
clock
Main
system
clock
SYSCK
XEN
Instruction
execution SET (SYSCR2). 7 CLR (SYSCR2). 5
Figure 2-15 Switching between the NORMAL2 and SLOW Modes

Warm up during SLOW2 mode
SLOW1 mode NORMAL2
mode
(b) Switching to the NORMAL2 mode
TMP86CM29LUG
2.3 Reset Circuit
TMP86CM29LUG
2.3 Reset Circuit

The TMP86CM29LUG has four types of reset generation procedures: An external reset input, an address trap
reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and
the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during
the maximum 24/fc[s] (The RESET pin outputs "L" level).
Also a reset circuit has an 11-stage counter for generation of flash reset, and the flash reset occurs immediately after
the malfunction reset and the external reset operation. The flash reset period is 210/fc [s] (64µs at 16.0MHz). RESET
pin becomes "H" level while the flash reset occurs.
Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5µs at 16.0MHz).
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
ized when power is turned on. Therefore, reset may occur during maximum 24/fc + 210/fc[s] (65.5µs at 16.0 MHz)
when power is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz).
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware Initial Value On-chip Hardware Initial Value
Program counter (PC) (FFFEH)
Stack pointer (SP) Not initialized

Prescaler and divider of timing generator 0
General-purpose registers
Not initialized
(W, A, B, C, D, E, H, L, IX, IY)
Jump status flag (JF) Not initialized Watchdog timer Enable
Zero flag (ZF) Not initialized
Carry flag (CF) Not initialized
Half carry flag (HF) Not initialized

Output latches of I/O ports Refer to I/O port circuitry
Sign flag (SF) Not initialized
Overflow flag (VF) Not initialized
Interrupt master enable flag (IMF) 0
Interrupt individual enable flags (EF) 0 Refer to each of control

Control registers
Interrupt latches (IL) 0 register
LCD data buffer Not initialized
RAM Not initialized
2.3.1 External Reset Input

The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-
ized.
When the high level goes on during 210/fc[s] (65.5µs at 16MHz) after the RESET pin input goes high, the
reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to
FFFFH.
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TMP86CM29LUG
VDD
Flash reset counter
RESET Internal reset
Watchdog timer reset

Malfunction
reset output Address trap reset
circuit
System clock reset
Figure 2-16 Reset Circuit
2.3.2 Address trap reset

If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc + 210/fc[s] (65.5µs at 16.0 MHz). Then, the RESET pin outputs "L"
level during maximum 24/fc[s].
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-
native.
Instruction JP a Reset release Instruction at address r

execution
Address trap is occurred
("L" output)
RESET output
Maximum 24/fc [s] 210/fc [s] 4/fc to 12/fc [s] 16/fc [s]
Note 3
Internal reset
signal
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Note 3: Varies on account of external condition: voltage or capacitance
Figure 2-17 Address Trap Reset
2.3.3 Watchdog timer reset

Refer to Section “Watchdog Timer”.
2.3.4 System clock reset

If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
CPU. (The oscillation is continued without stopping.)
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
The flash reset occurs immediately after the system clock reset operation. The reset time is maximum 24/fc +
210/fc (65.5 µs at 16.0 MHz). Then, the RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at
16.0MHz).
Page 35
2.3 Reset Circuit
TMP86CM29LUG
Page 36
TMP86CM29LUG
The TMP86CM29LUG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multi-
plexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest
are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Vector
Interrupt Factors Enable Condition Priority
Latch Address
Internal/External (Reset) Non-maskable – FFFE 1
Internal INTSWI (Software interrupt) Non-maskable – FFFC 2
INTUNDEF (Executed the undefined instruction

Internal Non-maskable – FFFC 2
interrupt)
Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2
Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2
External INT0 IMF• EF4 = 1, INT0EN = 1 IL4 FFF6 5
External INT1 IMF• EF5 = 1 IL5 FFF4 6
Internal INTTBT IMF• EF6 = 1 IL6 FFF2 7
External INT2 IMF• EF7 = 1 IL7 FFF0 8
Internal INTTC1 IMF• EF8 = 1 IL8 FFEE 9
Internal INTRXD IMF• EF9 = 1, IL9ER = 0 IL9 FFEC 10
Internal INTSIO IMF• EF9 = 1, IL9ER = 1
Internal INTTXD IMF• EF10 = 1 IL10 FFEA 11
Internal INTTC4 IMF• EF11 = 1 IL11 FFE8 12
Internal INTTC6 IMF• EF12 = 1 IL12 FFE6 13
Internal INTADC IMF• EF13 = 1 IL13 FFE4 14
External INT3 IMF• EF14 = 1, IL14ER = 0 IL14 FFE2 15
Internal INTTC3 IMF• EF14 = 1, IL14ER = 1
External INT5 IMF• EF15 = 1, IL15ER = 0 IL15 FFE0 16
Internal INTTC5 IMF• EF15 = 1, IL15ER = 1
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inter-
rupt Source Selector (INTSEL)).
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
3.1 Interrupt latches (IL15 to IL2)

An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" indi-
vidually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter-
rupt is requested while such instructions are executed.
Page 37
3.2 Interrupt enable register (EIR)
TMP86CM29LUG
Interrupt latches are not set to “1” by an instruction.

Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
Example 1 :Clears interrupt latches

DI ; IMF ← 0
LDW (ILL), 1110100000111111B ; IL12, IL10 to IL6 ← 0
EI ; IMF ← 1
Example 2 :Reads interrupt latchess

LD WA, (ILL) ; W ← ILH, A ← ILL
Example 3 :Tests interrupt latches

TEST (ILL). 7 ; if IL7 = 1 then jump
JR F, SSET

The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-
maskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1 Interrupt master enable flag (IMF)

The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter-
rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-
ized to “0”.
3.2.2 Individual interrupt enable flags (EF15 to EF4)

Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis-
ables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-
Page 38
TMP86CM29LUG
mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat-
ing EF or IL should be executed before setting IMF="1".
Example 1 :Enables interrupts individually and sets IMF

DI ; IMF ← 0
LDW (EIRL), 1110100010100000B ; EF15 to EF13, EF11, EF7, EF5 ← 1

: Note: IMF should not be set.
EI ; IMF ← 1
Example 2 :C compiler description example

unsigned int _io (3AH) EIRL; /* 3AH shows EIRL address */
_DI();
EIRL = 10100000B;
_EI();
Page 39
TMP86CM29LUG
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(003DH, 003CH) IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2
ILH (003DH) ILL (003CH)
at RD at WR
IL15 to IL2 Interrupt latches 0: No interrupt request 0: Clears the interrupt request R/W
1: Interrupt request 1: (Interrupt latch is not set.)
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers

(Initial value: 00000000 0000***0)
EIRH,EIRL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(003BH, 003AH) EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 EF7 EF6 EF5 EF4 IMF
EIRH (003BH) EIRL (003AH)
Individual-interrupt enable flag 0: Disables the acceptance of each maskable interrupt.

EF15 to EF4
(Specified for each bit) 1: Enables the acceptance of each maskable interrupt.
R/W
0: Disables the acceptance of all maskable interrupts
IMF Interrupt master enable flag
1: Enables the acceptance of all maskable interrupts
Note 1: *: Don’t care

Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
Page 40
TMP86CM29LUG
3.3 Interrupt Source Selector (INTSEL)

Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the
interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt
requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL reg-
ister must be set appropriately before interrupt requests are generated.
The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL.
1. INTRXD and INTSIO share the interrupt source level whose priority is 10.
2. INT3 and INTTC3 share the interrupt source level whose priority is 15.
3. INT5 and INTTC5 share the interrupt source level whose priority is 16.
Interrupt source selector
INTSEL 7 6 5 4 3 2 1 0
(003EH) - IL9ER - - - - IL14ER IL15ER (Initial value: *0** **00)
0: INTRXD
IL9ER Selects INTRXD or INTSIO R/W
1: INTSIO
0: INT3
IL14ER Selects INT3 or INTTC3 R/W
1: INTTC3
0: INT5
IL15ER Selects INT5 or INTTC5 R/W
1: INTTC5
3.4 Interrupt Sequence

An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
3.4.1 Interrupt acceptance processing is packaged as follows.

a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-
lowing interrupt.
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-
while, the stack pointer (SP) is decremented by 3.
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec-
tor table, is transferred to the program counter.
e. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
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TMP86CM29LUG
Interrupt service task

1-machine cycle
Interrupt
request
Interrupt
latch (IL)
IMF
Execute Execute Execute

instruction instruction Interrupt acceptance instruction Execute RETI instruction
PC a−1 a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2
SP n n−1 n−2 n-3 n−2 n−1 n
Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address Entry address
FFF2H 03H D203H 0FH Interrupt

Vector service
FFF3H D2H D204H 06H program
Figure 3-2 Vector table address,Entry address
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
level of current servicing interrupt is requested.
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
3.4.2 Saving/restoring general-purpose registers

During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using
the same data memory area for saving registers. The following methods are used to save/restore the general-
purpose registers.
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TMP86CM29LUG
3.4.2.1 Using PUSH and POP instructions
If only a specific register is saved or interrupts of the same source are nested, general-purpose registers
can be saved/restored using the PUSH/POP instructions.
Example :Save/store register using PUSH and POP instructions

PINTxx: PUSH WA ; Save WA register
(interrupt processing)
POP WA ; Restore WA register
RETI ; RETURN
Address
(Example)
SP b-5
A b-4
SP W SP b-3
PCL PCL PCL b-2
PCH PCH PCH b-1
PSW PSW PSW SP b
At acceptance of At execution of At execution of At execution of

an interrupt PUSH instruction POP instruction RETI instruction
Figure 3-3 Save/store register using PUSH and POP instructions
3.4.2.2 Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Example :Save/store register using data transfer instructions

PINTxx: LD (GSAVA), A ; Save A register
LD A, (GSAVA) ; Restore A register
RETI ; RETURN
Page 43
TMP86CM29LUG
Main task
Interrupt Interrupt
acceptance service task
Saving
registers
Restoring
registers
Interrupt return
Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.4.3 Interrupt return

Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word

(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Example 1 :Returning from address trap interrupt (INTATRAP) service program

PINTxx: POP WA ; Recover SP by 2
LD WA, Return Address ;
PUSH WA ; Alter stacked data
RETN ; RETURN
Example 2 :Restarting without returning interrupt

(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx: INC SP ; Recover SP by 3
INC SP ;
INC SP ;
LD EIRL, data ; Set IMF to “1” or clear it to “0”
JP Restart Address ; Jump into restarting address
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-
rupt can be accepted immediately after the interrupt return instruction is executed.
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TMP86CM29LUG
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-
rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.5 Software Interrupt (INTSW)

Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.5.1 Address error detection

FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-
ated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
3.5.2 Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
3.6 Undefined Instruction Interrupt (INTUNDEF)

Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-
erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-
rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
(SWI) does.
3.7 Address Trap Interrupt (INTATRAP)

Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-
cess is broken and INTATRAP interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
watchdog timer control register (WDTCR).
3.8 External Interrupts

The TMP86CM29LUG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external inter-
rupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt
control register (EINTCR).
Page 45
TMP86CM29LUG
Source Pin Enable Conditions Release Edge Digital Noise Reject
Pulses of less than 2/fc [s] are eliminated as

noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
INT0 INT0 IMF EF4 INT0EN=1 Falling edge
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Pulses of less than 15/fc or 63/fc [s] are elimi-

nated as noise. Pulses of 49/fc or 193/fc [s] or
Falling edge
more are considered to be signals. In the SLOW
INT1 INT1 IMF EF5 = 1 or
or the SLEEP mode, pulses of less than 1/fs [s]
Rising edge
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.

Falling edge
INT2 INT2 IMF EF7 = 1 or
Rising edge
ered to be signals.

IMF EF14 = 1 noise. Pulses of 25/fc [s] or more are considered
and Falling edge
INT3 INT3 or
IL14ER=0 Rising edge
ered to be signals.

IMF EF15 = 1
INT5 INT5 and Falling edge
IL15ER=0
ered to be signals.
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig-
nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an inter-
rupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Page 46
TMP86CM29LUG
External Interrupt Control Register

EINTCR 7 6 5 4 3 2 1 0
(0037H) INT1NC INT0EN - - INT3ES INT2ES INT1ES (Initial value: 00** 000*)
0: Pulses of less than 63/fc [s] are eliminated as noise

INT1NC Noise reject time select R/W
1: Pulses of less than 15/fc [s] are eliminated as noise
0: P63 input/output port

INT0EN P63/INT0 pin configuration R/W
1: INT0 pin (Port P63 should be set to an input mode)
0: Rising edge
INT3 ES INT3 edge select R/W
1: Falling edge
0: Rising edge
1: Falling edge
0: Rising edge
1: Falling edge
Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register
(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are dis-
abled using the interrupt enable register (EIR).
Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
Page 47
TMP86CM29LUG
Page 48
TMP86CM29LUG
The TMP86CM29LUG adopts the memory mapped I/O system, and all peripheral control and data transfers are
performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on
address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86CM29LUG.
4.1 SFR
Address Read Write
0000H Reserved
0001H P1DR
0002H P2DR
0003H P3DR
0004H P3OUTCR
0005H P5DR
0006H P6DR
0007H P7DR
0008H P1PRD -
0009H P2PRD -
000AH P3PRD -
000BH P5PRD -
000CH P6CR
000DH P7PRD -
000EH ADCCR1
000FH ADCCR2
0010H TREG1AL
0011H TREG1AM
0012H TREG1AH
0013H TREG1B
0014H TC1CR1
0015H TC1CR2
0016H TC1SR -
0017H Reserved
0018H TC3CR
0019H TC4CR
001AH TC5CR
001BH TC6CR
001CH TTREG3
001DH TTREG4
001EH TTREG5
001FH TTREG6
0020H ADCDR1 -
0021H ADCDR2 -
0022H Reserved
0023H Reserved
0024H Reserved
0025H UARTSR UARTCR1
Page 49
4.1 SFR
TMP86CM29LUG
Address Read Write
0026H - UARTCR2
0027H Reserved
0028H LCDCR
0029H P1LCR
002AH P5LCR
002BH P7LCR
002CH PWREG3
002DH PWREG4
002EH PWREG5
002FH PWREG6
0030H Reserved
0031H Reserved
0032H Reserved
0033H Reserved
0034H - WDTCR1
0035H - WDTCR2
0036H TBTCR
0037H EINTCR
0038H SYSCR1
0039H SYSCR2
003AH EIRL
003BH EIRH
003CH ILL
003DH ILH
003EH INTSEL
003FH PSW
Note 1: Do not access reserved areas by the program.

Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 50
TMP86CM29LUG
4.2 DBR
Address Read Write
0F80H SEG1/0
0F81H SEG3/2
0F82H SEG5/4
0F83H SEG7/6
0F84H SEG9/8
0F85H SEG11/10
0F86H SEG13/12
0F87H SEG15/14
0F88H SEG17/16
0F89H SEG19/18
0F8AH SEG21/20
0F8BH SEG23/22
0F8CH SEG25/24
0F8DH SEG27/26
0F8EH SEG29/28
0F8FH SEG31/30
0F90H SIOBR0
0F91H SIOBR1
0F92H SIOBR2
0F93H SIOBR3
0F94H SIOBR4
0F95H SIOBR5
0F96H SIOBR6
0F97H SIOBR7
0F98H - SIOCR1
0F99H SIOSR SIOCR2
0F9AH - STOPCR
0F9BH RDBUF TDBUF
0F9CH Reserved
0F9DH Reserved
0F9EH Reserved
0F9FH Reserved
Address Read Write
0FA0H Reserved
: : : :
0FBFH Reserved
Address Read Write
0FC0H Reserved
: : : :
0FDFH Reserved
Page 51
4.2 DBR
TMP86CM29LUG
Address Read Write
0FE0H EEPCR
0FE1H EEPSR -
0FE2H Reserved
0FE3H Reserved
0FE4H Reserved
0FE5H Reserved
0FE6H Reserved
0FE7H Reserved
0FE8H Reserved
0FE9H Reserved
0FEAH Reserved
0FEBH Reserved
0FECH Reserved
0FEDH Reserved
0FEEH Reserved
0FEFH Reserved
0FF0H Reserved
0FF1H Reserved
0FF2H Reserved
0FF3H Reserved
0FF4H Reserved
0FF5H Reserved
0FF6H Reserved
0FF7H Reserved
0FF8H Reserved
0FF9H Reserved
0FFAH Reserved
0FFBH Reserved
0FFCH Reserved
0FFDH Reserved
0FFEH Reserved
0FFFH Reserved
Note 1: Do not access reserved areas by the program.

Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 52
TMP86CM29LUG
5. I/O Ports
The TMP86CM29LUG has 6 parallel input/output ports (39 pins) as follows.
Primary Function Secondary Functions
External interrupt input, serial interface input/output, UART input/output and

Port P1 8-bit I/O port
segment output.
Low-frequency resonator connections, external interrupt input, STOP mode

release signal input.
Port P3 4-bit I/O port Timer/counter input/output and divider output.
Port P5 8-bit I/O port Segment output.
Analog input, external interrupt input, timer/counter input and STOP mode
release signal input.
Port P7 8-bit I/O port Segment output.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-
gram.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.

! " # ! " # ! " #

&'
%
! " # ! " # ! " #

$
$ ( )
$ &'
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Page 53
5. I/O Ports
5.1 Port P1 (P17 to P10)
TMP86CM29LUG
5.1 Port P1 (P17 to P10)

Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output,
UART input/output and segment output of LCD. When used as a segment pins of LCD, the respective bit of P1LCR
should be set to “1”.
When used as an input port or a secondary function (except for segment) pins, the respective output latch (P1DR)
should be set to “1” and its corresponding P1LCR bit should be set to “0”. When used as an output port, the respec-
tive P1LCR bit should be set to “0”. During reset, the output latch is initialized to “1”.
P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address.
When read the output latch data, the P1DR should be read and when read the terminal input data, the P1PRD reg-
ister should be read.
If the terminal input data which is configured as LCD segment output is read, unstable data is read.

! "

! "

Figure 5-2 Port P1
Port P1 control register

7 6 5 4 3 2 1 0
P1DR P17 P16 P15 P14 P13 P12 P11 P10
(0001H) SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
R/W (Initial value: 1111 1111)
SCK TxD RxD INT3 INT2 INT1
SO SI
7 6 5 4 3 2 1 0
P1LCR
(Initial value: 0000 0000)
(0029H)
Port P1/segment output control 0: P1 input/output port or secondary function (expect for segment)
P1LCR R/W
(set for each bit individually) 1: Segment output
7 6 5 4 3 2 1 0
P1PRD
(0008H) P17 P16 P15 P14 P13 P12 P11 P10
Read only
Page 54
TMP86CM29LUG
5.2 Port P2 (P22 to P20)

Port P2 is a 3-bit input/output port.
It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con-
nection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set
to “1”.
During reset, the P2DR is initialized to “1”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-
clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.
It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or
an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse.
ister should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable.

$ %

! " #"

$ %

$ %

Figure 5-3 Port P2

7 6 5 4 3 2 1 0
P2DR P22 P21 P20

(0002H) XTOUT XTIN INT5 (Initial value: **** *111)
R/W STOP
7 6 5 4 3 2 1 0
P2PRD P22 P21 P20

(0009H)
Read only
Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Page 55
5. I/O Ports
5.3 Port P3 (P33 to P30)
TMP86CM29LUG
5.3 Port P3 (P33 to P30)

Port P3 is a 4-bit input/output port.
It is also used as a timer/counter input/output, divider output.
When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to “1”.
It can be selected whether output circuit of P3 port is C-MOS output or a sink open drain individually, by setting
P3OUTCR. When a corresponding bit of P3OUTCR is “0”, the output circuit is selected to a sink open drain and
when a corresponding bit of P3OUTCR is “1”, the output circuit is selected to a C-MOS output. When used as an
input port or timer/counter input, respective output control (P3OUTCR) should be set to “0” after P3DR is set to “1”.
During reset, the P3DR is initialized to “1”, and the P3OUTCR is initialized to “0”.
ister should be read. If a read instruction is executed for port P3, read data of bits 7 to 4 are unstable.

Figure 5-4 Port P3

7 6 5 4 3 2 1 0
P3DR P33 P32 P31 P30

(0003H) PWM6 PWM4 PWM3 DVO
R/W PDO6 PDO4 PDO3 (Initial value: **** 1111)

PPG6 PPG4 TC3
TC6 TC4
P3OUTCR 7 6 5 4 3 2 1 0
(0004H) (Initial value: **** 0000)
Port P3 output circuit control 0: Sink open-drain output

P3OUTCR R/W
(set for each bit individually) 1: C-MOS ouput
7 6 5 4 3 2 1 0
P3PRD
(000AH) P33 P32 P31 P30
Read only
Page 56
TMP86CM29LUG
5.4 Port P5 (P57 to P50)

Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P5DR) should be set to “1”.
When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”. When used as an output
port, the respective P5LCR bit should be set to “0”.
ister should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is
read.

!

!

Figure 5-5 Port P5

7 6 5 4 3 2 1 0
P5DR
P57 P56 P55 P54 P53 P52 P51 P50
(0005H) (Initial value: 1111 1111)
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
R/W
P5LCR 7 6 5 4 3 2 1 0
(002AH) (Initial value: 0000 0000)
Port P5/segment output control 0: P5 input/output port

P5LCR R/W
(Set for each bit individually) 1: LCD segment output
7 6 5 4 3 2 1 0
P5PRD
(000BH) P57 P56 P55 P54 P53 P52 P51 P50
Read only
Page 57
5. I/O Ports
5.5 Port P6 (P67 to P60)
TMP86CM29LUG
5.5 Port P6 (P67 to P60)

Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also
used as an analog input, Key on Wake up input, timer/counter input and external interrupt input. Input/output modes
is specified by the P6 control register (P6CR), the P6 output latch (P6DR), and ADCCR1<AINDS>. During reset,
P6CR and P6DR are initialized to “0” and ADCCR1<AINDS> is set to “1”. At the same time, the input data of pins
P67 to P60 are fixed to “0”. To use port P6 as an input port, external interrupt input, timer/counter input or key on
wake up input, set data of P6DR to “1” and P6CR to “0”. To use it as an output port, set data of P6CR to “1”. To use
it as an analog input, set data of P6DR to “0” and P6CR to “0”, and start the AD. It is the penetration electric current
measures by the analog voltage.
Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be
executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog input
during AD conversion.
When the AD converter is in use (P6DR=0), bits mentioned above are read as “0” by executing input instructions.
STOPj
Key on wake up
Analog input
AINDS
SAIN
P6CRi D Q
P6CRi input
Data input (P6DR)
Data output (P6DR) D Q P6i

Note 1: i = 7 to 0, j = 7 to 4
Control input Note 2: STOP is bit 7 in SYSCR1
Note 3: SAIN is bit 0 to 3 in ADCCRA
STOP Note 4: STOPj is bit 4 to 7 in STOPCR.
Figure 5-6 Port P6
Page 58
TMP86CM29LUG

7 6 5 4 3 2 1 0
P6DR P67 P66 P65 P64 P63 P62 P61 P60

(0006H) AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 (Initial value: 0000 0000)
R/W STOP5 STOP4 STOP3 STOP2 INT0 ECNT ECIN
P6CR 7 6 5 4 3 2 1 0
(000CH) (Initial value: 0000 0000)
AINDS = 1 (AD unused) AINDS = 0 (AD used)
I/O control for port P6 P6DR = “0” P6DR = “1” P6DR = “0” P6DR = “1”
P6CR R/W
(specified for each bit) 0 Input “0” fixed Input mode AD input#1 Input mode
1 Output mode
#1 Do not set output mode to pin which is used for an analog input.
Note 1: When used as an INT0, ECNT and ECIN pins of a secondary function, the respective bit of P6CR should be set to “0”and
the P6 should set to “1”.
Note 2: When used as an STOP2 to STOP5 pins of Key on Wake up, the respective bit of P6CR should be set to “0”.
Note 3: When a read instruction for port P6 is executed, the bit of Analog input mode becomes read data “0”.
Note: Although P6DR is a read/writer register, because it is also used as an input mode control function, read-modify-
write instructions such as bit manipulate instructions cannot be used.
Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting Input
mode read data of terminal, the output latch is changed by these instruction. So P6 port can not input data.
Page 59
5. I/O Ports
5.6 Port P7 (P77 to P70)
TMP86CM29LUG
5.6 Port P7 (P77 to P70)

Port P7 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P7DR) should be set to “1”.
When used as a segment pins of LCD, the respective bit of P7LCR should be set to “1”. When used as an output
port, the respective P7LCR bit should be set to “0”.
ister should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is
read.

Figure 5-7 Port P7

7 6 5 4 3 2 1 0
P7DR
P77 P76 P75 P74 P73 P72 P71 P70
(0007H) (Initial value: 1111 1111)
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
R/W
P7LCR 7 6 5 4 3 2 1 0
(002BH) (Initial value: 0000 0000)
Port P7/segment output control 0: P7 input/output port

P7LCR R/W
(set for each bit individually) 1: Segment output
7 6 5 4 3 2 1 0
P7PRD
(000DH) P77 P76 P75 P74 P73 P72 P71 P70
Read only
Page 60
TMP86CM29LUG
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu-
rious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter-
rupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter-
rupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
6.1 Watchdog Timer Configuration
Reset release
23 15
fc/2 or fs/2 Binary counters
Selector
fc/221 or fs/213 Clock R

fc/219 or fs/211 Overflow WDT output
fc/217 or fs/29 1 2 Reset
Clear S Q request
2 Interrupt request
INTWDT
interrupt
request
Internal reset
Q
S R
WDTEN
Writing Writing
WDTT WDTOUT
disable code clear code
Controller
0034H 0035H
WDTCR1 WDTCR2
Watchdog timer control registers
Figure 6-1 Watchdog Timer Configuration
Page 61
6.2 Watchdog Timer Control
TMP86CM29LUG

The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch-
dog timer is automatically enabled after the reset release.
6.2.1 Malfunction Detection Methods Using the Watchdog Timer

The CPU malfunction is detected, as shown below.
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch-
dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and the RESET pin outputs a
low-level signal, then internal hardware is initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog
timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection
LD (WDTCR2), 4EH : Clears the binary counters.
LD (WDTCR1), 00001101B : WDTT ← 10, WDTOUT ← 1
LD (WDTCR2), 4EH : Clears the binary counters (always clears immediately before and
after changing WDTT).
:
Within 3/4 of WDT
detection time
:
:
Within 3/4 of WDT
detection time
:
Page 62
TMP86CM29LUG
Watchdog Timer Control Register 1
WDTCR1 7 6 5 4 3 2 1 0
(0034H) (ATAS) (ATOUT) WDTEN WDTT WDTOUT (Initial value: **11 1001)
0: Disable (Writing the disable code to WDTCR2 is required.) Write

WDTEN Watchdog timer enable/disable
1: Enable only
NORMAL1/2 mode SLOW1/2

DV7CK = 0 DV7CK = 1 mode
00 225/fc 217/fs 217/fs

Watchdog timer detection time Write
WDTT
[s] 01 223/fc 215/fs 215fs only
10 221fc 213/fs 213fs
11 219/fc 211/fs 211/fs
0: Interrupt request Write

WDTOUT Watchdog timer output select
1: Reset request only
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don’t care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “1.2.3 Watchdog Timer Disable”.
WDTCR2 7 6 5 4 3 2 1 0
(0035H) (Initial value: **** ****)
4EH: Clear the watchdog timer binary counter (Clear code)

Write B1H: Disable the watchdog timer (Disable code) Write
WDTCR2
Watchdog timer control code D2H: Enable assigning address trap area only
Others: Invalid
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.

Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
6.2.2 Watchdog Timer Enable

Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Page 63
TMP86CM29LUG
6.2.3 Watchdog Timer Disable

To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg-
ister in other procedures causes a malfunction of the microcontroller.
1. Set the interrupt master flag (IMF) to “0”.

2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer

DI : IMF ← 0
LD (WDTCR2), 04EH : Clears the binary coutner
LDW (WDTCR1), 0B101H : WDTEN ← 0, WDTCR2 ← Disable code
Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
Watchdog Timer Detection Time[s]

WDTT NORMAL1/2 mode SLOW
00 2.097 4 4
01 524.288 m 1 1
10 131.072 m 250 m 250 m
11 32.768 m 62.5 m 62.5 m
6.2.4 Watchdog Timer Interrupt (INTWDT)

When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt

LD SP, 063FH : Sets the stack pointer
LD (WDTCR1), 00001000B : WDTOUT ← 0
Page 64
TMP86CM29LUG
6.2.5 Watchdog Timer Reset

When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the RESET pin outputs a low-level sig-
nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). After
reset, the CPU enters a wait state until the power supply of the flash memory control circuit is stable. The wait
time is 210/fc [s] (62.5 µs @ fc = 16.0 MHz). The CPU halts and remains in a wait state, and restarts operation
after the wait time.
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
219/fc [s]
217/fc
Clock (WDTT=11)
Binary counter 1 2 3 0 1 2 3 0
Overflow
INTWDT interrupt request

(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1") A reset occurs
WDT reset output (High-Z)
Write 4EH to WDTCR2
Figure 6-2 Watchdog Timer Interrupt/Reset
Page 65
6.3 Address Trap
TMP86CM29LUG
6.3 Address Trap

The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
WDTCR1 7 6 5 4 3 2 1 0
(0034H) ATAS ATOUT (WDTEN) (WDTT) (WDTOUT) (Initial value: **11 1001)
0: Generate no address trap

Select address trap generation in
ATAS 1: Generate address traps (After setting ATAS to “1”, writing the control code
the internal RAM area Write
D2H to WDTCR2 is reguired)
only
0: Interrupt request
ATOUT Select opertion at address trap
1: Reset request
WDTCR2 7 6 5 4 3 2 1 0
(0035H) (Initial value: **** ****)
Write D2H: Enable address trap area selection (ATRAP control code)
Watchdog timer control code 4EH: Clear the watchdog timer binary counter (WDT clear code) Write
WDTCR2
and address trap area control B1H: Disable the watchdog timer (WDT disable code) only
code Others: Invalid
6.3.1 Selection of Address Trap in Internal RAM (ATAS)

WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> set-
ting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.
6.3.2 Selection of Operation at Address Trap (ATOUT)

When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.
6.3.3 Address Trap Interrupt (INTATRAP)

While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas-
ter flag (IMF).
When an address trap interrupt is generated while the other interrupt including a watchdog timer interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
Page 66
TMP86CM29LUG
6.3.4 Address Trap Reset

While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the RESET pin outputs a low-level signal and the internal
hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). After reset, the CPU enters a
wait state until the power supply of the flash memory control circuit is stable. The wait time is 210/fc [s] (62.5
µs @ fc = 16.0 MHz). The CPU halts and remains in a wait state, and restarts operation after the wait time.
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 67
6.3 Address Trap
TMP86CM29LUG
Page 68
TMP86CM29LUG
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
timer interrupt (INTTBT).
7.1 Time Base Timer
7.1.1 Configuration
MPX
fc/223 or fs/215
fc/221 or fs/213
fc/216 or fs/28 Source clock Falling edge IDLE0, SLEEP0
fc/214 or fs/26 release request
detector
fc/213 or fs/25 INTTBT
fc/212 or fs/24 interrupt request
fc/211 or fs/23
fc/29 or fs/2
TBTCK TBTEN
TBTCR
Time base timer control register
Figure 7-1 Time Base Timer configuration
7.1.2 Control
Time Base Timer is controled by Time Base Timer control register (TBTCR).
Time Base Timer Control Register

7 6 5 4 3 2 1 0
TBTCR
(DVOEN) (DVOCK) (DV7CK) TBTEN TBTCK (Initial Value: 0000 0000)
(0036H)
Time Base Timer 0: Disable

TBTEN
enable / disable 1: Enable
NORMAL1/2, IDLE1/2 Mode SLOW1/2

SLEEP1/2
DV7CK = 0 DV7CK = 1 Mode
000 fc/223 fs/215 fs/215
001 fc/221 fs/213 fs/213
Time Base Timer interrupt 010 fc/216 fs/28 –

TBTCK R/W
Frequency select : [Hz] 14 6
011 fc/2 fs/2 –
100 fc/213 fs/25 –
101 12 4 –
fc/2 fs/2
110 fc/211 fs/23 –
111 9 fs/2 –
fc/2
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Page 69
7.1 Time Base Timer
TMP86CM29LUG
Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre-
quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per-
formed simultaneously.
Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.
LD (TBTCR) , 00000010B ; TBTCK ← 010
LD (TBTCR) , 00001010B ; TBTEN ← 1
DI ; IMF ← 0
SET (EIRL) . 6
Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Time Base Timer Interrupt Frequency [Hz]

TBTCK
NORMAL1/2, IDLE1/2 Mode NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2 Mode
DV7CK = 0 DV7CK = 1
000 1.91 1 1
001 7.63 4 4
010 244.14 128 –
011 976.56 512 –
100 1953.13 1024 –
101 3906.25 2048 –
110 7812.5 4096 –
111 31250 16384 –
7.1.3 Function
An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider
output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled.
The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set
interrupt period ( Figure 7-2 ).
Source clock
TBTCR<TBTEN>
INTTBT
Interrupt period
Enable TBT
Figure 7-2 Time Base Timer Interrupt
Page 70
TMP86CM29LUG
7.2 Divider Output (DVO)

Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from DVO pin.
7.2.1 Configuration
Output latch
Data output D Q
DVO pin
MPX
fc/213 or fs/25 A
fc/212 or fs/24 B
fc/211 or fs/23 C Y
fc/210 or fs/22
D Port output latch
S
2
TBTCR<DVOEN>
DVOCK DVOEN
TBTCR
DVO pin output
Divider output control register
(a) configuration (b) Timing chart
Figure 7-3 Divider Output
7.2.2 Control
The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register

7 6 5 4 3 2 1 0
TBTCR
DVOEN DVOCK (DV7CK) (TBTEN) (TBTCK) (Initial value: 0000 0000)
(0036H)
Divider output 0: Disable

DVOEN R/W
enable / disable 1: Enable
NORMAL1/2, IDLE1/2 Mode SLOW1/2

SLEEP1/2
Divider Output (DVO) 00 fc/213 fs/25 fs/25

DVOCK R/W
frequency selection: [Hz]
01 fc/212 fs/24 fs/24
10 fc/211 fs/23 fs/23
11 fc/210 fs/22 fs/22
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
Page 71
7.2 Divider Output (DVO)
TMP86CM29LUG
Example :1.95 kHz pulse output (fc = 16.0 MHz)
LD (TBTCR) , 00000000B ; DVOCK ← "00"
LD (TBTCR) , 10000000B ; DVOEN ← "1"
Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Divider Output Frequency [Hz]
DVOCK NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2

00 1.953 k 1.024 k 1.024 k
01 3.906 k 2.048 k 2.048 k
10 7.813 k 4.096 k 4.096 k
11 15.625 k 8.192 k 8.192 k
Page 72
INTTC1
fc/212 or fs/24 TREG1B
A
8.1 Configuration
fc/213 or fs/25 B Y
fc/214 or fs/26 C 2
S TC1M
Window pulse
generator
2
SGEDG
WGPSCK 1
PWM6/PDO6/PPG6
1
TC6OUT
Edge detector
P33 Pin
C
B Y
ECNT Pin A
S
SEG
1 Pulse width
Page 73
measurement mode
10 CLEAR signal
ECIN Pin Edge detector H Frequency
measurement mode 11 Y 18- bit up-counter F/F
fs/215 or fc/223 C
fs/25 or fc/213 D Timer/Event count modes
Y 00 S
fs/23 or fc/211 E 1 1
Figure 8-1 Timer/Counter1

F CMP
fc/27
G
fc/23 TC1SR
fs B
fc A TREG1AL TREG1AM TREG1AH
3 2 2 1 1 2 1 2 1
SEG
SGP
TC1S
TC1C
TC1M
TC6OUT
TC1CK
SGEDG
WGPSCK
TC1CR1 TC1CR2
TMP86CM29LUG
8.2 Control
TMP86CM29LUG
8.2 Control
The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register
(TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B).
Timer register
7 6 5 4 3 2 1 0
TREG1AH
(0012H) − − − − − − TREG1AH (Initial value: ∗∗∗∗ ∗∗00)
R/W
7 6 5 4 3 2 1 0
TREG1AM
(0011H) TREG1AM (Initial value: 0000 0000)
R/W
7 6 5 4 3 2 1 0
TREG1AL
(0010H) TREG1AL (Initial value: 0000 0000)
R/W
7 6 5 4 3 2 1 0
TREG1B
Ta Tb (Initial value: 0000 0000)
(0013H)
NORMAL1/2,IDLE1/2 modes SLOW1/2,

WGPSCK
DV7CK=0 DV7CK=1 SLEEP1/2 modes
00 (16 - Ta) × 212/fc (16 - Ta) × 24/fs (16 - Ta) × 24/fs

Setting "H" level period of the window 13 5
Ta 01 (16 - Ta) × 2 /fc (16 - Ta) × 2 /fs (16 - Ta) × 25/fs
gate pulse R/W
10 (16 - Ta) × 214/fc (16 - Ta) × 26/fs (16 - Ta) × 26/fs
00 (16 - Tb) × 212/fc (16 - Tb) × 24/fs (16 - Tb) × 24/fs

Setting "L" level period of the window
Tb 01 (16 - Tb) × 213/fc (16 - Tb) × 25/fs (16 - Tb) × 25/fs
gate pulse
10 (16 - Tb) × 214/fc (16 - Tb) × 26/fs (16 - Tb) × 26/fs
Page 74
TMP86CM29LUG
Timer/counter 1 control register 1
7 6 5 4 3 2 1 0
TC1CR1
TC1C TC1S TC1CK TC1M (Initial value: 1000 1000)
(0014H)
Counter/overfow flag 0: Clear Counter/overflow flag ( “1” is automatically set after clearing.)
TC1C R/W
controll 1: Not clear Counter/overflow flag
00: Stop and counter clear and overflow flag clear

TC1S TC1 start control 10: Start R/W
*1: Reserved
NORMAL1/2,IDLE1/2 modes SLOW1/2 SLEEP1/2

DV7CK="0" DV7CK="1" mode mode
fc fc fc fc
000:
fs fs - -
001:
010: fc/223 fs/215 fs/215 fs/215
TC1CK TC1 source clock select R/W
13
011: fc/2 fs/25 fs/25 fs/25
100: fc/211 fs/23 fs/23 fs/23
101: fc/2 7
fc/27 - -
110: - -
fc/23 fc/23
111: External clock (ECIN pin input)
00: Timer/Event counter mode

01: Reserved
TC1M TC1 mode select R/W
10: Pulse width measurement mode
11: Frequency measurement mode
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; Don’t care
Note 2: Writing to the low-byte of the timer register 1A (TREG1AL, TREG1AM), the compare function is inhibited until the high-
byte (TREG1AH) is written.
Note 3: Set the mode and source clock, and edge (selection) when the TC1 stops (TC1S=00).
Note 4: “fc” can be selected as the source clock only in the timer mode during SLOW mode and in the pulse width measurement
mode during NORMAL 1/2 or IDLE 1/2 mode.
Note 5: When a read instruction is executed to the timer register (TREG1A), the counter immediate value, not the register set
value, is read out. Therefore it is impossible to read out the written value of TREG1A. To read the counter value, the read
instruction should be executed when the counter stops to avoid reading unstable value.
Note 6: Set the timer register (TREG1A) to ≥1.
Note 7: When using the timer mode and pulse width measurement mode, set TC1CK (TC1 source clock select) to internal clock.
Note 8: When using the event counter mode, set TC1CK (TC1 source clock select) to external clock.
Note 9: Because the read value is different from the written value, do not use read-modify-write instructions to TREG1A.
Note 10:fc/27, fc/23can not be used as source clock in SLOW/SLEEP mode.
Note 11:The read data of bits 7 to 2 in TREG1AH are always “0”. (Data “1” can not be written.)
Page 75
8.2 Control
TMP86CM29LUG
Timer/Counter 1 control register 2
7 6 5 4 3 2 1 0
TC1CR2
SEG SGP SGEDG WGPSCK TC6OUT "0" (Initial value: 0000 000*)
(0015H)
External input clock (ECIN) edge 0: Counts at the falling edge

SEG R/W
select 1: Counts at the both (falling/rising) edges
00: ECNT input

01: Internal window gate pulse (TREG1B)
SGP Window gate pulse select
10: PWM6/PDO6/PPG6 (TC6)output
11: Reserved R/W
Window gate pulse interrupt edge 0: Interrupts at the falling edge

SGEDG
select 1: Interrupts at the falling/rising edges
NORMAL1/2,IDLE1/2 modes SLOW1/2 SLEEP1/2

DV7CK="0" DV7CK="1" mode mode
Window gate pulse source clock

WGPSCK 00: 212/fc 24/fs 24/fs 24/fs R/W
select
13 5 5
01: 2 /fc 2 /fs 2 /fs 25/fs
10: 214/fc 26/fs 26/fs 26/fs
11: Reserved Reserved Reserved Reserved
TC6 output (PWM6/PDO6/PPG6) 0: Output to P33

TC6OUT R/W
external output select 1: No output to P33
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] *; Don't care
Note 2: Set the mode, source clock, and edge (selection) when the TC1 stops (TC1S = 00).
Note 3: If there is no need to use PWM6/PDO6/PPG6 as window gate pulse of TC1 always write "0" to TC6OUT.
Note 4: Make sure to write TC1CR2 "0" to bit 0 in TC1CR2.
Note 5: When using the event counter mode or pulse width measurement mode, set SEG to "0".
Page 76
TMP86CM29LUG
TC1 status register
7 6 5 4 3 2 1 0
TC1SR
HECF HEOVF "0" "0" "0" "0" "0" "0" (Initial value: 0000 0000)
(0016H)
0: Stop (during Tb) or disable

HECF Operating Status monitor
1: Under counting (during Ta) Read
0: No overflow only
HEOVF Counter overflow monitor
1: Overflow status
8.3 Function
TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode
to NORMAL2 mode.
8.3.1 Timer mode

In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with
the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared.
Counting up resumes after the counter is cleared.
Table 8-1 Source clock (internal clock) of Timer/Counter 1
Source Clock Resolution Maximum Time Setting
NORMAL1/2, IDLE1/2 Mode fs =32.768 fs =32.768

SLOW Mode SLEEP Mode fc = 16 MHz fc = 16 MHz
DV7CK = 0 DV7CK = 1 kHz kHz
fc/223 [Hz] fs/215 [Hz] fs/215 [Hz] fs/215 [Hz] 0.52 s 1s 38.2 h 72.8 h
fc/213 fs/25 fs/25 fs/25 512 ms 0.98 ms 2.2 min 4.3 min
fc/211 fs/23 fs/23 fs/23 128 ms 244 ms 0.6 min 1.07 min
fc/27 fc/27 - - 8 ms - 2.1 s -
fc/23 fc/23 - - 0.5 ms - 131.1 ms -
fc fc fc (Note) - 62.5 ns - 16.4 ms -
fs fs - - - 30.5 ms - 8s
Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper
bits 7 makes interrupts.
Page 77
8.3 Function
TMP86CM29LUG
Command Start
Internal clock
Up counter 0 1 2 3 4 n-1 n 0 1 2 3 4 5 6
TREG1A n
Match detect Counter clear

INTTC1 interrupt
Figure 8-2 Timing chart for timer mode
8.3.2 Event Counter mode

It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set
TC1CR1<TC1CK> to the external clock and then set TC1CR2<SEG> to “0” (Both edges can not be used).
The countents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared. Counting up resumes for ECIN pin input edge each after the
counter is cleared.
The maximum applied frequency is fc/24 [Hz] in NORMAL 1/2 or IDLE 1/2 mode and fs/24[Hz] in SLOW
or SLEEP mode . Two or more machine cycles are required for both the “H” and “L” levels of the pulse width.
Start
ECIN pin input
Up counter 0 1 2 n-1 n 0 1 2
TREG1A n
Match Detect Counter clear

INTTC1 interrupt
Figure 8-3 Event counter mode timing chart
Page 78
TMP86CM29LUG
8.3.3 Pulse Width Measurement mode

In this mode, pulse widths are counted on the falling edge of logical AND-ed pulse between ECIN pin input
(window pulse) and the internal clock. When using this mode, set TC1CR1<TC1CK> to suitable internal clock
and then set TC1CR2<SEG> to “0” (Both edges can not be used).
An INTTC1 interrupt is generated when the ECIN input detects the falling edge of the window pulse or both
rising and falling edges of the window pulse, that can be selected by TC1CR2<SGEDG>.
The contents of TREG1A should be read while the count is stopped (ECIN pin is low), then clear the counter
using TC1CR1<TC1C> (Normally, execute these process in the interrupt program).
When the counter is not cleared by TC1CR1<TC1C>, counting-up resumes from previous stopping value.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time, TC1SR<HEOVF>
is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be cleared by
TC1CR1<TC1C>.
Note:In pulse width measurement mode, if TC1CR1<TC1S> is written to "00" while ECIN input is "1", INTTC1 inter-
rupt occurs. According to the following step, when timer counter is stopped, INTTC1 interrupt latch should be
cleared to "0".
Example :
TC1STOP :
¦ ¦
DI ; Clear IMF
CLR (EIRH). 0 ; Clear bit0 of EIRH
LD (TC1CR1), 00011010B ; Stop timer couter 1
LD (ILH), 11111110B ; Clear bit0 of ILH
SET (EIRH). 0 ; Set bit0 of EIRH
EI ; Set IMF
¦ ¦
Note 1: When SGEDG (window gate pulse interrupt edge select) is set to both edges and ECIN pin input is "1" in
the pulse width measurement mode, an INTTC1 interrupt is generated by setting TC1S (TC1 start control)
to "10" (start).
Note 2: In the pulse width measurement mode, HECF (operating status monitor) cannot used.
Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and
the internal clock), if ECIN input becomes falling edge while internal source clock is "H" level, the up
counter stops plus "1".
Count Start Count Stop Count Start

ECIN pin input
Internal clock
AND-ed pulse
(Internal signal)
Up counter 0 1 2 3 n-2 n-1 n n+1 0 1 2
Read Clear
INTTC1 interrupt
Interrupt
TC1CR1<TC1C>
Figure 8-4 Pulse width measurement mode timing chart
Page 79
8.3 Function
TMP86CM29LUG
8.3.4 Frequency Measurement mode

In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by
TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to “00”.
An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate
pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of
TREG1A while the count is stopped (window gate pulse is low), then clear the counter using
TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.
The window pulse status can be monitored by TC1SR<HECF>.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,
TC1SR<HEOVF> is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be
cleared by TC1CR1<TC1C>.
Using TC6 output (PWM6/PDO6/PPG6) for the window gate pulse, external output of PWM6/PDO6/PPG6 to
P33 can be controlled using TC1CR2<TC6OUT>. Zero-clearing TC1CR2<TC6OUT> outputs PWM6/
PDO6/PPG6 to P33; setting 1 in TC1CR2<TC6OUT> does not output PWM6/PDO6/PPG6 to P33.
(TC1CR2<TC6OUT> is used to control output to P33 only. Thus, use the timer counter 6 control register to
operate/stop PWM6/PDO6/PPG6.)
When the internal window gate pulse is selected, the window gate pulse is set as follows.
Table 8-2 Internal window gate pulse setting time
NORMAL1/2,IDLE1/2 modes SLOW1/2,

WGPSCK
DV7CK=0 DV7CK=1 SLEEP1/2 modes
00 (16 - Ta) × 212/fc (16 - Ta) × 24/fs (16 - Ta) × 24/fs

Setting "H" level period of the window
Ta 01 (16 - Ta) × 213/fc (16 - Ta) × 25/fs (16 - Ta) × 25/fs
gate pulse R/W
10 14
(16 - Ta) × 2 /fc 6
(16 - Ta) × 2 /fs (16 - Ta) × 26/fs
00 (16 - Tb) × 212/fc (16 - Tb) × 24/fs (16 - Tb) × 24/fs

Setting "L" level period of the window
Tb 01 (16 - Tb) × 213/fc (16 - Tb) × 25/fs (16 - Tb) × 25/fs
gate pulse
10 (16 - Tb) × 214/fc (16 - Tb) × 26/fs (16 - Tb) × 26/fs
The internal window gate pulse consists of “H” level period (Ta) that is counting time and “L” level period
(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.
Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be
delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer.
Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When
Tb is overwritten during the Tb period, the update is valid from the next Tb period.
Note 3: In case of TC1CR2<SEG> = "1", if window gate pulse becomes falling edge, the up counter stops plus "1"
regardless of ECIN input level. Therefore, if ECIN is always "H" or "L" level, count value becomes "1".
Note 4: In case of TC1CR2<SEG> = "0", because the up counter is counted on the falling edge of logical AND-ed
pulse (between ECIN pin input and window gate pulse), if window gate pulse becomes falling edge while
ECIN input is "H" level, the up counter stops plus "1". Therefore, if ECIN input is always "H" level, count
value becomes "1".
Page 80
TMP86CM29LUG
Table 8-3 Table Setting Ta and Tb (WGPSCK = 10, fc = 16 MHz)
Setting Value Setting time Setting Value Setting time
0 16.38ms 8 8.19ms
1 15.36ms 9 7.17ms
2 14.34ms A 6.14ms
3 13.31ms B 5.12ms
4 12.29ms C 4.10ms
5 11.26ms D 3.07ms
6 10.24ms E 2.05ms
7 9.22ms F 1.02ms
Table 8-4 Table Setting Ta and Tb (WGPSCK = 10, fs = 32.768 kHz)
Setting Valuen Setting time Setting Value Setting time
0 31.25ms 8 15.63ms
1 29.30ms 9 13.67ms
2 27.34ms A 11.72ms
3 25.39ms B 9.77ms
4 23.44ms C 7.81ms
5 21.48ms D 5.86ms
6 19.53ms E 3.91ms
7 17.58ms F 1.95ms
Page 81
8.3 Function
TMP86CM29LUG
ECIN pin input
Window gate
pulse
Ta Tb Ta
AND-ed pulse
(Internal signal)
Up counter 0 1 2 3 4 5 6 0 1 2 3 4 5 6
INTTC1 interrupt Read Clear
TC1CR1<TC1C>
a) TC1CR2<SEG> = "0"
TC1CR2<SEG>
ECIN pin input
Window gate
pulse
Ta Tb Ta
Up counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12
INTTC1 interrupt Read Clear
TC1CR1<TC1C>
a) TC1CR2<SEG> = "1"
Figure 8-5 Timing chart for the frequency measurement mode (Window gate pulse falling
interrupt)
Page 82
TMP86CM29LUG
9.1 Configuration
PWM mode
Overflow
INTTC4
interrupt request
fc/211 or fs/23 A Clear
fc/2
7
B Y A Y 8-bit up-counter
fc/2
5
C B TC4S
fc/23 D S PDO, PPG mode
fs E A
fc/2 F Toggle
16-bit mode Y
fc G B Q
TC4 pin H S
16-bit Set PDO4/PWM4/
S Timer, Event
mode Counter mode Clear PPG4 pin
TC4M S
TC4S TC4CK Timer F/F4
TFF4 A
Y
TC4CR B
TTREG4 PWREG4 PWM, PPG mode DecodeEN PDO, PWM,
PPG mode
TFF4
16-bit
mode
TC3S
PWM mode
INTTC3
fc/211 or fs/23
Clear interrupt request
A
16-bit mode
fc/27 B Y 8-bit up-counter Overflow
fc/2
5
C PDO mode
3
fc/2 D
fs E Toggle
fc/2 F
fc G 16-bit mode Q
TC3 pin H Timer, Set PDO3/PWM3/
S Event Couter mode pin
Clear
TC3M Timer F/F3
TC3S TC3CK
TFF3
TC3CR PWM mode
DecodeEN PDO, PWM mode
TTREG3 PWREG3 16-bit mode
TFF3
Figure 9-1 8-Bit TimerCouter 3, 4
Page 83
9.1 Configuration
TMP86CM29LUG
9.2 TimerCounter Control

The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers
(TTREG3, PWREG3).
TimerCounter 3 Timer Register
TTREG3 7 6 5 4 3 2 1 0
(001CH)
PWREG3 7 6 5 4 3 2 1 0
(002CH)
Note 1: Do not change the timer register (TTREG3) setting while the timer is running.
Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 3 Control Register
TC3CR 7 6 5 4 3 2 1 0
(0018H) TFF3 TC3CK TC3S TC3M (Initial value: 0000 0000)
0: Clear
TFF3 Time F/F3 control R/W
1: Set
NORMAL1/2, IDLE1/2 mode SLOW1/2

SLEEP1/2
000 fc/211 fs/23 fs/23
001 fc/27 fc/27 –
010 fc/25 fc/25 –

TC3CK Operating clock selection [Hz] R/W
011 fc/23 fc/23 –
100 fs fs fs
101 fc/2 fc/2 –
110 fc fc fc (Note 8)
111 TC3 pin input
0: Operation stop and counter clear

TC3S TC3 start control R/W
1: Operation start
000: 8-bit timer/event counter mode

001: 8-bit programmable divider output (PDO) mode
010: 8-bit pulse width modulation (PWM) output mode
TC3M TC3M operating mode select R/W
011: 16-bit mode
(Each mode is selectable with TC4M.)
1**: Reserved
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz]

Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running.
Note 3: To stop the timer operation (TC3S= 1 → 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer opera-
tion (TC3S= 0 → 1), TC3M, TC3CK and TFF3 can be programmed.
Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR<TC4M>, where TC3M must
be fixed to 011.
Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC3CK. Set the timer start control
and timer F/F control by programming TC4CR<TC4S> and TC4CR<TFF4>, respectively.
Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Page 84
TMP86CM29LUG
Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9-
3.
Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.
Page 85
9.1 Configuration
TMP86CM29LUG
(TTREG4 and PWREG4).
TTREG4 7 6 5 4 3 2 1 0
(001DH)
PWREG4 7 6 5 4 3 2 1 0
(002DH)
TC4CR 7 6 5 4 3 2 1 0
(0019H) TFF4 TC4CK TC4S TC4M (Initial value: 0000 0000)
0: Clear
TFF4 Timer F/F4 control R/W
1: Set

SLEEP1/2
000 fc/211 fs/23 fs/23
001 fc/27 fc/27 –
010 fc/25 fc/25 –

011 3 3 –
fc/2 fc/2
100 fs fs fs
101 fc/2 fc/2 –
110 fc fc –
111 TC4 pin input

1: Operation start

011: Reserved
101: Warm-up counter mode
111: 16-bit PPG mode
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz]

Note 3: To stop the timer operation (TC4S= 1 → 0), do not change the TC4M, TC4CK and TFF4 settings.
To start the timer operation (TC4S= 0 → 1), TC4M, TC4CK and TFF4 can be programmed.
Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the
TC3CK setting.
Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR<TC3 M>
must be set to 011.
Page 86
TMP86CM29LUG
Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start
control and timer F/F control by programming TC4S and TFF4, respectively.
9-1 and Table 9-2.
3.
Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes)
fc/211
TC3 TC4
Operating mode or fc/27 fc/25 fc/23 fs fc/2 fc
pin input pin input
fs/23
8-bit timer Ο Ο Ο Ο – – – – –
8-bit event counter – – – – – – – Ο Ο
8-bit PDO Ο Ο Ο Ο – – – – –
8-bit PWM Ο Ο Ο Ο Ο Ο Ο – –
16-bit event counter – – – – – – – Ο –
Warm-up counter – – – – Ο – – – –
16-bit PWM Ο Ο Ο Ο Ο Ο Ο Ο –
16-bit PPG Ο Ο Ο Ο – – – Ο –
Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note 2: Ο : Available source clock
Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes)
fc/211
TC3 TC4
pin input pin input
fs/23
8-bit timer Ο – – – – – – – –
8-bit event counter – – – – – – – Ο Ο
8-bit PDO Ο – – – – – – – –
8-bit PWM Ο – – – Ο – – – –
16-bit timer Ο – – – – – – – –
16-bit event counter – – – – – – – Ο –
Warm-up counter – – – – – – Ο – –
16-bit PWM Ο – – – Ο – – Ο –
16-bit PPG Ο – – – – – – Ο –
Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note2: Ο : Available source clock
Page 87
9.1 Configuration
TMP86CM29LUG
Table 9-3 Constraints on Register Values Being Compared
Operating mode Register Value
8-bit timer/event counter 1≤ (TTREGn) ≤255
8-bit PDO 1≤ (TTREGn) ≤255
8-bit PWM 2≤ (PWREGn) ≤254
16-bit timer/event counter 1≤ (TTREG4, 3) ≤65535
Warm-up counter 256≤ (TTREG4, 3) ≤65535
16-bit PWM 2≤ (PWREG4, 3) ≤65534
1≤ (PWREG4, 3) < (TTREG4, 3) ≤65535

16-bit PPG and
(PWREG4, 3) + 1 < (TTREG4, 3)
Note: n = 3 to 4
Page 88
TMP86CM29LUG
9.3 Function
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
9.3.1 8-Bit Timer Mode (TC3 and 4)

In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock)
Source Clock Resolution Repeated Cycle
NORMAL1/2, IDLE1/2 mode SLOW1/2,

SLEEP1/2 fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz
fc/211 [Hz] fs/23 [Hz] fs/23 [Hz] 128 µs 244.14 µs 32.6 ms 62.3 ms
fc/27 fc/27 – 8 µs – 2.0 ms –
fc/25 fc/25 – 2 µs – 510 µs –
fc/23 fc/23 – 500 ns – 127.5 µs –
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later
(TimerCounter4, fc = 16.0 MHz)
LD (TTREG4), 0AH : Sets the timer register (80 µs÷27/fc = 0AH).
DI
SET (EIRH). 3 : Enables INTTC4 interrupt.
EI
LD (TC4CR), 00010000B : Sets the operating cock to fc/27, and 8-bit timer mode.
LD (TC4CR), 00011000B : Starts TC4.
Page 89
9.1 Configuration
TMP86CM29LUG
TC4CR<TC4S>
Internal
Source Clock
Counter 1 2 3 n-1 n 0 1 2 n-1 n 0 1 2 0
TTREG4 ? n

INTTC4 interrupt request
Figure 9-2 8-Bit Timer Mode Timing Chart (TC4)
9.3.2 8-Bit Event Counter Mode (TC3, 4)

In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 3, 4
TC4CR<TC4S>
TC4 pin input
Counter 0 1 2 n-1 n 0 1 2 n-1 n 0 1 2 0
TTREG4 ? n
Match detect Counter Counter

clear Match detect
INTTC4 interrupt request clear
Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4)
9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)

This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
Page 90
TMP86CM29LUG
Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)

Setting port
LD (TTREG4), 3DH : 1/1024÷27/fc÷2 = 3DH
LD (TC4CR), 00010001B : Sets the operating clock to fc/27, and 8-bit PDO mode.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PDOj pin to the high level.
Note 3: j = 3, 4
Page 91
9.1 Configuration
TC4CR<TC4S>
TC4CR<TFF4> Write of "1"
Internal
source clock
Counter 0 1 2 n 0 1 2 n 0 1 2 n 0 1 2 n 0 1 2 3 0
Page 92
TTREG4 ? n
Match detect Match detect Match detect Match detect
Timer F/F4 Set F/F
PDO4 pin
Held at the level when the timer

INTTC4 interrupt request is stopped
Figure 9-4 8-Bit PDO Mode Timing Chart (TC4)

TMP86CM29LUG
TMP86CM29LUG
9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)

This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
up-counter counts up using the internal clock.
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen-
erated. Upon reset, the timer F/Fj is cleared to 0.
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immedi-
ately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter-
rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).7: Sets the PWMj pin to the high level.
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out-
put from the PWMj pin during the warm-up period time after exiting the STOP mode.
Note 4: j = 3, 4
Table 9-5 PWM Output Mode


fc/2 7
fc/2 7 – 8 µs – 2.05 ms –
fc/2 5
fc/2 5 – 2 µs – 512 µs –
fc/23 fc/23 – 500 ns – 128 µs –
fs fs fs 30.5 µs 30.5 µs 7.81 ms 7.81 ms
fc/2 fc/2 – 125 ns – 32 µs –
fc fc – 62.5 ns – 16 µs –
Page 93
9.1 Configuration
TC4CR<TC4S>
TC4CR<TFF4>
Internal
source clock
Counter 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p

Write to PWREG4 Write to PWREG4
PWREG4 ? n m p
Page 94
Shift Shift Shift Shift
Shift registar ? n m p
Timer F/F4
PWM4 pin n p
n m
One cycle period

Figure 9-5 8-Bit PWM Mode Timing Chart (TC4)

TMP86CM29LUG
TMP86CM29LUG

In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad-
able to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 3, 4
Table 9-6 Source Clock for 16-Bit Timer Mode


fc/211 fs/23 fs/23 128 µs 244.14 µs 8.39 s 16 s
fc/27 fc/27 – 8 µs – 524.3 ms –
fc/25 fc/25 – 2 µs – 131.1 ms –
fc/23 fc/23 – 500 ns – 32.8 ms –
Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
LDW (TTREG3), 927CH : Sets the timer register (300 ms÷27/fc = 927CH).
DI
EI
LD (TC3CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode
(lower byte).
LD (TC4CR), 04H : Sets the 16-bit timer mode (upper byte).
LD (TC4CR), 0CH : Starts the timer.
TC4CR<TC4S>
Internal
source clock
Counter 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0
TTREG3 ? n
(Lower byte)
TTREG4 ? m
(Upper byte)
Match Counter Match Counter
detect clear detect clear
Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
Page 95
9.1 Configuration
TMP86CM29LUG
9.3.6 16-Bit Event Counter Mode (TC3 and 4)
In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3
and 4 are cascadable to form a 16-bit event counter.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after
the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is
cleared.
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC3 pin.
Two machine cycles are required for the low- or high-level pulse input to the TC3 pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 in
the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG3), and upper byte (TTREG4) in this
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect imme-
diately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
Note 3: j = 3, 4
9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)
TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the
logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC4 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maxi-
mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or
SLEEP1/2 mode.
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
generated. Upon reset, the timer F/F4 is cleared to 0.
(The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.)
Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to
PWREG4 and 3 can be changed while the timer is running. The values set to PWREG4 and 3 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG4 and 3. While the timer is
stopped, the values are shifted immediately after the programming of PWREG4 and 3. Set the lower byte
(PWREG3) and upper byte (PWREG3) in this order to program PWREG4 and 3. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG4 and 3 during PWM output, the values set in the shift register is
read, but not the values set in PWREG4 and 3. Therefore, after writing to the PWREG4 and 3, reading data of
PWREG4 and 3 is previous value until INTTC4 is generated.
Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt
request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC4 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not program
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing thePWM4 pin to the high level when the TimerCounter is stopped
Page 96
TMP86CM29LUG
CLR (TC4CR).3: Stops the timer.

CLR (TC4CR).7 : Sets the PWM4 pin to the high level.
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with-
out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4
pin during the warm-up period time after exiting the STOP mode.
Table 9-7 16-Bit PWM Output Mode


fc/211 fs/23 [Hz] fs/23 [Hz] 128 µs 244.14 µs 8.39 s 16 s
fc/27 fc/27 – 8 µs – 524.3 ms –
fc/25 fc/25 – 2 µs – 131.1 ms –
fc/23 fc/23 – 500ns – 32.8 ms –
fs fs fs 30.5 µs 30.5 µs 2 s 2s
fc/2 fc/2 – 125 ns – 8.2 ms –
fc fc – 62.5 ns – 4.1 ms –
Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)
Setting ports
LDW (PWREG3), 07D0H : Sets the pulse width.
LD (TC3CR), 33H : Sets the operating clock to fc/23, and 16-bit PWM output
mode (lower byte).
LD (TC4CR), 056H : Sets TFF4 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
LD (TC4CR), 05EH : Starts the timer.
Page 97
9.1 Configuration
TC4CR<TC4S>
TC4CR<TFF4>
Internal
source clock
Counter 0 1 an an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 FFFF 0 1 cp

PWREG3
(Lower byte) ? n m p
Page 98
PWREG4 a
(Upper byte) ? b c
16-bit ? an bm cp
shift register
Timer F/F4
PWM4 pin an cp
an bm
One cycle period

Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4)
TMP86CM29LUG
TMP86CM29LUG
9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad-
able to enter the 16-bit PPG mode.
The counter counts up using the internal clock or external clock. When a match between the up-counter and
the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is
switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is
switched to the opposite state again when a match between the up-counter and the timer register (TTREG3,
TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.
mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or
SLEEP1/2 mode.
(The logic level output from the PPG4 pin is the opposite to the timer F/F4.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4,
PWREG3 → PWREG4) (Programming only the upper or lower byte should not be attempted.)
For PPG output, set the output latch of the I/O port to 1.
Setting ports
LDW (TTREG3), 8002H : Sets the cycle period.
: Sets the operating clock to fc/23, and16-bit PPG mode

LD (TC3CR), 33H
(lower byte).
: Sets TFF4 to the initial value 0, and 16-bit

LD (TC4CR), 057H
PPG mode (upper byte).
LD (TC4CR), 05FH : Starts the timer.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values pro-
grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change
Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped
CLR (TC4CR).3: Stops the timer
CLR (TC4CR).7: Sets the PPG4 pin to the high level
Note 3: i = 3, 4
Page 99
9.1 Configuration
TC4CR<TC4S>
Internal
source clock
Counter 0 1 mn mn+1 qr-1 qr 0 1 mn mn+1 qr-1 qr 0 1 mn mn+1 0
PWREG3
(Lower byte) ? n
PWREG4
(Upper byte) ? m
Page 100
Match detect Match detect Match detect
TTREG3
(Lower byte) ? r
TTREG4
(Upper byte) ? q
Match detect Match detect F/F clear
Timer F/F4
stops
PPG4 pin
mn mn mn
Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40)
TMP86CM29LUG
TMP86CM29LUG
9.3.9 Warm-Up Counter Mode

In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a
16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match
detection and lower 8 bits are not used.
Note 3: i = 3, 4

In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XTEN> to
0 to stop the high-frequency clock.
Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Maximum Time Setting Maximum Time Setting

(TTREG4, 3 = 0100H) (TTREG4, 3 = FF00H)
7.81 ms 1.99 s
Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode
SET (SYSCR2).6 : SYSCR2<XTEN> ← 1
LD (TC3CR), 43H : Sets TFF3=0, source clock fs, and 16-bit mode.
LD (TC4CR), 05H : Sets TFF4=0, and warm-up counter mode.
: Sets the warm-up time.

LD (TTREG3), 8000H
(The warm-up time depends on the oscillator characteristic.)
DI : IMF ← 0
SET (EIRH). 3 : Enables the INTTC4.
EI : IMF ← 1
SET (TC4CR).3 : Starts TC4 and 3.
: :
PINTTC4: CLR (TC4CR).3 : Stops TC4 and 3.
SET (SYSCR2).5 : SYSCR2<SYSCK> ← 1

(Switches the system clock to the low-frequency clock.)
CLR (SYSCR2).7 : SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
RETI
: :
VINTTC4: DW PINTTC4 : INTTC4 vector table
Page 101
9.1 Configuration
TMP86CM29LUG

In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta-
bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.
request. After stopping the timer in the INTTC4 interrupt service routine, clear SYSCR2<SYSCK> to 0 to
switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to
stop the low-frequency clock.
Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode
Minimum time (TTREG4, 3 = 0100H) Maximum time (TTREG4, 3 = FF00H)
16 µs 4.08 ms
Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode
SET (SYSCR2).7 : SYSCR2<XEN> ← 1
LD (TTREG3), 0F800H : Sets the warm-up time.

DI : IMF ← 0
EI : IMF ← 1
SET (TC4CR).3 : Starts the TC4 and 3.
: :
PINTTC4: CLR (TC4CR).3 : Stops the TC4 and 3.
CLR (SYSCR2).5 : SYSCR2<SYSCK> ← 0

(Switches the system clock to the high-frequency clock.)
CLR (SYSCR2).6 : SYSCR2<XTEN> ← 0

(Stops the low-frequency clock.)
RETI
: :
Page 102
TMP86CM29LUG
10.1 Configuration
PWM mode
Overflow
INTTC6
interrupt request
fc/211 or fs/23 A Clear
fc/2
7
B Y A Y 8-bit up-counter
fc/2
5
C B TC6S
3
fc/2 D S PDO, PPG mode
fs E A
fc/2 F Toggle
16-bit mode Y
fc G B Q
TC6 pin H S Set PDO6/PWM6/
S 16-bit Timer, Event
mode Counter mode Clear PPG6 pin
TC6M S
TC6S TC6CK Timer F/F6
TFF6 A
Y
TC6CR B
TTREG6 PWREG6 PWM, PPG mode DecodeEN PDO, PWM,
PPG mode
TFF6
16-bit
mode
TC5S
fc/211 or fs/23 Clear INTTC5

A interrupt request
7
fc/2 B Y 8-bit up-counter
Overflow 16-bit mode
fc/25 C
3
fc/2 D
fs E
fc/2 F
fc G Timer mode
S
TC5M
TC5S TC5CK
TC5CR
TTREG5 PWREG5
Figure 10-1 8-Bit TimerCouter 5, 6
Page 103
10.1 Configuration
TMP86CM29LUG
10.2 TimerCounter Control

(TTREG5, PWREG5).
TTREG5 7 6 5 4 3 2 1 0
(001EH)
PWREG5 7 6 5 4 3 2 1 0
(002EH)
TC5CR 7 6 5 4 3 2 1 0
(001AH) TC5CK TC5S TC5M (Initial value: ∗000 0000)

SLEEP1/2
000 fc/211 fs/23 fs/23
001 fc/27 fc/27 –
010 fc/25 fc/25 –

011 fc/23 fc/23 –
100 fs fs fs
101 fc/2 fc/2 –
110 fc fc fc (Note 8)
111 Reserved

1: Operation start
000: 8-bit timer

001: Reserved
010: Reserved
011: 16-bit mode
(Each mode is selectable with TC6M.)
1**: Reserved
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz]

Note 3: To stop the timer operation (TC5S= 1 → 0), do not change the TC5M and TC5CK settings. To start the timer operation
(TC5S= 0 → 1), TC5M and TC5CK can be programmed.
Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR<TC6M>, where TC5M must
be fixed to 011.
Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC5CK. Set the timer start control
and timer F/F control by programming TC6CR<TC6S> and TC6CR<TFF6>, respectively.
10-1 and Table 10-2.
3.
Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.
Page 104
TMP86CM29LUG
(TTREG6 and PWREG6).
TTREG6 7 6 5 4 3 2 1 0
(001FH)
PWREG6 7 6 5 4 3 2 1 0
(002FH) R/
W (Initial value: 1111 1111)
TC6CR 7 6 5 4 3 2 1 0
(001BH) TFF6 TC6CK TC6S TC6M (Initial value: 0000 0000)
0: Clear
TFF6 Timer F/F6 control R/W
1: Set

SLEEP1/2
000 fc/211 fs/23 fs/23
001 fc/27 fc/27 –
010 fc/25 fc/25 –

011 3 3 –
fc/2 fc/2
100 fs fs fs
101 fc/2 fc/2 –
110 fc fc –
111 TC6 pin input

1: Operation start

011: Reserved
101: Warm-up counter mode
111: 16-bit PPG mode
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz]

Note 3: To stop the timer operation (TC6S= 1 → 0), do not change the TC6M, TC6CK and TFF6 settings.
To start the timer operation (TC6S= 0 → 1), TC6M, TC6CK and TFF6 can be programmed.
Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC6 overflow signal regardless of the
TC5CK setting.
Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR<TC5 M>
must be set to 011.
Page 105
10.1 Configuration
TMP86CM29LUG
Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start
control and timer F/F control by programming TC6S and TFF6, respectively.
10-1 and Table 10-2.
3.
Note 9: To use the PDO, PWM or PPG mode, a pulse is not output from the timer output pin when TC1CR2<TC6OUT> is set to 1.
To output a pulse from the timer output pin, clear TC1CR2<TC6OUT> to 0.
Table 10-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes)
fc/211
TC5 TC6
pin input pin input
3
fs/2
8-bit event counter – – – – – – – – Ο
8-bit PDO Ο Ο Ο Ο – – – – –
Warm-up counter – – – – Ο – – – –
16-bit PPG Ο Ο Ο Ο – – – – –
Note 1: For 16-bit operations (16-bit timer, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit
(TC5CK).
Note 2: Ο : Available source clock
Table 10-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes)
fc/211
TC5 TC6
pin input pin input
fs/23
8-bit timer Ο – – – – – – – –
8-bit event counter – – – – – – – – Ο
8-bit PDO Ο – – – – – – – –
8-bit PWM Ο – – – Ο – – – –
16-bit timer Ο – – – – – – – –
Warm-up counter – – – – – – Ο – –
16-bit PWM Ο – – – Ο – – – –
16-bit PPG Ο – – – – – – – –
Note1: For 16-bit operations (16-bit timer, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit
(TC5CK).
Note2: Ο : Available source clock
Page 106
TMP86CM29LUG
Table 10-3 Constraints on Register Values Being Compared
Operating mode Register Value
8-bit timer/event counter 1≤ (TTREGn) ≤255
8-bit PDO 1≤ (TTREGn) ≤255
8-bit PWM 2≤ (PWREGn) ≤254
16-bit timer 1≤ (TTREG6, 5) ≤65535
Warm-up counter 256≤ (TTREG6, 5) ≤65535
16-bit PWM 2≤ (PWREG6, 5) ≤65534
1≤ (PWREG6, 5) < (TTREG6, 5) ≤65535

16-bit PPG and
(PWREG6, 5) + 1 < (TTREG6, 5)
Note: n = 5 to 6
Page 107
10.1 Configuration
TMP86CM29LUG
10.3 Function
The TimerCounter 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-bit
pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16-bit
timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-
bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.

In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
Note 3: j = 5, 6
Table 10-4 Source Clock for TimerCounter 5, 6 (Internal Clock)

fc/27 fc/27 – 8 µs – 2.0 ms –
fc/25 fc/25 – 2 µs – 510 µs –
fc/23 fc/23 – 500 ns – 127.5 µs –
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later
(TimerCounter6, fc = 16.0 MHz)
LD (TTREG6), 0AH : Sets the timer register (80 µs÷27/fc = 0AH).
DI
EI
LD (TC6CR), 00010000B : Sets the operating cock to fc/27, and 8-bit timer mode.
Page 108
TMP86CM29LUG
TC6CR<TC6S>
Internal
Source Clock
Counter 1 2 3 n-1 n 0 1 2 n-1 n 0 1 2 0
TTREG6 ? n

Figure 10-2 8-Bit Timer Mode Timing Chart (TC6)
10.3.2 8-Bit Event Counter Mode (TC6)

In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 6
TC6CR<TC6S>
TC6 pin input
Counter 0 1 2 n-1 n 0 1 2 n-1 n 0 1 2 0
TTREG6 ? n
Match detect Counter Counter

clear Match detect
INTTC6 interrupt request clear
Figure 10-3 8-Bit Event Counter Mode Timing Chart (TC6)
10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC6)

This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
Page 109
10.1 Configuration
TMP86CM29LUG
Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz)

Setting port
LD (TTREG6), 3DH : 1/1024÷27/fc÷2 = 3DH
LD (TC6CR), 00010001B : Sets the operating clock to fc/27, and 8-bit PDO mode.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).7: Sets the PDOj pin to the high level.
Note 3: j = 6
Page 110
TC6CR<TC6S>
Internal
source clock
Counter 0 1 2 n 0 1 2 n 0 1 2 n 0 1 2 n 0 1 2 3 0
Page 111
TTREG6 ? n
Timer F/F6 Set F/F
PDO6 pin

INTTC6 interrupt request is stopped
Figure 10-4 8-Bit PDO Mode Timing Chart (TC6)

TMP86CM29LUG
10.1 Configuration
TMP86CM29LUG
10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6)

up-counter counts up using the internal clock.
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen-
erated. Upon reset, the timer F/Fj is cleared to 0.
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immedi-
ately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter-
rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).7: Sets the PWMj pin to the high level.
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out-
put from the PWMj pin during the warm-up period time after exiting the STOP mode.
Note 4: j = 6
Table 10-5 PWM Output Mode


fc/2 7
fc/2 7 – 8 µs – 2.05 ms –
fc/2 5
fc/2 5 – 2 µs – 512 µs –
fc/23 fc/23 – 500 ns – 128 µs –
fs fs fs 30.5 µs 30.5 µs 7.81 ms 7.81 ms
fc/2 fc/2 – 125 ns – 32 µs –
fc fc – 62.5 ns – 16 µs –
Page 112
TC6CR<TC6S>
TC6CR<TFF6>
Internal
source clock
Counter 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p

PWREG6 ? n m p
Page 113
Shift registar ? n m p
Timer F/F6
PWM6 pin n p
n m
One cycle period

Figure 10-5 8-Bit PWM Mode Timing Chart (TC6)

TMP86CM29LUG
10.1 Configuration
TMP86CM29LUG

In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad-
able to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the
timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 5, 6
Table 10-6 Source Clock for 16-Bit Timer Mode


fc/211 fs/23 fs/23 128 µs 244.14 µs 8.39 s 16 s
fc/27 fc/27 – 8 µs – 524.3 ms –
fc/25 fc/25 – 2 µs – 131.1 ms –
fc/23 fc/23 – 500 ns – 32.8 ms –
Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
LDW (TTREG5), 927CH : Sets the timer register (300 ms÷27/fc = 927CH).
DI
EI
LD (TC5CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode
(lower byte).
LD (TC6CR), 04H : Sets the 16-bit timer mode (upper byte).
LD (TC6CR), 0CH : Starts the timer.
TC6CR<TC6S>
Internal
source clock
Counter 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0
TTREG5 ? n
(Lower byte)
TTREG6 ? m
(Upper byte)
Match Counter Match Counter
detect clear detect clear
Figure 10-6 16-Bit Timer Mode Timing Chart (TC5 and TC6)
Page 114
TMP86CM29LUG
10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)
TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock.
When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the
logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC6 interrupt is generated at this time.
mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or
SLEEP1/2 mode.
(The logic level output from the PWM6 pin is the opposite to the timer F/F6 logic level.)
Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to
PWREG6 and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG6 and 5. While the timer is
stopped, the values are shifted immediately after the programming of PWREG6 and 5. Set the lower byte
(PWREG5) and upper byte (PWREG5) in this order to program PWREG6 and 5. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG6 and 5 during PWM output, the values set in the shift register is
read, but not the values set in PWREG6 and 5. Therefore, after writing to the PWREG6 and 5, reading data of
PWREG6 and 5 is previous value until INTTC6 is generated.
Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt
request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC6 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not program
Example: Fixing thePWM6 pin to the high level when the TimerCounter is stopped
CLR (TC6CR).3: Stops the timer.
CLR (TC6CR).7 : Sets the PWM6 pin to the high level.
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with-
out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM6
pin during the warm-up period time after exiting the STOP mode.
Table 10-7 16-Bit PWM Output Mode


fc/211 fs/23 [Hz] fs/23 [Hz] 128 µs 244.14 µs 8.39 s 16 s
fc/2 7
fc/2 7 – 8 µs – 524.3 ms –
fc/2 5
fc/2 5 – 2 µs – 131.1 ms –
3 3 – 500ns – 32.8 ms –
fc/2 fc/2
fs fs fs 30.5 µs 30.5 µs 2 s 2s
fc/2 fc/2 – 125 ns – 8.2 ms –
fc fc – 62.5 ns – 4.1 ms –
Page 115
10.1 Configuration
TMP86CM29LUG
Setting ports
LD (TC5CR), 33H : Sets the operating clock to fc/23, and 16-bit PWM output
mode (lower byte).
LD (TC6CR), 056H : Sets TFF6 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
LD (TC6CR), 05EH : Starts the timer.
Page 116
TC6CR<TC6S>
TC6CR<TFF6>
Internal
source clock
Counter 0 1 an an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 FFFF 0 1 cp

PWREG5
(Lower byte) ? n m p
PWREG6
Page 117
(Upper byte) ? a b c
16-bit ? an bm cp
shift register
Timer F/F6
PWM6 pin an cp
an bm
One cycle period

Figure 10-7 16-Bit PWM Mode Timing Chart (TC5 and TC6)
TMP86CM29LUG
10.1 Configuration
TMP86CM29LUG
10.3.7 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6)
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascad-
able to enter the 16-bit PPG mode.
The counter counts up using the internal clock. When a match between the up-counter and the timer register
(PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite
state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite
state again when a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected,
and the counter is cleared. The INTTC6 interrupt is generated at this time.
(The logic level output from the PPG6 pin is the opposite to the timer F/F6.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG5 → TTREG6,
PWREG5 → PWREG6) (Programming only the upper or lower byte should not be attempted.)
For PPG output, set the output latch of the I/O port to 1.
Setting ports
LDW (TTREG5), 8002H : Sets the cycle period.
: Sets the operating clock to fc/23, and16-bit PPG mode

LD (TC5CR), 33H
(lower byte).
: Sets TFF6 to the initial value 0, and 16-bit

LD (TC6CR), 057H
PPG mode (upper byte).
LD (TC6CR), 05FH : Starts the timer.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values pro-
grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
Note 2: When the timer is stopped during PPG output, the PPG6 pin holds the output status when the timer is
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not change
Example: Fixing the PPG6 pin to the high level when the TimerCounter is stopped
CLR (TC6CR).3: Stops the timer
CLR (TC6CR).7: Sets the PPG6 pin to the high level
Note 3: i = 5, 6
Page 118
TC6CR<TC6S>
Internal
source clock
Counter 0 1 mn mn+1 qr-1 qr 0 1 mn mn+1 qr-1 qr 0 1 mn mn+1 0
PWREG5
(Lower byte) ? n
PWREG6
(Upper byte) ? m
Page 119
Match detect Match detect Match detect
TTREG5
(Lower byte) ? r
TTREG6
(Upper byte) ? q
Match detect Match detect F/F clear
Timer F/F6
stops
PPG6 pin
mn mn mn
Figure 10-8 16-Bit PPG Mode Timing Chart (TC5 and TC60)
TMP86CM29LUG
10.1 Configuration
TMP86CM29LUG
10.3.8 Warm-Up Counter Mode

In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a
16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG6 and 5 are used for match
detection and lower 8 bits are not used.
Note 3: i = 5, 6

In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
request. After stopping the timer in the INTTC6 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XTEN> to
0 to stop the high-frequency clock.
Table 10-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Maximum Time Setting Maximum Time Setting

(TTREG6, 5 = 0100H) (TTREG6, 5 = FF00H)
7.81 ms 1.99 s
Example :After checking low-frequency clock oscillation stability with TC6 and 5, switching to the SLOW1 mode
SET (SYSCR2).6 : SYSCR2<XTEN> ← 1
: Sets the warm-up time.

LD (TTREG5), 8000H
DI : IMF ← 0
EI : IMF ← 1
SET (TC6CR).3 : Starts TC6 and 5.
: :
PINTTC6: CLR (TC6CR).3 : Stops TC6 and 5.
SET (SYSCR2).5 : SYSCR2<SYSCK> ← 1

(Switches the system clock to the low-frequency clock.)
CLR (SYSCR2).7 : SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
RETI
: :
Page 120
TMP86CM29LUG

In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta-
bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.
request. After stopping the timer in the INTTC6 interrupt service routine, clear SYSCR2<SYSCK> to 0 to
switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to
stop the low-frequency clock.
Table 10-9 Setting Time in High-Frequency Warm-Up Counter Mode
Minimum time (TTREG6, 5 = 0100H) Maximum time (TTREG6, 5 = FF00H)
16 µs 4.08 ms
Example :After checking high-frequency clock oscillation stability with TC6 and 5, switching to the NORMAL1 mode
SET (SYSCR2).7 : SYSCR2<XEN> ← 1
LD (TTREG5), 0F800H : Sets the warm-up time.

DI : IMF ← 0
EI : IMF ← 1
SET (TC6CR).3 : Starts the TC6 and 5.
: :
PINTTC6: CLR (TC6CR).3 : Stops the TC6 and 5.
CLR (SYSCR2).5 : SYSCR2<SYSCK> ← 0

(Switches the system clock to the high-frequency clock.)
CLR (SYSCR2).6 : SYSCR2<XTEN> ← 0

(Stops the low-frequency clock.)
RETI
: :
Page 121
10.1 Configuration
TMP86CM29LUG
Page 122
TMP86CM29LUG
11.1 Configuration
UART control register 1 Transmit data buffer

Receive data buffer
UARTCR1 TDBUF
RDBUF
3 2
2
Receive control circuit

Shift register
Transmit control circuit
Parity bit
Shift register
Stop bit
INTTXD Noise rejection
circuit RXD
TXD
INTRXD
Transmit/receive clock
Y
6
M A fc/2
P B fc/27
S X C fc/2
8
fc/13 A S
fc/26 B
fc/52 C 2 4
fc/104 D Y Counter 2
fc/208 E UARTSR UARTCR2
fc/416 F
INTTC5 G UART status register UART control register 2
fc/96 H MPX: Multiplexer
Baud rate generator
Figure 11-1 UART (Asynchronous Serial Interface)
Page 123
11.2 Control
TMP86CM29LUG
11.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni-
tored using the UART status register (UARTSR).
UART Control Register1
UARTCR1 7 6 5 4 3 2 1 0
(0025H) TXE RXE STBT EVEN PE BRG (Initial value: 0000 0000)
0: Disable
TXE Transfer operation
1: Enable
0: Disable
RXE Receive operation
1: Enable
0: 1 bit
STBT Transmit stop bit length
1: 2 bits
0: Odd-numbered parity
EVEN Even-numbered parity
1: Even-numbered parity
Write
0: No parity
PE Parity addition only
1: Parity
000: fc/13 [Hz]

001: fc/26
010: fc/52
011: fc/104
BRG Transmit clock select
100: fc/208
101: fc/416
110: TC5 ( Input INTTC5)
111: fc/96
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
UART Control Register2
UARTCR2 7 6 5 4 3 2 1 0
(0026H) RXDNC STOPBR (Initial value: **** *000)
00: No noise rejection (Hysteresis input)

Selection of RXD input noise 01: Rejects pulses shorter than 31/fc [s] as noise
RXDNC
rejectio time 10: Rejects pulses shorter than 63/fc [s] as noise Write
11: Rejects pulses shorter than 127/fc [s] as noise only
0: 1 bit
STOPBR Receive stop bit length
1: 2 bits
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
Page 124
TMP86CM29LUG
UART Status Register
UARTSR 7 6 5 4 3 2 1 0
(0025H) PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**)
0: No parity error
PERR Parity error flag
1: Parity error
0: No framing error
FERR Framing error flag
1: Framing error
0: No overrun error
OERR Overrun error flag
1: Overrun error Read
0: Receive data buffer empty only
RBFL Receive data buffer full flag
1: Receive data buffer full
0: On transmitting
TEND Transmit end flag
1: Transmit end
0: Transmit data buffer full (Transmit data writing is finished)

TBEP Transmit data buffer empty flag
1: Transmit data buffer empty
Note: When an INTTXD is generated, TBEP flag is set to "1" automatically.
UART Receive Data Buffer
RDBUF 7 6 5 4 3 2 1 0 Read only

(0F9BH) (Initial value: 0000 0000)
UART Transmit Data Buffer
TDBUF 7 6 5 4 3 2 1 0 Write only

(0F9BH) (Initial value: 0000 0000)
Page 125
11.3 Transfer Data Format
TMP86CM29LUG
11.3 Transfer Data Format

In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and
parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the
transfer data. The transfer data formats are shown as follows.
Frame Length
PE STBT
1 2 3 8 9 10 11 12
0 0 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1
0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2
1 0 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1
1 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2
Figure 11-2 Transfer Data Format
Without parity / 1 STOP bit
With parity / 1 STOP bit Without parity / 2 STOP bit
With parity / 2 STOP bit
Figure 11-3 Caution on Changing Transfer Data Format
Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except
for the initial setting.
Page 126
TMP86CM29LUG
11.4 Transfer Rate

The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows.
Table 11-1 Transfer Rate (Example)
Source Clock
BRG
16 MHz 8 MHz 4 MHz
000 76800 [baud] 38400 [baud] 19200 [baud]
001 38400 19200 9600
010 19200 9600 4800
011 9600 4800 2400
100 4800 2400 1200
101 2400 1200 600
When TC5 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer
rate are determined as follows:
Transfer clock [Hz] = TC5 source clock [Hz] / TTREG5 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
11.5 Data Sampling Method

The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG> until a start bit is
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
RXD pin Start bit Bit 0
RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
RT clock
Internal receive data Start bit Bit 0
(a) Without noise rejection circuit
RXD pin Start bit Bit 0
RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
RT clock
Internal receive data Start bit Bit 0
(b) With noise rejection circuit
Figure 11-4 Data Sampling Method
Page 127
11.6 STOP Bit Length
TMP86CM29LUG
11.6 STOP Bit Length

Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>.
11.7 Parity
Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>.
11.8 Transmit/Receive Operation
11.8.1 Data Transmit Operation

Set UARTCR1<TXE> to “1”. Read UARTSR to check UARTSR<TBEP> = “1”, then write data in TDBUF
(Transmit data buffer). Writing data in TDBUF zero-clears UARTSR<TBEP>, transfers the data to the transmit
shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit,
stop bits whose number is specified in UARTCR1<STBT> and a parity bit if parity addition is specified.
Select the data transfer baud rate using UARTCR1<BRG>. When data transmit starts, transmit buffer empty
flag UARTSR<TBEP> is set to “1” and an INTTXD interrupt is generated.
While UARTCR1<TXE> = “0” and from when “1” is written to UARTCR1<TXE> to when send data are
written to TDBUF, the TXD pin is fixed at high level.
When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR<TBEP> is not
zero-cleared and transmit does not start.
11.8.2 Data Receive Operation

Set UARTCR1<RXE> to “1”. When data are received via the RXD pin, the receive data are transferred to
RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR<RBFL> is set and an INTRXD
interrupt is generated. Select the data transfer baud rate using UARTCR1<BRG>.
If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive
data buffer) but discarded; data in the RDBUF are not affected.
Note:When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
Page 128
TMP86CM29LUG
11.9 Status Flag
11.9.1 Parity Error

When parity determined using the receive data bits differs from the received parity bit, the parity error flag
UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after read-
ing the UARTSR.
RXD pin Parity Stop
Shift register xxxx0** pxxxx0* 1pxxxx0
UARTSR<PERR> After reading UARTSR then

RDBUF clears PERR.
INTRXD interrupt
Figure 11-5 Generation of Parity Error
11.9.2 Framing Error

When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”.
The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin Final bit Stop
Shift register xxx0** xxxx0* 0xxxx0
UARTSR<FERR> After reading UARTSR then

RDBUF clears FERR.
INTRXD interrupt
Figure 11-6 Generation of Framing Error
11.9.3 Overrun Error

When all bits in the next data are received while unread data are still in RDBUF, overrun error flag
UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected.
The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Page 129
11.9 Status Flag
TMP86CM29LUG
UARTSR<RBFL>
RDBUF yyyy
UARTSR<OERR> After reading UARTSR then

RDBUF clears OERR.
INTRXD interrupt
Figure 11-7 Generation of Overrun Error
Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.
11.9.4 Receive Data Buffer Full

Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The
UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RDBUF yyyy xxxx
UARTSR<RBFL> After reading UARTSR then

RDBUF clears RBFL.
INTRXD interrupt
Figure 11-8 Generation of Receive Data Buffer Full
Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading
the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the
UARTSR again to check whether or not the overrun error flag which should have been cleared still remains
set.
11.9.5 Transmit Data Buffer Empty

When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF
are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag
UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after
reading the UARTSR.
Page 130
TMP86CM29LUG
Data write Data write
TDBUF xxxx yyyy zzzz
Shift register *****1 1xxxx0 *1xxxx ****1x *****1 1yyyy0
TXD pin Start Bit 0 Final bit Stop
UARTSR<TBEP>
After reading UARTSR writing TDBUF

INTTXD interrupt clears TBEP.
Figure 11-9 Generation of Transmit Data Buffer Empty
11.9.6 Transmit End Flag

When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag
UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is stated after
writing the TDBUF.
Shift register ***1xx ****1x *****1 1yyyy0 *1yyyy
TXD pin Stop Start Bit 0

Data write for TDBUF
UARTSR<TBEP>
UARTSR<TEND>
INTTXD interrupt
Figure 11-10 Generation of Transmit End Flag and Transmit Data Buffer Empty
Page 131
11.9 Status Flag
TMP86CM29LUG
Page 132
TMP86CM29LUG
The TMP86CM29LUG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit
and receive data buffer that can automatically and continuously transfer up to 64 bits of data.
Serial interface is connected to outside peripherl devices via SO, SI, SCK port.
12.1 Configuration
SIO control / status register
SIOSR SIOCR1 SIOCR2
CPU
Transmit and
receive data buffer
Buffer control (8 bytes in DBR)
Control circuit circuit
Shift register
Shift 7 6 5 4 3 2 1 0
SO
clock
Serial data output
8-bit transfer 4-bit transfer
SI
Serial data input
INTSIO interrupt request Serial clock SCK

Serial clock I/O
Figure 12-1 Serial Interface
Page 133
12.2 Control
TMP86CM29LUG
12.2 Control
The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be
determined by reading SIO status register (SIOSR).
The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data buffer is assigned to address
0F90H to 0F97H for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time.
When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in
the receive mode or transmit/receive mode) interrupt (INTSIO) is generated.
When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a
fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be
selected with SIOCR2<WAIT>.
SIO Control Register 1

SIOCR1 7 6 5 4 3 2 1 0
(0F98H) SIOS SIOINH SIOM SCK (Initial value: 0000 0000)
0: Stop
SIOS Indicate transfer start / stop
1: Start
0: Continuously transfer
SIOINH Continue / abort transfer
1: Abort transfer (Automatically cleared after abort)
000: 8-bit transmit mode Write

010: 4-bit transmit mode only
100: 8-bit transmit / receive mode

SIOM Transfer mode select
101: 8-bit receive mode
110: 4-bit receive mode
Except the above: Reserved

SLEEP1/2
000 fc/213 fs/25 fs/25
001 fc/28 fc/28 -
010 fc/27 fc/27 - Write

SCK Serial clock select
only
011 fc/26 fc/26 -
100 fc/25 fc/25 -
101 fc/24 fc/24 -
110 Reserved
111 External clock ( Input from SCK pin )
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz]

Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock.
Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Control Register 2

SIOCR2 7 6 5 4 3 2 1 0
(0F99H) WAIT BUF (Initial value: ***0 0000)
Page 134
TMP86CM29LUG
Always sets "00" except 8-bit transmit / receive mode.
00: Tf = TD(Non wait)
WAIT Wait control 01: Tf = 2TD(Wait)
10: Tf = 4TD(Wait)
11: Tf = 8TD (Wait)
000: 1 word transfer 0F90H

Write
001: 2 words transfer 0F90H ~ 0F91H only
010: 3 words transfer 0F90H ~ 0F92H
Number of transfer words 011: 4 words transfer 0F90H ~ 0F93H

BUF
(Buffer address in use) 100: 5 words transfer 0F90H ~ 0F94H
Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving.
Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest
address. ( The first buffer address transmitted is 0F90H ).
Note 3: The value to be loaded to BUF is held after transfer is completed.
Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0).
Note 5: *: Don't care
Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Status Register

SIOSR 7 6 5 4 3 2 1 0
(0F99H) SIOF SEF
Serial transfer operating status moni- 0: Transfer terminated

SIOF
tor 1: Transfer in process Read
0: Shift operation terminated only
SEF Shift operating status monitor
1: Shift operation in process
Note 1: Tf; Frame time, TD; Data transfer time

Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1".
(output)
SCK output
TD
Tf
Figure 12-2 Frame time (Tf) and Data transfer time (TD)
12.3 Serial clock
12.3.1 Clock source

Internal clock or external clock for the source clock is selected by SIOCR1<SCK>.
Page 135
12.3 Serial clock
TMP86CM29LUG
12.3.1.1 Internal clock
Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The
SCK pin goes high when transfer starts.
When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode)
cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock
and holds the next shift operation until the read/write processing is completed.
Table 12-1 Serial Clock Rate

DV7CK = 0 DV7CK = 1 SLEEP1/2 mode
SCK Clock Baud Rate Clock Baud Rate Clock Baud Rate
000 fc/213 1.91 Kbps fs/25 1024 bps fs/25 1024 bps
001 fc/28 61.04 Kbps fc/28 61.04 Kbps - -
010 fc/27 122.07 Kbps fc/27 122.07 Kbps - -
011 fc/26 244.14 Kbps fc/26 244.14 Kbps - -
100 fc/25 488.28 Kbps fc/25 488.28 Kbps - -
101 fc/24 976.56 Kbps fc/24 976.56 Kbps - -
110 - - - - - -
111 External External External External External External
Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz)
Automatically
wait function
SCK
pin (output)
SO a0 a1 a2 a3 b0 b1 b2 b3 c0 c1
pin (output)
Written transmit
data a b c
Figure 12-3 Automatic Wait Function (at 4-bit transmit mode)
12.3.1.2 External clock
An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this
port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This
pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for
interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the pro-
gram. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz).
SCK
pin (Output)
tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes)
tSCKL tSCKH 4/fs (In the SLOW1/2, SLEEP1/2 modes)
tSCKL, tSCKH > 4tcyc
Figure 12-4 External clock pulse width
Page 136
TMP86CM29LUG
12.3.2 Shift edge

The leading edge is used to transmit, and the trailing edge is used to receive.
12.3.2.1 Leading edge
Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/
output).
12.3.2.2 Trailing edge
Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/out-
put).
SCK pin
SO pin Bit 0 Bit 1 Bit 2 Bit 3
Shift register 3210 *321 **32 ***3

(a) Leading edge
SCK pin
SI pin Bit 0 Bit 1 Bit 2 Bit 3
Shift register **** 0*** 10** 210* 3210 *; Don’t care

(b) Trailing edge
Figure 12-5 Shift edge
12.4 Number of bits to transfer

Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of
the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving.
The data is transferred in sequence starting at the least significant bit (LSB).
12.5 Number of words to transfer

Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be trans-
ferred continuously. The number of words to be transferred can be selected by SIOCR2<BUF>.
An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of
words is to be changed during transfer, the serial interface must be stopped before making the change. The number of
words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not
required to be stopped.
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12.6 Transfer Mode
TMP86CM29LUG
SCK pin
SO pin a0 a1 a2 a3
INTSIO interrupt
(a) 1 word transmit
SCK pin
SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3
INTSIO interrupt
(b) 3 words transmit
SCK pin
SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3
INTSIO interrupt
(c) 3 words receive
Figure 12-6 Number of words to transfer (Example: 1word = 4bit)
12.6 Transfer Mode

SIOCR1<SIOM> is used to select the transmit, receive, or transmit/receive mode.
12.6.1 4-bit and 8-bit transfer modes

In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data
(number of transfer words to be transferred) to the data buffer registers (DBR).
After the data are written, the transmission is started by setting SIOCR1<SIOS> to “1”. The data are then
output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit
(LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift
register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (Buffer
empty) interrupt is generated to request the next transmitted data.
When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next
transmitted data are not loaded to the data buffer register by the time the number of data words specified with
the SIOCR2<BUF> has been transmitted. Writing even one word of data cancels the automatic-wait; therefore,
when transmitting two or more words, always write the next word before transmission of the previous word is
completed.
Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; there-
fore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do
not use the DBR of the remained 5 words.
When an external clock is used, the data must be written to the data buffer register before shifting next data.
Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request
to writing of the data to the data buffer register by the interrupt service program.
The transmission is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer
empty interrupt service program.
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TMP86CM29LUG
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
“0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7
INTSIO interrupt
DBR a b
Write Write
(a) (b)
Figure 12-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Input)
INTSIO interrupt
DBR a b
Write Write
(a) (b)
Figure 12-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
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12.6 Transfer Mode
TMP86CM29LUG
SCK pin
SIOSR<SIOF>
SO pin MSB of last word
tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)

tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-9 Transmiiied Data Hold Time at End of Transfer
12.6.2 4-bit and 8-bit receive modes

After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The
data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word
of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the
number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is
generated to request that these data be read out. The data are then read from the data buffer registers by the
interrupt service program.
When the internal clock is used, and the previous data are not read from the data buffer register before the
next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.
A wait will not be initiated if even one data word has been read.
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,
during SIO do not use such DBR for other applications.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay
between the time when the interrupt request is generated and when the data received have been read.
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has
ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiv-
ing is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIO-
INH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is
ignored, and it is not required to be read out.)
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read
out.
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans-
fer mode.
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TMP86CM29LUG
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SI pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7
INTSIO Interrupt
DBR a b
Read out Read out
Figure 12-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)
12.6.3 8-bit transfer / receive mode

After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first
to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”.
When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving,
the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit
data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when
the number of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive
data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and
receiving; therefore, always write the data to be transmitted after reading the all received data.
When the internal clock is used, a wait is initiated until the received data are read and the next transfer data
are written. A wait will not be initiated if even one transfer data word has been written.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is
necessary to read the received data and write the data to be transmitted next before starting the next shift oper-
ation. When an external clock is used, the transfer speed is determined by the maximum delay between genera-
tion of an interrupt request and the received data are read and the data to be transmitted next are written.
The transmit/receive operation is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to

“1” in INTSIO interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.
That the transmitting/receiving has ended can be determined from the status of SIOSR<SIOF>.
SIOSR<SIOF> is cleared to “0” when the transmitting/receiving is ended.
When SIOCR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIOSR<SIOF> is
cleared to “0”.
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”.
If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of transmit/receive operation, SIOCR2<BUF> must be rewritten before reading and
writing of the receive/transmit data.
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12.6 Transfer Mode
TMP86CM29LUG
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans-
fer mode.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(output)
SI pin c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
INTSIO interrupt
DBR a c b d
Write (a) Read out (c) Write (b) Read out (d)
Figure 12-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock)
SCK pin
SIOSR<SIOF>
SO pin Bit 6 Bit 7 of last word
tSODH = min 4/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)

tSODH = min 4/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-12 Transmitted Data Hold Time at End of Transfer / Receive
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TMP86CM29LUG
The TMP86CM29LUG have a 10-bit successive approximation type AD converter.
13.1 Configuration
The circuit configuration of the 10-bit AD converter is shown in Figure 13-1.
It consists of control register ADCCR1 and ADCCR2, converted value register ADCDR1 and ADCDR2, a DA
converter, a sample-hold circuit, a comparator, and a successive comparison circuit.
DA converter
VAREF VSS
R/2 R R/2
AVDD Reference
Analog input
Sample hold voltage
multiplexer
circuit
AIN0 A Y

10
Analog
comparator
AIN7 n Successive approximate circuit
S EN Shift clock
INTADC
Control circuit
4
IREFON
AINDS
ADRS
SAIN 8 2 EOCF ADBF

2 3
AMD ACK
ADCCR1 ADCCR2 ADCDR1 ADCDR2
AD converter control register 1, 2 AD conversion result register 1, 2
Note: Before using AD converter, set appropriate value to I/O port register conbining a analog input port. For details, see the sec-
tion on "I/O ports".
Figure 13-1 10-bit AD Converter
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13.2 Register configuration
TMP86CM29LUG

The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)

This register selects the analog channels and operation mode (Software start or repeat) in which to per-
form AD conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (Ladder
resistor network).
3. AD converted value register 1 (ADCDR1)
This register used to store the digital value fter being converted by the AD converter.
4. AD converted value register 2 (ADCDR2)
This register monitors the operating status of the AD converter.
AD Converter Control Register 1
ADCCR1 7 6 5 4 3 2 1 0
(000EH) ADRS AMD AINDS SAIN (Initial value: 0001 0000)
0: -
ADRS AD conversion start
1: AD conversion start
00: AD operation disable

01: Software start mode
AMD AD operating mode
10: Reserved
11: Repeat mode
0: Analog input enable

AINDS Analog input control
1: Analog input disable
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3 R/W
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
SAIN Analog input channel select
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
Note 1: Select analog input channel during AD converter stops (ADCDR2<ADBF> = "0").
Note 2: When the analog input channel is all use disabling, the ADCCR1<AINDS> should be set to "1".
Note 3: During conversion, Do not perform port output instruction to maintain a precision for all of the pins because analog input
port use as general input port. And for port near to analog input, Do not input intense signaling of change.
Note 4: The ADCCR1<ADRS> is automatically cleared to "0" after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register1 (ADCCR1) is all initialized and no data can
be written in this register. Therfore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1 or
NORMAL2 mode.
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TMP86CM29LUG
AD Converter Control Register 2
ADCCR2 7 6 5 4 3 2 1 0
(000FH) IREFON "1" ACK "0" (Initial value: **0* 000*)
DA converter (Ladder resistor) connection 0: Connected only during AD conversion

IREFON
control 1: Always connected
000: Reserved
001: Reserved
010: 78/fc R/W
AD conversion time select
011: 156/fc
ACK (Refer to the following table about the con-
100: 312/fc
version time)
101: 624/fc
110: 1248/fc
111: Reserved
Note 1: Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1".
Note 2: When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data.
Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register2 (ADCCR2) is all initialized and no data can
be written in this register. Therfore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1 or
NORMAL2 mode.
Table 13-1 ACK setting and Conversion time
Condition Conversion
16 MHz 8 MHz 4 MHz 2 MHz 10 MHz 5 MHz 2.5 MHz
ACK time
000 Reserved
001 Reserved
010 78/fc - - - 39.0 µs - - 31.2 µs
011 156/fc - - 39.0 µs 78.0 µs - 31.2 µs 62.4 µs
100 312/fc - 39.0 µs 78.0 µs 156.0 µs 31.2 µs 62.4 µs 124.8 µs
101 624/fc 39.0 µs 78.0 µs 156.0 µs - 62.4 µs 124.8 µs -
110 1248/fc 78.0 µs 156.0 µs - - 124.8 µs - -
111 Reserved
Note 1: Setting for "−" in the above table are inhibited. fc: High Frequency oscillation clock [Hz]
Note 2: Set conversion time setting should be kept more than the following time by Analog reference voltage (VAREF) .
- VAREF = 2.7 to 3.6 V 31.2 µs and more
- VAREF = 1.8 to 3.6 V 124.8 µs and more
AD Converted value Register 1
ADCDR1 7 6 5 4 3 2 1 0
(0020H) AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 (Initial value: 0000 0000)
AD Converted value Register 2
ADCDR2 7 6 5 4 3 2 1 0
(0021H) AD01 AD00 EOCF ADBF (Initial value: 0000 ****)
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TMP86CM29LUG
0: Before or during conversion

EOCF AD conversion end flag
1: Conversion completed Read
0: During stop of AD conversion only
ADBF AD conversion BUSY flag
1: During AD conversion
Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to
ADCDR2 more first than ADCDR1.
Note 2: The ADCDR2<ADBF> is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is
cleared upon entering STOP mode or SLOW mode .
Note 3: If a read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable.
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TMP86CM29LUG
13.3 Function
13.3.1 Software Start Mode

After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver-
sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished inter-
rupt (INTADC) is generated.
ADRS is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS> newly again
(Restart) during AD conversion. Before setting ADRS newly again, check ADCDR2<EOCF> to see that the
conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling rou-
tine).
AD conversion start AD conversion start

ADCCR1<ADRS>
ADCDR2<ADBF>
ADCDR1 status Indeterminate 1st conversion result 2nd conversion result
EOCF cleared by reading

ADCDR2<EOCF> conversion result
INTADC interrupt request
ADCDR1
Conversion result Conversion result
read read
ADCDR2
Conversion result Conversion result
read read
Figure 13-2 Software Start Mode
13.3.2 Repeat Mode

AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is performed repeatedly.
In this mode, AD conversion is started by setting ADCCR1<ADRS> to “1” after setting ADCCR1<AMD> to
“11” (Repeat mode).
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished inter-
rupt (INTADC) is generated.
In repeat mode, each time one AD conversion is completed, the next AD conversion is started. To stop AD
conversion, set ADCCR1<AMD> to “00” (Disable mode) by writing 0s. The AD convert operation is stopped
immediately. The converted value at this time is not stored in the AD converted value register.
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13.3 Function
TMP86CM29LUG
ADCCR1<AMD> “11” “00”
AD conversion start
ADCCR1<ADRS>
AD convert operation suspended.

1st conversion
Conversion operation result 2nd conversion result 3rd conversion result Conversion result is not stored.
ADCDR1,ADCDR2 Indeterminate 1st conversion result 2nd conversion result 3rd conversion result
ADCDR2<EOCF>
EOCF cleared by reading

INTADC interrupt request conversion result
ADCDR1
Conversion Conversion Conversion
ADCDR2 result read result read result read
Conversion Conversion Conversion

result read result read result read
Figure 13-3 Repeat Mode
13.3.3 Register Setting

1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
• Specify AMD for the AD converter control operation mode (software or repeat mode).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the con-
version time, refer to Figure 13-1 and AD converter control register 2.
• Choose IREFON for DA converter control.
3. After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”. If software start mode has been selected, AD conversion starts immediately.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD con-
verted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted
value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is gener-
ated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
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TMP86CM29LUG
Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD con-
version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store
the upper 8 bits in address 0009FH in RAM. The operation mode is software start mode.
;Set port register approrriately before setting AD
: (port setting) :
converter registers.
: : (Refer to section I/O port in details)
LD (ADCCR1) , 00100011B ; Select AIN3
;Select conversion time(312/fc) and operation

LD (ADCCR2) , 11011000B
mode
SET (ADCCR1) . 7 ; ADRS = 1(AD conversion start)
SLOOP : TEST (ADCDR2) . 5 ; EOCF= 1 ?
JRS T, SLOOP
LD A , (ADCDR2) ; Read result data
LD (9EH) , A
LD A , (ADCDR1) ; Read result data
LD (9FH), A
13.4 STOP/SLOW Modes during AD Conversion

When standby mode (STOP or SLOW mode) is entered forcibly during AD conversion, the AD convert operation
is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value). Also, the
conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read
the conversion results before entering standby mode (STOP or SLOW mode).) When restored from standby mode
(STOP or SLOW mode), AD conversion is not automatically restarted, so it is necessary to restart AD conversion.
Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing
into the analog reference voltage.
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13.5 Analog Input Voltage and AD Conversion Result
TMP86CM29LUG
13.5 Analog Input Voltage and AD Conversion Result

The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 13-4.
3FFH
3FEH
3FDH
AD
conversion
result
03H
02H
01H
VAREF VSS
0 1 2 3 1021 1022 1023 1024 1024

Analog input voltage
Figure 13-4 Analog Input Voltage and AD Conversion Result (Typ.)
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TMP86CM29LUG
13.6 Precautions about AD Converter
13.6.1 Analog input pin voltage range

Make sure the analog input pins (AIN0 to AIN7) are used at voltages within VAREF to VSS. If any voltage
outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain.
The other analog input pins also are affected by that.
13.6.2 Analog input shared pins

The analog input pins (AIN0 to AIN7) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
13.6.3 Noise Countermeasure

The internal equivalent circuit of the analog input pins is shown in Figure 13-5. The higher the output
impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the out-
put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac-
itor external to the chip.
Internal resistance Analog comparator

AINi 5 kΩ (typ)
Permissible signal Internal capacitance

C = 22 pF (typ.)
source impedance
5 kΩ (max)
DA converter
Note) i = 7 to 0
Figure 13-5 Analog Input Equivalent Circuit and Example of Input Pin Processing
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13.6 Precautions about AD Converter
TMP86CM29LUG
Page 152
TMP86CM29LUG
In the TMP86CM29LUG, the STOP mode is released by not only P20(INT5/STOP) pin but also four (STOP2 to
STOP5) pins.
When the STOP mode is released by STOP2 to STOP5 pins, the STOP pin needs to be used.
In details, refer to the following section " 14.2 Control ".
14.1 Configuration
INT5
STOP
STOP mode
release signal
(1: Release) STOP2
STOP3
STOP4
STOP5
STOP5
STOP4
STOP3
STOP2
STOPCR
(0F9AH)
Figure 14-1 Key-on Wakeup Circuit
14.2 Control
STOP2 to STOP5 pins can controlled by Key-on Wakeup Control Register (STOPCR). It can be configured as
enable/disable in 1-bit unit. When those pins are used for STOP mode release, configure corresponding I/O pins to
input mode by I/O port register beforehand.
Key-on Wakeup Control Register

STOPCR 7 6 5 4 3 2 1 0
(0F9AH) STOP5 STOP4 STOP3 STOP2 (Initial value: 0000 ****)
0:Disable Write
STOP5 STOP mode released by STOP5
1:Enable only
0:Disable Write
1:Enable only
0:Disable Write
1:Enable only
0:Disable Write
1:Enable only
14.3 Function
Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the
"L" level on STOP2 to STOP5 pins, which are enabled by STOPCR, for releasing STOP mode (Note1).
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14.3 Function
TMP86CM29LUG
Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register,
check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is startd (Note2).
Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2 to
STOP5 pins by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 to STOP5 pins
that are available input during STOP mode.
Note 2: When the STOP pin input is high or STOP2 to STOP5 pins inputwhich is enabled by STOPCR is low, executing an
instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release
sequence (Warm up).
Note 3: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 to
STOP5 pins, STOP pin also should be used as STOP mode release function.
Note 4: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on
Wakeup Control Register (STOPCR) may genarate the penetration current, so the said pin must be disabled AD
conversion input (analog voltage input).
Note 5: When the STOP mode is released by STOP2 to STOP5 pins, the level of STOP pin should hold "L" level (Figure
14-2).
a) STOP b) In case of STOP2 to STOP5
STOP pin STOP pin "L"

Release
STOP mode STOP mode
STOP2 pin
Release
STOP mode STOP mode
Figure 14-2 Priority of STOP pin and STOP2 to STOP5 pins
Table 14-1 Release level (edge) of STOP mode
Release level (edge)

Pin name SYSCR1<RELM>="1"
SYSCR1<RELM>="0"
(Note2)
STOP "H" level Rising edge
STOP2 "L" level Don’t use (Note1)
Page 154
TMP86CM29LUG
15. LCD Driver
The TMP86CM29LUG has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins
to be connected to LCD are as follows:
1. Segment output port 32 pins (SEG31 to SEG0)

2. Common output port4 pins (COM3 to COM0)
In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver’s booster circuit.
The devices that can be directly driven is selectable from LCD of the following drive methods:
1. 1/4 Duty (1/3 Bias) LCD Max 128 Segments(8 segments × 16 digits)
4. Static LCD Max 32 Segments(8 segments × 4 digits)
15.1 Configuration
LCDCR
7 6 5 4 3 2 1 0
EDSP BRES VFSEL DUTY SLF
DBR
fc/217, fs/29 display data area
fc/216, fs/28
fc/215
fc/213
Duty Timing
control control Display data select control
fc/213, fs/25
fc/211, fs/23
fc/210, fs/22 Blanking Display data buffer register
control
fc/29
Constant voltage Common driver Segment driver

booster circuit
COM0 to COM3 SEG0 SEG31

C0 C1 V1 V2 V3
Figure 15-1 LCD Driver
Note: The LCD driver incorporates a dedicated divider circuit. Therefore, the break function of a debugger (development
tool) will not stop LCD driver output.
Page 155
15. LCD Driver
15.2 Control
TMP86CM29LUG
15.2 Control
The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver’s display is enabled using
the EDSP.
LCD Driver Control Register
LCDCR 7 6 5 4 3 2 1 0
(0028H) EDSP BRES VFSEL DUTY SLF (Initial value: 0000 0000)
0: Blanking
EDSP LCD Display Control
1: Enables LCD display (Blanking is released)
0: Disable (use divider resistance)

BRES Booster circuit control
1: Enable
NORMAL1/2, IDLE/1/2 mode SLOW1/2,

DV7CK = 0 DV7CK = 1 SLEEP0/1/2 mode
00 fc/213 fs/25 fs/25

VFSEL Selection of boost frequency
01 fc/211 fs/23 fs/23
10 fc/210 fs/22 fs/22
11 fc/29 fc/29 –
R/W
00: 1/4 Duty (1/3 Bias)
01: 1/3 Duty (1/3 Bias)
DUTY Selection of driving methods
10: 1/2 Duty (1/2 Bias)
11: Static
NORMAL1/2, IDLE/1/2 mode SLOW1/2,

DV7CK = 0 DV7CK = 1 SLEEP0/1/2 mode
00 fc/217 fs/29 fs/29

Selection of LCD frame fre-
SLF
quency 01 fc/216 fs/28 fs/28
10 fc/215 fc/215 –
11 fc/213 fc/213 –
Note 1: When <BRES>(Booster circuit control) is set to “0”, VDD ≥ V3 ≥ V2 ≥ V1 ≥ VSS should be satisfied.
When <BRES> is set to “1”, 3.6 [V] ≥ V3 ≥ VDD should be satisfied.
If these conditions are not satisfied, it not only affects the quality of LCD display but also may damage the device due to
over voltage of the port.
Note 2: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set LCDCR<DUTY> to "10" or "11"
when the booster circuit is enable.
Note 3: Do not set SLF to “10” or “11” in SLOW1/2 modes.
Note 4: Do not set VFSEL to “11” SLOW1/2 modes.
Page 156
TMP86CM29LUG
15.2.1 LCD driving methods

As for LCD driving method, 4 types can be selected by LCDCR<DUTY>. The driving method is initialized
in the initial program according to the LCD used.
VLCD3 1/fF VLCD3 1/fF
0 0
−VLCD3 −VLCD3
Data "1" Data "0" Data "1" Data "0"
(a) 1/4 Duty (1/3 Bias) (b) 1/3 Duty (1/3 Bias)
1/fF
VLCD3 1/fF VLCD3
0 0
−VLCD3 −VLCD3
Data "1" Data "0"
Data "1" Data "0"
(c) 1/2 Duty (1/2 Bias) (d) Static
Note 1: fF: Frame frequency

Note 2: VLCD3: LCD drive voltage
Figure 15-2 LCD Drive Waveform (COM-SEG pins)
Page 157
15. LCD Driver
15.2 Control
TMP86CM29LUG
15.2.2 Frame frequency

Frame frequency (fF) is set according to driving method and base frequency as shown in the following Table
15-1. The base frequency is selected by LCDCR<SLF> according to the frequency fc and fs of the basic clock
to be used.
Table 15-1 Setting of LCD Frame Frequency
(a) At the single clock mode. At the dual clock mode (DV7CK = 0).
Frame frequency [Hz]

SLF Base frequency [Hz]
1/4 Duty 1/3 Duty 1/2 Duty Static
fc fc 4 fc 4 fc fc
-------- -------- --- • -------- --- • -------- --------
2
17
2
17 3 2 17 2 2 17 2
17
00
(fc = 16 MHz) 122 163 244 122
(fc = 8 MHz) 61 81 122 61
fc fc 4 fc 4 fc fc
-------- -------- --- • -------- --- • -------- --------
2
16
2
16 3 2 16 2 2 16 2
16
01
(fc = 8 MHz) 122 163 244 122
(fc = 4 MHz) 61 81 122 61
fc fc 4 fc 4 fc fc
-------- -------- --- • -------- --- • -------- --------
2
15
2
15 3 2 15 2 2 15 2
15
10
(fc = 4 MHz) 122 163 244 122
(fc = 2 MHz) 61 81 122 61
fc fc 4 fc 4 fc fc
-------- -------- --- • -------- --- • -------- --------
2
13
2
13 3 2 13 2 2 13 2
13
11
(fc = 1 MHz) 122 163 244 122
Note: fc: High-frequency clock [Hz]
Table 15-2
(b) At the dual clock mode (DV7CK = 1 or SYSCK = 1)
Frame frequency [Hz]

SLF Base frequency [Hz]
1/4 Duty 1/3 Duty 1/2 Duty Static
fs fs 4 fs 4 fs fs
------ ------ --- • ------ --- • ------ ------
2
9
2
9 3 29 2 29 2
9
00
(fs = 32.768 kHz) 64 85 128 64
fs fs 4 fs 4 fs fs
------ ------ --- • ------ --- • ------ ------
2
8
2
8 3 28 2 28 2
8
01
(fs = 32.768 kHz) 128 171 256 128
Note: fs: Low-frequency clock [Hz]
Page 158
TMP86CM29LUG
15.2.3 Driving method for LCD driver

In the TMP86CM29LUG, LCD driving voltages can be generated using either an internal booster circuit or
an external resistor divider. This selection is made in LCDCR<BRES>.
15.2.3.1 When using the booster circuit (LCDCR<BRES>="1")
When the reference voltage is connected to the V1 pin, the booster circuit boosts the reference voltage
twofold (V2) or threefold (V3) to generate the output voltages for segment/common signals. When the
reference voltage is connected to the V2 pin, it is reduced to 1/2 (V1) or boosted to 3/2 (V3). When the
reference voltage is connected to the V3 pin, it is reduced to 1/3 (V1) or 2/3 (V2).
LCDCR<VFSEL> is used to select the reference frequency in the booster circuit. The faster the boost-
ing frequency, the higher the segment/common drive capability, but power consumption is increased.
Conversely, the slower the boosting frequency, the lower the segment/common drive capability, but power
consumption is reduced. If the drive capability is insufficient, the LCD may not be displayed clearly.
Therefore, select an optimum boosting frequency for the LCD panel to be used.
Table 15-3 shows the V3 pin current capacity and boosting frequency.
Note: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set
LCDCR<DUTY> to "10" or "11" when the booster circuit is enable (LCDCR<BRES>="1").
Keep the following VDD

condition.
V3
C
V2
V3 C
V1
V1 = 1/3 x V3
C = 0.1 to 0.47 µF
Reference voltage
C1
C
C0
VSS
a) Reference pin = V1

condition.
V3
C
V2
V3 C
V1
V2 = 2/3 x V3 C
C = 0.1 to 0.47 µF
Reference voltage
C1
C
C0
VSS
b) Reference pin = V2
Page 159
15. LCD Driver
15.2 Control
TMP86CM29LUG

condition.
V3
C
V2
V3 C Reference voltage
V1
C
C = 0.1 to 0.47 µF
C1
C
C0
VSS
c) Reference pin = V3

condition.
V3
C
V2
V3 = C
V1
C
C = 0.1 to 0.47 µF
C1
C
C0
VSS
d) Reference pin = V3
Note 1: When the TMP86CM29LUG uses the booster circuit to drive the LCD, the power supply and capacitor for the booster cir-
cuit should be connected as shown above.
Note 2: When the reference voltage is connected to a pin other than V1, add a capacitor between V1 and GND.
Note 3: The connection examples shown above are different from those shown in the datasheets of the existing mask or OTP
products. Since the above connection method enhances the boosting characteristics, it is recommended that new boards
be designed using the above connection method. (Using the existing connection method does not affect LCD display.)
Especially for the TMP86CM29LUG, be sure to design the board using the above b) c) d) connection method. In the con-
nection a), it guarantee -10 to 85 °C as operating temperature range.
Figure 15-3 Connection Examples When Using the Booster Circuit (LCDCR<BRES> = “1”)
Table 15-3 V3 Pin Current Capacity and Boosting Frequency (typ.)
VFSEL Boosting frequency fc = 16 MHz fc = 8 MHz fc = 4 MHz fc = 32.768 MHz
00 fc/2 13
or fs/2 5 −37 mV/ µA −80 mV/ µA −138 mV/ µA −76 mV/ µA
01 fc/211 or fs/23 −19 mV/ µA −24 mV/ µA −37 mV/ µA −23 mV/ µA
10 fc/210 or fs/22 −17 mV/ µA −19 mV/ µA −24 mV/ µA −18 mV/ µA
11 fc/29 −16 mV/ µA −17 mV/ µA −19 mV/ µA –
Note 1: The current capacity is the amount of voltage that falls per 1µA.
Note 2: The boosting frequency should be selected depending on your LCD panel.
Note 3: For the reference pin V1 or V2, a current capacity ten times larger than the above is recommended to ensure stable oper-
ation.
For example, when the boosting frequency is fc/29 (at fc = 8 MHz), −1.7 mV/ µA or more is recommended for the current
capacity of the reference pin V1.
Page 160
TMP86CM29LUG
15.2.3.2 When using an external resistor divider (LCDCR<BRES>="0")
When an external resistor divider is used, the voltage of an external power supply is divided and input
on V1, V2, and V3 to generate the output voltages for segment/common signals.
The smaller the external resistor value, the higher the segment/common drive capability, but power con-
sumption is increased. Conversely, the larger the external resistor value, the lower the segment/common
drive capability, but power consumption is reduced. If the drive capability is insufficient, the LCD may
not be displayed clearly. Therefore, select an optimum resistor value for the LCD panel to be used.
Adjustment of Adjustment of Adjustment of

contrast contrast contrast
VDD VDD VDD

V3 V3 V3
R1 R1
V2 V2 V2
C0 Open C0 Open C0 Open
C1 Open R2 C1 Open C1 Open
V1 V1 V1
R3 R2 R1
VSS VSS VSS
1/3 Bias (R1 = R2 = R3) 1/2 Bias (R1 = R2) Static
Keep the following conditon.

VDD V3 V2 V1 VSS
Figure 15-4 Connection Examples When Using an External Resistor Divider

(LCDCR<BRES> = “0”)
15.3 LCD Display Operation
15.3.1 Display data setting

Display data is stored to the display data area (assigned to address 0F80H to 0F8FH, 16bytes) in the DBR.
The display data which are stored in the display data area is automatically read out and sent to the LCD driver
by the hardware. The LCD driver generates the segment signal and common signal according to the display
data and driving method. Therefore, display patterns can be changed by only over writing the contents of dis-
play data area by the program. Table 15-5 shows the correspondence between the display data area and SEG/
COM pins.
LCD light when display data is “1” and turn off when “0”. According to the driving method of LCD, the
number of pixels which can be driven becomes different, and the number of bits in the display data area which
is used to store display data also becomes different.
Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the
addresses not connected to LCD can be used to store general user process data (see Table 15-4).
Note:The display data memory contents become unstable when the power supply is turned on; therefore, the dis-
play data memory should be initialized by an initiation routine.
Page 161
15. LCD Driver
15.3 LCD Display Operation
TMP86CM29LUG
Table 15-4 Driving Method and Bit for Display Data
Driving methods Bit 7/3 Bit 6/2 Bit 5/1 Bit 4/0
1/4 Duty COM3 COM2 COM1 COM0
1/3 Duty – COM2 COM1 COM0
1/2 Duty – – COM1 COM0
Static – – – COM0
Note: –: This bit is not used for display data
Table 15-5 LCD Display Data Area (DBR)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0F80H SEG1 SEG0
0F81H SEG3 SEG2
0F82H SEG5 SEG4
0F83H SEG7 SEG6
0F84H SEG9 SEG8
0F85H SEG11 SEG10
0F86H SEG13 SEG12
0F87H SEG15 SEG14
0F88H SEG17 SEG16
0F89H SEG19 SEG18
0F8AH SEG21 SEG20
0F8BH SEG23 SEG22
0F8CH SEG25 SEG24
0F8DH SEG27 SEG26
0F8EH SEG29 SEG28
0F8FH SEG31 SEG30
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
15.3.2 Blanking
Blanking is enabled when EDSP is cleared to “0”.
Blanking turns off LCD through outputting a GND level to SEG/COM pin.
When in STOP mode, EDSP is cleared to “0” and automatically blanked. To redisplay ICD after exiting
STOP mode, it is necessary to set EDSP back to “1”.
Note:During reset, the LCD segment outputs and LCD common outputs are fixed “0” level. But the multiplex termi-
nal of input/output port and LCD segment output becomes high impedance. Therefore, when the reset input is
long remarkably, ghost problem may appear in LCD display.
Page 162
TMP86CM29LUG
15.4 Control Method of LCD Driver
15.4.1 Initial setting

Figure 15-5 shows the flowchart of initialization.
Example : To operate a 1/4 duty LCD of 32 segments × 4 com-mons at frame frequency fc/216 [Hz], and booster fre-
quency fc/213 [Hz]
LD (LCDCR), 01000001B ; Sets LCD driving method and frame frequency. Boost frequency
LD (P*LCR), 0FFH ; Sets segment output control register. (*; Port No.)
: :
: : ; Sets the initial value of display data.
LD (LCDCR), 11000001B ; Display enable
Sets LCD driving method (DUTY).

Sets boost frequency (VFSEL).
Sets frame frequency (SLF).
Enables booster circuit (BRES)
Sets segment output control registers

(P*LCR (*; Port No.))
Initialization of display data area.
Display enable (EDSP)

(Releases from blanking.)
Figure 15-5 Initial Setting of LCD Driver
15.4.2 Store of display data

Generally, display data are prepared as fixed data in program memory (ROM) and stored in display data area
by load command.
Page 163
15. LCD Driver
TMP86CM29LUG
Example :To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data mem-
ory at address 80H (when pins COM and SEG are connected to LCD as in Figure 15-6), display data
become as shown in Table 15-6.
LD A, (80H)
ADD A, TABLE-$-7
LD HL, 0F80H
LD W, (PC + A)
LD (HL), W
RET
TABLE: DB 11011111B, 00000110B,

11100011B, 10100111B,
00110110B, 10110101B,
11110101B, 00010111B,
11110111B, 10110111B
Note:DB is a byte data difinition instruction.
COM0
COM1
COM2
SEG0 COM3
SEG1
Figure 15-6 Example of COM, SEG Pin Connection (1/4 Duty)
Table 15-6 Example of Display Data (1/4 Duty)
No. display Display data No. display Display data
0 11011111 5 10110101
1 00000110 6 11110101
2 11100011 7 00000111
3 10100111 8 11110111
4 00110110 9 10110111
Page 164
TMP86CM29LUG
Example 2: Table 15-6 shows an example of display data which are displayed using 1/2 duty LCD in the
same way as Table 15-7. The connection between pins COM and SEG are the same as shown in Figure 15-7.
COM0
SEG3 SEG0
SEG2 COM1
SEG1
Figure 15-7 Example of COM, SEG Pin Connection
Table 15-7 Example of Display Data (1/2 Duty)
Display data Display data

Number Number
High order address Low order address High order address Low order address
0 **01**11 **01**11 5 **11**10 **01**01
1 **00**10 **00**10 6 **11**11 **01**01
2 **10**01 **01**11 7 **01**10 **00**11
3 **10**10 **01**11 8 **11**11 **01**11
4 **11**10 **00**10 9 **11**10 **01**11
Note: *: Don’t care
Page 165
15. LCD Driver
TMP86CM29LUG
15.4.3 Example of LCD drive output
COM0
COM1
COM2
SEG0 COM3
SEG1
EDSP
VLCD3
SEG0
0
VLCD3
SEG1
0
VLCD3
Display data area COM0
0
Address
VLCD3
0F80H 1011 0101 COM1
0
VLCD3
COM2
0
VLCD3
COM3
0
VLCD3
COM0-SEG0 0
(Selected)
−VLCD3
VLCD3
COM2-SEG1 0
(Non selected)
−VLCD3
Figure 15-8 1/4 Duty (1/3 bias) Drive
Page 166
TMP86CM29LUG
SEG1
SEG2 SEG0 COM0
COM1
COM2
EDSP
VLCD3
SEG0
0
VLCD3
SEG1
Display data area
0
VLCD3
Address SEG2
0F80H *111 *010 0
0F81H **** *001 VLCD3
COM0
0
*: Don’t care VLCD3
COM1
0
VLCD3
COM2
0
VLCD3
COM0-SEG1 0
(Selected)
−VLCD3
VLCD3
COM1-SEG2 0
(Non selected)
−VLCD3
Page 167
15. LCD Driver
TMP86CM29LUG
COM0
SEG3 COM0
COM2 COM1
COM1
EDSP
VLCD3
SEG0
0
VLCD3
SEG1
Display data area
0
Address VLCD3
SEG2
0F80H **01 **01 0
VLCD3
0F81H **11 **10 SEG3
0
VLCD3
*: Don’t care
COM0
0
VLCD3
COM1
0
VLCD3
COM0-SEG1 0
(Selected) VLCD3
−VLCD3
COM1-SEG2 0
(Non selected) −VLCD3
Page 168
TMP86CM29LUG
SEG0
SEG1
SEG5
SEG6
SEG4 SEG2 COM0
SEG3 SEG7
Display data area

EDSP
Address
VLCD3
0F80H ***0 ***1 SEG0
0F81H ***1 ***1 0
VLCD3
0F82H ***1 ***0 SEG4
0F83H 0
***0 ***1
VLCD3
*: Don’t care SEG7
0
VLCD3
COM0
0
VLCD3
COM0-SEG0 0
(Selected)
−VLCD3
VLCD3
COM0-SEG4 0
(Non selected) −VLCD3
Figure 15-11 Static Drive
Page 169
15. LCD Driver
TMP86CM29LUG
Page 170
TMP86CM29LUG
16.1 Control Pins

The input/output circuitries of the TMP86CM29LUG control pins are shown below.
Control Pin I/O Input/Output Circuitry Remarks
Osc. enable fc
VDD VDD Resonator connecting pins

XIN Input
Rf (High-frequency)
RO
XOUT Output Rf = 3 MΩ (typ.)
RO = 1 kΩ (typ.)
XIN XOUT
XTEN
Osc. enable fs
Resonator connecting pins

VDD VDD
XTIN Input Rf (Low-frequency)
R RO
XTOUT Output Rf = 20 MΩ (typ.)
RO = 220 kΩ (typ.)
XTIN XTOUT
VDD
RIN Sink open drain output
Hysteresis input
RESET I/O
Address-trap-reset Pull-up resistor
RIN = 220 kΩ (typ.)
Watchdog-timer
System-clock-reset
VDD
R D1 Pull-down resistor
TEST Input RIN = 70 kΩ (typ.)
RIN R = 1K Ω (typ.)
Note: The TEST pin of the TMP86PM29 does not have a pull-down resistor and protect diode(D1). Fix the TEST pin at low-level
in MCU mode.
Page 171
16.2 Input/Output Ports
TMP86CM29LUG
16.2 Input/Output Ports
Port I/O Input/Output Circuitry Remarks
Initial "High-Z"
P1LCR
SEG output Sink open drain output
P1 I/O Hysteresis input
Data output R = 100 Ω (typ.)
Input from output R
latch
Pin input
Initial "High-Z"
P5LCR/P7LCR
SEG output
P5 Sink open drain output
I/O
P7 R = 100 Ω (typ.)
Data output
Input from output R
latch
Pin input
Initial "High-Z" VDD
Sink open drain output

Data output
R R = 100 Ω (typ.)
Input from output latch
Pin input
Initial "High-Z"
VDD Sink oopen drain
Pch control or
Data output C-MOS output
Input from output latch High current output (Nch)
R (Programable port option)
Pin input R = 100 Ω (typ.)
Initial "High-Z"
VDD
Data output
Tri-state I/O
Disable R = 100 Ω (typ.)
R
Pin input
Note: Port P1, P5 and P7 are sink open drain outut. But they are also used as a segment output of LCD. Therefore, absolute max-
imum ratings of port input voltage should be used in −0.3 to VDD + 0.3 volts.
Page 172
TMP86CM29LUG
17.1 Absolute Maximum Ratings

The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down
or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(VSS = 0 V)
Parameter Symbol Pins Ratings Unit
VDD −0.3 to 4.0

Supply voltage V
VLCD V3 pin −0.3 to 4.0
Input voltage VIN −0.3 to VDD + 0.3 V
Output voltage VOUT1 −0.3 to VDD + 0.3 V
IOUT1 P3, P6 port −1.8
Output current (Per 1 pin) IOUT2 P1, P2, P5, P6, P7 port 3.2
IOUT3 P3 port 30 mA
Σ IOUT2 P1, P2, P5, P6, P7 port 60

Output current (Total)
Σ IOUT3 P3 port 80
Power dissipation [Topr = 85°C] PD 350 mW
Soldering temperature (Time) Tsld 260 (10 s)
Storage temperature Tstg −55 to 125 °C
Operating temperature Topr −40 to 85
Page 173
17.2 Recommended Operating Condition
TMP86CM29LUG
17.2 Recommended Operating Condition

The recommended operating conditions for a device are operating conditions under which it can be guaranteed that
the device will operate as specified. If the device is used under operating conditions other than the recommended
operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may
occur. Thus, when designing products which include this device, ensure that the recommended operating conditions
for the device are always adhered to.
(VSS = 0 V, Topr = −40 to 85°C)
Parameter Symbol Pins Condition Min Max Unit
NORMAL1, 2 mode
fc = 16 MHz 2.7
IDLE0, 1, 2 mode
fc = 8 MHz NORMAL1, 2 mode

(In case of connecting
a resonator) IDLE0, 1, 2 mode
Supply voltage VDD fc = 4.2 MHz NORMAL1, 2 mode 3.6

(In case of external
IDLE0, 1, 2 mode 1.8
clock input)
SLOW1, 2 mode
fs = 32.768 kHz
SLEEP0, 1, 2 mode
V
STOP mode
Except hysteresis
VIH1 VDD × 0.70
input VDD ≥ 2.7 V
Input high level VDD
VIH2 Hysteresis input VDD × 0.75
VIH3 VDD < 2.7 V VDD × 0.90
Except hysteresis
VIL1 VDD × 0.30
input VDD ≥ 2.7 V
Input low level 0
VIL2 Hysteresis input VDD × 0.25
VIL3 VDD < 2.7 V VDD × 0.10
VDD = 1.8 V to 3.6 V 8.0

Clock frequency fc XIN, XOUT 1.0 MHz
(In case of connecting VDD = 2.7 V to 3.6 V 16.0
a resonator)
fs XTIN, XTOUT VDD = 1.8 V to 3.6 V 30.0 34.0 kHz
VDD = 1.8 V to 3.6 V 4.2

Clock frequency fc XIN, XOUT 1.0 MHz
(In case of external VDD = 2.7 V to 3.6 V 16.0
clock input)
fs XTIN, XTOUT VDD = 1.8 V to 3.6 V 30.0 34.0 kHz
V1 V1 pin (Note1) 0.8 1.2
LCD reference voltage V2 V2 pin LCD booster circuit enable (V3 ≥ VDD) 1.6 2.4 V
V3 V3 pin 2.4 3.6
Capacity for LCD

CLCD LCD booster circuit enable (V3 ≥ VDD) 0.1 0.47 µF
booster circuit
Note 1: When V1 pin is used for LCD reference voltage input, the operating temperature (Topr) should be kept within −10 to 85 °C.
Page 174
TMP86CM29LUG
17.3 DC Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter Symbol Pins Condition Min Typ. Max Unit
Hysteresis voltage VHS Hysteresis input VDD = 3.3 V – 0.4 – V
IIN1 TEST VDD = 3.6 V, VIN = 0 V – – −5
Sink open drain, Tri-state

Input current IIN2 VDD = 3.6 V, VIN = 3.6 V/0 V – – ±5 µA
port
IIN3 RESET VDD = 3.6 V, VIN = 3.6 V – – 5
RIN1 TEST Pull-Down VDD = 3.6 V, VIN = 3.6 V – 70 –

Input Resistance kΩ
RIN2 RESET Pull-Up VDD = 3.6 V, VIN = 0 V 100 220 450
High frequency
RFB XOUT VDD = 3.6 V – 3 –
feedback resistor
MΩ
Low frequency
RFBT XTOUT VDD = 3.6 V – 20 –
feedback resistor
Sink open drain, Tri-state

Output leakage current ILO VDD = 3.6 V, VOUT = 3.4 V/0.2 V – – ± 10 µA
port
Output high voltage VOH2 C-MOS, Tri-state port VDD = 3.6 V, IOH = −0.6 mA 3.2 – –
V
Output low voltage VOL Except XOUT and P3 port VDD = 3.6 V, IOL = 0.9 mA – – 0.4
Output low current IOL High current port (P3 port) VDD = 3.6 V, VOL = 1.0 V – 6 – mA
V2 pin V3 ≥ VDD – V1 x 2 –
V2-3OUT Reference supply pin : V1 (Note5)
V3 pin – V1 x 3 –
SEG/COM pin : No load
LCD output voltage V1 pin V3 ≥ VDD – V2 x 1/2 –

(LCD booster is V1-3OUT Reference supply pin : V2 V
enable) V3 pin – V2 x 3/2 –
V1 pin V3 ≥ VDD – V3 x 1/3 –

V1-2OUT Reference supply pin : V3
V2 pin – V3 x 2/3 –
Supply current in VDD = 3.6 V

– 3.4 5.2
NORMAL 1, 2 modes VIN = 3.4/0.2 V
mA
Supply current in fc = 16 MHz
– 2.2 4.2
IDLE 0, 1, 2 modes fs = 32.768 kHz
Supply current in
– 7 19
SLOW 1 mode
IDD VDD = 3.0 V
Supply current in
VIN = 2.8 V/0.2 V – 5.5 17
SLEEP 1 mode
fs = 32.768 kHz µA
Supply current in
– 4.5 17
SLEEP 0 mode
Supply current in VDD = 3.6 V

– 0.5 10
STOP mode VIN = 3.4 V/0.2 V
Note 1: Typical values show those at Topr = 25°C, VDD = 3.3 V.

Note 2: Input current (IIN1, IIN3): The current through pull-up or pull-down resistor is not included.
Note 3: IDD does not include IREF current.
Note 4: The supply currents of SLOW 2 and SLEEP 2 modes are equivalent to IDLE 0, 1, 2.
Note 5: When V1 pin is used for LCD reference voltage input, the operating temperature (Topr) should be kept within −10 to 85 °C.
Page 175
17.4 AD Conversion Characteristics
TMP86CM29LUG
17.4 AD Conversion Characteristics
(VSS = 0.0 V, 2.7 V ≤ VDD ≤ 3.6 V, Topr = −40 to 85°C)
Parameter Symbol Condition Min Typ. Max Unit

Analog reference voltage VAREF AVDD − 1.0 – AVDD
Power supply voltage of analog control

AVDD VDD
circuit V
Analog reference voltage range (Note4) ∆VAREF 2.5 – –
Analog input voltage VAIN VSS – VAREF
Power supply current of analog refer- VDD = AVDD = VAREF = 3.6 V

IREF – 0.35 0.61 mA
ence voltage VSS = 0.0 V
Non linearity error – – ±2

VDD = AVDD = 2.7 V
Zero point error – – ±2
VSS = 0.0 V LSB
Full scale error – – ±2
VAREF = 2.7 V
Total error – – ±2
(VSS = 0.0 V, 2.0 V ≤ VDD < 2.7 V, Topr = −40 to 85°C)

AVDD VDD
circuit V
Power supply current of analog refer- VDD = AVDD = VAREF =2.0 V

IREF – 0.20 0.34 mA

VDD = AVDD = 2.0 V
VSS = 0.0 V LSB
VAREF = 2.0 V
(VSS = 0.0 V, 1.8 V ≤ VDD < 2.0 V, Topr = −10 to 85°C) (Note5)


AVDD VDD
circuit V
Power supply current of analog refer- VDD = AVDD = VAREF = 1.8 V

IREF – 0.18 0.31 mA

VDD = AVDD = 1.8 V
VSS = 0.0 V LSB
VAREF = 1.8 V
Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal con-
version line.
Note 2: Conversion time is different in recommended value by power supply voltage.
About conversion time, please refer to “Register Framing”.
Note 3: Please use input voltage to AIN input Pin in limit of VAREF – VSS.
Note 4: Analog Reference Voltage Range: ∆VAREF = VAREF − VSS
Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage.
Note 6: The AVDD pin should be fixed on the VDD level even though AD convertor is not used.
Page 176
TMP86CM29LUG
17.5 AC Characteristics
(VSS = 0 V, VDD = 2.7 to 3.6 V, Topr = −40 to 85°C)
NORMAL1, 2 modes
0.25 – 4
IDLE1, 2 modes
Machine cycle time tcy µs
SLOW1, 2 modes
117.6 – 133.3
SLEEP1, 2 modes
High level clock pulse width tWCH For external clock operation
(XIN input) – 31.25 – ns
Low level clock pulse width tWCL fc = 16 MHz
High level clock pulse width tWSH For external clock operation
(XTIN input) – 15.26 – µs
Low level clock pulse width tWSL fs = 32.768 kHz
(VSS = 0 V, VDD = 1.8 to 3.6 V, Topr = −40 to 85°C)
NORMAL1, 2 modes
0.5 – 4
IDLE1, 2 modes
Machine cycle time tcy µs
SLOW1, 2 modes
117.6 – 133.3
SLEEP1, 2 modes
(XIN input) – 119.05 – ns
Low level clock pulse width tWCL fc = 4.2 MHz
(XTIN input) – 15.26 – µs
Low level clock pulse width tWCL fs = 32.768 kHz
Page 177
17.6 Timer Counter 1 input (ECIN) Characteristics
TMP86CM29LUG
17.6 Timer Counter 1 input (ECIN) Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Frequency measurement mode Single edge count – –

16
VDD = 2.7 to 3.6 V Both edge count – –
TC1 input (ECIN input) tTC1 MHz
Frequency measurement mode Single edge count – –
8
VDD = 1.8 to 2.7 V Both edge count – –
Page 178
TMP86CM29LUG
17.7 Recommended Oscillating Conditions
XIN XOUT XTIN XTOUT
C1 C2 C1 C2
(1) High-frequency Oscillation (2) Low-frequency Oscillation
Note 1: A quartz resonator can be used for high-frequency oscillation only when VDD is 2.7 V or above. If VDD is below 2.7
V, use a ceramic resonator.
Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these
factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the
device will actually be mounted.
Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by
Murata Manufacturing Co., Ltd.
For details, please visit the website of Murata at the following URL:
http://www.murata.com
17.8 Handling Precaution

- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows:
Solderability rate until forming ≥ 95 %
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we
recommend electrically shielding the package in order to maintain normal operating condition.
Page 179
17.8 Handling Precaution
TMP86CM29LUG
Page 180
TMP86CM29LUG
P-LQFP64-1010-0.50D Unit: mm
Page 181
TMP86CM29LUG
Page 182
This is a technical document that describes the operating functions and electrical specifications of the 8-bit
microcontroller series TLCS-870/C (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS

production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.

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8 Bit Microcontroller

The information contained herein is subject to change without notice. 021023 _ D

© 2006 TOSHIBA CORPORATION

The Functional Differences on Products basis: TMP86CM29L, TMP86Cx29B, TMP86CH21

I/O port 39 pins

1.8V to 3.6V at 8.0MHz/

8-bit Timer counter 4ch 2ch

Time base timer 1ch

Watch dog timer 1ch

UART/SIO 1ch (Note1) N.A.

SIO N.A 1ch

Key-on wakeup 4ch

A/D converter 10-bit A/D: 8ch 8-bit A/D: 8ch

LCD driver 32SEG x 4COM

Operating Temperature -40 to 85 ℃ -40 to 85 ℃ (Note2) -40 to 85 ℃

The Functional Differences on Products basis: TMP86C829B/CH29B/CM29B/PM29A/

RAM 512 bytes 1.5K bytes

I/O port 39 pins

Large current output 4 pins (Sink-open-drain output) 4 pins (Sink-open-drain output)

Interrupt sources External: 5 Internal: 14

18bit Timer/Counter: 1ch

UART/SIO 1ch (Note1)

Key-on wakeup 4ch

AD converter 10bit x 8ch (Note3)

LCD driver 32SEG x 4COM

VDD No Protection VDD

1.8V to 5.5V at 4.2MHz/32.768kHz 1.8V to 3.6V at 8.0MHz/32.768kHz

After reset release 10 Halt Halt

Changing from STOP mode to NORMAL mode

Changing from STOP mode to SLOW mode

Changing from IDLE0/1/2 mode to NORMAL mode

Changing from SLEEP0/1/2 mode to SLOW mode

Type-1 Type-2 Type-3 Type-4 Type-5

VDD VDD VDD VDD

2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3. Interrupt Control Circuit

3.1 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4. Special Function Register (SFR)

5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6. Watchdog Timer (WDT)

6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7. Time Base Timer (TBT)

7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8. 18-Bit Timer/Counter (TC1)

9. 8-Bit TimerCounter (TC3, TC4)

10. 8-Bit TimerCounter (TC5, TC6)

10.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

11. Asynchronous Serial interface (UART )

11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12. Synchronous Serial Interface (SIO)

12.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13. 10-bit AD Converter (ADC)

13.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

14. Key-on Wakeup (KWU)

14.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

15. LCD Driver

15.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

16. Input/Ouput Circuitry

16.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171