Government of Karnataka

DEPARTMENT OF COLLEGIATE AND TECHNICAL EDUCATION

Programme Electronics and Communication Semester III
Course Code 20EC32P Type of Course Program Core
Course Name Logic Design using Verilog Contact Hours 8 hours/week
104 hours/semester
Teaching L:T:P :: 3:1:4 Credits 6
Scheme
CIE Marks 60 SEE Marks 40
1. Rationale
Digital Electronics is a field of electronics involving the study of digital signals and engineering of devices that use
or produce them. It is very important in today’s life because if digital circuits are used instead of analog circuits
the signals can be transmitted without degradation due to noise. Also in a digital system information stored is
easier than that of analog systems. The functionality of digital circuits can be changed easily with the help of
software without changing the actual circuit. Verilog, a Hardware Description Language, is used for describing
digital electronic circuits and systems. It is used for verification of digital circuits through simulation, for timing
analysis, for test analysis and for logic synthesis.

2. Course Outcomes: On successful completion of the course, the students will be able to:
CO-01 List the types of Verilog modeling and the use of each model for specific application
CO-02 Design and construct a sequential circuit for a given application and test the circuit to obtain the
desired result/output.
CO-03 Compare and contrast combinational and sequential circuits and simulate a given circuit using
Verilog descriptions to test to obtain the desired result/output
CO-04 List the various types of A to D, D to A converters along with memory and for a given application
select the appropriate converters and/or memory types to be used to obtain the given
result/output.

3. Course Content
CO PO Lecture Tutorial Practice
(Knowledge Criteria) (Activity (Performance Criteria)
Week Criteria)
3 hours/week 1 hour/week 4 hours/week (2
hours/batch twice in a week)
1 1 1,4,5, 1. VLSI - Introduction, Importance &
6,7 Need.
HDL- Introduction, Importance, 1. Familiarization of Xilinx
Need & Types. software.

2. Introduction to Verilog HDL, Refer Table 1

Types of modeling- Switch level,
Structural, Data flow and 2. Familiarization of
Behavioral. FPGA/CPLD KIT.

3. Basic Concepts- Lexical

conventions, comments, keywords,
identifiers, strings.

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2 1 1,2,4 1. Data types -Value Set, Wires, 1. Demonstrate and Practice
Nets, Registers, Vectors, Integers, simple examples using
Real, Time, Parameters, Arrays, different data types.
Strings.
2. Compute the output for
2. Operators- Arithmetic, Logical, Refer Table 1 expressions having different
Relational, Bit-wise. operators using simple
programs.
3. Reduction, Shift, Concatenation,
Replication, Conditional operators.
Operator Precedence.
3 1,3 1,2,3, 1. Program structure- Module Write the verilog code,
6 declaration, port declaration, port simulate and download to
connection. FPGA/CPLD kit for the
following
2. Gate level modeling for basic
gates. Refer Table 1 1. 2 input basic gates using
gate level modelling.
3. Gate level Verilog description for
half adder, full adder. 2. Full adder and full
subtractor using gate level
modelling.
4 1,3 1,2,3, 1. Data flow modeling- Continuous Write the verilog code,
4,6 assignment, Module instantiations, simulate and download to
net declaration, delays, expressions. FPGA/CPLD kit for the
following.
2. Data flow Verilog description of Refer Table 1
multiplexer and demultiplexer. 1. 4:1 Mux and 1:4 Demux
using data flow modeling.
3. Data flow Verilog description for
4-bit comparator 2. Comparator using data
flow modeling.
5 1,3 2,3,4, 1. System tasks-display, strobe, 1a.Write and execute simple
6 monitor, reset, stop, finish. programs to illustrate
Compiler directives- include, define. conditional statements.
Behavioral modeling- Always and 1b. Write and execute simple
Initial statements. programs to illustrate loops.
Refer Table 1
2. Procedural Assignments- 2. Write the verilog code,
Blocking and non-blocking simulate and download to
assignments. FPGA/CPLD kit for a 4-bit
Timing Control-Delay, Event ALU with any 2 arithmetic
and logical operations.
3. Conditional statements-if, if-else,
Case, Loops- While, For, Repeat,
Forever.
6 1,3 1,2,3, 1. Behavioral Verilog description 1. Write the verilog code,
4,6 for BCD to seven segment decoder simulate and download to
for common anode display using if- FPGA/CPLD kit for a BCD to
else, Case. seven segment decoder using
Refer Table 1 case statement.
2. Traffic light controller using
Behavioral description. 2. Write and simulate a Test
bench for half adder.
3. Test bench- Need, Importance,
testbench for half adder.

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7 2 1,2,3, 1. Sequential circuits - Introduction.
4,6,7 Flip flops- types, SR flip flop- Gate
level circuit using NAND gates, 1. Construct and test clocked
truth table, working, timing SR Flip flop using NAND
diagram. gates in digital trainer kit.
Refer Table 1
2. JK, JK-MS flip flops-Logic circuit,
truth table, working, timing 2. Implement D and T Flip
diagram. flops using JK flip flop in
digital trainer kit and
3. D, T flip flops-Logic circuit, truth observe the timing diagram.
table, working, timing diagram.
Relevance of Asynchronous inputs
to flip-flops.
8 2,3 1,2,3, 1. Verilog description of SR flip Write the verilog code,
4 flops using data flow modeling. simulate and download to
FPGA/CPLD kit for the
2. Verilog description of JK flip flop Refer Table 1 following.
using behavioral modeling.
1. SR, JK flip flops using data
3. Registers- Classification of flow modeling
registers, realization of simple (3 or 2.D, T flip flops using
4 bit) SISO using flip-flops. behavioral modeling
9 2,3 1,2,3, 1. Realization of SIPO, PISO and Construct and verify the
4,6,7 PIPO using flip flops. working of the following
using suitable IC in digital
2. Concept of universal shift- Refer Table 1 trainer kit
register. Ring counter and Johnson’s
counter (3 bit). 1. SISO, SIPO, PISO and
PIPO(4-bit) shift registers.
3. Verilog description of any one 2. Ring and Johnson
shift register using any modeling. counter(4-bit).
10 3 1,3,4, 1. Counters - definition, Construct and verify the
6,7 classification, modulus. Working working of the following
and realization of asynchronous (3 using digital trainer kit
bit/4 bit) counters using flip-flops.
Refer Table 1 1. 3 bit ripple counter using
2. Working and realization of IC 7476.
synchronous (3-bit/ 4-bit) counters 2. 4 bit counter as a
and their comparison. frequency divider.

3. Realization of partial mod (mod

n) counters-asynchronous,
synchronous.
11 3,4 1,2,6, 1. Realization of higher-mod 1. Write the verilog code,
7 counters using lower-mod counters. simulate and download to
Concept of up/ down counters. FPGA/CPLD kit for an
up/down counter using
2. Verilog description of any one Refer Table 1 behavioral modeling.
counter using any modeling.
2. Construct/Simulate and
3. Data converters- Need for DAC verify the working of R-2R
and ADC, DAC specifications, types, DAC.
working of Weighted resistor type.
12 4 1,2,3, 1. ADC specifications. types, 1. Construct/Simulate and
4,6,7 working of Flash ADC. Refer Table 1 verify the working of Flash
ADC.

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 2. Working of Successive
approximation and dual slope ADCs. 2. Illustrate the storing and
retrieving of data in RAM
3. Memory devices- Introduction, using suitable IC.
classification based on different
criteria, read and write operations.
13 4 1,2,3, 1. Introduction to PLDs- PAL, PLA,
4,7 CPLD, FPGA, ASIC.
IC Design Verification – Types & 1. Implementation of Boolean
Stages. expressions using PAL.
Refer Table 1
2. PAL- Architecture, 2. Implementation of Boolean
Implementation of a Boolean expressions using PLA.
expressions using PAL.

3. PLA-Architecture,
Implementation of a Boolean
expressions using PLA.
Total in hours 39 13 52

Note: 1) In Practice sessions Video demonstration should be followed by MCQs/Quiz/Subjective

questions and the evaluation has to be documented.
2) In Practice sessions, all circuits should be simulated using suitable software before its construction
and verification.

TABLE 1: Suggested activities for tutorials

The list is shared as an example and not inclusive of all possible activities of the course.
The list of activities for one week can be shared among teams in a batch of students.

Week Suggested activities for tutorials

No.

1. Explain the typical design flow for VLSI IC Circuits.

01
2. Give a presentation on comparison of different types of HDLs.

3. Give a presentation on comparison of different types of modeling in Verilog.

1. Prepare a report on declaration and initialization of variables of different data types in

02 Verilog.

2. Prepare a report on hierarchy of operators.

1. Explain basic components of a module? Which components are mandatory?

03
2. Prepare a report on Hierarchical names for variables.

3. Write and explain a Verilog code for 4:1 mux and 1:4 demux using gate level modeling.

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 1. Write and explain the Verilog code for full adder using data flow modeling.
04
2 Write and explain the Verilog code for 8:1 mux using data flow modeling.

1.Give a presentation on the differences between tasks and functions

05
2. Illustrate the use of system tasks with examples.

3. Illustrate the use of gate delays to model timing for a simple logic equation.

1. Compare if-else and case statements with the help of examples.

06
2. Compare all loops with the help of examples.

3. Write and explain the verilog code for full subtractor and 1:8 demux using behavioral
modeling.

4. Explain the Verilog Test bench with an example to verify the HDL designs.

1. Prepare a report on differences between Combinational and Sequential circuits with

07 examples.

2. Give a presentation on application of flip flop as bounce elimination switch.

3. Demonstrate the working of flip flop as a one bit memory element.

1. Prepare a report on flip flop ICs and their features.

08
2. Give a presentation on eliminating race -around condition in JK flip flop.

3. Compare the advantages and disadvantages of all flip flops.

1. Prepare a report on shift register ICs and their features.

09
2. Give a presentation on applications of shift registers in real life.

3. Demonstrate the working of IC 7495 as shift register.

1. Prepare a report on differences between asynchronous and synchronous counters.

10
2. Give a presentation on how counters can be used in a simple car parking system.

3. Give a presentation on implementation of footfall counter for various purposes

1. Prepare a report & explain the specifications of DAC and ADC ICs.
11
2. Give a presentation on any application of DAC in real life.

3. Give a presentation on any application of ADC in real life.

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 1. Prepare a report & explain the types of RAM and ROM.
12
2. Give a presentation on usage of RAM and ROM in different digital devices.

1. Study the latest technological changes in this course and present the impact of these changes
13 on industry.

2. Prepare a report on CPLD, FPGA and ASIC and its applications.

3. Give a presentation on importance or scope of Design Verification in Integrated circuit

designs.

LINKS.
1. https://verilogguide.readthedocs.io/en/latest/verilog/testbench.html
2. https://youtu.be/XES0QUi8ttY(week 11, exp 2)
3. https://www.youtube.com/watch?v=krmXg-WTbIU (week 12, exp 1)
4. http://www.asicguru.com/verilog/tutorial/system-tasks-and-functions/68/.
5. https://youtu.be/vHlg__QLGIQ (week 7,exp 3)
6. https://youtu.be/AtX5x53FcLI (week 9,exp 3)
7. https://youtu.be/Bx_4rsUAGoM
8. https://www.irisys.net/people-counting.

4. CIE and SEE Assessment Methodologies

Sl. Assessment Test Week Duration Max marks Conversion

No In minutes
1. CIE-1 Written Test 5 80 30 Average of three
2. CIE-2 Written Test 9 80 30 tests
3 CIE-3 Written Test 13 80 30 30
4. CIE-4 Skill Test-Practice 6 180 100 Average of two skill
5 CIE-5 Skill Test-Practice 12 180 100 tests
20
6 CIE-6 Portfolio continuous 1-13 10 10
evaluation of Activity through
Rubrics
Total CIE Marks 60
Semester End Examination (Practice) 180 100 40
Total Marks 100

5. Format for CIE (1,2,3) Written Test

Course Name Logic Design Using Verilog Test I/II/III Sem III/IV
Course Code 20EC32P Duration 80 Min Marks 30
Note: Answer any one full question from each section. Each full question carries 10 marks.
Section Assessment Questions Cognitive Course Marks
Levels Outcome
I 1

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 2
II 3
4
III 5
6
Note for the Course coordinator: Each question may have one, two or three subdivisions. Optional
questions in each section carry the same weightage of marks, Cognitive level and course outcomes.

5. (a) Format for CIE-4 Skill Test -Practice.

SL.
COs Particulars/Dimension Marks
No.

List the types of Verilog modelling and the use of each model for specific
1 1 20
application.
Write two Verilog programs on combinational circuits for a
given application -40 Marks
2 3 70
Simulation - 20 Marks
Download to FPGA kit - 10 Marks
3 1,3 PortFolio evaluation of Practice sessions through rubrics 10
Total Marks 100

5. (b) Format for CIE-5 Skill Test - Practice.

SL.
COs Particulars/Dimension Marks
No.

Write a Sequential circuit for a given application -20 Marks

1 2 Conduction using DTK -20 Marks 50
Output -10 Marks
Write a Verilog program on Sequential circuits for a given application - 10
Marks
2 3 20
Simulation -5 Marks
Output - 5 Marks
Identify various types of A to D, D to A converters/ memory for a given
3 4 application & select the appropriate converters/ memory types needed to 20
obtain the required output.

4 2,3,4 Portfolio evaluation of Practice sessions through rubrics. 10

Total Marks 100

6. Rubrics for Assessment of Activity (Qualitative Assessment)

Sl. No. Dimension Beginner Intermedia Good Advanced Expert Students
te Score
2 4 6 8 10

1 Descriptor Descriptor Descriptor Descriptor Descriptor 8

2 Descriptor Descriptor Descriptor Descriptor Descriptor 6
3 Descriptor Descriptor Descriptor Descriptor Descriptor 2
4 Descriptor Descriptor Descriptor Descriptor Descriptor 2
Average Marks= (8+6+2+2)/4=4.5 5
Note: Dimension and Descriptor shall be defined by the respective course coordinator as per the activities

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7. Reference:
Sl. No. Description
1 Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic
2 Verilog HDL by Samir Palnikar
3 Introduction to Verilog-Peter M Nyasulu
4 Verilog Tutorial-Deepak Kumar Tala

8. SEE Scheme of Evaluation

SL.
COs Particulars/Dimension Marks
No.

1 1 List the types of Verilog modelling and the use of each model for specific 10
application
Write a Sequential circuit for a given application -10 Marks
2 3 Conduction using DTK -10 Marks 30
Output -10 Marks
Write a Verilog program for a given application - 10 Marks
3 2 Simulation - 10 Marks 30
Download to FPGA kit- - 10 Marks
Identify various types of A to D, D to A converters and memory and for a given
4 4 application & select the appropriate converters and/or memory types needed to 10
obtain the given output.

1,2,
5 Viva-Voce 20
3,4

Total Marks 100

9. Equipment/software list with Specification for a batch of 20 students

Sl. Particulars Specification Quantity

No.
Computers Intel Core i5 11th gen/8GB RAM/1 20
1
TB HDD/256GB SSD/ Graphics 2 GB
2 Xilinx software
3 Digital trainer kits 20
4 Verilog kits 20
5 Dual trace oscilloscope 20-30MHz 10
6 Digital multimeters 05
7 Patch cards different length 250
8 Digital IC Tester 02
9 ICs 10 each
7400,7402,7404,7408,7432,7486,7442,
7445,7446,7474,7476,7427,7489,7490,
7494,7495,74141,74148,74153,74157,
74155,74193,74194,DAC0808,ADC-
0800,741

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