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    DFT Interview Questions

    Uploaded by

    rupesh kumar
    The document contains 55 interview questions related to digital circuit design for testability (DFT). Some of the topics covered include scan insertion steps, clock gating cells, scan chains, test coverage, ATPG outputs, fault models like stuck-at and transition delay faults, decompression, compression, and techniques to improve testability like on-chip compression and modular ATPG.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    DFT Interview Questions

    Uploaded by

    rupesh kumar
    3K views2 pages
    The document contains 55 interview questions related to digital circuit design for testability (DFT). Some of the topics covered include scan insertion steps, clock gating cells, scan chains, test coverage, ATPG outputs, fault models like stuck-at and transition delay faults, decompression, compression, and techniques to improve testability like on-chip compression and modular ATPG.

    Original Description:

    Frequently asked DFT questions

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    The document contains 55 interview questions related to digital circuit design for testability (DFT). Some of the topics covered include scan insertion steps, clock gating cells, scan chains, test coverage, ATPG outputs, fault models like stuck-at and transition delay faults, decompression, compression, and techniques to improve testability like on-chip compression and modular ATPG.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    3K views2 pages

    DFT Interview Questions

    Uploaded by

    rupesh kumar
    The document contains 55 interview questions related to digital circuit design for testability (DFT). Some of the topics covered include scan insertion steps, clock gating cells, scan chains, test coverage, ATPG outputs, fault models like stuck-at and transition delay faults, decompression, compression, and techniques to improve testability like on-chip compression and modular ATPG.

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    © All Rights Reserved
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    DFT Interview Questions

    1. Explain the scan insertion steps?


    2. Basic things to take care for scan insertion?
    3. Explain DRC’s which you have faced with an example?
    4. Why we do Test Point Insertion?
    5. What is the gate count and flop count in your previous project?
    6. Explain Decompressor logic?
    7. What is SDC? What it contains?
    8. Why we need clock gating cell in design?
    9. Explain the structure of ICG cell?
    10. Why we need latch in ICG cell?
    11. What is scan DFF?
    12. Explain the operation of three stiched ff’s?
    13. How do you decide number of chains in the design?
    14. If you know number of ff’s and number of channels for scan then how do you
    decide number of chains should be there?
    15. What is Lock up Latch? Why do we use this?
    16. What is manufacturing defects?
    17. What is clock latency? Will it affect shifting?
    18. What is clock skew?
    19. Draw 2x1 MUX using 2 input NAND gates?
    20. What is CTL? Where it is used?
    21. Explain Decompressor and Compactor?
    22. Why by increasing compression Ratio,The Test coverage decreases?
    23. How many clocks are there in your design?
    24. What are the things we have to take care of during OCC insertion?
    25. In which path we add lock up latch,data or clock?
    26. How to remove combinational feedback loop?
    27. What is flop tray?Why we need this?
    28. Why we go for DFT?
    29. Can we manually make scan chains?Reason for Yes or No?
    30. What is the coverage improvement you did?
    31. What is meant by AU fault?
    32. How much test coverage you got in last project?where were you losing rest of
    coverage?
    33. What are the files needed for Scan Insetion and what is it’s Output?
    34. What are the files needed for ATPG and what is it’s output?
    35. What is Stuck-At fault?
    36. What is Transition faults?
    37. What is difference between Transition Delay and Path Delay ?
    38. What is SPF? Explain?
    39. Explain Fault Classes?
    40. What do you mean by Fault Collapsing?
    41. Why do we need two pulses in capture for transition delay fault checking?
    42. How two pulses is coming in Transition?
    43. Briefly explain the design of OCC?
    44. What are the DRC’s you faced in ATPG?
    45. How to improve transition test coverage?
    46. What do you mean by AU.TC?
    47. If TDF is done then Path Delay is required or not?
    48. What is Redundant fault? Explain with an example?
    49. What are parallel patterns?
    50. Name some DRC’s which give coverage loss?
    51. How test data volume and text time reduced due to compression?
    52. What do you mean by Tester Time?
    53. How DFT vector is different from functional vector?
    54. What do you mean by Modular ATPG/ EDT?
    55. Why we need to do Simulations?
    56.

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