Consortium Techno 0019

3D simulation of Nanowire by Full-Real Space NEGF
Simulator
Nima Dehdashti, Aryan Afzalian, Chi-Woo Lee, Ran Yan, G. Fagas and Jean-Pierre Colinge
Tyndall National Institute, Lee Malting, Prospect Row, Cork, Ireland
1. Abstract speed up of the solver with the number of CPUs used.

In this article, we present the effects of device Details about numerical implementation of NEGF
parameters variations on the electrical characteristics of formalism can be found in the literature.
rectangular Nanowire. Our three dimensional (3D)
device simulator is based on the Non Equilibrium Green 4. Simulation Results
Function (NEGF) formalism. Starting from a basic Figure 1 shows the schematic structure of Triple-
structure GAA Nanowire with a gate length of 10 nm, Gate rectangular Nanowire created by COMSOL
variation of gate length and channel thickness was MultiPhysics®. The NEGF mesh can be chosen to be
carried out in connection with the numerical calculation uniform or non-uniform depending on the problem at
of device characteristics. In this work Quantum hand. Figure 2 shows the 3D electron density in the
transport equations are solved in 3D by NEGF method nanowire at saturation. Figure 3. Shows the potential
in active area of the device to obtain the charge density profile cut in the middle of the device (not in
and Poisson’s equation is solved in entire domain of saturation). Figure 4 shows the I-V characteristics for
simulation to get potential profile. triple-gate Nanowire with different silicon
thicknesses/width (Wsi=Tsi). the variations of different
2. Introduction electrical characteristics such as Ioff, Vth and
Current technology pushes device dimensions subthreshold swing (SS) can easily be derived from this
toward limits where the traditional semiclassical graph. Figure 5 shows the transmission versus energy
Boltzmann theory can no longer be applied and full for different silicon thicknesses. One can see that as the
quantum mechanical approaches which describe the thickness increases the number of energy level increases
quantum transport in nanostructures are required. and the separation between subbands become smaller.
Recently reported device structures have metal-oxide Figure 6 shows the efficiency of the parallel
semiconductor (MOS) channel lengths in the order of 10 algorithm. In calculating the efficiency we have
nm or even smaller. Multigate devices and other neglected the communication time between CPUs and
nanowire transistors are considered to be the promising other parameters. In general, we have defined the
candidate for the nanoscale regime. Numerical device efficiency as follow:
simulation is an important procedure for the design and Time _ serial(1 CPU )
Speedup/ Efficiency =
optimization of such novel semiconductor devices. Time _ parallel(1 CPU )
Advantages are the calculation of the electrical behavior Where the serial and parallel times are the time spent
before the fabrication process, the calculation and in the Recursive algorithm only.
visualization of values such as the carrier concentration
profile and the potential distribution inside a device.
3. Device simulation
The simulation procedure consists in solving the
Poisson and NEGF equations self-consistently until
convergence is reached. NEGF equation is solved by
discretizing the 3D effective-mass Hamiltonian using a
Finite Difference Method (FDM). We have used
COMSOL MultiPhysics® Software to solve the 3D
Poisson equation. This package uses the finite element
method (FEM) with irregular mesh to solve the
Poisson’s equation. We have parallelized the quantum
transport equation using Message Passing Interface
Fig.1: Schematic view of Silicon Nanowire Transistor. The
(MPI) and run it on the SFI400 UNIX Cluster available
irregular mesh in the geometry is generated by COMSOL
in the Tyndall National Institute. Neglecting the MultiPhysics® to solve Poisson equation.
communication overhead between CPUs we got a linear
Fig.2: Three dimensional Electron Density in the active
region of TripleGate Nanowire Transistor with 3nm cross
section. VG=? and VD =?
Fig.5: Transmission Vs Energy for Nanowire with different
cross-section. The number of subbands and their spacing
varies with silicon thickness.
Fig.6: Speedup/efficiency in parallelizing RGF algorithm over

Fig.3: Potential profile cut in the middle of the device with energy space. It is clear that almost a linear efficiency can be
Tsi=3nm, Vds=0.05 V. achieved neglecting the time required to communicate
between CPUs.
.
5. Conclusions
In this paper, we have shown the development of
three dimension real-space Device simulator based on
Non-equilibrium Green Function formalism.
Furthermore we parallelized the simulator in order to be
fast and be able to simulate large device structures. The
speed and numerical stability of the simulator has been
verified by applying it to different Nanowire device
structures.
Acknowledgements
This material is based upon works supported by Science
Foundation Ireland under Grant 05/IN/I888.
Fig.4: I-V characteristic Triple_Gate Nanowire device with References

Lgate =10nm and variable Silicon Thickness. The variation of [1] Svizhenko, A. et al, J. Appl. Phys. 91, 2343–2354 (2002).
Io ff, SS and Vth can easily be seen from this graph. VD=?
[2] Nima Dehdashti et al, Amherst, USA; 10-08-2007 - 10-10-
2007; in: "Proc. of IWCE", (2007), 175 - 176.

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3D simulation of Nanowire by Full-Real Space NEGF

1. Abstract speed up of the solver with the number of CPUs used.

Fig.6: Speedup/efficiency in parallelizing RGF algorithm over

Fig.4: I-V characteristic Triple_Gate Nanowire device with References

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