Unit 5

Body effect in MOS:
All MOS transistors are usually fabricated on a common substrate and substrate (body)
voltage of all devices is normally constant. However, as we shall see in subsequent chapters,
when circuits are realized using a number of MOS devices, several devices are connected in
series. This results in different source potentials for different devices. It may be noted that the
threshold voltage Vt is not constant with respect to the voltage difference between the
substrate and the source of the MOS transistor. This is known as the substrate-bias effect or
body effect. Increasing the Vsb causes the channel to be depleted of charge carries and this
leads to increase in the threshold voltage.
Resistive Load NMOS inverter
Vout= Vdd – iRRL

IR = Ids = K [(Vgs - Vtn)^2 ]/2
Voltage Transfer Characteristics of NMOS
VOH: Maximum output voltage when the output level is logic " 1"
VOL :Minimum output voltage when the output level is logic "0"
VIL : Maximum input voltage which can be interpreted as logic "0"
VIH : Minimum input voltage which can be interpreted as logic " 1"
Voltage transfer characteristics CMOS Inverter
Region-1
In this region the input is in the range of (0,Vtn). Since the input voltage is less than Vtn,
the NMOS is in cut-off region. No current flows from Vdd to Vss, The entire Vdd will
appear at the Output terminal.
NMOS is in cut-off as Vgs < Vtn
PMOS is in linear as Vgsp < Vtp and Vdsp > Vgsp -Vtp.
Zero current flows from supply voltage and the power dissipation is zero.
Region-2
In this region the input is in the range of (Vtn,Vdd/2). Since the input voltage is greater
than Vtn the NMOS is conducting and it jumps to saturation as it has large Vds across
it(Vout is high). PMOS still remains in the linear region.
NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.
PMOS is in linear region as Vdsp > Vgsp -Vtp.
since both the transistors are conducting some amount of current flows from supply in
this region.
Region-3
In this region the input voltage is Vdd/2. At this point the output voltage is also Vdd/2 as
one can see in figure-2. At this voltage both the NMOS and PMOS are in saturation and
the output drops drastically from Vdd to Vdd/2. At this point a large amount of current
flows from the supply. Most of the power consumed in CMOS inverter is at this point. So
care should be taken that the Input should not stay at Vdd/2 for more amount of time.
NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.
PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.
Large amount of current is drawn from supply and hence large power dissipation.
Region-4
In this region the input voltage is in the range of (Vdd/2 , Vdd-Vtp). Here the PMOS
remains in saturation as Vout < Vin - Vtp and Vgsp < Vtp. But the NMOS moves from
saturation to linear region since the drain to source voltage now is less than Vgsn-Vtn.
NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.
PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.
A medium amount of current is drawn as NMOS is in linear region and power dissipation
is low.
Region-5
In this region the input voltage is in the range of (Vdd-Vtp,Vdd). Here the PMOS moves
from saturation to cutoff as the Vgsp is so high that Vgsp > Vtp. The NMOS still remains
in linear as the drain to source voltage now is less than Vgsn-Vtn.
NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.
PMOS is in cutoff as Vgsp > Vtp.
Zero current flows from the supply and so the power dissipation is zero.
Driving Large capacitive loads

when signals are propagated from the chip to off chip destinations we can face problems
to drive large capacitive loads. Generally off chip capacitances may be several orders
higher than on chip values.
The capacitances which of this order must be driven through low resistances, otherwise
excessively long delays will occur. Large capacitance is presented at the input, which in
turn slows down the rate of change of voltage at input.
Cascaded Inverters as drivers
Inverters to drive large capacitive loads must be present low pull-up and pull down
resistance. For MOS circuits low resistance values imply low L:W ratio. Since length L
cannot be reduced below the minimum feature size, the channels must be made very wide
to reduce resistance value. Consider N cascaded inverters as on increasing the width
factor of ‘f’ than the previous stage as shown in figure
As the width factor increases, the capacitive load presented at the inverter input increases
and the area occupied increases also. It is observed that as the width increases, the
number N of stages are decreased to drive a particular value of C L. Thus with large
f(width), N decreases but delay per stage increases for 4:1 n MOS inverters.
Delay per stage = fτ for ∆Vin
=4fτ for ∆-Vin

Where ∆Vin indicates logic 0 to 1 transition and
∆-Vin indicates logic 1 to 0 transition of Vin
Total delay per nMOS pair = 4fτ
Super buffers
Generally the pull-up and the pull down transistors are not equally capable to drive
capacitive loads. This asymmetry is avoided in super buffers. Basically, a super buffer is
a symmetric inverting or non inverting driver that can supply (or) remove large currents
and is nearly symmetrical in its ability to drive capacitive load. It can switch large
capacitive loads than an inverter. An inverting type nMOS super buffer as shown in
figure.
 Consider a positive going (0 to 1) transition at input Vin turns ON the inverter formed
by T1 and T2.
 With a small delay, the gate of T3 is pulled down to 0 volts. Thus, device T3 is cut off.
Since gate of T4 is connected to Vin, it is turned ON and the output is pulled down
very fast.
o For the opposite transition of Vin (1 to 0), Vin drops to 0 volts. The gate of
transistor
o T3 is allowed to rise to VDD quickly.
 Simultaneously the low Vin turns off T4 very fast. This makes T3 to conduct with its
gate voltage approximately equal to VDD.
 This gate voltage is twice the average voltage that would appear if the gate was
connected to the source as in the conventional nMOS inverter.
 Now as Idsα Vgs , doubling the effective Vgs increases the current and there by reduces
the delay in charging at the load capacitor of the output. The result is more
symmetrical transition.
Bi-CMOS drivers
 In Bi-CMOS technology we use bipolar transistor drivers as the output stage of

inverter and logic gate circuits.
 In bipolar transistors, there is an exponential dependence of the collector (output)
current on the base to emitter (input) voltage Vbe.
 Hence, the bipolar transistors can be operated with much smaller input voltage swings
than MOS transistors and still switch large current.
 Another consideration in bipolar devices is that the temperature effect on input
voltage Vbe.
 In bipolar transistor, Vbe is logarithmically dependent on collector current IC and also
other parameters such as base width, doping level, electron mobility.
 Now, the temperature differences across an IC are not very high. Thus the Vbe values
of the bipolar devices spread over the chip remain same and do not differ by more
than a few mV.
Power Consumption in a CMOS circuit
Two components determine the power consumption in a CMOS circuit:

• Static power consumption
• Dynamic power consumption
CMOS devices have very low static power consumption, which is the result of leakage
current. This power consumption occurs when all inputs are held at some valid logic level
and the circuit is not in charging states. But, when switching at a high frequency, dynamic
power consumption can contribute significantly to overall power consumption. Charging and
discharging a capacitive output load further increases this dynamic power consumption.
Static power consumption
Typically, all low-voltage devices have a CMOS inverter in the input and output stage.
Therefore, for a clear understanding of static power consumption, refer to the CMOS inverter
modes shown in Figure 1.
Figure a
As shown in Figure a, if the input is at logic 0, the n-MOS device is OFF, and the p-MOS
device is ON (Case 1). The output voltage is VCC, or logic 1. Similarly, when the input is at
logic 1, the associated n-MOS device is biased ON and the p-MOS device is OFF. The output
voltage is GND, or logic 0. Note that one of the transistors is always OFF when the gate is in
either of these logic states. Since no current flows into the gate terminal, and there is no dc
current path from VCC to GND, the resultant quiescent (steady-state) current is zero, hence,
static power consumption (Pq) is zero However, there is a small amount of static power
consumption due to reverse-bias leakage between diffused regions and the substrate. This
leakage inside a device can be explained with a simple model that describes the parasitic
diodes of a CMOS inverter, as shown in Figure b.
Figure b
The source drain diffusion and N-well diffusion form parasitic diodes. In Figure b, the
parasitic diodes are shown between the N-well and substrate. Because parasitic diodes are
reverse biased,only their leakage currents contribute to static power consumption.
Acknowledgement
www.nptel.ac.in
https://www.allaboutcircuits.com/

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Body effect in MOS:

Resistive Load NMOS inverter

Vout= Vdd – iRRL

Voltage Transfer Characteristics of NMOS

VIL : Maximum input voltage which can be interpreted as logic "0"

Driving Large capacitive loads

Delay per stage = fτ for ∆Vin

=4fτ for ∆-Vin

∆-Vin indicates logic 1 to 0 transition of Vin

Total delay per nMOS pair = 4fτ

 In Bi-CMOS technology we use bipolar transistor drivers as the output stage of

Power Consumption in a CMOS circuit

Two components determine the power consumption in a CMOS circuit:

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