VLSI TECHNOLOGY

UNIT -1
MOS TRANSISTOR
MOS transistor structure
A MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or MOS, as is
commonly called, is an electronic device which converts change in input voltage
into a change in output current. The basic structure of a MOS transistor (as seen
sideways) is as shown in figure 1. The substrate is a lightly doped
semiconductor. Source and Drain regions are heavily doped regions of type
opposite to substrate. In-between source and drain is a region called channel.
Above the channel is a very thin layer of oxide.

The voltage is applied to input terminal, which is called "Gate" terminal. If

sufficient voltage is applied at the gate terminal, a channel gets formed between
source and drain terminals. Depending upon the nature of channel formed, MOS
is termed as N-MOS or P-MOS.

N-MOS: For an N-MOS, substrate is P-type, source and drain regions are N-
type. Application of a positive voltage at Gate terminal with respect to substrate
will result in formation of channel of electrons.

P-MOS: For a P-MOS, substrate is N-type, source and drain regions are P-type.
Application of a negative voltage at Gate terminal with respect to substrate will
result in formation of channel of holes.
The Fluid Model :
The operation of an MOS transistor can be analyzed by using a suitable analytical technique,
which will give mathematical expressions for different device character- istics. This, however,
requires an in-depth knowledge of the physics of the device. Sometimes, it is possible to develop
an intuitive understanding about the operation of a system by visualizing the physical behavior
with the help of a simple fig.

MOS Transistors effective model. TheFluid model[1] is one such tool, which can be used to visu-
alize the behavior of charge-controlled devices such as MOS transistors, charge- coupled devices
(CCDs), and bucket-brigade devices (BBDs). Using this model, even a novice can understand the
operation of these devices. The model is based on two simple ideas: (a) Electrical charge is
considered as fluid, which can move from one place to another depending on the difference in
their level, of one from the other, just like a fluid and (b) electrical potentials can be mapped into
the geometry of a container, in which the fluid can move around.

Mos capacitor:
The capacitance of the MOS capacitor depends upon the voltage
applied on the gate terminal. Usually the body is grounded when
the gate voltage is applied.
The flat band voltage is an important term related to the MOS
capacitor. It is defined as the voltage at which there is no charge on
the capacitor plates and hence there is no static electric field
across the oxide. An applied positive gate voltage larger than the
flat band voltage (Vgb > Vfb) then positive charge is induced on the
metal (poly silicon) gate The only negative charged electrons are
available as negative charges and they accumulate at the surface.
This is known as surface accumulation.

If the applied gate voltage is lower than the flat band voltage (V gb <
Vfb) then a negative charge is induced at the interface between the
poly-silicon gate and the oxide and positive charge in the
semiconductor.
This is only possible by pushing the negatively charged electrons
away from the surface exposing the fixed positive charges from
donors. This is known as surface depletion.

The MOS capacitor is not a widely used device in itself. However,

it is part of the MOS transistor which is by far the most widely used
semiconductor device.
The typical capacitance-voltage characteristics of a MOS capacitor
with n-type body is given below,

Capacitance vs. Gate Voltage (CV) diagram of a MOS Capacitor.

The flatband voltage (Vfb) separates the Accumulation region from
the Depletion region. The threshold voltage (Vth) separates the
depletion region from the inversion region.
MOS TRANSISTOR:
Regions of operation of MOS transistors

A Metal Oxide Semiconductor Field Effect Transistors (MOSFET, or simply, MOS) is a

four terminal device. Figure 1 below shows the general representation of an N-MOS (for
PMOS, simply replace N regions with P and vice-versa). MOS is a Voltage-controlled
current source as the current through MOS is a function of relative voltage levels of its
terminals. The relative voltages of gate, drain and source terminals (assuming bulk or
substrate to be at same voltage as source) determine the magnitude of current flowing
in MOS. In each of these regions, we can represent the current as a function of gate-to-
source voltage (VGS) and drain-to-source voltage (VDS).
 MOS transistor - a 4-transistor device

In a MOS device, the current flows on formation of channel of carriers between source
and drain terminals. For this, voltage at gate terminal needs to be such that it attracts
carriers of appropriate type towards itself. When sufficient carriers are attracted towards
gate, channel is said to be formed. A current, then, flows between source and drain
terminals depending upon the voltage levels of these terminals. The voltage level of
substrate also impacts the magnitude of current as it also determines the level of
carriers in the channel.

For an N-MOS device, the channel is formed by electrons. So, to attract electrons, gate
voltage must be greater than source voltage. For the formation of channel, the
difference between VG and VS (VG – VS) must be greater than Vth (threshold voltage of
the MOS).

Threshold voltage is defined as the minimum difference in gate-to-source voltage

needed for the formation of channel in a MOS device. For NMOS, V th is positive as for
channel formation gate needs to be at higher voltage as explained above. Similarly, for
PMOS, Vth is negative as gate needs to be at lower voltage than source for channel to
be formed.

On increasing gate voltage beyond threshold voltage, current through MOS increases
with increasing gate voltage. Also, if we increase drain voltage keeping gate voltage
constant, current increases till a particular drain voltage. After that, increasing drain
voltage does not affect the current. Depending upon the relative voltages of its
terminals, MOS is said to operate in either of the cut-off, linear or saturation region.

 Cut off region – A MOS device is said to be operating when the gate-to-source
voltage is less than Vth. Thus, for MOS to be in cut-off region, the necessary condition is
–
0 < VGS < Vth - for NMOS
0 > VGS > Vth - for PMOS (as threshold voltage of PMOS is
negative)

Cut-off region is also known as sub-threshold region. In this region, the dependence of
current on gate voltage is exponential. The magnitude of current flowing through MOS
in cut-off region is negligible as the channel is not present. The conduction happening in
this region is known as sub-threshold conduction.
 Linear or non saturation region – For an NMOS, as gate voltage increases
beyond threshold voltage, channel is formed between source and drain terminals. Now,
if there is voltage difference between source and drain, current will flow. The magnitude
of current increases linearly with increasing drain voltage till a particular drain voltage
determined by the following relations –
VGS ≥ Vth
VDS < VGS – Vth

The current is, then, represented as a linear function of gate-to-source and drain-to-
source voltages. That is why, MOS is said to be operating in linear region. The linear
region voltage-current relation is given as follows:
Id(Linear) = µ Cox W/L (Vgs – Vth – Vds/2) Vds.
Similarly, for P-MOS transistor, condition for P-MOS to be in linear region is represented
as:
VGS < Vth OR VSG > |Vth|
And VDS > VGS + Vth OR VSD < VSG - |Vth|
 Saturation Region – For an NMOS, at a particular gate and source voltage,
there is a particular level of voltage for drain, beyond which, increasing drain voltage
seems to have no effect on current. When a MOS operates in this region, it is said to be
in saturation. The condition is given as:
VGS ≥ Vth
VDS > VGS – Vth
The current, now, is a function only of gate and source voltages:
Id(saturation) = µ Cox W/L (Vgs – Vth – Vds/2)2
MOSFET Characteristics

Depletion Type mosfet

A depletion type mosfet has a channel permanently
fabricated at the time of its construction itself
N-channel depletion-type MOSFET Characteristics

As shown in above diagram, gate-to-source voltage is set

to zero by shorting gate and source and a voltage V DS is
applied between drain and source.

Since VGS=0 therefore, no charging of capacitor therefore

no change in channel. Due to VDS , a current IDSS flows
between D and S.Lets set VGS=-1V now. This charges
capacitor with gate plate negative and channel as
positive plate.

Depending upon the magnitude of VGS , a level of

recombination of electrons and holes will occur , reducing
the number of free electrons available for conduction.
Recombination reduces channel width or increases
channel resistance and ∴ IDS decreases. As we keep
increasing the negative VGS , IDS keep decreasing and
finally becomes zero at particular VGS. This VGS is known
as pinch-off voltage VP .
If VGS is set +ve say +1V , just opposite process occurs.
+ve VGS charges gate plate +ve and channel as –ve
plate.
This increases the channel width or decreases channel
resistance. Hence, IDS increases. Transfer characteristics
are extrapolated from drain characteristics.
As evident from characteristics curves, a MOSFET has
three operating regions :-
(1) Cut-off region :- In cut-off region, MOSFET will be OFF
i.e IDS=0 and it behaves like an open-circuit between D
and S terminals. This operation is obtained by
keeping VGS (negative) ≥ VP .
(2) Ohmic or linear region :- In ohmic region, IDS increases
almost linearly with an increase in VDS . MOSFETs
operating in this region are used as amplifiers.
(3) Saturation region :- In saturation region, MOSFET has
its IDS constant inspite of an increase in VDS and it
behaves like a closed-switch between D and S terminals.

P-channel depletion-type MOSFET Characteristics

Characteristic explanation would be exactly similar as
that for n-channel except that the voltage and current
directions would be reversed.

P-channel Enhancement-type MOSFET

Characteristics

Enhancement Type mosfet

An enhancement type mosfet does not have a channel
permanently fabricated rather it is induced by applying a
voltage between gate and source.

N-channel Enhancement-type MOSFET

Characteristics
Lets set VGS=0V and apply a voltage VDS between drain
and source.

Since there is no channel fabricated in an enhancement

mosfet and no channel is induced as VGS=0V therefore
ID=0A.
Let make VGS some positive value say VGS=+4V .This +4V
charges capacitor with gate plate +ve and channel –ve.
Thus a channel is created. This created channel enables
conduction between D and S.
As we keep increasing VGS , the channel penetrates more
deeper into mosfet i.e channel width increases or channel
resistance decreases therefore drain current increases as
shown in below figure.

You may have noted a term VT in characteristics ,

called threshold voltage. It is the minimum gate-source
voltage VGS that must be applied so that drain current
ID just starts to flow.
 P-channel Enhancement-type MOSFET
Characteristics

Threshold voltage ;
The threshold voltage of a MOSFET (Metal-Oxide-Semiconductor Field-Effect
Transistor) is the minimum gate-to-source voltage required to create a
conducting channel between the source and drain terminals. The formula for the
threshold voltage of a MOSFET is:

Vth = VFB + 2ϕF + γ(sqrt(2ϕF + VSB) - sqrt(2ϕF))

where:

 Vth is the threshold voltage

 VFB is the flatband voltage, which is the voltage difference between the
gate and source terminals at which the MOSFET is just starting to
conduct
 ϕF is the Fermi potential, which is the potential difference between the
Fermi level and the intrinsic level in the semiconductor
 γ is the body-effect coefficient, which is a material-dependent
parameter that describes the sensitivity of the threshold voltage to
changes in the substrate voltage (VSB)
Note that the threshold voltage depends on several parameters such as the gate
oxide thickness, the doping concentration of the semiconductor, and the
temperature. Therefore, the formula for the threshold voltage of a MOSFET can
vary depending on the specific device and operating conditions.
Transconductance:
Transconductance (gm) is defined as the ratio between the change in output current
and the corresponding change in the input voltage of a MOSFET.
The SI unit of transconductance is Siemens (S). The transconductance value indicates
the sensitivity of MOSFET to input voltage change. It determines MOSFET's
amplification capabilities in small-signal applications. A higher transconductance value
enables greater amplification and improved linearity, making MOSFETs suitable for
applications such as audio amplifiers and RF circuits. The transconductance parameter
also influences biasing, stability, and power efficiency thus helping the PCB designers in
achieving optimal performance and efficiency in their circuit designs.

Factors Affecting Transconductance

The transconductance of a MOSFET is influenced by various factors that can impact its
performance and behavior. These factors include:

 Biasing Conditions: The biasing conditions determine the voltage difference

between the gate and source (VGS) and the drain current (ID). Different biasing
configurations can alter the MOSFET's transconductance value, affecting the
overall amplifier performance and linearity.
 Device Dimensions: The physical dimensions of the MOSFET, such as the
channel length and width, impact its transconductance. The channel dimensions
determine the effective width of the conducting channel, which affects the
mobility of charge carriers and the overall transconductance. Modifying the
channel dimensions during the fabrication process can result in MOSFETs with
varying transconductance characteristics.
 Material Properties: The choice of materials used in the MOSFET fabrication
process can influence transconductance. Different materials have distinct
electron mobility and charge carrier properties, which affect the device's
transconductance. The properties of the semiconductor substrate, gate oxide,
and other materials used in the MOSFET construction can impact its overall
performance.
 Temperature: MOSFETs are sensitive to temperature variations. Any change in
the temperature can affect the transconductance. Higher temperatures can result
in increased electron scattering, leading to a reduction in mobility and,
consequently, a decrease in transconductance.
 Process Variations: During the manufacturing process, there can be variations
in parameters such as doping concentration, oxide thickness, and channel
dimensions, which can affect the transconductance of MOSFETs. These process
variations can lead to device-to-device variations in transconductance, impacting
the consistency and performance of MOSFET-based circuits.
 Voltage Overdrive: It is defined as the difference between the gate-to-source
voltage (VGS) and the threshold voltage (Vth). Increasing the voltage overdrive
can enhance the channel modulation and increase the transconductance, leading
to improved amplification capabilities.
 Figure of merit
Figure of merit” (FOM) is a way of evaluating FETs. It takes into
account both their conduction losses and their switching losses.
Commonly, it’s calculated as on-resistance (R(DS)ON) times gate
charge (QG).

“Figure of merit” (FOM) is a way of evaluating FETs. It accounts for both

their conduction losses and their switching losses. Commonly, it’s calculated
as on-resistance (R(DS)ON) times gate charge (QG). QG is the charge that must
be brought to the gate of the MOSFET to turn it fully on. Design-wise, it’s
hard to reduce both at the same time, which makes their product a good
basis for comparison.

Of course, it’s only possible to make that comparison under a standard set of
conditions. That means both the gate-source voltage (V GS) that’s delivering
the charge and drain-source voltage (VDS) that’s being burned up in R(DS). (It
also means not just when the channel is fully on, but while R(DS) is ramping
up and down, too.) Complicating things, R (DS)ON varies a little with drain
current, so when comparing switching transistors, the operational value of ID
ought to be specified as well.

Sometimes, you will see a slightly different figure of merit: FOMSW, which is
the product of R(DS)ON and Q. It’s a characteristic called switching charge,
which is a little shorter than QG.

Body effect mosfet

Consider an NMOS device it will have p substrate and n channel. Now if the
substrate is at 0V then you will not see body effect but if the substrate voltage
is lower than 0V then the electrons will need more positive gate potential to get
attracted towards the channel because the substrate potential is acting against
the gate potential thus you will see the Vt of the NMOS getting increased. This is
body effect.

this answer assumes source is at ground. Body effect is also seen if VB is at

ground and the voltage of source is increased. It is the VSB that matters.
Channel length modulation :

Channel length modulation (CLM) is an effect in field effect transistors, a shortening of

the length of the inverted channel region with increase in drain bias for large drain biases. The result
of CLM is an increase in current with drain bias and a reduction of output resistance

Transitor as a switch
switching in Electronics
Semiconductor switching in electronic circuit is one of the important aspects. A
semiconductor device like a BJT or a MOSFET are generally operated as
switches i.e., they are either in ON state or in OFF state.

Ideal Switch Characteristics

For a semiconductor device, like a MOSFET, to act as an ideal switch, it must
have the following features:

 During ON state, there should not be any limit on the amount of current it
can carry.
 In OFF state, there should not be any limit on the blocking voltage.
 When the device is in ON state, there should be zero voltage drop.
 OFF state resistance should be infinite.
 Operating speed of the device has no limits.
Practical Switch Characteristics
But the World isn’t ideal and it is applicable even to our semiconductor switches.
In a practical situation, a semiconductor device like a MOSFET has the following
characteristics.

 During ON state, the power handling capabilities are limited i.e., limited
conduction current. The blocking voltage during OFF state is also limited.
 Finite turn on and turn off times, which limit the switching speed. Maximum
operating frequency is also limited.
 When the device is ON, there will be a finite on state resistance resulting in
a forward voltage drop. There will also be a finite off state resistance which
results in a reverse leakage current.
 A practical switch experiences power loses during on state, off state and
also during the transition state (on to off or off to on).
Working of a MOSFET as a Switch
If you understood the working of the MOSFET and its regions of operation, you
would have probably guessed how a MOSFET works as a switch. We will
understand the operation of a MOSFET as a switch by considering a simple
example circuit.
This is a simple circuit, where an N-Channel Enhancement mode MOSFET will
turn ON or OFF a light. In order to operate a MOSFET as a switch, it must be
operated in cut-off and linear (or triode) region.

Assume the device is initially OFF. The voltage across Gate and Source i.e.,
VGS is made appropriately positive (technically speaking, VGS > VTH), the MOSFET
enters linear region and the switch is ON. This makes the Light to turn ON.

If the input Gate voltage is 0V (or technically < VTH), the MOSFET enters cut-off
state and turns off. This in turn will make the light to turn OFF.
Transmission Gate
Connecting PMOS and NMOS devices together in parallel we can create a
basic bilateral CMOS switch, known commonly as a “Transmission Gate”.
Note that transmission gates are quite different from conventional CMOS logic
gates as the transmission gate is symmetrical, or bilateral, that is, the input
and output are interchangeable. This bilateral operation is shown in the
transmission gate symbol below which shows two superimposed triangles
pointing in opposite directions to indicate the two signal directions.

CMOS Transmission Gate

Two MOS transistors are connected back-to-back in parallel with an inverter

used between the gate of the NMOS and PMOS to provide the two
complementary control voltages. When the input control signal, VC is LOW,
both the NMOS and PMOS transistors are cut-off and the switch is open.
When VC is high, both devices are biased into conduction and the switch is
closed.
Thus the transmission gate acts as a “closed” switch when VC = 1, while the
gate acts as an “open” switch when VC = 0 operating as a voltage-controlled
switch. The bubble of the symbol indicating the gate of the PMOS FET.

Transmission Gate Boolean Expression

As with traditional logic gates, we can define the operation of a transmission
gate using both a truth table and boolean expression as follows.

Transmission Gate Truth Table

 Symbol Truth Table

Control A B

1 0 0

1 1 1

0 0 Hi-Z
Transmission Gate
0 1 Hi-Z

Boolean Expression B = A.Control Read as A AND Cont. gives B

We can see from the above truth table, that the output at B relies not only the
logic level of the input A, but also on the logic level present on the control
input. Thus the logic level value of B is defined as both A AND Control giving
us the boolean expression for a transmission gate of:
B = A.Control
Since the boolean expression of a transmission gate incorporates the logical
AND function, it is therefore possible to implement this operation using a
standard 2-input AND gate with one input being the data input while the other
is the control input as shown.

AND Gate Implementation

One other point to consider about transmission gates, a single NMOS or a
single PMOS on its own can be used as a CMOS switch, but the combination
of the two transistors in parallel has some advantages. An FET channel is
resistive so the ON-resistances of both transistors are effectively connected in
parallel.
As a FETs On-resistance is a function of the gate-to-source voltage, VGS, as
one transistor becomes less conducting due to the gate drive, the other
transistor takes over and becomes more conducting. Thus the combined
value of the two ON-resistances (as low as 2 or 3Ω) stays more or less
constant than would be the case for a single switching transistor on its own.
When can demonstrate this in the following diagram.

Transmission Gate ON-resistance

 UNIT-2

Fabrication Technology:
• Silicon of extremely high purity
– chemically purified then grown into large crystals
• Wafers
– crystals are sliced into wafers
– wafer diameter is currently 150mm, 200mm, 300mm
– wafer thickness <1mm
– surface is polished to optical smoothness
• Wafer is then ready for processing
• Each wafer will yield many chips
– chip die size varies from about 5mmx5mm to 15mmx15mm
– A whole wafer is processed at a time
• Different parts of each die will be made P-type or N-type (small
amount of other
atoms intentionally introduced - doping -implant)
• Interconnections are made with metal
• Insulation used is typically SiO2. SiN is also used. New materials
being investigated
(low-k dielectrics)
• nMOS Fabrication
• CMOS Fabrication
• p-well process
• n-well process
• twin-tub process
• All the devices on the wafer are made at the same time
• After the circuitry has been placed on the chip
• the chip is overglassed (with a passivation layer) to protect it
• only those areas which connect to the outside world will be left
uncovered (the
pads)
• The wafer finally passes to a test station
• test probes send test signal patterns to the chip and monitor the output
of the
chip
• The yield of a process is the percentage of die which pass this testing
• The wafer is then scribed and separated up into the individual chips.
These are then
packaged
• Chips are ‘binned’ according to their performance
basic Fabrication Steps
1. Oxidation
The process of growing a layer of silicon dioxide (SiO2)on the surface of a silicon wafer.

Oxidation is a process which converts silicon on the wafer into silicon dioxide. The chemical
reaction of silicon and oxygen already starts at room temperature but stops after a very thin
native oxide film. For an effective oxidation rate the wafer must be settled to a furnace with
oxygen or water vapor at elevated temperatures. Silicon dioxide layers are used as highquality
insulators or masks for ion implantation. The ability of silicon to form high quality silicon
dioxide is an important reason, why silicon is still the dominating material in IC fabrication.
OXIDATION TECHNIQUES 1.Cleaned wafers are placed in the wafer load station where dry
nitrogen (N2) is introduced into the chamber. The nitrogen prevents oxidation from occurring
while the furnace reaches the required temperature. 2.Once the specified temperature in the
chamber is reached, the nitrogen gas flow is shut off and oxygen (O2) is added to the chamber.
The source of the oxygen can be gas or water vapor depending upon the dry process or wet
process. •After the oxidation is complete and the oxide layer is the correct thickness, nitrogen is
reintroduced into the chamber to prevent further oxidation from occurring. •The wafers are then
removed from the chamber. After inspection, they are ready for further processing. •Thermal
oxidation can be either a dry or a wet process
Uses:
· Provide isolation between two layers
· Protect underlying material from contamination
· Very thin oxides (100 to 1000 Å) are grown using dry-oxidation techniques. Thicker oxides
(>1000 Å) are grown using wet oxidation techniques.
2. Diffusion
Movement of impurity atoms at the surface of the silicon into the bulk of the silicon - from
higher concentration to lower concentration. Diffusion typically done at high temperatures: 800
to 1400 °C.
Diffusion is the movement of impurity atoms in a semiconductor material at high temperatures.
The driving force of diffusion is the concentration gradient. There is a wide range of diffusivities
for the various dopant species, which depend on how easy the respective dopant impurity can
move through the material. Diffusion is applied to anneal the crystal defects after ion
implantation or to introduce dopant atoms into silicon from a chemical vapor source. In the last
case the diffusion time and temperature determine the depth of dopant penetration. Diffusion is
used to form the source, drain, and channel regions in a MOS transistor. But diffusion can also
be an unwanted parasitic effect, because it takes place during all high temperature process steps.

3. Ion Implantation

Ion implantation is the process by which impurity ions are accelerated to a high velocity
and physically lodged into the target.
· It is required to activate the impurity atoms and repair physical damage to the crystal
lattice. This step is done at 500 to 800 °C.
· Lower temperature process compared to diffusion.
· Can implant through surface layers, thus it is useful for field-threshold adjustment.
 · Unique doping profile available with buried concentration peak.

4. Deposition
A multitude of layers of different materials have to be deposited during the IC fabrication
process. The two most important deposition methods are the physical vapor deposition (PVD)
and the chemical vapor deposition (CVD). During PVD accelerated gas ions sputter particles
from a sputter target in a low pressure plasma chamber. The principle of CVD is a chemical
reaction of a gas mixture on the substrate surface at high temperatures. The need of high
temperatures is the most restricting factor for applying CVD. This problem can be avoided with
plasma enhanced chemical vapor deposition (PECVD), where the chemical reaction is enhanced
with radio frequencies instead of high temperatures. An important aspect for this technique is the
uniformity of the deposited material, especially the layer thickness. CVD has a better uniformity
than PVD.
Deposition is the means by which various materials are deposited on the silicon wafer.
Examples:
· Silicon nitride (Si3N4)
· Silicon dioxide (SiO2)
· Aluminum
· Polysilicon
There are various ways to deposit a meterial on a substrate:
· Chemical-vapor deposition (CVD)
· Low-pressure chemical-vapor deposition (LPCVD)
· Plasma-enhanced chemical-vapor deposition (PECVD)
· Sputter deposition
Materials deposited using these techniques cover the entire wafer.
5. Etching
Etching is the process of selectively removing a layer of material.
When etching is performed, the etchant may remove portions or all of:
· the desired material
· the underlying layer
· the masking layer
Important considerations:
· Anisotropy of the etch
A = 1 - (lateral etch rate / vertical etch rate)
· Selectivity of the etch (film to mask and film to substrate)
Sfilm-mask = film etch rate / mask etch rate
Desire perfect anisotropy (A=1) and invinite selectivity.
There are basically two types of etches:
· Wet etch, uses chemicals
· Dry etch, uses chemically active ionized gasses.

6. Photolithography
1. The photolithographic process "involves the transfer of the image from the mask to the
surface of the wafer by the use of UV light and a photoresist. Photoresists are chemical
compositions containing light sensitive material. They come in liquid form. There are two
types of photoresists: negative and positive. Exposure to UV light hardens a negative
photoresist and therefore the exposed resist becomes insoluble in a developer solution
while the unexposed resist is soluble. A positive resist becomes soft when exposed to UV
light. As a result, the exposed resist dissolves in the developer and unexposed resist
remains insoluble. The sensitivity of positive resist is less than that of a negative resist.
The application of thin film of photoresist over the wafer is achieved by placing a small
drop of resist on the top of the wafer and then spinning the wafer at high speed. This
results in a very thin, even layer of liquid resist over the wafer surface. The wafer is then
baked at 100oC in an oven to remove the excess solvent (prebaking). After cooling to
room temperature, the wafer is exposed to UV light through the mask and then developed
in a developer. It is again baked in an oven (postbaking) to increase the adherence of the
resist to the surface of the wafer. illustrates the steps involved in photolithographic
process. The process sequence for selective diffusion by photolithography is listed below:
1. Grow oxide 6. Remove photoresist from exposed portion 2. Coat photoresist 7.
Postbake 3. Postbake 8. Etch oxide to open window 4. Prebake 9. Strip photoresist 5.
Place reticle (mask) over photoresist 10. Diffuse impurity through window. There are
many methods of photoresist exposure through a mask. The simplest method is contact
printing in which the mask remains in contact with the photoresist. But if there are
particles protruding from the wafer surface, the mask is locally damaged by them.
Proximity printing partially overcome this problem. In proximity printing, the mask is
separated from the wafer by a small distance of about 20 µm. Another solution for mask
damage problem is 132 Introduction To Fabrication Technology projection printing in
which the mask is separated from the wafer, and its image is projected on the surface of
the wafer using an optical system
N-MOS Fabrication Steps
A brief introduction to the general aspects of the polysilicon gate self-aligning nMOS
fabrication process will now be given. As well as being relevant in their own right, the
fabrication processes used for nMOS are relevant to CMOS

BiCMOS which may be viewed as involving additional fabrication steps. Also, it

is clear that an appreciation of the fabrication processes will give an insight into

the way in which design information must be presented and into the reasons for

certain performance characteristics and limitations. An nMOS process is illustrated

and may be outlined as follows:

1. Processing is carried out on a thin wafer cut from a single crystal of silicon

of high purity into which the required p-impurities are introduced as the crystal

is grown. Such wafers are typically 75 to 150 mm in diameter and 0.4 mm

thick and are doped with, say, boron to impurity concentrations of 1015/cm3

to lO'61cm3 , giving resistivity in the approximate range 25 ohm cm to

2 ohm cm.
2. A layer of silicon dioxide (Si02), typically I itm thick, is grown all over the

surface of the wafer to protect the surface, act as a barrier to dopants during

processing, and provide a generally insulating substrate onto which other

layers may be deposited and patterned.

3. The surface is now covered with a photoresist which is deposited onto the

wafer and spun to achieve an even distribution of the required thickness.

4. The photoresist layer is then exposed to ultraviolet light through a mask which

defines those regions into which diffusion is to take place together with transistor

channels. Assume, for example, that those areas exposed to ultraviolet radiation

are polymerized (hardened), but that the areas required for diffusion are shielded

by the mask and remain unaffected.

5. These areas are subsequently readily etched away together with the underlying

silicon dioxide so that the wafer surface is exposed in the window defined by
the mask.
6. The remaining photoresist is removed and a thin layer of Si0 2 (0.1 Inn typical)

is grown over the entire chip surface and then polysilicon is deposited on top

of this to form the gate structure. The polysilicon layer consists of heavily

doped polysilicon deposited by chemical vapor deposition (CVD). In the

fabrication of fine pattern devices, precise control of thickness, impurity

concentration, and resistivity is necessary.

7. Further photoresist coating and masking allows the polysilicon to be patterned

(as shown in Step 6), and then the thin oxide is removed to expose areas into

which n-type impurities are to be diffused to form the source and drain as

shown. Diffusion is achieved by heating the wafer to a high temperature and

passing a gas containing the desired n-type impurity (for example, phosphorus)

over the surface as indicated in Figure 1-8. Note that the polysilicon with

underlying thin oxide and the thick oxide act as masks during diffusion -

the process is self-aligning.

 8. Thick oxide (Si02) is grown over all again and is then masked with photoresist

and etched to expose selected areas of the polysilicon gate and the drain and

source areas where connections (i.e. contact cuts) are to be made.

9. The whole chip then has metal (aluminum) deposited over its surface to a

thickness typically of I jim. This metal layer is then masked and etched to
form the required interconnection pattern.

It will be seen that the process revolves around the formation or deposition

and patterning of three layers, separated by silicon dioxide insulation. The layers

are diffusion within the substrate, polysilicon on oxide on the substrate, and metal

insulated again by oxide.

To form depletion mode devices it is only necessary to introduce a masked

ion implantation step between Steps 5 and 6 in Figure 1-7. Again, the thick oxide

acts as a mask and this process stage is also self-aligning.

Consideration of the processing steps will reveal that relatively few masks

are needed and the self-aligning aspects of the masking processes greatly ease

the problems of mask registration. In practice, some extra process steps are necessary,

including the overgiassing of the whole wafer, except where contacts to the outside
world are required. However, the process is basically straightforward to envisage

and circuit design eventually comes down to the business of delineating the masks
for each stage of the process.

CMOS fabrication
There are a number of approaches to CMOS fabrication, including the p-well,

the n-well, the twin-tub, and the silicon-on-insulator processes. In order to introduce

the reader to CMOS design we will be concerned mainly with well-based circuits.

The p-well process is widely used-in practice and the n-well process is also popular,

particularly as it was an easy retrofit to existing nMOS lines.

For the lambda-based rules set out later, we will assume a p-well process

CMOS Fabrication
CMOS or Complementary Metal Oxide Semiconductor is a combination of
NMOS and PMOS transistors. NMOS is an N-type Metal Oxide Semiconductor,
and PMOS is a P-type Metal Oxide Semiconductor. N-type is a type of
pentavalent impurities, and P-type is a type of trivalent impurities doped on
the semiconductor. The three terminals of the transistors are Gate (G),
Source (S), and Drain (D). The doping of p-type/n-type is applied on the D
and S terminals.

The CMOS transistors are used in various applications, such as amplifiers,

switching circuits, logic circuits, Integrated circuit chips,
microprocessors, etc. The importance of CMOS in semiconductor
technology is its low power dissipation and low operating currents. Its
manufacturing requires fewer steps as compared to the Field Effect
Transistors and Bipolar Junction transistors
  The p-well process

A brief overview of the fabrication steps may be obtained with reference to, noting that the basic
processing steps are of the same nature as those used

for nMOS.

In primitive terms, the structure consists of an n-type substrate in which p-

devices may be formed by suitable masking and diffusion and, in order to

accommodate n-type devices, a deep p-well is diffused into the n-type substrate

This diffusion must be carried out with special care since the p-well doping

concentration and depth will affect the threshold voltages as well as the breakdown

voltages of the n-transistors. To achieve low threshold voltages (0.6 to 1.0 V),

we need either deep well diffusion or high well resistivity. However, deep wells

require larger spacing between the n- and p-type transistors and wires because of

lateral diffusion and therefore a larger chip area.

The p-wells act as substrates for the n-devices within the parent n-substrate,

and, provided that voltage polarity restrictions are observed, the two areas are

electrically isolated. However, since there are now in effect two substrates, two

substrate connections ( V 0 and V5) are required

 CMOS p-well inverter showing Vand V substrate cQnnections

In all othe'r respects - masking, patterning, and diffusion - the process issimilar to nMOS
fabrication. In summary, typical processing steps are:

• Mask I - defines the areas in which the deep p-well diffusions are to take place.
• Mask 2 - defines 'the thinox regions, namely those areas where the thick

oxide is to be stripped and thin oxide grown to accommodate p- and n-transistors and diffusion
wires.

• Mask. 3 - used to pattern the polysilicon layer which is deposited after the thin oxide.

• Mask 4—A p-plus mask is now used (to be in effect 'Anded' with Mask 2) to define all areas
where p-aiffusion is to take place.

• Mask 5 - This is usually performed using the negative form of the p-plus mask and, with
Mask2, defines those areas where n-type diffusion is to take place.

• Mask 6 - Contact cuts are now defined.

• Mask 7 - The metal layer pattern is defined by this mask.

• Mask 8 - An overall passivation (overglass) layer is now applied and

Mask 8 is needed to define the openings for access to bonding pads.

 The N-well process

1. A mdkatcd earlier, although the p-well process is widely used, n-well fabrication
2. has also gained wide acceptance, initially as a retrofit to nMOS lines.
3. N-well CMOS circuits are also superior to p-well because of the lower substrate
4. bias effects on transistor threshold voltage and inherently lower parasitic
capacitances
5. associated with source and drain regions.
6. Typical n-well fabrication steps are illustrated in Figure 1-11. The first mask
7. defines the n-well regions. This is followed by a low dose phosphorus implant
8. driven in by a high temperature diffusion step to form the n-wells. The well
9. depth is optimized to ensure against p-substrate to p 4 diffusion breakdown
without
10. compromising the n-well to n4 mask separation. The next steps are to define the
11. devices and diffusion paths, grow field oxide, deposit and pattern the polysilicon,
12. carry out the diffusions, make contact cuts, and finally metallize as before.
13. It will be seen that an n 4 mask and its complement may be used to define the
14. n- and p-diffusion regions respectively. These same masks also include the VOD
15. and V3.5 contacts (respectively). It should be noted that, alternatively, we could
16. have used a p4 mask and its complement, since the n and p masks are generally
17. complementary.
 18. By way of illustration,an inverter circuit fabricated by the n-well process, and this
may be directly compared

Owing to differences in charge carrier mobilities, the n-well process creates

non-optimum p-channel characteristics. However, in many CMOS designs (such

as domino-logic and dynamic-logic structures), this is relatively unimportant since

they contain a preponderance of n-channel devices. Thus the n-channel transistors

are mainly those used to form logic elements, providing speed and high density

of elements. Latch-up problems can be considerably reduced by using a low-resistivity epitaxial p-type
substrate as the starting material, which can subsequently act asa very low resistance ground-plane to
collect substrate currents.However, a factor of the r-well process is that the performance of the
alreadypoorly performing p-transistor is even further degraded. Modern process lineshave come to grips
with these problems, andgood device performance may beachieved for both p-well and n-well
fabrication. -

The design rules which are presented for 1.2 ILm and 2 gm technologies in

this text are for OrbiPM n-well processes.

 The twin-tub process

1. A logical extension of the p-well and n-well approaches is the twin-tub fabrication
process.
2. Here we start with a substrate of high resistivity n-type material and then
3. create both n-well and p-well regions. Through this process it is possible to preserve
4. the performance of n-transistors without compromising the p-transistors. Doping
5. control is more readily achieved and some relaxation in manufacturing tolerances results.
6. This is particularly important as far as latch-up is concerned.
7. In general, the twin-tub process allows separate optimization of the tri- and p-'transistors.
8. The arrangement of an inverter is illustrated ,
9. Which may in turn be compared with others

twin-tub structure

Latch-Up Problem and Its Prevention

Latchup is the most common problem in the CMOS transistor. Mainly causes due to the
formation of BJTs (PNP and NPN) and can be prevented using Guard Rings.

First of all, this is the most important VLSI interview question. Most of the interview
guys prefer to ask this question to check the basics of the candidate regarding MOS and
its second-order effects.
You must also read these topics which I am listing below.

1. Non-ideal characteristics of MOSFET such as Velocity Saturation, Mobility

degradation, Channel length modulation (CLM), body effect, subthreshold conduction,
DIBL (Drain induced barrier lowering), BTBT (Band to band tunneling), GIDL (Gate
induced barrier lowering),
2. the Tunneling effect,
3. Latchup,
4. Stack effect,
5. Charge sharing effect,
6. Short channel effects, and Narrow channel effects.

Latchup:
Latchup is a condition in which the parasitic components such as PNP and
NPN transistors give rise to the establishment of low resistance
conducting path between VDD (Supply) and GND (ground).

The above circuit shows a CMOS Inverter circuit and the parasitic components.
In addition to PMOS and NMOS, the circuit is composed of an NPN transistor, a
PNP transistor, and two resistors connected between power and ground rails.

The NPN transistor is formed between the Grounded N diffusion source, P

substrate, and N-well. and The PNP transistor is formed between P-type drain,
N-well, and P substrate.
And the 2 resistors are due to resistance through the substrate of MOS,
resistance through the substrate, and well taps. The cross-coupled
transistors form a Bistable Silicon Controlled Rectifier (SCR) and ordinarily, both
BJTs are off.
Latchup Cause:
Latchup can be triggered when the transient currents flow through the substrate
during normal chip power-up.
Or When external voltage outside the normal operating range is applied.

Latchup effects:
If the substantial current flows into the substrate Vsub (Substrate voltage) will
rise, turning ON the NPN transistor. this pulls current through the Rwell resistor
bringing down Vwell and turning ON the PNP transistor.
The PNP transistor’s current intern rises Vsub, initiating the +ve
feedback loop between VDD and GND, which persists until the power supply
is turned off or the power wires melt.
Latchup prevention techniques:
1. Reducing Rsub (Substrate Resistance) by making High Substrate doping
level and Reducing Rwell (Well Resistance) by making low resistance
contact to (GND) that is place substrate and well taps close to each other.
2. Input-Output (I/O) pads are essentially susceptible to Latchup because
external voltages can ring below GND or above VDD, which causes forward
biasing the junction between Drain and Substrate or Drain and well and injecting
the current into the Substrate.

3. Guard rings should be used to collect the currents.

4. SOI (Silicon on Insulator) avoids Latchup entirely because they have no

parasitic bipolar structures.

5. The process with VDD less than 0.7volts is immune to Latchup because BJT
never has a large Base to Emitter Vbe to turn ON.

6. The n-type transistors or NMOS transistors must be clustered together near

the Ground and PMOS transistors must be clustered together near the Supply
Voltage VDD.

Each and every well must have at least one tap in it. and A tap must be placed
for every 5 to 10 transistors.
1. Guard ring:

Figure-2: Guard Ring

If Vout goes bellow the VSS and the diode between drain and p-
substrate of nMOS become forward bias, electrons from drain
start injecting from to substrate and collected by the body of
pMOS. This cause a current from in the opposite direction of
electron flow. which ultimately triggers the Qp transistor as
shown in the figure-1. Now to break this chain, two sets of n+
implant in n-well, p+ implant on p-substrate added in between
nMOS and nMOS as shown in the figure-2. These will collect the
electrons injected from the drain of nMOS and prevent the
current flow from the drain of nMOS to the body of pMOS. Which
stops triggering the Qp BJT.

Similarly in case of the Vout goes above the VDD and drain of
pMOS start injecting holes in n-well and goes and collected by the
body of nMOS. This lead to the trigger of Qn BJT. But by adding
the guard ring these holes will be collected by the guard ring and
stop the latch-up.

2. Oxide trench isolation:

In this technique, nMOS and pMOS have insolated using the

buried oxide and oxide trench. A horizontal buried oxide created
deep inside and vertical oxide trenches are created later and
connected both together to separate the n-well and p-substrate.
The oxide trenches are isolator in nature so oxide trench stops
the formation of the PNPN device. A cross-section of oxide
trench isolation is shown in the below figure

Crosssection of a trench isolation

Drain-Induced Barrier Lowering (DIBL) For long-channel devices, the source-channel potential
barrier is determined primarily by the voltage applied to the gate. Increasing the gate voltage
causes the barrier height to reduce, resulting in injection of electrons from the source into the
channel. At a particular gate voltage – the threshold voltage – the barrier has reduced sufficiently
to allow a significant amount of injection, and flow of current, to take place. In a short-channel
device, the drain junction is now quite close to the source junction. As a consequence, the
potential at the source-channel region is determined not only by the gate voltage, but also the
drain voltage. The drain voltage can cause a lowering of the barrier at the source end of the
channel, causing current to flow for a lower vale of gate voltage. This effect is called Drain-
Induced Barrier Lowering or DIBL (pronounced “dibble”). The magnitude of DIBL obviously
depends on the channel length L, but also on the doping NA. Higher doping’s would mean that
electric field from the drain is more effectively screened, resulting in lower DIBL. Another way
to interpret DIBL is that the potential lowering is due to merging of the edges of the depletion
regions emanating from the source and drain junctions. Higher doping’s reduce the depletion
widths, and consequently delay their merging, reducing the DIBL effect. Thus, increasing the
bulk doping is a good strategy to minimize DIBL.

Effect on threshold voltage

One consequence of DIBL is an apparent reduction of the threshold voltage. This is clear
physically,

because with DIBL present, a smaller bias at the gate (threshold voltage) is reduce the barrier

sufficiently to allow current to flow. since larger drain voltages result in increased barrier
lowering, the
threshold voltage keeps decreasing with increasing VDS, that is, VT is now a function of VDS,
which

was not the case for long channel devices.

Effect on Subthreshold Behaviour

The coupling of the drain field to the source-channel junction affects how current flows in the

sub threshold region for a short-channel device. As drain voltage increases, the barrier reduces
due to

DIBL, and a larger drain current flows. This behavior is very different from what is seen for the
long-

channel device, where the sub threshold current is independent of drain voltage.

Parameters affecting sub-threshold regime

Recalling the equation which describes the drain current in the sub threshold regime
Velocity Saturation

As the MOS device is scaled down, electric fields in the device become large. This creates a

significant problem. It is true that the voltages used have also scaled down from 5 V to about

1 V in an attempt to keep the field within limits, but with the corresponding channel lengths

decreasing from 5 μm to 70 nm, and gate oxide thickness from 100 nm to 1.5 nm, it is clear

that the electric fields, both horizontal and vertical, have increased significantly in short-

channel MOSFETs. There are several consequences of the high electric fields. One of the most

important is velocity saturation experienced by the carriers as they move along the channel in

the presence of a high lateral electric field.

It is well-known that the drift velocity of carriers in a semiconductor does not continue to

increase linearly with electric field at higher fields. On the contrary, the velocity, plotted as a

function of field, starts to level off, and finally saturates at a value vsat. For electrons and holes

in silicon, the value of vsat is about 1x107 cm/sec at room temperature. Several models have

been used for drift velocity v as a function of electric field E. One of the most common is
Hot Carrier Effects and Impact Ionization

As channel lengths reduce, the lateral electric field increases, if applied voltages remain the

same. This causes carriers flowing along the channel to gain energy and become “hot”. The hot

carriers can cause impact ionization, which produces extra hole electron pairs. This produces

extra drain current, and also a substrate current consisting of the ionization-generated holes

which flow towards the substrate, the most negative point in the transistor. The hot carriers

may also gain sufficient energy to surmount the potential barrier at the silicon-insulator

interface, and get injected into the insulator. These effects are shown schematically

Schematic figure showing effects of impact ionization (a) increase in drain current ΔID

(b )increase in substrate current Isub and (c) injection of hot carriers into the oxide.

The effects of hot carriers and impact ionization on MOSFET characteristics and

performance are discussed in the sections below.

1.4.1 Increase in Output Conductance

The electrons generated by impact ionization contribute to extra drain current. In saturation, as
the voltage VDS increases, and field in part of the MOSFET increases. This increased field

causes impact ionization, and results in increased drain current as well as substrate current

Hot Carrier Effects

Due to the high electric field in the channel, electrons, which constitute the drain current in n-

channel transistors, can get hot. If some of these electrons get sufficiently heated up – more

than the 3.1 eV barrier Фox between silicon and silicon dioxide conduction bands – and also

have their momentum directed (through an elastic collision) towards the interface, then these

electrons can get injected into the insulator.

Furthermore, some of the holes created by impact ionization may also get heated up and be

injected into insulator (though this process is more difficult for holes than for electrons, given

the larger 4.9 eV barrier for holes at the Si/SiO2 interface). The holes and electrons flowing

into the insulator cause several problems, including electron and hole trapping, interface state

generation, and generation of bulk and “border” traps in the insulator. These phenomena,
 UNIT 3: Layout Design Rules

Scaling

1. The only constant in VLSI is constant change

 2. Feature size shrinks by 30% every 2-3 years

3. Transistors become cheaper

4. Transistors become faster and lower power

5. Wires do not improve (and may get worse)

6. Scale factor S

7. Typically

8. Technology nodes

Dennard Scaling

1. Proposed by Dennard in 1974

2. Also known as constant field scaling

a. Electric fields remain the same as features scale

3. Scaling assumptions

a. All dimensions (x, y, z => W, L, tox)

b. Voltage (VDD)

4. Doping levels

Device Scaling

Parameter Sensitivity Dennard Scaling

L: Length 1/S
W: Width 1/S

tox: gate oxide thickness 1/S

VDD: supply voltage 1/S

Vt: threshold voltage 1/S

NA: substrate doping S

b W/(Ltox) S

Ion: ON current b(VDD-Vt)2 1/S

R: effective resistance VDD/Ion 1

C: gate capacitance WL/tox 1/S

t: gate delay RC 1/S

f: clock frequency 1/t S

E: switching energy / gate CVDD2 1/S3

P: switching power / gate Ef 1/S2

A: area per gate WL 1/S2

Switching power density P/A 1

Switching current density Ion/A S

1. Gate capacitance per micron is nearly independent of process

2. But ON resistance * micron improves with process

3. Gates get faster with scaling (good)

4. Dynamic power goes down with scaling (good)

5. Current density goes up with scaling (bad)

6. Gate capacitance is typically about 1 fF/mm

7. The typical FO4 inverter delay for a process of feature size f (in nm) is about 0.5f ps
 8. Estimate the ON resistance of a unit (4/2 l) transistor.

Real Scaling

1. tox scaling has slowed since 65 nm

a. Limited by gate tunneling current

b. Gates are only about 4 atomic layers thick!

c. High-k dielectrics have helped continued scaling of effective oxide thickness

2. VDD scaling has slowed since 65 nm

a. SRAM cell stability at low voltage is challenging

3. Dennard scaling predicts cost, speed, power all improve

a. Below 65 nm, some designers find they must choose just two of the three

Wire Scaling

1. Wire cross-section

a. w, s, t all scale

1. Wire length

a. Local / scaled interconnect

b. Global interconnect

i. Die size scaled by Dc » 1.1

Interconnect Scaling

Parameter Sensitivity Scale Factor

w: width 1/S

s: spacing 1/S

t: thickness 1/S

h: height 1/S

Dc: die size Dc

 Rw: wire resistance/unit length 1/wt S2

Cwf: fringing capacitance / unit length t/s 1

Cwp: parallel plate capacitance / unit length w/h 1

Cw: total wire capacitance / unit length Cwf + Cwp 1

twu: unrepeated RC delay / unit length RwCw S2

twr: repeated RC delay / unit length sqrt(RCRwCw) sqrt(S)

Crosstalk noise w/h 1

Ew: energy per bit / unit length CwVDD2 1/S2

Interconnect Delay

Parameter Sensitivity Local / Semiglobal Global

l: length 1/S Dc

Unrepeated wire RC delay l2twu 1 S2Dc2

Repeated wire delay ltwr sqrt(1/S) Dcsqrt(S)

Energy per bit lEw 1/S3 Dc/S2

1. Capacitance per micron is remaining constant

a. About 0.2 fF/mm

b. Roughly 1/5 of gate capacitance

2. Local wires are getting faster

a. Not quite tracking transistor improvement

b. But not a major problem

3. Global wires are getting slower

a. No longer possible to cross chip in one cycle

Scaling Implications

1. Improved Performance
 2. Improved Cost

3. Interconnect Woes

4. Power Woes

5. Productivity Challenges

6. Physical Limits

Scalable CMOS Design Rules

SCMOS Design Rules This document defines the official MOSIS scalable CMOS (SCMOS) layout rules.
It supersedes all previous revisions. In the SCMOS rules, circuit geometries are specified in the Mead and
Conway’s lambda based methodology [1]. The unit of measurement, lambda, can easily be scaled to
different fabrication processes as semiconductor technology advances. Each design has a technology-code
associated with the layout file. At the moment, three technology-codes are used to specify the basic
CMOS process. Each technology-code may have one or more associated options added for the purpose of
specifying either (a) special features for the target process or (b) the presence of novel devices in the
design. At the time of this revision, MOSIS is offering six CMOS processes from three different
foundries with feature sizes from 2.0 micron to 0.5 micron.

This document defines the official MOSIS scalable CMOS (SCMOS) layout rules. It

supersedes all previous revisions.

MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules,

which provide a nearly process- and metric-independent interface to many CMOS

fabrication processes available through MOSIS. The designer works in the abstract SCMOS

layers and metric unit ("lambda"). He then specifies which process and feature size he

wants the design to be fabricated in. MOSIS maps the SCMOS design onto that process,

generating the true logical layers and absolute dimensions required by the process

vendor. The designer can often submit exactly the same design, but to a different

fabrication process or feature size. MOSIS alone handles the new mapping.

By contrast, using a specific vendor's layers and design rules ("vendor rules") will yield a

design which is less likely to be directly portable to any other process or feature size.

Vendor rules usually need more logical layers than the SCMOS rules, even though both

fabricate onto exactly the same process. More layers means more design rules, a higher
learning curve for that one process, more interactions to worry about, more complex

design support required, and longer layout development times. Porting the design to a

new process will be burdensome.

SCMOS designers access process-specific features by using MOSIS-provided abstract

layers which implement those features. For example, a designer wishing to use secondpoly
would use the MOSIS-provided second-poly abstract layer, but must then submit to a

process providing for two polysilicon layers. In the same way, designers may access

multiple metals, or different types of analog structures such as capacitors and resistors,

without having to learn any new set of design rules for the more standard layers such as

metal-1. SCMOS is there for portability and simplicity. It is NOT there for fine-tuned

layout.

Vendor rules may be more appropriate when seeking maximal use of silicon area, more

direct control over analog circuit parameters, or for very large production runs, where the

added investment in development time and loss of design portability is clearly justified.

However the advantages of using SCMOS rules may far outweigh such concerns, and

should be considered.

CMOS Process Enhancements

In the Analog, Digital or RF CMOS integrated circuits along with transistors
other elements such as interconnects, resistors, capacitors are to be
integrated on chip. In order to achieve this, enhancements in CMOS process
technology is required. The main goals of adding CMOS enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.

(3) To provide routing of interconnects.

The enhancements in CMOS technology are :

(1) Multilevel metal layers.

(2) Multilevel poly layers.

Transistors :

To enhance the CMOS technology the bipolar transistors can be integrated

on chip in CMOS technology and this forms the BiCMOS technology. Here we
will discuss the processing requirements to make these devices on chip.

Figure below shows the cross-section of BiCMOS process in which NMOS and
npn transistor are fabricated on the same substrate.

The starting material is p substrate on which n type epitaxial layer is grown.

To form the NMOS transistor a p well is diffused in selected area. And
n+ diffusions form the source and drain contacts. The nepilar is diffused with
the p+ diffusion which forms the base for the npn transistor both the devices
i.e. NMOS and npn transistors are isolated by field oxide.

Interconnect :

The most important enhancement in CMOS processes is the additions of

signal and power supply routing layers. The advantage of this type of routing
is it improves power and clock distribution to the different modules inside the
chip. The interconnect layers involved in process are :

(1) Metal interconnect

(2) Polysilicon interconnect

(3) Local interconnect.

The second layer of metal interconnect (Metal 2) is required for digital

Integrated circuits. The connection between first metal layer (Metal 1) and
second metal layer (Metal 2) is established with the help of via. For high
speed chips third metal layer (Metal 3) is also required.

Polysilicon Interconnect layers are used in ICs because of its high melting
points as compare to Al. But the major problem with polysilicon interconnect
is it has high sheet resistance because of this for long distance interconnects
this provides significant delay

If silicide is used as a interconnect layer for connecting different cells then it

is called as local interconnect. The important advantage of local interconnect
is it allows direct connection
between polysilicon and diffusion regions due to this metal contacts are
eliminated which reduces the chip area.

Circuit Elements :

Resistor :

In order to create the on chip resistors n-well or polysilicon materials can be

used. The resistance of a material is a function of the materials resistivity
‘r’ and the dimensions of the material. Figure below shows the slab of
the material. The resistance between the two leads A and B is given as,

R = × = Rsheet

where Rsheet is the sheet resistance of material in W/square.

Capacitor :

Figure below shows the layout of capacitors used in integrated circuits.

As shown in Figure the capacitor can be formed by adding extra poly silicon
layer. In Figure (b) allows contacts to poly to be placed directly on top of the
thin oxide which is the isolation between two poly plates. The bottom plate of
the capacitor is made using poly 1 while the top plate where area determines
the capacitance is made using poly 2. A circular disc is used for poly 2. In
Figure (a) the contact to poly is lying over the field region. In this, sharp
corners are avoided in the layout.