“Do not wait to strike till the iron is

hot; but make it hot by striking.”

…. William Butler Yeats

2
CHAPTER

AC and DC Biasing-BJTs
and FET
Learning Objectives
After reading this chapter, you will know:
1. Operating Point
2. Bias Stabilization
3. Self-Bias, Emitter Bias
4. Stabilization Against Variations in ICO , VBE, Beta
5. Collector -Current Stability
6. Techniques Compensation
7. Biasing Techniques
8. Thermal Runaway, Stability

Introduction
The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of
the system. Too often it is assumed that the transistor is a magical device that can rise the level of the
applied ac input without the assistance of an external energy source. In actually, the improved output
ac power level is the result of a transfer of energy from the applied dc supplies. The analysis or
design of any electronic amplifier therefore, has two components; The dc portion and the ac portion.
Fortunately, the superposition theorem is applicable and the investigation of the dc conditions can be
totally separated from the ac response.
1. Depending on the biasing of the junction there are four modes in which a transistor can
operate,
JE JC
i) FB FB --------------- Saturation mode
ii) FB RB --------------- Active mode
iii) RB FB --------------- Inverted mode
iv) RB RB --------------- Cut off mode
2. For the BJT to be based in its saturation collector emitter junction voltage of about 0.2V.
3. A Transistor can be operated as a switch when operated only in saturation and cut off modes.
4. A Transistor can be used as an amplifier in active mode.
5. The transistor dissipates maximum power when it is operated in active mode.
6. Power dissipation in the transistor is given by PD = IC VCE
7. Dissipation in the transistor is minimum in saturation and cut off modes.
8. In active mode the collector current depends on base current and is independent of collector
emitter voltage (IC = βIB )
9. Inverted mode is not used since the current gain is very low.

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 AC and DC Biasing-BJTs and FET

For the BJT to be biased in its linear or active operating region, the following must be true:
 The base- emitter junction must be forward-biased with a resulting forward bias voltage of
about 0.6 to 0.7 V
 The base – collector junction must be reverse - biased, with the reverse – bias voltage being
any value within the maximum limits of the device.

Operating Point
The term biasing appearing in the title of this chapter is an all inclusive term for the application of dc
voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc
current and voltage establish an operating point on the characteristics that define the region that will
be employed for amplification of the applied signal. Since the operating point is a fixed point on the
characteristics, It is also called quiescent point (abbreviated Q-point). By definition, quiescent means
quiet, still, inactive. The following figure shows a general output device characteristics with four
operating points. The biasing circuit can be designed to set the device operation at Q (VC, IC) within
the active region. The maximum ratings are indicated on the characteristics by a horizontal line for
the maximum collector current IC max and a vertical line at the maximum collector to emitter
voltage VCE max . The maximum power constraint is defined by the curvePc(max) . At the lower end of
the scales are the cut off region defined by IB ≤ 0 μA, and the saturation region, defined by
VCE ≤ VCE sat .
IC (mA) 80 μA

70 μA
ICmax 25
60 μA

20 50 μA

PCmax 40 μA

15 30 μA
Saturation
B
10 20 μA
D

10 μA
5 C
IB = 0 μA
A
0 5 10 15 20 VCE (V)
VCEsat
Cutoff
VCEmax
Various Operating Points Within the Limits of Operation of a Transistor

DC Analysis
The DC analysis of transistor circuits involves solving of all the currents and voltages in the circuits.
The most important DC parameters to solve are IC and VCE. This is defined ‘Q - point’ of the transistor.

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 AC and DC Biasing-BJTs and FET

RL
C
Rb C

R′L
~ VAC

For DC Analysis
 Open circuit all the capacitance in the circuit
 Short circuit all the AC voltage source
Above circuit become
VCC

Ic RL
− −
Rb
VCE

R′L
V0

+
+
VCC = IC R L + VCE
VCC −1
⇒ Ic = + ( ) VCE
RL RL
∴ y = mx + c
−1
Slope = m =
RL
IC

DC Load Line

IB3
IB2

IB1

VCE
For this circuit – Q point can be anywhere on this DC load line
Note: Right now we can’t figure out the location of Q-point because base emitter junction is not biased
properly.
For below circuit

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 AC and DC Biasing-BJTs and FET

VCC VCC

RC
C R C IC
Rb Vo IC
Rb

C +
Ib
VCE
+
VAC
VBE −
−

𝐃𝐂 − 𝐄𝐪𝐮𝐢𝐯𝐚𝐥𝐞𝐧𝐭 𝐂𝐢𝐫𝐜𝐮𝐢𝐭
VCC VCE
VCC = IC R C + VCE ⇒ IC = −
RC RC
VCC − VBE
VCC = IB R b + VBE = IB =
Rb
For active mode VBE ≅ 0.7 V (for forward bias PN junction)
VC − 0.7
IB =
Rb
Now Ic = βIb ⇒ Ib = IC /β
IC VCC − 0.7 1 VCC β
= ⇒ IC = (− ) 0.7β + … … … (1)
β Rb Rb Rb
1 1
IC = (− ) VCE + VCC … … … (2)
RC Rc
Using equation (1) and 2 we can figure out the value of IC and VCE , (IC , VCE ) is the Q-point of the circuit
Example: R b = 100 kΩ, R C = 500 Ω, VCC = 5 V, β = 100
−0.7 × 100 5 × 100
IC = + = (5 − 0.7)mA
100 100
IC = 4.3 mA
VCE = −4.3 × 10−3 × 500 + 5 = 2.85 V
Q point (IC , VCE ) ≡ 4.3 mA, 2.85 V
Note: In the similar way we can calculate the Q-point of any circuit
IC

DC Load Line
(10 mA) VCC IB
RL
IB

(4.3 mA, 2.85 V)

Q IB

IB

VCC
VCE
(5 V)

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 AC and DC Biasing-BJTs and FET

Note:
 Regard less of the behavior of the transistor, the collector current IC & the collector emitter
voltage VCE must always lie on the DC load line.
 Quiescent amplifier is one that has no ac signal applied & therefore has constant dc values of
IC & VCE
 The interaction of the dc bias value of IB with the dc load line determines the Q point.
 When a circuit is designed to have a centered Q point, the amplifier is said to be midpoint biased.

AC Analysis
1. When an ac signal is applied to the base of the transistor, IC and VCE will both way around their
Q-point values.
a. Since the quiescente point is only one and since the IC and VCE values of the quiescente point
are critical. We usually use the pointer “Q”. So, for the quiescente IC current we use the
symbol ICQ .
b. The AC collector current is given by the following equation:
IC = ΔIC = IC − ICQ
c. And the AC collector voltage:
VCE = ΔVCE = VCE − VCEQ

2. When the Q-point centered, IC and VCE can both make the maximum possible transitions above
and below their initial dc values
IC
IC(sat)

Q
1
I
2 C(sat)
VCE
0

0 1 VCC
V
2 CC

3. When the Q-point is above the center on the load line, the input signal may cause the transistor
to saturate. When this happens, part of the output signal will be clipped off.

4. When the Q-point is below midpoint on the load line, the input signal may cause the transistor
to cutoff. This can also cause portion of the signal to be clipped.

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 AC and DC Biasing-BJTs and FET

Clipped Off IC
IC

ICQ VCEQ VCEQ + ICQ R C

0
VCE 0 VCE
ICQ R C
Clipped Off
VCFQ
(a) Limited by Saturation (b) Limited by Cutoff
IC

0
VCE

Clipped Off
Clipped Off
(c) Centered Q − Point
So for circuit
VCC
Vo
RC
Rb RC
Vo

⇒ AC Equivalent
~ VAC ~ VAC Rb

For AC analysis → Short circuit all the capacitance

→ Ground all DC voltage sources
So,

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 AC and DC Biasing-BJTs and FET

IC
(ICQ + VCEQ ⁄R′C ) Note: Here R′C = R C ||R L

VCE
RC
Q
DC Load Line

VCC

VCE
AC Load Line VCEQ + ICQ R′C

Note: This AC load line is the load line of the circuit at infinite frequency and that’s the reason we are
replacing capacitors with short circuits & inductors with open circuits. Practically, the slope of AC
load line depends on the frequency of the applied signal. So there may be many AC load line
(at frequency = 0) to a limiting AC load line (commonly known as AC load line) at infinite frequency
& all having a common intersection at the dc-operating point (Q-point)

Bias Stabilization
The operating point shifts with changes in temperature T because the transistor parameters
(β, ICO and VBE ) are function of T. The network design must provide a degree of temperature stability
so that temperature changes result in minimum changes of the operating point. This in maintenance
the operating point can be specified by a stability factor, S, which indicates the degree of change in
operating point due to temperature variation.
Thus the stability of a system is a measure of the sensitivity of a network to variations in its
parameters. The collector current is sensitive for each of the following parameters:
β: Increases with temperature.
VBE: The Base to emitter voltageVBE, decreases about 2.5 mV per degree Celsius (℃) increase in
temperature.
ICO (reverse saturation current): doubles in value for every 10℃ increase in temperature.
Any or all of these factors can cause the bias point to drift from the designed point of operation.
IC = f (ICO, VBE, β)
∂IC ∂IC ∂IC
∆IC = ∆ICO + ∆VBE + ∆β
∂ICO ∂VBE ∂β
∆IC = S∆ICO + S ′ VBE + S ′′ ∆β
∂IC
S, S ′ , S ′′ are stability factors where, S = |
∂ICO V ,β Constant
BE

′
∂IC
S = |
∂VBE I
CO ,β Constant
∂IC
S ′′ = |
∂β I
CO ,VBE Constant
Networks that are quite stable and relatively insensitive to temperature variations have low
stability factor. The higher the stability factor, the more sensitive is the network to variations in that
parameter.
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 AC and DC Biasing-BJTs and FET

Fixed Bias Circuit

Vcc

IC R c Cb 2
Rb
Cb1 +
IB
+
+
VBE − RL Output V
Signal Signal
o
Vi Input
IE

− −

The Fixed–Bias Circuit

The fixed bias circuit provides a relatively straight forward and simple approach of transistor dc bias
biasing.

Base-Emitter Loop (DC-Analysis): Consider the base emitter circuit loop, writing Kirchhoff’s voltage
equation in the clockwise direction for the loop, we obtain
+VCC – IBRB – VBE = 0
VCC − VBE
∴ IB =
RB
Since the supply voltage VCC and the base-emitter voltage VBE are constants, the selection of R B , sets
the levels of base current for the operating point.

Collector – Emitter Loop:

IC = βIB
Since the base current is controlled by the level of RB and IC is related to IB by a constant β the
magnitude of IC is not a function of the resistance RC. However, the level of RC will determine the
magnitude of VCE. Applying KVL in the clockwise direction around the closed loop
VCE + IC RC – VCC = 0 and VCE = VCC – IC RC
But VCE = VC – VE = VC and VBE = VB – VE = VB , Since VE = 0 V

Transistor Saturation: For a transistor operating in the saturation region, the current is a maximum
value for the particular design. The highest saturation level is defined by the maximum collector
current. To know the approximate maximum collector current for a design, simply insert a
short-circuit equivalent between collector and emitter of the transistor and calculate the resulting
collector current. For the fixed bias, the short circuit has been applied, causing the voltage across R C
Vcc
to be the applied voltage VCC. The resulting saturation current is, IC sat =
RC
Here IB is fixed because the biasing voltage VCC and base resistance RB are constant. As the
temperature increases, ICO increases, hence IC increases. As IC increases, junction temperature
increases, so again ICO increases. This cumulative process leads to thermal run away because here IB
is constant.
IC = βIB + (1 + β) ICO
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 AC and DC Biasing-BJTs and FET

∂IC
Stability factor, S = |
∂ICO β,V constant
BE
∂IC ∂IB ∂ICO
=β + (β + 1)
∂IC ∂IC ∂IC
∂IB 1
1=β + (β + 1)
∂IC S
β+1
So, S = ∂I
1−β B
∂IC
∂IB
Since IB is constant, =0
∂IC
1+β
∴S= ∂I
=1+ β
1 − β ∂IB
C
From the above equation we can conclude that for a small change occurring in I CO makes a large
change in IC. So, this circuit gives less stability and not commonly use.

Fixed Bias Circuit with Emitter Resistor

Base Emitter Loop:
Writing Kirchhoff’s voltage law in the clockwise direction,
+VCC – IBRB – VBE − IERE = 0
But IE = ( 1 + β ) IB
∴ VCC – IBRB – VBE – (β + 1) IBRE = 0
VCC − VBE
∴ IB =
R B + (β + 1)R E
β(VCC − VBE )
IC = β IB =
R B + (β + 1)R E
VCC

IC

RB RC

VO
C2
IB
Vi

C1
IE

RE

BJT Bias Circuit with Emitter Resistor

Since β > > 1 and VBE is very small,

VCC
IC ≈ R
RE + B
β
VCC − VBE − IC R E ∂IB −R E
IB = ⇒ =
RB ∂IC RB
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 AC and DC Biasing-BJTs and FET

1+β
Stability factor S = ∂IB
1−β ∂IC
1+β
∴S = ∂I
1 − β ∂IB
C
An increase in IC due to an increase in ICO will cause the voltage VE = IE RE ≅ICRE to increase. The result
is a drop in the level of IB. A drop in IB will have the effect of reducing the level of IC through transistor
action and thereby offset the tendency of IC to increase due to an increase in temperature. In total,
therefore, the configuration is such that there is a reaction to an increase in IC that will tend to oppose
the change in bias conditions. To decrease the stability factor we have to increase RE value, but this
 Decrease the gain of the amplifier
 Increase voltage drop across Re
The first draw back can be avoided by connecting a by pass capacitor across R E but the second one
cannot be avoided. Hence this circuit is not used.

Collector to Base Biasing Circuit

Base – Emitter Loop:
Writing Kirchoff’s voltage law in the clockwise direction
+VCC

RC

RB C

IB
IC IC

VCC – (IB + IC) RC – IBRB – VBE = 0

VCC – IB(RC + RB) – ICRC – VBE = 0
VCC − IC R C − VBE
IB =
RB + RC
VCE = VCC – ICRC
1+β ∂IB −R C
Stabilizing factor S = ∂IB
; =
1 − β ∂I ∂IC RB + RC
C
1+β
S = βRC
≅ 1 for R C >> R B
1+R
B +RC
R B is the feedback resistor and eliminating the feedback is difficult. So this method is rarely used.
This feedback configuration operates in much the same way as the fixed-bias with emitter resistor
configuration when it comes to levels of stability. If IC increase due to an increase in temperature, the
level of voltage across RC will increase and the level of IB will decrease. The result is a stabilizing effect
as described for the fixed-bias with emitter resistor configuration.

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 AC and DC Biasing-BJTs and FET

Self Bias Circuit or Emitter Bias

This Voltage divider biasing circuit is the most widely used circuit.
VCC

IC RC
R1
C
B
+
IB

Vi vi R2 IE RE

− N

Voltage Divider Biasing with By- Pass Capacitor

Applying Thevenin’s theorem at the input side,

IC RC

RB + +
B
VCE VCC
− −
+ IB
Vth
− IB + IC RE

R2 R1 R 2
Vth = VCC ; RB =
R1 + R 2 R1 + R 2
Applying KVL to input, – Vth + IB R B + VBE + IE R E = 0. . . . . . . . . . . . . . . (1)
Vth = IB R B + VBE + R E (IC + IB )
Vth − VBE − R E IC
IB = … … … … … (2)
RB + RE
IC = β IB
Applying KVL to output
VCC − IC R C − VCE − (IC + IB )R E = 0
VCE = Vcc − IB R E − IC (R C + R E )
βVth
Neglecting VBE , IC ≅ (from equation (1))
R B + (1 + β)R E
Vth
Since β >> 1, IC R
B
β
+ RE
1+β
Stability factor S = ∂IB
1−β
∂IC
∂IB −R E
= (from equation (2))
∂IC R B + R E
1+β
S = βRE
≅ 1, for R B << R E
1+
RB +RE

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 AC and DC Biasing-BJTs and FET

Negative feedback can be eliminated by connecting a by pass capacitor across RE. The most stable of
the configurations is the voltage divider bias network. If the condition β RE > > 10 R2 is satisfied, the
voltage VB will remain fairly constant for changing levels of IC. If IC tends to increase, say because ICO
has risen as a result of an elevated temperature, the current in R E increases. As a consequence of the
increase in voltage drop across R E , the base current is decreased. Hence IC will increase less than it
would have increased there been no self-biasing resistor R E .

Example: The transistor of below circuit is a Si device with a base current of 40 µA and ICBO = 0. If
VBB = 6 V, R E = 1k Ω, and β = 80, find (a) IE (b) R B (c) If Vcc = 15 V and R C = 3 kΩ, find
VCE ?

C RC
iC
RB
B
+
iB VCC
−
iE
+
VBB E
− RE

Solution: IE = (1 + β)IB = 3.24 mA

(a) Applying KVL around the base-emitter loop gives
VBB − VBE − IE R E
RB =
IB
6 − 0.7 − 3.24 mA × 1kΩ)
= = 51.5 kΩ
40 × 10−6
(b) IC = βIB = (80)(40 × 10−6 ) = 3.2 mA
Then, by applying KVL around the collector circuit,
VCE = Vcc − IE R E − IC R C
= 15 – 3.24 × 1 – (3.2) (3) = 2.16 V

Example: The Si Darlington transistor pair of below circuit has negligible leakage current and
β1 = β2 = 50. Let Vcc = 12 V R E = 1 kΩ, and R 2 → ∞ . (a) Find the value of R1 needed to
bias the circuit so that VCE2 = 6V. (b) with R1 as found in part a, find VCE1 .
+Vcc
R1

I R1
T1

T2
IB 2
R2
RE
I R2

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 AC and DC Biasing-BJTs and FET

Solution: Since R 2 → ∞, IR2 = 0 and IB1 = IR1

By KVL,
VCC − VCE2 12 − 6
I E2 = = = 6 mA
RE 1 × 103
I E2
I B 2 = I E1 =
β2 + 1
I E1 I E2 6 × 10−3
And IR1 = IB1 = = = = 2.31 µA
β1 + 1 (β1 + 1)(β2 + 1) (50 + 1)(50 + 1)
By KVL (around a path that includes R1 , both transistors, and R E ) and Ohm’s law,
VR VCC − VBE1 − VBE2 − IE2 R E
R1 = 1 =
IR1 IR1
12 − 0.7 − 0.7 − (6 × 10−3 )(1 × 103 )
= = 1.99 MΩ
2.31 × 10−6
Applying KVL around a path including both transistors and R E , we have
VCE1 = VCC − VBE2 − IE2 R E = 12 − 0.7 − (6 × 10−3 )(1 × 103 ) = 5.3 V

Example: For the given circuit as shown in below circuit find R1 and R 2 and the range of R L for the
transistor (Q1 ) to remain in the active region. Assume β = 100 for both transistors.
Zener voltage VZ = 4 V
Take IL = 2 mA, IZ = 5 mA
VEB1 = 0.7V = VEB2
+12 V

Q2 IE
R2

IZ
Q1
+
IB
VR1 R1 RL
− iB2 IL

Solution: IE = IB + IL
IL = IC = βIB
IL
Or IB = = 0.02 mA
β
IE = (2 + 0.02) mA = 2.02 mA
For Q 2 : KVL
12 = VEB2 + VZ + VR1
or VR1 = 12 − VEB2 − VZ = 12 − 0.7 − 4 = 7.3V
Hence,
VR1
R1 = = 1.45 kΩ
IZ + IB
VR2 = Voltage drop across R 2

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 AC and DC Biasing-BJTs and FET

= VEB2 + VZ − VEB1 = 4 V
4
R2 = = 1.98 kΩ
2.02
Voltage drop across Base-to-collector of Q1 (from KVL)
VBC = 12 − VR2 − VEB1 − IL R L
= 12−4 − 0.7 − IL R L = 7.3−2R L
For Q1 to be in active Region VBC should be + ve means.
7.3 ≥ 2R L
or 2R L ≤ 7.3
or R L ≤ 3.65 kΩ
Hence
0 ≤ R L ≤ 3.65 kΩ

Example: Temperature variations can shift the quiescent point by affecting leakage current and
base-to-emitter voltage. In the circuit of below circuit, VBB = 6V, R B = 50 kΩ, R E = 1 kΩ
R C = 3 kΩ, β = 75, VCC = 15 V, and the transistor is a Si device. Initially, ICBO = 0.5 µA
and VBEQ = 0.7 V, but the temperature of the device increases by 20℃. Find the exact
change in ICQ
+VCC
RC
ICQ

ICBO
IBQ

RB IEQ
+
VBB RE
CE
−

Solution: Let the subscript 1 denote quantities at the original temperature T1 , and 2 denote
quantities at T1 + 20℃ = T2
VBB − VBE1 + ICBO1 (R B + R E )
IC1 = RB
β
+ RE
6 − 0.7 + (0.5 × 10−6 )(51 × 103 )
=
(50 × 103 /75) + 1 × 103
= 3.1953 mA
The leakage current doubles per 10℃,
ICBO2 = ICBO1 2∆T/10
= 0.5 × 10−6 220/10 = 2 µA
VBE decreases 2mv per ℃,
∆VBE = −2 × 10−3 ∆T
= (−2 × 10−3 ) (20) = − 0.04 V

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 AC and DC Biasing-BJTs and FET

So, VBE2 = VBE1 + ∆VBE

= 0.7 − 0.04 = 0.66 V
VBB − VBE2 + ICBO2 (R B + R E )
IC2 = RB
β
+ RE
6 − 0.66 + (2 × 10−6 )(51 × 103 )
= = 3.2652 mA
(50 × 103 /75) + 1 × 103
Thus,
∆IC = IC2 − IC1 = 3.2652 − 3.1953 = 0.0699 mA

Compensation Techniques
The compensation technique is used only to compensate the temperature parameters and not to fix
the operating point in active region. The operating point is fixed by stabilization technique by using
biasing resistors. So, the compensation technique is applicable only after the stabilization. With
compensation technique we can compensate temperature parameter exactly.
There are four types of compensation techniques available:
1. Diode compensation for VBE
2. Diode compensation for ICO
3. Thermistor compensation
4. Sensistor compensation

Diode Compensation for 𝐕𝐁𝐄

VCC
Rc

Vo
R th
+
IB VBE
−
IE RE
+
Vth Rd
−
−
−
Vo D D VDD
+ +

Stabilization by Means of Self – Bias and Diode-Compensation Techniques

The variation in VBE can be cancelled by connecting the diode in series with emitter such that the
voltage across diode is in opposite direction to VBE. Here the diode and transistor are made with
same material to get the same temperature effect in both the devices. The diode is kept biased in
forward direction by the source VDD and resistance R d . Writing KVL around base circuit,

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 AC and DC Biasing-BJTs and FET

Vth – IB R th – VBE – IE R E + Vo = 0
Since Vo = VBE
Vth – R th IB – R E (IB + βIB ) = 0
VBE = Vo because any change in VBE due to temperature, the same change occurs in Vo . So, the collector
current is independent of VBE

Diode Compensation for 𝐈𝐂𝐎

If the diode and transistor are made of same material then the reverse saturation current I 0 of the
diode will increase with temperature at the same rate as the transistor reverse saturation current ICO
VCC

RC
Ii R1 IC

IB

Io D VBE

Diode Compensation for a Transistor

IC = β IB + (1 + β )ICO
IB = Ii – Io
∴ IC = β (Ii – Io ) + (1 +β) ICO
Since β > > 1
IC = β (Ii – Io ) + βICO, IC = β Ii − β(Io – ICO), IC = β Ii Since Io = ICO

Thermistor Compensation
Thermistor is a temperature sensitive device having a negative temperature coefficient, (i.e.,) its
resistance decreases with increase in temperature.
−VCC

IC RC
R1
RT
IB
Vi

−
R2 −
+ Re
+

Thermistor Compensation of the Increase in 𝐈𝐂 with T

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 AC and DC Biasing-BJTs and FET

As T rises, R T decreases, and the current fed through R T into R e increases. So drop across R e
increases, which causes decrease in IB and it compensate the increase in IC due to T.
Thermistors are used to minimize the increase in IC due to change in temperature.

Sensistor Compensation
Sensistor is a heavily doped semiconductor device having positive temperature coefficient, (i.e.,) its
resistance increase with temperature. As T rises, R T increases and effective emitter resistor increases
which increases VE and reduces base current.
−VCC

Rc
R1

Vi IB

−
R2 −
Re RT
+
+

Thermal Stability – Thermal Runaway

Thermal stability is the condition to avoid the thermal runaway. The increase in IC due to increase in
temperature gives more power dissipation in the collector junction. Due to the power dissipation in
the collector junction again junction temperature increases. So, IC again increases. This cumulative
process gives more heat at collector junction and spoils the transistor. This process is called
“Thermal Runaway”.

Condition for Thermal Stability – Thermal Resistance

The steady state temperature rise at collector junction is proportional to power dissipation at the
junction, (Tj – TA ) ∝ PD
Where,
Tj - Junction temperature
TA - Ambient temperature
PD - Power dissipated at collector junction
Tj − TA = θ PD
Where, θ is thermal resistance °C/Watt
To get the change in power dissipation with respect to junction temperature, partially differentiate
with respect to Tj ,
∂PD ∂PD 1
1– 0 =θ ⇒ =
∂Tj ∂Tj θ
Condition for thermal stability is, the rate at which heat is generated at collector junction should be
less than the rate at which heat dissipated,

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 AC and DC Biasing-BJTs and FET

∂PC ∂PD ∂PC 1

(i. e. , ) < ⇒ <
∂Tj ∂Tj ∂Tj θ
This is the condition to avoid thermal runaway. This can be written as,
∂PC ∂PC ∂IC ∂IC0 1
= ( )( )( )<
∂Tj ∂IC ∂IC0 ∂Tj θ

Stability Factor 7 % per oC = 0.07 ICO

VCC
If transistor is biased in such a way that VCE < 2
, thermal runaway will not occur.

FET Biasing: For the field-effect transistor the relationship between input and output quantities is
non-linear due to the squared term in Shockley’s equation. This non-linear relationship between ID
and VGS can complicate the mathematical approach to the dc analysis of FET configuration. A
graphical approach may limit solutions to tenth’s place accuracy but it is a quicker method for most
FET amplifiers.
Another distinct difference between the analysis of BJT and FET transistors is that the input
controlling variable for a BJT transistor is a current level, while for the FET a voltage is the controlling
variable. In both cases, however, the controlled variable on the output side is a current level that also
defines the important voltage levels of the output circuit. The general relationships that can be
applied to the dc analysis of all FET amplifiers are
IG ≅ 0A and ID = IS
For JFETs and depletion-type MOSFETs shockley's equation is applied to relate the input and output
quantities:
VGS 2
ID = IDSS [1 − ]
VP
For enhancement-type MOSFETs the following equation is applicable:
ID = K(VGS − VT )2

JFETs and Depletion Types of MOSFETS

Fixed Bias Configuration: The simplest of biasing arrangements for the n-channel JFET appears in the
following figures
VDD
VDD
ID

RD RD

D D+
V
G G
V C2 VDS
C1 +
S
RG VGS − S
−
− VGG
VGG +
+

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 AC and DC Biasing-BJTs and FET

The configuration includes the ac levels Vi and Vo and the coupling capacitors (C1 and C2). The
coupling capacitors are "open circuits" for the dc analysis and low impedances for the ac analysis. The
resistor Rc1 is present to ensure that Vi appears at the input to the- JFET amplifier for the ac analysis.
For the dc analysis
IG = 0A
and VRG = IG R G = (0 A)R G = 0 V
Applying KVL in the clockwise direction of the indicated loop will result in
−VGG − VGS = 0
VGS = −VGG
Since VGG is a fixed dc supply the voltage VGS is fixed in magnitude, resulting in the notation
“Fixed-Bias Configuration". The resulting level of drain current ID is now controlled by shockley’s
equation
VGS 2
ID = IDSS [1 − ]
VP
The Drain-to-Source voltage of the output section can be determined by applying Kirchoff’s voltage
law as follow:
+VDS + ID R D − VDD = 0
And VDS = VDD − ID R D
For the configuration of the given circuit, Vs = 0 V
Using double subscript notation:
VDS = VD − VS
VD = VDS + VS = VDS + 0 V ⇒ VD = VDS
In addition, VGS = VG − VS
VG = VGS + VS = VGS + 0 V
⇒ VG = VGS
Since the configuration requires two dc supplies, its use is limited.

Self Bias Configuration

The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-source
voltage is now determined by the voltage across a resistor R S introduced in the source leg of the
configuration.
VDD
VDD
ID
ID
RD
RD
D
D
Vo
G G
Vi C2
+ +
C1 VGS − VGS
S − S
RG
+
Rs KVL RVS RS
−
IS = ID

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 AC and DC Biasing-BJTs and FET

For the dc analysis the capacitors can again be replaced by “open circuits” and the resistor R G
replaced by a short circuit equivalent since IG = 0 A
The current through R S is the source IS , but IS = ID and VRS = ID R S
For the indicated closed loop,
−VGS − VRS = 0; i. e. , VGS = −VRS
or VGS = −ID R S
Note: In this case that VGS is a function of the output current ID and not fixed in magnitude as occurred
for the fixed-bias configuration.
VGS 2 ID R S 2
ID = IDSS [1 − ] = IDS [1 + ]
VP VP
The quadratic equation can be solved for the appropriate solution for ID
Applying Kirchoff s voltage law to the output circuit,
VRS + VDS + VRD − VDD = 0
⇒ VDS = VDD − VRS − VRD
VDS = VDD − IS R s − ID R D
but ID = IS
And VDS = VDD − ID (R S + R D )
In addition:VS = ID R S
VG = 0 V
And VD = VDS + VS = VDD − VRD

Voltage - Divider Biasing

The voltage divider bias arrangement applied to BJT transistor amplifiers is also applied to FET
amplifiers. The base construction is exactly the same, but the dc analysis of each is quite different.
IG = 0 A for FET amplifier, but the magnitude of IB for common-emitter amplifiers can affect the dc
levels of current and voltage in both the input and output circuits. IB provided the link between input
and output circuits for the BJT voltage-divider configuration while VGS will do the same for the FET
configuration.
VDD VDD VDD

R1 RD RD
R1
Vo ID
IG = 0 A
C2
Vi +
C1
− IS
C3
+
+ Vs Rs
R2 Rs
R 2R 2 VG −
−

All the capacitors, including the by pass capacitor CS, have been replaced by an "open circuit"
equivalent. In addition, the source VDD was separated into two equivalent sources to permit a further
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 AC and DC Biasing-BJTs and FET

separation of the input and output regions of the network. Since IG = 0A, Kirchoff’s current law
requires that IR1 = IR2 using voltage divider rule:
R 2 VDD
VG =
R1 + R 2
Applying KVL in the clockwise direction to the indicated loop
VG − VGS − VRS = 0
VGS = VG − VRS
⇒ VGS = VG − ID R S
Applying graphical analysis,
VG
VGS = VG |ID = 0 mA , ID = |
RS V = 0 V
GS
VGS = VG − ID R s
∴[ ]
0 = VG − ID R s

The two points defined above, permit the drawing of a straight line to represent the equation. The
intersection of the straight line with the transfer curve in the region to the left of the vertical axis will
define the operating point and the corresponding levels of ID and VGS.
Increasing value of R s result in lower quiescent value of ID and more negative values of VGS .
Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis can be
performed in the usual manner. That is,
VDS = VDD − ID (R D + R S )
VD = VDD − ID R D
VS = ID R S
VDD
IR1 = IR2 =
R1 + R 2
The similarities in appearance between the transfer curves of JFETs the depletion type MOSFETs
permit a similar analysis of each in the dc domain. The primary difference between the two in the fact
that depletion type MOSFETs permit operating points with positive values of VGS and levels of ID that
exceed IDSS. In fact, for all the configurations discussed thus far, the analysis is the same if the JFET is
replaced by a depletion-type MOSFET.

Enhancement Type MOSFETS

The transfer characteristics of the enhancement type MOSFET are quite different from those
encountered for the JFET and depletion type MOSFETs resulting in a graphical solution quite different
from the preceding sections. For the n-channel enhancement-type MOSFET, the drain current is zero
for levels of gate-to-source voltage less than the threshold level VGS(th)- For levels of VGS greater than
VGS(th), the drain current is defined by ID = K( VGS - VGS(th))2 where
ID(on)
K= 2
(VGS(on) − VGS(th) )

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 AC and DC Biasing-BJTs and FET

Feed Back Biasing Arrangement

VDD VDD
ID
RD
RD
VD = VO

D D
RG
+
G G
VDS
Vi
+
VGS
S − S

The resistor R G brings a suitably large voltage to the gate to drive the MOSFET ‘ON’ IG = 0 mA and
VRG = 0 V for the dc equivalent network
A direct connection now exists between drain and gate, resulting in VD = VG and VDS = VGS
For the output circuit, VGS = VDD − ID R D
Since the above equation is that of a straight line, the points
VDD
VGS = VDD | and ID = |
ID =0mA RD V
GS = 0 mA

Determine the two points that will define the plot on the graph.

ID
VDD
RD

IDQ Q − Point

0 VGSQ VDD VGS

Determining the Q-Point for the Network

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 AC and DC Biasing-BJTs and FET

Voltage Divider Biasing Arrangement

VDD

R1 RD

D
IG = 0 A

G
+ − S
VGS
R2 RS

The fact that IG = 0 mA results in the following equation for VGG as derived from an application of the
voltage divider rule
R 2 VDD
VG =
R1 + R 2
Applying KVL around the indicated loop
+VG − VGS − VRS = 0
And VGS = VG − VRS
or VGS = VG − ID R S
For the output section
VRS + VDS + VRD − VDD = 0
And VDS = VDD − VRS − VRD
or VDS = VDD − ID (R S + R D )

Since the characteristics are a plot of ID versus VGS and the above equation relates the same two
variables, the two curves can be plotted on the same graph and a solution determined at their
intersection. Once IDQ and VGSQ are known, all the remaining quantities of the network such as VDS , VD
and VS can be determined.

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 AC and DC Biasing-BJTs and FET

Example: Circuit shows a power amplifier using a p-n-p germanium transistor with β = 100 and
ICO = −5 mA. The quiescent collector current is IC = −1 A. Find (a) the value of resistor
R b; (b) the largest value of θ that can result in a thermally stable circuit. Assume that the
effect of ICO dominates.
−VCC = −40 V

10 Ω RL
Rb
IC

IB
Vi

Re = 5 Ω C

Power Amplifier with a Transformer – Coupled Load

Solution:
a. The collector current is given by
IC = βIB + (1 + β)ICO ≈ β(IB + ICO )
And
1 − 5 × 10−3 × 100
IB = − A = −5 mA
100
If we neglect VEB, we have
5 × 10−3 R b = 40 − 5 or R b = 7,000 Ω
1
b. Since |VCE | = 40 − 15 = 25 > 2 |VCC | = 20 V, of the circuit is not inherently stable.
The stability factor S is obtained
1 + 7,000⁄5
S = 101 = 94.3
101 + 7,000⁄5
Substituting in thermal stability thermal resistance equation we get
1
(40 − 2 × 1 × 15)(94.3)(0.07 × 5 × 10−3 ) < or
θ
θ < 3.03℃/W

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