1(a).

CE AMPLIFIER
OBJECTIVE:
1. Design a common emitter amplifier for the given Specifications.
VCC=12V, IC=2mA, hFE =100,Fl=100Hz, AV =5, V RE2=1v
2. To simulate the same circuit using Multisim.
3. Find the following parameters.
1 a. Bandwidth
2 b. Input and output impedances.
3 c. Voltage gain

EQUIPMENT REQUIRED FOR HARDWARE:

1. R.P.S (0-30V)
2. C.R.O
3. Transistor (BC107)
4. Function generator
5. Resistors
6. Capacitors
CIRCUIT DIAGRAM:
XSC1

E xt T rig
+
_
A B
+ _ + _

0
8

R1 Rc
47kΩ 2.2kΩ
C2
4 7
Vout
Vin 3 10uF
Q1
C1
2

10uF

5
V1 R2
12 V
10kΩ Re 1
120Ω RL
820Ω
V2
6
70.7mVrms
1kHz Re 2
0 0 0
0° 560Ω C3
22uF
0
0 0

Common-Emitter Amplifier
Design
Output requirements: Mid-band voltage gain of the amplifier = 5 and required output voltage
swing = 10 V.
Selection of transistor Select transistor BC107 since its minimum guaranteed (h FE = 100) is
more than the required gain (AV =5) of the amplifier.
DC biasing conditions
VCC is taken as 20% more than required output swing. Hence V CC = 12 V. IC = 2 mA,
because hFE is guaranteed 100 at that current as per data sheet. In order to make the operating
point at the middle of the load line, assume the dc conditions VRC = 40% of V CC = 4.8 V, VRE =
10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V .
Design of RC
VRC = IC X RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.
Design of RE
Suppose you’re asked to design a transistor amplifier for a voltage gain of 5. The gain
from the base to the collector can be approximated by the collector resistance over the emitter
resistance.

Where RC’ is the AC resistance seen by the collector, RC|| RL, and RE’ is the AC resistance
seen by the emitter, RE1. Why include RE2 in the circuit if it’s AC bypassed by CE? The emitter
resistance performs 2 functions: RE1 influences the AC voltage gain and RE1+RE2 controls the DC
bias.
VRE = IE X RE = 1.2 V, V RE2=1v. From this, we get RE = 600Ω
because IE ≈ IC. Use 680Ω std.
RE= RE1+RE2. From this, we get RE1=120Ω, RE2=560Ω std.
Design of voltage divider R1 and R2
Assume the current through R1 = 10IB and that through R2 = 9IB for a stable voltage
across R1 and R2 independent of the variations of the base current.

VR2 = Voltage drop across R2 = VBE + VRE:

i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V: Also, VR2 = 9IBR2 = 1.8 V

But IB = = = 20 µA: Then R2 = = 10.6 k. Use 10 k.

VR1 = voltage across R1 = VCC - VR2 = 12 V - 1.8 V = 10.2 V
 Also, VR1 = 10IBR1 = 10.1 V. Then R1 = = 50 k. Select 47 k std.
Design of RL
Gain of the common emitter amplifier is given by the expression
AV = -(rc/re).

Where rc = RC║RL and re = = = 12.5.

Since the required gain = 5, substituting it in the expression we get, RL = 845Ω. Use 820Ω Std.
Design of coupling capacitors CC1 and CC2
XC1 should be less than the input impedance of the transistor. Here, Rin is the series impedance.

Then XC1 ≤ = Here Rin = R1║R2║ (1 + hFEre) because is RE by passed.

We get Rin = 1.1 kΩ. Then XC1 ≤ 110Ω .

So, CC1 ≥ = 14 µF. Use 15 µF std.

Similarly, XC2 ≤ , Where Rout = RC. Then XCE ≤ 240Ω .

So, CC2 ≥ = 6.6 µF. Use 10 µF std.

Design of bypass capacitors CE
To bypass the lowest frequency (say 100Hz), XCE should be less than or equal to
the resistance RE2.

i.e., XCE ≤ Then, CE ≥ = 23 µF. Use 22 µF

PROCEDURE:
1 1. Connect the circuit diagram as shown in Figure.
2 2. Keep VS at 100 mv, using the signal generator.
3 3. Keeping the input voltage constant, vary the frequency from 0 to 1 MHz in regular steps and
note down the corresponding output voltage.
4 4. Plot the graph between gain (dB) and frequency.
1 5. Calculate the bandwidth from the graph.
2 8. Note down the bandwidth, input and output impedances.

OBSERVATIONS:
From CRO:
1. Input voltage Vi =
2. Output voltage V0 =
3. Voltage gain AV=V0/Vi=
4. Phase shift θ =
From Frequency response:
1. Maximum gain AVmax
2. Lower cutoff frequency(f1) at AVmax-3dB (decibel scale) =
at AVmax/√2 (linear scale) =
3. Higher cutoff frequency(f2) at AVmax-3dB (decibel scale) value
at AVmax/√2 (linear scale) value

S.NO Frequency(Hz) Vo(volts) Gain Av = vo/vs Gain in dB = 20logAv

Graph:
RESULT:

With CE:
Mid-band gain of the amplifier =
Bandwidth of the amplifier =

Without CE:
Mid-band gain of the amplifier =
Bandwidth of the amplifier =
 1(b). CC AMPLIFIER

Aim:
1. To design and construct BJT Common Collector Amplifier using voltage divider bias
(self-bias).
2. To measure the gain and to plot the frequency response & to determination of Gain
3. Bandwidth Product
Apparatus required:
1. Transistors - BC107
2. Regulated Power Supply
3. Audio Frequency Oscillator
4. Resistors - 6Kohm, 8Kohm, 10Kohm(all are ¼ W)
5. Capacitors - 47µF
6. CRO
CIRCUIT DIAGRAM:
Design:
Since voltage amplification is done in the transistor amplifier circuit, we assume
equaldrops across VCE and Emitter Resistance RE. VRE = 6V. The quiescent current of 1mA is
assumed. We assume a standard supply of Vcc = 12V.Drop across RE is assumed to be V RE
=6VDrop across VCE is VCC –VRE =6V We know that ICQ =IE,

Design of R1 & R2
Drop across RE is 6V

Drop across VBE is 0.6V

Drop across the resistance R2 is VR2 = VBE + VRE =6.6V
Assume R2 =10K
 PROCEDURE:
5
6 1. Connect the circuit diagram as shown in Figure.
7 2. Keep VS at 500 mv, using the signal generator.
8 3. Keeping the input voltage constant, vary the frequency from 0 to 10 Mhz in regular steps and
note down the corresponding output voltage.
9 4. Plot the graph between gain (dB) and frequency.
3 5. Calculate the bandwidth from the graph.
4 8. Note down the bandwidth, input and output impedances.

OBSERVATIONS
From CRO:
5. Input voltage Vi =
6. Output voltage V0 =
7. Voltage gain AV=V0/Vi=
8. Phase shift θ =
From Frequency response:
3. Maximum gain AVmax
4. Lower cutoff frequency(f1) at AVmax-3dB (decibel scale) =
at AVmax/√2 (linear scale) =
Higher cutoff frequency(f2) at AVmax-3dB (decibel scale) =
at AVmax/√2 (linear scale) value

S.NO Frequency(Hz) Vo(volts) Gain Av = Vo/Vs Gain in dB = 20logAv

Graph:

RESULT:
Mid-band gain of the amplifier =
Bandwidth of the amplifier =
 2(a).CURRENT SHUNT FEEDBACK AMPLIFIERS
OBJECTIVE:
1. Design a Current Shunt feedback amplifier for the given Specifications.
VCC=12V, IC=2mA, hFE =100,Fl=100HZ, AV =5, V RE2=1v

2. Find the following parameters.

a. Bandwidth
b. Voltage gain

EQUIPMENT REQUIRED FOR HARDWARE:

1. R.P.S (0-30V)
2. R.O
3. Transistor (BC107)
4. Function generator
5. Resistors
6. capacitors
CIRCUIT DIAGRAMS:
 XSC1
V2
0 5 Ext T rig
+
_
12 V A B
Rc2 + _ + _

Rc1 R21 2.2kΩ

R11 2.2kΩ 47kΩ
47kΩ C5
9
7
10uF
Q2
C3
C1 R2 Q1 4 3
8 11
6
4.7kΩ 10uF
10uF BC107BP
BC107BP 2
0
1
V1 Re2
R22 680Ω
Re1 C2 10kΩ
17.67mVrms R12 680Ω 23uF
1kHz 10kΩ
0°

R1

68kΩ

Design
Output requirements: Mid-band voltage gain of the amplifier = 5 and required output voltage
swing = 10 V.
Selection of transistor Select transistor BC107 since its minimum guaranteed (hFE = 100) is
more than the required gain (AV =5) of the amplifier.
DC biasing conditions
VCC is taken as 20% more than required output swing. Hence V CC = 12 V. IC = 2 mA,
because hFE is guaranteed 100 at that current as per data sheet. In order to make the operating
point at the middle of the load line, assume the dc conditions VRC = 40% of V CC = 4.8 V, VRE =
10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V .
Design of RC
VRC = IC X RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.
Design of RE
Suppose you’re asked to design a transistor amplifier for a voltage gain of 5. The gain
from the base to the collector can be approximated by the collector resistance over the emitter
resistance.

Where RC’ is the AC resistance seen by the collector, R C|| RL, and RE’ is the AC resistance
seen by the emitter, RE1. Why include RE2 in the circuit if it’s AC bypassed by CE? The emitter
resistance performs 2 functions: RE1 influences the AC voltage gain and RE1+RE2 controls the DC
bias.

VRE = IE X RE = 1.2 V, V RE2=1v. From this, we get RE = 600Ω

because IE ≈ IC. Use 680Ω std.
RE= RE1+RE2. From this, we get RE1=120Ω, RE2=560Ω std.

Design of voltage divider R1 and R2

Assume the current through R1 = 10IB and that through R2 = 9IB for a stable voltage
across R1 and R2 independent of the variations of the base current.
VR2 = Voltage drop across R2 = VBE + VRE:
i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V: Also, VR2 = 9IBR2 = 1.8 V

But IB = = = 20 µA: Then R2 = = 10.6 k. Use 10 k.

VR1 = voltage across R1 = VCC - VR2 = 12 V - 1.8 V = 10.2 V

Also, VR1 = 10IBR1 = 10.1 V. Then R1 = = 50 k. Select 47 k std.

Design of RL
Gain of the common emitter amplifier is given by the expression
AV = -(rc/re).

Where rc = RC║RL and re = = = 12.5.

Since the required gain = 5, substituting it in the expression we get, RL = 845Ω. Use 820Ω Std.
Design of coupling capacitors CC1 and CC2
XC1 should be less than the input impedance of the transistor. Here, Rin is the series impedance.

Then XC1 ≤ = Here Rin = R1║R2║ (1 + hFEre) because is RE by passed.

We get Rin = 1.1 kΩ. Then XC1 ≤ 110Ω .

So, CC1 ≥ = 14 µF. Use 15 µF std.

Similarly, XC2 ≤ , Where Rout = RC. Then XCE ≤ 240Ω .

So, CC2 ≥ = 6.6 µF. Use 10 µF std.

Design of bypass capacitors CE
To bypass the lowest frequency (say 100Hz), XCE should be less than or equal to
the resistance RE2.

i.e., XCE ≤ Then, CE ≥ = 23 µF. Use 22 µF

PROCEDURE:
 10
11 1. Connect the circuit diagram as shown in Figure.
12 2. Keep VS at 100 mv, using the signal generator.
13 3. Keeping the input voltage constant, vary the frequency from 0 to 1 Mhz in regular steps
and note down the corresponding output voltage.
14 4. Plot the graph between gain (dB) and frequency.
5 5. Calculate the bandwidth from the graph.
6 8. Note down the bandwidth, input and output impedances.

EQUATIONS:

Design values AVF=50, AIF=100

B= (RE2/RF+RE2)
AIF=1/B= (1+RF/RE2)
AVF= (AIF (RC2/RI1))
AIF=100= (1+RF/RE2)
RF=99RE2

OBSERVATIONS:
From CRO:
1. Input voltage Vi =
2. Output voltage V0 =
3. Voltage gain AV=V0/Vi=
4. Phase shift θ =
From Frequency response:
1. Maximum gain AVmax
2. Lower cutoff frequency(f1) at AVmax-3dB (decibel scale) =
a. at AVmax/√2 (linear scale) =
3. Higher cutoff frequency(f2) at AVmax-3dB (decibel scale) value
a.i. at AVmax/√2 (linear scale) value
S.NO Frequency(Hz) Vo(volts) Gain Av = vo/vs Gain in dB = 20logAv
RESULT:
 2(b).Voltage Shunt Feedback Amplifier
AIM:

To measure the voltage gain of current - series feed back amplifier.

APPARATUS:

Transistor BC 107

Breadboard

Regulated Power Supply (0-30V,1A)

Function Generator

CRO(30 Mhz,dualtrace)

Resistors and Capacitors

CIRCUIT DIAGRAM:

THEORY:

When any increase in the output signal results into the input in such a way as to cause the
decrease in the output signal, the amplifier is said to have negative feedback.The advantages of
providing negative feedback are that the transfer gain of the amplifier with feedback can be
establised against variations in the hybrid parameters of the transistor or the parameters of the
other active devices used in the circuit. The most advantage of the negative feedback is that by
propere use of this, there is significant improvement in the frequency response and in the
linearity of the operation of the amplifier.This disadvantage of the negative feedback is that the
voltage gain is decreased.

Model Wave forms and Frequency Response:

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Keep the input voltage constant at 20mV peak-peak and 1kHz frequency.For different
values of load resistance, note down the output voltage and calculate the gain by using the
expression
Av = 20log(V0 / Vi ) dB
3. Remove the emitter bypass capacitor and repeat STEP 2.And observe the effect of
feedback on the gain of the amplifier.
4. For plotting the frquency the input voltage is kept constant at 20mV peak-peak and
the frequency is varied from 100Hz to 1MHz.
5. Note down the value of output voltage for each frequency. All the readings are tabulated
and the voltage gain in dB is calculated by using expression Av = 20log (V0 / Vi ) dB
6. A graph is drawn by takung frquency on X-axis and gain on Y-axis on semi log graph sheet
7.The Bandwidth of the amplifier is calculated from the graph using the expression
Bandwidth B.W = f2 – f 1.
Where f1 is lower cutt off frequency of CE amplifier f 2 is
upper cutt off frequency of CE amplifier
8. The gain-bandwidth product of the amplifier is calculated by using the expression
Gain-Bandwidth Product = 3-dB midband gain X Bandwidth.
Tabular Colums:

Voltage Gain: Vi = 20 mV

S.NO Output V o l t a g e Output Voltage Gain(dB) with Gain(dB)

(Vo) with (Vo) feedback without
feed b a ck without feedback feedback

PRECAUTIONS:

1. While taking the observations for the frequency response , the input voltage must be
maintained constant at 20mV.
2. The frequency should be slowly increased in steps.
3. The three terminals of the transistor should be carefully identified.
4. All the connections should be correct.

RESULT:

3(a).COMMON SOURCE AMPLIFIER

AIM: 1. To obtain the frequency response of the common source FET
Amplifier
2. To find the Bandwidth.
APPRATUS:
N-channel FET (BFW11)
Resistors (6.8KΩ, 1MΩ, 1.5KΩ)
Capacitors (0.1µF, 47µF)
Regulated power Supply (0-30V)
Function generator
CRO
CRO probes
Bread board
Connecting wires

CIRCUIT DIAGRAM:

THEORY:
 A field-effect transistor (FET) is a type of transistor commonly used for weak-signal
amplification (for example, for amplifying wireless (signals). The device can amplify analog or
digital signals. It can also switch DC or function as an oscillator. In the FET, current flows along
a semiconductor path called the channel. At one end of the channel, there is an electrode called
the source. At the other end of the channel, there is an electrode called the drain. The physical
diameter of the channel is fixed, but its effective electrical diameter can be varied by the
application of a voltage to a control electrode called the gate. Field-effect transistors exist in two
major classifications. These are known as the junction FET (JFET) and the metal-oxide-
semiconductor FET (MOSFET). The junction FET has a channel consisting of N-type
semiconductor (N-channel) or P-type semiconductor (P-channel) material; the gate is made of
the opposite semiconductor type. In P-type material, electric charges are carried mainly in the
form of electron deficiencies called holes. In N-type material, the charge carriers are primarily
electrons. In a JFET, the junction is the boundary between the channel and the gate. Normally,
this P-N junction is reverse-biased (a DC voltage is applied to it) so that no current flows
between the channel and the gate. However, under some conditions there is a small current
through the junction during part of the input signal cycle. The FET has some advantages and
some disadvantages relative to the bipolar transistor. Field-effect transistors are preferred for
weak-signal work, for example in wireless, communications and broadcast receivers. They are
also preferred in circuits and systems requiring high impedance. The FET is not, in general, used
for high-power amplification, such as is required in large wireless communications and broadcast
transmitters.
Field-effect transistors are fabricated onto silicon integrated circuit (IC) chips. A single IC can
contain many thousands of FETs, along with other components such as resistors, capacitors, and
diodes.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. A signal of 1 KHz frequency and 50mV peak-to-peak is applied at the
Input of amplifier.
3. Output is taken at drain and gain is calculated by using the expression,
Av=V0/Vi

4. Voltage gain in dB is calculated by using the expression,

Av=20log 10(V0/Vi)
5. Repeat the above steps for various input voltages.
6. Plot Av vs. Frequency
7. The Bandwidth of the amplifier is calculated from the graph using the
Expression,
Bandwidth BW=f2-f1
Where f1 is lower 3 dB frequency
f2 is upper 3 dB frequency

OBSERVATIONS:

S.NO INPUT OUTPUT VOLTAGE GAIN

VOLTAGE(Vi) VOLTAGE(V0) Av= (V0/Vi)

MODEL GRAPH:
PRECAUTIONS:

1. All the connections should be tight.

2. Transistor terminals must be identified properly
.
RESULT:

3(b).COMMON DRAIN AMPLIFIER

AIM:
To connect a JFET in the common-drain configuration and plot its characteristics
APPRATUS:
N-channel FET (BFW11)
Resistors
Capacitors
Regulated power Supply (0-30V)
Function generator
CRO
CRO probes
Bread board
Connecting wires

CIRCUIT DIAGRAM:

THEORY:
The basic circuit for the common-drain configuration or the source follower configuration is
shown. As is evident from the figure no resistor is connected in series with the drain terminal.
The voltage across resistor RS provides the gate-source biasing voltage. This configuration is
similar to the common-collector configuration for the BJTs. Like the common-collector
configuration, the common-drain configuration also offers high input impedance, low output
impedance, nearly unity voltage gain and no input-output phase reversal.
Procedure:
1. Connect the circuit as shown.
2. Use RG of 1 kΩ and RS of 470 Ω. The DCSource0 is used for VGS and DCSource1 is used
for VDS. The ammeter will measure the ID current.
3. Click on Run > DCAnalysis . Sweep VDS from 0 to 10V and VGS from 0 to 2V
4. Click on “Run” to run the simulation and obtain the charactersitics

OBSERVATIONS:

S.NO INPUT OUTPUT VOLTAGE GAIN

VOLTAGE(Vi) VOLTAGE(V0) Av= (V0/Vi)

PRECAUTIONS:

1. All the connections should be tight.

2. Transistor terminals must be identified properly
.
RESULT: The frequency response of the common drain FET
Amplifier and Bandwidth is obtained.

4. TWO STAGE RCCOUPLED AMPLIFIERS

AIM:
To obtain the frequency response of’ a two stage RC coupled amplifier.

Apparatus:

Transistors
 BC 107
Resistors
Capacitors
Signal Generators & CRO

Circuit Diagram:

Theory :

The output from a single stage amplifier is usually insufficient to drive an o/p device. To achieve
more gain, the o/p of one stage is given as the input to the other stage which forms multistage
amplifier. If the two stages are coupled by R and C, then the amplifier is called RC coupled amplifier.
The performance of an amplifier can be determined from the following terms.

Gain:-

The gain is defined as ratio of output to input. The gain of multistage

amplifier is equal to the product of gains of individual stages i.e G=G1.G2.G3.

Frequency Response:-

At low frequencies (<50HZ) the reactance of coupling capacitor cc is high

and hence very small part of signal will pass from one stage to next stage. This
increases the loading effect of next stage and reduces the voltage gain.

At high frequencies, capacitance reduces. Due to this base emitter junction

is low which increases the base current. This reduces the amplification factor.

At mid frequencies, the voltage gain of the amplifier is constant. In this

range, as frequency increases, reactance of CC reduces which tends to increase
the gain. At the same time, lower reactance means higher reactance of first stage
and hence lower gain, these two factors cancel each other resulting in a uniform
gain at mid frequency.

PROCEDURE
1. Connect the circuit as per the circuit diagram
2. Give 1 KHz signal, 25 mV (p-p) as Vs from signal generator
3. Observe the output on CRO for proper working of the amplifier
1.4. After ensuring the amplifier function, vary signal
frequency from 50 Hz to 600 Hz in proper steps for 15
to 20 readings. Keeping Vs = 25 mV (p-p) at every
frequency, note down the resetting output voltage and
tabulate in a table.
05. Calculate gain db and plot on semi log graph paper for frequency VS gain db.
Expected waveforms:

Tabular Form:
S.NO FREQUENCY OUTPUT GAIN GAIN IN
(HZ) V OLTA G E( A v = Vo/Vi dB

RESULT:

5. CASCODE AMPLIFIER

OBJECTIVE:

1. To design a Cascade Amplifier for the given specifications.

EQUIPMENT REQUIRED:
 1. Regulated power supply (0-30V)
2. Cathode Ray Oscilloscope with probes
3. Transistor (BC107) - 2No.
4. Resistors
5. Capacitors

CIRCUIT DIAGRAM:

0
V2 XSC1
10 V
8
R7 Ext Trig
R3 3kΩ
+
_
53.5kΩ C1 A B
5 6 + _ + _

3 Q2 1.4uF
C3
0

1.6uF
BC107BP
R2
30kΩ 9
R6
Q1 9kΩ 0
R4 C2
1 4
7 V1
600Ω 15.2uF
BC107BP
17.6mVrms R1
16.5kΩ 2
60 Hz
R5 C4
0° 1kΩ 31.8uF

PROCEDURE:

1. Connect the circuit as per the diagram. Set 20mv-O.3v in AF oscillator.

2. Keep the input voltage constant.
3. Measure the output (V out) for different ranges of frequencies (20Hz-50 KHz) in steps.
4. Plot the graph between frequency and gain.
5. Calculate the gain and band width.

Graphs:

The frequency response curve for an Cascade amplifier is plotted, taking frequency on X-axis
and gain on Y-axis. 3db points are noted by taking the calculations as following.
1. Determine 70.7 % of maximum gain on graph.
2. Draw horizontal line corresponding to 3db points wherever this line cuts the curve
points are Noted as f2 & fl.

Band width =f2-f1.

RESULT:
 6. RC PHASE SHIFT OSCILLATOR using TRANSISTOR
AIM: To study and determine the frequency of oscillations of RC phase shift oscillator and
verify with the theoretical value.
APPARATUS REQUIRED:
6. Regulated power supply (0-30V)
7. Cathode Ray Oscilloscope with probes
8. Transistor (BC107) - 1No.
9. Resistors (2.2K,680,47K,10K) - 1No.
2.2K - 3No.s
5. Capacitors (100µF) - 1No.
10µF - 2N0.s
10nF - 3No.s
6. Connecting wires.
CIRCUIT DIAGRAM:
XSC1
Ext T rig
+
_
5 A B
+ _ + _

0
V1 3
12 V R1 Rc
0 47kΩ 2.2kΩ Cc2
4

Q1 10uF
Cc1 1

10uF BC107BP
R2
10kΩ
2

Re Ce
680Ω 100uF
0
C3 C2 C1
7 8 9

10nF 10nF 10nF

Ro1 Ro2 Ro3
2.2kΩ 2.2kΩ 2.2kΩ

0
Design
Output requirements: Mid-band voltage gain of the amplifier = 5 and required output voltage
swing = 10 V.
Selection of transistor Select transistor BC107 since its minimum guaranteed (hFE = 100) is
more than the required gain (AV =5) of the amplifier.
DC biasing conditions
VCC is taken as 20% more than required output swing. Hence V CC = 12 V. IC = 2 mA,
because hFE is guaranteed 100 at that current as per data sheet. In order to make the operating
point at the middle of the load line, assume the dc conditions VRC = 40% of V CC = 4.8 V, VRE =
10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V .
Design of RC
VRC = IC X RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.
Design of RE
VRE = IE X RE = 1.2 V, V RE=1v. From this, we get RE = 600Ω
because IE ≈ IC. Use 680Ω std.
Design of voltage divider R1 and R2
Assume the current through R1 = 10IB and that through R2 = 9IB for a stable voltage
across R1 and R2 independent of the variations of the base current.
VR2 = Voltage drop across R2 = VBE + VRE:
i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V: Also, VR2 = 9IBR2 = 1.8 V

But IB = = = 20 µA: Then R2 = = 10.6 k. Use 10 k.

VR1 = voltage across R1 = VCC - VR2 = 12 V - 1.8 V = 10.2 V

Also, VR1 = 10IBR1 = 10.1 V. Then R1 = = 50 k. Select 47 k std.

Design of coupling capacitors CC1 and CC2
XC1 should be less than the input impedance of the transistor. Here, Rin is the series impedance.

Then XC1 ≤ = Here Rin = R1║R2║ (1 + hFEre) because is RE by passed.

We get Rin = 1.1 kΩ. Then XC1 ≤ 110Ω .

So, CC1 ≥ = 14 µF. Use 15 µF std.

Similarly, XC2 ≤ , Where Rout = RC. Then XCE ≤ 240Ω .

So, CC2 ≥ = 6.6 µF. Use 10 µF std.

Design of bypass capacitors CE
To bypass the lowest frequency (say 2kHz), XCE should be less than or equal to
the resistance RE.
i.e., XCE ≤ Then, CE ≥ = 100 µF. Use 100 µF
PROCEDURE:
1. Switch ON the computer and open the multisim software.
2. Check whether the icons of the instruments are activated and enable.
3. Now connect the circuit using the designed values of each and every component.
4. Connect the Cathode Ray Oscilloscope (CRO) to the out put terminals of the circuit.
5. Go to simulation button click it for simulation process.
6. From the CRO note the following values
a. Amplitude of the output wave form
b. Time period of the signal
OBSERVATIONS:
From CRO:
1. Amplitude of the output wave form
2. Time period of the signal
CALCULATIONS:
Theoretically:
Where R= Ro1+Ro2+Ro3=2.2k Ω , C=C1=C2=C3=10nF
f = k=

Practically:
7
S.No Therotical Frequeny Practical Frequnecy

MODEL GRAPH:

9
 10
11
RESULT:

7. WEIN BRIDGE OSCILLATOR

AIM:
To Design Wein Bridge Oscillator so that the output frequency is 965 Hz.

APPARATUS
1.CRO (Dual channel) - 1 No
2. Bread Board – 1 No
3. Dual Channel Power Supply – 1 No

COMPONENTS:
1. 1kΩ Resistor – 3 No.
2. 10kΩ Resistor – 4 No.
3. 33 kΩ Resistor – No.
4. 2.2 kΩ Resistor – 2 No.
5. 0.01 F Capacitor – 2 No.
6. 10 F Capacitor – 2 No.

THEORY:

In this oscillator the Wein Bridge Circuit is connected between the amplifier input
terminals and the output terminal. The bridge has a series RC network in one arm and parallel
RC network in the adjoining arm. In the remaining two arms of the bridge resistors R1 and RF
o
are connected. The total phase-shift around the circuit is 0 when the bridge is balanced.

CIRCUIT DIAGRAM:

Procedure
i. Construct the circuit as shown in the circuit diagram.
ii. Adjust the potentiometer R such that an output wave form is
f
btained.
iii. Calculate the output wave form frequency and peak to peak voltage.
iv. Compare the theoretical and practical values of the output waveform frequency.

OBSERVATIONS:

The frequency of oscillation =

CALCULATIONS:
The frequency of oscillation f is exactly the resonant frequency of the balanced Wein
o
Bridge and is given by f = 1/ (2 π RC)
o
= 0.159 / RC

The gain required for sustained oscillations is given by A = 3. i.e., R = 2R

v f 1
Let C = 0.05 F
Then f = 1/ (2 RC)
o
 R = 1/ (2 f C)
o
 = 3.3 k Now let
R = 12 k Then
1
R =2R = 4 k
f 1
Use R = 50 k potential meter
f

GRAPH:

RESULT: