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    Project 1: Combinational Logic: I-Conception of Digital Adders and Subtractors

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    Mehdi Ait EL Kadi
    The document discusses digital logic circuits including adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. 1) It describes half adders, full adders, half subtractors, and full subtractors using truth tables and logic diagrams. 2) It explains multiplexers and demultiplexers with 2 and 4 inputs/outputs. 3) It discusses the difference between decoders and demultiplexers and how a decoder with an enable input can function as a demultiplexer. 4) It provides an example of a BCD decimal decoder with its output truth table.

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    Project 1: Combinational Logic: I-Conception of Digital Adders and Subtractors

    Uploaded by

    Mehdi Ait EL Kadi
    29 views11 pages
    The document discusses digital logic circuits including adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. 1) It describes half adders, full adders, half subtractors, and full subtractors using truth tables and logic diagrams. 2) It explains multiplexers and demultiplexers with 2 and 4 inputs/outputs. 3) It discusses the difference between decoders and demultiplexers and how a decoder with an enable input can function as a demultiplexer. 4) It provides an example of a BCD decimal decoder with its output truth table.

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    The document discusses digital logic circuits including adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. 1) It describes half adders, full adders, half subtractors, and full subtractors using truth tables and logic diagrams. 2) It explains multiplexers and demultiplexers with 2 and 4 inputs/outputs. 3) It discusses the difference between decoders and demultiplexers and how a decoder with an enable input can function as a demultiplexer. 4) It provides an example of a BCD decimal decoder with its output truth table.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views11 pages

    Project 1: Combinational Logic: I-Conception of Digital Adders and Subtractors

    Uploaded by

    Mehdi Ait EL Kadi
    The document discusses digital logic circuits including adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. 1) It describes half adders, full adders, half subtractors, and full subtractors using truth tables and logic diagrams. 2) It explains multiplexers and demultiplexers with 2 and 4 inputs/outputs. 3) It discusses the difference between decoders and demultiplexers and how a decoder with an enable input can function as a demultiplexer. 4) It provides an example of a BCD decimal decoder with its output truth table.

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    R

    ​ éalisé par : EL MEHDI AIT ELKADI 


     

       

     
     

    Project 1: Combinational logic 


     
    I- Conception of Digital Adders and 
    Subtractors 
    1) Digital adder : 

    ● Half-Adder:   
    A  B  Sn   Rn 

    0  0  0  0 

    0  1  1  0 

    1  0  1  0 

    1  1  0  1 

    -From the truth table, the simplified function S of the half-adder : 

    ● Sn= ​A̅B+AB̅=A⊕B ; Rn=​AB

     
    2  

    -the logic diagram :

    ● Full-Adder:  
     

    An   Bn   Rn-1  Sn   Rn 

    0  0  0  0  0 

    0  0  1  1  0 

    0  1  0  1  0 

    0  1  1  0  1 

    1  0  0  1  0 

    1  0  1  0  1 

    1  1  0  0  1 

    1  1  1  1  1 

    -From the truth table, the simplified function S of the half-adder : 

    ● Sn=(An⊕(Bn⊕Rn-1))
    ● Rn=(An⊕Bn)Rn-1+AnBn

        
    3  

    -the logic diagram :

    2) Digital subtractor : 

    Half-Substractor:   

    An  Bn  Dn  Rn 

    0  0  0  0 

    0  1  1  1 

    1  0  1  0 

    1  1  0  0 

    -​From the truth table, the simplified function S of the half-adder : 

    Sn= ​A̅nBn+AnB̅n=An⊕Bn ; Rn=A̅nBn

        
    4  

    -the logic diagram​ :

    Full-Substractor​:

    An Bn Rn-1 Dn Rn

    0 0 0 0 0

    0 0 1 1 1

    0 1 0 1 1

    0 1 1 0 1

    1 0 0 1 0

    1 0 1 0 0

    1 1 0 0 0

    1 1 1 1 1

    -From the truth table, the simplified function S of the half-adder : 

    ● Dn=(An⊕(Bn⊕Rn-1))
    ● Rn=Rn-1Bn

        
    5  

    -the logic diagram :

    II- Conception of Multiplexer and Demultiplexer circuits:

    1- Multiplexer with k inputs:

    ● MUX with 2 inputs :

    A S

    0 D0

    1 D1

    S=A̅D0+AD1

        
    6  

    MUX with 4 inputs :

    A B S

    0 0 D0

    0 1 D1

    1 0 D2

    1 1 D3

    S=A̅B̅D0+A̅BD1+AB̅D2+A̅B̅D3

        
    7  

    2-Demultiplexer with k output :

    ● DEMUX with 2 outputs :

    A S0 S1

    0 D 0

    1 0 D

    S0=A̅D ; S1=AD

        
    8  

    ● DEMUX with 4 outputs :

        
    9  

    Difference Between a Decoder and Demultiplexer is the function of Decoder and a

    Demultiplexer – Decoder is the inverse function of an encoder, which is to translate coded

    digital input signals into equivalent coded output signals. Demultiplexer, on the other

    hand, does exactly the opposite of what a multiplexer does, which is to consolidate several

    data streams into a single stream of media or information.

    A Decoder with Enable input can function as a demultiplexer. A demultiplexer is a circuit that receives 

    information from a single line and directs it to one of 2^n possible output lines. A 2^n demultiplexor 

    receives as input, n selection lines and one Input line. These selection lines are used to select one 

    output line out of 2^n possible lines. To implement a 2^n demultiplexor, we use a n:2^n decoder with 

    Enable input. The n selection lines of the demultiplexer are the n input lines that the decoder gets and 

    the one input line of demulitplexer is the Enable input of the Decoder. 

        
    10  

    III- Conception of Coder and Decoder circuits:

    Decoder is a circuit that generally has n inputs and k=2 n outputs. For each of the possible
    combinations of inputs, only one output line is validated. Decoders are often provided with one or
    more enable inputs (EN: Enable) which are used to validate the ongoing operation.

    1- Decimal decoder BCD (Binary Coded Decimal):

    BCD decoder output table

    Inputs Outputs

    D C B A 0 1 2 3 4 5 6 7 8 9

    0 0 0 0 0 1 1 1 1 1 1 1 1 1

    0 0 0 1 1 0 1 1 1 1 1 1 1 1

    0 0 1 0 1 1 0 1 1 1 1 1 1 1

    0 0 1 1 1 1 1 0 1 1 1 1 1 1

    0 1 0 0 1 1 1 1 0 1 1 1 1 1

    0 1 0 1 1 1 1 1 1 0 1 1 1 1

    0 1 1 0 1 1 1 1 1 1 0 1 1 1

    0 1 1 1 1 1 1 1 1 1 1 0 1 1

    1 0 0 0 1 1 1 1 1 1 1 1 0 1

    1 0 0 1 1 1 1 1 1 1 1 1 1 0

        
    11  

        

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