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    LAB-5 Design and Implementation of Multiplexer and De-Multiplexer

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    Raghuveer
    This document describes a student's lab assignment to design and implement various multiplexers and de-multiplexers using logic gates. The tasks included a 2:1 multiplexer, 1:2 de-multiplexer, 4:1 multiplexer, 1:4 de-multiplexer, and an 8:1 multiplexer built from smaller multiplexers. For each circuit, the student provides the truth table, logic expression, components used, and simulation results verifying the design works as intended.

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    LAB-5 Design and Implementation of Multiplexer and De-Multiplexer

    Uploaded by

    Raghuveer
    70 views13 pages
    This document describes a student's lab assignment to design and implement various multiplexers and de-multiplexers using logic gates. The tasks included a 2:1 multiplexer, 1:2 de-multiplexer, 4:1 multiplexer, 1:4 de-multiplexer, and an 8:1 multiplexer built from smaller multiplexers. For each circuit, the student provides the truth table, logic expression, components used, and simulation results verifying the design works as intended.

    Original Description:

    Digital Logic Microprocessor Lab 5

    Original Title

    20MIS1060_ADURIRAGHUVEER(DLM_LAB-5)

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    This document describes a student's lab assignment to design and implement various multiplexers and de-multiplexers using logic gates. The tasks included a 2:1 multiplexer, 1:2 de-multiplexer, 4:1 multiplexer, 1:4 de-multiplexer, and an 8:1 multiplexer built from smaller multiplexers. For each circuit, the student provides the truth table, logic expression, components used, and simulation results verifying the design works as intended.

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    70 views13 pages

    LAB-5 Design and Implementation of Multiplexer and De-Multiplexer

    Uploaded by

    Raghuveer
    This document describes a student's lab assignment to design and implement various multiplexers and de-multiplexers using logic gates. The tasks included a 2:1 multiplexer, 1:2 de-multiplexer, 4:1 multiplexer, 1:4 de-multiplexer, and an 8:1 multiplexer built from smaller multiplexers. For each circuit, the student provides the truth table, logic expression, components used, and simulation results verifying the design works as intended.

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    Name: ADURI RAGHUVEER

    Reg No: 20MIS1060


    Program M. Tech SE (Int) Fall 2021-2022
    Course Title Digital Logic Microprocessor Lab LAB-5
    Course Code SWE1003 L43+L44

    LAB-5
    Design and Implementation of Multiplexer and De-Multiplexer

    Aim:
     To design and implement a 2:1 multiplexer
     To design and implement a 1:2 de-multiplexer
     To design and implement a 4:1 multiplexer
     To design and implement a 1:4 de-multiplexer
     To design and implement an 8:1 multiplexer using 4:1 and 2:1
    multiplexers (Challenging Task)
    SOFTWARE USED:
    Logic Gate Simulator

    Task 1
    To design and implement a 2:1 multiplexer
    TRUTH TABLE
    Input Output
    S Io I1 Y = IoS’+I1S
    0 0 0 0
    0 1 0 1
    0 0 1 0
    0 1 1 1
    1 0 0 0
    1 1 0 0
    1 0 1 1
    1 1 1 1

    Karnaugh Map and Boolean Expression:


    For Y :
    S\BC A'B’ A’B AB AB’
    S’ 0 0 0 0
    S 1 1 1 0

    Y = IoS’+I1S
    Components used for 2:1 Multiplexer:
    S.No. Component Specification Quantity
    1. AND IC 7408 2
    2. NOT IC 7404 1
    3. OR IC 7432 1
    Simulation:
    RESULT:

    Hence, the 2:1 Multiplexer is successfully implemented, designed


    and verified

    Task 2
    To design and implement a 1:2 de-multiplexer
    TRUTH TABLE
    Input Output
    S D P Q
    0 0 0 0
    0 1 0 1
    1 0 0 0
    1 1 1 0

    Karnaugh Map and Boolean Expression:


    For Y1 (P):

    S\D D' D
    S’ 0 0
    S 0 1

    Y1=DS

    For Yo (Q):
    S\D D' D
    S’ 0 0
    S 0 1
    Yo=DS’
    Components used for 1:2 De-Multiplexer:
    S.No. Component Specification Quantity
    1. AND IC 7408 2
    2. NOT IC 7404 1
    Simulation:

    RESULT:

    Hence, the 1:2 De-Multiplexer is successfully implemented,


    designed and verified

    Task 3

    To design and implement a 4:1 multiplexer


    TRUTH TABLE
    Input Output
    S1 So A B C D Y=ASo’S1’+BS1’So+CS1So’+DS1So
    0 0 0 0 0 0 0
    0 0 1 0 0 0 1
    0 1 0 0 0 0 0
    0 1 0 1 0 0 1
    1 0 0 0 0 0 0
    1 0 0 0 1 0 1
    1 1 0 0 0 0 0
    1 1 0 0 0 1 1

    Boolean Expression:
    Y=ASo’S1’+BS1’So+CS1So’+DS1So

    Components used for 4:1 Multiplexer:


    S.No. Component Specification Quantity
    1. AND IC 7408 4
    2. NOT IC 7404 2
    3. OR IC 7432 1

    Simulation:
    RESULT:

    Hence, the 4:1 Multiplexer is successfully implemented, designed


    and verified

    Task 4

    To design and implement a 1:4 De-multiplexer


    TRUTH TABLE
    Data Input Select Input Output
    I So S1 Y3 Y2 Y1 Yo
    I 0 0 0 0 0 1
    I 0 1 0 0 1 0
    I 1 0 0 1 0 0
    I 1 1 1 0 0 0

    Karnaugh Map and Boolean Expression:


    For Yo:
    I\SoS1 S0'S1’ So’S1 SoS1 SoS1’
    I’ 0 0 0 0
    I 1 0 0 0

    Yo = I. so’. S1’

    For Y1:
    I\SoS1 S0'S1’ So’S1 SoS1 SoS1’
    I’ 0 0 0 0
    I 0 0 0 1
    Y1 = I. So. S1’

    For Y2:
    I\SoS1 S0'S1’ So’S1 SoS1 SoS1’
    I’ 0 0 0 0
    I 0 1 0 0

    Y2 = I. So’. S1
    For Y3:
    I\SoS1 S0'S1’ So’S1 SoS1 SoS1’
    I’ 0 0 0 0
    I 0 0 0 0

    Y3 = I. So. S1

    Components used for 1:4 De-Multiplexer:


    S.No. Component Specification Quantity
    1. AND IC 7408 4
    2. NOT IC 7404 2

    Simulation:
    RESULT:
    Hence, the 1:4 De-Multiplexer is successfully implemented,
    designed and verified

    Challenging Task

    To design and implement an 8:1 multiplexer using 4:1 and 2:1


    multiplexers
    TRUTH TABLE
    SELECT INPUT OUTPUT
    S2 S1 So Y
    0 0 0 Io
    0 0 1 I1
    0 1 0 I2
    0 1 1 I3
    1 0 0 I4
    1 0 1 I5
    1 1 0 I6
    1 1 1 I7

    Components used for 8:1 Multiplexer using 4:1 and 2:1 Multiplexer:
    S.No. Component Quantity
    1. 4:1 MUX 2
    2. 2:1 MUX 1

    Simulation:
    RESULT:

    Hence, the 8:1 Multiplexer is successfully implemented, designed


    and verified

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