78k Series Micro User Manual

User’s Manual
78K/0S Series
8-Bit Single-Chip Microcontroller
Instructions
Common to 78K/0S Series
Document No. U11047EJ3V0UMJ1 (3rd edition)

Date Published November 2000 N CP(K)
© 1996
Printed in Japan
[MEMO]
2 User’s Manual U11047EJ3V0UM00

NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM is a trademark of NEC Corporation.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The following products are manufactured and sold based on a license contract with CP8 Transac
regarding the EEPROM microcontroller patent.
These products cannot be used for an IC card (SMART CARD).
Applicable products: µPD789146, 789156, 789197AY, 789217AY Subseries
User’s Manual U11047EJ3V0UM00 3

ë ë
3XUFKDVHý RIý 1(&ý , &ý FRPSRQHQWVý FRQYH\Vý Dý OLFHQVHý XQGHUý WKHý 3KLOLSVý , &ý 3DWHQWý 5LJKWVý WRý XVHý WKHVH
ë ë
FRPSRQHQWVý LQý DQý , &ý V\VWHPñý SURYLGHGý WKDWý WKHý V\VWHPý FRQIRUPVý WRý WKHý , &ý 6WDQGDUGý 6SHFLILFDWLRQý DV
GHILQHGýE\ý3KLOLSVï
$SSOLFDEOHýSURGXFWVãýµ3'æåäìäæ$<ñýæåäëìæ$<ý6XEVHULHV
• The information in this document is current as of March, 1999. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4

Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 408-588-6000 Eindhoven, The Netherlands Tel: 2886-9318
800-366-9782 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 408-588-6130 Fax: 040-2444580
800-729-9288 NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A. Seoul Branch
NEC Electronics (Germany) GmbH Velizy-Villacoublay, France Seoul, Korea
Duesseldorf, Germany Tel: 01-30-67 58 00 Tel: 02-528-0303
Tel: 0211-65 03 02 Fax: 01-30-67 58 99 Fax: 02-528-4411
Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
NEC Electronics (UK) Ltd. Madrid Office United Square, Singapore
Milton Keynes, UK Madrid, Spain Tel: 65-253-8311
Tel: 01908-691-133 Tel: 91-504-2787 Fax: 65-250-3583
Fax: 01908-670-290 Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Taipei, Taiwan
Milano, Italy Scandinavia Office Tel: 02-2719-2377
Tel: 02-66 75 41 Taeby, Sweden Fax: 02-2719-5951
Fax: 02-66 75 42 99 Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7

MAJOR REVISIONS IN THIS EDITION
Page Contents
Throughout • Addition of the following target products

µPD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167, 789177, 789197AY,
789217AY, 789407A, 789417A, and 789842 Subseries
• Deletion of the following target products

µPD789407, 789417, and 789806Y Subseries
p. 52 Modification of MOV PSW, #byte instruction code
p. 52 Modification of MOVW rp, AX instruction code
p. 54 Modification of XOR A, r instruction code
p. 54 Modification of CMP A, r instruction code
The mark shows major revised points.

INTRODUCTION
Readers This manual is intended for users who wish to understand the functions of 78K/0S
Series products and to design and develop its application systems and programs.
78K/0S Series products

• µPD789014 Subseries: µPD789011, 789012, 78P9014
• µPD789026 Subseries: µPD789022, 789024, 789025, 789026, 78F9026
• µPD789046 Subseries µPD789046, 78F9046
Note
:
• µPD789104 Subseries: µPD789101, 789102, 789104
• µPD789114 Subseries: µPD789111, 789112, 789114, 78F9116
• µPD789124 Subseries µPD789121, 789122, 789124
Note
:
• µPD789134 Subseries µPD789131, 789132, 789134, 78F9136
Note
:
• µPD789146 Subseries µPD789144, 789146
Note
:
• µPD789156 Subseries µPD789154, 789156, 78F9156
Note
:
• µPD789167 Subseries µPD789166, 789167
Note
:
Note
:
• µPD789197AY Subseries : µPD789196AY, 789197AY, 78F9197AY
Note
• µPD789217AY Subseries : µPD789216AY, 789217AY, 78F9217AY

Note
• µPD789407A Subseries: µPD789405A, 789406A, 789407A

• µPD789417A Subseries: µPD789415A, 789416A, 789417A, 78F9418A
• µPD789800 Subseries: µPD789800, 78F9801
Note
:
Note Under development
Purpose This manual is intended for users to understand the instruction functions of 78K/0S
Series products.
Organization The contents of this manual are broadly divided into the following.
• CPU functions
• Instruction set
• Explanation of instructions
How to read this manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To check the details of the functions of an instruction whose mnemonic is known:

→ See APPENDICES A and B INSTRUCTION INDEX.
• To check an instruction whose mnemonic is not known but whose general function is
known:
→ Check the mnemonic in CHAPTER 4 INSTRUCTION SET, then the functions in
CHAPTER 5 EXPLANATION OF INSTRUCTIONS.
• To understand the overall functions of the 78K/0S Series products instructions in
general:
→ Read this manual in the order of the CONTENTS.

• To learn the hardware functions of the 78K/0S Series products:
→ Refer to the user's manual for each product (see Related documents).
Conventions Data significance: Higher digits on the left and lower digits on the right
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeral representation: Binary...............×××× or ××××B
Decimal ............××××
Hexadecimal ....××××H
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Document common to 78K/0S Series
Document Name Document Number
English Japanese
User's Manual Instructions This manual U11047J
Individual documents
• µPD789014 Subseries
English Japanese
µPD789011, 789012 Data Sheet U11095E U11095J
µPD78P9014 Data Sheet U10912E U10912J
µPD789014 Subseries User's Manual U11187E U11187J
English Japanese
µPD789022, 789024, 789025, 789026 Data Sheet U11715E U11715J
µPD78F9026 Data Sheet U11858E U11858J
English Japanese
µPD789046 Preliminary Product Information U13380E U13380J
µPD78F9046 Preliminary Product Information U13546E U13546J
µPD789046 Subseries User’s Manual U13600E U13600J

English Japanese
µPD789101, 789102, 789104 Data Sheet To be prepared U12815J
English Japanese
µPD789111, 789112, 789114 Preliminary Product Information U13013E U13013J
English Japanese
English Japanese
• µPD789146, 789156 Subseries
English Japanese
µPD789144, 789146, 789154, 789156 Preliminary Product Information U13478E U13478J
µPD78F9156 Preliminary Product Information To be prepared U13756J
µPD789146, 789156 Subseries User’s Manual U13651E U13651J
• µPD789167, 789177 Subseries
English Japanese
µPD789166, 789167, 789176, 789177 Preliminary Product Information To be prepared U14017J
µPD78F9177 Preliminary Product Information To be prepared U14022J
µPD789177 Subseries User’s Manual To be prepared To be prepared

• µPD789197AY Subseries
English Japanese
µPD789196AY, 789197AY Preliminary Product Information U13853E U13853J
µPD78F9197Y Preliminary Product Information U13224E U13224J
µPD789217Y Subseries User’s Manual U13186E U13186J
• µPD789217AY Subseries
English Japanese
µPD789216Y, 789217Y Preliminary Product Information U13196E U13196J
µPD78F9217Y Preliminary Product Information U13205E U13205J
µPD789217Y Subseries User’s Manual U13186E U13186J
• µPD789407A, 789417A Subseries
English Japanese
µPD789405A, 789406A, 789407A, 789415A, 789416A, 789417A Data Sheet To be prepared U14024J
µPD78F9418A Data Sheet To be prepared To be prepared
µPD789407A, 789417A Subseries User's Manual To be prepared U13952J
English Japanese
µPD789800 Data Sheet U12627E U12627J
English Japanese
µPD789841, 789842 Preliminary Product Information U13790E U13790J
Caution The above documents are subject to change without prior notice. Be sure to use the latest
version document when starting design.

CONTENTS
CHAPTER 1 MEMORY SPACE................................................................................................................ 15

1.1 Memory Space........................................................................................................................................... 15
1.2 Internal Program Memory (Internal ROM) Space ................................................................................... 15
1.3 Vector Table Area ..................................................................................................................................... 17
1.4 CALLT Instruction Table Area ................................................................................................................. 20
1.5 Internal Data Memory Space.................................................................................................................... 20
1.6 Special Function Register (SFR) Area .................................................................................................... 22
CHAPTER 2 REGISTERS ........................................................................................................................ 23

2.1 Control Registers...................................................................................................................................... 23
2.1.1 Program counter (PC)................................................................................................................... 23
2.1.2 Program status word (PSW) ......................................................................................................... 23
2.1.3 Stack pointer (SP)......................................................................................................................... 24
2.2 General-Purpose Registers...................................................................................................................... 25
2.3 Special Function Registers (SFRs) ......................................................................................................... 27
CHAPTER 3 ADDRESSING ..................................................................................................................... 29

3.1 Addressing of Instruction Address ......................................................................................................... 29
3.1.1 Relative addressing ...................................................................................................................... 29
3.1.2 Immediate addressing .................................................................................................................. 30
3.1.3 Table indirect addressing.............................................................................................................. 31
3.1.4 Register addressing...................................................................................................................... 32
3.2 Addressing of Operand Address............................................................................................................. 33
3.2.1 Direct addressing.......................................................................................................................... 33
3.2.2 Short direct addressing................................................................................................................. 34
3.2.3 Special function register (SFR) addressing .................................................................................. 35
3.2.4 Register addressing...................................................................................................................... 36
3.2.5 Register indirect addressing ......................................................................................................... 37
3.2.6 Based addressing ......................................................................................................................... 38
3.2.7 Stack addressing .......................................................................................................................... 38
CHAPTER 4 INSTRUCTION SET ............................................................................................................. 39

4.1 Operation ................................................................................................................................................... 40
4.1.1 Operand representation and description formats ......................................................................... 40
4.1.2 Description of operation column ................................................................................................... 41
4.1.3 Description of flag column ............................................................................................................ 41
4.1.4 Description of clock column .......................................................................................................... 42
4.1.5 Operation list................................................................................................................................. 43
4.1.6 Instruction list by addressing ........................................................................................................ 48
4.2 Instruction Codes ..................................................................................................................................... 51
4.2.1 Description of instruction code table............................................................................................. 51
4.2.2 Instruction code list ....................................................................................................................... 52

CHAPTER 5 EXPLANATION OF INSTRUCTIONS.................................................................................. 57
5.1 8-Bit Data Transfer Instructions .............................................................................................................. 59
5.2 16-Bit Data Transfer Instructions ............................................................................................................ 62
5.3 8-Bit Operation Instructions .................................................................................................................... 65
5.4 16-Bit Operation Instructions .................................................................................................................. 74
5.5 Increment/Decrement Instructions.......................................................................................................... 78
5.6 Rotate Instructions ................................................................................................................................... 83
5.7 Bit Manipulation Instructions .................................................................................................................. 88
5.8 CALL/RETURN Instructions..................................................................................................................... 92
5.9 Stack Manipulation Instructions.............................................................................................................. 97
5.10 Unconditional Branch Instruction ......................................................................................................... 101
5.11 Conditional Branch Instructions ........................................................................................................... 103
5.12 CPU Control Instructions ....................................................................................................................... 111
APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) .................................................. 117
APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ............................ 119
APPENDIX C REVISION HISTORY ........................................................................................................ 121

LIST OF FIGURES
Figure No. Title Page
2-1. Format of Program Counter..............................................................................................................................23

2-2. Format of Program Status Word.......................................................................................................................23
2-3. Format of Stack Pointer....................................................................................................................................24
2-4. Data to Be Saved to Stack Memory .................................................................................................................25
2-5. Data to Be Restored from Stack Memory .........................................................................................................25
2-6. General-Purpose Register Configuration .........................................................................................................26
LIST OF TABLES
Table No. Title Page
1-1. Internal ROM Space of 78K/0S Series Products ..............................................................................................15

1-2. Vector Table (0000H to 0013H) ( µPD789014 Subseries) ................................................................................17
1-3. Vector Table (0000H to 002BH) ( µPD789026 Subseries) ................................................................................17
1-5. Vector Table (0000H to 0015H) ( µPD789104, 789114, 789124, 789134 Subseries) ......................................17
1-6. Vector Table (0000H to 0019H) (µPD789146, 789156 Subseries) ..................................................................18
1-7. Vector Table (0000H to 0023H) ( µPD789167, 789177 Subseries) ..................................................................18
1-8. Vector Table (0000H to 0027H) ( µPD789197AY, 789217AY Subseries).........................................................18
1-9. Vector Table (0000H to 0023H) ( µPD789407A and µPD789417A Subseries).................................................19
1-12. Internal Data Memory Space of 78K/0S Series Products.................................................................................20
4-1. Operand Representation and Description Formats ..........................................................................................40

[MEMO]

CHAPTER 1 MEMORY SPACE
1.1 Memory Space
The 78K/0S Series product program memory map varies depending on the internal memory capacity. For details
of the memory mapped address area, refer to the User's Manual of each product.
1.2 Internal Program Memory (Internal ROM) Space
The 78K/0S Series product has internal ROM in the address space shown below. Program and table data, etc.
are stored in ROM. This memory space is usually addressed by the program counter (PC).
Table 1-1. Internal ROM Space of 78K/0S Series Products (1/2)
Capacity 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes
Address 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to

Space 07FFH 0FFFH 1FFFH 2FFFH 3FFFH 5FFFH 7FFFH
Subseries Name
µPD789014 µPD789011 µPD789012 µPD78P9014

Subseries
µPD789026 µPD789022 µPD789024 µPD789025 µPD789026

Subseries µPD78F9026
µPD789046 µPD789046
µPD789104 µPD789101 µPD789102 µPD789104

Subseries
µPD789114 µPD789111 µPD789112 µPD789114 µPD78F9116

Subseries
µPD789124 µPD789121 µPD789122 µPD789124

Subseries
µPD789134 µPD789131 µPD789132 µPD789134 µPD78F9136

Subseries
µPD789146 µPD789144 µPD789146

Subseries
µPD789156 µPD789154 µPD789156

µPD789167 µPD789166 µPD789167

Subseries
µPD789177 µPD789176 µPD789177

µPD789197AY µPD789196AY µPD789197AY

Subseries µPD78F9197AY

Table 1-1. Internal ROM Space of 78K/0S Series Products (2/2)
Capacity 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes
Address 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to

Space 07FFH 0FFFH 1FFFH 2FFFH 3FFFH 5FFFH 7FFFH
Subseries Name
µPD789217AY µPD789216AY µPD789217AY

Subseries µPD78F9217AY
µPD789407A µPD789405A µPD789406A µPD789407A

Subseries
µPD789417A µPD789415A µPD789416A µPD789417A µPD78F9418A

Subseries
µPD789800 µPD789800 µPD78F9801

Subseries
µPD789842 µPD789841 µPD789842


1.3 Vector Table Area
The vector table area stores program start addresses to which execution branches when the RESET signal is
input or when an interrupt request is generated. Of the 16-bit address, the lower 8 bits are stored in an even
address, and the higher 8 bits are stored in an odd address.
Table 1-2. Vector Table (0000H to 0013H) (µPD789014 Subseries)
Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H RESET input 000CH INTSR/INTCSI0
0004H INTWDT 000EH INTST
0006H INTP0 0010H INTTM0
000AH INTP2
Table 1-3. Vector Table (0000H to 002BH) (µPD789026 Subseries)
0000H RESET input 000CH INTSR/INTCSI0
0004H INTWDT 000EH INTST
000AH INTP2 002AH INTKR
0000H RESET input 000EH INTST20
0004H INTWDT 0010H INTWT
0006H INTP0 0012H INTWTI
000AH INTP2 0016H INTTM90
000CH INTSR20/INTCSI20 0018H INTKR00
Table 1-5. Vector Table (0000H to 0015H) (µPD789104, 789114, 789124, 789134 Subseries)
0000H RESET input 000CH INTSR20/INTCSI20
0004H INTWDT 000EH INTST20
000AH INTP2 0014H INTAD0

Table 1-6. Vector Table (0000H to 0019H) (µPD789146, 789156 Subseries)
0000H RESET input 000EH INTST20
0004H INTWDT 0010H INTTM80
0008H INTP1 0014H INTAD0
000AH INTP2 0016H INTLVI0
000CH INTSR20/INTCSI20 0018H INTEE1
Table 1-7. Vector Table (0000H to 0023H) (µPD789167, 789177 Subseries)
0000H RESET input 0012H INTWT
0004H INTWDT 0014H INTWTI
000AH INTP2 001AH INTTM82
000CH INTP3 001CH INTTM90
000EH INTSR20/INTCSI20 0022H INTAD0
0010H INTST20
Table 1-8. Vector Table (0000H to 0027H) (µPD789197AY, 789217AY Subseries)
0000H RESET input 0016H INTTM80
0006H INTP0 001AH INTTM82
0008H INTP1 001CH INTTM90
000AH INTP2 001EH INTSMB0
000CH INTP3 0020H INTSMBOV0
0010H INTST20 0024H INTLVI0
0012H INTWT 0026H INTEE1
0014H INTWTI

Table 1-9. Vector Table (0000H to 0023H) (µPD789407A and µPD789417A Subseries)
0000H RESET input 0014H INTWTI
0008H INTP1 001AH INTTM02
000AH INTP2 001CH INTTM50
000CH INTP3 001EH INTKR00
0010H INTST00 0022H INTCMP0
0012H INTWT
0000H RESET input 000EH INTUSBRE
0004H INTWDT 0010H INTP0
0006H INTUSBTM 0012H INTCSI10
0008H INTUSBRT 0014H INTTM00
000AH INTUSBRD 0016H INTTM01
000CH INTUSBST 0018H INTKR00
0000H RESET input 0016H INTST00
0004H INTWDT 0018H INTWT
0006H INTP0 001AH INTWTI
0008H INTP1 001CH INTTM80
000AH INTTM7 001EH INTTM81
000CH INTSER00 0020H INTTM82
000EH INTSR00 0022H INTAD

1.4 CALLT Instruction Table Area
In a 64-byte address area 0040H to 007FH, the subroutine entry address of a 1-byte call instruction (CALLT) can
be stored.
1.5 Internal Data Memory Space
The 78K/0S Series products incorporate the following data memory:
(1) Internal high-speed RAM

The 78K/0S Series products incorporate internal high-speed RAM in the address space shown in Table 1-12.
The internal high-speed RAM is also used as a stack memory.
(2) LCD display RAM (µPD789407A and µPD789417A Subseries)
LCD display RAM is allocated in the area between FA00H and FA1BH.
The LCD display RAM can also be used as ordinary RAM.
(µPD789146, 789156, 789197AY, 789217AY Subseries)
TM
(3) EEPROM
Electrically erasable PROM (EEPROM) is allocated in the address space shown in Table 1-12.
Unlike ordinary RAM, EEPROM retains the data it contains even when the power is turned off. Also, unlike
EPROM, the contents of EEPROM can be erased electrically, without the need to expose the chip to
ultraviolet light.
Table 1-12. Internal Data Memory Space of 78K/0S Series Products (1/2)
Subseries Name Product Name High-Speed RAM LCD Display RAM EEPROM
µPD789014 µPD789011 FE80H to FEFFH  
Subseries µPD789012 (128 bytes)
µPD78P9014 FE00H to FEFFH

(256 bytes)
µPD789025 FD00H to FEFFH
µPD789026 (512 bytes)
µPD78F9026
µPD789046 µPD789046 FD00H to FEFFH  
Subseries µPD78F9046 (512 bytes)
µPD789104
µPD789114
µPD78F9116

Table 1-12. Internal Data Memory Space of 78K/0S Series Products (2/2)
Subseries Name Product Name High-Speed RAM LCD Display RAM EEPROM
µPD789124
µPD789134
µPD78F9136
µPD789146 µPD789144 FE00H to FEFFH  F800H to F8FFH
Subseries µPD789146 (256 bytes) (256 bytes)
µPD789156 µPD789154 FE00H to FEFFH  F800H to F8FFH
Subseries µPD789156 (256 bytes) (256 bytes)
µPD78F9156
µPD78F9177
µPD789197AY µPD789196AY FD00H to FEFFH  F800H to F87FH
Subseries µPD789197AY (512 bytes) (128 bytes)
µPD78F9197AY
µPD789217AY µPD789216AY FD00H to FEFFH  F800H to F87FH
Subseries µPD789217AY (512 bytes) (128 bytes)
µPD78F9217AY
µPD789407A µPD789405A FD00H to FEFFH FA00H to FA1BH 
Subseries µPD789406A (512 bytes) (28 bytes)
µPD789407A
µPD789417A µPD789415A FD00H to FEFFH FA00H to FA1BH 
Subseries µPD789416A (512 bytes) (28 bytes)
µPD789417A
µPD78F9418A
Subseries µPD78F9801 (256 bytes)
µPD78F9842

1.6 Special Function Register (SFR) Area
Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area FF00H to FFFFH
(refer to the User's Manual of each product).

CHAPTER 2 REGISTERS
2.1 Control Registers
The control registers have dedicated functions such as controlling the program sequence, statuses, and stack
memory. The control registers include a program counter, program status word, and stack pointer.
2.1.1 Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
______________
When the RESET signal is input, the program counter is set to the value of the reset vector table, which are
located at addresses 0000H and 0001H.
Figure 2-1. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
2.1.2 Program status word (PSW)

Program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
The contents of program status word are automatically stacked when an interrupt request is generated or when
the PUSH PSW instruction is executed and, are automatically reset when the RETI and POP PSW instruction are
executed.
______________
RESET input sets PSW to 02H.
Figure 2-2. Format of Program Status Word
7 0
IE Z 0 AC 0 0 1 CY

CHAPTER 2 REGISTERS
(1) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is
controlled by the interrupt mask flag for each interrupt source.
The IE flag is reset (0) when the DI instruction execution is executed or when an interrupt is acknowledged,
and set (1) when the EI instruction is executed.
(2) Zero flag (Z)

When the operation result is zero, this flag is set (1); otherwise, it is reset (0).
(3) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set (1); otherwise, it is reset (0).
(4) Carry flag (CY)

This flag records an overflow or underflow upon add/subtract instruction execution. It also records the shift-
out value upon rotate instruction execution, and functions as a bit accumulator during bit operation instruction
execution.
2.1.3 Stack pointer (SP)

This is a 16-bit register that holds the first address of the stack area in the memory. Only the internal high-speed
RAM area can be set as the stack area.
Figure 2-3. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory, and is incremented after read (reset) from the
stack memory.
The data saved/restored as a result of each stack operation are as shown in Figures 2-4 and 2-5.
______
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
executing an instruction.

CHAPTER 2 REGISTERS
Figure 2-4. Data to Be Saved to Stack Memory
PUSH rp CALL, CALLT Interrupt

instruction instructions
SP SP − 3
SP SP − 2 SP SP − 2 SP − 3 PC7 to PC0
Lower byte in
SP − 2 SP − 2 PC7 to PC0 SP − 2 PC15 to PC8
register pair
Upper byte in
SP − 1 SP − 1 PC15 to PC8 SP − 1 PSW
register pair
SP SP SP
Figure 2-5. Data to Be Restored from Stack Memory
POP rp RET instruction RETI instruction

instruction
Lower byte in
SP SP PC7 to PC0 SP PC7 to PC0
register pair
Upper byte in
SP + 1 SP + 1 PC15 to PC8 SP + 1 PC15 to PC8
register pair
SP SP + 2 SP SP + 2 SP + 2 PSW
SP SP + 3
2.2 General-Purpose Registers
The general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
Registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).

CHAPTER 2 REGISTERS
Figure 2-6. General-Purpose Register Configuration
(a) Absolute name
16-bit processing 8-bit processing
R7
RP3
R6
R5
RP2
R4
R3
RP1
R2
R1
RP0
R0
15 0 7 0
(b) Functional name
16-bit processing 8-bit processing
H
HL
L
D
DE
E
B
BC
C
A
AX
X
15 0 7 0

CHAPTER 2 REGISTERS
2.3 Special Function Registers (SFRs)
Unlike general-purpose registers, special function registers have their own functions and are allocated to the 256-
byte area FF00H to FFFFH.
A special function register can be manipulated, like a general-purpose register, by using operation, transfer, and
bit manipulation instructions. The bit units in which one register is to be manipulated (1, 8, and 16) differ depending
on the special function register type.
The bit unit for manipulation is specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
addressing an address, describe an even address.
For details of the special function registers, refer to the User's Manual of each product.

[MEMO]

CHAPTER 3 ADDRESSING
3.1 Addressing of Instruction Address
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 per byte) automatically according to the number of bytes of an instruction to be fetched each time
another instruction is executed. When a branch instruction is executed, the branch destination information is set in
the PC and branched by the following addressing (For details of each instruction, see CHAPTER 5 EXPLANATION
OF INSTRUCTIONS).
3.1.1 Relative addressing
[Function]
The value obtained by adding the 8-bit immediate data (displacement value: jdisp8) of an instruction code to
the first address of the following instruction is transferred to the program counter (PC) and program branches.
The displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
Thus, relative addressing causes a branch to an address within the range of –128 to +127, relative to the first
address of the next instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
... PC holds the first address
PC
of instruction next to
BR instruction.
+
15 8 7 6 0
α S
jdisp8
15 0
PC
When S = 0, all bits of α are 0.

When S = 1, all bits of α are 1.

3.1.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and program branches.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
The CALL !addr16 and BR !addr16 instructions can be used to branch to any address within the memory
spaces.
[Illustration]
In case of CALL !addr16 or BR !addr16 instruction
7 0
CALL or BR
Low addr.
High addr.
15 8 7 0
PC

3.1.3 Table indirect addressing
[Function]
Table contents (branch destination address) of a particular location, addressed by the immediate data of bits 1
to 5 of an instruction code are transferred to the program counter (PC), and program branches.
Table indirect addressing is performed when the CALLT [addr5] instruction is executed. This instruction
references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory
space.
[Illustration]
7 6 5 1 0
Instruction code 0 1 ta4 to 0 1
15 8 7 6 5 1 0
Effective address 0 0 0 0 0 0 0 0 0 1 0
7 Memory (table) 0
Low addr.
Effective address + 1 High addr.
15 8 7 0
PC

3.1.4 Register addressing
[Function]
Register pair (AX) contents specified with an instruction word are transferred to the program counter (PC) and
program branches.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7 0 7 0
rp A X
15 8 7 0
PC

3.2 Addressing of Operand Address
The following methods are available to specify the register and memory (addressing) which undergo manipulation
during instruction execution.
3.2.1 Direct addressing
[Function]
This addressing directly addresses a memory to be manipulated with immediate data in an instruction word.
[Operand format]
Operand Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 0 0 1 0 1 0 0 1 OP code
0 0 0 0 0 0 0 0 00H
1 1 1 1 1 1 1 0 FEH
[Illustration]
7 0
OP code
addr16 (lower)
addr16 (higher)
Memory

3.2.2 Short direct addressing
[Function]
This addressing directly addresses memory to be manipulated in the fixed space with the 8-bit data in an
instruction word.
This addressing is applied to the 256-byte fixed space of FE20H to FF1FH. An internal high-speed RAM and
special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H-FF1FH) to which short direct addressing is applied constitutes only part of the overall
SFR area. In this area, ports that are frequently accessed in a program and a compare register of the timer/event
counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is 20H to FFH, bit 8 of an effective address is set to 0. When it is 00H to 1FH, bit 8
is set to 1. See Illustration below.
[Operand format]
Operand Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code 1 1 1 1 0 1 0 1 OP code
0 0 1 1 0 0 0 0 30H (saddr-offset)
0 1 0 1 0 0 0 0 50H (immediate data)
[Illustration]
7 0
OP code
saddr-offset
Short direct memory

15 8 0
Effective
address 1 1 1 1 1 1 1 α
When 8-bit immediate data is 20H to FFH, α = 0.

When 8-bit immediate data is 00H to 1FH, α = 1.

3.2.3 Special function register (SFR) addressing
[Function]
This addressing is to address special function registers (SFRs) mapped to the memory with the 8-bit immediate
data in an instruction word.
This addressing is applied to the 240-byte spaces of FF00H to FFCFH and FFE0H to FFFFH. However, the
SFRs mapped at FF00H to FF1FH can also be accessed by means of short direct addressing.
[Operand format]
Operand Description
sfr Special function register name
MOV PM0, A; When selecting PM0 for sfr
Instruction code 1 1 1 0 0 1 1 1
0 0 1 0 0 0 0 0
[Illustration]
7 0
OP code
sfr-offset
SFR
15 8 7 0
Effective
1 1 1 1 1 1 1 1
address

3.2.4 Register addressing
[Function]
This addressing is to access a general-purpose register by specifying it as an operand. The general-purpose
register to be accessed is specified with a register specification code in an instruction code or function name.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits (register specification code) in the
instruction code.
[Operand format]
Operand Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A,
C, B, E, D, L, H, AX, BC, DE, and HL).
MOV A, C; When selecting the C register for r
0 0 1 0 0 1 0 1
Register specification code
INCW DE; When selecting the DE register pair for rp
Register specification code

3.2.5 Register indirect addressing
[Function]
This addressing is to address memory using the contents of the special register pair as an operand. The
register pair to be accessed is specified with the register pair specification code in an instruction code. This
addressing can be carried out for the entire memory space.
[Operand format]
Operand Description
 [DE], [HL]
MOV A, [DE]; When selecting register pair [DE]
[Illustration]
15 8 7 0
DE D E
Memory address
specified with
7 0 register pair DE
The contents of
the specified memory
address are transferred.
7 0

3.2.6 Based addressing
[Function]
This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of
the base register, i.e., the HL register pair. The addition is performed by expanding the offset data as a positive
number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for the entire memory
space.
[Operand format]
Operand Description
 [HL + byte]
MOV A, [HL+10H]; When setting “byte” to 10H
0 0 0 1 0 0 0 0
3.2.7 Stack addressing
[Function]
This addressing is to indirectly address the stack area with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, or RETURN
instructions is executed or when the register is saved/restored upon generation of an interrupt request.
Stack addressing can address the internal high-speed RAM area only.
In the case of PUSH DE

CHAPTER 4 INSTRUCTION SET
This chapter lists the instruction set of the 78K/0S Series. The instructions are common to all 78K/0S Series
products.

4.1 Operation
4.1.1 Operand representation and description formats

In the operand column of each instruction, an operand is described according to the description format for
operand representation of that instruction (for details, refer to the assembler specifications). When there are two or
more description methods, select one of them. Uppercase characters, #, !, $ and [ ] are keywords and must be
described as is. Each symbol has the following meaning.
• # : Immediate data • $ : Relative address

• ! : Absolute address • [ ] : Indirect address
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe #, !, $, or [ ].
For operand register description formats, r and rp, either functional names (X, A, C, etc.) or absolute names
(names in parentheses in the table below, R0, R1, R2, etc.) can be described.
Table 4-1. Operand Representation and Description Formats
Operand Description Format
r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

rp AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr Special function register symbol
saddr FE20H to FF1FH Immediate data or labels

saddrp FE20H to FF1FH Immediate data or labels (even addresses only)
addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
addr5 0040H to 007FH Immediate data or labels (even addresses only)
word 16-bit immediate data or label

byte 8-bit immediate data or label
bit 3-bit immediate data or label
Remark Refer to the User's Manual of each product for symbols of special function registers.

4.1.2 Description of operation column
A: A register; 8-bit accumulator

X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
4.1.3 Description of flag column
(Blank): Not affected

0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored

4.1.4 Description of clock column
The number of clock cycles during instruction execution is outlined as follows.

One instruction clock cycle is equal to one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
The operation list is shown below.

4.1.5 Operation list
Mnemonic Operand Byte Clock Operation Flag
Z AC CY
MOV r, #byte 3 6 r ← byte
saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A←r
Note 1
A, r 2 4
r←A
Note 1
r, A 2 4
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte × × ×
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A × × ×
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL + byte] 2 6 A ← (HL + byte)
[HL + byte], A 2 6 (HL + byte) ← A
XCH A, X 1 4 A↔X
A↔r
Note 2
A, r 2 6
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ sfr
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
A, [HL + byte] 2 8 A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).

Z AC CY
MOVW rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX ← rp
Note
AX, rp 1 4
rp ← AX
Note
rp, AX 1 4
AX ↔ rp
Note
XCHW AX, rp 1 8
ADD A, #byte 2 4 A, CY ← A + byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × ×
A, r 2 4 A, CY ← A + r × × ×
A, saddr 2 4 A, CY ← A + (saddr) × × ×
A, !addr16 3 8 A, CY ← A + (addr16) × × ×
A, [HL] 1 6 A, CY ← A + (HL) × × ×
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × ×
ADDC A, #byte 2 4 A, CY ← A + byte + CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × ×
A, r 2 4 A, CY ← A + r + CY × × ×
A, saddr 2 4 A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 8 A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 6 A, CY ← A + (HL) + CY × × ×
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × ×
SUB A, #byte 2 4 A, CY ← A – byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) – byte × × ×
A, r 2 4 A, CY ← A – r × × ×
A, saddr 2 4 A, CY ← A – (saddr) × × ×
A, !addr16 3 8 A, CY ← A – (addr16) × × ×
A, [HL] 1 6 A, CY ← A – (HL) × × ×
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) × × ×
Note Only when rp = BC, DE, or HL.
register (PCC).

Z AC CY
SUBC A, #byte 2 4 A, CY ← A – byte – CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY × × ×
A, r 2 4 A, CY ← A – r – CY × × ×
A, saddr 2 4 A, CY ← A – (saddr) – CY × × ×
A, !addr16 3 8 A, CY ← A – (addr16) – CY × × ×
A, [HL] 1 6 A, CY ← A – (HL) – CY × × ×
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY × × ×
AND A, #byte 2 4 A ← A∧byte ×
saddr, #byte 3 6 (saddr) ← (saddr)∧byte ×
A, r 2 4 A ← A∧r ×
A, saddr 2 4 A ← A∧(saddr) ×
A, !addr16 3 8 A ← A∧(addr16) ×
A, [HL] 1 6 A ← A∧(HL) ×
A, [HL + byte] 2 6 A ← A∧(HL + byte) ×
OR A, #byte 2 4 A ← A∨byte ×
saddr, #byte 3 6 (saddr) ← (saddr)∨byte ×
A, r 2 4 A ← A∨r ×
A, saddr 2 4 A ← A∨(saddr) ×
A, !addr16 3 8 A ← A∨(addr16) ×
A, [HL] 1 6 A ← A∨(HL) ×
A, [HL + byte] 2 6 A ← A∨(HL + byte) ×
XOR A, #byte 2 4 A ← A∨byte ×
saddr, #byte 3 6 (saddr) ← (saddr)∨byte ×
A, r 2 4 A ← A∨r ×
A, saddr 2 4 A ← A∨(saddr) ×
A, !addr16 3 8 A ← A∨(addr16) ×
A, [HL] 1 6 A ← A∨(HL) ×
A, [HL + byte] 2 6 A ← A∨(HL + byte) ×
CMP A, #byte 2 4 A – byte × × ×
saddr, #byte 3 6 (saddr) – byte × × ×
A, r 2 4 A–r × × ×
A, saddr 2 4 A – (saddr) × × ×
A, !addr16 3 8 A – (addr16) × × ×
A, [HL] 1 6 A – (HL) × × ×
A, [HL + byte] 2 6 A – (HL + byte) × × ×
register (PCC).

Z AC CY
ADDW AX, #word 3 6 AX, CY ← AX + word × × ×
SUBW AX, #word 3 6 AX, CY ← AX – word × × ×
CMPW AX, #word 3 6 AX – word × × ×
INC r 2 4 r←r+1 × ×
saddr 2 4 (saddr) ← (saddr) + 1 × ×
DEC r 2 4 r←r–1 × ×
saddr 2 4 (saddr) ← (saddr) – 1 × ×
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp – 1
ROR A, 1 1 2 (CY, A7 ← A0, Am–1 ← Am) × 1 ×
ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 ×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am–1 ← Am) × 1 ×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×
SET1 saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 × × ×
[HL].bit 2 10 (HL).bit ← 1
CLR1 saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 × × ×
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
×
_____
NOT1 CY 1 2 CY ← CY
CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,

PC ← addr16, SP ← SP – 2
CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,

PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP – 2
register (PCC).

Z AC CY
RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP), R R R

PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1
rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP – 2
POP PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R
rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
MOVW SP,AX 2 8 SP ← AX
AX,SP 2 6 AX ← SP
BR !addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
AX 1 6 PCH ← A, PCL ← X
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
BT saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
BF saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
DBNZ B, $addr16 2 6 B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode
register (PCC).

4.1.6 Instruction list by addressing
(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None
1st operand
Note
A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR
Note
ADDC XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP
Note
r MOV MOV INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV MOV DBNZ INC

ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16 MOV
PSW MOV MOV PUSH

POP
[DE] MOV
[HL] MOV
[HL + byte] MOV
Note Except r = A.

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Note
2nd operand #word AX rp saddrp SP None
1st operand
AX ADDW MOVW MOVW MOVW

SUBW XCHW
CMPW
Note
rp MOVW MOVW INCW
DECW
PUSH
POP
saddrp MOVW
SP MOVW
Note Only when rp = BC, DE, HL.
(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF
2nd operand $saddr None

1st operand
A.bit BT SET1
BF CLR1
sfr.bit BT SET1
BF CLR1
saddr.bit BT SET1
BF CLR1
PSW.bit BT SET1
BF CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, DBNZ
2nd operand AX !addr16 [addr5] $addr16

1st operand
Basic instructions BR CALL CALLT BR

BR BC
BNC
BZ
BNZ
Compound instructions DBNZ
(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

4.2 Instruction Codes
4.2.1 Description of instruction code table
r rp
R2 R1 R0 reg P1 P0 reg-pair
0 0 0 R0 X 0 0 RP0 AX
0 0 1 R1 A 0 1 RP1 BC
0 1 0 R2 C 1 0 RP2 DE
0 1 1 R3 B 1 1 RP3 HL
1 0 0 R4 E
1 0 1 R5 D
1 1 0 R6 L
1 1 1 R7 H
Bn: Immediate data corresponding to “bit”

Data: 8-bit immediate data corresponding to “byte”
Low/High byte: 16-bit immediate data corresponding to “word”
Saddr-offset: 16-bit address lower 8-bit offset data corresponding to “saddr”
Sfr-offset: sfr 16-bit address lower 8-bit offset data
Low/High addr: 16-bit immediate data corresponding to “addr16”
jdisp: Signed two's complement data (8 bits) of relative address distance between the start and branch
addresses of the next instruction
ta4 to 0: 5 bits of immediate data corresponding to “addr5”

4.2.2 Instruction code list
Mnemonic Operand Instruction Code
B1 B2 B3 B4
MOV r, #byte 0 0 0 0 1 0 1 0 1 1 1 1 R2 R1 R0 1 Data
saddr, #byte 1 1 1 1 0 1 0 1 Saddr-offset Data
sfr, #byte 1 1 1 1 0 1 1 1 Sfr-offset Data

Note 1
A, r 0 0 0 0 1 0 1 0 0 0 1 0 R2 R1 R0 1
Note 1
r, A 0 0 0 0 1 0 1 0 1 1 1 0 R2 R1 R0 1
A, saddr 0 0 1 0 0 1 0 1 Saddr-offset
saddr, A 1 1 1 0 0 1 0 1 Saddr-offset
A, sfr 0 0 1 0 0 1 1 1 Sfr-offset
sfr, A 1 1 1 0 0 1 1 1 Sfr-offset
A, !addr16 0 0 1 0 1 0 0 1 Low addr High addr
!addr16, A 1 1 1 0 1 0 0 1 Low addr High addr
PSW, #byte 1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 Data
A, PSW 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0
PSW, A 1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0
A, [DE] 0 0 1 0 1 0 1 1
[DE], A 1 1 1 0 1 0 1 1
A, [HL] 0 0 1 0 1 1 1 1
[HL], A 1 1 1 0 1 1 1 1
A, [HL + byte] 0 0 1 0 1 1 0 1 Data
[HL + byte], A 1 1 1 0 1 1 0 1 Data
XCH A, X 1 1 0 0 0 0 0 0
Note 2
A, r 0 0 0 0 1 0 1 0 0 0 0 0 R2 R1 R0 1
A, sfr 0 0 0 0 0 1 1 1 Sfr-offset
A, [DE] 0 0 0 0 1 0 1 1
A, [HL] 0 0 0 0 1 1 1 1
A, [HL + byte] 0 0 0 0 1 1 0 1 Data
MOVW rp, #word 1 1 1 1 P 1 P0 0 0 Low byte High byte
AX, saddrp 1 1 0 1 0 1 1 0 Saddr-offset
saddrp, AX 1 1 1 0 0 1 1 0 Saddr-offset
Note 3
AX, rp 1 1 0 1 P1 P0 0 0
Note 3
rp, AX 1 1 1 0 P1 P0 0 0
Note 3
XCHW AX, rp 1 1 0 0 P1 P0 0 0
Notes 1. Except r = A.
2. Except r = A, X.
3. Only when rp = BC, DE, or HL.

B1 B2 B3 B4
ADD A, #byte 1 0 0 0 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 1 0 0 0 R2 R1 R0 1
A, [HL] 1 0 0 0 1 1 1 1
A, [HL + byte] 1 0 0 0 1 1 0 1 Data
ADDC A, #byte 1 0 1 0 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 1 0 1 0 R2 R1 R0 1
A, [HL] 1 0 1 0 1 1 1 1
A, [HL + byte] 1 0 1 0 1 1 0 1 Data
SUB A, #byte 1 0 0 1 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 1 0 0 1 R2 R1 R0 1
A, [HL] 1 0 0 1 1 1 1 1
A, [HL + byte] 1 0 0 1 1 1 0 1 Data
SUBC A, #byte 1 0 1 1 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 1 0 1 1 R2 R1 R0 1
A, [HL] 1 0 1 1 1 1 1 1
A, [HL + byte] 1 0 1 1 1 1 0 1 Data
AND A, #byte 0 1 1 0 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 0 1 1 0 R2 R1 R0 1
A, [HL] 0 1 1 0 1 1 1 1
A, [HL + byte] 0 1 1 0 1 1 0 1 Data

B1 B2 B3 B4
OR A, #byte 0 1 1 1 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 0 1 1 1 R2 R1 R0 1
A, [HL] 0 1 1 1 1 1 1 1
A, [HL + byte] 0 1 1 1 1 1 0 1 Data
XOR A, #byte 0 1 0 0 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 0 1 0 0 R2 R1 R0 1
A, [HL] 0 1 0 0 1 1 1 1
A, [HL + byte] 0 1 0 0 1 1 0 1 Data
CMP A, #byte 0 0 0 1 0 0 1 1 Data
A, r 0 0 0 0 1 0 1 0 0 0 0 1 R2 R1 R0 1
A, [HL] 0 0 0 1 1 1 1 1
A, [HL + byte] 0 0 0 1 1 1 0 1 Data
ADDW AX, #word 1 1 0 1 0 0 1 0 Low byte High byte
SUBW AX, #word 1 1 0 0 0 0 1 0 Low byte High byte
CMPW AX, #word 1 1 1 0 0 0 1 0 Low byte High byte
INC r 0 0 0 0 1 0 1 0 1 1 0 0 R2 R1 R0 1
saddr 1 1 0 0 0 1 0 1 Saddr-offset
DEC r 0 0 0 0 1 0 1 0 1 1 0 1 R2 R1 R0 1
saddr 1 1 0 1 0 1 0 1 Saddr-offset
INCW rp 1 0 0 0 P 1 P0 0 0
DECW rp 1 0 0 1 P 1 P0 0 0
ROR A, 1 0 0 0 0 0 0 0 0
ROL A, 1 0 0 0 1 0 0 0 0
RORC A, 1 0 0 0 0 0 0 1 0
ROLC A, 1 0 0 0 1 0 0 1 0

B1 B2 B3 B4
SET1 saddr.bit 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 1 0 1 0 Saddr-offset
sfr.bit 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 0 1 1 0 Sfr-offset
A.bit 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 0 0 1 0
PSW.bit 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 1 0 1 0 0 0 0 1 1 1 1 0
[HL].bit 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 1 1 1 0
CLR1 saddr.bit 0 0 0 0 1 0 1 0 1 B 2 B1 B0 1 0 1 0 Saddr-offset
sfr.bit 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 0 1 1 0 Sfr-offset
A.bit 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 0 0 1 0
PSW.bit 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 1 0 1 0 0 0 0 1 1 1 1 0
[HL].bit 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 1 1 1 0
SET1 CY 0 0 0 1 0 1 0 0
CLR1 CY 0 0 0 0 0 1 0 0
NOT1 CY 0 0 0 0 0 1 1 0
CALL !addr16 0 0 1 0 0 0 1 0 Low addr High addr
CALLT [addr5] 0 1 ta4 to 0 0
RET 0 0 1 0 0 0 0 0
RETI 0 0 1 0 0 1 0 0
PUSH PSW 0 0 1 0 1 1 1 0
rp 1 0 1 0 P1 P0 1 0
POP PSW 0 0 1 0 1 1 0 0
rp 1 0 1 0 P1 P0 0 0
MOVW SP, AX 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0
AX, SP 1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0
BR !addr16 1 0 1 1 0 0 1 0 Low addr High addr
$addr16 0 0 1 1 0 0 0 0 jdisp
AX 1 0 1 1 0 0 0 0
BC $addr16 0 0 1 1 1 0 0 0 jdisp
BNC $addr16 0 0 1 1 1 0 1 0 jdisp
BZ $addr16 0 0 1 1 1 1 0 0 jdisp
BNZ $addr16 0 0 1 1 1 1 1 0 jdisp
BT saddr.bit, $addr16 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 1 0 0 0 Saddr-offset jdisp
sfr.bit, $addr16 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 0 1 0 0 Sfr-offset jdisp
A.bit, $addr16 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 0 0 0 0 jdisp
PSW.bit, $addr16 0 0 0 0 1 0 1 0 1 B2 B 1 B 0 1 0 0 0 0 0 0 1 1 1 1 0 jdisp

B1 B2 B3 B4
BF saddr.bit, $addr16 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 1 0 0 0 Saddr-offset jdisp
sfr.bit, $addr16 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 0 1 0 0 Sfr-offset jdisp
A.bit, $addr16 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 0 0 0 0 jdisp
PSW.bit, $addr16 0 0 0 0 1 0 1 0 0 B2 B 1 B 0 1 0 0 0 0 0 0 1 1 1 1 0 jdisp
DBNZ B, $addr16 0 0 1 1 0 1 1 0 jdisp
C, $addr16 0 0 1 1 0 1 0 0 jdisp
saddr, $addr16 0 0 1 1 0 0 1 0 Saddr-offset jdisp
NOP 0 0 0 0 1 0 0 0
EI 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
DI 0 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
HALT 0 0 0 0 1 1 0 0
STOP 0 0 0 0 1 1 1 0

CHAPTER 5 EXPLANATION OF INSTRUCTIONS
This chapter explains the instructions of 78K/0S Series. Each instruction is described in the unit of mnemonic,
including description of multiple operands.
The basic configuration of instruction descriptions is shown on the next page.
For the number of instruction bytes and operation codes, refer to CHAPTER 4 INSTRUCTION SET.
All the instructions are common to 78K/0S Series products.

DESCRIPTION EXAMPLE
Mnemonic Full name
Move
MOV
Byte Data Transfer
Meaning of instruction
[Instruction format] MOV dst, src: Indicates the basic description format of the instruction.
[Operation] dst ← src: Indicates instruction operation using symbols.
[Operand] Indicates operands that can be specified with this instruction. Refer to 4.1 Operation
for a description of each operand symbol.
Mnemonic Operand (dst, src) Mnemonic Operand (dst, src)
MOV r, #byte MOV A, PSW
A, saddr [HL], A
saddr, A A, [HL + byte]
PSW, #byte [HL + C], A
[Flag] Indicates the operation of the flag that changes by instruction execution.
Each flag operation symbol is shown in the legend.
Z AC CY
Legend
Symbol Description
Blank Unchanged
0 Cleared to 0
1 Set to 1
× Set or cleared according to the result
R Previously saved value is restored
[Description] Describes the instruction operation in detail.

• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination
operand (dst) specified by the 1st operand.
MOV A, #4DH; 4DH is transferred to A register.

5.1 8-Bit Data Transfer Instructions
The following instructions are 8-bit data transfer instructions.
MOV ... 60
XCH ... 61

Move
MOV Byte Data Transfer
[Instruction format] MOV dst, src
[Operation] dst ← src
[Operand]
MOV r, #byte MOV !addr16, A
saddr, #byte PSW, #byte
sfr, #byte A, PSW

Note
A, r PSW, A
Note
r, A A, [DE]
A, saddr [DE], A
saddr, A A, [HL]
A, sfr [HL], A
sfr, A A, [HL + byte]
A, !addr16 [HL + byte], A
Note Except r = A
[Flag]
PSW, #byte and PSW, A All other operand
operands combinations
Z AC CY Z AC CY
× × ×
[Description]
• No interrupts are acknowledged between the “MOV PSW, #byte” instruction or the “MOV PSW, A” instruction
and the subsequent instruction.
MOV A, #4DH; 4DH is transferred to A register.

Exchange
XCH Byte Data Exchange
[Instruction format] XCH dst, src
[Operation] dst ↔ src
[Operand]
Mnemonic Operand (dst, src)
XCH A, X
Note
A, r
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL + byte]
Note Except r = A, X
[Flag]
Z AC CY
[Description]
• The 1st and 2nd operand contents are exchanged.
XCH A, 0FEBCH; The A register contents and address FEBCH contents are exchanged.

5.2 16-Bit Data Transfer Instructions
The following instructions are 16-bit data transfer instructions.
MOVW ... 63
XCHW ... 64

Move Word
MOVW Word Data Transfer
[Instruction format] MOVW dst, src
[Operand]
MOVW rp, #word
AX, saddrp
saddrp, AX
Note
AX, rp
Note
rp, AX
Note Only when rp = BC, DE or HL
[Flag]
Z AC CY
[Description]
MOVW AX, HL; The HL register contents are transferred to the AX register.
[Caution]
Only an even address can be specified to saddrp. An odd address cannot be specified.

Exchange Word
XCHW Word Data Exchange
[Instruction format] XCHW dst, src
[Operation] dst ↔ src
[Operand]

Note
XCHW AX, rp
Note Only when rp = BC, DE or HL
[Flag]
Z AC CY
[Description]
• The 1st and 2nd operand contents are exchanged.
XCHW AX, BC; The memory contents of AX register are exchanged with those of the BC register.

5.3 8-Bit Operation Instructions
The following are 8-bit operation instructions.
ADD ... 66
ADDC ... 67
SUB ... 68
SUBC ... 69
AND ... 70
OR ... 71
XOR ... 72
CMP ... 73

Add
ADD Byte Data Addition
[Instruction format] ADD dst, src
[Operation] dst, CY ← dst + src
[Operand]
ADD A, #byte ADD A, !addr16
saddr, #byte A, [HL]
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
× × ×
[Description]
• The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified
with the 2nd operand and the result is stored in the CY flag and the destination operand (dst).
• If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
• If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).
• If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
ADD CR10, #56H; 56H is added to the CR10 register and the result is stored in the CR10 register.

Add with Carry

ADDC Addition of Byte Data with Carry
[Instruction format] ADDC dst, src
[Operation] dst, CY ← dst + src + CY
[Operand]
ADDC A, #byte ADDC A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
× × ×
[Description]
• The destination operand (dst) specified with the 1st operand, the source operand (src) specified with the 2nd
operand, and the CY flag are added and the result is stored in the destination operand (dst) and the CY flag.
The CY flag is added to the least significant bit. This instruction is mainly used to add two or more bytes.
• If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).
• If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
ADDC A, [HL]; The A register contents, the contents at address (HL register), and the CY flag are added and
the result is stored in the A register.

Subtract
SUB Byte Data Subtraction
[Instruction format] SUB dst, src
[Operation] dst, CY ← dst – src
[Operand]
SUB A, #byte SUB A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
× × ×
[Description]
• The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst)
specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination
operand (dst).
• If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
• If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
• If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag
is cleared (0).
SUB A, D; The D register is subtracted from the A register and the result is stored in the A register.

Subtract with Carry

SUBC Subtraction of Byte Data with Carry
[Instruction format] SUBC dst, src
[Operation] dst, CY ← dst – src – CY
[Operand]
SUBC A, #byte SUBC A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
× × ×
[Description]
• The source operand (src) specified with the 2nd operand and the CY flag are subtracted from the destination
operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst).
The CY flag is subtracted from the least significant bit. This instruction is mainly used for subtraction of two
or more bytes.
(0).
is cleared (0).
SUBC A, [HL]; The (HL register) address contents and the CY flag are subtracted from the A register and the
result is stored in the A register.

And
AND Logical Product of Byte Data
[Instruction format] AND dst, src
[Operation] dst ← dst ∧ src
[Operand]
AND A, #byte AND A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
[Description]
• The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the
2nd operand are ANDed bit wise, and the result is stored in the destination operand (dst).
• If the logical product shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
AND 0FEBAH, #11011100B; The FEBAH contents and 11011100B are ANDed bit wise and the result is stored
at FEBAH.

Or
OR Logical Sum of Byte Data
[Instruction format] OR dst, src
[Operation] dst ← dst ∨ src
[Operand]
OR A, #byte OR A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
[Description]
2nd operand are ORed bit wise, and the result is stored in the destination operand (dst).
• If the logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
OR A, 0FE98H; The A register and FE98H are ORed bit wise and the result is stored in the A register.

Exclusive Or
XOR Exclusive Logical Sum of Byte Data
[Instruction format] XOR dst, src
[Operation] dst ← dst ∨ src
[Operand]
XOR A, #byte XOR A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
[Description]
2nd operand are XORed bit wise, and the result is stored in the destination operand (dst).
Logical negation of all bits of the destination operand (dst) is possible with this instruction by selecting #0FFH
for the source operand (src).
• If the exclusive logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is
cleared (0).
XOR A, L; The A and L registers are XORed bit wise and the result is stored in the A register.

Compare
CMP Byte Data Comparison
[Instruction format] CMP dst, src
[Operation] dst – src
[Operand]
CMP A, #byte CMP A, !addr16
A, r A, [HL + byte]
A, saddr
[Flag]
Z AC CY
× × ×
[Description]
specified with the 1st operand.
The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.
• If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
(0).
is cleared (0).
CMP 0FE38H, #38H; 38H is subtracted from the contents at address FE38H and only the Z, AC, and CY flags
are changed (comparison of contents at address FE38H and the immediate data).

5.4 16-Bit Operation Instructions
The following are 16-bit operation instructions.
ADDW ... 75
SUBW ... 76
CMPW ... 77

Add Word
ADDW Word Data Addition
[Instruction format] ADDW dst, src
[Operation] dst, CY ← dst + src
[Operand]
ADDW AX, #word
[Flag]
Z AC CY
× × ×
[Description]
• The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified
with the 2nd operand and the result is stored in the destination operand (dst).
• If the addition generates a carry from bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
• As a result of addition, the AC flag becomes undefined.
ADDW AX, #0ABCDH; ABCDH is added to the AX register and the result is stored in the AX register.

Subtract Word
SUBW Word Data Subtraction
[Instruction format] SUBW dst, src
[Operation] dst, CY ← dst – src
[Operand]
SUBW AX, #word
[Flag]
Z AC CY
× × ×
[Description]
specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination
operand (dst).
(0).
• As a result of subtraction, the AC flag becomes undefined.
SUBW AX, #0ABCDH; ABCDH is subtracted from the AX register contents and the result is stored in the AX
register.

Compare Word
CMPW Word Data Comparison
[Instruction format] CMPW dst, src
[Operation] dst – src
[Operand]
CMPW AX, #word
[Flag]
Z AC CY
× × ×
[Description]
specified with the 1st operand.
The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.
• If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
(0).
• As a result of subtraction, the AC flag becomes undefined.
CMPW AX, #0ABCDH; ABCDH is subtracted from the AX register and only the Z, AC, and CY flags are
changed (comparison of the AX register and the immediate data).

5.5 Increment/Decrement Instructions
The following are increment/decrement instructions.
INC ... 79
DEC ... 80
INCW ... 81
DECW ... 82

Increment
INC Byte Data Increment
[Instruction format] INC dst
[Operation] dst ← dst + 1
[Operand]
Mnemonic Operand (dst)
INC r
saddr
[Flag]
Z AC CY
× ×
[Description]
• The destination operand (dst) contents are incremented by only one.
• If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
• If the increment generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
• Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are not
changed (to hold the CY flag contents in multiple-byte operation).
INC B; The B register is incremented.

Decrement
DEC Byte Data Decrement
[Instruction format] DEC dst
[Operation] dst ← dst – 1
[Operand]
DEC r
saddr
[Flag]
Z AC CY
× ×
[Description]
• The destination operand (dst) contents are decremented by only one.
• If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
• If the decrement generates a carry from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
• Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are
not changed (to hold the CY flag contents in multiple-byte operation).
• If dst is the B or C register or saddr, and it is not desired to change the AC and CY flag contents, the DBNZ
instruction can be used.
DEC 0FE92H ; The contents at address FE92H are decremented.

Increment Word
INCW Word Data Increment
[Instruction format] INCW dst
[Operation] dst ← dst + 1
[Operand]
INCW rp
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents are incremented by only one.
• Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC,
and CY flag contents are not changed.
INCW HL ; The HL register is incremented.

Decrement Word
DECW Word Data Decrement
[Instruction format] DECW dst
[Operation] dst ← dst – 1
[Operand]
DECW rp
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents are decremented by only one.
• Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z,
AC, and CY flag contents are not changed.
DECW DE ; The DE register is decremented.

5.6 Rotate Instructions
The following are rotate instructions.
ROR ... 84
ROL ... 85
RORC ... 86
ROLC ... 87

Rotate Right
ROR Byte Data Rotation to the Right
[Instruction format] ROR dst, cnt
[Operation] (CY, dst7 ← dst0, dstm–1 ← dstm) × one time
[Operand]
Mnemonic Operand (dst, cnt)
ROR A, 1
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents specified with the 1st operand are rotated to the right just once.
• The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag.
CY 7 0
ROR A, 1; The A register contents are rotated one bit to the right.

Rotate Left
ROL Byte Data Rotation to the Left
[Instruction format] ROL dst, cnt
[Operation] (CY, dst0 ← 0dst7, dstm+1 ← dstm) × one time
[Operand]
ROL A, 1
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents specified with the 1st operand are rotated to the left just once.
• The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag.
CY 7 0
ROL A, 1; The A register contents are rotated to the left by one bit.

Rotate Right with Carry

RORC Byte Data Rotation to the Right with Carry
[Instruction format] RORC dst, cnt
[Operation] (CY ← dst0, dst7 ← CY, dstm–1 ← dstm) × one time
[Operand]
RORC A, 1
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents specified with the 1st operand are rotated just once to the right
including the CY flag.
CY 7 0
RORC A, 1; The A register contents are rotated to the right by one bit including the CY flag.

Rotate Left with Carry

ROLC Byte Data Rotation to the Left with Carry
[Instruction format] ROLC dst, cnt
[Operation] (CY ← dst7, dst0 ← CY, dstm+1 ← dstm) × one time
[Operand]
ROLC A, 1
[Flag]
Z AC CY
[Description]
• The destination operand (dst) contents specified with the 1st operand are rotated just once to the left
including the CY flag.
CY 7 0
ROLC A, 1; The A register contents are rotated to the left by one bit including the CY flag.

5.7 Bit Manipulation Instructions
The following are bit manipulation instructions.
SET1 ... 89
CLR1 ... 90
NOT1 ... 91

Set Single Bit (Carry Flag)

SET1 1 Bit Data Set
[Instruction format] SET1 dst
[Operation] dst ← 1
[Operand]
SET1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
[Flag]
dst = PSW.bit dst = CY In all other cases

Z AC CY Z AC CY Z AC CY
× × × 1
[Description]
• The destination operand (dst) is set (1).
• When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1).
SET1 0FE55H.1; Bit 1 of FE55H is set (1).

Clear Single Bit (Carry Flag)

CLR1 1 Bit Data Clear
[Instruction format] CLR1 dst
[Operation] dst ← 0
[Operand]
CLR1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
[Flag]
dst = PSW.bit dst = CY In all other cases

Z AC CY Z AC CY Z AC CY
× × × 0
[Description]
• The destination operand (dst) is cleared (0).
• When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0).
CLR1 P3.7; Bit 7 of port 3 is cleared (0).

Not Single Bit (Carry Flag)

NOT1 1 Bit Data Logical Negation
[Instruction format] NOT1 dst
_______
[Operation] dst ← dst
[Operand]
NOT1 CY
[Flag]
Z AC CY
[Description]
• The CY flag is inverted.
NOT1 CY; The CY flag is inverted.

5.8 CALL/RETURN Instructions
The following are call/return instructions.
CALL ... 93
CALLT ... 94
RET ... 95
RETI ... 96

Call
CALL Subroutine Call (16 Bit Direct)
[Instruction format] CALL target
[Operation] (SP – 1) ← (PC + 3)H,

(SP – 2) ← (PC + 3)L,
SP ← SP – 2,
PC ← target
[Operand]
Mnemonic Operand (target)
CALL !addr16
[Flag]
Z AC CY
[Description]
• This is a subroutine call with a 16-bit absolute address or a register indirect address.
• The next instruction’s start address (PC + 3) is saved in the stack and is branched to the address specified
with the target operand (target).
CALL !3059H; Subroutine call to 3059H

Call Table
CALLT Subroutine Call (Call Table Reference)
[Instruction format] CALLT [addr5]
[Operation] (SP – 1) ← (PC + 1)H,

(SP – 2) ← (PC + 1)L,
SP ← SP – 2,
PCH ← (00000000,addr5 + 1)
PCL ← (00000000,addr5)
[Operand]
Mnemonic Operand ([addr5])
CALLT [addr5]
[Flag]
Z AC CY
[Description]
• This is a subroutine call for call table reference.
• The next instruction’s start address (PC + 1) is saved in the stack and is branched to the address indicated
with the word data of a call table (the higher 8 bits of address are fixed to 00000000B and the following 5 bits
are specified with addr5).
CALLT [40H]; Subroutine call to the addresses indicated by word data of 0040H and 0041H.

Return
RET Return from Subroutine
[Instruction format] RET
[Operation] PCL ← (SP),

PCH ← (SP + 1),
SP ← SP + 2
[Operand]
None
[Flag]
Z AC CY
[Description]
• This is a return instruction from the subroutine call made with the CALL and CALLT instructions.
• The word data saved in the stack returns to the PC, and the program returns from the subroutine.

Return from Interrupt

RETI Return from Hardware Vectored Interrupt
[Instruction format] RETI
[Operation] PCL ← (SP),

PCH ← (SP + 1),
PSW ← (SP + 2),
SP ← SP + 3,
NMIS ← 0
[Operand]
None
[Flag]
Z AC CY
R R R
[Description]
• This is a return instruction from the vectored interrupt.
• The data saved in the stack returns to the PC and PSW, and the program returns from the interrupt service
routine.
• None of interrupts are acknowledged between this instruction and the next instruction to be executed.
• The NMIS flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the RETI
instruction.
[Caution]
When the return from non-maskable interrupt servicing is performed by an instruction other than the RETI
instruction, the NMIS flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts) can
be acknowledged.

5.9 Stack Manipulation Instructions
The following are stack manipulation instructions.
PUSH ... 98
POP ... 99
MOVW SP, AX ... 100
MOVW AX, SP ... 100

Push
PUSH Push
[Instruction format] PUSH src
[Operation] When src = rp When src = PSW

(SP – 1) ← srcH, (SP – 1) ← src
(SP – 2) ← srcL, SP ← SP − 1
SP ←SP − 2
[Operand]
Mnemonic Operand (src)
PUSH PSW
rp
[Flag]
Z AC CY
[Description]
• The data of the register specified with the source operand (src) is saved in the stack.
PUSH AX; AX register contents are saved in the stack.

Pop
POP Pop
[Instruction format] POP dst
[Operation] When dst = rp When dst = PSW

dstL ← (SP), dst ← (SP)
dstH ← (SP + 1), SP ← SP + 1
SP ← SP + 2
[Operand]
POP PSW
rp
[Flag]
dst = rp PSW
Z AC CY Z AC CY
R R R
[Description]
• Data is returned from the stack to the register specified with the destination operand (dst).
• When the operand is PSW, each flag is replaced with stack data.
• No interrupts are acknowledged between the POP PSW instruction and the subsequent instruction.
POP AX; The stack data is returned to the AX register.

MOVW SP, AX Move Word

Word Data Transfer with Stack Pointer
MOVW AX, SP
[Instruction format] MOVW dst, src
[Operand]
MOVW SP, AX
AX, SP
[Flag]
Z AC CY
[Description]
• This is an instruction to manipulate the stack pointer contents.
• The source operand (src) specified with the 2nd operand is stored in the destination operand (dst) specified
with the 1st operand.
MOVW SP, AX; AX register contents are stored in the stack pointer.

5.10 Unconditional Branch Instruction
The following is an unconditional branch instruction.
BR ... 102

Branch
BR Unconditional Branch
[Instruction format] BR target
[Operation] PC ← target
[Operand]
Mnemonic Operand (target)
BR !addr16
AX
$addr16
[Flag]
Z AC CY
[Description]
• This is an instruction to branch unconditionally.
• The word data of the target address operand (target) is transferred to PC and program branches.
BR AX; The AX register contents are regarded as an address to which the program branches.

5.11 Conditional Branch Instructions
The following are conditional branch instructions.
BC ... 104
BNC ... 105
BZ ... 106
BNZ ... 107
BT ... 108
BF ... 109
DBNZ ... 110

Branch if Carry
BC Conditional Branch with Carry Flag (CY = 1)
[Instruction format] BC $addr16
[Operation] PC ← PC + 2 + jdisp8 if CY = 1
[Operand]
Mnemonic Operand ($addr16)
BC $addr16
[Flag]
Z AC CY
[Description]
• When CY = 1, program branches to the address specified with the operand.
When CY = 0, no processing is carried out and the subsequent instruction is executed.
BC $300H; When CY = 1, program branches to 0300H (with the start of this instruction set in the range of
addresses 027FH to 037EH).

Branch if Not Carry

BNC Conditional Branch with Carry Flag (CY = 0)
[Instruction format] BNC $addr16
[Operation] PC ← PC + 2 + jdisp8 if CY = 0
[Operand]
BNC $addr16
[Flag]
Z AC CY
[Description]
• When CY = 0, program branches to the address specified with the operand.
When CY = 1, no processing is carried out and the subsequent instruction is executed.
BNC $300H; When CY = 0, program branches to 0300H (with the start of this instruction set in the range of
addresses 027FH to 037EH).

Branch if Zero
BZ Conditional Branch with Zero Flag (Z = 1)
[Instruction format] BZ $addr16
[Operation] PC ← PC + 2 + jdisp8 if Z = 1
[Operand]
BZ $addr16
[Flag]
Z AC CY
[Description]
• When Z = 1, program branches to the address specified with the operand.
When Z = 0, no processing is carried out and the subsequent instruction is executed.
DEC B
BZ $3C5H; When the B register is 0, program branches to 03C5H (with the start of this instruction set in the
range of addresses 0344H to 0443H).

Branch if Not Zero

BNZ Conditional Branch with Zero Flag (Z = 0)
[Instruction format] BNZ $addr16
[Operation] PC ← PC + 2 + jdisp8 if Z = 0
[Operand]
BNZ $addr16
[Flag]
Z AC CY
[Description]
• When Z = 0, program branches to the address specified with the operand.
When Z = 1, no processing is carried out and the subsequent instruction is executed.
CMP A, #55H
BNZ $0A39H; If the A register is not 0055H, program branches to 0A39H (with the start of this instruction set in
the range of addresses 09B8H to 0AB7H).

Branch if True
BT Conditional Branch by Bit Test (Byte Data Bit = 1)
[Instruction format] BT bit, $addr16
[Operation] PC ← PC + b + jdisp8 if bit = 1
[Operand]
Mnemonic Operand (bit, $addr16) b (Number of bytes)
BT saddr.bit, $addr16 4
sfr.bit, $addr16 4
A.bit, $addr16 3
PSW.bit, $addr16 4
[Flag]
Z AC CY
[Description]
• If the 1st operand (bit) contents have been set (1), program branches to the address specified with the 2nd
operand ($addr16).
If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent
instruction is executed.
BT 0FE47H.3, $55CH; When bit 3 at address FE47H is 1, program branches to 055CH (with the start of this
instruction set in the range of addresses 04DAH to 05D9H).

Branch if False
BF Conditional Branch by Bit Test (Byte Data Bit = 0)
[Instruction format] BF bit, $addr16
[Operation] PC ← PC + b + jdisp8 if bit = 0
[Operand]
Mnemonic Operand (bit, $addr16) b (Number of bytes)
BF saddr.bit, $addr16 4
sfr.bit, $addr16 4
A.bit, $addr16 3
PSW.bit, $addr16 4
[Flag]
Z AC CY
[Description]
• If the 1st operand (bit) contents have been cleared (0), program branches to the address specified with the
2nd operand ($addr16).
If the 1st operand (bit) contents have not been cleared (0), no processing is carried out and the subsequent
instruction is executed.
BF P2.2, $1549H; When bit 2 of port 2 is 0, program branches to address 1549H (with the start of this instruction
set in the range of addresses 14C6H to 15C5H).

Decrement and Branch if Not Zero

DBNZ Conditional Loop (R1 ≠ 0)
[Instruction format] DBNZ dst, $addr16
[Operation] dst ← dst – 1,

then PC ← PC + b + jdisp16 if dst R1 ≠ 0
[Operand]
Mnemonic Operand (dst, $addr16) b (Number of bytes)
DBNZ B, $addr16 2
C, $addr16 2
saddr, $addr16 3
[Flag]
Z AC CY
[Description]
• One is subtracted from the destination operand (dst) contents specified with the 1st operand and the
subtraction result is stored in the destination operand (dst).
• If the subtraction result is not 0, program branches to the address indicated with the 2nd operand ($addr16).
When the subtraction result is 0, no processing is carried out and the subsequent instruction is executed.
• The flag remains unchanged.
DBNZ B, $1215H; The B register contents are decremented. If the result is not 0, program branches to 1215H
(with the start of this instruction set in the range of addresses 1194H to 1293H).

5.12 CPU Control Instructions
The following are CPU control instructions.
NOP ... 112

EI ... 113
DI ... 114
HALT ... 115
STOP ... 116

No Operation
NOP No Operation
[Instruction format] NOP
[Operation] no operation
[Operand]
None
[Flag]
Z AC CY
[Description]
• No processing is performed and only time is consumed.

Enable Interrupt
EI Interrupt Enabled
[Instruction format] EI
[Operation] IE ← 1
[Operand]
None
[Flag]
Z AC CY
[Description]
• The maskable interrupt acknowledge-enable status is set (by setting the interrupt enable flag (IE) (1)).
• Interrupts are acknowledged immediately after this instruction is executed.
• If this instruction is executed, vectored interrupt acknowledgment with another source can be disabled. For
details, refer to "Interrupt Functions" in the User's Manual of each product.

Disable Interrupt
DI Interrupt Disabled
[Instruction format] DI
[Operation] IE ← 0
[Operand]
None
[Flag]
Z AC CY
[Description]
• Maskable interrupt acknowledgment with vectored interrupt is disabled (with the interrupt enable flag (IE)
cleared (0)).
• No interrupts are acknowledged between this instruction and the subsequent instruction.
• For details of interrupt servicing, refer to "Interrupt Functions" in the User's Manual of each product.

Halt
HALT HALT Mode Set
[Instruction format] HALT
[Operation] Set HALT Mode
[Operand]
None
[Flag]
Z AC CY
[Description]
• This instruction is used to set the HALT mode to stop the CPU operation clock. Total power consumption of
the system can be reduced with intermittent operations through combination with the normal operation mode.

Stop
STOP Stop Mode Set
[Instruction format] STOP
[Operation] Set STOP Mode
[Operand]
None
[Flag]
Z AC CY
[Description]
• This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole
system. Power dissipation can be minimized to an ultra-low leakage current level only.

APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION)
[8-bit data transfer instructions] [Bit manipulation instructions]
MOV ... 60 SET1 ... 89

XCH ... 61 CLR1 ... 90
NOT1 ... 91
[16-bit data transfer instructions]
[Call/return instructions]
MOVW ... 63
XCHW ... 64 CALL ... 93
CALLT ... 94
[8-bit operation instructions] RET ... 95
RETI ... 96
ADD ... 66
ADDC ... 67 [Stack manipulation instructions]
SUB ... 68
SUBC ... 69 PUSH ... 98
AND ... 70 POP ... 99
OR ... 71 MOVW SP, AX ... 100
XOR ... 72 MOVW AX, SP ... 100
CMP ... 73
[Unconditional branch instruction]
[16-bit operation instructions]
BR ... 102
ADDW ... 75
SUBW ... 76 [Conditional branch instructions]
CMPW ... 77
BC ... 104
[Increment/decrement instructions] BNC ... 105
BZ ... 106
INC ... 79 BNZ ... 107
DEC ... 80 BT ... 108
INCW ... 81 BF ... 109
DECW ... 82 DBNZ ... 110
[Rotate instructions] [CPU control instructions]
ROR ... 84 NOP ... 112

ROL ... 85 EI ... 113
RORC ... 86 DI ... 114
ROLC ... 87 HALT ... 115
STOP ... 116

[MEMO]

APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)
[A] [M]
ADD ... 66 MOV ... 60

ADDC ... 67 MOVW ... 63
ADDW ... 75 MOVW AX, SP ... 100
AND ... 70 MOVW SP, AX ... 100
[B] [N]
BC ... 104 NOP ... 112

BF ... 109 NOT1 ... 91
BNC ... 105
BNZ ... 107 [O]
BR ... 102
BT ... 108 OR ... 71
BZ ... 106
[P]
[C]
POP ... 99
CALL ... 93 PUSH ... 98
CALLT ... 94
CLR1 ... 90 [R]
CMP ... 73
CMPW ... 77 RET ... 95
RETI ... 96
[D] ROL ... 85
ROLC ... 87
DBNZ ... 110 ROR ... 84
DEC ... 80 RORC ... 86
DECW ... 82
DI ... 114 [S]
[E] SET1 ... 89

STOP ... 116
EI ... 113 SUB ... 68
SUBC ... 69
[H] SUBW ... 76
HALT ... 115 [X]
[I] XCH ... 61

XCHW ... 64
INC ... 79 XOR ... 72
INCW ... 81

[MEMO]

APPENDIX C REVISION HISTORY
A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the
revision was applied.
Edition Contents Applied to:
2nd Addition of the following target products Throughout

µPD789026, 789407, 789417, 789800, and 789806Y Subseries
Modification of the format of the table of the internal data memory space of the CHAPTER 1 MEMORY
78K/0S Series products SPACE
3rd Addition of the following target products Throughout

µPD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167,
789177, 789197AY, 789217AY, 789407A, 789417A, and 789842 Subseries
Deletion of the following target products

µPD789407, 789417, and 789806Y Subseries
Modification of MOV PSW, #byte instruction code CHAPTER 4 INSTRUCTION

SET
Modification of MOVW rp, AX instruction code
Modification of XOR A, r instruction code
Modification of CMP A, r instruction code

[MEMO]

Facsimile Message Although NEC has taken all possible steps
to ensure that the documentation supplied
to our customers is complete, bug free
and up-to-date, we readily accept that
From:
errors may occur. Despite all the care and
precautions we've taken, you may
Name encounter problems in the documentation.
Please complete this form whenever
Company you'd like to report errors or suggest
improvements to us.
Tel. FAX
Address
Thank you for your kind support.
North America Hong Kong, Philippines, Oceania Asian Nations except Philippines
NEC Electronics Inc. NEC Electronics Hong Kong Ltd. NEC Electronics Singapore Pte. Ltd.
Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: +65-250-3583
Fax: 1-800-729-9288
1-408-588-6130
Korea Japan
Europe
NEC Electronics Hong Kong Ltd. NEC Semiconductor Technical Hotline
NEC Electronics (Europe) GmbH
Seoul Branch Fax: 044-435-9608
Technical Documentation Dept.
Fax: 02-528-4411
Fax: +49-211-6503-274
South America Taiwan
NEC do Brasil S.A. NEC Electronics Taiwan Ltd.
Fax: +55-11-6465-6829 Fax: 02-2719-5951
I would like to report the following error/make the following suggestion:
Document title:
Document number: Page number:
If possible, please fax the referenced page or drawing.
Document Rating Excellent Good Acceptable Poor

Clarity
Technical Accuracy
Organization
CS 00.6

78k Series Micro User Manual

Uploaded by

Copyright:

Available Formats

78k Series Micro User Manual

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

78k Series Micro User Manual

Uploaded by

Copyright:

Available Formats

User’s Manual

Common to 78K/0S Series

Document No. U11047EJ3V0UMJ1 (3rd edition)

2 User’s Manual U11047EJ3V0UM00

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

EEPROM is a trademark of NEC Corporation.

User’s Manual U11047EJ3V0UM00 3

4 User’s Manual U11047EJ3V0UM00

• Product release schedule

• Availability of related technical literature

User’s Manual U11047EJ3V0UM00 5

Throughout • Addition of the following target products

• Deletion of the following target products

p. 52 Modification of MOVW rp, AX instruction code

p. 54 Modification of XOR A, r instruction code

p. 54 Modification of CMP A, r instruction code

The mark shows major revised points.

6 User’s Manual U11047EJ3V0UM00

78K/0S Series products

• µPD789217AY Subseries : µPD789216AY, 789217AY, 78F9217AY

• µPD789407A Subseries: µPD789405A, 789406A, 789407A

Note Under development

• To check the details of the functions of an instruction whose mnemonic is known:

User’s Manual U11047EJ3V0UM00 7

Document common to 78K/0S Series

Document Name Document Number

User's Manual Instructions This manual U11047J

Document Name Document Number

µPD789011, 789012 Data Sheet U11095E U11095J

µPD78P9014 Data Sheet U10912E U10912J

µPD789014 Subseries User's Manual U11187E U11187J

Document Name Document Number

µPD789022, 789024, 789025, 789026 Data Sheet U11715E U11715J

µPD78F9026 Data Sheet U11858E U11858J

µPD789026 Subseries User's Manual U11919E U11919J

Document Name Document Number

µPD789046 Preliminary Product Information U13380E U13380J

µPD78F9046 Preliminary Product Information U13546E U13546J

µPD789046 Subseries User’s Manual U13600E U13600J

8 User’s Manual U11047EJ3V0UM00

Document Name Document Number

µPD789101, 789102, 789104 Data Sheet To be prepared U12815J

µPD789134 Subseries User’s Manual U13045E U13045J

Document Name Document Number

µPD789111, 789112, 789114 Preliminary Product Information U13013E U13013J

µPD78F9116 Preliminary Product Information U13037E U13037J

µPD789134 Subseries User’s Manual U13045E U13045J

Document Name Document Number

µPD789121, 789122, 789124 Preliminary Product Information U13025E U13025J

µPD789134 Subseries User’s Manual U13045E U13045J

Document Name Document Number

µPD789131, 789132, 789134 Preliminary Product Information U13015E U13015J

µPD78F9136 Preliminary Product Information U13036E U13036J

µPD789134 Subseries User’s Manual U13045E U13045J

• µPD789146, 789156 Subseries

Document Name Document Number

µPD789144, 789146, 789154, 789156 Preliminary Product Information U13478E U13478J