Introduction to the

ARM Instruction Set

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Agenda
Data Processing Instructions
Branch Instructions
Load-Store Instructions
Software Interrupt Instructions
Program Status Register Instructions
Loading Constants
ARMv5E Extensions
Conditional Execution
Summary

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ARM Instruction Set
Mnemonics ARM ISA Description
ADC v1 add two 32 bit values & carry
ADD v1 add two 32 bit values
AND v1 logical bitwise AND of two 32 bit values
B v1 branch relative +/- 32MB
BIC v1 logical bit clear of two 32 bit values
BKPT v5 breakpoint instructions
BL v1 relative branch with link
BLX v5 branch with link and exchange
BX v4T branch with exchange
CDP CDP2 v2 v5 coprocessor data processing operation
CLZ v5 count leading zeroes
CMN v1 compare negative two 32-bit values
CMP v1 compare two 32 bit values
EOR v1 logical EOR of two 32 bit values
LDC LDC2 v2 v5 load to coprocessor single or multiple
32 – bit values
LDM v1 load multiple 32 – bit words from
memory to ARM registers
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ARM Instruction Set - Contd
Mnemonics ARM ISA Description
LDR v1 v4 v5E load a single value from a virtual
address in memory
MCR MCR2 MCRR v1 v4 v5E move to coprocessor from an ARM
register to registers
MLA v2 multiply & accumulate 32 bit values
MOV v1 move a 32 bit value into a register
MRC MRC2 MRRC v1 v4 v5E move to ARM register or registers from
a coprocessor
MRS v3 move to ARM register from a status
register (cpsr or spsr)
MSR v3 move to a status register (cpsr or spsr)
from an ARM register
MUL v2 multiply two 32 bit values
MVN v1 move the logical NOT of 32 bit value
into a register
ORR v1 Logical bitwise OR of two 32 bit values
PLD v5E preload hint instruction
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ARM Instruction Set - Contd
Mnemonics ARM ISA Description
QADD v5E signed saturated 32 bit add
QDADD v5E signed saturated double and 32 bit add
QDSUB v5E signed saturated double and 32 bit sub.
QSUB v5E signed saturated 32 bit subtract
RSB v1 reverse subtract of two 32 bit values
RSC v1 reverse subtract with carry of two 32
bit integers
SBC v1 subtract with carry of two 32 bit values
SMLAxy v5E signed multiply accumulate instruction
((16 x 16) + 32 = 32 – bit)
SMLAL v3M signed multiply accumulate long
((32 x 32) + 64 = 64 – bit)
SMLALxy v5E signed multiply accumulate long
((32 x 16) + 64 = 64 – bit)
SMLAWy v5E signed multiply accumulate instruction
((32 x 16) >> 16 +32 = 32 – bit)
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ARM Instruction Set - Contd
Mnemonics ARM ISA Description
SMULL v3M signed multiply long (32x32 = 64 – bit)
SMULxy v5E signed multiply instructions
(16 x 16 = 32 – bit)
SMULWy v5E signed multiply instructions
(32 x 16) >> 16 = 32 – bit)
STC STC2 v2 v5 store to memory single or multiple 32
bit values from coprocessor
STM v1 store multiple 32 bit registers to memory
STR v1 v4 v5E store register to a virtual address in
memory
SUB v1 subtract two 32 bit values
SWI v1 software interrupt
SWP v2a swap a word/byte in memory with a
register, without interruption
TEQ v1 test for equality of two 32 bit values

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ARM Instruction Set - Contd
Mnemonics ARM ISA Description
TST v1 test for bits in a 32 bit value
UMLAL v3M unsigned multiply accumulate long
(32 x 32) + 64 = 64 – bit)
UMULL v3M unsigned multiply long
(32 x 32 = 64 – bit)
Different ARM architecture revisions support different
instructions
ARM instructions process data held in registers and only
access memory with load and store instructions
ARM instructions commonly take two or three operands

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Data Processing Instructions
Manipulate data within registers
 Move Instructions
 Arithmetic Instructions
 Logical Instructions
 Comparison Instructions
 Multiply Instructions
Most data processing instructions can process
one of their operands using the barrel shifter
S suffix updates the flags in the cpsr

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Move Instructions
<instruction>{<cond>}{S} Rd, N
Useful for setting values and transferring data
between registers
N can be a register or an immediate value
preceded by #
MOV Move a 32 bit value into a register Rd = N

MVN Move the NOT of the 32 bit value into a register Rd = ~N

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Barrel Shifter
Rn Rm

Pre-processing
No pre-processing
Shift the 32 bit
binary pattern in Barrel Shifter
one of the source Result N
registers left or
right by a specific Arithmetic Logic Unit
number of
positions before it
Rd
enters the ALU

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Logical shift left by one
Bit Bit Bit
31 2 0
nzcv 1 0 0 0 1 0 0 = 0x80000004
Condition Bags
31

nzCv 0 0 0 1 0 0 0 = 0x00000008
Condition Bags

Condition flags
PRE r5 = 5
Updated when r7 = 8
S is present
MOV r7,r5,LSL #1 ; POSTr5
=5 r7 = 10

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Barrel Shifter Operations
Mne. Description Shift Result Shift amount y
LSL logical shift left xLSLy x << y #0-31 or Rs
LSR logical shift right xLSRy (unsigned)x >> y #1-32 or Rs
ASR arith. right shift xASRy (signed)x >> y #1-32 or Rs
ROR rotate right xRORy ((unsigned)x >> y) | #1-32 or Rs
(x <<(32 – y))
RRX rotate right xRRXy (c flag << 31) | none
extended ((unsigned)x >>1)

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ARM Shift Operations
31 0 31 0

00000 00000

LSL #5 LSR #5

31 0 31 0

0 1

00000 0 11111 1

ASR #5 , positive operand ASR #5 , negative operand

31 0 31 0
C

C C

ROR #5 RRX

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 Barrel Shift Operation Syntax for
Data Processing Instructions
N Shift Operations Syntax
Immediate #immediate
Register Rm
Logical Shift Left by Immediate Rm, LSL #shift_imm
Logical Shift Left by Register Rm, LSL Rs
Logical Shift Right by Immediate Rm, LSR #shift_imm
Logical Shift Right by Register Rm, LSR Rs
Arithmetic Shift Right by Immediate Rm, ASR #shift_imm
Arithmetic Shift Right by Register Rm, ASR Rs
Rotate right by immediate Rm, ROR #shift_imm
Rotate right by register Rm, ROR Rs
Rotate right with extend Rm, RRX

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Arithmetic Instructions
<instruction>{<cond>}{S} Rd, Rn, N
ADC Add two 32 bit values and carry Rd = Rn + N +
carry
ADD Add two 32 bit values Rd = Rn + N
RSB Reverse subtract of two 32 bit values Rd = N – Rn
RSC Reverse subtract with carry of two 32 bit Rd = N – Rn -!
values (carry flag)
SBC Subtract with carry of two 32 bit values Rd = Rn -N–!
(carry flag)
SUB Subtract two 32 bit values Rd = Rn -N

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Arithmetic Instructions
RSB can be used to negate numbers

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Logical Instructions
<instruction>{<cond>}{S} Rd, Rn, N

AND logical bitwise AND of two 32 bit values Rd = Rn & N

ORR logical bitwise OR of two 32 bit values Rd = Rn | N

EOR logical exclusive OR of two 32 bit values Rd = Rn ^ N

BIC Logical bit clear (AND NOT) Rd = Rn & ~ N

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Logical Instructions
BIC is useful when clearing status bits
and is frequently used to change
interrupts masks in the cpsr
The logical instructions update the cpsr
flags only if the S suffix is present

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Compare Instructions
<instruction>{<cond>} Rn, N

CMN compare negated Flag set as a result of

Rn + N
CMP compare Flag set as a result of
Rn - N
TEQ test for equality of two 32 bit values Flag set as a result of
Rn ^ N
TST test bits of a 32 bit values Flag set as a result of
Rn & N

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Compare Instructions
They update the cpsr flag according to
the result but do not affect other
registers
CMP is effectively a subtract instruction
with result discarded
TST is logical AND operation
TEQ is logical EOR

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Multiply Instructions
MLA{<cond>}{S} Rd, Rm, Rs, Rn
MUL{<cond>}{S} Rd, Rm, Rs

instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs

MLA multiply & accumulate Rd = (Rm * Rs) + Rn

MUL multiply Rd = Rm * Rs

SMLAL signed multiply accumulate [RdHi,RdLo]=[RdHi,RdLo] +

long (Rm * Rs)
SMULL signed multiply long [RdHi,RdLo]=(Rm * Rs)
UMLAL unsigned multiply [RdHi,RdLo]=[RdHi,RdLo] +
accumulate long (Rm * Rs)
UMULL unsigned multiply long [RdHi,RdLo]=Rm * Rs
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Branch Instructions
Changes the flow of execution or is
used to call a routine
Forces the pc is point to a new address
B{<cond>} label
BL{<cond>} label
BX{<cond>} Rm
BLX{<cond>} label | Rm

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Branch Instructions
B branch pc = label
BL branch with link pc = label
lr = address of the next inst. After BL
BX branch pc = Rm & 0xfffffffe,
exchange T = Rm & 1
BLX branch pc=label, T = 1
exchange with pc = Rm & 0xfffffffe,
link T = Rm & 1
lr = address of the next inst. After BL

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Branch Instructions
The branch with link, or BL, instruction is
similar the B instruction but overwrites the link
register with a return address
To return from a subroutine, the link register should
be copied to the pc
BL subroutine ; branch to subroutine
CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ; if (r1 == 5) then r1 = 0
subroutine
….
….
MOV pc, lr ; return by moving pc = lr

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Load Store Instructions
Transfer data between memory and
processor registers
Single – register transfer
Multiple – register transfer
Swap

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Single Register Transfer
Moving a single data item in and out of
a register
Data types supported are signed and
unsigned words (32 bit), half words (16
bit) and bytes
<LDR|STR> {<cond>}{B} Rd,addressing
<LDR> {<cond>}SB|H|SH Rd,addressing
<STR> {<cond>}H Rd,addressing

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Single Register Transfer
LDR load word into a register Rd <-mem32[address]
STR save byte or word from a register Rd ->mem32[address]
LDRB load byte into a register Rd <-mem8[address]

STRB save byte from a register Rd ->mem8[address]

LDRH load half word into a register Rd <-mem16[address]

STRH save half word from a register Rd ->mem16[address]

LDRSB load signed byte into a register Rd <-SignExtend

(mem8[address])
LDRSH load signed half word into a Rd <-SignExtend
register (mem16[address])

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Single Register Load Store
Addressing Modes
The ARM instruction set provides different
modes for addressing memory
preindex with writeback
preindex
postindex

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Index Methods
Index Data Base Example
Method Address
Register
preindex mem[base+offset] base+ LDR r0, [r1, #4]!
with offset
writeback
preindex mem[base+offset] not LDR r0, [r1, #4]
updated
postindex mem[base] base+ LDR r0, [r1], #4
offset

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Index Methods
Preindex with writeback calculates an address from a
base register plus address offset and then updates that
address base register with the new address.
Preindex offset is same as the preindex with writeback
but does not update the address base register.
Postindex only updates the address base register after
the address is used

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Single Register Load Store
Addressing word or unsigned byte
Addressing Mode & Index Method Addressing Syntax
Preindex with immediate offset [Rn, #+/-offset_12]
Preindex with register offset [Rn, +/-Rm]
Preindex with scaled register offset [Rn, +/-Rm, shift #shift_imm]
Preindex writeback with immediate offset [Rn, +/-offset_12]!
Preindex writeback with register offset [Rn, +/-Rm]!
Preindex writeback with scaled register offset [Rn, +/-Rm, shift #shift_imm]!
Immediate postindexed [Rn], +/-offset_12
Register postindex [Rn], +/-Rm
Scaled register postindex [Rn], +/-Rm, shift #shift_imm

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Eg. of LDR instructions using
different addressing modes
Instruction r0= r1+=
Preindex LDR r0,[r1,#0x4]! mem32[r1+0x4] 0x4
with
writeback
LDR r0,[r1,r2]! mem32[r1+r2] r2
LDR r0,[r1,r2,LSR#0x4]! mem32[r1+(r2 LSR 0x4)] r2 LSR 0x4
Preindex LDR r0,[r1,#0x4] mem32[r1+0x4] not updated
LDR r0,[r1,r2] mem32[r1+r2] not updated
LDR r0,[r1,-r2,LSR#0x4] mem32[r1-(r2 LSR 0x4)] not updated
Postindex LDR r0,[r1],#0x4 mem32[r1] 0x4
LDR r0,[r1],r2 mem32[r1] r2
LDR r0,[r1],r2,LSR#0x4 mem32[r1] R2 LSR 0x4

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Variations of STRH instructions
Instruction Result r1+=
Preindex STRH r0,[r1,#0x4]! mem16[r1+0x4] =r0 0x4
with
writeback
STRH r0,[r1,r2]! mem16[r1+r2] =r0 r2
Preindex STRH r0,[r1,#0x4]! mem16[r1+0x4] =r0 not updated
STRH r0,[r1,r2] mem16[r1+r2] =r0 not updated
Postindex STRH r0,[r1],#0x4 mem16[r1] =r0 0x4
STRH r0,[r1],r2 mem16[r1] =r0 r2

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Multiple Register Transfer
Load–store multiple instructions can transfer multiple
registers between memory and the processor in a single
instruction.
Moving blocks of data around memory and saving and
restoring context stacks
<LDM|STM>{<cond>}<addressing mode>
Rn{!},<registers>{^}

LDM load multiple registers {Rd}*N <- mem32[start address

+ 4*N] optional Rn updated

STM save multiple registers {Rd}*N -> mem32[start address

+ 4*N] optional Rn updated

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Addressing Mode for Load Store
Multiple Instructions

Add: Description Start End Rn!

Mode Address Address
IA increment after Rn Rn +4*N-4 Rn+4*N

IB increment Rn + 4 Rn + 4*N Rn+4*N

before
DA decrement after Rn–4*N + 4 Rn Rn+4*N
DB decrement Rn – 4*N Rn - 4 Rn+4*N
before

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Example 3.17
Pre-condition of LDMIA Instruction
Memory Address Data
Address Pointer 0x00008020 0x00000005
0x0000801C 0x00000004
0x00008018 0x00000003 r3=0x00000000
0x00008014 0x00000002 r2=0x00000000
r0=0x00008010 0x00008010 0x00000001 r1=0x00000000
0x0000800C 0x00000000
Post-condition of LDMIA Instruction
Memory Address Data
Address Pointer
0x00008020 0x00000005
r0=0x0000801C 0x0000801C 0x00000004
0x00008018 0x00000003 r3=0x00000003
0x00008014 0x00000002 r2=0x00000002
0x00008010 0x00000001 r1=0x00000001
0x0000800C 0x00000000
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Example 3.17
Pre-condition of LDMIB Instruction
Memory Address Data
Address Pointer 0x00008020 0x00000005
0x0000801C 0x00000004
0x00008018 0x00000003 r3=0x00000000
0x00008014 0x00000002 r2=0x00000000
r0=0x00008010 0x00008010 0x00000001 r1=0x00000000
0x0000800C 0x00000000
Post-condition of LDMIB Instruction
Memory Address Data
Address Pointer
0x00008020 0x00000005
r0=0x0000801C 0x0000801C 0x00000004 r3=0x00000004
0x00008018 0x00000003 r2=0x00000003
0x00008014 0x00000002 r1=0x00000002
0x00008010 0x00000001
0x0000800C 0x00000000
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Load Store Multiple pairs when
base update used

Store Multiple Load Multiple

STMIA LDMDB
STMIB LDMDA
STMDA LDMIB
STMDB LDMIA

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Stack Operations
ARM architecture uses the load store multiple
instructions to carry out stack operations
Ascending –stack grows towards higher
memory address
Descending –stack grows towards lower
memory address
Full – sp points to the last item on the stack
Empty - sp points after the last item on the
stack

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Addressing Methods for Stack
Operations

Add: Description Pop =LDM Push =STM

Mode
FA full ascending LDMFA LDMDA STMFA STMIB

FD full descending LDMFD LDMIA STMFD STMDB

EA empty LDMEA LDMDB STMEA STMIA

ascending
ED empty LDMED LDMIB STMED STMDA
descending

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Stack Operations
ARM Thumb Procedure Call Standard
(ATPCS) defines how routines are called
and how registers are allocated.
In ATPCS stacks are defined as being
full descending stacks.
LDMFD and STMFD instructions provide
the pop and push functions.

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STMFD – full stack push
operation
PRE Address Data
0x00008018 0x00000001
sp 0x00008014 0x00000002
0x00008010 Empty
0x0000800C Empty

POST Address Data

0x00008018 0x00000001
0x00008014 0x00000002
0x00008010 0x00000003
sp 0x0000800C 0x00000002

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STMED – empty stack push
operation
PRE Address Data
0x00008018 0x00000001
0x00008014 0x00000002
sp 0x00008010 Empty
0x0000800C Empty
0x00008008 Empty

POST Address Data

0x00008018 0x00000001
0x00008014 0x00000002
0x00008010 0x00000003
0x0000800C 0x00000002
sp 0x00008008 Empty

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SWAP Instruction
Swaps the contents of memory with the
contents of a register
Atomic operation– it reads and writes a
location in the same bus operation,preventing any
other instruction from reading or writing to that
location until it completes.
SWP{B}{<cond>} Rd, Rm, [Rn]

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SWAP Instruction
SWP swap a word between tmp=mem32[Rn]
memory and a register mem32[Rn]=Rm
Rd=tmp
SWPB swap a byte between tmp=mem8[Rn]
memory and a register mem8[Rn]=Rm
Rd=tmp

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Software Interrupt Instruction
Causes a software interrupt exception
Provides a mechanism to call OS routines
SWI{<cond>} SWI_number
SWI software lr_svc=address of instruction
following the SWI
interrupt spsr_svc=cpsr
pc=vectors+0x8
cpsr mode =SVC
cpsr I = 1 (mask IRQ interrupts)

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Program Status Register
Instructions
2 instructions to directly control a psr
MRS - transfers the contents of cpsr or
spsr into a register
MSR - transfers the contents of register
into cpsr or spsr
Flags[24:31] Status[16:23] Extension[8:15] Control[0:7]
Fields
Bit 31 30 29 28 7 6 5 4 0

NZ C V I F T Mode
Function Condition Flags Interrupt Processor Mode
Masks
Thumb State
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Program Status Register
Instructions
MRS{<cond>} Rd,<cpsr|spsr>
MSR{<cond>} <cpsr|spsr>_<fields>,Rm
MSR{<cond>} <cpsr|spsr>_<fields>,#immediate

MRS copy psr to a gpr Rd = psr

MSR move gpr to a psr psr[field] = Rm

MSR move an immediate value to psr[field] = immediate

a psr

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Coprocessor Instructions
Are used to extend the instruction set
Additional computation capability
Used to control the memory subsystem
Used only cores with a coprocessor
CDP{<cond>} cp,opcode1,Cd,Cn{,opcode2}
<MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm{,
opcode2}
<LDC|STC>{<cond>} cp, Cd, addressing

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Coprocessor Instructions
cp field represents the coprocessor
number between p0 and p15
opcode fields describe the operation to
take place on the coprocessor
Cn, Cm and Cd describe registers within
the coprocessor
CP15 – system control purposes
MRC p15, 0, r10, c0, c0, 0

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Coprocessor Instructions

CDP coprocessor data processing -perform an

operation in a coprocessor
MRC coprocessor register transfer –move data
MCR to/from coprocessor registers

LDC coprocessor memory transfers –load and

store blocks of memory to/from a
STC coprocessor

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Loading Constants
LDR Rd, =constant
ADR Rd, label
LDR Load constant Rd = 32 bit
pseudoinstruction constant
ADR Load address Rd = 32 bit relative
pseudoinstruction address

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Loading Constants

Pseudo instruction Actual instruction

LDR r0, =0xff MOV r0, #0xff

LDR r0, =0x55555555 LDR r0, [pc,#offset_12]

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Loading 32-bit Constants
To allow larger constants to be loaded, the
assembler offers a pseudo-instruction:
 LDR Rd,=const
This will either:
 Produce a MOV or MVN instruction to generate the
value (if possible) or
 Generate a LDR instruction with a PC-relative address
to read the constant from a literal pool (constant data
area embedded in the code)
As this mechanism will always generate the best
instruction for a given case, it is the
recommended way of loading constant

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ARMv5E Extensions
Provide many new instructions
Provides greater flexibility and efficiency
when manipulating 16 bit values

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ARMv5E Extensions
Instruction Description
CLZ {<cond>} Rd, Rm count leading zeroes
QADD {<cond>} Rd, Rm, Rn signed saturated 32 bit add

QDADD {<cond>} Rd, Rm, Rn signed saturated double 32 bit add

QDSUB {<cond>} Rd, Rm, Rn signed saturated double 32 bit subtract
QSUB {<cond>} Rd, Rm, Rn signed saturated 32 bit subtract
SMLAxy {<cond>} Rd, Rm, Rs, Rn signed multiply accumulate 32 bit
SMLALxy {<cond>} RdLo, RdHi, Rm, Rs signed multiply accumulate 64 bit
SMLAWy {<cond>} Rd, Rm, Rs, Rn signed multiply accumulate 32 bit

SMULxy {<cond>} Rd, Rm, Rs signed multiply

SMULWy {<cond>} Rd, Rm, Rs signed multiply

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Count Leading Zeroes Instruction

CLZ
Counts the number of zeroes between
the MSB and the first bit set to 1
 R1=0x00000010
 CLZ R0,R1
 R0 = 6

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Saturated Arithmetic
Once the highest number is exceeded
the results remain at the maximum
value of 0x7fffffff
This avoids the requirement for any
additional code to check for possible
overflows
QADD Rd=Rn + Rm
QDADD Rd=Rn + (Rm*2)
QSUB Rd=Rn - Rm
QDSUB Rd=Rn - (Rm*2)

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ARMv5.E Multiply Instructions
Signed Multiply Signed Q Flag
Instruction [Accumulate] Result updated Calculation
SMLAxy (16-bit*16-bit)+32-bit 32-bit yes Rd=(Rm.x*Rs.y)+Rn
SMLALxy (16-bit*16-bit)+64-bit 64-bit - [RdHi,RdLo]+=
Rm.x*Rs.y
SMLAWxy ((32-bit*16-bit) >>16) 32-bit yes Rd=((Rm*Rs.y) >>16)
+32-bit +Rn
SMULxy (16-bit*16-bit) 32-bit - Rd=Rm.x*Rs.y
SMULWy ((32-bit*16-bit) >>16) 32-bit - Rd=(Rm*Rs.y) >>16

x and y select which 16 bits of a 32 bit register

are used for the first and second operands
T for the top 16 bits and B for the bottom 16 bits
SMLATB r4, r1, r2, r3  r4 = (r1.T * r2.B) + r3
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Conditional Execution
The instruction only executes if the
condition code flags pass a given
condition or test
Increase performance & code density
2 letter mnemonic (eg: AL)
Conditional execution depends on
 Condition field
 Condition flags

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Summary
All ARM instructions are 32 bit in length
Arithmetic, logical, comparison & move
instructions can all use the inline barrel shifter
3 types of load store instruction – single
register, multiple register, swap
SWI & Program Status Register
ARMv5E –CLZ, saturation, improved multiply
instructions
Conditional execution

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