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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1

Analysis and Demonstration of an IIP3

Improvement Technique for Low-Power
RF Low-Noise Amplifiers
Chun-Hsiang Chang and Marvin Onabajo , Senior Member, IEEE

Abstract— This paper describes a linearization method to power supply voltages (VDD ). However, the prevalent design
enhance the third-order distortion performance of a subthreshold challenge associated with subthreshold RF front-end circuits
common-source cascode low-noise amplifier (LNA) without extra has been linearity degradation. For example, in earlier pub-
power consumption by using passive components. An inductor
between the gate of the cascode transistor and the power supply lished subthreshold LNAs and mixers [5]–[13], the third-order
in combination with a digitally programmable capacitor between intermodulation intercept point (IIP3) is typically equal to or
the gate and the drain of the cascode transistor enable to below −10 dBm.
improve the third-order intermodulation intercept point (IIP3) of The most prevalent IIP3 improvement methods for low-
a subthreshold LNA. The theoretical mechanisms that underlie power LNAs in narrowband applications can be broadly
the linearity improvement are analyzed comprehensively under
the consideration of the LNA’s input stage, cascode stage, reverse divided into two categories. The first approach is to use
isolation, and stability. A 1.8-GHz LNA was designed and an auxiliary transistor biased in the weak inversion region
fabricated using 0.11-µm CMOS technology to prove the con- to cancel the third-order nonlinearity coefficient (g3 ), but
cept. Measurement results reveal that the linearized low-power the main transistor has to be operated in strong inversion
LNA has a 14.8-dB voltage gain, a 3.7-dB noise figure, and with higher linear transconductance (g1 = gm ) than that
a −3.7-dBm IIP3 with a power consumption of 0.336 mW.
in the auxiliary path [15], [16]. The second method is to
Index Terms— Low-noise amplifier, subthreshold biasing, weak operate the main transistor between the moderate inversion and
inversion, third-order intermodulation intercept point (IIP3) subthreshold regions for finding the optimum bias zone [17].
improvement, low-power radio frequency (RF) front-end design,
digitally programmable tuning. However, linearization methods have not yet been reported
with measurements of RF amplifiers using only transistors
biased in the subthreshold region.
I. I NTRODUCTION In this paper, measurement results are described together
with further analysis for a subthreshold LNA linearization
R EQUIREMENTS for portable electronic devices with
low-power radio frequency (RF) circuits are based on
the needs to extend battery lifetimes [1], [2] or to operate
technique that only uses passive devices for the third-order
nonlinearity coefficient reduction without additional power
with harvested energy [3], [4]. The low-noise amplifier (LNA) consumption. Furthermore, a digitally programmable IIP3
is a critical block in RF receiver front-ends because its tuning topology is employed for application in RF front-
specifications strongly impact the system-level performance of end calibration methods [18], [19]. The measurement results
the complete receiver, including the overall noise and linearity. were first presented in [20], and this extended article provides
Transistors operated in the subthreshold (or weak inversion) new insights from the detailed analysis of the LNA’s input
region offer opportunities to minimize power consumption of stage and cascode stage, including impacts of gate-to-bulk
CMOS RF front-end circuits. Over the past years, some of capacitances. Reverse isolation and stability considerations are
such LNAs and mixers were reported with very low power also discussed based on newly derived analytical expressions
consumptions [5]–[14], which were made possible through and plots. Additional simulations reveal how the linearization
high transconductance-to-drain current ratios (gm /ID ) and low method affects voltage gains associated with internal nodes
of the LNA. The paper is organized as follows. Section II
Manuscript received May 24, 2017; revised October 25, 2017; accepted briefly summarizes key subthreshold RF circuit design aspects.
December 4, 2017. This work was supported by the National Science
Foundation under Award 1451213. This paper was recommended by Associate The analyses of linearity, gain, noise, and input matching
Editor F. Lustenberger. (Corresponding author: Marvin Onabajo.) conditions for the linearized subthreshold LNA under investi-
C.-H. Chang was with the Department of Electrical and Computer gation are presented in Section III. Chip measurement results
Engineering, Northeastern University, Boston, MA 02115 USA. He is
now with OmniVision Technologies, Santa Clara, CA 95054 USA (e-mail: are summarized in Section IV, and conclusions are made
chunhsiang.chang@ovt.com). in Section V.
M. Onabajo is with the Department of Electrical and Computer
Engineering, Northeastern University, Boston, MA 02115 USA (e-mail: II. S UBTHRESHOLD D ESIGN C ONSIDERATIONS
monabajo@ece.neu.edu). The key distinguishing characteristics of subthreshold bias-
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. ing compared to strong inversion biasing are stated below to
Digital Object Identifier 10.1109/TCSI.2017.2781369 summarize our prior simulation-based works [21]–[24].
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 1. Drain current (ID ) with logarithmic scale and current efficiency
(gm /ID ) vs. overdrive voltage (VOV = VGS − VTH ) of an NMOS transistor
with 130nm channel length.

1) Higher power efficiency: transistors biased in sub-

threshold can provide a higher gm /ID ratio than when
biased in strong inversion. As can be seen in Fig. 1,
power-efficient subthreshold biasing involves the use of
gate-to-source (VGS ) bias voltages below the threshold
voltage (VTH ), where the overdrive voltage on the
x-axis is VOV = VGS − VTH . Hence, the drain-to-source
voltage (VDS ) can be low with subthreshold biasing,
which permits the use of reduced power supply voltages
at the expense of slightly higher noise figure.
2) Increase of parasitic capacitances and relative changes
of their values: In subthreshold mode of operation, the Fig. 2. (a) Contribution of parasitic capacitances to the total gate capac-
itance (Cgg ) vs. gm /ID ; (b) transition frequency (fT ) vs. gm /ID of an
gate-to-source capacitance (Cgs ) no longer dominates, NMOS transistor with 130nm channel length.
implying that the gate-to-drain capacitance (Cgd ) and
the gate-to-bulk capacitance (Cgb ) have to be taken tionship of the small-signal gate-source voltage (vgs) and
into account for more sophisticated design. As visual- the drain current (id ) can be expressed by the first three
ized in Fig. 2(a), the simulated Cgs /Cgg ratio (where: power series terms [25], [26]:
Cgg = Cgs + Cgd + Cgb ) decreases approximately 20% i d = g1 v gs + g2 v gs
2
+ g3v gs
3
, (1)
when gm /ID is swept such that the bias point changes
from the strong inversion region to the subthreshold where g1 , g2 and g3 are the linear transconductance
region. As a result, Cgs no longer dominates in the gain, second-order nonlinearity coefficient and third-
subthreshold region. Hence, the gate-drain capacitance order nonlinearity coefficient of the transistor, respec-
Cgd and the gate-bulk capacitance Cgb should be taken tively. Notice that these parameters can be obtained by
into account for precise input impedance matching cal- taking derivatives of the DC drain current (ID ) with
culation and linearity estimation. Moreover, to achieve respect to the DC gate-source voltage (VGS ) at the bias
similar transconductance gains as in strong inversion point:
it is required to increase the transistor widths, which ∂ ID 1 ∂ 2 ID 1 ∂ 3 ID
results in higher parasitic capacitances and lower tran- g1 = , g2 = , g 3 = . (2)
∂ VG S 2! ∂ VG2S 3! ∂ VG3S
sition frequency (fT ). Fig. 2(b) shows that the transition
frequency changes from 70 GHz to a few GHz when The sign of g3 changes from negative to positive when
the transistor bias is varied from the strong inversion to the transistor biasing is changed from strong inversion
the subthreshold region. In the past, transistors biased to subthreshold [21]. In addition, the value of g3 /g1
in subthreshold region were not seriously considered strongly depends on the gm /ID ratio when biasing tran-
for RF circuit design because fT was severely lim- sistors in the subthreshold region. This has created the
ited. However, newer CMOS process technologies have need to develop adapted or new linearization methods
significantly improved fT values, which has made it compared to existing schemes for RF circuits with
possible to design subthreshold circuits with operating transistors biased in the strong inversion region.
frequencies up to several gigahertz using 130nm CMOS
and smaller technology nodes. III. L INEARIZED S UBTHRESHOLD LNA
3) Linearity degradation due to highly positive g3 /g1 ratio, Fig. 3 displays the schematic of the LNA under investiga-
where g1 = gm and g3 is the third-order nonlinearity tion, where inductor Lg2 and digitally-programmable capacitor
coefficient: For a weakly nonlinear transistor, the rela- Cgd2_ext can improve the IIP3 in the presence of variations.
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CHANG AND ONABAJO: ANALYSIS AND DEMONSTRATION OF AN IIP3 IMPROVEMENT TECHNIQUE 3

Fig. 5. Small-signal model of the LNA’s input stage with M1 under

consideration of its nonlinear drain-to-source current.
Fig. 3. Linearized subthreshold LNA, where the voltage at the source of M2
is referred to as Vy . A. Linearity Analysis of the Input Stage
The input stage (transistor M1 ) and cascode stage
(transistor M2 ) of the LNA in Fig. 3 are split into two
individual parts to simplify the linearity analysis. Fig. 5 shows
the small-signal model of the input stage where the extra
metal-insulator-metal capacitor (Cgs1e xt ) is lumped into the
parasitic capacitance Cgs1 . The IIP3 of transistor M1 can be
derived after Volterra series analysis [15], [16], [28] as
1
I I P3,M1 = , (3)
6Rs · |H1 (ω)| · |A11 (ω)|3 · |ε M1 (ω, 2ω)|
where ω is the center frequency of the two intermodulation
Fig. 4. Digitally-programmable capacitance (Cgd2_ext ). tones at ωRF1 and ωRF2 , ω is defined as |ωRF1 − ωRF2 |,
and Rs is the antenna impedance of 50. H1 (ω) is the
third-order nonlinearity transfer function from Vin to the drain-
Inductor Lg1 , inductor Lbuffer , and capacitor Cbuffer are off- source current (id1 ) of M1 , A11 (ω) is the linear transfer
chip components for impedance matching purposes. Cgd2_ext is function from the input voltage (Vx ) to the gate-to-source
implemented with a fixed metal-insulator-metal (MIM) capaci- voltage (Vgs1 ), and εM1 (ω, 2ω) represents the nonlinear
tor (Cgd2_ext0 ) and a 3-bit digitally-programmable MIM capac- contribution from the second-order and third-order terms of
itor (Cgd2_ext1 , Cgd2_ext2 , and Cgd2_ext3 ) as illustrated in Fig. 4. transistor M1 . Minimization of the term |εM1 (ω, 2ω)| in (3)
Preliminary simulations showed that MOS capacitors can also leads to improved IIP3 . For this reason, we will now focus on
be employed to realize Cgd2_ext , but resulting in slightly the analysis of the ε(ω, 2ω) term for transistors M1 and M2 .
increased LNA gain variation and less linearity improvement The εM1 (ω, 2ω) term of M1 can be expressed as
due to inherent nonlinearity and voltage-dependent variation of
MOS capacitances compared to metal-insulator-metal capac- ε M1 (ω, 2ω) = g3,M1 − go B,M1, (4)
itors. All passive devices (with frequency-dependent quality
factor limitations) and active devices were simulated using where (5)–(12) define the parameters, as shown at the bottom
foundry-supplied models. In this section, the bonding/package of the next page.
parasitics and buffer stage were neglected to simplify the The variables g1,M1 , g2,M1 and g3,M1 are the linear transcon-
small-signal analysis. It has been shown in [27] that an induc- ductance gain, second-order nonlinearity coefficient and third-
tor between the gate of the cascode transistor and the power order nonlinearity coefficient of transistor M1 , respectively.
supply can improve stability of a common-source cascode The terms gM1 (ω) and gM1 (2ω) in (5) can be evaluated by
LNA by creating a sharp notch in the transfer function of substituting ω = |ωRF1 − ωRF2 | and 2ω = (ωRF1 + ωRF2 ) for
the reverse isolation (S12) around the operating frequency. ω in (6) respectively. Note that contrary to [21], the parasitic
In another related work [28], a fully differential common- capacitance Cgb1 was included above to further improve the
source LNA topology with an inductor at the gate of the accuracy of the analysis and the insights gained from it, for
cascode transistor, combined with a cross-coupling capacitor which more detailed derivations are provided here. Conceptu-
between the gate of the cascode transistor and the source of ally, Fig. 6 visualizes that the mechanism of the partial third-
the opposite cascode transistor, was introduced to decrease order intermodulation cancellation in (4) entails changing the
the noise figure, improve the linearity, and enhance the magnitude and phase of goB,M1 in (5) such that they are almost
voltage gain. Nevertheless, this LNA was biased in the strong identical to those of g3,M1 , where goB2,M1 represents a better
inversion region. The linearization method described in the design point (with more cancellation of g3,M1) than goB1,M1
next subsection was developed for subthreshold common- as result of different parameters.
source cascode LNAs and does not require cross-coupling for To continue the analysis, the following equations can be
nonlinearity cancellation. written after applying Kirchhoff’s current law to nodes 1, 2,
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

On the other hand, the relationship between the drain

current (id1 ) and the gate-to-source voltage (Vgs1 ) of tran-
sistor M1 can be written in terms of its linear transconduc-
tance (g1,M1 ) and its nonlinear transconductance components
(g2,M1, g3,M1 , . . .):
 
i d1 Vgs1 = g1,M1 Vgs1 +g2,M1 Vgs1 2
+g3,M1 Vgs1
3
+ . . . . (19)
Furthermore, the relation between Vx and Vgs1 in Fig. 5 can
Fig. 6. Vector diagram of the third-order intermodulation cancellation, where also be expressed with a Volterra series as
goB1,M1 and goB2,M1 are goB,M1 realizations in (4) with different design
parameters. Vgs1 (ω) = A11 (ω) ◦ Vx + A12 (ω1 , ω2 ) ◦ Vx
+ A13 (ω1 , ω2 , ω3 ) ◦ Vx . . . . (20)

and 3 in Fig. 5: From [15], [16], and [28] , the linear transfer functions
  A11 (ω) and C11 (ω) above can be determined by applying a
Vx
− j ωC gs1 + j ωC gd1 + j ωC gb1 +
1
V11 , single tone [Vx (ω) = ejωt ] in the analysis, which results in:
Z 11 Z 11 
1 1 + j ωC gd1 Z 13 (ω)
+ j ωC gs1 V12 + j ωC gd1 V13 = 0 (13) A11 (ω) = , (21)
  g1,M1 + g M1 (ω) Z (ω)
1
j ωC gs1 V11 − j ωC gs1 + V12 + i d1 = 0, (14) j ωC gd1d(ω)−[d(ω)+e(ω)] g1,M1 A11 (ω)
Z 12 C11 (ω) = Z 13 (ω) ;
 
1 b (ω)+c(ω) + j ω C gs1 Z (ω)
j ωC gd1 V11 − j ωC gd1 + V13 − i d1 = 0. (15) (22)
Z 13
Furthermore, where:

Vgs1 = V11 − V12 . (16) b (ω) = 1 + j ωC gd1 Z 13 (ω) , (23)

c (ω) = [ j ωC gs1 + j ωC gd1 + j ωC gb1 −ω C gd1C gb1 Z 13 (ω)] 2

Using (13) through (16) and the definitions of gM1 (ω) in (6), · Z 11 (ω) , (24)
Z(ω) in (7), and Z13 (ω) in (10), Vgs1 (ω) can be derived as d (ω) = 1 + j ωC gs1 Z 12 (ω) , (25)
the following function of Vx and id1 : e (ω) = [ j ωC gs1 + j ωC gd1 + j ωC gb1 −ω2 C gs1C gb1 Z 12 (ω)]
  
1 1+ j ωC gd1 Z 13 (ω) Vx · Z 11 (ω). (26)
Vgs1 (ω) = −i d1 . (17)
g M1 (ω) Z (ω)

The relation between Vx and V13 , where Vx and V13 are the B. Linearity Analysis of the Cascode Stage
input and output voltages of the input stage with transistor M1 , Fig. 7 depicts the small-signal model of the cascode stage,
can be expressed with a Volterra series as where the extra MIM capacitor Cgd2_ext is merged with the
parasitic capacitance Cgd2 . A cascode device whose gate
V13 (ω) = C11 (ω) ◦ Vx + C12 (ω1 , ω2 ) ◦ Vx is connected to an AC ground (i.e., VDD ) typically only
+ C13 (ω1 , ω2 , ω3 ) ◦ Vx . . . . (18) has a small impact on the overall linearity of a cascode


2 2 2 1
go B,M1 = g2,M1 + , (5)
3 g1,M1 +g M1 (ω) g1,M1 +g M1 (2ω)
1 + j ωC gd1 · [Z 11 (ω) + Z 13 (ω)] + j ωC gs1 · [Z 11 (ω) + Z 12 (ω)] + j ωC gb1 · [1 + j ωC gd1 Z 13 (ω)] · Z 11 (ω)
g M1 (ω) = ,
Z (ω)
(6)
Z (ω) = Z 12 (ω) + j ωC gb1[1 + j ωC gd1 Z 13 (ω)]Z 11 (ω) Z 12 (ω)
+ j ωC gd1 [Z 11 (ω) Z 12 (ω) + Z 11 (ω) Z 13 (ω) + Z 12 (ω) Z 13 (ω)] , (7)
Z 11 (ω) = Rs + j ωL g1, (8)
Z 12 (ω) = j ωL s , (9)
1 + j ωC gd2 Z 23 (ω) + [ j ωC gs2 + j ωC gd2 −ω2 C gs2 C gd2 Z 23 (ω)]· Z 22 (ω)
Z 13 (ω) = , (10)
g1,M2 + j ωC gs2 + [ j ωC gd2 g1,M2 − ω2 C gd2 C gs2 ] · [Z 22 (ω) + Z 23 (ω)]
   −1
Z 22 (ω) = j ωL g2 // j ωC gb2 , (11)
−1
Z 23 (ω) = Rd // ( j ωL d ) // ( j ωCd ) . (12)
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CHANG AND ONABAJO: ANALYSIS AND DEMONSTRATION OF AN IIP3 IMPROVEMENT TECHNIQUE 5

and 5 in Fig. 7, the following equations can be obtained:

V22
j ωC gs2 (V22 −V21)+ + j ωC gd2 (V22 − V23 ) = 0, (31)
Z 22
V23
j ωC gd2 (V23 − V22 ) + + i d2 = 0. (32)
Z 23
It can be noted that
Vgs2 = V22 − V21 . (33)
From (31) through (33) and the previous gM2 (ω), Z22 (ω)
and Z23 (ω) definitions, Vgs2 (ω) can be found in terms of V21
Fig. 7. Small-signal model of the LNA’s cascode stage with M2 under and id2 as follows:
consideration of its nonlinear drain-to-source current. 
1 f (ω)V21
Vgs2 (ω) = − i d2 , (34)
g M2 (ω) j ω C gd2 Z 22 (ω) Z 23 (ω)
common-source LNA. On the other hand, the cascode stage where:
with additional components at the gate of M2 in Fig. 3  
has a significant impact on the overall linearity performance. f (ω) = 1 + j ωC gd2 Z 23 (ω) · [1 + j ωC gd2 Z 22 (ω)]
Subthreshold RF designs typically employ wide transistors to + ω2 C gd12 Z 22 (ω) Z 23 (ω) . (35)
achieve sufficiently high transconductances. Hence, increasing
The relationship between V21 and V23 in Fig. 7, where V21
the width/length ratio of M2 is not a feasible option to reduce
and V23 are the input and output voltages of transistor M2 ,
its impact on linearity because the adverse effects of the para-
can be written with Volterra series:
sitic capacitances on gain and reverse isolation would become
worse. However, nonlinearity cancellation in the cascode stage V23 (ω) = C21 (ω) ◦ V21 + C22 (ω1 , ω2 ) ◦ V21
is realized with the proposed design technique to improve + C23 (ω1 , ω2 , ω3 ) ◦ V21 . . . . (36)
third-order linearity. The linearity effect of the cascode device
was only briefly analyzed in [20], and the following analysis The relation between the drain current (id2 ) and the gate-
in this section provides further insights into internal transfer to-source voltage (Vgs2) of transistor M2 is
functions that affect the LNA’s voltage gain (Section III-C).  
i d2 Vgs2 = g1,M2 Vgs2 +g2,M2 Vgs22
+g3,M2 Vgs2
3
+ . . . . (37)
By applying Volterra series [28] analysis, the upper AIIP3 limit
(i.e., max. IIP3 point in volts) due to transistor M2 can be Furthermore, the relationship between V21 and Vgs2 can be
derived as expressed by applying Volterra series as
4 1 Vgs2 (ω) = A21 (ω) ◦ Vx + A22 (ω1 , ω2 ) ◦ Vx
A2IIP3,M2 = · . (27)
3 |H2 (ω)| · |A21 (ω)|3 |ε M2 (ω, 2ω)| + A23 (ω1 , ω2 , ω3 ) ◦ Vx . . . . (38)
The definition of εM2 (ω, 2ω) is the same as in (4) and Correspondingly, the linear transfer functions A21 (ω) and
can be rewritten as C21 (ω) can be determined through single-tone analysis [using
V21 (ω) = ejωt ], which are:
ε M2 (ω, 2ω) = g3,M2 − go B,M2, (28) 
1 f (ω)
A21 (ω) = , (39)
where: g1,M2 +g M2 (ω) j ωC gd2 Z 22 (ω) Z 23 (ω)
 ⎡  ⎤
2 2 2 1 1+ j ωC gs2 + j ωC gd2
go B,M2 = g2,M2 + , ⎢g1,M2 A21 (ω) ⎥
3 g1,M2 +g M2 (ω) g1,M2 +g M2 (2ω) ⎢ f (ω) ⎥
C21 (ω) = Z 23 (ω) ⎢ ⎥.
(29) ⎣ ω2 C gs2C gd2 Z 22 (ω) ⎦
−
1 + j ωC gd2 Z 23 (ω) f (ω)
  (40)
+ j ωC gs2 + j ωC gd2 · [1 + j ωC gd2 Z 23 (ω)]
· Z 22 (ω) Fig. 8 visualizes the numerical calculations of
+ω2 C gs2 C gd2 Z 22 (ω) Z 23 (ω) |εM2 (ω, 2ω)| in equation (28) versus Lg2 for three values
g M2 (ω) = . (30) of Cgd2_ext based on the above equations. In this design
j ωC gd2 Z 22 (ω) Z 23 (ω)
example, an Lg2 value around 3.5 nH leads to optimum IIP3.
Parameters g1,M2 , g2,M2 and g3,M2 are the linear gain, In addition to the cancellations associated with equations (28)
second-order nonlinearity coefficient and third-order nonlin- and (4) for the cascode stage and input stage respectively, the
earity coefficient of transistor M2 . The terms gM2 (ω) and effectiveness of the linearization is impacted by higher-order
gM2 (2ω) in (29) can be evaluated by substituting ω = nonlinearities and interactions between the stages. Depending
|ωRF1 − ωRF2 | and 2ω = (ωRF1 + ωRF2 ) for ω in (30) respec- on a particular LNA’s design parameters, its center frequency,
tively. The linear transfer function A21 (ω) in equation (27) is and the process technology; either transistor M1 or M2
derived next. By applying Kirchhoff’s current law to nodes 4 can be the linearity bottleneck with subthreshold biasing.
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 8. Calculation results of |ε(ω, 2ω)| in equation (28) for Lg2 with Fig. 9. Simulated voltage gains from Vin to Vy (at the source of M2 ) and
three Cgd2_ext combinations in the cascode stage (with M2 ). Vgs2 of the LNA with and without Lg2 and Cgd2_ext (ideal components).

In this design, M2 imposes more severe linearity degradation. voltage gain from Vin to Vy is same as that from Vin to Vgs2
In general, numerical evaluations of equations (4) and (28) but with opposite phase. The LNA with Lg2 = 3.5 nH and
for a few Cgd2_ext values can serve as a helpful first design Cgd2_ext = 150 fF has a lower voltage gain Vy /Vin than the
step, as it allows the selection of the Lg2 range for an initial conventional cascode common-source LNA, but both LNAs
design by observing the inductor values for optimum M1 and have a similar Vgs2 /Vin gain for frequencies around and above
M2 linearity. While the above equations provide a theoretical the 1.8 GHz operating frequency. Hence, the attenuation at Vy
foundation for the proposed linearization technique to identify and reduced signal swing at this node (due to Lg2 and Cgd2_ext )
tradeoffs based on key parameters, in practice a designer can contributes to the linearity improvement.
select a reasonable Cgd2_ext value and sweep Lg2 in post-
layout circuit simulations with accurate device models and
D. Input Matching Network
extracted parasitics. A standard IIP3 metric can be monitored
during the simulations in lieu of the |εM2 (ω, 2ω)| term. The input matching of a subthreshold common-source
In our previous research [21], two LNA designs (with and LNA was analyzed in [23] without inductor Lg2 . For the
without this linearized technique) were compared based on modified LNA (with linearization) presented in this paper, it
simulations. The LNAs were designed with the same power can be shown that the input impedance under consideration of
consumption, and have the same voltage gain in the typical the extra components can be estimated as
corner case. The comparison revealed that the conventional 1
∗
cascode LNA has a slightly better noise performance (0.4 dB) Z in (ω) = j ωL g1 + Z in (ω) // ; (42)
j ωC M F
than the linearized LNA. However, the linearized LNA has a
significantly higher IIP3 (e.g., 11.2 dB better in [21]) with where
negligible difference in the other performance parameters. ∗ 1 g1,M1 L s
The related reverse isolation (S12) and stability aspects Z in (ω) = + j ωL s + , (43)
j ωC gs1 C gs1
for the selection of Lg2 and Cgd2_ext values are discussed C M F = (1 + A (ω)) · C gd1 + C gb1 , (44)
in Section III-F.
A (ω) = G 1,M1−ef f (ω) · Z 13 (ω) , (45)
g1,M1
C. Voltage Gain G 1,M1−e f f (ω) = − j ωC gd1,
1 + j ωL s (g1,M1 + j ωC gs1)
The voltage gain of the linearized LNA can be separated (46)
to identify the contributions associated with transistors M1
and M2 . In sections III-A and III-B, the linear transfer and Z13 (ω) is defined in equation (10).
functions from Vx to V13 (in Fig. 5) and from V21 to V23
(in Fig. 7) were derived, which represent the frequency-
E. Noise
dependent voltage gains C11 (ω) and C21 (ω) of the two stages.
From equations (22) and (40), these voltage gains can be The noise factor analysis for the subthreshold common-
combined to determine the overall LNA gain: source LNA with inductive source degeneration has been
reported in [29] with the following result:
Av (ω) = |C11 (ω)| × |C21 (ω)| . (41) ⎡
ω 2 R γ n2 V δα 2   C2
In addition to the nonlinearity cancellation analyzed above, F = 1 + Ct2 × o
s T ⎣ 1 + Q 2in
gs1
a secondary mechanism leads to linearity enhancement thanks ID 5γ Ct2
to the extra components at the gate of M2 . Fig. 9 displays  ⎤
the simulated voltage gains from Vin to Vy (at the source C gs1 δα 2
+ 1 − 2 |c| ⎦, (47)
of M2 ) and Vgs2 (in Fig. 3). For the LNA without Lg2 , the Ct 5γ
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

CHANG AND ONABAJO: ANALYSIS AND DEMONSTRATION OF AN IIP3 IMPROVEMENT TECHNIQUE 7

where Ct = Cgs1 + Cgs1_ext , ω0 is the operating fre-

quency, γ and δ are the channel and gate noise coefficients,
α = g1,M1 /gd0,M1, gd0,M1 is the channel conductance with
zero drain-source voltage, VT is the thermal voltage, Qin is
the quality factor of the input matching network, and c is
the correlation parameter between the gate and channel noise
currents.
F. Reverse Isolation and Stability
Compared to conventional common-source cascode LNAs,
the described linearization method requires an inductor at the
gate of the cascode transistor. As shown in [27], the reverse
isolation of such an LNA can be improved in the desired
frequency band with proper sizing of the inductor at the gate
of the cascode transistor. To analytically estimate the impact
on reverse isolation, the transfer function from Vout_LNA to Vy
(at the source of M2 ) in Fig. 3 can be derived from the small-
signal circuit in Fig. 10(a):
Vy s 3 + b2 s 2 + b0
H (s) = = , (48)
Vout _L N A a3 s3 + a2 s 2 + a1 s + a0
where:
a3 = 1 + C gb2 /C gd2,
a2 = (ro2 + Z M1 + gm2ro2 Z M1 )/(C gs2ro2 Z M1 )
+ (ro2 + Z M1 )/(C gd2ro2 Z M1 )
+ C gb2 (1 + gm2ro2 + ro2 /Z M1 )/(C gs2 C gd2ro2 ),
Fig. 10. (a) Simplified small-signal model of the cascode stage for reverse
a1 = 1/(C gd2 L g2 ), isolation analysis, and (b) simulated reverse isolation from Vout_LNA to Vy
a0 = (1 + gm2ro2 + ro2 /Z M1 )/(C gs2 C gd2ro2 L g2 ), with and without Lg2 .

b2 = 1/(C gs2ro2 ) + 1/(C gd2ro2 ) + gm2 /C gs2 where  = S11 · S22 − S12 · S21. The unconditional stability
+ C gb2 /(C gs2 C gd2ro2 ), requirement is K > 1 and || < 1. Note that S11 and S22
b0 = 1/(C gs2C gd2ro2 L g2 ), are close to zero when the input and output of the LNA are
matched to the source and load impedances. Based on the
ro2 is the drain-source resistor of transistor M2 , and ZM1 is the measured S-parameters in Section IV, the value of || is less
equivalent impedance looking into the drain of transistor M1 . than 1 and the value of K is more than 1 in the frequency
Note that Lg2 and Cgd2_ext have to be chosen properly for range from 0.1 GHz to 8.5 GHz. The || and K values are
enhanced reverse isolation in the desired frequency band. 0.05 and 17.67 at 1.8GHz, respectively.
To simplify the assessment of Lg2 ’s effect on the reverse iso- From LNA simulations without buffer, the reverse isolation
lation from Vout_LNA to Vy , ZM1 can be replaced by the drain- at 1.8 GHz with Lg2 = 3.5 nH and Cgd2e xt = 150 fF
source resistance (ro1 ) of M1 . However, Lg2 was modeled as a is slightly better (−29.7 dB) than without Lg2 and Cgd2_ext
non-ideal inductor based on the information in [30] and [31]. (−27.4 dB). As S12 decreases, the value of K increases
The macromodel simulation results in Fig. 10(b) show that and || decreases, resulting in better stability. However, it is
the reverse isolation (Vy /Vout_LNA ) has a notch and a peak important to consider that the values of Lg2 and Cgd2_ext can
as predicted by equation (48). Note that the depth of the degrade reverse isolation and stability if they are not carefully
notch and magnitude of the peak are overestimated with selected. If Lg2 and Cgd2_ext become too large, then the peak
the simulations of the macromodel with an inductor having of the transfer function in equation (48) moves from higher to
a high quality factor of 12.5. With a reduced Lg2 quality lower frequency, which can cause a stability problem.
factor of 7.1, the peak in this example reduces by 5.3 dB.
In practice, the peak and notch depth are further reduced IV. E XPERIMENTAL R ESULTS
by parasitic capacitances from routing and devices that are
A 1.8 GHz linearized subthreshold LNA has been designed
not included in the model, which further improves stability
and fabricated in Dongbu 0.11μm CMOS technology. Fig. 11
by lowering the quality factor of the network at the gate of
displays the chip micrograph of the LNA with an area of
transistor M2 . In addition, the peak in particular is further
810 μm × 770 μm. Table I lists the key design parameters
reduced by transconductance degradation at high frequencies.
of the LNA. It consumes a 480 μA current (with exclusion of
The stability factor of the LNA is defined in [28] and [29]:
the buffer) from a 0.7 V power supply instead of the nominal
1 + ||2 − |S11|2 − |S22|2 1.2 V supply voltage for this technology. In order to limit the
K = , (49)
2 · |S21| · |S12| linearity degradation due to the output buffer that was designed
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 11. Chip micrograph of fabricated linearized subthreshold LNA. Fig. 12. Measured scattering parameters of the LNA with buffer stage
TABLE I (−5.3 dB gain).
LNA D ESIGN PARAMETERS

Fig. 13. Measured noise figure of the LNA with buffer stage (−5.3 dB gain).

within 0.8 dB, which supports that the measured LNA gain
is at least 14.8 dB because any significant reduction of the
LNA gain would significantly degrade the overall noise figure
of the combined LNA and buffer stages. Notice that the
−5.3 dB gain of the buffer in Fig. 3 is in the presence of
parasitics due to the bonding, the integrated circuit package,
to test the LNA, a 1.2 V supply is used for the buffer. The and the PCB at the interface to the measurement equipment
Lg2 value of this design was selected to be 3.5 nH (with a with 50 termination. Fig. 14 shows the measured input IIP3
quality factor of 6.5 at 1.8 GHz), and final post-layout simu- of the LNA, and the output spectrum from a test with a
lations were performed with foundry-supplied device models two-tone input signal (1.8 GHz and 1.7995 GHz) and an
for all on-chip components. The prototype chip was bonded input power of −35 dBm. Fig. 15 contains the plot of output
to a conventional QFN16 package that was assembled on a power measurements from a power level sweep of a single
printed circuit board for measurements. 1.8 GHz tone to determine the 1-dB compression point (P1dB )
of the LNA. The IIP3 and P1dB of the linearized LNA are
−3.7 dBm and −12.6 dBm, respectively. Fig. 16 confirms that
A. Performance K > 1 and || < 1 within the 8.5 GHz range of the network
The control switch settings for Cgd2_ext of D3 D2 D1 = 100 analyzer used for the measurements.
resulted in the best linearity after fabrication process varia- Table II summarizes the performance of narrowband
tions. Fig. 12 shows the measured scattering parameters of low-power RF LNAs with operating frequencies ranging
the linearized subthreshold LNA. S11 and S22 are both below from 1 to 3 GHz in comparison to the presented design.
−10 dB at 1.8 GHz. The measured voltage gain of 9.5 dB at Most of the reported low-power LNA measurement results
1.8 GHz is the combination of the LNA and buffer. Also note reveal that the IIP3 is constricted to below −10 dBm except
that S12 is under −40 dB around the frequency of interest. in this work as well as in [17] and [32]. Compared to this
Fig. 13 displays the plot of the measured noise figure (NF) work with packaged chip measurements at 1.8 GHz on a
that is 6.3 dB at 1.8 GHz with the buffer. The voltage printed circuit board, the 1 GHz LNA in [32] was measured
gain and noise figure of the LNA are 14.8 dB and 3.7 dB on a probe station. Furthermore, the design in [32] contains a
after de-embedding the effects of the buffer stage loss and single transistor and three 11 nH inductors. Even though the
SMA cables. As part of the de-embedding process, the simu- cascode stage of a subthreshold LNA has negative impact on
lated gain and noise figure of the LNA and buffer combination linearity as discussed in Section III, we opted to include the
were compared to the measurement results. The overall noise cascode transistor to maintain adequate reverse isolation (S12)
figure difference between simulations and measurements was in this work with linearization enhancement. On a different
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

CHANG AND ONABAJO: ANALYSIS AND DEMONSTRATION OF AN IIP3 IMPROVEMENT TECHNIQUE 9

Fig. 15. Measured input-referred 1-dB compression point of the LNA with
buffer stage (−5.3 dB gain) at 1.8 GHz.

Fig. 14. (a) Measured input IIP3 of the LNA with buffer stage (−5.3 dB
gain), (b) output spectrum from a test with two tones at 1.8 GHz and
1.7995 GHz and an input power of −35 dBm.
TABLE II
C OMPARISON OF M EASUREMENT R ESULTS

Fig. 16. Plots from measured S-parameters: (a) ||, (b) K factor.

where ‘1’ and ‘0’ indicate that a switch is closed by applying

0 V or open by applying 0.7 V, respectively. Fig. 17 shows
the simulated IIP3 with a fixed setting of D3 D2 D1 = [100]
for various PVT (process, voltage, and temperature) cases.
note regarding Table II, the work in [17] is an indicator for the In Fig. 17(a), the best IIP3 is 3.9 dBm in the typical cor-
state-of-the-art in narrowband low-power LNA design because ner with VDD = 0.77 V and −10 °C. The worst IIP3 is
this recently published fully differential LNA was designed −8 dBm in the slow corner with VDD = 0.63 V and 85 °C
in 90nm CMOS technology and measured on a probe station. in Fig. 17(b). By tuning D3 D2 D1 from [100] to [001], the
simulated IIP3 can be improved by 3dB in the slow corner
B. IIP3 Tunability with VDD = 0.63 V and 85 °C. The digital programmability
The maximum and minimum capacitance values of Cgd2_ext has been included in this work to alleviate the IIP3 change
(in Fig. 4) occur with D3 D2 D1 = [111] and D3 D2 D1 = [000], due to variations.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE III
G AIN AND T HIRD -O RDER I NTERMODULATION D ISTORTION OF
THE LNA FOR A LL L INEARITY T UNING S ETTINGS

Fig. 19. IIP3 vs. Cgd2_ext comparison (simulation vs. measurement results).

circuit-level realization of the tuning capability. Thus, the

Fig. 17. Simulated IIP3 with PVT variations: (a) typical corner, (b) slow system-level development aspects related to automatic per-
corner, (c) fast corner.
formance enhancement with on-chip resources are outside
the scope of this paper, especially because associated built-
in testing and calibration approaches have been published
in [18], [19], [34], and [35].
V. C ONCLUSION
A 1.8 GHz subthreshold LNA with an IIP3 enhance-
ment technique was designed, analyzed, and fabricated
in 0.11μm CMOS technology. The proposed linearization
method involves extra passive components to accomplish
partial cancellation of third-order nonlinearity products. It does
Fig. 18. PCB to test the LNA with IIP3 tuning functionality. not require any auxiliary amplification circuitry that would
increase the power consumption. Therefore, the presented
As can be observed in Fig. 18, DIP switches on the linearization method is well-suited for low-power applications.
PCB were employed to set the control voltages (VDD or Measurement results of the 0.336 mW LNA on the prototype
ground) at the gates of the PMOS switches for IIP3 tuning. chip demonstrated an IIP3 of −3.7 dBm, a voltage gain
Table III lists the eight different capacitance combinations of 14.8 dB, and a noise figure of 3.7 dB.
with the corresponding measurement results of gain and the
third-order intermodulation distortion (IM3) when two tones ACKNOWLEDGMENT
at 1.8 GHz and 1.7995 GHz were applied with an input power The authors thank Kainan Wang and Li Xu for assistance
of −35 dBm. The results indicate that changing Cgd2_ext from with chip measurements and for valuable discussions.
70 to 210 fF has a minor effect on the gain while permitting to
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Chun-Hsiang Chang received the B.S. degree in
IEEE Microw. Wireless Compon. Lett., vol. 19, no. 11, pp. 719–721,
electronic engineering from the National Taiwan
Nov. 2009.
University of Science and Technology in 2000, the
[14] G. H. Tan, H. Ramiah, P.-I. Mak, and R. P. Martins, “A 0.35–V M.Eng. degree in electrical engineering from Texas
520-μW 2.4-GHz current-bleeding mixer with inductive-gate and A&M University in 2009, and the Ph.D. degree in
forward-body bias, achieving >13-dB conversion gain and >55-dB port- electrical engineering for Northeastern University
to-port isolation,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 4, in 2016. He is currently an Analog Design Engi-
pp. 1284–1293, Apr. 2017. neer with OmniVision Technologies, Santa Clara,
[15] V. Aparin, “Linearization of CDMA receiver front-ends,” Ph.D. disserta- CA, USA. His researches concentrate on RF front
tion, Dept. Elect. Comput. Eng., Univ. California, San Diego, San Diego, ends, bio-medical integrated circuit designs, CMOS
CA, USA, 2005. image sensor, and calibration circuits to compensate
[16] V. Aparin and L. E. Larson, “Modified derivative superposition method for PVT variations, particularly on the development of performance enhance-
for linearizing FET low-noise amplifiers,” IEEE Trans. Microw. Theory ment techniques for subthreshold circuits.
Techn., vol. 53, no. 2, pp. 571–581, Feb. 2005.
[17] R. Fiorelli, F. Silveira, and E. Peralıas, “MOST moderate–weak-
inversion region as the optimum design zone for CMOS 2.4-GHz Marvin Onabajo (S’01–M’10–SM’14) received the
CS-LNAs,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, B.S. degree (summa cum laude) from The University
pp. 556–566, Mar. 2014. of Texas at Arlington in 2003 and the M.S. and
[18] H. Chauhan, Y. Choi, M. Onabajo, I.-S. Jung, and Y.-B. Kim, “Accurate Ph.D. degrees from Texas A&M University in 2007
and efficient on-chip spectral analysis for built-in testing and calibration and 2011, respectively, all in electrical engineering.
approaches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, He is currently an Assistant Professor with the
no. 3, pp. 497–506, Mar. 2014. Electrical and Computer Engineering Department,
Northeastern University.
[19] Y. Choi, C.-H. Chang, H. Chauhan, I.-S. Jung, M. Onabajo, and
From 2004 to 2005, he was an Electrical
Y.-B. Kim, “A built-in calibration system to optimize third-order inter-
Test/Product Engineer at Intel Corporation, Hills-
modulation performance of RF amplifiers,” in Proc. IEEE Int. Midwest
boro, OR, USA. He joined the Analog and Mixed-
Symp. Circuits Syst. (MWSCAS), Aug. 2014, pp. 599–602.
Signal Center, Texas A&M University in 2005, where he was engaged
[20] C.-H. Chang and M. Onabajo, “Low-power low-noise amplifier IIP3 in research projects involving analog built-in testing, data converters, and
improvement under consideration of the cascode stage,” in Proc. IEEE on-chip temperature sensors for thermal monitoring. In 2011, he was a
Int. Symp. Circuits Syst. (ISCAS), May 2017. Design Engineering Intern with the Broadband RF/Tuner Development Group,
[21] C.-H. Chang and M. Onabajo, “Linearization of subthreshold low-noise Broadcom Corporation, Irvine, CA, USA. He has been with Northeastern
amplifiers,” in Proc. IEEE Intl. Symp. Circuits Syst. (ISCAS), May 2013, University, since 2011. His current research areas are analog/RF integrated
pp. 377–380. circuit design, on-chip built-in testing and calibration, mixed-signal integrated
[22] C.-H. Chang and M. Onabajo, “IIP3 enhancement of subthreshold active circuits for medical applications, data converters, and on-chip sensors for
mixers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 11, thermal monitoring. He received the 2015 CAREER Award from the National
pp. 731–735, Nov. 2013. Science Foundation, the 2017 Young Investigator Program Award from the
[23] C.-H. Chang and M. Onabajo, “Input impedance matching optimization Army Research Office, and the 2015 Martin Essigman Outstanding Teaching
for adaptive low-power low-noise amplifiers,” Analog Integr. Circuits Award from the College of Engineering, Northeastern University. He currently
Signal Process., vol. 77, no. 3, pp. 583–592, Dec. 2013. serves as an Associate Editor on the editorial boards of the IEEE T RANS -
[24] L. Xu, K. Wang, C.-H. Chang, and M. Onabajo, “Inductorless lineariza- ACTIONS ON C IRCUITS AND S YSTEMS –I and the IEEE Circuits and Systems
tion of low-power active mixers,” in Proc. IEEE Int. Symp. Circuits Magazine. From 2014 to 2015, he was on the Editorial Board of the IEEE
Syst. (ISCAS), May 2015, pp. 2213–2216. T RANSACTIONS ON C IRCUITS AND S YSTEMS –II.