Comparison of Transformerless Converter

Topologies for Photovoltaic Application Concerning

Efficiency and Mechanical Volume
W.-Toke Franke, Nils Oestreich, Friedrich W. Fuchs
Institute of Power Electronics and Electrical Drives
Christian-Albrechts-University of Kiel
Kaiserstr. 2 24143 Kiel, Germany
Phone: +49 431 8806106
Fax: +49 431 8806103
Email: tof@tf.uni-kiel.de, fwf@tf.uni-kiel.de
URL: http://www.tf.uni-kiel.de

Abstract—Three transformerless converters for three phase

solar applications are compared concerning efficiency, leakage
current and mechanical volume. The investigated topologies
are the voltage source inverter (VSI), the three level neutral
point clamped (NPC) inverter and the z-source inverter (ZSI).
Therefore the topologies are introduced and the working prin-
ciples are explained. The power losses, the resulting leakage
current at the pv array and the volume of the inverter are
investigated mathematically, by simulation and experimental
measurements. From the efficiency point of view the NPC has
Figure 1. Grid-connected solar system, Pictures: SMA Solar Technology AG
the best performance followed by the VSI and ZSI. The leakage
current is for all topologies acceptable.

I. I NTRODUCTION

Due to great decrease of the prices for solar cells in 2009

and constant high prices for electrical energy there is an
increasing demand on high efficient three phase solar inverters.
During the last years many topologies of solar inverters have
been proposed [1]–[5]. In general they can be classified into
topologies with and without a transformer. The transformer
decouples the pv array and the grid avoiding leakage currents
Figure 2. Voltage Source Inverter linked with a dc boost converter and
at the panels. The transformer can also be used to boost earthed midpoint
the input voltage [6]. The advantages of the transformerless
topologies are higher efficiency and less volume. However
the lack of the transformer also leads to some drawbacks: II. S YSTEM D ESCRIPTION
The main problems are the leakage currents between the
The regarded system is shown in figure 1. There is on the
solar panel and earth. These leakage currents are a risk for
left side the solar panel. For this analysis, a rated power of 5
humans touching the panel and for some kind of solar cells
kW and an open circuit voltage of 1000 V is chosen. In the
they accelerate the aging of the cells. In this paper three
middle the solar inverter is shown, which is connected to the
three-phase four wire transformerless topologies are selected
grid by a LCL filter.
that overcome the problem of the leakage currents. They are
For the inverter three different topologies with earthed dc
compared regarding their leakage currents, their power losses
link midpoint have been investigated:
and their volume. Therefore in section 2 the three systems
• Three phase four wire voltage source inverter linked with
are described and mathematical equations for calculating the
power losses are derived. After that the leakage currents dc-dc boost converter (BC+VSI) (figure 2)
• Three phase four wire Z-Source inverter (ZSI) (figure 3)
are explained and main parts of the inverter are discussed
• Three phase four wire neutral point clamped inverter
concerning their volume. In the next section the topologies
are compared to each other. At the end a conclusion is given. linked with dc-dc boost converter (BC+NPC) (figure 4)

978-1-4244-6392-3/10/$26.00 ©2010 IEEE 724

 Table I
R EQUIREMENTS FOR THE POWER SEMICONDUCTORS FOR A 5 K W P /
1000 V ARRAY

BC+VSI ZSI BC+NPC

max. blocking voltage switches 1200 V 1200 V 1200 V / 600 V
max. blocking voltage diodes 1200 V 1200 V 1200 V / 600 V
max. RMS current boost switches 8A - 8A
max. RMS current boost/dc link diode 8A 10 A 8A
max. RMS current VSI switches 8A 15 A 8A

is blocking since the dc link is short circuit by turning all

Figure 3. Z-source inverter with earthed midpoint switches simultaneously on. The current is limited by the
inductors in the dc link [11].
A. Power Losses
Operating semiconductors in switching mode, four different
kinds of losses occur. These losses are conducting and off-
state losses as well as switching and driving losses. Compared
with the conducting and switching losses the off-state and
driving losses are very small and can be neglected [12]. In
the following the forward or conducting characteristics of the
semiconductors have been linearized. The conducting losses
PC are calculated for one IGBT and one diode and depend
on the mean and the rms values of the current iV through the
valves. VCE,0 and VF,0 describe the threshold voltages and rCE
and rF the differential ohmic resistances of the IGBT and the
Figure 4. Neutral point clamped inverter with earth midpoint
diode, respectively.

PCIGBT = VCE,0 īV + rCE ĩV2 (1)

The boost converter of the BC+VCI topology is turned off
as long as the output voltage of the pv array is above 750 V. PCdiode = VF,0 īV + rF ĩV2 (2)
When the input voltage of the inverter drops below 750 V the
The switching losses are a function of the switching fre-
boost converter adjusts the input voltage of the VSI Vdc to 750
quency, voltage and current. However they depend also on the
V. In both operation modes the MPP-tracking is realized by
chosen PWM-method and the switching loss energies of the
the VSI. Even though the maximum dc link voltage is 1000
IGBT (Eon , Eo f f ) and the diode (Erec ). In datasheets these
V power semiconductors that are able to block 1200 V are
information are only given for a reference voltage vre f and
sufficient since 1000 V is the open circuit voltage. As soon
current ire f . The switching power losses are given for the
as the inverter starts to operate the voltage drops immediately
continuous PWM depending on actual voltage vV and current
to the maximum power point voltage. During this process the
iV [12] [13].
current fed into the grid is limited by the inverter control.
The requirements for the power semiconductors are listed in 1 vv i v
table I. The NPC inverter is a three level topology producing PSIGBT = fs (Eon + Eo f f ) (3)
π vre f ire f
three voltage levels per phase leg as + V2dc , 0 V and V2dc to
the output. The advantage is that due to a lower current ripple 1 vv iv
PSdiode = fs Erec (4)
smaller filter efforts are necessary. The working principle is π vre f ire f
that the inner switches define the positive and negative half B. Power Losses VSI+BC
of the sinusoidal waveform. The outer devices modulate the
The derivation of the power losses for the VSI+BC- topol-
sinusoidal output current.
ogy are performed in [14] and [10]. Therefore only the final
The Z-source inverter is a new inverter that has been results are presented here. Based on equation (1) and (2) the
discussed in several papers [7] [8]. Because of its unique conducting losses of the voltage source inverter with IGBTs
dc link network it is suitable for similar applications as the are derived:
three phase voltage source inverter linked with a dc to dc
boost converter [9] [10]. As long as the input voltage is  
above 750 V the ZSI works similar as VSI. In case the input IGBT VCE,0 îL Mπ
PC,V SI = 1+ cos ϕ +
voltage drops below this mark, the ZSI starts to boost the 2π 4
(5)
rCE î2L π
  
input voltage by applying shoot-through-states instead of zero 2
+M cos ϕ
states. During such a shoot-through state the dc link diode 2π 4 3

725
  
Diode VF,0 îL Mπ
PC,V SI = 1− cos ϕ + waveform is the sum of the sinusoidal grid current and the
2π 4 shoot-through peaks, which are non-linear. The mean and rms
(6)
rF î2L π
  
2 values of the shoot-through current through one IGBT are:
−M cos ϕ
2π 4 3
2 Pin
They depend on the line current iL , the modulation index M īIGBT
ST = D (14)
3 Vin
and on the power factor cos ϕ. The switching losses are given v
in (3) and (4) by subsituting the actual vv by Vdc and iv by iL .
!
Pin VC Tst 2
u 
u4
The losses of the boost converter depend on the input current ĩIGBT
ST = t D − +
9 Vin 2L 2
iin and the modulation index a that is defined as: (15)
2 "
Tst2
  
Ton Vin Pin VC Tst VC Tst 1 VC
a= = 1− (7) + − +
Ts Vdc Vin 2L 2 L 2 3 L 3
The modulation index is a function of the ratio of the input where D is the duty cycle of the shoot-through states. The
voltage to the output voltage that is in this case the dc link mean and rms values of the current through one IGBT and
voltage. The IGBT of the boost converter is turned on for the one diode are:
time Ton . The conducting losses for the IGBT and the diode r
are
 
IGBT /Diode 2 Pout πM
īL = 1± cos ϕ (16)
3 2πVout,l2l 4
PCIGBT = VCE,0 īV + rCE ĩV2 · a


(8) s
2
 
2 Pout π 2
PCdiode = VF,0 īV + rF ĩV2 · (1 − a)

IGBT /Diode
(9) ĩL = 2
± M cos ϕ (17)
3 2πVout,l2l 4 3
The switching losses of the semiconductors of the boost
converter are calculated by (3) and (4) with vv = Vdc and iv = There the +-sign is for the IGBT and the −-sign for the
iin . diode. While the mean value of the current through one IGBT
is the sum of īIGBT
G and īIGBT
ST the rms values cannot be
C. Power Losses NPC summed. As proposed in [10] an approximation for calculating
The power losses of the boost converter with IGBT of the rms value can be applied by defining the rms current as
the NPC topology are derived according to (8) and (9). The done in the last factor of the following equations:
conducting losses of the NPC inverter with MOSFETsare

2
given in the following equations for the first leg and half a PCIGBT
low
= VCE,0 īIGBT
L + īST + rCE īIGBT
L + ĩST (18)
fundamental period referening to (1), (2) and [15].

2
PCIGBT
high
= VCE,0 īIGBT
L + īST + rCE ĩIGBT
L + īST (19)
î2 RDS,on M
v1
Pcon = L (1 + cos ϕ)2 (10) Depending on the ratio of the input and output voltage
6π equation (18) or (19) has to be applied. If the higher losses
î2 RDS,on M 3π
 
v2 are chosen the error is always below 3%. The losses for the
Pcon = L + 4 cos ϕ − cos 2ϕ − 3 (11)
12π M diodes are given by
′ V f îL M
′ î2 R f M
v1 ,v2
Pcon = (sin ϕ − ϕ cos ϕ) + L (1 − cos ϕ)2 (12)
  2 
4π 6π PCDiode = VF,0 īDiode
L + r ĩ
F L
Diode
(1 − DST ) (20)
 
D1 îLV f M 4
Pcon = + 2ϕ cos ϕ − π cos ϕ − sin ϕ + The conducting losses of the dc link diode and the switching
4π M
  (13) losses also based on (3) and (4) can be found in [10].
1 M
+î2L R f 1 + cos2 ϕ


−
4 3π E. Leakage Current
The switching losses are calculated by (3) and (4) applying One of the main issues of transformerless solar inverters is
Vdc the leakage current at the pv array. It arises due to variation of
2 for vv and iL for iv .
the dc link potential to ground that derives from the switching
D. Power Losses ZSI pattern. Assuming that the load is y-connected the midpoint
For the calculation of the losses of the Z-source inverter with of the dc link has four different potential during one switching
IGBT the two operating modes have to be distinguished. In period. During one of the two zero-states all three phases of the
case that the ZSI is working as VSI because the input voltage grid are short circuited by having all upper devices conducting
is above 750 V the losses can be calculated as for the VSI. and the lower ones blocking or vice versa. In this state the
In case that it is working in boost mode the additional losses upper or lower rail of the dc link is connected to ground so
of the shoot-through-states have to be considered as well. The that the midpoint of the dc link is at ± V2dc . During active states
derivation of the losses is performed in [10]. The main issue one device of each phase is conducting whereas at least one of
is to derive the current through the valves, since the current them is in the upper half and one is in the lower half. In case

726
that two upper device and one lower device is conducting two valid for the proposed three phase four wire system.For the
phases are switched in parallel and connected to the upper dc NPC inverter the current passing through the clamping diodes
link rail. Thus the voltage drop across the load is only half of into the dc link has to be considered that leads to very long
the voltage drop of the phase that is connected to the lower equations. Calculations and simulations have shown that (22)
dc link rail. That leads to a midpoint voltage of the dc link also lead to acceptable results for the NPC inverter. Beside the
to ground of − V6dc and to V6dc in case that two device in the current ripple caused by the inverter also the current ripple
lower half are conducting. To reduce the leakage current at of the boost converter has to be considered that is for both
the panel one very effective way is to connect the midpoint to inverters the same:
CPV
ground. The leakage current is reduced by a factor of 2C dc
.
1
q
3 (1 − a) ∆iind 2 + 12 iin 2 a


F. Volume ĩBC =
6
The volume of the solar inverter is given by the size of īBC = (1 − a) iin (23)
the discrete parts as heat sink, filter inductors and capacitors, r
dc link capacitors, boost inductor, power semiconductors and 1
(1 − a) ∆iind 2 + 12 iin 2 a


ĩC,BC =
control section. In this paper the heat sink, the dc link 12
capacitors and the inductors are regarded. Since the dc link capacitor decouples the ripple of the boost
1) Heat sink: The size of the heat sink is determined by its converter and the VSI, it has to carry both ac components.
ability to dissipate the power losses of the semiconductors Ptot . Typically ripple currents produced by the inverter and the
The heat dissipation is proportional to the thermal resistance boost converter have different frequencies. For calculating the
Rth,HA between the heat sink and the ambient. The maximum lifetime of the capacitor the current ripple has to be transferred
thermal resistance that limits the junction temperature of to an equivalent current ripple at 100 Hz ĩ100 for the specific
the power device to their maximum temperature T j,max is capacitor by a factor given in the datasheet [18].
calculated by [16] For the worst case when none of the ripples are canceled
out the rms of ac current is
T j,max − TA
Rth,HA,max = − Rth,tot (21) q
Ptot ĩ100,C,tot = ĩ2100,C,V SI + ĩ2100,C,BC (24)
Here Rth,tot describes the total thermal resistance between
junction and heat sink. The volume of the heat sink is inversely Current Ripple of the DC Link Capacitors of the ZSI
proportional to Rth,HA The ZSI requires three capacitors and two inductors in the
2) DC Link Capacitors: The number of the electrolytic dc link. In case the ZSI is not in boost operation the ripple
capacitors in the dc link is determined by the maximum current for all four capacitors is the same and can be calculated
allowed current ripple for a specified lifetime of the capacitors according to (22) since the high frequent current has to pass
and the maximum allowed voltage drop during load steps. For through all four capacitors. Assuming that the inductor current
solar applications the load steps are not a big issue, since the is constant, the ripple current through the boost capacitors C1
power of the pv array changes slowly and the changes in the and C2 in boosting mode is
grid voltage are occur infrequently. Therefore the number of r
Vin D
capacitors is derived due to a lifetime of 10 years. From the ĩC1,2 = (25)
datasheet of the capacitors its lifetime for a specific magnitude Pin 1 − D
of the rms value of the ripple current at 100 or 120 Hz can For calculating the ĩ100 value, twice the switching frequency
be extracted. Higher frequencies have to be converted into its has to be taken as a basis. Since the rms current from (25)
equivalent 100 Hz frequency concerning the application notes. is for typical boost duty cycles (D = 0.1...0.3) much higher
In the following the current ripples for the different topologies than the rms value of the capacitor current due to the switching
are calculated. transients calculated by (22), the last one can be neglected. The
Current Ripple of the DC Link Capacitor for the BC+VSI inductances L1 and L2 are designed according to the maximum
and BC+NPC allowed current ripple that is calculated for the maximum
The ripple current for the VSI is calculated by boost modulation by
√ ! √ "
q 3D Vin 3 1
ĩC,V SI = ĩ2dc − ī2dc ∆iL1,2 = √ 1− D (26)
3D − 1 2L 2 2 fsw
√ !√
v !
(22)
u ""
u 3 3 9M and the input current.
= îL tM + cos2 ϕ −
4π π 16 Calculation of the required number of capacitors
The number of capacitors in parallel is determined by the re-
The derivation of the ĩdc , īdc and (22) can be found in quired lifetime of the inverter. The lifetime L of the aluminum
[17]. Even though the equations are derived for a three phase electrolytic capacitors depend on the ambient temperature TA
three wire system simulations have shown that they are also and the standardized current ripple ĩ100,C,tot [18]:

727
  2
ĩ100,C,tot
T0 −TA − 1k ∆T0 ĩC,rated
L = L0 2 10 2 (27)
There L0 , T0 , k, ∆T0 and ĩC,rated can be found in the
datasheet. If the required lifetime is not reached the current
ripple per capacitor has to be reduced by connecting capacitors
in parallel. The volume of the capacitors depends on the dc
voltage and the capacitance. For the EPCOS B43501 with a
rated voltage of VR = 500V the volume can be approximated
by
C
VolCdc = µF
+ 27cm3 (28)
2.5 cm 3

3) Inductances: Even though the grid filter is designed as

a LCL filter the volume of the capacitor will be neglected Figure 5. Leakage current of VSI, NPC and ZSI. Red line is the rms value
in this paper since it will be designed similar for all three of the leakage current, Pin = 2500 W
inverters. The volume of the inductors is roughly proportional
to its stored energy W : 

1

VolL ≈ W = Lĩ2L (29)


2


The line current through the grid filter is for all topologies






equivalent. For the VSI and ZSI also the same inductances may


be applied. For the NPC inverter only half the inductances are


required due to the three voltage levels. The inductances of

 


the boost converters in the dc link of the VSI and the NPC


inverter are designed similar. For the ZSI the sum of both the 

dc link inductors must have a higher energy storage capability 





 

as for the boost converter, since a boost of the dc link voltage

requires a reduction of the modulation index to achieve longer
shoot-through states on the one hand but also cause a buck
Figure 6. Efficiency based on thermal simulation with PLECS (Matlab),
behavior of the inverter on the other hand. Input Voltage 650 V
III. C OMPARISON
Based on the equations derived in section 2, simulations
and measurements of the three topologies VSI, ZSI and NPC
inverter are compared concerning their leakage currents, their
efficiency and their volume.
Simulations (figure 5) and measurements have shown that
the rms value of the leakage currents is for all three topologies
similar and meets the relevant standards as VDE 0126-1-1.
The simulated and measured efficiency is shown in 6 and 7.
To achieve comaprable results the semiconductors are rated to
operate at maximum load at 120◦ C junction temperature and
80◦ C heat sink temperature. No semiconductors are connected
in parallel. The measured efficiencies are for all topologies
lower than the simulated ones. For low power it could be
identified that the waveform of the efficiencies derivate for all Figure 7. Efficiency based on measurements with DEWETRON 2010,
topologies since the resistors to balance the dc link capacitors Accuracy 0.5% Vin = 525V
have been neglected in simulations. However they produce Table II
constant power losses of 10 W for the NPC and VSI and VOLUME
30 W for the ZSI. The volumes of the inverters are roughly
BC+NPC BC+VSI ZSI
compared in table II. The heat sink is designed according to Heat sink + 0 -
the maximum power losses as described in section II The NPC DC capacitance + + -
and VSI require the same number of dc link capacitors while Inductance dc link + + -
Inductance grid filter + 0 0
for the ZSI a high number parallel capacitors is necessary due

728
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