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Ex. No.: 3 Date: Design of Half - Adder and Full - Adder Circuits

This document describes the design of half-adder and full-adder circuits using ORCAD/PSpice simulation software. It includes the circuit diagrams and components required for a half-adder, which outputs the sum and carry functions of two input bits A and B, and a full-adder, which outputs the sum and carry functions for three input bits A, B, and C. The simulations are run for 4ms and 8ms to test the functionality of the half-adder and full-adder circuits respectively.

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adrijeet8deb
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194 views1 page

Ex. No.: 3 Date: Design of Half - Adder and Full - Adder Circuits

This document describes the design of half-adder and full-adder circuits using ORCAD/PSpice simulation software. It includes the circuit diagrams and components required for a half-adder, which outputs the sum and carry functions of two input bits A and B, and a full-adder, which outputs the sum and carry functions for three input bits A, B, and C. The simulations are run for 4ms and 8ms to test the functionality of the half-adder and full-adder circuits respectively.

Uploaded by

adrijeet8deb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Ex. No.

: 3 Date:
Design of Half – Adder and Full – Adder circuits
Aim:
Design of Half – Adder and Full – Adder circuits

Apparatus/Tool required:
ORCAD / PSpice simulator - > 7400 Library – 7408, 7432 & 7486
Source Library - Digclock
Simulation Settings: Analysis Type - Time Domain
Run to time: 4ms (for Half Adder)
Run to time: 8ms (for Full Adder)
Circuit Diagram:

Half – Adder Circuit

OFFTIME = 2mSDSTM1 U1A


ONTIME = 2mS CLK 1
DELAY = 3 S = A B
STARTVAL = 0 2
OPPVAL = 1
7486
OFFTIME = 1mSDSTM2
ONTIME = 1mS CLK
DELAY =
STARTVAL = 0
OPPVAL = 1
U2A
1
3 C = A . B
2

7408

Full – Adder Circuit

OFFTIME = 4mSDSTM3 U3A


ONTIME = 4mS CLK 1 U4A
DELAY = 3 1 S = A B C
STARTVAL = 0 2 3
OPPVAL = 1 2
7486
OFFTIME = 2mSDSTM4 7486
ONTIME = 2mS CLK
DELAY =
STARTVAL = 0
OPPVAL = 1 U6A
1
OFFTIME = 1mSDSTM5 3
ONTIME = 1mS CLK 2 C = (A  B).C + A·B
DELAY = U7A
STARTVAL = 0 7408 1
OPPVAL = 1 3
U5A 2
1
3 7432
2

7408

13

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