Experiment Half Adder and Full Adder
Experiment Half Adder and Full Adder
EXPERIMENT NO.
Title: Design & implementation of half adder and full adder circuit
using logic gates.
1
Department of Electrical and Electronics Engineering SOC
Electrical and Electronics Engineering Lab (FY)
EXPERIMENT NO.
AIM: Design & implementation of half adder and full adder circuit using logic gates.
Objective:
• To design, realize and verify the adder circuits using basic gates and universal gates.
• To design, realize and verify full adder using two half adders.
Components required:
IC 7404, IC 7408, IC 7486, and IC 7432, Patch cards and IC Trainer Kit
Theory:
Half-Adder:
A combinational logic circuit that performs the addition of two data bits, A and B, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is
the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C=AB
Full-Adder:
The half-adder does not take the carry bit from its previous stage into account. This carry bit from
its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and
B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the full-adder
are:
S = (A⊕ B) ⊕ Cin C = AB+BCin+ACin
I. TO REALIZE HALF ADDER
2
Department of Electrical and Electronics Engineering SOC
Electrical and Electronics Engineering Lab (FY)
3
Department of Electrical and Electronics Engineering SOC
Electrical and Electronics Engineering Lab (FY)
Procedure:
• Check the components for their working
• Insert the appropriate IC into the IC base
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.
Conclusion
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4
Department of Electrical and Electronics Engineering SOC
Electrical and Electronics Engineering Lab (FY)
Questions
5
Department of Electrical and Electronics Engineering SOC