D D D D D D D: SN54HC541, SN74HC541 Octal Buffers and Line Drivers With 3-State Outputs
D D D D D D D: SN54HC541, SN74HC541 Octal Buffers and Line Drivers With 3-State Outputs
D D D D D D D: SN54HC541, SN74HC541 Octal Buffers and Line Drivers With 3-State Outputs
OE1
OE2
VCC
printed circuit board layout.
A2
A1
The 3-state outputs are controlled by a two-input
NOR gate. If either output-enable (OE1 or OE2) 3 2 1 20 19
A3 4 18 Y1
input is high, all eight outputs are in the Y2
A4 5 17
high-impedance state. The ’HC541 devices
A5 6 16 Y3
provide true data at the outputs.
A6 7 15 Y4
A7 8 14 Y5
9 10 11 12 13
A8
Y8
Y7
Y6
GND
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube SN74HC541N SN74HC541N
Tube SN74HC541DW
SOIC – DW HC541
Tape and reel SN74HC541DWR
–40°C to 85°C SOP – NS Tape and reel SN74HC541NSR HC541
SSOP – DB Tape and reel SN74HC541DBR HC541
Tube SN74HC541PW
TSSOP – PW HC541
Tape and reel SN74HC541PWR
CDIP – J Tube SNJ54HC541J SNJ54HC541J
–55°C to 125°C CFP – W Tube SNJ54HC541W SNJ54HC541W
LCCC – FK Tube SNJ54HC541FK SNJ54HC541FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.
FUNCTION TABLE
(each buffer/driver)
INPUTS OUTPUT
OE1 OE2 A Y
L L L L
L L H H
H X X Z
X H X Z
2 18
A1 Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
VCC
Input 50% 50%
0V
tPLH tPHL
In-Phase VOH
90% 90%
Output 50% 50%
10% 10% V
OL
tr tf Output
Control VCC
tPHL tPLH
VOH (Low-Level 50% 50%
Out-of-Phase 90% 90% Enabling) 0V
50% 50%
Output 10% 10% tPZL tPLZ
VOL
tf tr Output ≈VCC ≈VCC
Waveform 1 50%
VOLTAGE WAVEFORMS
(See Note B) 10% VOL
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
tPZH tPHZ
VCC Output VOH
Input 90% 90% 90%
50% 50% Waveform 2 50%
10% 10% 0 V
(See Note B) ≈0 V
tr tf
PINS **
14 16 20
DIM
0.100 (2,54)
0.020 (0,51) MIN A
0.070 (1,78)
0.023 (0,58)
0.015 (0,38) 0°–15°
4040083/E 03/99
NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
4040140 / D 10/96
PINS **
14 16 18 20
DIM
1 8
0.070 (1,78) MAX
0.325 (8,26)
0.035 (0,89) MAX 0.020 (0,51) MIN
0.300 (7,62)
0.015 (0,38)
Seating Plane
0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
16 9
0.419 (10,65)
0.400 (10,15)
0.299 (7,59) 0.010 (0,25) NOM
0.291 (7,39)
Gage Plane
0.010 (0,25)
1 8
0°– 8° 0.050 (1,27)
A 0.016 (0,40)
Seating Plane
0.012 (0,30)
0.104 (2,65) MAX 0.004 (0,10)
0.004 (0,10)
PINS **
16 18 20 24 28
DIM
4040000/E 08/01
0,51
1,27 0,25 M
0,35
14 8
0,15 NOM
5,60 8,20
5,00 7,40
Gage Plane
1 7 0,25
Seating Plane
PINS **
14 16 20 24
DIM
4040062 / B 02/95
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
PINS **
14 16 20 24 28 30 38
DIM
4040065 /E 12/01
0,30
0,65 0,10 M
0,19
14 8
0,15 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
1 7
0°– 8°
A 0,75
0,50
Seating Plane
PINS **
8 14 16 20 24 28
DIM
4040064/F 01/97
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