P5.

1 COMBINATIONAL BLOCKS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
1 INPUT SELECTION P5.1

Combinational circuit: 
to_reg is a function of instruction, 
IN0, ∙∙∙ , IN7 and result. 
Functional specification
loop
instruction input_control
case instruction is
ASSIGN_VALUE 00
when (ASSIGN_VALUE, k, A) => 
DATA_INPUT 01
to_reg := A;
OPERATION 10
when (DATA_INPUT, k, j) => 
others ‐‐
to_reg := IN(j);
when (OPERATION, i, j, k, f) =>  control signals
to_reg := result;
when others => 
to_reg := don't care;
end case;
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end loop;
(input selection) P5.1
instruction input_control
ASSIGN_VALUE 00
DATA_INPUT 01
OPERATION 10
others ‐‐
loop
case input_control is
Functional specification
loop when 00 => 
case instruction is to_reg := A;
when (ASSIGN_VALUE, k, A) =>  when 01 => 
to_reg := A; to_reg := IN(j);
when (DATA_INPUT, k, j) =>  when 10 => 
to_reg := IN(j); to_reg := result;
when (OPERATION, i, j, k, f) => 
when 11 => 
to_reg := result;
when others =>  to_reg := don't care;
to_reg := don't care; end case;
end case; end loop;
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end loop;
(input selection) P5.1
straightforward implementation:

loop
case input_control is
when 00 => 
to_reg := A;
when 01 => 
to_reg := IN(j);
when 10 => 
to_reg := result;
when 11 => 
to_reg := don't care;
end case;
end loop;
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(input selection: VHDL model) P5.1
package main_parameters is
constant m: natural := 8; ‐‐ m‐bit processor
end main_parameters;

library IEEE; use IEEE.std_logic_1164.all;

use work.main_parameters.all;
entity input_selection is
port (
IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7: 
in std_logic_vector(m‐1 downto 0);
A, result: in std_logic_vector(m‐1 downto 0);
j: in std_logic_vector(2 downto 0);
input_control: in std_logic_vector(1 downto 0);
to_reg: out std_logic_vector(m‐1 downto 0)
);
end input_selection;
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(input selection: VHDL model) P5.1

architecture structure of input_selection is
signal selected_port: std_logic_vector(m‐1 downto 0);
begin
first_mux: process(j, IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7)
begin
case j is
when "000" => selected_port <= IN0;
when "001" => selected_port <= IN1;
∙∙∙
when "110" => selected_port <= IN6;
when others => selected_port <= IN7;
end case;
end process;
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(input selection: VHDL model) P5.1

second_mux: 
process(input_control, A, selected_port, result)
begin
case input_control is
when "00" => to_reg <= A;
when "01" => to_reg <= selected_port;
when "10" => to_reg <= result;
when others => to_reg <= (others => '0');
end case;
end process;
end structure;
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 2 COMPUTATION RESOURCES P5.1

VHDL model:

library ieee; use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all; 
Functional specification use ieee.std_logic_unsigned.all;
if f = 0 then result := left_in + right_in; use work.main_parameters.all;
else result := left_in ‐ right_in; entity computation_resources is
end if; port (
left_in, right_in: in std_logic_vector(m‐1 downto 0);
f: in std_logic;
Combinational circuit:  result: out std_logic_vector(m‐1 downto 0)
result is a function of f, left_in and right_in.  );
(an adder / subtractor) end computation_resources;

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 (computation resources: VHDL model) P5.1

architecture behavior of computation_resources is

begin
Functional specification
process(f, left_in, right_in)
if f = 0 then result := left_in + right_in;
begin
else result := left_in ‐ right_in;
if f = '0' then result <= left_in + right_in;
end if;
else result <= left_in ‐ right_in;
end if;
end process;
end behavior;

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SUMMARY P5.1

 VHDL models of combinational blocks:
 input selection,
 computation resources.

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P5.2 SEQUENTIAL BLOCKS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
1 OUTPUT SELECTION P5.2

Sequential circuit: 
OUT0, ∙∙∙ , OUT7 are registered outputs. 
Functional specification
loop
case program(number) is
when (DATA_OUTPUT, i, j) =>  instruction out_en out_sel
OUT(i) := reg; DATA_OUTPUT 1 1
when (OUTPUT_VALUE, i, A) =>  OUTPUT_VALUE 1 0
OUT(i) := A;        others 0 ‐
end case;
end loop; control signals

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(output selection) P5.2
instruction out_en out_sel
DATA_OUTPUT 1 1
OUTPUT_VALUE 1 0
others 0 ‐

Functional specification loop
loop case (out_en, out_sel) is
case program(number) is when 11 => 
when (DATA_OUTPUT, i, j) => 
OUT(i) := reg;
OUT(i) := reg;
when (OUTPUT_VALUE, i, A) =>  when 10 => 
OUT(i) := A;        OUT(i) := A;       
end case; when others => 
end loop; null;       
end case;
end loop;
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(output selection) P5.2
straightforward implementation:

loop
case (out_en, out_sel) is
when 11 => 
OUT(i) := reg;
when 10 => 
OUT(i) := A;       
when others => 
null;       
end case;
end loop;
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(output selection: VHDL model) P5.2

library ieee; use ieee.std_logic_1164.all;

use work.main_parameters.all;
entity output_selection is
port (
A, reg: in std_logic_vector(m‐1 downto 0);
clk, out_en, out_sel: in std_logic;
i: in std_logic_vector(2 downto 0);
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7: 
out std_logic_vector(m‐1 downto 0)  
);
end output_selection;

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(output selection: VHDL model) P5.2
architecture structure of output_selection is
signal EN: std_logic_vector(0 to 7);
signal DEC_OUT: std_logic_vector(0 to 7); 
signal to_ports: std_logic_vector(m‐1 downto 0); 
begin
decoder: process(i)
begin
case i is
when "000" => DEC_OUT <= "10000000"; 
when "001" => DEC_OUT <= "01000000"; 
∙     ∙∙∙∙∙
when "110" => DEC_OUT <= "00000010"; 
when others => DEC_OUT <= "00000001"; 
end case;
end process;
and_gate: process(DEC_OUT, out_en)
begin
for i in 0 to 7 loop EN(i) <= DEC_OUT(i) AND out_en; 
end loop;
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end process;  
(output selection: VHDL model) P5.2

multiplexer: process(out_sel, A, reg)
begin
if out_sel = '0' then to_ports <= A;
else to_ports <= reg;  end if;
end process;
output_registers: process(clk)
begin
to_ports
if clk'event and clk = '1' then
case EN is
when "10000000" => OUT0 <= to_ports;
when "01000000" => OUT1 <= to_ports;
∙∙∙∙∙∙∙∙∙∙
when "00000001" => OUT7 <= to_ports;
when others => null;
end case;
end if;
end process;
end structure; 17
SUMMARY P5.2

 VHDL model of a sequential:
 output selection.

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