Branch instructions (2)

* When executing the instruction, the processor:

• shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
* Execution then continues from the new PC, once the pipeline has been
refilled.
* The "Branch with link" instruction implements a subroutine call by
writing PC-4 into the LR of the current bank.
• i.e. the address of the next instruction following the branch with link
(allowing for the pipeline).
* To return from subroutine, simply need to restore the PC from the LR:
• MOV pc, lr
• Again, pipeline has to refill before execution continues.
* The "Branch" instruction does not affect LR.
* Note: Architecture 4T offers a further ARM branch instruction, BX
• See Thumb Instruction Set Module for details.

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 Data processing Instructions
* Largest family of ARM instructions, all sharing the same instruction
format.
* Contains:
• Arithmetic operations
• Comparisons (no results - just set condition codes)
• Logical operations
• Data movement between registers
* Remember, this is a load / store architecture
• These instruction only work on registers, NOT memory.
* They each perform a specific operation on one or two operands.
• First operand always a register - Rn
• Second operand sent to the ALU via barrel shifter.
* We will examine the barrel shifter shortly.

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 Arithmetic Operations
* Operations are:
• ADD operand1 + operand2
• ADC operand1 + operand2 + carry
• SUB operand1 - operand2
• SBC operand1 - operand2 + carry -1
• RSB operand2 - operand1
• RSC operand2 - operand1 + carry - 1
* Syntax:
• <Operation>{<cond>}{S} Rd, Rn, Operand2
* Examples
• ADD r0, r1, r2
• SUBGT r3, r3, #1
• RSBLES r4, r5, #5

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 Comparisons
* The only effect of the comparisons is to
• UPDATE THE CONDITION FLAGS. Thus no need to set S bit.
* Operations are:
• CMP operand1 - operand2, but result not written
• CMN operand1 + operand2, but result not written
• TST operand1 AND operand2, but result not written
• TEQ operand1 EOR operand2, but result not written
* Syntax:
• <Operation>{<cond>} Rn, Operand2
* Examples:
• CMP r0, r1
• TSTEQ r2, #5

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 Logical Operations
* Operations are:
• AND operand1 AND operand2
• EOR operand1 EOR operand2
• ORR operand1 OR operand2
• BIC operand1 AND NOT operand2 [ie bit clear]
* Syntax:
• <Operation>{<cond>}{S} Rd, Rn, Operand2
* Examples:
• AND r0, r1, r2
• BICEQ r2, r3, #7
• EORS r1,r3,r0

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 Data Movement
* Operations are:
• MOV operand2
• MVN NOT operand2
Note that these make no use of operand1.
* Syntax:
• <Operation>{<cond>}{S} Rd, Operand2
* Examples:
• MOV r0, r1
• MOVS r2, #10
• MVNEQ r1,#0

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 Quiz #2
Start
* Convert the GCD
algorithm given in this
flowchart into
r0 = r1 Yes Stop 1) “Normal” assembler,
? where only branches can
be conditional.
No
2) ARM assembler, where
all instructions are
Yes r0 > r1 No
conditional, thus
? improving code density.

r0 = r0 - r1 r1 = r1 - r0 * The only instructions you

need are CMP, B and SUB.

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 Quiz #2 - Sample Solutions
“Normal” Assembler

gcd cmp r0, r1 ;reached the end?

beq stop
blt less ;if r0 > r1
sub r0, r0, r1 ;subtract r1 from r0
bal gcd
less sub r1, r1, r0 ;subtract r0 from r1
bal gcd
stop

ARM Conditional Assembler

gcd cmp r0, r1 ;if r0 > r1

subgt r0, r0, r1 ;subtract r1 from r0
sublt r1, r1, r0 ;else subtract r0 from r1
bne gcd ;reached the end?

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 The Barrel Shifter
* The ARM doesn’t have actual shift instructions.

* Instead it has a barrel shifter which provides a mechanism to carry out

shifts as part of other instructions.

* So what operations does the barrel shifter support?

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 Barrel Shifter - Left Shift
* Shifts left by the specified amount (multiplies by powers of two) e.g.
LSL #5 = multiply by 32

Logical Shift Left (LSL)

CF Destination 0

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 Barrel Shifter - Right Shifts
Logical Shift Right
Logical Shift Right
•Shifts right by the
specified amount
(divides by powers of ...0 Destination CF
two) e.g.
LSR #5 = divide by 32

Arithmetic Shift Right Arithmetic Shift Right

•Shifts right (divides by
powers of two) and
preserves the sign bit, Destination CF
for 2's complement
operations. e.g. Sign bit shifted in
ASR #5 = divide by 32

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 Barrel Shifter - Rotations
Rotate Right (ROR) Rotate Right
• Similar to an ASR but the
bits wrap around as they
leave the LSB and appear as Destination CF
the MSB.
e.g. ROR #5
• Note the last bit rotated is
also used as the Carry Out.

Rotate Right Extended (RRX)

Rotate Right through Carry
• This operation uses the
CPSR C flag as a 33rd bit.
• Rotates right by 1 bit. Destination CF
Encoded as ROR #0.

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 Using the Barrel Shifter:
The Second Operand
Operand Operand * Register, optionally with shift
1 2 operation applied.
* Shift value can be either be:
• 5 bit unsigned integer
• Specified in bottom byte of
Barrel another register.
Shifter
* Immediate value
• 8 bit number
• Can be rotated right through
an even number of
ALU positions.
• Assembler will calculate
rotate for you from
constant.
Result
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