RT9218

5V/12V Synchronous Buck PWM DC-DC and Linear Power

Controller
General Description Features
The RT9218 is a dual output with one synchronous buck z Operating with 5V or 12V Supply Voltage
PWM and one linear controller. The part is proposed to z Drives All Low Cost N-MOSFETs
generate logic-supply voltages for PC based systems. The z Voltage Mode PWM Control
high-performance device includes internal soft-start, z 300kHz Fixed Frequency Oscillator
frequency-compensation networks, power good signaling z Fast Transient Response :
with specific sequence, and it comes all of the logic control, `High-Speed GM Amplifier
output adjustment, power monitoring and protection `Full 0 to 100% Duty Ration
functions into a small footprint package. The part is z Internal Soft-Start
operated at fixed 300kHz frequeny providing an optimum z Power Good Indicator
compromise between efficiency, external component size, z Adaptive Non-Overlapping Gate Driver
and cost. The linear controller is implemented to drive an z Over-Current Fault Monitor on MOSFET, No Current
external MOSFET for regulation and it's adjustable by Sense Resistor Required
setting external resistors. Moreover the specific internal z Specific power good indicator for Intel®
PGOOD sequence and indicator is also implemented to Grantsdale FSB_VTT power sequence
conform to Intel® new platform requirement on FSB_VTT z RoHS Compliant and 100% Lead (Pb)-Free
power plane. An adjustable over-current protection (OCP)
is proposed to monitor the voltage drop across the
Applications
RDS(ON) of the lower MOSFET for synchronous buck z Graphic Card
PWM DC-DC controller. z Motherboard, Desktop Servers
z IA Equipments
Ordering Information z Telecomm Equipments
RT9218 z High Power DC-DC Regulators
Package Type
S : SOP-14 Pin Configurations
Operating Temperature Range
P : Pb Free with Commercial Standard
(TOP VIEW)
G : Green (Halogen Free with Commer-
cial Standard)
BOOT 14 PHASE
UGATE 2 13 OPS
Note :
GND 3 12 FB
RichTek Pb-free and Green products are : LGATE 4 11 VCC
`RoHS compliant and compatible with the current require- DRV 5 10 PGOOD
NC 6 9 FBL
ments of IPC/JEDEC J-STD-020. NC 7 8 NC
`Suitable for use in SnPb or Pb-free soldering processes.
SOP-14
`100% matte tin (Sn) plating.

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RT9218
Typical Application Circuit

VIN VCC VCC

5 to 12V 12V D1 RBOOT C8 12V
1N4148 2.2 0.1uF
PHASE

C1 to C2 C3 to C4 C7 RT9218
1000uF x 2 1uF x 2 RUGATE 1uF R3 ROCSET
1 BOOT 14 10R
Q1 PHASE
SVOUT 2.2
L1 MU 2 UGATE 13
OPS
PHASE 3 12
GND FB Q4 Disable
2.2uH
R Q2 4 11 3904
LGATE VCC C10
C5 to C6 ML 1uF
1000uF x 2 C 5 DRV PGOOD 10
6 9
NC FBL
7 8
NC NC
Q3

R1
LVOUT
4k R2
C9 8k R4 C11
470uF 1k/NC 0.1uF/NC R6

R5 32R

68R

SVOUT = VREF × (1 + R5 )
R6
LVOUT = VREF × (1 + R1 )
R2
VREF : Internal reference voltage
(0.8V ± 2%)

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 RT9218
Functional Pin Description
UGATE (Pin 2) VCC (Pin 11)
Upper gate driver output. Connect to gate of the high- Connect this pin to a well-decoupled 5V or 12V bias
side power N-MOSFET. This pin is monitored by the supply. It is also the positive supply for the lower gate
adaptive shoot-through protection circuitry to determine driver, LGATE.
when the upper MOSFET has turned off.
GND (Pin 3)
BOOT (Pin 1) Both signal and power ground for the IC. All voltage levels
Bootstrap supply pin for the upper gate driver. Connect are measured with respect to this pin. Ties the pin directly
the bootstrap capacitor between BOOT pin and the PHASE to the low-side MOSFET source and ground plane with
pin. The bootstrap capacitor provides the charge to turn the lowest impedance.
on the upper MOSFET.
DRV (Pin 5)
PHASE (Pin 14) Connect this pin to the base/gate of an external transistor/
Connect this pin to the source of the upper MOSFET and MOSFET. This pin provides the drive for the linear
the drain of the lower MOSFET. regulator's pass transistor/MOSFET.

OPS (OCSET, POR and Shut-Down) (Pin 13) FBL (Pin 9)

This pin provides multi-function of the over-current setting, Linear regulator feedback voltage. This pin is the inverting
UGATE turn-on POR sensing, and shut-down features. input of the error amplifier and protection monitor. Connect
Connecting a resistor (ROCSET) between OPS and PHASE this pin to the external resistor divider network of the linear
pins sets the over-current trip point. regulator.
Pulling the pin to ground resets the device and all external
PGOOD (Pin 10)
MOSFETs are turned off allowing the output voltage power
rails to float. PGOOD is an open-drain output used to indicate that the
regulator is within normal operating voltage ranges and
This pin is also used to detect VIN in power on stage and
it's implemented with a specific sequence as following
issues an internal POR signal.
chart.
LGATE (Pin 4)
NC (Pin 6,7,8)
Lower gate drive output. Connect to gate of the low-side
No internal connection.
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.

FB (Pin 12)
Switcher feedback voltage. This pin is the inverting input
of the error amplifier. FB senses the switcher output
through an external resistor divider network.

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RT9218
Function Block Diagram
VCC

EN +
- 0.15V

PH_M +
Bias & Regulators Power On
Reference - 1.5V
(3V_Logic & 3VDD_Analog) Reset
0.8VREF
3V

0.64V + UV_S 40uA

VCC Soft-Start
-
&
+ Fault Logic OC - OPS
DRV 0.64V + UV_L 0.4V
- +
-
+
FBL -

PGOOD
BOOT

UGATE

PHASE
+ EO
+GM + Gate Control
FB - +
- Logic
VCC

LGATE
Oscillator
(300k/600kHz)

GND

Timing Diagram

Specific Power Sequence for LDO

90%
80%

FSB_VTT (1.2V @ 5Amp) 1-10ms

VTT_GD
<1ms

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 RT9218
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC -------------------------------------------------------------------------------------- 16V
z BOOT, VBOOT - VPHASE ------------------------------------------------------------------------------------ 16V

z PHASE to GND

DC ------------------------------------------------------------------------------------------------------------- −5V to 15V

< 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V
z BOOT to PHASE ------------------------------------------------------------------------------------------ 15V

z BOOT to GND

DC ------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V

< 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V
z UGATE ------------------------------------------------------------------------------------------------------- VPHASE − 0.3V to VBOOT + 0.3V

z LGATE ------------------------------------------------------------------------------------------------------- GND − 0.3V to VVCC + 0.3V

z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V

z Package Thermal Resistance (Note 4)

SOP-14, θJA ------------------------------------------------------------------------------------------------- 127.67°C/W

z Junction Temperature ------------------------------------------------------------------------------------- 150°C

z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C

z Storage Temperature Range ---------------------------------------------------------------------------- −40°C to 150°C

z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV

MM (Machine Mode) -------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 3)

z Supply Voltage, VCC -------------------------------------------------------------------------------------- 5V ± 5%,12V ± 10%
z Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
VCC Supply Current
Nominal Supply Current ICC UGATE and LGATE Open -- 6 15 mA
Power-On Reset
POR Threshold VCCRTH VCC Rising -- 4.1 4.5 V
Hysteresis VCCHYS 0.35 0.5 -- V
Switcher Reference
Reference Voltage VREF VCC = 12V 0.784 0.8 0.816 V
Oscillator
Free Running Frequency fOSC VCC = 12V 250 300 350 kHz
Ramp Amplitude ΔVOSC -- 1.5 -- VP-P
To be continued

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RT9218
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier (GM)
E/A Transconductance gm -- 0.2 -- ms
Open Loop DC Gain AO -- 90 -- dB
Linear Regulator
DRV Driver Source IDS VDRV = 6V -- 1.4 -- mA
Reference Voltage VREFREG VCC = 12V 0.784 0.8 0.816 V
PWM Controller Gate Drivers (VCC = 12V)
VBOOT − VPHASE = 12V
Upper Gate Source IUGATE 0.6 1 -- A
VUGATE − VPHASE = 6V
VBOOT − VPHASE = 12V
Upper Gate Sink RUGATE -- 4 -- Ω
VUGATE − VPHASE = 1V
Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V 0.6 1 -- A
Lower Gate Sink RLGATE VCC = 12V, VLGATE = 1V -- 3 4 Ω
Dead Time TDT -- -- 100 ns
Protection
FB Under-Voltage Trip ΔFBUVT FB Falling 70 75 80 %
FBL Under-Voltage Trip ΔFBLUVT FB and FBL Falling 70 75 80 %
OC Current Source IOC VPHASE = 0V -- 40 -- μA
Soft-Start Interval TSS -- 3.5 -- ms
Power Good
Power Good Rising Threshold VCC = 12V -- 90 -- %

Power Good Hysteresis VCC = 12V -- 10 -- %

PG Sink Capability VCC = 12V, 1mA -- 0.2 0.4 V

Power Good Rising Delay VCC = 12V 1 3 10 ms

Power Good Falling Delay VCC = 12V -- 15 -- us

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.

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 RT9218
Typical Operating Characteristics
(VOUT = 2.5V, unless otherwise specified )
Efficiency vs. Output Current Efficiency vs. Output Current
1 1

0.95 0.95

0.9 0.9

Efficiency(%)
0.85 0.85
Efficiency(%)

0.8 0.8

0.75 0.75

0.7 0.7

0.65 VCC = 12V 0.65 VCC = 5V

VIN = 5V VIN = 5V
0.6 0.6
0 5 10 15 20 25 0 5 10 15 20 25
Output Current (A) Output Current (A)

Reference Voltage vs. Temperature Frequency vs. Temperature

0.812 350
VCC = 12V
0.81 VIN = 5V
330
Reference Voltage (V)

Frequency (kHz)

0.808

310
0.806

0.804 290

0.802
270
0.8

0.798 250
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -10 20 50 80 110 140
Temperature (°C) Temperature (°C)

POR vs. Temperature OCP

4.75

Rising
POR Rising or Falling (V)

4.5

(10V/Div)
4.25 UGATE

4 (10A/Div)
Falling

3.75 VCC = 12V, VIN = 5V

IL IOCSET= 20A
ROCSET = 15kΩ
3.5
-40 -10 20 50 80 110 140 Time (5us/Div)
Temperature (°C)

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RT9218

VCC Switching VCC Switching

(100mV/Div) (100mV/Div)

SVOUT SVOUT

IOUT IOUT
(10A/Div) (10A/Div)

UGATE UGATE

(20V/Div) (20V/Div)
V CC V CC
(10V/Div)
VCC = 12Vto 5V
IOUT= 10A (10V/Div) VCC = 5V to 12V
VIN = 5V IOUT= 10A, VIN = 5V

Time (10ms/Div) Time (10ms/Div)

Power On Power Off

V CC
(500mV/Div)
SVOUT
SV OUT

IOUT (2A/Div) V IN

UGATE
(10V/Div) UGATE

Time (500us/Div) Time (5ms/Div)

Dead Time (Rising) Dead Time (Falling)

VCC = VIN = 5V VCC = 12V
IOUT= 25A VIN = 5V
IOUT= 25A

UGATE
UGATE

PHASE
PHASE

LGATE LGATE

Time (25ns/Div) Time (10ns/Div)

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 RT9218

Transient Response (Rising) Transient Response (Falling)

L = 2.2uH
C = 2000uF
UGATE
UGATE (10V/Div)
(10V/Div)

SVOUT
(100mV/Div) SVOUT
(100mV/Div)
VCC = VIN = 12V
IOUT= 0A to 15A VCC = VIN = 12V
IL IOUT= 15A to 0A
IL f = 1/20ms
L = 2.2uH
(10A/Div) (10A/Div) SR = 2.5A/us
f = 1/20ms, SR = 2.5A/us C = 2000uF

Time (5us/Div) Time (25us/Div)

Soft Start & PGOOD

(1V/Div)
PGOOD

(500mV/Div)
SVOUT
(2A/Div)
IL

Time (10ms/Div)

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RT9218
Application Information
Inductor Selection According to Figure 1 the ripple current of inductor can be
The selection of output inductor is based on the calculated as follows :
considerations of efficiency, output power and operating ΔIL D V
VIN − VOUT = L ; Δt = ; D = OUT
frequency. Low inductance value has smaller size, but Δt fs VIN
results in low efficiency, large ripple current and high output VOUT
L = (VIN − VOUT ) × (1)
ripple voltage. Generally, an inductor that limits the ripple VIN × fs × ΔIL
current (ΔIL) between 20% and 50% of output current is Where :
appropriate. Figure 1 shows the typical topology of
VIN = Maximum input voltage
synchronous step-down converter and its related
waveforms. VOUT = Output Voltage

iS1 IL Δt = S1 turn on time

L
+ VL - ΔIL = Inductor current ripple
iC IOUT
iS2 + fS = Switching frequency
S1 VOR rC +
VIN S2
- RL VOUT D = Duty Cycle
+

+
VOC COUT - rC = Equivalent series resistor of output capacitor
-
Output Capacitor

TS The selection of output capacitor depends on the output

ripple voltage requirement. Practically, the output ripple
Vg1 TON TOFF voltage is a function of both capacitance value and the
equivalent series resistance (ESR) rC. Figure 2 shows
Vg2
the related waveforms of output capacitor.
VIN - VOUT
diL VIN-VOUT diL VOUT
iL =
VL dt L dt = L

- VOUT IOUT

TS

iL iC
IL = IOUT
ΔIL 1/2ΔIL
0 ΔIL

iS1 VOC

ΔVOC

iS2
VOR

ΔIL x rc
0

Figure 1. The waveforms of synchronous step-down

t1 t2
converter
Figure 2. The related waveforms of output capacitor
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 RT9218
The AC impedance of output capacitor at operating ZOUT is the shut impedance at the output node to ground
frequency is quite smaller than the load impedance, so (see Figure 3 and Figure 4),
the ripple current (ΔIL) of the inductor current flows mainly
through output capacitor. The output ripple voltage is GM VOUT
described as :
C1
ΔVOUT = ΔVOR + ΔVOC (2) C2
1 t2 R1
ΔVOUT = ΔIL × rc + ∫ ic dt (3)
CO t1
1 VOUT 2
ΔVOUT = ΔIL × ΔIL × rc + (1− D)T (4)
8 COL S
Figure 3. A Type 2 error-amplifier with shut network to
ground
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90 to 95% VOUT
of the output voltage ripple is contributed by the ESR of +
RO
+
output capacitor. So Equation (4) could be simplified as : EA+
EA- - GM
ΔVOUT = ΔIL x rc (5)

Users could connect capacitors in parallel to get calculated Figure 4. Equivalent circuit
ESR.
Pole and Zero :
Input Capacitor
The selection of input capacitor is mainly based on its FP = 1 ; FZ = 1
2π × R1C 2 2π × R1C1
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
We can see the open loop gain and the Figure 3 whole
the on time of S1 as shown in Figure 1. The RMS value of
loop gain in Figure 5.
ripple current flowing through the input capacitor is
described as :

Irms = IOUT D(1 − D) (A) (6)

Open Loop, Unloaded Gain

The input capacitor must be cable of handling this ripple

A Closed Loop, Unloaded Gain
Gain (dB)

current. Sometime, for higher efficiency the low ESR

capacitor is necessarily.
FZ FP

PWM Loop Stability Gain = GMR1

B
RT9218 is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
100 1000 10k 100k
Operational Transconductance Amplifier).
Frequency (Hz)
The transconductance : Figure 5. Gain with the Figure 2 circuit
dI
GM = OUT
dVm RT9218 internal compensation loop :
The mid-frequency gain :
GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF
dVOUT = dIOUT Z OUT = GMdVIN Z OUT
dVOUT
G= = GMZ OUT
dVIN

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RT9218
OPS (Over Current Setting, VIN_POR and Shutdown)
1.OCP
Sense the low-side MOSFET's RDS(ON) to set over-current trip point.
Connecting a resistor (ROCSET) from this pin to the source of the upper MOSFET and the drain of the lower MOSFET
sets the over-current trip point. ROCSET, an internal 40μA current source, and the lower MOSFET on resistance, RDS(ON),
set the converter over-current trip point (IOCSET) according to the following equation :
40uA × R OCSET − 0.4V
I OCSET =
R DS(ON) of the lower MOSFET

OPS pin function is similar to RC charging or discharging circuit, so the over-current trip point is very sensitive to
parasitic capacitance (ex. shut-down MOSFET) and the duty ratio.
Below Figures say those effect. And test conditions are Rocset = 15kΩ (over -current trip point = 20.6A), Low-side
MOSFET is IR3707.

OCP OCP

UGATE (10V/Div) UGATE

(10V/Div)

IL (10A/Div)
IL (10A/Div)
OPS (200mV/Div)

VIN = 5V, VCC = 12V VIN = 5V, VCC = 12V

VOUT = 1.5V VOUT = 1.5V

Time (5μs/Div) Time (5μs/Div)

OCP OCP
OPS
(200mV/Div)

UGATE (10V/Div)
UGATE
(10V/Div)

IL (10A/Div)

IL (10A/Div)

VIN = 12V, VCC = 12V VIN = 12V, VCC = 12V

VOUT = 1.5V VOUT = 1.5V

Time (2.5μs/Div) Time (2.5μs/Div)

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 RT9218
2. VIN_POR 1) Mode 1 (SS< Vramp_valley)
UGATE will continuously generate a 10kHz colck with Initially the COMP stays in the positive saturation. When
1% duty cycle before VIN is ready. VIN is recognized ready SS< VRAMP_Valley, there is no non-inverting input available
by detecting VOPS crossing 1.5V four times (rising & to produce duty width. So there is no PWM signal and
falling). ROCSET must be kept lower than 37.5kΩ for large VOUT is zero.
ROCSET will keep VOPS always higher than 1.5V. Figure 6 2) Mode 2 (VRAMP_Valley< SS< Cross-over)
shows the detail actions of OCP and POR. It is highly
When SS>VRAMP_Valley, SS takes over the non-inverting
recommend-ed that ROCSET be lower than 30kΩ.
input and produce the PWM signal and the increasing
3V
duty width according to its magnitude above the ramp
signal. The output follows the ramp signal, SS. However
40uA while VOUT increases, the difference between VOUT and
ROCSET
PHASE
SSE (SS − VGS) is reduced and COMP leaves the
-
OC 0.4V OPS
+ 10pF Q2 saturation and declines. The takeover of SS lasts until it
DISABLE
+ Cparasitic meets the COMP. During this interval, since the feedback
-
path is broken, the converter is operated in the open loop.
1st 2nd 3rd 4th OPS
VIN POR_H + waveform 3) Mode3 ( Cross-over< SS < VGS + VREF)
UGATE
PHASE_M -
1.5V (1) Internal Counter will count (VOPS > 1.5V)
four times (rising & falling) to recognize When the Comp takes over the non-inverting input for PWM
VIN is ready.
(2) ROCSET can　be set too large. Or can　
Amplifier and when SSE (SS − VGS) < VREF, the output of
detect VIN is ready (counter = 1, not equal 4) the converter follows the ramp input, SSE (SS − VGS).
Before the crossover, the output follows SS signal. And
Figure 6. OCP and VIN_POR actions
when Comp takes over SS, the output is expected to follow
3. Shutdown SSE (SS − VGS). Therefore the deviation of VGS is
Pulling low the OPS pin by a small single transistor can represented as the falling of VOUT for a short while. The
shutdown the RT9218 PWM controller as shown in typical COMP is observed to keep its decline when it passes the
application circuit. cross-over, which shortens the duty width and hence the
falling of VOUT happens.
Soft Start
Since there is a feedback loop for the error amplifier, the
A built-in soft-start is used to prevent surge current from output’ s response to the ramp input, SSE (SS − VGS) is
power supply input during power on. The soft-start voltage lower than that in Mode 2.
is controlled by an internal digital counter. It clamps the
4) Mode 4 (SS > VGS + VREF)
ramping of reference voltage at the input of error amplifier
and the pulse-width of the output driver slowly. The typical When SS > VGS + VREF, the output of the converter follows
soft-start duration is 3ms. the desired VREF signal and the soft start is completed
now.

COMP
VRAMP_Valley
Cross-over

SS_Internal

VCORE

SSE_Internal

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RT9218
Under Voltage Protection VIN_SW (5V/12V)

The voltage at FB and FBL pin is monitored and protected

against UV (under voltage). The UV threshold is the FB VIN_LDO (3.3V)
or FBL under 75%. UV detection has 30μs triggered delay.
When OC or UV_FBL is trigged, a hiccup restart
sequence will be initialized, as shown in Figure 7 Only 4
OPS_Disable
times of trigger are allowed to latch off. Hiccup is disabled
Shutdown Enable
during soft-start interval, but UV_FB has some difference
from OC and UV_FBL, it will always trigger VIN power
Figure 9. LDO power sequence
sensing after 4 times hiccup, as shown in Figure 8.
PWM Layout Considerations
COUNT = 1 COUNT = 2 COUNT = 3 COUNT = 4
4V MOSFETs switch very fast and efficiently. The speed with
Internal
SS

2V
which the current transitions from one device to another
0V
OVERLOAD
causes voltage spikes across the interconnecting
APPLIED impedances and parasitic circuit elements. The voltage
Inductor Current

spikes can degrade efficiency and radiate noise, that results

in over-voltage stress on devices. Careful component
0A
placement layout and printed circuit design can minimize
T0 T1 T2 T3 T4 the voltage spikes induced in the converter. Consider, as
TIME
an example, the turn-off transition of the upper MOSFET
Figure 7. UV and OC trigger hiccup mode prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
Power Off upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
UGATE
(20V/Div) interval. Careful component selections, layout of the
UV VIN Power
FB Sensing critical components, and use shorter and wider PCB traces
(500mV/Div)
help in minimizing the magnitude of voltage spikes.
VOUT
VIN There are two sets of critical components in a DC-DC
(2V/Div) converter using the RT9218. The switching power
components are most critical because they switch large
(2V/Div) amounts of energy, and as such, they tend to generate
IOUT = 2A
equally large amounts of noise. The critical small signal
Time (10ms/Div) components are those connected to sensitive nodes or
those supplying critical bypass current.
Figure 8, UV_FB trigger VIN power sensing
The power components and the PWM controller should
LDO Power Sequence be placed firstly. Place the input capacitors, especially
In VGA field, the MOSFET of LVOUT is sourced by external the high-frequency ceramic decoupling capacitors, close
voltage not by SVOUT. to the power switches. Place the output inductor and
This connection may trigger UV protection to shutdown output capacitors between the MOSFETs and the load.
RT9218, but using the typical application circuit won't have Also locate the PWM controller near by MOSFETs.
this issue. See figure 9 using OPS pin to control the power A multi-layer printed circuit board is recommended.
sequence.

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 RT9218
Figure 10 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each
of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common
voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on
the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the
PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the
surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal
routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source
of MOSFETs should be sized to carry 2A peak currents.

IQ1 IL

5V/12V VOUT
Q1

+
+

+
IQ2 LOAD
Q2
GND

LGATE VCC GND

UGATE RT9218
FB

Figure 10. The connections of the critical components in the converter

Below PCB gerber files are our test board for your reference :

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 RT9218

According to our test experience, you must still notice two items to avoid noise coupling :
1.The ground plane should not be separated.
2.VCC rail adding the LC filter is recommended.

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RT9218
Outline Dimension

A H
M

J B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 8.534 8.738 0.336 0.344
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050

14–Lead SOP Plastic Package

Richtek Technology Corporation Richtek Technology Corporation

Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com

www.richtek.com DS9218-08 March 2007

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