RT8279

5A, 36V, 500kHz Step-Down Converter

General Description Features
The RT8279 is a step-down regulator with an internal power z 5A Output Current
MOSFET. It achieves 5A of continuous output current over z Internal Soft-Start
a wide input supply range with excellent load and line z 110mΩ Ω Internal Power MOSFET Switch
regulation. Current mode operation provides fast transient z Internal Compensation Minimizes External Parts
response and eases loop stabilization. Count
z High Efficiency up to 90%
For protection, the RT8279 provides cycle-by-cycle current
z 25μμA Shutdown Mode
limiting and thermal shutdown protection. An adjustable
z Fixed 500kHz Frequency
soft-start reduces the stress on the input source at
z Thermal Shutdown
startup. In shutdown mode, the regulator draws only 25μA
z Cycle-by-Cycle Over Current Protection
of supply current.
z Wide 5.5V to 36V Operating Input Range
The RT8279 requires a minimum number of readily z Adjustable Output Voltage from 1.222V to 26V
available external components, providing a compact z Available In an SOP8 (Exposed Pad) Package
solution. The RT8279 is available in the SOP-8 (Exposed z RoHS Compliant and Halogen Free
Pad) package.
Applications
Ordering Information z Distributive Power Systems
RT8279
Package Type z Battery Charger
SP : SOP-8 (Exposed Pad-Option 1) z DSL Modems
Lead Plating System z Pre-regulator for Linear Regulators
G : Green (Halogen Free and Pb Free)
Pin Configurations
Note : (TOP VIEW)
Richtek products are : BOOT 8 SW
` RoHS compliant and compatible with the current require- NC 2 7 VIN
GND
ments of IPC/JEDEC J-STD-020. NC 3 6 GND
9
FB 4 5 EN
` Suitable for use in SnPb or Pb-free soldering processes.
SOP-8 (Exposed Pad)
Marking Information
RT8279GSP : Product Number
RT8279 YMDNN : Date Code
GSPYMDNN

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Typical Application Circuit

VIN 7 1
VIN BOOT
5.5V to 36V CIN CBOOT
4.7µF/ RT8279
10nF L1
Chip Enable 50V x 2
5 EN SW 8 VOUT
Open = Automatic D1
B550A CFF R1
Startup COUT
22µF x 2
6, 9 (Exposed Pad)
GND FB 4
R2

Table 1. Recommended Component Selection

VOUT (V) R1 (kΩ) R2 (kΩ) CFF (pF) L (μH) COUT (μF)
2.5 100 100 82 6.8 22 x 2
3.3 100 58.6 82 10 22 x 2
5 100 31.6 82 15 22 x 2
8 100 18 82 22 22 x 2

Functional Pin Description

Pin No. Pin Name Pin Function
High Side Gate Drive Boost Input. BOOT supplies the drive for the high side
1 BOOT N-MOSFET switch. Connect a 10nF or greater capacitor from SW to BOOT to
power the high side switch.
2, 3 NC No Internal Connection.
4 FB Feedback Input. The feedback threshold is 1.222V.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN
5 EN higher than 1.4V to turn on the regulator, lower than 0.4V to turn it off. For
automatic startup, leave EN unconnected.
6, Ground. The exposed pad must be soldered to a large PCB and connected to
GND
9 (Exposed Pad) GND for maximum power dissipation.
Power Input. A suitable large capacitor should be bypassed from VIN to GND to
7 VIN
eliminate noise on the input to the IC.
Power Switching Output. Note that a capacitor is required from SW to BOOT to
8 SW
power the high side switch.

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Function Block Diagram

VIN
Current Sense
Ramp Amplifier -
Generator +

BOOT

Oscillator
EN Regulator S
500kHz
Q Driver
+
R
-
Reference Error PWM SW
+ Amplifier Comparator
FB -
12k Bootstrap
30pF Control
400k

GND

13pF

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Absolute Maximum Ratings (Note 1)
z Supply Voltage, VIN ------------------------------------------------------------------------------------------ −0.3V to 40V
z Switching Voltage, SW ------------------------------------------------------------------------------------- −0.3V to VIN + 0.3V
z BOOT Voltage ------------------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)
z The Other Pins ------------------------------------------------------------------------------------------------ −0.3V to 6V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------- 15°C/W
z Junction Temperature ---------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
z Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Voltage, VIN ------------------------------------------------------------------------------------------ 5.5V to 36V
z Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 12V, TA = 25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Reference Voltage VREF 5.5V ≤ VIN ≤ 36V 1.202 1.222 1.239 V
High Side Switch-On Resistance RDS(ON)1 -- 110 160 mΩ
Low Side Switch-On Resistance RDS(ON)2 -- 10 15 Ω
High Side Switch Leakage VEN = 0V, VSW = 0V -- -- 10 μA
Current Limit ILIM Duty = 90%, VBOOT−SW = 4.8V 6 7.5 9 A
Oscillator Frequency fOSC 425 500 575 kHz
Short Circuit Frequency VFB = 0V -- 150 -- kHz
Maximum Duty Cycle DMAX VFB = 0.8V 85 90 95 %
Minimum On-Time tON -- 100 150 ns
Under Voltage Lockout Threshold
3.8 4.2 4.5 V
Rising
Under Voltage Lockout Threshold
-- 315 -- mV
Hysteresis
EN Threshold Logic-High VIH EN_hys = 350mV 1.4 -- --
V
Voltage Logic-Low VIL -- -- 0.4
Enable Pull Up Current -- 1 -- μA
Shutdown Current ISHDN VEN = 0V -- 25 45 μA
Quiescent Current IQ VEN = 2V, VFB = 1.5V -- 0.6 1 mA
Soft-Start Period CSS = 0.1μF 3 5 8.2 ms
Thermal Shutdown TSD -- 150 -- °C

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 RT8279
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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Typical Operating Characteristics
Efficiency vs. Output Current Reference Voltage vs. Input Voltage
100 1.230
90
80 VIN = 12V 1.226

Reference Voltage (V)

70 VIN = 32V
VIN = 36V
Efficiency (%)

60 1.222
50
40 1.218
30
20 1.214
10
VOUT = 5V VOUT = 5V, IOUT = 0A
0 1.210
0 1 2 3 4 5 4 8 12 16 20 24 28 32 36
Output Current (A) Input Voltage (V)

Reference Voltage vs. Temperature Output Voltage vs. Output Current

1.230 5.008

1.228 5.004
5.000
1.226
Reference Voltage (V)

4.996 VIN = 36V

Output Voltage (V)

1.224 VIN = 24V

4.992
VIN = 12V
1.222 4.988
1.220 VIN = 12V 4.984
VIN = 24V 4.980
1.218 VIN = 36V
4.976
1.216
4.972
1.214
4.968
1.212 4.964
IOUT = 0A VOUT = 5V
1.210 4.960
-50 -25 0 25 50 75 100 125 0 1 2 3 4 5
Temperature (°C) Output Current (A)

Frequency vs. Input Voltage Frequency vs. Temperature

540 540

530 530

520 520
Frequency (kHz)
Frequency (kHz)

510 510

500 500

490 490

480 480

470 470 VIN = 12V

VIN = 24V
460 460
VIN = 36V
450 450
VOUT = 5V, IOUT = 0A VOUT = 5V
440 440
4 8 12 16 20 24 28 32 36 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

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Current Limit vs. Temperature Shutdown Current vs. Input Voltage

12 60

11 50

Shutdown Current (μA)

10
Current Limit (A)

40
9
30
8
20
7

6 10

VIN = 12V VEN = 0V

5 0
-50 -25 0 25 50 75 100 125 4 8 12 16 20 24 28 32 36
Temperature (°C) Input Voltage (V)

Quiescent Current vs. Temperature Load Transient Response

1
0.9
Quiescent Current (mA)

0.8 VOUT
(200mV/Div)
0.7
0.6
0.5 VIN = 36V
VIN = 24V
0.4 VIN = 12V
0.3
0.2 IOUT
0.1 (2A/Div)
VIN = 12V, VOUT = 5V, IOUT = 0.2A to 5A
0
-50 -25 0 25 50 75 100 125 Time (100μs/Div)
Temperature (°C)

Load Transient Response Switching

VOUT VOUT
(200mV/Div) (10mV/Div)

VSW
(10V/Div)

IOUT IL
(2A/Div) (5A/Div)
VIN = 12V, VOUT = 5V, IOUT = 2.5A to 5A VIN = 12V, VOUT = 5V, IOUT = 5A

Time (100μs/Div) Time (1μs/Div)

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Power On from EN Power Off from EN

VEN VEN
(5V/Div) (5V/Div)

VOUT VOUT
(5V/Div) (5V/Div)

IL IL
(5A/Div) (5A/Div)

VIN = 12V, VOUT = 5V, IOUT = 5A VIN = 12V, VOUT = 5V, IOUT = 5A

Time (2.5ms/Div) Time (2.5ms/Div)

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Application Information
The RT8279 is an asynchronous high voltage buck Soft-Start
converter that can support the input voltage range from The RT8279 contains an internal soft-start clamp that
5.5V to 32V and the output current can be up to 5A. gradually raises the output voltage. The typical soft-start
time is 5ms.
Output Voltage Setting
The resistive divider allows the FB pin to sense the output Chip Enable Operation
voltage as shown in Figure 1.
The EN pin is the chip enable input. Pull the EN pin low
(<0.4V) will shutdown the device. During shutdown mode,
VOUT
the RT8279 quiescent current drops to lower than 25μA.
Drive the EN pin to high (>1.4V, <5.5V) will turn on the
R1
FB
device again. If the EN pin is open, it will be pulled to high
by internal circuit. For external timing control (e.g.RC),the
RT8279 R2
EN pin can also be externally pulled to High by adding a
GND
100kΩ or greater resistor from the VIN pin (see Figure 3).
Figure 1. Output Voltage Setting
Inductor Selection
The inductor value and operating frequency determine the
The output voltage is set by an external resistive divider
ripple current according to a specific input and output
according to the following equation :
voltage. The ripple current ΔIL increases with higher VIN
VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ and decreases with higher inductance.
⎝ R2 ⎠
ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥
V V
Where VREF is the reference voltage (1.222V typ.).
⎣ f × L ⎦ ⎣ VIN ⎦
Where R1 = 100kΩ.
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
External Bootstrap Diode
ripple. High frequency with small ripple current can achieve
Connect a 10nF low ESR ceramic capacitor between the
highest efficiency operation. However, it requires a large
BOOT pin and SW pin. This capacitor provides the gate
inductor to achieve this goal.
driver voltage for the high side MOSFET.
For the ripple current selection, the value of ΔIL = 0.2(IMAX)
It is recommended to add an external bootstrap diode
will be a reasonable starting point. The largest ripple
between an external 5V and BOOT pin for efficiency
current occurs at the highest VIN. To guarantee that the
improvement when input voltage is lower than 5.5V or duty
ripple current stays below the specified maximum, the
ratio is higher than 65% .The bootstrap diode can be a
inductor value should be chosen according to the following
low cost one such as IN4148 or BAT54. The external 5V
equation :
can be a 5V fixed input from system or a 5V output of the
RT8279. ⎡ VOUT ⎤ ⎡ VOUT ⎤
L =⎢ ⎥ × ⎢1 − ⎥
⎣ f × Δ IL(MAX) ⎦ ⎣ VIN(MAX) ⎦
5V

The inductor's current rating (caused a 40°C temperature

rising from 25°C ambient) should be greater than the
BOOT
maximum load current and its saturation current should
RT8279 10nF
be greater than the short circuit peak current limit. Please
SW
see Table 2 for the inductor selection reference.

Figure 2. External Bootstrap Diode

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Table 2. Suggested Inductors for Typical The output ripple, ΔVOUT , is determined by :

ΔVOUT ≤ ΔIL ⎡⎢ESR + 1 ⎤

Application Circuit
Component Dimensions ⎣ 8fCOUT ⎦⎥
Series
Supplier (mm) The output ripple will be highest at the maximum input
TAIYO
NR10050 10 x 9.8 x 5 voltage since ΔIL increases with input voltage. Multiple
YUDEN
capacitors placed in parallel may be needed to meet the
TDK SLF12565 12.5 x 12.5 x 6.5
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
Diode Selection capacitors are all available in surface mount packages.
When the power switch turns off, the path for the current Special polymer capacitors offer very low ESR value.
is through the diode connected between the switch output However, it provides lower capacitance density than other
and ground. This forward biased diode must have a types. Although Tantalum capacitors have the highest
minimum voltage drop and recovery times. Schottky diode capacitance density, it is important to only use types that
is recommended and it should be able to handle those pass the surge test for use in switching power supplies.
current. The reverse voltage rating of the diode should be Aluminum electrolytic capacitors have significantly higher
greater than the maximum input voltage, and current rating ESR. However, it can be used in cost-sensitive applications
should be greater than the maximum load current. For for ripple current rating and long term reliability
more detail please refer to Table 4. considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
CIN and COUT Selection and audible piezoelectric effects. The high Q of ceramic
The input capacitance, C IN, is needed to filter the capacitors with trace inductance can also lead to significant
trapezoidal current at the source of the high side MOSFET. ringing.
To prevent large ripple current, a low ESR input capacitor
Higher values, lower cost ceramic capacitors are now
sized for the maximum RMS current should be used. The
becoming available in smaller case sizes. Their high ripple
RMS current is given by :
current, high voltage rating and low ESR make them ideal
V VIN for switching regulator applications. However, care must
IRMS = IOUT(MAX) OUT −1
VIN VOUT be taken when these capacitors are used at input and
This formula has a maximum at VIN = 2VOUT, where output. When a ceramic capacitor is used at the input
I RMS = I OUT/2. This simple worst-case condition is and the power is supplied by a wall adapter through long
commonly used for design because even significant wires, a load step at the output can induce ringing at the
deviations do not offer much relief. input, VIN. At best, this ringing can couple to the output
Choose a capacitor rated at a higher temperature than and be mistaken as loop instability. At worst, a sudden
required. Several capacitors may also be paralleled to inrush of current through the long wires can potentially
meet size or height requirements in the design. cause a voltage spike at VIN large enough to damage the
part.
For the input capacitor, two 4.7μF low ESR ceramic
capacitors are recommended. For the recommended Checking Transient Response
capacitor, please refer to table 3 for more detail. The regulator loop response can be checked by looking
The selection of COUT is determined by the required ESR at the load transient response. Switching regulators take
to minimize voltage ripple. several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
Moreover, the amount of bulk capacitance is also a key
equal to ΔILOAD (ESR) also begins to charge or discharge
for COUT selection to ensure that the control loop is stable.
COUT generating a feedback error signal for the regulator
Loop stability can be checked by viewing the load transient
to return VOUT to its steady-state value. During this
response as described in a later section.

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 RT8279
recovery time, VOUT can be monitored for overshoot or snubber between SW and GND and make them as close
ringing that would indicate a stability problem. as possible to the SW pin (see Figure 3). Another method
is to add a resistor in series with the bootstrap
EMI Consideration capacitor, CBOOT. But this method will decrease the driving
Since parasitic inductance and capacitance effects in PCB capability to the high side MOSFET. It is strongly
circuitry would cause a spike voltage on SW pin when recommended to reserve the R-C snubber during PCB
high side MOSFET is turned-on/off, this spike voltage on layout for EMI improvement. Moreover, reducing the SW
SW may impact on EMI performance in the system. In trace area and keeping the main power in a small loop will
order to enhance EMI performance, there are two methods be helpful on EMI performance. For detailed PCB layout
to suppress the spike voltage. One is to place an R-C guide, please refer to the section of Layout Consideration.

RBOOT*
VIN 7 1
VIN BOOT
5.5V to 32V CIN CBOOT L
REN* 4.7µF x 2 RT8279
10nF 10µH VOUT
SW 8
5 EN 5V/5A
RS* D
CEN* B550C R1 COUT
CS* 10k
47µFx2
6, 9 (Exposed Pad)
GND FB 4 (POSCAP)
R2
3.16k
* : Optional

Figure 3. Reference Circuit with Snubber and Enable Timing Control

Thermal Considerations
For continuous operation, do not exceed the maximum P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
operation junction temperature. The maximum power (min.copper area PCB layout)
dissipation depends on the thermal resistance of IC PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W (70mm2
package, PCB layout, the rate of surroundings airflow and copper area PCB layout)
temperature difference between junction to ambient. The
The thermal resistance θJA of SOP-8 (Exposed Pad) is
maximum power dissipation can be calculated by following
determined by the package architecture design and the
formula :
PCB layout design. However, the package architecture
PD(MAX) = (TJ(MAX) − TA ) / θJA design had been designed. If possible, it's useful to
Where T J(MAX) is the maximum operation junction increase thermal performance by the PCB layout copper
temperature , TA is the ambient temperature and the θJA is design. The thermal resistance θJA can be decreased by
the junction to ambient thermal resistance. adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
For recommended operating conditions specification of
RT8279, the maximum junction temperature is 125°C. The As shown in Figure 4, the amount of copper area to which
junction to ambient thermal resistance θJA is layout the SOP-8 (Exposed Pad) is mounted affects thermal
dependent. For PSOP-8 package, the thermal resistance performance. When mounted to the standard
θJA is 75°C/W on the standard JEDEC 51-7 four-layers SOP-8 (Exposed Pad) pad (Figure 4a), θJA is 75°C/W.
thermal test board. The maximum power dissipation at Adding copper area of pad under the SOP-8 (Exposed
TA = 25°C can be calculated by following formula : Pad) (Figure 4.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 4.e)
reduces the θJA to 49°C/W.

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RT8279
The maximum power dissipation depends on operating
ambient temperature for fixed T J (MAX) and thermal
resistance θJA. For the RT8279, the Figure 5 of derating
curves allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation
allowed.
2.2 (d) Copper Area = 50mm2 , θJA = 51°C/W
Four Layer PCB
2.0
1.8
Power Dissipation (W)

1.6 Copper Area

70mm2
1.4 50mm2
1.2 30mm2
10mm2
1.0
Min.Layout
0.8
0.6
0.4 (e) Copper Area = 70mm2 , θJA = 49°C/W
0.2 Figure 4. Thermal Resistance vs. Copper Area Layout
0.0 Design
0 25 50 75 100 125
Ambient Temperature (°C)

Figure 5. Derating Curves for RT8279 Package Layout Consideration

Follow the PCB layout guidelines for optimal performance
of the RT8279.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device

pins (VIN and GND).

` SW node is with high frequency voltage swing and should

(a) Copper Area = (2.3 x 2.3) mm , θJA = 75°C/W

2
be kept at small area. Keep analog components away
from the SW node to prevent stray capacitive noise pick-
up.
` Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the RT8279.
` Connect all analog grounds to a common node and then

connect the common node to the power ground behind

(b) Copper Area = 10mm2, θJA = 64°C/W the output capacitors.
` An example of PCB layout guide is shown in Figure 6 for

reference.

(c) Copper Area = 30mm2 , θJA = 54°C/W

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 RT8279
SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.

SW VOUT COUT

CBOOT COUT
L1
D1
BOOT 8 SW
NC 2 7 VIN
GND CIN
VOUT NC 3 6 GND
R1 9
CIN
FB 4 5 EN
R2 Input capacitor should be
placed as close to the IC
The feedback components as possible.
should be connected as close
to the device as possible. GND
Figure 6. PCB Layout Guide

Table 3. Suggested Capacitors for CIN and COUT

Location Component Supplier Part No. Capacitance (μF) Case Size
CIN MURATA GRM32ER71H475K 4.7 1206
CIN TAIYO YUDEN UMK325BJ475MM-T 4.7 1206
COUT MURATA GRM31CR60J476M 47 1206
COUT TDK C3225X5R0J476M 47 1210
COUT MURATA GRM32ER71C226M 22 1210
COUT TDK C3225X5R1C22M 22 1210

Table 4. Suggested Diode

Component Supplier Series VRRM (V) IOUT (A) Package
DIODES B550C 50 5 SMC
PANJIT SK55 50 5 SMC

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RT8279
Outline Dimension
H
A

EXPOSED THERMAL PAD Y

(Bottom of Package)
J X B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138

8-Lead SOP (Exposed Pad) Plastic Package

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Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

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