Digital Fundamentals 1 Counters PDF

Digital Fundamentals
Counters
1
Objectives
•Describe the difference between an asynchronous and a synchronous counter
•Analyze counter timing diagrams
•Analyze counter circuits
•Explain how propagation delays affect the operation of a counter
•Determine the modulus of a counter
•Modify the modulus of a counter
•Recognize the difference between a 4-bit binary counter and a decade counter
•Use an up/down counter to generate forward and reverse binary sequences
•Determine the sequence of a counter
•
•Use IC counters in various applications
•Design a counter that will have any specified sequence of states
•Use cascaded counters to achieve a higher modulus
•Use logic gates to decode any given state of a counter
•Eliminate glitches in counter decoding
•Explain how a digital clock operates
•Troubleshoot counters for various types of faults
•Interpret counter logic symbols that use dependency notation
•Discuss mode selection in an SPLD

2
•Apply a counter in a system application
Figure 9--1 A 2-bit asynchronous binary counter. Open file F09-01 to verify operation.
Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.
3
Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.
Digital Fundamentals, 8e Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F09-03 to verify operation.
4
Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
5
Figure 9-5 Example 9-1: Four-bit asynchronous binary counter and its timing diagram. Open file F09-05 and verify the operation.
Propagation delay is 10 ns for the flip-flops. Draw the timing diagram and determine the total propagation delay and the maximum
clock frequency at which the counter can be operated.
t p ( tot ) = 4 ⋅10 ns = 40 ns
1 1
f max = = = 25 MHz 6
Thomas L. Floyd
Digital Fundamentals, 8e t p (tot ) 40 ns Copyright ©2003 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.
7
Figure 9-7 Example 9-2: Asynchronously clocked modulus-12 counter with asynchronous recycling.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
0000
etc.
8
Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are
internally connected HIGH.)
Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n
states.)
9
Figure 9-10 Example 9-3: Show how the 74LS93A can be connected as a modulus-12 counter.
10
Figure 9--11 A 2-bit synchronous binary counter.
11
Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be
equal).
12
Figure 9--13 Timing diagram for the counter of Figure 9-11. NO EXTRA DELAYS!
13
Figure 9--14 A 3-bit synchronous binary counter. Open file F09-14 to verify the operation.
000
001
010
011
100
101
Figure 9--15 Timing diagram for the counter of Figure 9-14.
110
111
000
14
Figure 9--16 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the
shaded areas.
15
Figure 9--17 A synchronous BCD decade counter. Open file F09-17 to verify operation.
16
Figure 9--19 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)
17
18
19
Figure 9--20 Timing example for a 74HC163.
20
Figure 9--21 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)
21
22
Figure 9--22 Timing example for a 74LS160.
23
Figure 9--23 A basic 3-bit up/down synchronous counter. Open file F09-23 to verify operation.
24
Figure 9-24 Example 9-4: Shot the timing diagram in the following situation:
Q
3210
0000
0001 UP
0010
0100
0011
0010
0001 DOWN
0000
1111
0000
0001 UP
0010
0001
DOWN
0000
25
Figure 9--25 The 74HC190 up/down synchronous decade counter.
26
27
Figure 9--26 Timing example for a 74HC190.
28
Design of synchronous counters
Figure 9--27 General clocked sequential circuit.
29
Figure 9--28 State diagram for a 3-bit Gray code counter.
STEP 1
30
Next-State table
Present Next
state state
Q Q
210 210
000 001
STEP 2 001 011
011 010
010 110
110 111
111 101
101 100
100 000
31
Flip-flop transition table
Output Flip-flop
transitions inputs
STEP 3 Q Q
N N+1 J K
0→0 0 X
0→1 1 X
1→0 X 1
1→1 X 0
Q
N: present state
N+1: next state
X: don’t care
32
Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.
STEP 4
33
From the K-maps:
STEP 5
J 0 = Q2Q1 + Q2 Q1 = Q2 ⊕ Q1
K 0 = Q2 Q1 + Q2Q1 = Q2 ⊕ Q1
J1 = Q2Q0
K1 = Q2Q0
J 2 = Q1 Q0
K 2 = Q1 Q0
34
Figure 9--30 Karnaugh maps for present-state J and K inputs.
35
Figure 9--31 Three-bit Gray code counter. Open file F09-31 to verify operation.
STEP 6
36
Summary of steps:
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required

for each transition. The transition table is always the same for
a given type of flip-flop.
4. Transfer the J and K states from the transition table to K-maps.

There is a K-map for each input of each flip-flop.
5. Group the K-map cells to generate and derive the logic express-
ion for each flip-flop input.
6. Implement the expressions with combinational logic, and comb-

ine with the flip-flops to create the counter. 37
Figure 9-32 Example 9-5: Design a counter with following state diagram:
Step 1
Present Next
state state
Q Q Step 3
210 210
001 010
Step 2 0 1 0 101
101 111
111 001
38
Figure 9--33
Step 4
39
Step 5
J 0 = 1, K 0 = Q2
J 1 = K1 = 1
J 2 = K 2 = Q1
40
Figure 9--34
Step 6
41
Figure 9-35 Example 9-6: Develop a synchronous 3-bit u/d counter with a Gray code sequence.
STEP 1 STEP 2
STEP 3
42
Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.
STEP 4
43
STEP 5
44
Figure 9--37 Three-bit up/down Gray code counter.
STEP 6
45
CASCADED COUNTERS
Figure 9--38 Two cascaded counters (all J and K inputs are HIGH).
Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38.
46
Figure 9--40 A modulus-100 counter using two cascaded decade counters.
47
Figure 9--41 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-
100 outputs.
48
Figure 9-42 Example 9: Determine the overall modulus in the following cascaded counters
Solution
8x12x16 = 1536
10x4x7x5 = 1400
49
Figure 9-43 Example 9-8: Use 74LS160 counters to obtain a 10 kHz waveform from a 1 MHz clock.
Solution: A divide-by-100 counter using two 74LS160 decade counters.
50
Figure 9--44 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in
binary order (the right-most bit D0 is the LSB in each counter).
51
Counter decoding
Figure 9--45 Decoding of state 6 (110). Open file F09-45 to verify operation.
52
Figure 9-46 Example 9-9: Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. A 3-bit
counter with active-HIGH decoding of count 2 and count 7. Open file F09-46 to verify operation.
53
Figure 9--48 Outputs with glitches from the decoder in Figure 9-47.
Decoding glitches Glitch widths are exaggerated for illustration and are usually only a
few nanoseconds wide.
Figure 9-47 A basic decade (BCD) counter and decoder.
54
Figure 9--49 The basic decade counter and decoder with strobing to eliminate glitches.
Figure 9--50 Strobed decoder outputs for the circuit of Figure 9-49.
55
Application examples
Figure 9--51 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-
53.
56
Figure 9--52 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in
binary order (the right-most bit is the LSB).
57
Figure 9--53 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.
58
Figure 9--54 Functional block diagram for parking garage control.
Figure 9--55 Logic diagram for modulus-100 up/down counter for automobile parking control.
59
Figure 9--57 Example of parallel-to-serial conversion timing for the
Figure 9--56 Parallel-to-serial data conversion logic. circuit in Figure 9-56.
60
Troubleshooting
Figure 9--58 Example of a failure that affects following counters in a cascaded arrangement.
61
Figure 9--59 Example of a failure in a cascaded counter with a truncated sequence.
62
Figure 9-60 Example 9-10: Frequency measurements are made on the truncated counter (see below) as indicated. Determine
if the counter is working properly, and if not, isolate the fault.
Solution:
Check frequency at TC 4 ...
63
Figure 9-61 Example 9-11: Determine if there is a problem with the counter
64
Hands on tip
When observing the time relationship between two digital signals with a dual-trace oscillo-
scope, trigger the scope with the slower signal (it has fewer possible trigger points!).
Hence do not use clock signals for triggering (they are usually the fastest signal in the
system).
65
Logic symbols with dependency notation
Figure 9--62 The 74HC163 4-bit synchronous counter.
66
Figure 9--63 Combinational mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.
67
Figure 9--64 Registered mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.
68
Figure 9--65
69
Figure 9--66 Traffic light control system block diagram and light sequence.
70
Figure 9--67 Block diagram of the sequential logic.
71
Figure 9--68 State diagram showing the 2-bit Gray code sequence.
72
Figure 9--69 Sequential logic.
73
74
Figure 9--70
75
Figure 9--71
76
Figure 9--72
77
Figure 9--73 Comparison of asynchronous and synchronous counters.
78
Figure 9--74 Note that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturer’s
data book you are using. The devices shown are functionally the same and pin compatible with the same device types in other available
TTL and CMOS IC families.
79

Digital Fundamentals 1 Counters PDF

Uploaded by

Copyright:

Available Formats

Digital Fundamentals 1 Counters PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Fundamentals 1 Counters PDF

Uploaded by

Copyright:

Available Formats

Digital Fundamentals

•Describe the difference between an asynchronous and a synchronous counter

•Analyze counter timing diagrams

•Analyze counter circuits

•Explain how propagation delays affect the operation of a counter

•Determine the modulus of a counter

•Modify the modulus of a counter

•Use an up/down counter to generate forward and reverse binary sequences

•Determine the sequence of a counter

•Design a counter that will have any specified sequence of states

•Use cascaded counters to achieve a higher modulus

•Use logic gates to decode any given state of a counter

•Eliminate glitches in counter decoding

•Explain how a digital clock operates

•Troubleshoot counters for various types of faults

•Interpret counter logic symbols that use dependency notation

•Discuss mode selection in an SPLD

Figure 9--27 General clocked sequential circuit.

2. Derive a next-state table from the state diagram.

3. Develop a transition table showing the flip-flop inputs required

4. Transfer the J and K states from the transition table to K-maps.

6. Implement the expressions with combinational logic, and comb-

Figure 9--62 The 74HC163 4-bit synchronous counter.

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.