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A Simple Floating MOS-Memristor for High-Frequency Applications

Article  in  IEEE Transactions on Very Large Scale Integration (VLSI) Systems · January 2019
DOI: 10.1109/TVLSI.2018.2890591

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1186 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 5, MAY 2019

A Simple Floating MOS-Memristor for

High-Frequency Applications
John Vista, Student Member, IEEE, and Ashish Ranjan , Member, IEEE

Abstract— This research paper reports on a floating memris- circuits [7], adaptive filters [8], chaotic circuits [9], and many
tor model with minimum metal–oxide–semiconductor field-effect more [10]–[13]. Moreover, the memristor design by HP labo-
transistor count. The proposed structure uses only three nMOS ratories is still unavailable in the commercial market because
transistors with a constant current bias and a single external
capacitor. It offers less design complexity as compared to other of its fabrication complexity and high cost that delays the
existing memristor designs. The heart of the proposed design commercialization of real-time applications of the memristor.
incorporates a MOS-based feedback circuit as an electronically Therefore, the design of memristor emulators using digital [14]
controlled element for the memristance value. The memristor and analog [15] methods has gained phenomenal attention to
model has been integrated with 0.18-µm Taiwan Semiconductor widen the possibility of a memristor in various applications.
Manufacturing Company Ltd. (TSMC) CMOS parameter. The
pinched hysteresis loop of memristor for different frequency The memristor design using various current-mode building
ranges and their composite characteristics are well analyzed blocks such as second-generation Current Conveyor (CCII)
using PSPICE simulation. The operating frequency range of the [16], electronically tunable CCII [17], electronically tun-
reported memristor is suitable up to few megahertz range. In able Differential Different Current Conveyor [18], operational
addition to that application of the proposed MOS-memristor transconductance amplifier (OTA) [19], current feedback oper-
model is well described that comprises a Op-Amp-based Schmitt
trigger circuit, a high-frequency modulation scheme, and an ational amplifier (CFOA) [20], differential difference current
associative learning process. Finally, the postlayout simulation conveyor [21], current conveyor transconductance amplifier
and experimental results are presented to validate the workability (CCTA) [22], and differential voltage CCTA [23], and other
of the proposed memristor model. memristor models [24]–[34] are widely available in the lit-
Index Terms— Frequency analysis, memristor, metal–oxide– erature. An intensive study of the literature reveals that the
semiconductor field-effect transistor (MOSFET), pinched design of memristor emulator using current mode building
hysteresis loop. blocks [15]–[34] uses a number of transistors along with
few passive components. Integration of such active blocks
I. I NTRODUCTION
is still a challenging task for the circuit designer, but few
M EMRISTOR, the fourth passive element, has gained
attention among the research community due to its
ability to process and store information. Basically, a memristor
advance commercial integrated circuits like OTA as (LM3080,
LM13700), Diamond Transistor (OPA860), CCII as (EL2082),
CFOA as (AD844), and some analog multipliers as (AD633,
is a two-terminal device whose resistance value depends on the
AD834) are available. Hence, the author has made an attempt
history of current which flows through it [1]–[3]. The mem-
to design a simple memristor without any current-mode active
ristor offers a unique relationship between the time integral
blocks and commercially available integrated circuits.
of current (charge) and the time integral of voltage (flux) and
In this paper, we will present a compact MOS-memristor
depends on the magnitude and polarity of the voltages across
model using three nMOS transistors, a current source, and an
it. After the first literature reported by Chua [1], the mem-
external capacitor. The drain-to-source resistance is modeled to
ristor was fabricated in HP laboratories using titanium oxide
vary with respect to time which ensures the floating memristor
(TiO2 ) in which the semiconductor film forms two distinct
characteristics. The proposed memristor model is suitable for
resistive regions as low resistance (Ron ) and higher resistance
monolithic integration as compared to [14]–[34]. The paper is
(Roff ), respectively. However, the boundary between these two
subdivided into five sections in which Section II introduces
resistive regions will be translated by an applied external
a MOS-memristor topology with mathematical justification
voltage [4]. This design attracts researchers for further devel-
and their frequency analysis. A full workability test of the
opment of memristor design for real-world applications. Since
proposed model using the simulation and experimental results
the memristor has the capability to store information, it can
along with postlayout simulation in Cadence’s Virtuoso tool
be used in multitude of applications such as nonvolatile mem-
is well illustrated in Sections III and IV, respectively. Also,
ories [5], programmable analog circuits [6], neuromorphic
the application of the proposed memristor model is discussed
Manuscript received August 10, 2018; revised November 13, 2018; accepted in Section V. Finally, the conclusion part is included in
December 21, 2018. Date of publication January 16, 2019; date of current Section VI.
version April 24, 2019. (Corresponding author: Ashish Ranjan.)
The authors are with the Department of Electronics and Communication
Engineering, National Institute of Technology, Manipur, Imphal 795004, India
(e-mail: jkwista@gmail.com; ashish.ism @rediffmail.com). II. MOS-M EMRISTOR T OPOLOGY
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. The concept of the memristor design is visualized in
Digital Object Identifier 10.1109/TVLSI.2018.2890591 Fig. 1 in which a variable resistance must be achieved by
1063-8210 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
VISTA AND RANJAN: SIMPLE FLOATING MOS-MEMRISTOR FOR HIGH-FREQUENCY APPLICATIONS 1187

the capacitor is obtained by applying KCL at node Vo as

i = i D1 − i D2
 
μn Cox W
⇒i = [(v GS1 − Vt )2 + (v GS2 − Vt )2 ]
2 L 1,2
 2  2 
k1,2 Vin (t) −Vin (t)
Fig. 1. Concept of the proposed memristor model. ⇒i = − V0 − Vt − − Vt
2 2 2
k1,2  
⇒i = −2Vin (t)Vt + V02 − Vo Vin (t) + 2Vo Vt . (2)
2
For simplification, the term −2Vin (t)Vt can be discarded
because the value is much lower in comparison to Vo2 −
Vo Vin (t) + 2Vo Vt and the current (i ) through capacitor can
be approximated as i = CdV o /dt that transforms (2) as
d Vo k1,2  2 
C = V0 − Vo Vin (t) + 2Vo Vt
dt 2
dV o k1,2 k1,2
⇒ Vo−2 + Vo−1 (Vin (t) − 2Vt ) = . (3)
dt 2C 2C
The approximate analysis of the earlier equation leads a first-
order linear differential equation by substituting Vo−1 = Z
Fig. 2. MOS realization of the proposed Memristor model. and Vt ≈ 0 where threshold voltage (Vt ) in the term [Vin (t) −
2Vt ] contributes dc offset only in the time-varying input signal
Vin (t). Hence, (3) transforms to
proper feedback of voltage across the resistor (M R ) [35].
Let us consider a situation, where a resistor (M R ) can be dZ k1,2 k1,2
− Vin (t)Z = − (4)
replaced by metal–oxide–semiconductor field-effect transis- dt 2C 2C
tor (MOSFET) whose resistance can be modified through feed- Now, (4) looks like a perfect first-order linear differential
back network. Now, this idea can be transformed into our new equation as (dZ/dt) − PZ = −Q whose solution with the
design for memristor by using n-MOSFET as shown in Fig. 2. integration constant (D) is
The MOS-based feedback circuit in Fig. 2 is responsible for
 
producing a voltage difference of magnitude (V0 = VA − VB ) ze− Pdt = −Qe− Pdt dt + D. (5)
as a feedback network when activated through external voltage
sources (VA , VB ). In addition, Fig. 2 associates the voltage By substituting the value of P as (k1,2 /2C)Vin (t) in (5),
difference output with an additional transistor followed by a it gives
grounded capacitor.
 k1,2  k1,2
In Fig. 2, the transistor M3 contributes variable resistance,
ze− 2C Vin (t )dt = −Qe− 2C Vin (t )dt dt + D (6)
namely, drain-to-source resistance (rds3) that numerical values
can be formulated in linear mode as  k1,2
Vin (t )dt
⇒ Z ≈ De 2C . (7)
1
rds3 = (1)
k(Vgs3 − Vt3 − Vds3 ) Using V0−1 = Z in (7), we obtain the final output voltage (Vo )
where k = μn Cox (W /L) is termed as the transconductance as
parameter as a function of mobility (μn ), gate-oxide capac- k1,2
V0−1 ≈ De 2C ϕ(t )
itance (Cox ), aspect ratio (W /L), and other parameters are
gate-to-source voltage (Vgs3), drain-to-source voltage (Vds3), 1 k1,2
⇒ Vo ≈ − ϕ(t). (8)
and threshold voltage (Vt3 ). In linear mode, rds3 is dependent D 2DC
on Vg3 that allocates control over rds3 . According to the Then, the memristance value due to the external voltage across
proposed concept, rds3 has to vary with respect to Vds3, which (A–B) is deliberated from the following procedure. The drain
is accomplished by the feedback circuit. The input voltage Vin current of transistor M3 can be considered as the current
(t) = VA − VB is given across the drain [VA = Vin (t)/2] and through memristor where the expression of the drain current
source [VB = −Vin (t)/2] terminal of transistor M3 . In order in the linear region is given as
to observe the control voltage Vo , we have assumed that

the two identical transistors (M1 , M2 ) are operating in the W v 2D S
saturation region by using a constant current source. Also, i D = μn Cox (v G S − Vt )v D S − . (9)
L 2
the input provided across A–B is differential input, and the
corresponding input voltages at points A and B are considered By substituting v G3 = Vo , v DS = Vin (t), and VA = −VB =
as VA = −VB = Vin (t)/2. Then, the current (i ) flows through Vin (t)/2, the resultant drain current from (9) is obtained as
1188 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 5, MAY 2019

follows:
   
W Vin (t)
i D3 (t) = μn Cox Vo + − Vt Vin (t)
3L 2
Vin (t) 2  
W
− = μn Cox Vin(t)(Vo − Vt )
2 L 3
   Fig. 3. Modification of the incremental memristance value.
W 1 k1,2
⇒ i D3(t) = μn Cox − ϕ(t)−Vt Vin (t). (10)
L 3 D 2DC
2) When τ = 1/ f , maximum-pinched hysteresis loop
Finally, the overall inverse memristance value can be
will be attained capacitor value because the time con-
represented as
stant of the memristor and signal source frequency is
  
−1 W 1 k1,2 equal.
M (ϕ(t)) ≈ μn Cox − Vt − ϕ(t) . (11) 3) When τ ≤ 1/ f , the memristor time constant is lesser
L 3 D 2DC
than the signal source frequency which causes loss of
Equation (11) witnesses the conversion of linear pinched hysteresis loop.
drain-to-source resistance to a time-dependent drain-to- Till now, an ideal behavior of the proposed memristor is
source resistance that emulates the memristor characteristics. analyzed. However, the transistor experiences deviation from
Therefore, the memristor exhibits linear time-varying resistor. its ideal nature due to the parasitic components present in
The memristor will retain the past memristance value even it. In order to examine the circuit, (11) is calculated by
if it is not connected with external sources. Since there is considering the parasitic capacitances (Cp ) and resistance (Rp )
no path for the current flow and simultaneously the voltage of transistor M3 . Let us consider the dominating parasitic
across it will be sensed and stored in capacitors, the capacitor capacitances are gate–source (Cgs ) and drain–source (Cds )
starts to discharge which imparts current flow in M3 , and capacitances that result in a parasitic capacitance (Cp ) par-
hence, the process will continue that confirms the nonvolatile allel to C at node V o. Hence, the inverse memristance is
nature of memristor. In another way, we can say that the modified to
memristance depends on the history and direction of previous   
W 1 k1,2
current flow through it. Hence, the current flow is sensed M −1 (ϕ(t)) = μn Cox − Vt − ϕ(t)
and forwarded in terms of voltage which influences the gate L 3 D 2D(C + C p )
voltage of M3 . Vin (t)
To analyze the frequency behavior, the proposed memristor × Vin (t) + . (14)
Rp
circuit is excited with sinusoidal input source Vin (t) = Am
sin(2πft) with ( Am and f ) as amplitude and operating fre- The parasitic capacitance (Cp ) affects the rate of change
quency. Now, the ON-state inverse memristance value can be of memristance which causes a decrease in the area of the
represented as pinched hysteresis loop, and hence, the memristance value
  deviates from the ideal characteristics.
−1 W k1,2 Am In addition, we have the flexibility to increase or decrease
M (q(t)) = μn Cox cos(ωt). (12)
L 3 2DωC the memristor value. From (11), we can observe that the
variable parameter in inverse memristor is dependent on the
From (12), as the frequency tends to infinity, the ON-state aspect ratio (W /L)3 and capacitor value (C). The capacitor
inverse memristance value becomes zero. Then, the amplitude value is restricted to very small range due to the relationship
of ON-state memristance can be rewritten as between the time constant and input frequency (τ = 1/ f ).
 
W k1,2 Am cos(ωt) 1 However, the variation in the aspect ratio (W /L)1,2 will not
M −1 (q(t)) = μn Cox = (13) affect the memristance value since M1 and M2 only act as
L 3 2DC ω τf
a feedback circuit. Hence, the product of memristance values
where τ = μn Cox (W /L)3 (Am /4πDC) represents the time can be increased by either varying (W /L)3 value or by the
constant of the proposed emulator that controls the pinched addition of transistors in series as shown in Fig. 3. In brief,
hysteresis loop. Therefore, we have to adjust τ as per the the following steps have to be considered for the satisfactory
operating frequency. Observation states that the parameters, memristor operation.
namely, μn , Cox , (W /L), and Am will become constant. The 1) Transistors M1 and M2 should be identical,
leftover variable is the capacitor (C) which acts as a tunable i.e., (μn Cox W/L)1 = (μn Cox W/L)2 and Vt 1 = Vt 2 .
parameter for the time constant (τ ) as per the operating 2) The current source (I ) should be selected such a way
frequency. From (13), we can analyze some useful relationship that M1 and M2 remain in the saturation region.
between the time constant and input frequency in the following 3) The aspect ratio (W /L) for transistor M3 has to be
cases. chosen according to the requirement for incremen-
1) When the frequency tends to infinity ( f → ∞), tal/decremental memristance range in the ON state.
the ON-state resistance will be zero, and hence, the mem- 4) The value of capacitance has to adopt in such
ristance will be dominated by linear time-invariant a way that it satisfies the time-constant condition
resistance part. (τ = 1/ f ).
VISTA AND RANJAN: SIMPLE FLOATING MOS-MEMRISTOR FOR HIGH-FREQUENCY APPLICATIONS 1189

Fig. 4. Waveform (a) pinched hysteresis curve at 50 Hz and (b) voltage and
current plot for memristor at f = 50 Hz. Fig. 5. Variation in pinched hysteresis curve for the proposed memristor
with frequencies of (a) 500 and 1000 Hz, and (b) 100 KHz and 1 MHz.

III. S IMULATION R ESULTS

In order to validate theoretical predictions of the memristor
model, SPICE simulation is first introduced for simple
MOS-based topology demonstrated as Fig. 2. Memristor
model based on MOSFET uses 0.18-μm Taiwan Semiconduc-
tor Manufacturing Company Ltd. (TSMC) CMOS technology
with aspect ratio of transistors (W /L)1 = (W/L)2 = 1 μ /1 μ
and (W /L)3 = 50 μ /1 μ. The external current source and
capacitor values are 10 μA and 1 nF, respectively. The pinched
hysteresis loop for sinusoidal input (1 V, 50 Hz) from B
to A along with current waveform is shown in Fig. 4 from
which we investigate clearly that the area of simulated pinched
hysteresis curve is narrower than theoretical one due to the
effect of parasitic capacitance and resistance. Also, we observe
some deviation in simulated current and theoretical current for
memristor at f = 50 Hz.
In addition, the pinched hysteresis loop for (500 Hz, 1 KHz)
and (100 KHz, 1 MHz) with capacitor value 100 and 0.01 pF
value is shown in Fig. 5, which confirms that the hysteresis
loop becomes narrower as the frequency increases in theoreti-
cal as well as simulation results. Further analysis of the design
in terms of the area over the right lobe (R): 0–1 V and left lobe
(L): −1–0 V of pinched hysteresis is evaluated using Origin
software, and the measurement is displayed in Fig. 6(a) where Fig. 6. Area calculation for different frequencies. (a) Variation in the area
the two regions are separated by a dotted line. The dotted of pinched hysteresis loop. (b) Overall area and ratio of (R − L) and (R + L).
line represents the maximum area obtained at 100 kHz due to
the time constant that is equal to the input signal frequency.
Also, an observation for f < 100 kHz shows pinched (R + L) and the ratio of difference between two lobe areas to
hysteresis loop with lesser area, and for f > 100 kHz, area the overall area (R − L/R + L) are demonstrated in Fig. 6(b).
bounded decreases when the frequency approaches infinity. The proposed memristor is also well applicable for pinched
Then, the summation of area over right lobe and left lobe hysteresis loop of single (MR), series (MR1 + MR2 ), and
1190 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 5, MAY 2019

Fig. 7. Pinched hysteresis curve for different memristor combinations.

Fig. 9. Postlayout simulation of memristor model. (a) V –I characteristics.

(b) Pinched hysteresis.

Fig. 8. Variation of memductance with respect to time.

parallel (MR1 ||MR2 ) memristor are indicated in Fig. 7 for

frequency 100 Hz. It indicates that when identical memristors
are connected in series with the same polarity, this will result
in double of each memristance value but a reduction in current
value by half. On the other hand, the parallel connection of
identical memristor produces a reduction in memristance value
by half, but the current value is doubled. To demonstrate the
nonvolatile nature of memristor for the C = 100 pF, a pulse
input signal is provided with amplitude 1 V and pulsewidth 0.5
μs up to a period of 30 μs. Fig. 8 shows the corresponding
memductance value over a period of time, which concludes
with the constant memductance value even for the absence
of input signal. This property confirms that the proposed
memristor exhibits nonvolatile nature. Fig. 10. Layout of the proposed memristor model.

IV. P OSTLAYOUT S IMULATION AND

E XPERIMENTAL V ERIFICATION respectively, and the aspect ratio (W /L)1,2,3 of transistors is
To justify the simulation results more precisely, we have (50 μ/1 μ). The postlayout voltage–current transient behavior
performed the advance simulation results using Cadence Vir- under sinusoidal signal (500 mV, 50 Hz) and the pinched
tuoso tool comprising postlayout simulation and experimental hysteresis loop are shown in Fig. 9. In addition, the complete
verification with off the self-active and passive components. CMOS layout is designed excluding the passive elements
Section I discusses the proposed memristor layout design with pins for current source (I dc), capacitor (CAP), input
where the capacitor is considered as an external component terminals (A, B), and ground terminal (GND) are shown
since the value of the capacitor tends to vary in terms of in Fig. 10. The total area of the present layout and the power
input signal frequency. The numerical values of the capac- consumption is observed through the Cadence Virtuoso tool
itor (C) and current (I ) are taken as 1 nF and 10 μA, are 2803.25 μm2 and 6.725 nW, respectively. In addition,
VISTA AND RANJAN: SIMPLE FLOATING MOS-MEMRISTOR FOR HIGH-FREQUENCY APPLICATIONS 1191

Fig. 14. Op-Amp-based Schmitt trigger circuit with memristor.

Fig. 11. Pinched hysteresis loop at different process corners.

Fig. 12. Variation in pinched hysteresis curve for a different bias current.

Fig. 15. Schmitt trigger. (a) Input and output voltage waveforms.
(b) Hysteresis curve of Schmitt trigger.

We observed that the model of the proposed memristor is

quite different in comparison to various memristor emulators
available in [20], [21], [23]–[29], [33], and [34]. Very few of
them are easy to integrate and most of the studies have more
power dissipation in comparison to the proposed memristor
model. Also, very few articles provide experimental validation
and the proposed design is well examined on a breadboard
using IRF840 [36] transistor and capacitor (0.47 μF). The
current source (I ) has to be selected in which the transistor
should remain in the saturation region. Likewise, the input
Fig. 13. Experimental verification of V –I characteristics of memristor with voltage amplitude should be greater than the threshold voltage
frequency of (a) 11.4 MHz, (b) 12.2 MHz, and (c) 13 MHz. for proper operation. The current source is provided using
Tektronix—2231A-30-3 triple-channel dc power supply. The
transistor M3 is replaced with three IRF840 transistors in
one important observation based on different process corners, series and their gates are connected to the capacitor, as shown
namely, fast N transistor (FF), nominal N transistor (NN), and in Fig. 3, in order to experience high OFF-state resistance
slow N transistor (SS), are illustrated to validate the feasibility and wide hysteresis loop in digital storage oscilloscope. The
of the memristor model. Fig. 11 shows the characteristics of frequency analysis informs that the time constant of the
the memristor model at different process corners, which clearly proposed memristor depends on the capacitor value. A possible
facilitates its broad nature. Moreover, the memristor model way to adjust the time constant with respect to frequency is
is analyzed for different current values and the observations to change the capacitor value. Although the capacitor value
are mentioned in Fig. 12. In the above-mentioned two cases, is fixed at 0.47 μF, we found that there is a difficulty
the pinched hysteresis curve deviates for different process in attaining the hysteresis loop due to the internal source
variations, but the proposed model follows the hysteresis loop, resistance of the voltage source which indirectly affects the
and the current value is zero for the absence of the input signal. time constant. Therefore, the voltage source is connected to
1192 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 5, MAY 2019

Fig. 16. Memristor-based associative learning process [37].

the circuit with external variable resistance R1 . Moreover,

the addition of external variable resistance along with the
voltage source provides an additional controlling parameter
for time constant (τ ). Hence, the resistance provides an easy
way for the generation of the current waveform, [Iin (t)].
The experimental results corresponding to Vin (t) versus Iin (t)
are directly observed across a voltage source and resistance
R1 , respectively. The input sinusoidal voltage waveform is
provided by DG4102 waveform generator and a series poten-
tiometer of 10 K for the purpose to attain the hysteresis
loop at different frequencies. Fig. 13 presents the experi-
mental pinched hysteresis loop at different frequencies such
as 11.4 KHz, 12.2 MHz, and 13 MHz with R1 value as
8.027, 6.12, and 0.279 k, respectively. We can observe that
the hysteresis loop gets narrower as the frequency increases
which validates the theoretical concept. This experimental
verification validates our memristor model and these results
have similar characteristics as that of simulation results.
Finally, Table I presents the comparison of the proposed
design with existing memristor design. For better compari-
son, various memristor emulators [20], [21], [23]–[25], [27]–
[29], [33], [34] that comprise active current mode blocks and
commercially available IC are illustrated along with physical
structure, performance parameters such as CMOS Technology,
operating frequency, and power consumption. From Table I,
Fig. 17. Response for associative learning process.
we can observe that the proposed memristor does not require
any analog active blocks as those in [20], [21], [23]–[29], [33],
and [34]; instead, the proposed memristor is made only with
N-channel transistors which, in turn, requires only one passive memristance value MR , the threshold voltage can be changed
element, unlike in [20], [21], and [23]–[28]. Also, very few at any instant by changing the state of memristor [6]. This
studies have high operating frequency, say 1 MHz [21], [23]; allows ease of changing the threshold voltage instead of
the proposed memristor model also offers high operating replacing the resistor with new resistance value. For simulation
frequency range. In addition, unlike other memristor models, purpose, TL082 Op-Amp is used with supply voltage ±10 V.
the proposed memristor model consumes less power. The component values are chosen as R1 = 7 k with
sinusoidal input of 250 Hz and 1 V peak-to-peak voltage. The
V. A PPLICATION change of memristance value in order to change the threshold
To facilitate the application of the proposed memristor voltage is attained by applying a series of programing pulses at
model, a simple Op-Amp-based Schmitt trigger circuit is Vo of the proposed memristor circuit after 10 ms. The change
performed as per Fig. 14. The switching thresholds of Schmitt in the threshold voltage is observed in transient response as
trigger can be obtained by the routine analysis as well as the hysteresis curve of the Schmitt trigger as shown
  in Fig. 15. In addition to the Schmitt trigger, the use of
MR
VTH = Vsat (15) memristor for associative learning process is also illustrated
R
1  in Fig. 16 [37] which includes adder circuit [resistors R1 , R2
MR
VTL = −Vsat (16) along with Op-Amp(1)] and voltage divider circuit (memristor
R1 and Rdiv ) followed by a comparator [Op-Amp(2)].
where Vsat is the saturation voltage (supply voltage) in the Associative learning is a learning process in animal behavior
case of Op-Amp. As the threshold voltage depends on the in which the learning process occurs with the application of
VISTA AND RANJAN: SIMPLE FLOATING MOS-MEMRISTOR FOR HIGH-FREQUENCY APPLICATIONS 1193

TABLE I
C OMPARISON OF THE P ROPOSED M ODEL W ITH E XISTING M EMRISTOR D ESIGN

Fig. 18. Memristor-based AM modulation and demodulation of FM signal.

external stimulus through instrumental conditioning. The adder unconditional stimulus as well as neural stimulus. At the end
provides the output voltage (Vadd ) as an inverse summation of of the associative learning process, i.e., after learning process
input signals such as VUCS indicates unconditional stimulus is over, one can get the response with the occurrence of either
that occurs due to habituation of particular species and VNS unconditional stimulus or neural stimulus.
represents the neutral stimulus that is provided through the Furthermore, one more application of the proposed mem-
external instrument. Then, the voltage division incorporated ristor model to emphasise the high-frequencies application is
by memristor and Rdiv results in the voltage (Vdiv ) and presented as amplitude modulation and demodulation of the
Vdiv = Vadd ∗ Rdiv /(Rmem + Rdiv ) is compared with VCOM . The FM signal. Since the memristance of the proposed memristor
output voltage (Vout ) is produced only if Vdiv > VCOM which model depends on the amplitude and frequency of the input
strongly depends on the memristance value as well as the signal, we can change the voltage (VAM ) corresponding to
learning period. The memristance changes with the variation the FM input signal by using Op-Amp (1). The amplitude
of the adder output voltage (Vadd ). In biological point of view, modulation circuit followed by envelop detector and demod-
the change in resistance values leads to change in Vdiv and, ulation circuit is shown in Fig. 18. The component values
in turn, results in Vout as a learning condition of the synapse, are R1,2,3,4 = 10 k, R5,6 = 1 k, C1 = 1 nF, and
i.e., the synapse gives response to a neutral stimulus after a C2,3 = 0.1 nF. The FM signal is provided as input (Vin )
particular period of time. Fig. 17 shows a transient response with 1-V amplitude, 50-kHz modulation frequency, 1-MHz
in three categories: before learning, during learning, and after carrier frequency, and modulation index as 5. Fig. 19(a) shows
learning. In the before learning case, the response will be due the modulated signal output (VAM ) in which we can observe
to unconditional stimulus alone. During the learning process, that the amplitude of the modulated signal varies with respect
the response of animal is obtained due to the occurrence of to the input signal frequency. Also, the demodulated signal
1194 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 5, MAY 2019

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The authors would like to thank the anonymous review- based high frequency incremental/decremental memristor emulator and
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[27] H. Kim, M. P. Sah, C. Yang, S. Cho, and L. O. Chua, “Memristor emu- John Vista (S’18) was born in 1992. She received
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pp. 23–33, Mar. 2017. design from the National Institute of Technol-
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simulations via a versatile 4-port built with new adder and subtractor is currently working toward the Ph.D. degree at
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trical nonlinearity emulation technique for current-controlled memristive of Electronics Engineering, Indian Institute of Tech-
devices,” IEEE Access, vol. 5, pp. 5399–5409, 2017. nology (Indian School of Mines), Dhanbad, India,
[35] A. S. Elwakil, B. J. Maundy, and C. Psychalinos, “On the pinched in 2013.
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Commun., vol. 74, pp. 171–175, Apr. 2017. Department of Electronics and Communication
[36] IRF 840, STMicroelectronics, Geneva, Switzerland, May 2002. Engineering, National Institute of Technology,
[37] Y. Babacan and F. Kacar, “FCS based memristor emulator with associa- Manipur, Imphal, India. His current research inter-
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vol. 17, no. 2, pp. 3433–3437, 2017. fractional-order circuit.

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