5 4 3 2 1

D D

Hadley15" Schematics Document

Haswell ULT

C C

2013-06-28
REV : A00

B B

DY : None Installed
UMA: UMA only installed
OPS: Optimus solution installed.
eDP: Support eDP Panel installed.
LVDS: Support LVDS Panel installed.

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 1 of 101
5 4 3 2 1
 5 4 3 2 1

Project code : 91.47L01.001

Hadly15 Block Diagram PCB P/N : 12311-1
Revision : A00
CHARGER
BQ24717 44
INPUTS OUTPUTS
AD+
eDP/ eDP BT+ DCBATOUT

LVDS SYSTEM DC/DC

D 15.6" LCD Option DDR3L Channel A
DDR3L 45 D
eDP to LVDS Slot A 12 TPS51225
FHD(1920 x 1080) circuit 1600MHz
Converter INPUTS OUTPUTS
LVDS eDP
52 Realtek
52, 53
RTD2136R 53
Intel CPU DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
DDR3L Channel B
DDR3L 5V_CHARGER
Haswell ULT Slot B 13
1600MHz 3D3V_PWR

HDMI CONN TMDS 15W/25W CPU DC/DC

TPS51622 46~47
54 VRAM(GDDR5)
GPU GDDR5 Ch A INPUTS OUTPUTS
128M x 16 x4(1GB) DCBATOUT VCC_CORE
USB PowerShare PCI-E x4
25W
USB 2.0
PERICOM USB 2.0
N14P-GT SYSTEM DC/DC
PI5USB1457AZAE TPS51363 48
USB 3.0 / Power share 35 GDDR5 Ch B
73~77 VRAM(GDDR5) INPUTS OUTPUTS
34 USB 3.0 128M x 16 x 4(1GB) DCBATOUT 1D05V_S0
Lynx Point-LP
8 USB 2.0/1.1 ports
SYSTEM DC/DC
TPS51216 49
USB 2.0 2-4 USB 3.0 ports USB 2.0 Touch Screen
High Definition Audio 52
INPUTS OUTPUTS
C USB 3.0 CONN C

USB 3.0 4 SATA ports DCBATOUT 1D35V_S3

34 0D675V_S0
8-12 PCIE ports
LPC I/F USB 2.0
2M 720P SYSTEM DC/DC
Mini-Card PCI-E Camera NCP81172 82
ACPI 4.0a 52
INPUTS OUTPUTS
802.11a/b/g/n SMBUS
FFS
USB 2.0 ST INT2 DCBATOUT VGA_CORE
BT 58
DE351DL
INT1 67 Switches 36, 83
Daughter board INPUTS OUTPUTS
SATA repeater 5V_S5 5V_S0
3D3V_S5 3D3V_S0
USB 2.0 SATA3 TI SATA3 HDD 56 3D3V_S0 3D3V_VGA_S0
SN75LVCP601 1D05V_S0 1D05V_VGA_S0
USB 3.0 CONN USB3.0 Redriver 1D35V_S3 1D35V_VGA_S0

USB 3.0
TI USB 3.0
LDO
SN65LVPE502RGER RJ45 31 TLV70215DBVR 51
LAN+Card reader
INPUTS OUTPUTS
B
PCI-E
(10/100/1000M) 3D3V_S5 B

USB 2.0 Realtek

MMI Card Connector
RTL8411B 30 (SD/SDHC/SDXC/
PCB LAYER
USB 3.0 CONN USB3.0 Redriver SD-UHS/MS/MS-Pro)
L1 : TOP
TI 33 L2 : GND
USB 3.0 USB 3.0
SN65LVPE502RGER L3 : Signal
L4 : Signal
LPC
LPC debug port
Thermal L5 : VCC
mSATA 65 SMBus
SATA repeater Nuvoton L6 : Signal
SATA3 TI SATA3 NCT7718W L7 : GND
26
SN75LVCP601 L8 : Bottom
KBC
Nuvoton
DC Fan Contrroller
NPCE985PA0DX DC Fan
SPI ANPEC
Internal Digital MIC 52 24 Module
Audio Codec APL5606AKI 26
26
HDA
PS2

A Universal jack Realtek Flash ROM A

29 ALC3223 8MB 25 <Core Design>

27
Touch Backlight
Wistron Corporation
SMBus 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH SPEAKER Pad Int. KB
62 62 Title
29
Block Diagram
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 2 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 3 of 101
5 4 3 2 1
 5 4 3 2 1
SSID = CPU

D D

1D05S_VCCST
HSW_ULT_DDR3L 1D05S_VCCST
CPU1B 2 OF 19
1
RN401
R401 TP401 1 SKTOCC# D61 XDP_TDO 1 8
62R2J-GP TP402 H_CATERR# PROC_DETECT# XDP_TDI
1 K61 CATERR#
MISC 2 7
N62 J62 XDP_PRDY# 3 6
[24] H_PECI PECI PRDY#
K62 XDP_PREQ#
XDP_PRDY# [96]
XDP_PREQ# [96] XDP_TMS 4
XDP 5
2

PREQ# XDP_TCLK
PROC_TCK E60
E61 XDP_TMS SRN51J-1-GP
H_PROCHOT#_R JTAG PROC_TMS XDP_TRST#
[24,42,44,46] H_PROCHOT# 1 2 K63 PROCHOT# PROC_TRST# E59
R403 THERMAL F63 XDP_TDI
PROC_TDI XDP_TRST# R402 XDP 2 51R2J-2-GP
C 56R2J-4-GP PROC_TDO F62 XDP_TDO
XDP_TCLK R406
1
2 51R2J-2-GP
C
Layout Note: TP403 1 H_CPUPW RGD C61
1

Impedance control:50 ohm PROCPWRGD PWR XDP_BPM[7:0]

R405 XDP_BPM[7:0] [96]
2 1 J60 XDP_BPM0
BPM#0 XDP_BPM1
10KR2J-3-GP BPM#1 H60
H61 XDP_BPM2
BPM#2 XDP_BPM3
BPM#3 H62
SM_RCOMP_0 AU60 K59 XDP_BPM4
SM_RCOMP_1 SM_RCOMP0 DDR3L BPM#4 XDP_BPM5
AV60 SM_RCOMP1 BPM#5 H63
SM_RCOMP_2 AU61 K60 XDP_BPM6
SM_DRAMRST# SM_RCOMP2 BPM#6 XDP_BPM7
AV15 SM_DRAMRST# BPM#7 J61
R407 1 2 200R2F-L-GP SM_RCOMP_0 DDR_PG_CTRL AV61
[12] DDR_PG_CTRL SM_PG_CNTL1
R408 1 2 120R2F-GP SM_RCOMP_1

R409 1 2 100R2F-L1-GP-U SM_RCOMP_2 HASW ELL-6-GP

1D35V_S3
Layout Note:
Layout Note: Place close to DIMM

1
Design Guideline: R410
SM_RCOMP keep routing length less than 500 mils. 470R2J-2-GP

2
B SM_DRAMRST# R404 1 2 DDR3_DRAMRST# [12,13]
B
0R0402-PAD-2-GP

X01 change to short pad

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 4 of 101
 5 4 3 2 1

SSID = CPU

CPU1C HSW_ULT_DDR3L 3 OF 19 CPU1D HSW_ULT_DDR3L 4 OF 19

M_A_DQ[63:0]
[12] M_A_DQ[63:0] M_B_DQ[63:0]
M_A_DQ0 AH63 AU37
SA_DQ0 SA_CLK#0 M_A_DIMA_CLK_DDR#0 [12] [13] M_B_DQ[63:0]
M_A_DQ1 AH62 AV37 M_B_DQ0 AY31 AM38
D M_A_DQ2 SA_DQ1 SA_CLK0 M_A_DIMA_CLK_DDR0 [12] M_B_DQ1 SB_DQ0 SB_CK#0 M_B_DIMB_CLK_DDR#0 [13] D
AK63 AW36 M_A_DIMA_CLK_DDR#1 [12] AW31 AN38 M_B_DIMB_CLK_DDR0 [13]
M_A_DQ3 SA_DQ2 SA_CLK#1 M_B_DQ2 SB_DQ1 SB_CK0
AK62 SA_DQ3 SA_CLK1 AY36 M_A_DIMA_CLK_DDR1 [12] AY29 SB_DQ2 SB_CK#1 AK38 M_B_DIMB_CLK_DDR#1 [13]
M_A_DQ4 AH61 M_B_DQ3 AW29 AL38
M_A_DQ5 SA_DQ4 M_B_DQ4 SB_DQ3 SB_CK1 M_B_DIMB_CLK_DDR1 [13]
AH60 AU43 M_A_DIMA_CKE0 [12] AV31
M_A_DQ6 SA_DQ5 SA_CKE0 M_B_DQ5 SB_DQ4
AK61 SA_DQ6 SA_CKE1 AW43 M_A_DIMA_CKE1 [12] AU31 SB_DQ5 SB_CKE0 AY49 M_B_DIMB_CKE0 [13]
M_A_DQ7 AK60 AY42 M_B_DQ6 AV29 AU50
M_A_DQ8 SA_DQ7 SA_CKE2 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIMB_CKE1 [13]
AM63 AY43 AU29 AW49
M_A_DQ9 SA_DQ8 SA_CKE3 M_B_DQ8 SB_DQ7 SB_CKE2
AM62 AY27 AV50
M_A_DQ10 SA_DQ9 M_B_DQ9 SB_DQ8 SB_CKE3
AP63 AP33 M_A_DIMA_CS#0 [12] AW27
M_A_DQ11 SA_DQ10 SA_CS#0 M_B_DQ10 SB_DQ9
AP62 AR32 M_A_DIMA_CS#1 [12] AY25 AM32 M_B_DIMB_CS#0 [13]
M_A_DQ12 SA_DQ11 SA_CS#1 M_B_DQ11 SB_DQ10 SB_CS#0
AM61 AW25 AK32 M_B_DIMB_CS#1 [13]
M_A_DQ13 SA_DQ12 TP_M_A_DIMA_ODT0 TP501 M_B_DQ12 SB_DQ11 SB_CS#1
AM60 AP32 1 AV27
M_A_DQ14 SA_DQ13 SA_ODT0 M_B_DQ13 SB_DQ12 TP_M_B_DIMB_ODT0 TP503
AP61 SA_DQ14 AU27 SB_DQ13 SB_ODT0 AL32 1
M_A_DQ15 AP60 AY34 M_A_RAS# [12] M_B_DQ14 AV25
M_A_DQ16 SA_DQ15 SA_RAS# M_B_DQ15 SB_DQ14
AP58 SA_DQ16 SA_WE# AW34 M_A_WE# [12] AU25 SB_DQ15 SB_RAS# AM35 M_B_RAS# [13]
M_A_DQ17 AR58 AU34 M_A_CAS# [12] M_B_DQ16 AM29 AK35 M_B_WE# [13]
M_A_DQ18 SA_DQ17 SA_CAS# M_B_DQ17 SB_DQ16 SB_WE#
AM57 SA_DQ18 AK29 SB_DQ17 SB_CAS# AM33 M_B_CAS# [13]
M_A_DQ19 AK57 AU35 M_A_BS0 [12] M_B_DQ18 AL28
M_A_DQ20 SA_DQ19 SA_BA0 M_B_DQ19 SB_DQ18
AL58 SA_DQ20 SA_BA1 AV35 M_A_BS1 [12] AK28 SB_DQ19 SB_BA0 AL35 M_B_BS0 [13]
M_A_DQ21 AK58 AY41 M_A_BS2 [12] M_B_DQ20 AR29 AM36 M_B_BS1 [13]
M_A_DQ22 SA_DQ21 SA_BA2 M_B_DQ21 SB_DQ20 SB_BA1
AR57 SA_DQ22 M_A_A[15:0] [12] AN29 SB_DQ21 SB_BA2 AU49 M_B_BS2 [13]
M_A_DQ23 AN57 AU36 M_A_A0 M_B_DQ22 AR28
M_A_DQ24 SA_DQ23 SA_MA0 M_A_A1 M_B_DQ23 SB_DQ22 M_B_A0 M_B_A[15:0] [13]
AP55 SA_DQ24 SA_MA1 AY37 AP28 SB_DQ23 SB_MA0 AP40
M_A_DQ25 AR55 AR38 M_A_A2 M_B_DQ24 AN26 AR40 M_B_A1
M_A_DQ26 SA_DQ25 SA_MA2 M_A_A3 M_B_DQ25 SB_DQ24 SB_MA1 M_B_A2
AM54 SA_DQ26 SA_MA3 AP36 AR26 SB_DQ25 SB_MA2 AP42
M_A_DQ27 AK54 AU39 M_A_A4 M_B_DQ26 AR25 AR42 M_B_A3
M_A_DQ28 SA_DQ27 SA_MA4 M_A_A5 M_B_DQ27 SB_DQ26 SB_MA3 M_B_A4
AL55 SA_DQ28 SA_MA5 AR36 AP25 SB_DQ27 SB_MA4 AR45
M_A_DQ29 AK55 AV40 M_A_A6 M_B_DQ28 AK26 AP45 M_B_A5
M_A_DQ30 SA_DQ29 SA_MA6 M_A_A7 M_B_DQ29 SB_DQ28 SB_MA5 M_B_A6
AR54 SA_DQ30 SA_MA7 AW39 AM26 SB_DQ29 SB_MA6 AW46
M_A_DQ31 AN54 DDR CHANNEL A AY39 M_A_A8 M_B_DQ30 AK25 AY46 M_B_A7
M_A_DQ32 SA_DQ31 SA_MA8 M_A_A9 M_B_DQ31 SB_DQ30 SB_MA7 M_B_A8
AY58 SA_DQ32 SA_MA9 AU40 AL25 SB_DQ31 SB_MA8 AY47
M_A_DQ33 AW58 AP35 M_A_A10 M_B_DQ32 AY23 DDR CHANNEL B AU46 M_B_A9
M_A_DQ34 SA_DQ33 SA_MA10 M_A_A11 M_B_DQ33 SB_DQ32 SB_MA9 M_B_A10
AY56 SA_DQ34 SA_MA11 AW41 AW23 SB_DQ33 SB_MA10 AK36
M_A_DQ35 AW56 AU41 M_A_A12 M_B_DQ34 AY21 AV47 M_B_A11
M_A_DQ36 SA_DQ35 SA_MA12 M_A_A13 M_B_DQ35 SB_DQ34 SB_MA11 M_B_A12
C AV58 SA_DQ36 SA_MA13 AR35 AW21 SB_DQ35 SB_MA12 AU47 C
M_A_DQ37 AU58 AV42 M_A_A14 M_B_DQ36 AV23 AK33 M_B_A13
M_A_DQ38 SA_DQ37 SA_MA14 M_A_A15 M_B_DQ37 SB_DQ36 SB_MA13 M_B_A14
AV56 SA_DQ38 SA_MA15 AU42 AU23 SB_DQ37 SB_MA14 AR46
M_A_DQ39 AU56 M_A_DQS#[7:0] [12] M_B_DQ38 AV21 AP46 M_B_A15
M_A_DQ40 SA_DQ39 M_A_DQS#0 M_B_DQ39 SB_DQ38 SB_MA15
AY54 SA_DQ40 SA_DQSN0 AJ61 AU21 SB_DQ39 M_B_DQS#[7:0] [13]
M_A_DQ41 AW54 AN62 M_A_DQS#1 M_B_DQ40 AY19 AW30 M_B_DQS#0
M_A_DQ42 SA_DQ41 SA_DQSN1 M_A_DQS#2 M_B_DQ41 SB_DQ40 SB_DQSN0 M_B_DQS#1
AY52 SA_DQ42 SA_DQSN2 AM58 AW19 SB_DQ41 SB_DQSN1 AV26
M_A_DQ43 AW52 AM55 M_A_DQS#3 M_B_DQ42 AY17 AN28 M_B_DQS#2
M_A_DQ44 SA_DQ43 SA_DQSN3 M_A_DQS#4 M_B_DQ43 SB_DQ42 SB_DQSN2 M_B_DQS#3
AV54 AV57 AW17 AN25
M_A_DQ45 SA_DQ44 SA_DQSN4 M_A_DQS#5 M_B_DQ44 SB_DQ43 SB_DQSN3 M_B_DQS#4
AU54 AV53 AV19 AW22
M_A_DQ46 SA_DQ45 SA_DQSN5 M_A_DQS#6 M_B_DQ45 SB_DQ44 SB_DQSN4 M_B_DQS#5
AV52 AL43 AU19 AV18
M_A_DQ47 SA_DQ46 SA_DQSN6 M_A_DQS#7 M_B_DQ46 SB_DQ45 SB_DQSN5 M_B_DQS#6
AU52 AL48 AV17 AN21
M_A_DQ48 SA_DQ47 SA_DQSN7 M_B_DQ47 SB_DQ46 SB_DQSN6 M_B_DQS#7
AK40 M_A_DQS[7:0] [12] AU17 AN18
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ48 SB_DQ47 SB_DQSN7
AK42 AJ62 AR21 M_B_DQS[7:0] [13]
M_A_DQ50 SA_DQ49 SA_DQSP0 M_A_DQS1 M_B_DQ49 SB_DQ48 M_B_DQS0
AM43 AN61 AR22 AV30
M_A_DQ51 SA_DQ50 SA_DQSP1 M_A_DQS2 M_B_DQ50 SB_DQ49 SB_DQSP0 M_B_DQS1
AM45 AN58 AL21 AW26
M_A_DQ52 SA_DQ51 SA_DQSP2 M_A_DQS3 M_B_DQ51 SB_DQ50 SB_DQSP1 M_B_DQS2
AK45 AN55 AM22 AM28
M_A_DQ53 SA_DQ52 SA_DQSP3 M_A_DQS4 M_B_DQ52 SB_DQ51 SB_DQSP2 M_B_DQS3
AK43 AW57 AN22 AM25
M_A_DQ54 SA_DQ53 SA_DQSP4 M_A_DQS5 M_B_DQ53 SB_DQ52 SB_DQSP3 M_B_DQS4
AM40 AW53 AP21 AV22
M_A_DQ55 SA_DQ54 SA_DQSP5 M_A_DQS6 M_B_DQ54 SB_DQ53 SB_DQSP4 M_B_DQS5
AM42 AL42 AK21 AW18
M_A_DQ56 SA_DQ55 SA_DQSP6 M_A_DQS7 M_B_DQ55 SB_DQ54 SB_DQSP5 M_B_DQS6
AM46 AL49 AK22 AM21
M_A_DQ57 SA_DQ56 SA_DQSP7 M_B_DQ56 SB_DQ55 SB_DQSP6 M_B_DQS7
AK46 AN20 AM18
M_A_DQ58 SA_DQ57 +V_SM_VREF_CNT M_B_DQ57 SB_DQ56 SB_DQSP7
AM49 AP49 +V_SM_VREF_CNT [37] AR20
M_A_DQ59 SA_DQ58 SM_VREF_CA M_B_DQ58 SB_DQ57
AK49 AR51 DDR_WR_VREF01 [12] AK18
M_A_DQ60 SA_DQ59 SM_VREF_DQ0 M_B_DQ59 SB_DQ58
AM48 AP51 DDR_WR_VREF02 [13] AL18
M_A_DQ61 SA_DQ60 SM_VREF_DQ1 M_B_DQ60 SB_DQ59
AK48 AK20
M_A_DQ62 SA_DQ61 M_B_DQ61 SB_DQ60
AM51 AM20
M_A_DQ63 SA_DQ62 M_B_DQ62 SB_DQ61
AK51 AR18
SA_DQ63 M_B_DQ63 SB_DQ62
AP18
SB_DQ63

B B

HASWELL-6-GP HASWELL-6-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 5 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

CPU1S HSW_ULT_DDR3L 19 OF 19

D D

CFG[19:0]
[96] CFG[19:0]
CFG0 AC60 AV63
CFG1 CFG0 RSVD_TP#AV63
AC62 CFG1 RSVD_TP#AU63 AU63
CFG2 AC63
CFG3 CFG2
AA63 CFG3
CFG4 AA60 C63
CFG5 CFG4 RSVD_TP#C63
Y62 CFG5 RSVD_TP#C62 C62
CFG6 Y61 B43 EDP_SPARE 1
CFG7 CFG6 RSVD#B43 TP605
Y60 CFG7
CFG8 V62 A51
CFG9 CFG8 RSVD_TP#A51
V61 CFG9 RSVD_TP#B51 B51
CFG10 V60
CFG11 CFG10
U60 CFG11 RSVD_TP#L60 L60
CFG12 T63
CFG13 CFG12 RESERVED
T62 CFG13 RSVD#N60 N60
CFG14 T61
CFG15 CFG14
T60 CFG15 RSVD#W23 W23
Y22 PROC_OPI_COMP3 R606 1 2 49D9R2F-GP
CFG16 AA62
RSVD#Y22
AY15 PROC_OPI_COMP R602 1 DY 2 49D9R2F-GP
CFG18 CFG16 PROC_OPI_RCOMP
U63 CFG18
CFG17 AA61 AV62
CFG19 CFG17 RSVD#AV62
U62 CFG19 RSVD#D58 D58

CFG_RCOMP
1 2 V63 CFG_RCOMP VSS P22
N21
Layout Note:
VSS
R601 A5 RSVD#A5
1.Referenced "continuous" VSS plane only.
49D9R2F-GP P20 HVM_CLK# 1 2.Avoid routing next to clock pins or noisy
RSVD#P20
C E1 R20 HVM_CLK 1 TP619 C
D1
RSVD#E1 RSVD#R20 TP620 signals.
RSVD#D1 3.Trace width: 12~15mil
J20 RSVD#J20
H18 RSVD#H18 4.Isolation Spacing: 12mil
1 2 TD_IREF B12 5.Max length: 500mil
TD_IREF
R603
8K2R2F-1-GP

CFG3

1
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
R604
1KR2J-1-GP 0 : ENABLED
DY
2
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED

CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
B 1KR2J-1-GP B
0 : ENABLED
CFG[4] AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
2

1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RESERVED)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 6 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

HSW_ULT_DDR3L VCC_CORE
CPU1L 12 OF 19

L59 RSVD#L59 VCC C36

1D35V_S3 J58 C40
RSVD#J58 VCC
VCC C44
1D05S_VCCST AH26 C48
VDDQ VCC
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
R703 1 2 75R2F-2-GP VR_SVID_ALERT# AJ37 E23
VDDQ VCC
AN33 VDDQ VCC E25
R704 1 2 130R2F-1-GP H_CPU_SVIDDAT AP43 E27
VCC_CORE VDDQ VCC
Layout Note: AR48
AY35
VDDQ VCC E29
E31
VDDQ VCC
1. Place close to CPU AY40 VDDQ VCC E33
2. VCC_SENSE/ VSS_SENSE AY44 VDDQ VCC E35

1
AY50 E37
impedance=50 ohm VDDQ VCC
E39
3. Lwngth match<25mil R702 VCC
VCC_CORE F59 VCC VCC E41
100R2F-L1-GP-U N58 E43
RSVD#N58 VCC
AC58 E45

2
RSVD#AC58 VCC
VCC E47
[46] VCC_SENSE E63 VCC_SENSE VCC E49
AB23 RSVD#AB23 VCC E51
TP701 1 TP_VCCIO_OUT A59 VCCIO_OUT VCC E53
+VCCIOA_OUT E20 VCCIOA_OUT VCC E55
C AD23 E57 C
RSVD#AD23 VCC
AA23 RSVD#AA23 VCC F24
R701 AE59 F28
43R2J-GP RSVD#AE59 VCC
VCC F32
[46] VR_SVID_ALERT# 1 2H_CPU_SVIDALRT# L62 VIDALERT# VCC F36
H_CPU_SVIDCLK N63 HSW ULT POWER F40
3D3V_S5 [46] H_CPU_SVIDCLK VIDSCLK VCC
H_CPU_SVIDDAT L63 F44
[46] H_CPU_SVIDDAT VIDSOUT VCC
H_VCCST_PW RGD B59 F48
VCCST_PWRGD VCC
[46] H_VR_ENABLE F60 VR_EN VCC F52
1 2 10KR2J-3-GP C59 F56
1D05S_VCCST C705 1 2 IMVP_PW RGD_R DY R710 VR_READY VCC
G23
DY VCC
1

D63 G25
C702 DY SCD1U25V2KX-GP PW R_DEBUG H59
VSS VCC
G27
SCD1U10V2KX-5GP PWR_DEBUG# VCC
P62 G29
2

VSS VCC
1D05S_VCCST R705 1 2150R2J-L1-GP-U P60 RSVD_TP#P60 VCC G31
1

P61 RSVD_TP#P61 VCC G33

U701 R706 N59 G35
RSVD_TP#N59 VCC

[36,48] 1D05V_VTT_PW RGD 1 5 DY 10KR2J-3-GP N61

T59
RSVD_TP#N61 VCC G37
G39
NC#1 VCC RSVD#T59 VCC
AD60 G41
2

RSVD#AD60 VCC
2 AD59 G43
A DY AA59
RSVD#AD59 VCC
G45
EC701 H_VCCST_PW RGD RSVD#AA59 VCC
3 GND Y 4 AE60 RSVD#AE60 VCC G47
1
SCD1U25V2KX-GP

AC59 RSVD#AC59 VCC G49

AG58 G51
DY 74LVC1G07GW -GP U59
RSVD#AG58 VCC
G53
2

1D05S_VCCST RSVD#U59 VCC

73.01G07.0HG V59 RSVD#V59 VCC G55
VCC G57
AC22 VCCST VCC H23
B B
AE22 VCCST VCC J23
1 2 VCC_CORE AE23 K23
R707 VCCST VCC
VCC K57
100KR2F-L1-GP AB57 L22
VCC VCC
1

AD57 VCC VCC M23

R709 AG57 M57
VCC VCC
51KR2J-1-GP C24 VCC VCC P57
C28 VCC VCC U57
C32 W57
2

VCC VCC

HASW ELL-6-GP

A00 0619

H_VR_ENABLE

1
PR714 PR715
1 2
DY 10KR2F-2-GP
1D05V_S0 1D05S_VCCST
0R2J-2-GP

2
1 2 [24,46] IMVP_PW RGD 1 2 IMVP_PW RGD_L IMVP_PW RGD_R
PD701
R713
SC22U6D3V5MX-2GP

SC1U6D3V2KX-GP
C701

C703

R711 100KR2F-L1-GP C704 A K

DY
1

1
SCD1U25V2KX-GP

0R0805-PAD-2-GP-U
1

R712 PC706
A
DY DY 47KR2F-GP BAT54LPS-7-GP DY SCD047U10V2KX-2GP
<Core Design> A
2

2
DY
2
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 7 of 101
5 4 3 2 1
 5 4 3 2 1
SSID = CPU

D D

X01 remove CPU1A HSW_ULT_DDR3L 1 OF 19

[54] HDMI_DATA2# C54 DDI1_TXN0 EDP_TXN0 C45 EDP_TX0_DN [53]

[54] HDMI_DATA2 C55 DDI1_TXP0 EDP_TXP0 B46 EDP_TX0_DP [53]
[54] HDMI_DATA1# B58 A47
HDMI [54] HDMI_DATA1 C58
DDI1_TXN1
DDI1_TXP1
EDP_TXN1
EDP_TXP1 B47
EDP_TX1_DN
EDP_TX1_DP
[53]
[53]
+VCCIOA_OUT
[54] HDMI_DATA0# B55 DDI1_TXN2
[54] HDMI_DATA0 A55 DDI1_TXP2 EDP_TXN2 C47
[54] HDMI_CLK# A57 DDI1_TXN3 EDP_TXP2 C46 Design Guideline:

1
[54] HDMI_CLK B57 DDI1_TXP3 EDP_TXN3 A49 EDP_COMP keep routing length max 100 mils.
DDI EDP B49 R801
EDP_TXP3 Trace Width:20 mils.
C51 DDI2_TXN0 24D9R2F-L-GP
C50 DDI2_TXP0 EDP_AUXN A45 EDP_AUX_DN [53]
C53 B45 EDP_AUX_DP [53]

2
DDI2_TXN1 EDP_AUXP
B54 DDI2_TXP1
C49 D20 EDP_COMP
DDI2_TXN2 EDP_RCOMP EDP_BRIGHTNESS
B50 DDI2_TXP2 EDP_DISP_UTIL A43 1 TP801
A53 DDI2_TXN3
C B53 DDI2_TXP3 C

HASW ELL-6-GP

B B

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDI/EDP)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 8 of 101
 5 4 3 2 1

SSID = CPU

D D

CPU1P HSW_ULT_DDR3L 16 OF 19

VSS H17
D33 VSS VSS H57
D34 VSS VSS J10
D35 VSS VSS J22
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
D59 VSS VSS R10
C D62 R22 C
VSS VSS
D8 VSS VSS R8
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS
G3 VSS
G5 VSS VSS V58
G6 VSS VSS AH46
G8 VSS VSS V23
H13 E62 VSS_SENSE VSS_SENSE [46]
VSS VSS_SENSE
VSS AH16

100R2F-L1-GP-U
1
HASW ELL-6-GP
Layout Note:

R901
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm

2
B B
3. Lwngth match<25mil

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 9 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

1D35V_S3

D D

C1001
SC10U6D3V3MX-GP

C1002
SC10U6D3V3MX-GP

C1003
SC10U6D3V3MX-GP

C1004
SC10U6D3V3MX-GP

C1005
SC10U6D3V3MX-GP

C1006
SC10U6D3V3MX-GP
Layout Note:
1

1
As close to CPU as possible
DY
2

2
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
C1017

C1018

C1019

C1020
1

1
DY DY
2

Layout Note:
Direct tie to CPU VccIn/Vss balls

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(Power CAP1)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 10 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

MAX: 1.92A
1.838A 41mA 42mA

1D05V_HSIO +V1.05DX_MODPHY_PCH 1D05V_HSIO +V1.05S_ASATA3PLL

1D05V_HSIO +V1.05S_AUSB3PLL
1 2 L1102 1 2 IND-2D2UH-196-GP +V1.05S_ASATA3PLL

C1102
SC1U6D3V2KX-GP

C1101
SC1U6D3V2KX-GP
L1101 1 2 IND-2D2UH-196-GP +V1.05S_AUSB3PLL
68.2R21D.10R

C1105
SC1U6D3V2KX-GP

C1106
SC10U6D3V3MX-GP

C1107
SC10U6D3V3MX-GP
R1101

1
C1103
SC1U6D3V2KX-GP

C1104
SC10U6D3V3MX-GP

C1123
SC10U6D3V3MX-GP
0R0805-PAD-2-GP-U
68.2R21D.10R

1
DY
2

2
DY

2
2

2
CAP need close to pin K9 L10 CAP need close to pin B18 1205 Add CAP need close to pin B11

57mA 62mA 200mA

C C

1D05V_S0 +V1.05S_APLLOPI 1D05V_S0 +V1.05S_AXCK_DCB

3D3V_S5_PCH +V3.3A_PSUS
L1103 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_DCB
1 2 +V1.05S_APLLOPI 1 2
68.2R21D.10R

C1108
SC10U6D3V3MX-GP

C1111
SC1U6D3V2KX-GP

C1112
SC10U6D3V3MX-GP

C1125
SC10U6D3V3MX-GP
R1102 R1103

1
C1109
SC1U6D3V2KX-GP

C1110
SC10U6D3V3MX-GP

C1124
SC10U6D3V3MX-GP
0R0603-PAD-2-GP-U 0R0603-PAD-2-GP-U
1

DY DY
DY

2
2

1205 Add
1205 Add
CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18
31mA 658mA 1.632A 1mA
1D05V_S0 +1.05M_ASW 1D05V_S0
1D05V_S0 IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL RTC_AUX_S5
L1104 1 2
1 2 R1104
C1115
SC22U6D3V5MX-2GP

C1116
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C1117

SC1U6D3V2KX-GP
C1118

C1119
SC10U6D3V3MX-GP

C1120
SCD1U10V2KX-5GP

C1121
SCD1U10V2KX-5GP

C1122
SC1U6D3V2KX-GP
0R0603-PAD-2-GP-U
68.2R21D.10R
1

1
C1113
SC1U6D3V2KX-GP

C1114
SC10U6D3V3MX-GP
1

DY DY
DY
2

2
B B
2

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11 CAP need close to pin AG10

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(Power CAP2)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 11 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY
DM1

[5] M_A_A[15:0] M_A_A0 98 NP1

M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96 A2
M_A_A3 95 110 M_A_RAS# [5] SA0_DIMA Note:
M_A_A4 A3 RAS# SA1_DIMA
92 113 M_A_WE# [5]
M_A_A5 A4 WE# SA0 DIM0 = 0, SA1_DIM0 = 0
91 115 M_A_CAS# [5]
M_A_A6 A5 CAS#
90 A6 SO-DIMMA SPD Address is 0xA0

1
M_A_A7 86 114 M_A_DIMA_CS#0 [5]
A7 CS0#
D M_A_A8 89
A8 CS1#
121 M_A_DIMA_CS#1 [5] R1202 R1201 SO-DIMMA TS Address is 0x30 D
M_A_A9 85 0R0402-PAD-2-GP 0R0402-PAD-2-GP
M_A_A10 A9
107 A10/AP CKE0 73 M_A_DIMA_CKE0 [5]
M_A_A11 84 74 M_A_DIMA_CKE1 [5]

2
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 [5]
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 [5]
M_A_A15 A14 CK0#
78
A15
[5] M_A_BS2 79 102 M_A_DIMA_CLK_DDR1 [5]
A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 [5]
CK1#
[5] M_A_BS0 109
BA0
[5] M_A_BS1 108 11
BA1 DM0
[5] M_A_DQ[63:0] DM1 28
M_A_DQ13 5 46
M_A_DQ8 DQ0 DM2
7 DQ1 DM3 63
M_A_DQ14 15 136
M_A_DQ10 DQ2 DM4
M_VREF_CA_DIMMA Layout Note: M_A_DQ9
17
4
DQ3 DM5 153
170
DQ4 DM6
Place these caps M_A_DQ12 6 DQ5 DM7 187
close to VREF_CA M_A_DQ15 16
M_A_DQ11 DQ6
18 DQ7 SDA 200 PCH_SMBDATA [13,18,58,62,67]
M_A_DQ29 21 202
DQ8 SCL PCH_SMBCLK [13,18,58,62,67]
M_A_DQ28 23
M_A_DQ30 DQ9 3D3V_S0
33 DQ10 EVENT# 198
1

M_A_DQ31 35
DY DY DQ11
C1201

C1218

C1202
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

M_A_DQ25 22 199
M_A_DQ24 DQ12 VDDSPD
24
2

M_A_DQ27 DQ13 SA0_DIMA

34 DQ14 SA0 197

1
M_A_DQ26 36 201 SA1_DIMA C1203
M_A_DQ44 DQ15 SA1 SCD1U10V2KX-5GP
39
M_A_DQ41 41
DQ16
77
DY

2
M_A_DQ43 DQ17 NC#1
M_A_DQ47
51
53
DQ18 NC#2 122
125 1D35V_S3 Layout Note:
M_A_DQ45 DQ19 NC#/TEST
40 DQ20
Place Close SO-DIMMA.
C M_A_DQ40 42 75 C
M_A_DQ42 DQ21 VDD1
50 DQ22 VDD2 76
M_A_DQ46
Layout Note: M_A_DQ51
52
57
DQ23 VDD3 81
82
DQ24 VDD4
Place these caps M_A_DQ50 59 DQ25 VDD5 87
M_A_DQ49 67 88 1D35V_S3
close to VREF_DQ M_A_DQ48 DQ26 VDD6 0D675V_VTTREF 1D35V_S3
69 DQ27 VDD7 93
M_VREF_DQ_DIMMA M_A_DQ52 56 94
DQ28 VDD8 [5] DDR_WR_VREF01
M_A_DQ53 58 99
M_A_DQ54 DQ29 VDD9
68 100
DQ30 VDD10

1
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_A_DQ55 70 105 R1215
DQ31 VDD11

C1207

C1208

C1209
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C1220

C1221

C1222
M_A_DQ0 129 106 0R2J-2-GP R1211
DQ32 VDD12

1
SC2D2U6D3V2MX-GP

M_A_DQ1 131 111 1K8R2F-GP

DQ33 VDD13 DY
C1205

M_A_DQ2 141 112

DQ34 VDD14 DY
1

M_A_DQ6 143 117 2R2F-GP

2
DQ35 VDD15
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C1204

C1206

M_A_DQ5 130 118 R1210

DY DY M_A_DQ4 132
DQ36 VDD16
123 1 2 M_VREF_DQ_DIMMA
2

M_A_DQ3 DQ37 VDD17

140 124
M_A_DQ7 DQ38 VDD18
142
DQ39

1
M_A_DQ21 147 2 C1219
M_A_DQ20 DQ40 VSS SCD022U16V2JX-GP R1213
149 3
M_A_DQ17 DQ41 VSS 1K8R2F-GP
157 8

2
M_A_DQ16 DQ42 VSS
159 9
DQ43 VSS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
M_A_DQ18 146 13 +V_VREF_PATH1

2
DQ44 VSS

1
0D675V_S0

C1210

C1211

C1212

C1213
M_A_DQ19 148 14
DQ45 VSS

1
M_A_DQ22 158 19 R1212
M_A_DQ23 DQ46 VSS 24D9R2F-L-GP
160 20
M_A_DQ36 DQ47 VSS
163 25

2
M_A_DQ33 DQ48 VSS
165 26

2
DQ49 VSS
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_A_DQ34 175 31
DQ50 VSS
C1214

C1215

C1216

M_A_DQ38 177 32
DQ51 VSS
1

M_A_DQ37
Layout Note: M_A_DQ32
164
166
DQ52 VSS
37
38
DY DY Place these caps M_A_DQ35 174
DQ53 VSS
43
2

M_A_DQ39 DQ54 VSS

close to VTT1 and 176 44
B
M_A_DQ62 DQ55 VSS B
181 48
VTT2. M_A_DQ58 183
DQ56 VSS
49
M_A_DQ60 191
DQ57 VSS
54
Layout Note:
M_A_DQ61 DQ58 VSS
193
DQ59 VSS
55 Place these Caps near SO-DIMMA.
M_A_DQ63 180 60
M_A_DQ59 DQ60 VSS 1D35V_S3
182 61
M_A_DQ56 DQ61 VSS
192 65
M_A_DQ57 DQ62 VSS
194 66
DQ63 VSS
71
M_A_DQS#1 VSS
10 72
M_A_DQS#3 DQS0# VSS
27 127

D
M_A_DQS#5 DQS1# VSS
45 128
M_A_DQS#6 DQS2# VSS Q1202
62 133
M_A_DQS#0 DQS3# VSS 5V_S5
135 134 2N7002K-2-GP
M_A_DQS#2 DQS4# VSS
152 138
M_A_DQS#4 DQS5# VSS 84.2N702.J31
[5] M_A_DQS#[7:0] 169 139
M_A_DQS#7 DQS6# VSS 1D35V_S3 2ND = 84.2N702.031 R1206
186
DQS7# VSS
144 1 2 66D5R2F-GP M_A_DIMA_ODT0
[5] M_A_DQS[7:0] 145
VSS

1
M_A_DQS1 12 150 R1207 1 2 66D5R2F-GP M_A_DIMA_ODT1

S
G
M_A_DQS3 DQS0 VSS
29
DQS1 VSS
151 X01 change to short pad R1208
M_A_DQS5 47 155 220KR2J-L2-GP M_A_B_DIMM_ODT R1203 1 2 66D5R2F-GP
DQS2 VSS M_B_DIMB_ODT0 [13]
M_A_DQS6 64 156
DQS3 VSS R1209
M_A_DQS0 137 161 1 2 66D5R2F-GP M_B_DIMB_ODT1 [13]

2
M_A_DQS2 DQS4 VSS 0R0402-PAD-2-GP
154 162
M_A_DQS4 DQS5 VSS
171 167 R1205
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS DDR_PG_CTRL_R DDR_VTT_PG_CTRL
172 [4] DDR_PG_CTRL 1 2 S D DDR_VTT_PG_CTRL [49]
M_A_DIMA_ODT0 VSS
116 173
ODT0 VSS

1
M_A_DIMA_ODT1 120 178
ODT1 VSS R1204
179 Q1201
VSS 2MR2-GP
M_VREF_CA_DIMMA 126
VREF_CA VSS
184 Q1201 Need check Vth=1V DMN5L06K-7-GP DY
Layout Note: M_VREF_DQ_DIMMA 1
VREF_DQ VSS
185
189
84.05067.031

2
VSS
All VREF traces should [4,13] DDR3_DRAMRST# 30 RESET# VSS 190
A A
have width=20mil; VSS 195
196
spacing=20 mil VSS
C1217
SCD1U10V2KX-5GP

0D675V_S0 203 VTT1 VSS 205 <Core Design>

1

204 VTT2 VSS 206

DY SKT_DDR 204P SMD
Wistron Corporation
2

DDR3-204P-122-GP-U1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
62.10017.Z51 Taipei Hsien 221, Taiwan, R.O.C.

Title

close to dimm DDR3L-SODIMM1

Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 12 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DM2

M_B_A0 98 NP1
M_B_A1 A0 NP1
97 A1 NP2
NP2
M_B_A[15:0] [5] M_B_A2 96
M_B_A3 A2
95 110 M_B_RAS# [5]
M_B_A4 A3 RAS#
92 113 M_B_WE# [5]
M_B_A5 A4 WE#
91 A5 CAS# 115 M_B_CAS# [5]
M_B_A6 90
D M_B_A7 A6 D
86 114 M_B_DIMB_CS#0 [5]
M_B_A8 A7 CS0#
89 A8 CS1# 121 M_B_DIMB_CS#1 [5]
M_B_A9 85
M_B_A10 A9
M_B_A11
107
A10/AP CKE0
73 M_B_DIMB_CKE0 [5] Note:
84 74 M_B_DIMB_CKE1 [5]
M_B_A12 A11 CKE1 SO-DIMMB SPD Address is 0xA4
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 [5] SO-DIMMB TS Address is 0x34
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 [5]
M_B_A15 A14 CK0#
78
A15
[5] M_B_BS2 79 102 M_B_DIMB_CLK_DDR1 [5]
A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 [5]
CK1#
[5] M_B_BS0 109
BA0
[5] M_B_BS1 108 BA1 DM0 11
[5] M_B_DQ[63:0] DM1 28
M_B_DQ8 5 46 3D3V_S0
M_VREF_CA_DIMMB M_B_DQ14 DQ0 DM2
7 DQ1 DM3 63
M_B_DQ10 15 136
M_B_DQ11 DQ2 DM4
17 DQ3 DM5 153

1
M_B_DQ12
Layout Note: M_B_DQ9
4
6
DQ4 DM6 170
187 R1301
DQ5 DM7 10KR2J-3-GP
Place these caps M_B_DQ13 16 DQ6
1

close to VREF_CA M_B_DQ15 18 200

DQ7 SDA PCH_SMBDATA [12,18,58,62,67]
C1301

EC1302

C1302
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

M_B_DQ28 21 202
DY DY PCH_SMBCLK [12,18,58,62,67]

2
M_B_DQ29 DQ8 SCL
23
2

M_B_DQ26 DQ9 3D3V_S0

33 DQ10 EVENT# 198
M_B_DQ27 35
M_B_DQ25 DQ11 SA1_DIMB
22 DQ12 VDDSPD 199
M_B_DQ24 24 DQ13

1
M_B_DQ30 34 197 SA0_DIMB SA0_DIMB
M_B_DQ31 36
DQ14 SA0
201 SA1_DIMB C1303 DY
M_B_DQ40 DQ15 SA1 SCD1U10V2KX-5GP
39

2
DQ16

1
M_B_DQ41 41 77
M_B_DQ46 DQ17 NC#1 R1302
51 DQ18 NC#2 122
M_B_DQ42 53 125 1D35V_S3 0R0402-PAD-2-GP
M_B_DQ45 DQ19 NC#/TEST
C 40 DQ20 C
M_B_DQ44 42 75

2
M_B_DQ47 DQ21 VDD1
50 DQ22 VDD2 76
M_B_DQ43 52 81
M_B_DQ56 DQ23 VDD3
57 82
M_B_DQ57 59
DQ24 VDD4
87
Layout Note:
M_B_DQ59 DQ25 VDD5
Layout Note: 67 DQ26 VDD6 88 Place Close SO-DIMMA.
M_VREF_DQ_DIMMB M_B_DQ58 69 93
DQ27 VDD7
Place these caps M_B_DQ61 56
DQ28 VDD8
94
close to VREF_DQ M_B_DQ60 58 99
M_B_DQ63 DQ29 VDD9
68 100
M_B_DQ62 DQ30 VDD10 1D35V_S3
70 105
DQ31 VDD11
SC2D2U6D3V2MX-GP
C1305

M_B_DQ4 129 106

DQ32 VDD12
1

M_B_DQ1 131 111 0D675V_VTTREF 1D35V_S3

DQ33 VDD13 [5] DDR_WR_VREF02
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
C1304

C1306

M_B_DQ3 141 112

DY DY M_B_DQ7 143
DQ34 VDD14
117
2

DQ35 VDD15

1
M_B_DQ5 130 118
DQ36 VDD16

C1312

C1311

C1310

C1309

C1308

C1307
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
M_B_DQ0 132 123 R1308 R1306
DQ37 VDD17 DY

1
M_B_DQ2 140 124 0R2J-2-GP 1K8R2F-GP
M_B_DQ6 DQ38 VDD18
142
M_B_DQ21 147
DQ39
2
DY DY DY DY 2R2F-GP

2
M_B_DQ20 DQ40 VSS R1304
149 3
M_B_DQ22 DQ41 VSS
157 8 1 2 M_VREF_DQ_DIMMB
M_B_DQ23 DQ42 VSS
159 9
M_B_DQ16 DQ43 VSS
146 13
DQ44 VSS

1
M_B_DQ17 148 14 C1320
M_B_DQ19 DQ45 VSS SCD022U16V2JX-GP R1303
158 19
0D675V_S0 M_B_DQ18 DQ46 VSS 1K8R2F-GP
160 20

2
DQ47 VSS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_B_DQ36
Layout Note: 163
DQ48 VSS
25

C1313

C1314

C1315

EC1301
M_B_DQ33 165 26 +V_VREF_PATH2

2
DQ49 VSS

1
Place these caps M_B_DQ35 175
DQ50 VSS
31
close to VTT1 and M_B_DQ39 177 32 R1307
DQ51 VSS
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C1316

C1317

C1318

M_B_DQ37 164 37 24D9R2F-L-GP

VTT2. DY

2
DQ52 VSS
1

M_B_DQ32 166 38
M_B_DQ34 DQ53 VSS
174 43
DY

2
B
M_B_DQ38 DQ54 VSS B
176 44
2

M_B_DQ52 DQ55 VSS

181 48
M_B_DQ49 DQ56 VSS
183 49
M_B_DQ48 DQ57 VSS
191 54
M_B_DQ53 DQ58 VSS
193 55
M_B_DQ51 DQ59 VSS
180 60
M_B_DQ55 DQ60 VSS
182 61
M_B_DQ54 192
DQ61 VSS
65
Layout Note:
M_B_DQ50 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
71
M_B_DQS#1 VSS
10 72
M_B_DQS#3 DQS0# VSS
27 127
M_B_DQS#5 DQS1# VSS
45 128
M_B_DQS#7 DQS2# VSS
62 133
M_B_DQS#0 DQS3# VSS
135 134
M_B_DQS#2 DQS4# VSS
152 138
M_B_DQS#4 DQS5# VSS
169 139
M_B_DQS#6 DQS6# VSS
M_B_DQS#[7:0] [5] 186 144
DQS7# VSS
145
M_B_DQS1 VSS
M_B_DQS[7:0] [5] 12 150
M_B_DQS3 DQS0 VSS
29 151
M_B_DQS5 DQS1 VSS
47 155
M_B_DQS7 DQS2 VSS
64 156
M_B_DQS0 DQS3 VSS
137 161
M_B_DQS2 DQS4 VSS
154 162
M_B_DQS4 DQS5 VSS
171 167
M_B_DQS6 DQS6 VSS
188 168
DQS7 VSS
172
VSS
[12] M_B_DIMB_ODT0 116 173
ODT0 VSS
[12] M_B_DIMB_ODT1 120 178
ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
A Layout Note: 30
VSS 189
190 A
[4,12] DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS 195
have width=20mil; VSS 196 <Core Design>
C1319
SCD1U10V2KX-5GP

0D675V_S0 203 205

spacing=20 mil VTT1 VSS
1

204 VTT2 VSS 206

DY SKT_DDR 204P SMD Wistron Corporation
2

DDR3-204P-122-GP-U1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
62.10017.Z51
Title

DDR3L-SODIMM2
close to dimm Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 13 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

M1&M3
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 14 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

3D3V_S0

1
2
RN1501
HSW_ULT_DDR3L
CPU1I 9 OF 19 SRN2K2J-1-GP
C C

4
3
0R0402-PAD-2-GP
[53] L_BKLT_CTRL 1 R1501 2L_BKLT_CTRL_R B8 EDP_BKLCTL DDPB_CTRLCLK B9 PCH_HDMI_CLK [54]
[24] L_BKLT_EN A9 EDP_BKLEN DDPB_CTRLDATA C9 PCH_HDMI_DATA [54]
RN1504 C6 eDP SIDEBAND D9
[52] EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK
1 4 DGPU_PW R_EN D11
DDPC_CTRLDATA
2
OPS 3 DGPU_HOLD_RST#
A00 change to PIRQB#
SRN10KJ-5-GP 0R0402-PAD-2-GP PIRQA# U6 PIRQA#/GPIO77
[67] HDD_FALL_INT 1 R1503 2 PIRQB# P4 PIRQB#/GPIO78 DDPB_AUXN C5
100KR2J-1-GP PIRQC# N4 B6
R1509 PIRQD# PIRQC#/GPIO79 DISPLAY DDPC_AUXN
N2 PIRQD#/GPIO80 DDPB_AUXP B5
1 2 DGPU_PW ROK TP1501 1 PCI_PME# AD4 PME# DDPC_AUXP A6
PCIE
TP1503 1 MCP_GPIO55 U7
DGPU_PW R_EN L1 GPIO55
[82,83] DGPU_PW R_EN GPIO52
[73] DGPU_HOLD_RST# DGPU_HOLD_RST#L3 C8
DGPU_PW ROK GPIO54 DDPB_HPD HDMI_PCH_DET [54]
[24,82,83] DGPU_PW ROK R5 GPIO51 DDPC_HPD A8
TP1502 1 PCH_SD_CD# L4 D6 EDP_HPD [52,53]
GPIO53 EDP_HPD

3D3V_S0
HASW ELL-6-GP

B RN1505 B

8 1 PIRQD#
7 2 PIRQC#
6 3 PIRQB#
5 4 PIRQA#

SRN10KJ-6-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU ( EDP SIDEBAND/GPIO/DDI )

Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 15 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D USB 2.0 Table D

CPU1K HSW_ULT_DDR3L 11 OF 19 Pair Device

PCIE Table
Port Device Share BUS [73] CPU_RXN_C_dGPU_TXN0 F10 PERN5_L0 USB2N0 AN8 USB_PN0 [34] 0 USB3.0 Port2
[73] CPU_RXP_C_dGPU_TXP0 E10 PERP5_L0 USB2P0 AM8 USB_PP0 [34]
SCD1U10V2KX-5GP USB3.0 port1
1 N/A USB3.0_3 [73] dGPU_RXN_C_CPU_TXN0 C1606 1OPS 2 dGPU_RXN_CPU_TXN0 C23
PETN5_L0 USB2N1 AR7 USB_PN1 [35] 1 (with Power Share)
[73] dGPU_RXP_C_CPU_TXP0 1OPS 2 dGPU_RXP_CPU_TXP0 C22 AT7 USB_PP1 [35]
C1605 PETP5_L0 USB2P1
2 N/A USB3.0_4 [73] CPU_RXN_C_dGPU_TXN1 SCD1U10V2KX-5GP F8 PERN5_L1 USB2N2 AR8 USB_PN2 [63] 2 USB3.0 Port3
[73] CPU_RXP_C_dGPU_TXP1 E8 PERP5_L1 USB2P2 AP8 USB_PP2 [63]
SCD1U10V2KX-5GP
3 WLAN [73] dGPU_RXN_C_CPU_TXN1 C1608 1OPS 2 dGPU_RXN_CPU_TXN1 B23
PETN5_L1 USB2N3 AR10 USB_PN3 [63] 3 USB3.0 Port4
[73] dGPU_RXP_C_CPU_TXP1 1OPS 2 dGPU_RXP_CPU_TXP1 A23 AT10 USB_PP3 [63]
PETP5_L1 USB2P3
LAN+ C1607
4 Card reader [73] CPU_RXN_C_dGPU_TXN2 SCD1U10V2KX-5GP H10 PERN5_L2 USB2N4 AM15 USB_PN4 [52] 4 CAMERA
[73] CPU_RXP_C_dGPU_TXP2 G10 PERP5_L2 USB2P4 AL15 USB_PP4 [52]
SCD1U10V2KX-5GP
5(4lane) GPU [73] dGPU_RXN_C_CPU_TXN2 C1610 1OPS 2 dGPU_RXN_CPU_TXN2 B21
PETN5_L2 USB2N5 AM13 USB_PN5 [58] 5 WLAN
[73] dGPU_RXP_C_CPU_TXP2 1OPS 2 dGPU_RXP_CPU_TXP2 C21 AN13 USB_PP5 [58]
C1609 PETP5_L2 USB2P5
6(4lane) N/A SATA0~3 [73] CPU_RXN_C_dGPU_TXN3 SCD1U10V2KX-5GP E6 PERN5_L3 USB2N6 AP11 USB_PN6 [52] 6 Touch Panel
[73] CPU_RXP_C_dGPU_TXP3 F6 PERP5_L3 USB2P6 AN11 USB_PP6 [52]
SCD1U10V2KX-5GP
[73] dGPU_RXN_C_CPU_TXN3 C1612 1OPS 2 dGPU_RXN_CPU_TXN3 B22
PETN5_L3 USB2N7 AR13 USB_PN7 1 TP1602 7 N/A
[73] dGPU_RXP_C_CPU_TXP3 1OPS 2 dGPU_RXP_CPU_TXP3 A21 AP13 USB_PP7 1 TP1601
C1611 PETP5_L3 USB2P7
C
[58] PCIE_PRX_W LANTX_N3 SCD1U10V2KX-5GP G11 C
PERN3
[58] PCIE_PRX_W LANTX_P3 F11 PERP3 USB3RN1 G20 USB3_PRX_CTX_N0 [34]
SCD1U10V2KX-5GP H20
USB3RP1 USB3_PRX_CTX_P0 [34]
[58] PCIE_PTX_W LANRX_N3_C C1601 1 2 PCIE_PTX_W LANRX_N3 C29 PETN3 WLAN PCIE USB
[58] PCIE_PTX_W LANRX_P3_C 1 2 PCIE_PTX_W LANRX_P3 B30 C33 USB3_PTX_CRX_N0 [34]
C1602 PETP3 USB3TN1
USB3TP1 B34 USB3_PTX_CRX_P0 [34]
[30] PCIE_PRX_LANTX_N4 SCD1U10V2KX-5GP F13 PERN4
[30] PCIE_PRX_LANTX_P4 G13 PERP4 USB3RN2 E18 USB3_PRX_CTX_N1 [34]
SCD1U10V2KX-5GP LAN+Card reader USB3RP2 F18 USB3_PRX_CTX_P1 [34]
[30] PCIE_PTX_LANRX_N4_C C1603 1 2 PCIE_PTX_LANRX_N4 B29
PCIE_PTX_LANRX_P4 PETN4
[30] PCIE_PTX_LANRX_P4_C 1 2 A29 PETP4 USB3TN2 B33 USB3_PTX_CRX_N1 [34]
C1604 A33 USB3_PTX_CRX_P1 [34]
SCD1U10V2KX-5GP USB3TP2
[63] USB3_PRX_DTX_N2 G17 PERN1/USB3RN3
[63] USB3_PRX_DTX_P2 F17 PERP1/USB3RP3
[63] USB3_PTX_DRX_N2 C30
Layout Note:
PETN1/USB3TN3 USB_COMP 1. USB_COMP using 50 ohm
[63] USB3_PTX_DRX_P2 C31 PETP1/USB3TP3 USBRBIAS# AJ10 1 2
AJ11 R1602 single-ended impedance
USBRBIAS 22D6R2F-L1-GP
[63] USB3_PRX_DTX_N3 F15 PERN2/USB3RN4 RSVD#AN10 AN10 2. Isolation Spacing :15mil
[63] USB3_PRX_DTX_P3 G15 PERP2/USB3RP4 RSVD#AM10 AM10 3. Total trace length<500mil
[63] USB3_PTX_DRX_N3 B31 PETN2/USB3TN4
[63] USB3_PTX_DRX_P3 A31 PETP2/USB3TP4
AL3 USB_OC#0_1 USB_OC#0_1 [35]
OC0/GPIO40# USB_OC#2_3
OC1/GPIO41# AT1 USB_OC#2_3 [35]
AH2 USB_OC#4_5
+V1.05S_AUSB3PLL R1601 OC2/GPIO42# USB_OC#6_7
E15 RSVD#E15 OC3/GPIO43# AV3
3KR2F-GP E13
PCIE_RCOMP RSVD#E13
1 2 A27 PCIE_RCOMP
B B
B27 PCIE_IREF

3D3V_S5_PCH
RN1601
HASW ELL-6-GP USB_OC#0_1 1 8
USB_OC#2_3
Layout Note: USB_OC#4_5
2
3
7
6
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil USB_OC#6_7 4 5
2. Isolation Spacing: 12mil
3. Total trace length<500mil SRN10KJ-6-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/USB)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 16 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
On Die DSW VR Enable R1720 RTC_AUX_S5
330KR2J-L1-GP
DSW ODVREN 1 2
Low = Disable
DSWODVREN High = Enable (default) 1
DY 2
* R1721
330KR2J-L1-GP

D D

RN1703
1 4 PM_RSMRST#
2 3 PM_PCH_PW ROK

1 SRN10KJ-5-GP
2 SYS_PW ROK
R1717 DY 10KR2J-3-GP

3D3V_S0

RN1704
1 4 XDP_DBRESET#
2 3 PM_CLKRUN#

SRN8K2J-3-GP

CPU1H HSW_ULT_DDR3L 8 OF 19

SYSTEM POWER MANAGEMENT NON DS3

0R2J-2-GP
PM_SUSACK#_R AK2 AW7 DSW ODVREN R1704 3D3V_S5 0311 PCH WAKE# pin PH 1K
XDP_DBRESET# SUSACK# DSWVRMEN PCH_DPW ROK
AC3 SYS_RESET# DPWROK AV5 1 2 PM_RSMRST#
C
[24,96] SYS_PW ROK SYS_PW ROK AG2 AJ5 PCH_W AKE# R1703 1 2 1KR2J-1-GP C
R1706 SYS_PWROK WAKE#
[24,26,36] PCH_PW ROK 1 2 0R0402-PAD-2-GP PM_PCH_PW ROK AY7
PCH_PWROK
1 R1707 2 MPW ROK AB5 APWROK
0R0402-PAD-2-GP A00 0618
0R0402-PAD-2-GP PCI_PLTRST# AG7 V5 PM_CLKRUN# 1 R1709 2 PM_CLKRUN#_EC [24]
PLTRST# CLKRUN#/GPIO32 PM_SUS_STAT#1 TP1702
SUS_STAT#/GPIO61 AG4
AE6 SUS_CLK R1710 1 2 PCH_SUSCLK_KBC [24]
SUSCLK/GPIO62 PM_SLP_S5# 1 TP1703 0R0402-PAD-2-GP
SLP_S5#/GPIO63 AP5
PM_RSMRST# AW6
PM_SUSW ARN#_R RSMRST#
AV4 SUSWARN#/SUSPWRDNACK#/GPIO30
[24,96] PM_PW RBTN# PM_PW RBTN# AL7 AJ6 PM_SLP_S4# PM_SLP_S4# [24,49]
AC_PRESENT PWRBTN# SLP_S4# PM_SLP_S3#
[24,76] AC_PRESENT AJ8 ACPRESENT/GPIO31 SLP_S3# AT4 PM_SLP_S3# [24,36,48,49,51]
BATLOW # AN4 AL5 PM_SLP_A# 1 TP1704
PCH_SLP_S0# BATLOW#/GPIO72 SLP_A# PM_SLP_SUS#
[48] PCH_SLP_S0# AF3 SLP_S0# SLP_SUS# AP4 PM_SLP_SUS# [24,38]
1 PCH_SLP_W LAN# AM5 AJ7 PM_SLP_LAN# 1 TP1707
TP1705 SLP_WLAN#/GPIO29 SLP_LAN#
0R0402-PAD-2-GP
R1713

[24,30,58,65,73] PLT_RST# 1 2 PCI_PLTRST#

HASW ELL-6-GP
1

R1715 C1701
100KR2J-1-GP SC220P50V2KX-3GP
DY DY A00 0618
2
2

A00 0618
RN
3D3V_S5 PCH_DPW ROK 1 R1718 2 KBC_DPW ROK [24]
RN1701 1 4 PM_SUSACK#_R 0R0402-PAD-2-GP
[24] PM_SUSACK#

1
B BATLOW # PM_SUSW ARN#_R B
1 4 [24] PM_SUSW ARN# 2 3
2 3 AC_PRESENT R1725
0R4P2R-PAD 100KR2F-L1-GP
SRN10KJ-5-GP RN1702
DS3

2
3D3V_AUX_S5
NON DS3
1 2
R1708
2

100KR2J-1-GP
R1726
10KR2J-3-GP

1KR2J-1-GP
Q1701
1

3D3V_S5_PCH R1702
4 3 PM_RSMRST#
1 2 RSMRST#_KBC [24]
PCH_SUSCLK_KBC
1 2 PM_SUS_STAT# 3V_5V_POK# 5 2 3V_5V_POK_C 1 R1728 2
R1724 DY 10KR2J-3-GP
3V_5V_POK [45]

2
1 2 PM_SUSW ARN# 6 1 0R2J-2-GP
R1727 10KR2J-3-GP EC1701
NON DS3 SC4D7P50V2CN-1GP DY

1
2N7002KDW -GP PM_SLP_SUS#
1 2
R1729
0R0402-PAD-2-GP

A00 0618
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PM)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 17 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
www.qdzbwx.com XTAL24_IN
A00 0618
0R0402-PAD-2-GP
1 R1810 2 XTAL24_IN_R
C1801
1 2

SC15P50V2JN-2-GP

2
3D3V_S0
RN1801 R1802
1 8 CLK_PCIE_REQ# 1M1R2J-GP
2 7 CLK_PCIE_W LAN_REQ3# XTAL-24MHZ-86-GP
3 6 PEG_CLKREQ# X1801

2
4 5 CLK_PCIE_LAN_REQ4#
D
82.30004.891 D

3
HSW_ULT_DDR3L
CPU1F 6 OF 19
SRN10KJ-6-GP
C1802
XTAL24_OUT 1 2
+V1.05S_AXCK_LCPLL
C43 A25 XTAL24_IN 3KR2F-GP SC15P50V2JN-2-GP
CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT
C42 CLKOUT_PCIE_P0 XTAL24_OUT B25 1 R1803 2
CLK_PCIE_REQ# U2 RN1803
PCIECLKRQ0#/GPIO18 SRN10KJ-5-GP
RSVD#K21 K21
B41 CLKOUT_PCIE_N1 RSVD#M21 M21 2 3
A41 C26 XCLK_BIASREF 1 4
CLK_PCIE_REQ# CLKOUT_PCIE_P1 DIFFCLK_BIASREF
Y5 PCIECLKRQ1#/GPIO19
C35 MCP_TESTLOW 1 RN1808
CLOCK TESTLOW_C35 MCP_TESTLOW 2 SRN10KJ-5-GP
[58] CLK_PCIE_W LAN_N3 C41 CLKOUT_PCIE_N2 TESTLOW_C34 C34
MCP_TESTLOW 3
[58] CLK_PCIE_W LAN_P3
[58] CLK_PCIE_W LAN_REQ3#
B42
AD1
CLKOUT_PCIE_P2
PCIECLKRQ2#/GPIO20
WLAN SIGNALS TESTLOW_AK8
TESTLOW_AL8
AK8
AL8 MCP_TESTLOW 4
1
2
4
3

CLK_PCI_LPC_R R1804 1 2 0R2J-2-GP

[30] CLK_PCIE_LAN_N4
[30] CLK_PCIE_LAN_P4
B38
C37
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
LAN/ CLKOUT_LPC_0
CLKOUT_LPC_1
AN15
AP15 CLK_PCI_KBC_R R1805 1 LPC 2
CLK_PCI_LPC [65]
CLK_PCI_KBC [24]
N1 A00 0618 0R0402-PAD-2-GP
[30] CLK_PCIE_LAN_REQ4# PCIECLKRQ3#/GPIO21 Card reader CLKOUT_ITPXDP# B35 PCIE_CLK_XDP_N [96]
[73] CLK_PCIE_VGA# A39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P A35 PCIE_CLK_XDP_P [96]
[73] CLK_PCIE_VGA
[73] PEG_CLKREQ#
B39
U5
CLKOUT_PCIE_P4
PCIECLKRQ4#/GPIO22
GPU

EC1801
SC10P50V2JN-4GP

EC1802
SC10P50V2JN-4GP
B37 CLKOUT_PCIE_N5

1
A37 CLKOUT_PCIE_P5
CLK_PCIE_REQ# T2
C PCIECLKRQ5#/GPIO23 DY DY C

2
HASW ELL-6-GP
3D3V_S5_PCH

X01 0321
RN1807
RN1806
LPC_AD[3..0] HSW_ULT_DDR3L
[24,65] LPC_AD[3..0] 0R8P4R-PAD-1-GP CPU1G 7 OF 19 SML0_DATA 4 5
RN SML0_CLK 3 6
LPC_AD0 8 1 LPC_LAD0_PCH AU14 AN2 MCP_GPIO11 SML1_CLK 2 7
LPC_AD1 LPC_LAD1_PCH LAD0 SMBALERT#/GPIO11 SMB_CLK SML1_DATA
7 2 AW12 LAD1 SMBCLK AP2 1 8
LPC_AD2 6 3 LPC_LAD2_PCH AY12 LPC AH1 SMB_DATA
LPC_AD3 LPC_LAD3_PCH LAD2 SMBUS SMBDATA CARD_PW R_EN SRN2K2J-4-GP
5 4 AW11 LAD3 SML0ALERT#/GPIO60 AL2
LPC_LFRAME#_PCH AV12 AN1 SML0_CLK RN1809
LFRAME# SML0CLK SML0_CLK [53]
AK1 SML0_DATA SRN10KJ-6-GP
SML0DATA SML0_DATA [53]
AU4 MCP_GPIO73 MCP_GPIO73 1 8
0R0402-PAD-2-GP SML1ALERT#/PCHHOT#/GPIO73
[24,65] LPC_FRAME# 1 R1801 2 SML1CLK/GPIO75 AU3 SML1_CLK
SML1_CLK [24,26,76]
MCP_GPIO11 2 7
AH3 SML1_DATA CARD_PW R_EN 3 6
SML1DATA/GPIO74 SML1_DATA [24,26,76]
[24,25] SPI_CLK_R 33R2J-2-GP 1 2 R1806 PCH_SPI_CLK AA3 4 5
0R0402-PAD-2-GP 1 R1807 PCH_SPI_CS0# SPI_CLK TP_CL_CLK 1 TP1803
[24,25] SPI_CS0#_R 2 Y7 SPI_CS0# CL_CLK AF2
X01 0321 Y4 AD2 TP_CL_DATA1 TP1804
SPI_CS1# CL_DATA RN1804
AC2 SPI C-LINK AF4 TP_CL_RST# 1 TP1805
0R0402-PAD-2-GP R1808 PCH_SPI_SI SPI_CS2# CL_RST# SMB_DATA
[24,25] SPI_SI_R 1 2 AA2 SPI_MOSI 2 3
[24,25] SPI_SO_R 0R0402-PAD-2-GP 1 R1809 2 PCH_SPI_SO AA4 SMB_CLK 1 4 3D3V_S5_PCH
0R0402-PAD-2-GP R1811 PCH_SPI_DQ2 SPI_MISO
[25] SPI_W P# 1 2 Y6 SPI_IO2
0R0402-PAD-2-GP 1 R1812 2 PCH_SPI_DQ3 AF1
[25] SPI_HOLD# SPI_IO3 SRN2K2J-1-GP
B B

3D3V_S5 3D3V_S0

HASW ELL-6-GP
RN1805
1
2

2 3 3D3V_S0
RN1802 1 4
SRN1KJ-11-GP-U
SRN2K2J-1-GP
Q1801
4
3

PCH_SPI_DQ3 SMB_DATA 6 1 PCH_SMBDATA [12,13,58,62,67]

PCH_SPI_DQ2
5 2
84.2N702.A3F
4 3 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
2N7002KDW -GP 4th = 84.2N702.F3F

PCH_SMBCLK [12,13,58,62,67]

SMB_CLK

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CLK/SMB/LPC/SPI)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 18 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
RTC_X1

1 2 RTC_X2
R1915 10MR2J-L-GP
X1901

1 4
RTC_AUX_S5 X02 0502 change C1903 C1904 from 18pF to 15 pF
D D

1
2 3
C1903 C1904

SC15P50V2JN-2-GP

SC15P50V2JN-2-GP
2

2
X-32D768KHZ-65-GP

1
RTC_AUX_S5 R1903 R1901 82.30001.A41
330KR2J-L1-GP 1M1R2J-GP 2nd = 82.30001.841

2
1
2
RN1901
CPU1E HSW_ULT_DDR3L 5 OF 19
SRN20KJ-1-GP

RTC_X1 AW5

4
3
RTC_X2 RTCX1
AY5 RTCX2
Q1901 SM_INTRUDER# AU6 J5 SATA3_PRX_DTX_N0 [56]
PCH_INTVRMEN AV7 INTRUDER# SATA_RN0/PERN6_L3
[24] RTCRST_ON G INTVRMEN SATA_RP0/PERP6_L3 H5 SATA3_PRX_DTX_P0 [56]
SRTC_RST# AV6 RTC B15 SATA3_PTX_DRX_N0 [56]
SRTCRST# SATA_TN0/PETN6_L3 HDD1
1

D RTC_RST# AU7 A15 SATA3_PTX_DRX_P0 [56]

R1902 RTCRST# SATA_TP0/PETP6_L3

2
10KR2J-3-GP S SATA_RN1/PERN6_L2 J8 SATA3_PRX_DTX_N1 [63]

1
G1901 H8 SATA3_PRX_DTX_P1 [63]
SATA_RP1/PERP6_L2 mSATA

1
2N7002K-2-GP C1901 C1902 A17 SATA3_PTX_DRX_N1 [63]
2

SATA_TN1/PETN6_L2

SC1U6D3V2KX-GP

GAP-OPEN
84.2N702.J31 SC1U6D3V2KX-GP B17 SATA3_PTX_DRX_P1 [63]

2
SATA_TP1/PETP6_L2
2ND = 84.2N702.031

2
C 3rd = 84.07002.I31 HDA_BITCLK AW8 J6 C
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
HDA_RST# AU8 B14
HDA_SDIN0 HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1
[27] HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 HDA_SDI1/I2S1_RXD
HDA_SDOUT AU11 F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
1TP_HDA_DOCK_EN# AW10 HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0 E5
TP1902 AV10 C17
HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17
[27] HDA_CODEC_BITCLK R1907 1 2 33R2J-2-GP HDA_BITCLK
+V1.05S_ASATA3PLL
V1 EC_SMI# EC_SMI# [24]
SATA0GP/GPIO34 MCP_GPIO35
SATA1GP/GPIO35 U1
V6 SATA_ODD_PRSNT#
SATA2GP/GPIO36
SATA3GP/GPIO37 AC1 MSATA_DET# [63]
TP1901 1PCH_JTAG_TRST# AU62 0R0402-PAD-2-GP
PCH_JTAG_TCK PCH_TRST# SATA_IREF
AE62 PCH_TCK SATA_IREF A12 1 R1904 2
Flash Descriptor Security Overide/ PCH_JTAG_TDI AD61 L11
R1905 PCH_TDI RSVD#L11
Intel ME Debug Mode [27] HDA_CODEC_SYNC 1 2 0R0402-PAD-2-GP HDA_SYNC PCH_JTAG_TDO AE61 PCH_TDO RSVD#K10 K10
[27,29] HDA_CODEC_RST# R1908 1 2 0R0402-PAD-2-GP HDA_RST# PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP 1 2
R1910 PCH_TMS SATA_RCOMP
Low = Default * [27] HDA_CODEC_SDOUT 1 2 0R0402-PAD-2-GP HDA_SDOUT AL11 RSVD#AL11 SATALED# U3 SATA_LED# SATA_LED# [61]
HDA_SDOUT High = Enable AC4 R1906
XDP_TCK_JTAGX RSVD#AC4 3KR2F-GP
[24] ME_UNLOCK 1 2 AE63 JTAGX
The internal pull-down is disabled after R1909 1KR2J-1-GP AV2 RSVD#AV2
PLTRST# deasserts

Layout Note:
B B
R1913 HASW ELL-6-GP 4mil trace at break-out and 3
1 2 PCH_INTVRMEN 1D05S_VCCST 12-15mil trace with <0.2 ohms
DY and length total <= 500mils.
330KR2J-L1-GP
2
DY 1 PCH_JTAG_TDI
R1916 51R2J-2-GP
2 1 PCH_JTAG_TDO
Integrated SUS 1V VRM Enable R1917 DY 51R2J-2-GP 3D3V_S0
2 1 PCH_JTAG_TMS
Low = External VRs R1918 DY 51R2J-2-GP RN1902
INTVRMEN 2 1 XDP_TCK_JTAGX EC_SMI# 1 8
High = Internal VRs* R1919 DY 1KR2J-1-GP MCP_GPIO35 2 7
MSATA_DET# 3 6
SATA_ODD_PRSNT# 4 5

SRN10KJ-6-GP

1 2 PCH_JTAG_TCK
R1920 DY 51R2J-2-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RTC/SATA/HDA/JTAG)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 19 of 101
5 4 3 2 1
 5 4 3 2 1

1D05S_VCCST
SSID = CPU

1
HSW_ULT_DDR3L
CPU1J 10 OF 19 R2018
1KR2J-1-GP

2
[67] FFS_INT2 FFS_INT2 P1 D60 PCH_THERMTRIP
3D3V_S5 MCP_GPIO8 BMBUSY#/GPIO76 THRMTRIP# H_RCIN#
AU2 GPIO8 RCIN#/GPIO82 V4 H_RCIN# [24]
MCP_GPIO12 AM7 T4 INT_SERIRQ INT_SERIRQ [24]
MCP_GPIO15 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ PCH_OPIRCOMP
RN2006 AD6 AW15 1 2
MCP_GPIO12 GPIO15 MISC PCH_OPI_RCOMP
D 1 4 TP2004 1MCP_GPIO16 Y1 GPIO16 RSVD#AF20 AF20 D
MCP_GPIO27 SATA_ODD_DA# R2003
2 3
[25] RTC_DET# RTC_DET#
T3
AD5
GPIO17 RSVD#AB21 AB21
49D9R2F-GP Layout Note:
GPIO24
SRN10KJ-5-GP MCP_GPIO27 AN5 GPIO27
1.Referenced "continuous" VSS plane only.
MCP_GPIO28 AD7 2.Avoid routing next to clock pins or noisy
MCP_GPIO26 GPIO28
AN3 GPIO26
R6 MCP_GPIO83 1
signals.
GSPI0_CS#/GPIO83 TP2010
MCP_GPIO56 AG6 L6 MCP_GPIO84 1 TP2011
3. Trace width: 12~15mil
MCP_GPIO57 GPIO56 GSPI0_CLK/GPIO84 SATA_ODD_PW RGT
AP1 GPIO57 GSPI0_MISO/GPIO85 N6 1 TP2021 4. Isolation Spacing: 12mil
MCP_GPIO58 AL4 L8 LPSS_GSPI0_MOSI_BBS0_R 5. Max length: 500mil
W LAN_PLT_RST# GPIO58 GSPI0_MOSI/GPIO86 MCP_GPIO87
AT5 GPIO59 GSPI1_CS#/GPIO87 R7 1 TP2012
DRAM_SEL0 GPIO MCP_GPIO88
GPIO[47:44]=[1,1,1,1] for SODIMM configuration DRAM_SEL3
AK4 GPIO44 GSPI1_CLK/GPIO88 L5
TOUCH_PW R_EN
1 TP2013
AB6 GPIO47 GSPI1_MISO/GPIO89 N7 1 TP2014
BOARD_ID1 U4 K2 KB_DET# [62]
BOARD_ID2 GPIO48 GSPI_MOSI/GPIO90
Y3 GPIO49 UART0_RXD/GPIO91 J1 KB_LED_BL_DET [62]
TP2002 1 MCP_GPIO50 P3 K3 DBC_EN [52]
GPIO50 UART0_TXD/GPIO92 MCP_GPIO93
[21] HSIOPC Y2 HSIOPC/GPIO71 UART0_RTS#/GPIO93 J2 1 TP2015
MCP_GPIO13 AT3 SERIAL IO G1 MCP_GPIO94 1
GPIO13 UART0_CTS#/GPIO94 TP2016
MCP_GPIO14 AH4 K4 MCP_GPIO0 1 TP2017
GPIO14 UART1_RXD/GPIO0
TP2020 1CAMERA_PW R_EN AM4 GPIO25 UART1_TXD/GPIO1 G2 MCP_GPIO1 1 TP2018
3D3V_S5_PCH DRAM_SEL1 AG5 J3 MCP_GPIO2 1
GPIO45 UART1_RST#/GPIO2 TP2019
DRAM_SEL2 AG3 J4 BLUETOOTH_EN [58]
GPIO46 UART1_CTS#/GPIO3 I2C0_SDA
I2C0_SDA/GPIO4 F2
1

[24] EC_SW I# EC_SW I# AM3 F3 I2C0_SCL

R2013 EC_SCI# GPIO9 I2C0_SCL/GPIO5 I2C1_SDA
A00 0618 [24] EC_SCI# AM2 GPIO10 I2C1_SDA/GPIO6 G4
10KR2J-3-GP [56] HDD_DEVSLP P2 F1 I2C1_SCL
MCP_GPIO70 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 COLOR_ENGINE 3D3V_S0
TP2009 1 C4 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 E3 COLOR_ENGINE [52]
[63] MSATA_DEVSLP L2 F4 MCP_GPIO65 1 TP2005 RN2014
2

MCP_GPIO_PH MCP_GPIO39 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 LPSS_SDIO_D0_CMNHDR SRN10KJ-6-GP

TP2003 1 N5 DEVSLP2/GPIO39 SDIO_D0/GPIO66 D3
C 0R0402-PAD-2-GP 1 R2001 2 MCP_GPIO58 [27] HDA_SPKR V2 E4 MCP_GPIO67 1 TP2006 INT_SERIRQ 1 8 C
0R0402-PAD-2-GP 1 R2002 DRAM_SEL0 SPKR/GPIO81 SDIO_D1/GPIO67 MCP_GPIO68 KB_DET#
2 SDIO_D2/GPIO68 C3 1 TP2007 2 7
0R0402-PAD-2-GP 1 R2004 2 DRAM_SEL2 E2 MCP_GPIO69 1 TP2008 H_RCIN# 3 6
0R0402-PAD-2-GP 1 R2007 MCP_GPIO26 SDIO_D3/GPIO69 DBC_EN
2 4 5
0R0402-PAD-2-GP 1 R2015 2 MCP_GPIO56
0R0402-PAD-2-GP 1 R2016 2 DRAM_SEL1 HASW ELL-6-GP
0R0402-PAD-2-GP 1 R2017 2 MCP_GPIO14 3D3V_S0
0R0402-PAD-2-GP 1 R2019 2 MCP_GPIO28
0R0402-PAD-2-GP 1 R2020 2 MCP_GPIO8 RN2007
0R0402-PAD-2-GP 1 R2021 MCP_GPIO13 3D3V_S0 SRN10KJ-6-GP
0R0402-PAD-2-GP 1 R2022
2
2 DRAM_SEL3 RN2005 PCH strap pin: I2C0_SDA 8 1
0R0402-PAD-2-GP 1 R2023 2 MCP_GPIO57 SRN10KJ-6-GP I2C1_SCL 7 2
1 8 FFS_INT2 NO REBOOT I2C1_SDA 6 3
2 7 BOARD_ID1 3D3V_S0 I2C0_SCL 5 4
3 6 SATA_ODD_DA# 1KR2J-1-GP
3D3V_S5_PCH BLUETOOTH_EN Low = Disable (Default) R2006
RN2012
4 5
HDA_SPKR
* 1 2 HDA_SPKR
SRN10KJ-6-GP
High = Enable DY
1 8 EC_SCI#
2 7 EC_SW I# The internal pull-down is disabled after
3 6 RTC_DET# 3D3V_S0
W LAN_PLT_RST#
PLTRST# deasserts
4 5
10KR2J-3-GP
R2009 1 2 HDD_DEVSLP
DY
R2010 1 2 MSATA_DEVSLP
3D3V_S0 10KR2J-3-GP DY 3D3V_S0
R2024 Top-Block Swap Override mode

1
B HSIOPC B
1 2
High = Enable "Top-Block swap" R2011
SDIO_D0 mode (Default)
DY 1KR2J-1-GP
100KR2J-1-GP
/ GPIO66 Low = Disable "Top-Block swap" mode
*

2
LPSS_SDIO_D0_CMNHDR
The internal pull-down is disabled after
PLTRST# deasserts
BIOS strap pin:
3D3V_S0
BIOS UMA/DIS Strap pin
1

3D3V_S5_PCH
BOARD_ID1 BOARD_ID2 R2005 TLS Confidentiality
OPS 10KR2J-3-GP

1
PX(AMD) 0 0 *Low = Disable Intel ME Crypto TLS R2014
DY
2

GPIO15 High = Enable Intel ME Crypto TLS 1KR2J-1-GP

DIS 0 1 BOARD_ID2

2
The internal pull-down is disabled after MCP_GPIO15
1

RSMRST# deasserts.
UMA 1 0 R2008
10KR2J-3-GP
UMA
Optimus(NV) 1 1
2

3D3V_S0
A <Core Design> A
Boot BIOS Strap Bit BBS
1

Boot BIOS * Low = SPI DY R2012 Wistron Corporation

1KR2J-1-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Destination High = LPC Taipei Hsien 221, Taiwan, R.O.C.
2

The internal pull-down is disabled after LPSS_GSPI0_MOSI_BBS0_R Title

PLTRST# deasserts CPU (GPIO)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 20 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

3D3V_S5_PCH

A00 0618
D D
0R0402-PAD-2-GP
+3.3A_DSW_PRTCSUS 1 R2102 2

1
+V1.05DX_MODPHY_PCH C2109
CPU1M HSW_ULT_DDR3L 13 OF 19 SC1U6D3V2KX-GP

2
+V1.05DX_MODPHY_PCH K9
1D05V_S0 VCCHSIO
L10
R2104 VCCHSIO RTC_AUX_S5
M9
+V1.05S_AIDLE VCCHSIO HSIO RTC
1 2 N8
VCC1_05 VCCSUS3_3
AH11
0R0402-PAD-2-GP P9 AG10
VCC1_05 VCCRTC +VCCRTCEXT C2110 1
+V1.05S_AUSB3PLL B18 VCCUSB3PLL DCPRTC AE7 2

1
C2105
SC1U6D3V2KX-GP
+V1.05S_ASATA3PLL B11 VCCSATA3PLL SCD1U10V2KX-5GP 3D3V_S5
DY

2
TP2102 1 TP_VCCAPLLOPI_VAL Y20 SPI Y8
RSVD#Y20 VCCSPI
+V1.05S_APLLOPI AA21 VCCAPLL
OPI

1
W21 C2147
VCCAPLL SCD1U10V2KX-5GP
VCCASW AG14
AG13 1D05V_S0

2
VCCASW
3D3V_S5_PCH +V3.3A_1.5A_HDA TP2107 1 +V1.05A_VCCUSB3SUS J13 USB3
DCPSUS3
A00 0618 VCC1_05 J11 1D05V_S0
VCC1_05 H11
1 2 +V3.3A_1.5A_HDA AH14 HDA H15
R2105 VCCHDA VCC1_05 R2110 C2114
VCC1_05 AE8

1
0R0402-PAD-2-GP

C2116
SC1U6D3V2KX-GP
AF22 5D1R2F-GP SC1U6D3V2KX-GP
TP2108 +V1.05A_USB2SUS VRM VCC1_05
1 AH13 DCPSUS2 DCPSUSBYP#AG19 AG19 +PCH_VCCDSW 1 2PCH_VCCDSW_R 1 2
CORE AG20

2
DCPSUSBYP#AG20
AE9 +1.05M_ASW
VCCASW
VCCASW AF9 X02 remove C2103
3D3V_S0 AC9 AG8
3D3V_S5 +V3.3A_DSW_P +V3.3A_PSUS VCCSUS3_3 VCCASW
C AA9 GPIO/LPC AD10 +V1.05A_SUS_PCH1 TP2106 C
R2101 R2106 VCCSUS3_3 DCPSUS1#AD10
+V3.3A_DSW_P AH10 VCCDSW3_3 DCPSUS1#AD8 AD8
1 2 1 2 +V3.3S_PCORE V8
0R0402-PAD-2-GP 0R0402-PAD-2-GP VCC3_3 3D3V_S0
W9 VCC3_3

1
C2136
SCD1U10V2KX-5GP

VCCTS1_5 J15 1D5V_S0

1

C2123 THERMAL SENSOR K14

SC10U6D3V3MX-GP VCC3_3
K16
DY

2
VCC3_3

C2128
SC1U6D3V2KX-GP
2

1
+V1.05S_AXCK_DCB J18
VCCCLK SERIAL IO +V3.3S_1.8S_LPSS_SDIO 3D3V_S0
K19 U8 +V3.3S_1.8S_LPSS_SDIO

2
1D05V_S0 +V1.05S_SSCF100 VCCCLK VCCSDIO R2103
+V1.05S_AXCK_LCPLL A20 T9
R2117 VCCACLKPLL VCCSDIO
+V1.05S_SSCF100 J17 1 2
VCCCLK 0R0402-PAD-2-GP
1 2 +V1.05S_SSCFF R21
0R0402-PAD-2-GP VCCCLK LPT LP POWER
T21
VCCCLK

1
C2137
SC1U6D3V2KX-GP

1 TP_V1.05S_SSCF100 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS 1 TP2109

RSVD#K18 DCPSUS4
1

TP2103 1 TP_V1.05S_AXCK_DCB M20 C2104

TP2104 RSVD#M20 SC1U6D3V2KX-GP
1 TP_V1.05S_SSCFF V21

2
TP2101 RSVD#V21
+V3.3A_PSUS AE20 AC20 TP_V1.05S_APLLOPI 1 TP2105
2

VCCSUS3_3 RSVD#AC20
AE21 AG16 1D05V_S0
VCCSUS3_3 USB2 VCC1_05
AG17
VCC1_05

1
C2135
SC1U6D3V2KX-GP
2
HASWELL-6-GP

1D05V_S0 +V1.05S_SSCFF
R2118
1 2 1D05V_S0 1D05V_HSIO
0R0402-PAD-2-GP
C2138
SC1U6D3V2KX-GP

R2122
1

1 0R5J-5-GP
2
B Non-HSIO B
2

R2123
[20] HSIOPC 1 2 HSIOPC_R
HSIO
0R2J-2-GP 1D05V_HSIO

9
U2101
0R5J-5-GP

ON
5V_S5 1 8 R2114
VDD GND HSIO_OUT
1D05V_S0 2 7 1 2
D#2 S#7
3
D#3 HSIOS#6 6
4
D#4 S#5
5 HSIO

C2101
SC10U6D3V3MX-GP
1
SLG59M1470VTR-GP
1

74.59147.093 HSIO
HSIO C2102

2
SC4D7U6D3V3KX-GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (POWER2)
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 21 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

HSW_ULT_DDR3L
CPU1Q 17 OF 19

DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW 3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 TP_DC_TEST_A4 TP2202
AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 1
TP2201 1TP_DC_TEST_AY60 AY60
DC_TEST_AY61_AW 61 DAISY_CHAIN_NCTF_AY60 TP_DC_TEST_A60 TP2203
AY61 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A60 1
DC_TEST_AY62_AW 62 AY62 A61 DC_TEST_A61_B61
TP2204 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61
1TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 A62 TP_DC_TEST_A62 1 TP2205
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 1 TP2206
DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 TP_DC_TEST_AW 1 TP2207
B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1 1
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW 2
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW 3
B63 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3
DC_TEST_C1_C2 C1 AW61 DC_TEST_AY61_AW 61
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW 62
C2 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62
AW63 TP_DC_TEST_AW 63 1 TP2208
DAISY_CHAIN_NCTF_AW63
HASW ELL-6-GP

HSW_ULT_DDR3L
C CPU1R 18 OF 19 C

RSVD#N23 N23
RSVD#R23 R23
RSVD#T23 T23
AT2 RSVD#AT2
RSVD#U10 U10
AU44 RSVD#AU44
AV44 RSVD#AV44
D15 RSVD#D15
RSVD#AL1 AL1
RSVD#AM11 AM11
RSVD#AP7 AP7
F22 RSVD#F22
RSVD#AU10 AU10
H22 RSVD#H22
RSVD#AU15 AU15
J21 RSVD#J21
RSVD#AW14 AW14
RSVD#AY14 AY14

HASW ELL-6-GP

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RSVD
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 22 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

HSW_ULT_DDR3L HSW_ULT_DDR3L
CPU1N 14 OF 19 CPU1O 15 OF 19

D A11 VSS VSS AJ35 AP22 VSS VSS AV59 D

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A24 VSS VSS AJ43 AP29 VSS VSS AW24
A28 VSS VSS AJ45 AP3 VSS VSS AW33
A32 VSS VSS AJ47 AP31 VSS VSS AW35
A36 VSS VSS AJ50 AP38 VSS VSS AW37
A40 VSS VSS AJ52 AP39 VSS VSS AW4
A44 VSS VSS AJ54 AP48 VSS VSS AW40
A48 VSS VSS AJ56 AP52 VSS VSS AW42
A52 VSS VSS AJ58 AP54 VSS VSS AW44
A56 VSS VSS AJ60 AP57 VSS VSS AW47
AA1 VSS VSS AJ63 AR11 VSS VSS AW50
AA58 VSS VSS AK23 AR15 VSS VSS AW51
AB10 VSS VSS AK3 AR17 VSS VSS AW59
AB20 VSS VSS AK52 AR23 VSS VSS AW60
AB22 VSS VSS AL10 AR31 VSS VSS AY11
AB7 VSS VSS AL13 AR33 VSS VSS AY16
AC61 VSS VSS AL17 AR39 VSS VSS AY18
AD21 VSS VSS AL20 AR43 VSS VSS AY22
AD3 VSS VSS AL22 AR49 VSS VSS AY24
AD63 VSS VSS AL23 AR5 VSS VSS AY26
AE10 VSS VSS AL26 AR52 VSS VSS AY30
AE5 VSS VSS AL29 AT13 VSS VSS AY33
AE58 VSS VSS AL31 AT35 VSS VSS AY4
AF11 VSS VSS AL33 AT37 VSS VSS AY51
AF12 VSS VSS AL36 AT40 VSS VSS AY53
AF14 VSS VSS AL39 AT42 VSS VSS AY57
AF15 VSS VSS AL40 AT43 VSS VSS AY59
C AF17 AL45 AT46 AY6 C
VSS VSS VSS VSS
AF18 VSS VSS AL46 AT49 VSS VSS B20
AG1 VSS VSS AL51 AT61 VSS VSS B24
AG11 VSS VSS AL52 AT62 VSS VSS B26
AG21 VSS VSS AL54 AT63 VSS VSS B28
AG23 VSS VSS AL57 AU1 VSS VSS B32
AG60 VSS VSS AL60 AU16 VSS VSS B36
AG61 VSS VSS AL61 AU18 VSS VSS B4
AG62 VSS VSS AM1 AU20 VSS VSS B40
AG63 VSS VSS AM17 AU22 VSS VSS B44
AH17 VSS VSS AM23 AU24 VSS VSS B48
AH19 VSS VSS AM31 AU26 VSS VSS B52
AH20 VSS VSS AM52 AU28 VSS VSS B56
AH22 VSS VSS AN17 AU30 VSS VSS B60
AH24 VSS VSS AN23 AU33 VSS VSS C11
AH28 VSS VSS AN31 AU51 VSS VSS C14
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
B B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31

HASW ELL-6-GP

HASW ELL-6-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 23 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = KBC VBAT 3D3V_AUX_KBC VBAT

VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
R2402
X00 100.0K 10.0K 3.0V (DOH70)UMA 100.0K 10.0K(64.10025.6DL) 3.0V

1
R2405
49K9R2F-L-GP
VBAT 2 1 A00 0618 (DOH50)UMA/eDP 100.0K 13.7K(64.13725.6DL) 2.902V

1
X01 100.0K 20.0K 2.75V TBD 100.0K 17.8K(64.17825.6DL) 2.801V

2
R2404 (DOH70)DIS 100.0K 22.1K(64.22125.6DL) 2.702V
0R0603-PAD-2-GP-U R2403 64K9R2F-1-GP X02 100.0K 33.0K 2.48V TBD 100.0K 27.0K(64.27025.6DL) 2.598V
2D2R3-1-U-GP TBD 100.0K 32.4K(64.32425.6DL) 2.492V

2
X03 100.0K 47.0K 2.24V TBD 100.0K 37.4K(64.37425.6DL) 2.402V

2
3D3V_AUX_KBC_VCC TBD 100.0K 43.2K(64.43225.6DL) 2.304V

1
PCB_VER_AD A00 100.0K 64.9K 2.0V MODEL_ID_DET (DOH50)UMA/LVDS 100.0K 49.9K(64.49925.6DL) 2.201V
(DOH50)DIS/eDP 100.0K 57.6K(64.57625.6DL) 2.093V

1
Reserved 100.0K 76.8 1.87V TBD 100.0K 64.9K(64.64925.6DL) 2.001V

2
R2406 R2407 TBD 100.0K 73.2K(64.73225.6DL) 1.905V

2
1D05V_S0

100KR2F-L1-GP
100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V C2403 TBD 100.0K 82.5K(64.82525.6DL) 1.808V
DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
C2405
C2404

C2406

C2407

C2408

C2409

C2410

C2411
C2402 SCD1U10V2KX-5GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V
D
DY D

1
1

1
1 R2401 2 EC_VTT SCD1U10V2KX-5GP Reserved 100.0K 143.0K 1.358V TBD 100.0K 107K(64.10735.6DL) 1.594V

2
TBD 100.0K 120K(64.12035.6DL) 1.499V
DY DY
1
0R0402-PAD-2-GP Reserved 100.0K 174.0K 1.204V TBD 100.0K 137K(64.13735.6DL) 1.392V
DY

2
C2401
TBD 100.0K 154K(64.15435.6DL) 1.299V

SCD1U10V2KX-5GP
EC_AGND Reserved 100.0K 215.0K 1.048V EC_AGND (DOH50)DIS/LVDS 100.0K 200K(64.20035.6DL) 1.099V
2

TBD 100.0K 232K(64.23236.6DL) 0.994V

Layout Note:
Need very close to EC
X01 0321
EC_AGND

ECSCI#_KBC 0R0402-PAD-2-GP 1 R2408 2 EC_SCI# [20]

KBC24
ECSMI#_KBC 0R0402-PAD-2-GP 1 R2409 2
KROW[0..7] [62] EC_SMI# [19]
19 54 KROW0
VCC KBSIN0/GPIOA0/N2TCK KROW1 ECSWI#_KBC 0R0402-PAD-2-GP
46 55 1 R2410 2 EC_SWI# [20]
VCC KBSIN1/GPIOA1/N2TMS KROW2
76 56
3D3V_S0 VCC KBSIN2/GPIOA2 KROW3
88 57
VCC KBSIN3/GPIOA3 KROW4
115 58
VCC KBSIN4/GPIOA4 KROW5
59
KBSIN5/GPIOA5 KROW6
102 60
AVCC KBSIN6/GPIOA6 KROW7
61
KBSIN7/GPIOA7
4 KCOL[0..16] [62]
VDD
C2413
SC2D2U6D3V2MX-GP

3D3V_AUX_KBC
1

EC_VTT 12 53 KCOL0
[44] AD_IA VTT KBSOUT0/GPOB0/SOUT_CR/JENK#
C2412 52 KCOL1
SCD1U10V2KX-5GP DY KBSOUT1/GPIOB1/TCK
51 KCOL2
2

C2414 KBSOUT2/GPIOB2/TMS KCOL3 AC_IN_KBC#

1 2 SCD1U10V2KX-5GP 97 50 R2426 1 2100KR2J-1-GP
EC_AGND DY PCB_VER_AD 98
GPIO90/AD0 KBSOUT3/GPIOB3/TDI
49 KCOL4 USB_DET# R2411 1 2100KR2J-1-GP
GPIO91/AD1 KBSOUT4/GPOB4/JEN0# KCOL5
[42] PSID_EC 99 48
AMB_TEMP GPIO92/AD2 KBSOUT5/GPIOB5/TDO KCOL6
100 47
GPIO93/AD3 KBSOUT6/GPIOB6/RDY# KCOL7 3D3V_AUX_KBC
[17,38] PM_SLP_SUS# 108 43
GPIO5/AD4 KBSOUT7/GPIOB7 KCOL8
[44] BOOST_MON 96 42 RN2401
GPIO4/AD5 KBSOUT8/GPIOC0 KCOL9
95 41
[35] USBCHARGER_CB0 MODEL_ID_DET GPIO3/EXT_PURST#/AD6 KBSOUT9/GPOC1/SDP_VIS# KCOL10 BAT_SCL
94 40 3 2
GPIO7/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2 KCOL11 BAT_SDA
39 4 1
KBSOUT11/P80_DAT/GPIOC3 KCOL12
38
KBSOUT12/GPO64/TEST# KCOL13 SRN4K7J-8-GP
[26] FAN1_DAC_1 101 37
GPIO94/DA0 KBSOUT13/GPI/O63/TRIST# KCOL14
C
[44] AD_IA_HW 105 36 C
GPIO95/DA1 KBSOUT14/GPI/O62/XORTR# KCOL15
[76] EC_FB_CLAMP_TGL_REQ# 106 35
GPIO96/DA2 KBSOUT15/GPIO61/XOR_OUT KCOL16 ECRST# R2418 1
[7,46] IMVP_PWRGD 107 34 2 10KR2J-3-GP
GPIO97/DA3 GPIO60/KBSOUT16 USB_DET#
33
GPIO57/KBSOUT17

[43,44,53] BAT_SCL 70 LPC_AD[3..0] [18,65]

GPIO17/SCL1/N2TCK LPC_AD0
[43,44,53] BAT_SDA 69 126
GPIO22/SDA1/N2TMS LAD0/GPIOF1 LPC_AD1
[18,26,76] SML1_CLK 67 127
GPIO73/SCL2/N2TCK LAD1/GPIOF2 LPC_AD2
[18,26,76] SML1_DATA 68 128
GPIO74/SDA2/N2TMS LAD2/GPIOF3 LPC_AD3
[30] PM_LAN_ENABLE 119
GPIO23/SCL3/N2TCK LAD3/GPIOF4
1 A00 0618
[19] RTCRST_ON 120 2 CLK_PCI_KBC [18]
PROCHOT_EC GPIO31/SDA3/N2TMS LCLK/GPIOF5 0R0402-PAD-2-GP 3D3V_AUX_KBC
24 3 LPC_FRAME# [18,65]
LCD_TST_EN GPIO47/SCL4/N2TCK LFRAME#/GPIOF6 PLT_RST#_EC
[52] LCD_TST_EN 28 7 1 R2416 2 PLT_RST# [17,30,58,65,73]
GPIO53/SDA4/N2TMS LRESET#/GPIOF7 AC_IN# R2413 1
26 2 100KR2J-1-GP
[52] LCD_TST 1 2
[35] USBCHG_EN
ECSWI#_KBC 123
GPIO51/TA3/N2TCK BAT_IN# R2414 1 DY 2 100KR2J-1-GP
GPIO67/N2TMS

1
R2417 0R0402-PAD-2-GP EC_SPI_CS#_C SC220P50V2KX-3GP OVER_CURRENT_P8#
90 1 R2419 2 0R0402-PAD-2-GP R2424 1 2 100KR2J-1-GP
F_CS0#
92 EC_SPI_CLK_C 2 R2412 1 33R2J-2-GP
SPI_CS0#_R [18,25] DY C2415 DY
F_SCK SPI_CLK_R [18,25]
[62] TPCLK 72 109 CAP_LED# [62]

2
GPIO37/PSCLK1 GPIO30/F_WP#
[62] TPDATA 71 80 BAT_IN# [42,43,44]
GPIO35/PSDAT1 GPIO41/F_WP# EC_SPI_DI_C 3D3V_S0
[36] ALL_SYS_PWRGD 10 87 1 R2420 2 0R0402-PAD-2-GP SPI_SI_R [18,25]
GPIO26/PSCLK2 F_SDIO/F_SDIO0 EC_SPI_DO_C
[42] PWR_CHG_AD_OFF 11 86 1 R2422 2 0R0402-PAD-2-GP SPI_SO_R [18,25]
GPIO27/PSDAT2 F_SDI/F_SDIO1 FAN_TACH1 R2415 1
[44] AD_IA_HW2 25 91 PM_SUSACK# [17] 2 10KR2J-3-GP
GPIO50/PSCLK3/TDO GPIO81/F_WP#/F_SDIO2
[52] BLON_OUT 27 77 PCH_SUSCLK_KBC [17]
GPIO52/PSDAT3/RDY# GPIO0/EXTCLK/F_SDIO3
3D3V_AUX_S5
PSL_IN1#
[26] FAN_TACH1
[17,96] PM_PWRBTN#
31
117
GPIO56/TA1 PSL_IN1#/GPI70
73
93 PSL_IN2# Layout Note:
GPIO20/TA2/IOX_DIN_DIOPSL_IN2#/GPI6/EXT_PURST#

2
63 74 PSL_OUT# Need very close to EC
[75,76,83] EC_FB_CLAMP GPIO14/TB1 PSL_OUT#/GPIO71
[17,36,48,49,51] PM_SLP_S3# 64 R2425
GPIO1/TB2
330KR2J-L1-GP
29 ECSCI#_KBC 3D3V_S5
ECSCI#/GPIO54 ECRST# 0R0402-PAD-2-GP
[61] PWRLED# 32 85

1
GPIO15/A_PWM EXT_RST# PSL_IN2#
[27] KBC_BEEP 118 122 H_RCIN# [20] [61] KBC_PWRBTN# 1 R2427 2
GPIO21/B_PWM KBRST#/GPIO86 LID_CLOSE# R2421 1
[52] EC_BRIGHTNESS 62 2100KR2J-1-GP
GPIO13/C_PWM
[42] AC_IN_KBC# 65 75 3D3V_AUX_S5
GPIO32/D_PWM VSBY EC_VBKUP
[62] KB_BL_CTRL 22 114 1 R2428 2 0R0402-PAD-2-GP
RTC_AUX_S5 C2416 SC1U6D3V2KX-GP
GPIO45/E_PWM VBKUP KBC_VCORF 0R0402-PAD-2-GP
[30] LAN_WAKE# 16 44 1 2
GPIO40/F_PWM/1_WIRE VCORF PECI PSL_IN1#
Don't PD [17] KBC_DPWROK 81
GPIO66/G_PWM PECI
13 1 2 H_PECI [4] [44] AC_IN# 1 R2430 2
[61] CHG_AMBER_LED# 66 125 INT_SERIRQ [20] R2429

1
GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0 ECSMI#_KBC C2422 43R2J-GP
6
GPIO24
ALL_SYS_PWRGD assert, delay 10ms; [17,26,36] PCH_PWROK 104
GPIO80/VD_IN1 GPIO36/TB3
15 OVER_CURRENT_P8# [76] DY SC100P50V2JN-3GP
B B
PCH_PWROK assert.

2
[35] USB_PWR_EN# 110 21 PM_SLP_S4# [17,49] D2401
GPIO82/IOX_LDSH/VD_OUT1 GPIO44/TDI USB_DET#
[17,76] AC_PRESENT 112 20 RSMRST#_KBC [17] 1
GPIO84/IOX_SCLK/VD_OUT2 GPIO43/TMS
ALL_SYS_PWRGD assert, delay 100ms; GPIO42/TCK
17 LID_CLOSE# [61]
SYS_PWROK assert. 23 ME_UNLOCK [19] [34] USBDET_CON# 3
GPIO46/CIRRXM/TRST#
84
[17,96] SYS_PWROK
[58] AOAC_WLAN_EN 83
GPIO77/SPI_MISO
113 WIFI_WAKE# [58] D2402
Layout Note: 2 KBC_ON#_GATE_L
GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR
LVDS backlight Control from PS8625 [58] WIFI_RF_EN 82
GPIO75/SPI_SCK GPIO34/CIRRXL
14 S5_ENABLE [36] 1 2 TOUCH_PANEL_INTR# [52] Need very close to EC
79 BAT54CPT-2-GP 3D3V_AUX_S5 C2417 3D3V_AUX_S5
[17] PM_SUSWARN# GPIO2/SPI_CS# C2422 PDG is 47p SCD1U10V2KX-5GP
75.00054.K7D

2
5 CH751H-40PT-GP
GND R2431
124 18 1 2
[15,82,83] DGPU_PWROK
[44] DIS_DTM 121
GPIO10/LPCPD# GND
45
83.R0304.A8F 330KR2J-L1-GP
GPIO85/GA20 GND
[58] E51_TxD 111 78
R2444 L_BKLT_EN_EC GPIO83/SOUT_CR GND 1KR2J-1-GP
1 2 9 89
[15] L_BKLT_EN eDP

S
1
0R2J-2-GP GPIO65/SMI# GND R2432
116
GND PSL_OUT# KBC_ON#_GATE_L KBC_ON#_GATE
eDP backlight Control from PCH [17] PM_CLKRUN#_EC 8
GPIO11/CLKRUN#
1 2 1 2 G G
[27] AMP_MUTE# 30 103
1

R2446 1 GPIO55/CLKOUT/IOX_DIN_DIO AGND R2433

[53] LVDS_R2136_BKLT_EN LVDS 2 X01 0321
1

0R2J-2-GP R2445 20KR2J-L2-GP Q2402 D

Backlight Control from LVDS Converter 100KR2J-1-GP NPCE985PA0DX-1-GP R2435 DMP2130L-7-GP

D
71.00985.C0G 0R0402-PAD-2-GP 84.02130.031
2ND = 84.03413.A31
2

3D3V_AUX_KBC 3D3V_AUX_KBC
EC_AGND
Layout Note:

1
Connect GND and AGND planes via either
AOAC Ambient temperature detect 0R resistor or connect directly. R2436
10KR2J-3-GP
Q2403
EC_AGND G

2
VBAT
D S5_ENABLE

S
EC_GPIO47 High Active
1

3D3V_AUX_S5
R2437 2N7002K-2-GP
10KR2F-2-GP R2438 R2434 84.2N702.J31
1

0R2J-2-GP 1 2 ECRST# 2ND = 84.2N702.031

1 2 R2439 DY 3rd = 84.07002.I31
DY
2

A 0R2J-2-GP A
10KR2J-3-GP 4th = 84.2N702.W31
AMB_TEMP
Q2401 C2418
2

PROCHOT_EC G
SC1U6D3V2KX-GP
E
2

DY
2

R2441 D H_PROCHOT#_EC 1 R2440 2 H_PROCHOT# [4,42,44,46] [26,36,76] PURE_HW_SHUTDOWN# B

2
1

NTC-10K-26-GP C2419 C2420 0R0402-PAD-2-GP <Core Design>

R2442 S Q2404
69.60037.011
SCD1U10V2KX-5GP

C
1

100KR2J-1-GP C2421 MMBT3906-4-GP

DY
SC100P50V2JN-3GP

Wistron Corporation
1

2N7002K-2-GP SC47P50V2JN-3GP 84.T3906.A11

84.2N702.J31 2nd = 84.03906.F11 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

2ND = 84.2N702.031 Taipei Hsien 221, Taiwan, R.O.C.

3rd = 84.07002.I31
4th = 84.2N702.W31 Title
EC_AGND
KBC Nuvoton NPCE985
Size Document Number Rev
A2 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 24 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM
SPI Flash ROM(8M) for PCH
3D3V_S5 3D3V_S5

C2501
SC10U6D3V3MX-GP
1

1
C2502
D
DY D

4
3
SCD1U10V2KX-5GP

2
R2501 RN2501
4K7R2J-2-GP
DY SRN4K7J-8-GP Single SPI shared flash connection (SPI Quad I/O mode)

1
2
SPI25 3D3V_S5

[18,24] SPI_CS0#_R 1 CS# VCC 8

[18,24] SPI_SO_R 2 DO/IO1 HOLD#/IO3 7 SPI_HOLD# [18]
[18] SPI_W P# 3 WP#/IO2 CLK 6 SPI_CLK_R [18,24]
4 GND DI/IO0 5 SPI_SI_R [18,24]

1
W 25Q64FVSSIQ-GP
EC2502 DY EC2501 EC2503
SC4D7P50V2CN-1GP 72.25Q64.K01 SC4D7P50V2CN-1GP DY DY SC10P50V2JN-4GP
2

2
C C
Source QUAD/DUAL fast read DUAL fast read

72.25Q64.K01 O O

72.25647.00A O O
Refer to "NCPE985x/ NPCE995x board design reference guide"

SSID = RBATT
+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5
A00 0619
AFTP2502 1 +RTC_VCC
B D2501 B

RTC1 1KR2J-1-GP 3
R2502
1 2 1 RTC_PW R 1
PWR

2
GND 2
NP1 BAS40CW -GP C2503
NP1 SC1U6D3V2KX-GP
NP2 83.00040.E81
1
NP2

BAT-AAA-BAT-054-P06-GP-U 1 AFTP2501
62.70001.061

Q2505
G
A <Core Design> A
1

D RTC_DET# [20]
R2504
10MR2J-L-GP S
Wistron Corporation
2N7002K-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

84.2N702.J31 Taipei Hsien 221, Taiwan, R.O.C.

2ND = 84.2N702.031
3rd = 84.07002.I31 Title
4th = 84.2N702.W31
Flash/RTC
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 25 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Thermal
Fan controller1
5V_S0
R2605 FAN261
0R2J-2-GP
3D3V_S0 3D3V_S0 1 2 FON# 1 8
DY

SC4D7U6D3V3KX-GP
FSM# GND

C2605

C2611
2 7

SCD1U10V2KX-5GP
5V_S0 VIN GND
FAN_VCC_1 3 6
VOUT GND

1
D [24] FAN1_DAC_1 4 VSET GND 5 D

1
2

2
RN2602 APL5606AKI-TRG-GP
SRN2K2J-1-GP 74.05606.A71
2nd = 74.02113.0E1
3D3V_S0 Layout Note:

4
3
Need 10 mil trace width.
6 1 THM_SML1_DATA
[18,24,76] SML1_DATA
5 2 FAN1
84.2N702.A3F
C2601
SC10U6D3V3MX-GP

0R0402-PAD-2-GP
C2602
SCD1U10V2KX-5GP 4
1

4 3 2nd = 84.DM601.03F [24] FAN_TACH1 1 R2606 2 FAN_TACH1_C 1

3rd = 84.2N702.E3F
Q2601 4th = 84.2N702.F3F 2
2

2N7002KDW -GP FAN_VCC_1 3

THM_SML1_CLK 5

C2603
SC2200P50V2KX-2GP
2
1

1
C2604 D2601 ETY-CON3-8-GP
[18,24,76] SML1_CLK Layout Note: SC4D7U6D3V3KX-GP 20.F1841.003
84.03904.L06 Signal Routing Guideline: DY DY DY

2
2ND = 84.03904.P11 Trace width = 15mil

1
NCT7718_DXP
THM26 CH551H-30PT-GP
3

1 8 THM_SML1_CLK 83.R5003.C8F
C C2606 C2607 VDD SCL THM_SML1_DATA FAN_TACH1 AFTP2601 C
1 2 D+ SDA 7 2ND = 83.R5003.H8H 1
Q2603 SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT# 3rd = 83.5R003.08F
DY
2

PMBS3904-1-GP T_CRIT# D- ALERT# FAN_VCC_1 AFTP2602

4 5 1

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
2

T_CRIT# GND

1
NCT7718_DXN

C2608

C2609
2.System Sensor, Put on palm rest NCT7718W -GP DY DY

2
74.07718.0B9
A00 0618
1

R2601 1204 change to PCH_PWROK

0R0402-PAD-2-GP
Q2602
Layout Note: [17,24,36] PCH_PW ROK G
2

C2812 close U2801

D
PURE_HW _SHUTDOW N# [24,36,76]
THERM_SYS_SHDN# S

1
Layout Note: 2N7002K-2-GP C2610
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 84.2N702.J31 DY SCD1U10V2KX-5GP

2
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
3D3V_S0

R2603 1 2 18K7R2F-GP ALERT#

B B
R2604 1 2 2KR2F-3-GP T_CRIT#

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 26 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

AGND DGND
EC2708 1 SCD1U10V2KX-5GP
[29] LINE1_VREFO_R MIC2_VREFO [29] DY2
AUD_AGND EC2707 1 2 SCD1U10V2KX-5GP
[29] LINE1_VREFO_L

SC2D2U6D3V2MX-GP
EC2706 1 2 SCD1U10V2KX-5GP
D D
[29] AUD_HP1_JACK_L EC2705 SCD1U10V2KX-5GP
1 2
3D3V_S0 25mA +3V_AVDD
[29] AUD_HP1_JACK_R EC2704 1 SCD1U10V2KX-5GP
DY2

1 C2705
1 2
R2701
0R0402-PAD-2-GP
SC1U6D3V2KX-GP
C2704
AGND DGND EC2703 1 2 SCD1U10V2KX-5GP

1
A00 0618 1 2
Layout Note:

1
C2701 C2702
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP +5V_AVDD A00 0618 5V_S0 AUD_AGND Tied at point only under
2

Close pin36 Codec or near the Codec

AUD_VREF 2

LDO1_CAP 2
R2703

1
+3V_AVDD 1 2
+5V_AVDD
1.5A

CPVEE
C2703

CBN
5V_S0 +5V_PVDD SC1U6D3V2KX-GP 0R0603-PAD-2-GP-U
AUD_AGND

1
C2710 C2711 AGND DGND

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP
0R0805-PAD-2-GP-U
A00 0618 2 R2702 1
Layout Note:

2
Place close to Pin 26 R2711 2 0R0603-PAD-2-GP-U

36
1

35

34

33

32

31

30

29

28

27

26

25
C2706 C2707 C2708 C2709 HDA27 R2706 1 2 0R0603-PAD-2-GP-U
1

1
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

0R0805-PAD-2-GP-U

VREF
CPVEE

LDO1_CAP
CPVDD

CBN

HP_OUT_R

LINE1_VREFO_R
HP_OUT_L

LINE1_VREFO_L

MIC2_VREFO

AVDD1

AVSS1
2 R2704 1
2

CBP 37 24 AUD_AGND AUD_AGND Layout Note:

CBP LINE2_L
Tied at point only under
AUD_AGND 38 AVSS2 LINE2_R 23 Codec or near the Codec
AUD_AGND C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22
LDO2_CAP LINE1_L LINE1_L [29]

Layout Note: Layout Note: +3V_1D5V_AVDD 40 AVDD2 LINE1_R 21 LINE1_R [29]

Close pin41 Close pin46 +5V_PVDD 41 PVDD1 CPVREF 20

C AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP AUD_AGND C

[29] AUD_SPK_L+ SPK_L+ MIC_CAP
DGND AGND [29] AUD_SPK_L-
AUD_SPK_L- 43 SPK_L- MIC2_R/SLEEVE 18 SLEEVE [29] Layout Note:
AUD_SPK_R- 44 17 Width>40mil, to improve
[29] AUD_SPK_R- SPK_R- MIC2_L/RING2 RING2 [29]
A00 0618 Headpohone Crosstalk noise
3D3V_S0 1D5V_S0 +3V_1D5V_AVDD AUD_SPK_R+ 45 16
0R0402-PAD-2-GP [29] AUD_SPK_R+ SPK_R+ MONO_OUT
1 R2705 2 +5V_PVDD 46 15 JDREF R2707 1 2 20KR2F-L-GP AUD_AGND
0R0402-PAD-2-GP PVDD2 JDREF

GPIO0/DMIC_DATA
1

GPIO1/DMIC_CLK
R2710 1 2 0R2J-2-GP 1 R2708 2 EAPD# 47 14
DY C2715 [24] AMP_MUTE# PDB SENSE_B

SDATA_OUT
SC4D7U6D3V3KX-GP COMBO-GPI 48 13 AUD_SENSE_A 1 2 AUD_SENSE
2

SPDIFO/GPIO2 SENSE_A AUD_SENSE [29]

LDO3_CAP

SDATA_IN

DVDD_IO
BIT_CLK

PCBEEP
RESET#
Close pin40 49
GND
R2709

DVDD

SYNC
DVSS
39K2R2F-L-GP
AUD_AGND remove D2702 R2710 R2711 Add R2708_0R(PDB pin)
ALC3223-CG-GP
Layout Note:

10

11

12
+3V_AVDD AGND Place close to Pin 13

LDO3_CAP
AUD_PC_BEEP
1 +3V_AVDD
Azalia I/F EMI TP2702
DGND

C2718
1

C2719
EC2701 ER2701 C2716 C2717

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP 47R2J-2-GP SC4D7U6D3V3KX-GP

1
2

2
2 1PCH_AZ_CODEC_SDOUT1
2 1HDA_CODEC_SDOUT 0109 Add
DY DY Close pin2 SC22P50V2JN-4GP

2
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
2 1HDA_CODEC_BITCLK_C 1 2HDA_CODEC_BITCLK
DY DY C2724
EC2702 ER2702 1 2
SC22P50V2JN-4GP 47R2J-2-GP DY A00 0618
B 0R0402-PAD-2-GP B

[52] DMIC_DATA 1 R2714 2 DMIC_DATA_R

[52] DMIC_CLK 1 R2716 2 DMIC_CLK_R

0R0402-PAD-2-GP
[19] HDA_CODEC_SDOUT
2

C2723
SC22P50V2JN-4GP
DY [19] HDA_CODEC_BITCLK 0R0402-PAD-2-GP
1

[19] HDA_SDIN0 1 R2718 2 HDA_CODEC_SDIN0

Close pin3 [19] HDA_CODEC_SYNC

HDA_CODEC_SYNC

HDA_CODEC_RST#
[19,29] HDA_CODEC_RST#
RN

D2701
HDA_SPKR_R 1
[20] HDA_SPKR 1 4
[24] KBC_BEEP 2 3 3AUD_PC_BEEP_C 1 2 AUD_PC_BEEP

0R4P2R-PAD KBC_BEEP_R 2 C2720

1

RN2701 SCD1U10V2KX-5GP
BAT54CPT-2-GP R2717
1KR2J-1-GP
75.00054.K7D
2nd=75.00054.J7D
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3223

Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 27 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 28 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

Speaker
A00 0618
SPK1
5
D 0R0603-PAD-2-GP-U 2 1 R2904 AUD_SPK_R+_C 1 D
[27] AUD_SPK_R+
0R0603-PAD-2-GP-U 2 1 R2903 AUD_SPK_R-_C 2
[27] AUD_SPK_R- 0R0603-PAD-2-GP-U 2 R2902 AUD_SPK_L+_C
[27] AUD_SPK_L+ 1 3
0R0603-PAD-2-GP-U 2 1 R2901 AUD_SPK_L-_C 4 CONN Pin Net name
[27] AUD_SPK_L-
6
Pin1 SPK_R+
ACES-CON4-7-GP-U Pin2 SPK_R-
20.F0772.004
Pin3 SPK_L+

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP
EC2901

EC2902

EC2903

EC2904
1

1
DY DY DY DY Pin4 SPK_L_

2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

C C

RN2901
SRN2K2J-1-GP Universal jack
[27] MIC2_VREFO 1 4
2 3
A00 0618
HPMIC1
[27] RING2 0R0603-PAD-2-GP-U 2 1 R2906 RING2_R 3
R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 0R0603-PAD-2-GP-U 2 1 R2907 AUD_PORTA_L_R_B 1
[27] AUD_HP1_JACK_L C2907 1
[27] LINE1_L 2LINE1_L_C R2921 1 2 1KR2J-1-GP
SC4D7U6D3V3KX-GP R2912 1 2 2K2R2J-2-GP 5
[27] LINE1_VREFO_L
[27] AUD_SENSE 6
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 0R0603-PAD-2-GP-U 2 1 R2909 AUD_PORTA_R_R_B 2
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2LINE1_R_C R2922 1 2 1KR2J-1-GP 0R0603-PAD-2-GP-U 2 1 R2911 SLEEVE_R 4
SC4D7U6D3V3KX-GP R2913 1 2 2K2R2J-2-GP MS
[27] LINE1_VREFO_R

SC100P50V2JN-3GP
EC2908

SC100P50V2JN-3GP
EC2907

SC100P50V2JN-3GP
EC2906

SC100P50V2JN-3GP
EC2905
1

1
10KR2J-3-GP
R2919

10KR2J-3-GP
R2920
[27] SLEEVE

1
AUDIO-JK404-GP
DY 22.10270.V01
2

2
2

2
AUD_AGND

AUD_PORTA_L_R_B 1 AFTP2906
AUD_PORTA_R_R_B 1 AFTP2907
AUD_AGND 1 AFTP2908
B AUD_SENSE AFTP2909 B
1

AUD_AGND AUD_AGND

AUD_PORTA_R_R_B 5V_PW R_2 +3V_AVDD

AUD_PORTA_L_R_B
RING2_R
1

AUD_SENSE
SLEEVE_R R2915 R2918
220KR2J-L2-GP 100KR2J-1-GP DY
2

2
AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP
ED2901

ED2902

ED2903

ED2904

ED2905

0R0402-PAD-2-GP
1

1 R2917 2 HDA_CODEC_RST# [19,27]

U2901
S D
4 3
A
DY DY DY DY DY AUD_AGND
G G
SLEEVE [27] <Core Design> A

POP_G1 5 2 POP_G2
D S Wistron Corporation
1

6 1
C2901 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
75.02025.077 75.02025.077 75.02025.077 75.02025.077 75.02025.077 2N7002KDW -GP DY SC1U6D3V2KX-GP Taipei Hsien 221, Taiwan, R.O.C.
2

Title

Speaker/HPMIC CONN
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 29 of 101
5 4 3 2 1
 5 4 3 2 1

A00 0618
SSID = LOM 0R0603-PAD-2-GP-U
Close To Pin 13
3D3V_S0

C3011 R3008 1 2 ISOLATE#

3D3V_S5 3D3V_LAN_S5 LANXOUT 1 2 1 2 CARD_3D3V R3014

1
PA102FMG-GP-U 1KR2J-1-GP
Q3004 R3015

1
SC15P50V2JN-2-GP C3015
15KR2F-GP DY
DY

SCD1U10V2KX-5GP
S D

2
1

3
1
C3013
SCD1U10V2KX-5GP
R3021 X3001

1
D 10KR2J-3-GP XTAL-25MHZ-155-GP D

G
C3003

1
R3022 SC1U6D3V2KX-GP
DY

2
20KR2F-L-GP C3005

2
SCD1U10V2KX-5GP
1 2 PM_LAN_ENABLE_R

2
3D3V_LAN_S5

LAN_ENABLE_R_C
main: 84.00102.031
2nd: 84.03403.031
C3001

2
1
LANXIN 1 2 RN3001
Q3001
G
[24] PM_LAN_ENABLE SC15P50V2JN-2-GP DY
1

D SRN10KJ-5-GP
R3023
DY

1Q402_13
4
100KR2J-1-GP S 3D3V_LAN_S5

2N7002K-2-GP Close To Pin 27

2

1
VDD33/18
R3036
0R2J-2-GP 2 3 PLT_RST#_LAN
LAN_SW [17,24,58,65,73] PLT_RST# DY

1
C3017 C3027
Q3003
DY

2
PMBS3904-1-GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP
2

2
ENSW REG
2 R3016 1 A00 0618
A00 0618

1
3D3V_LAN_S5 VDDREG 0R0402-PAD-2-GP
C A00 0618 0311 modify power rail R3037 C
0R0402-PAD-2-GP
R3006 1 2 0R0603-PAD-2-GP-U
3D3V_LAN_S5

2
LAN_SW LAN_SW
1

1
C3007 C3008 C3012 C3009 C3010
R3039
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

10KR2J-3-GP
2

U3001
2

LAN_W AKE# VDD10

X5R VDD10
3
8
AVDD10 MDIP0 1
2
LAN_MDI0P [31]
VDD10 AVDD10 MDIN0 LAN_MDI0N [31]
46 AVDD10 MDIP1 4 LAN_MDI1P [31]
MDIN1 5 LAN_MDI1N [31]
VDD10 33 6
DVDD10 MDIP2 LAN_MDI2P [31]
MDIN2 7 LAN_MDI2N [31]
EVDD10 20 9
EVDD10 MDIP3 LAN_MDI3P [31]
0110 add CAP MDIN3 10 LAN_MDI3N [31]
3D3V_LAN_S5 11
need close to chip 3D3V_LAN_S5 AVDD33
48 AVDD33
44 LANXIN
3D3V_S0 CKXTAL1 LANXOUT
A00 0618 Pin12 Pull VCC33 (3D3V_S0) 12 DVDD33 CKXTAL2 45
3D3V_LAN_S5 32
Supported RTD3 DVDD33

1
C3028
SCD1U10V2KX-5GP
R3034 1 2 0R0603-PAD-2-GP-U
A00 0618 CARD_3D3V 13 34 ENSW REG R3038
CARD_3V3 ENSWREG_H REGOUT 2K49R2F-GP
36

2
0R0603-PAD-2-GP-U VDD33/18 REGOUT RSET
27 VDD33/18 RSET 47 2 1
B L3010 R3007 B
REGOUT 1 2 1 2 VDD10 VDDREG 35
IND-4D7UH-242-GP VDDREG LED_CR TP3004 TPAD14-OP-GP
LED_CR 40 1
LAN_SW 41 LED0 1 TP3003 TPAD14-OP-GP
C3024 C3014 LAN_W AKE# LED0 LED1 TP3002 TPAD14-OP-GP
[24] LAN_W AKE# 39 LANWAKE# LED1/GPO 38 1
1

C3018 LAN_SW LAN_SW C3019 C3020 C3021 C3022 ISOLATE# 31 37 LED3 1 TP3001 TPAD14-OP-GP
ISOLATE# LED3
1

68.4R71E.10G A00 0618

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY
2

2
SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

[18] CLK_PCIE_LAN_REQ4# 29 15 SP2 2 R3017 1 0R0402-PAD-2-GP SP2/SD_D0/MS_D1 [33]

2

PLT_RST#_LAN CLKREQ# SD_D0/MS_D1 SP1 R3018 0R0402-PAD-2-GP

30 PERST# SD_D1 14 2 1 SP1/SD1 [33]
19 SP6 2 R3019 1 0R0402-PAD-2-GP SP6/SD_D2/MS_CLK [33]
CLK_PCIE_LAN_P4 SD_D2/MS_CLK SP5 R3020 0R0402-PAD-2-GP
23 REFCLK_P SD_D3/MS_D3 18 2 1 SP5/SD_D3/MS_D3 [33]
CLK_PCIE_LAN_N4
X5R 24 REFCLK_N
16 SP3 2 R3032 1 0R0402-PAD-2-GP SP3/SD_CLK/MS_D0 [33]
PCIE_PTX_LANRX_P4_C SD_CLK/MS_D0 SP4 R3033 1 0R0402-PAD-2-GP
21 HSIP SD_SMD/MS_D2 17 2 SP4/SD_CMD/MS_D2 [33]
PCIE_PTX_LANRX_N4_C 22 28 SP7 2 R3035 1 0R0402-PAD-2-GP SP7/SD_W P/MS_BS [33]
EVDD10 HSIN SD_WP/MS_BS
LAN_TXP_C_PCH_RXP4 25 42 SD_CD# [33]
LAN_TXN_C_PCH_RXN4 HSOP SD_CD#
26 HSON MS_CD# 43 MS_CD# [33]
1

C3016 C3023
GND 49
SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
2

RTL8411B-CGT-GP
71.08411.D03
A <Core Design> A
C3025 SCD1U10V2KX-5GP
LAN_TXP_C_PCH_RXP4 1 2 PCIE_PRX_LANTX_P4 [16]
LAN_TXN_C_PCH_RXN4 1
C3026
2
SCD1U10V2KX-5GP
PCIE_PRX_LANTX_N4 [16]
Wistron Corporation
PCIE_PTX_LANRX_P4_C 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PCIE_PTX_LANRX_P4_C [16] Taipei Hsien 221, Taiwan, R.O.C.
PCIE_PTX_LANRX_N4_C
PCIE_PTX_LANRX_N4_C [16]
Title
CLK_PCIE_LAN_P4 [18]
CLK_PCIE_LAN_N4 [18] LOM(RTL8411B)
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 30 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = LOM

D
GIGA LAN TransFormer D

XF3101 MCT1
[30] LAN_MDI3N 2 23 MDO3-
1 MCT0 U3101
EC3108 DY2SC10P50V2JN-4GP 1 24 MCT0
MCT3 LAN_MDI0P 1 9 LAN_MDI0P
[30] LAN_MDI3P 3 22 MDO3+ LAN_MDI0N 2 8 LAN_MDI0N
1 2 1:1 MCT2 3
EC3107 DY SC10P50V2JN-4GP LAN_MDI1P 4
DY 7 LAN_MDI1P
[30] LAN_MDI2N 5 20 MDO2- LAN_MDI1N 5 6 LAN_MDI1N
1
EC3106 DY2SC10P50V2JN-4GP 4 21 MCT1
ESD3V3U4ULC-GP

4
3
2
1
6 19 MDO2+
[30] LAN_MDI2P
1 1:1 RN3101 83.3V3U4.0A0
EC3105 DY2SC10P50V2JN-4GP SRN75J-1-GP
[30] LAN_MDI1N 8 17 MDO1- U3102
1
EC3104 DY2SC10P50V2JN-4GP 7 18 MCT2 LAN_MDI2P 1 9 LAN_MDI2P

MCT 5
6
7
8
LAN_MDI2N 2 8 LAN_MDI2N
9 16 MDO1+ 3
[30] LAN_MDI1P
1:1 LAN_MDI3P DY LAN_MDI3P
LOM_TCT

1
EC3103 DY2SC10P50V2JN-4GP LAN_MDI3N
4
5
7
6 LAN_MDI3N

1
[30] LAN_MDI0N 11 14 MDO0-
1 C3101
EC3102 DY2SC10P50V2JN-4GP 10 15 MCT3 SC100P3KV8JN-2-GP ESD3V3U4ULC-GP

2
C
[30] LAN_MDI0P 12 13 MDO0+ 78.1013N.1AL 83.3V3U4.0A0 C
1 1:1
EC3101 DY2SC10P50V2JN-4GP XFORM-24P-63-GP

68.89240.30D
1

C3106
SCD01U16V2KX-3GP
2

RJ45
Follow Reference Schematic 0.01uF~0.4uF 9
Layout: MDO0+ 1
Place near RJ45 MDO0- 2
MDO1+ 3
MDO2+ 4
AFTP3107 1 MDO0+ MDO2- 5
AFTP3102 1 MDO0- MDO1- 6
AFTP3101 1 MDO1+ MDO3+ 7
AFTP3103 1 MDO2+ MDO3- 8
AFTP3104 1 MDO2- 10
AFTP3106 1 MDO1-
AFTP3105 1 MDO3+ RJ45-8P-118-GP-U
AFTP3108 1 MDO3-
22.10019.141

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RJ45+Transformer
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 31 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 32 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = SDIO

D
CARD_3D3V_S0 CARD_3D3V_S0 D

CARD1

Close To Pin 4 MS_VCC AFTP3308 1 11 SD_VDD/MMC_VDD MS_DATA0 12 SP3/SD_CLK/MS_D0 [30]

MS_DATA1 13 SP2/SD_D0/MS_D1 [30]
4 MS_VCC MS_DATA2 10 SP4/SD_CMD/MS_D2 [30]
1

1
C3303 C3302 C3304 7 SP5/SD_D3/MS_D3 [30]
MS_DATA3
SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP
[30] SD_CD# 20 8 MS_CD# [30]
2

2
SD_CD MS_INS
[30] SP5/SD_D3/MS_D3 3 SD_CD/DAT3/MMC_RSV MS_BS 15 SP7/SD_W P/MS_BS [30]
MS_SCLK 5 SP6/SD_D2/MS_CLK [30]
[30] SP3/SD_CLK/MS_D0 14 SD_SLK/MMC_CLK
[30] SP4/SD_CMD/MS_D2 6 23 1 AFTP3309
SD_CMD/MMC_CMD GND
GND 24
[30] SP2/SD_D0/MS_D1 18 SD_DAT0/MMC_DAT
[30] SP1/SD1 19 SD_DAT1
[30] SP6/SD_D2/MS_CLK 1 SD_DAT2 SD_GND 21
Close To Pin11 SD_VCC
[30] SP7/SD_W P/MS_BS 22 SD_WP/SW MS_VSS 16
MS_VSS 2

NP1 NP1 SD_VSS/MMC_VSS1 9

NP2 NP2 SD_VSS/MMC_VSS2 17

CARDBUS22P-SKT-2-GP-U
62.10051.H21
C C

Reserve EMI Cap, 0107 CLK Cap DY

AFTP3301 1 SP1/SD1
AFTP3302 1 SP2/SD_D0/MS_D1
AFTP3303 1 SP3/SD_CLK/MS_D0
AFTP3304 1 SP4/SD_CMD/MS_D2
AFTP3305 1 SP5/SD_D3/MS_D3
SP1/SD1 AFTP3306 1 SP6/SD_D2/MS_CLK
SP2/SD_D0/MS_D1 AFTP3307 1 SP7/SD_W P/MS_BS
SP3/SD_CLK/MS_D0
SP4/SD_CMD/MS_D2
SP5/SD_D3/MS_D3
SP6/SD_D2/MS_CLK
SP7/SD_W P/MS_BS
EC3301
SC4D7P50V2BN-GP

EC3302
SC4D7P50V2BN-GP

EC3303
SC4D7P50V2BN-GP

EC3304
SC4D7P50V2BN-GP

EC3305
SC4D7P50V2BN-GP

EC3306
SC4D7P50V2BN-GP

EC3307
SC4D7P50V2BN-GP

B B
1

DY DY DY DY DY DY DY
2

layout note:
EC3305 need colse to chip

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Card Reader CONN
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 33 of 101
5 4 3 2 1
 5 4 3 2 1

USB3.0 Port2
SSID = USB
USB30_VCCB USB2
CHASSIS CHASSIS
10 13
USB30_TXDP1_C 9
AFTP3408 1 1

USB30_TXDN1_C 8
USB3.0 Port1 with power share USB20_DN0_C 2
USB30_VCCA 7
D USB1 AFTP3405 1 USB20_DN0_C USB20_DP0_C 3 D
AFTP3406 1 USB20_DP0_C USB30_RXDP1_C 6
AFTP3407 1 1 5 USB30_RXDN0_C 4
VBUS STDA_SSRX- USB30_RXDP0_C USB30_RXDN1_C
STDA_SSRX+ 6 5
11 12
USB20_DN1_C 2 8 USB30_TXDN0_C CHASSIS CHASSIS

USB20_DP1_C D- STDA_SSTX- USB30_TXDP0_C

3 9 SKT-USB13-32-GP-U
D+ STDA_SSTX+
AFTP3403 1 USB20_DN1_C 10 X01 0321
22.10341.531 1 AFTP3404
AFTP3402 USB20_DP1_C 10
1 11 11
12 4 USBDET1# 1 2 USBDET_CON# [24]
12 GND
13 13 GND_DRAIN 7
R3402
0R0402-PAD-2-GP
SKT-USB13-144-GP X02 stuff TR3412
1 AFTP3401 A00 0618
22.10339.W31 1 2 USB30_TXDN1_R 1 R3441 2 USB30_TXDN1_C
[16] USB3_PTX_CRX_N1
C3407 0R0402-PAD-2-GP [16] USB_PP0 A00 0618 USB20_DP0_C
SCD1U10V2KX-5GP
X02 stuff TR3403

A00 0618 TR3412

A00 0618 4 3
[16] USB3_PTX_CRX_N0 1 2 USB30_TXDN0_R 1 R3404 2 USB30_TXDN0_C [35] USB_PP1_R USB20_DP1_C A00 0618
1 2
C3401 0R0402-PAD-2-GP
C SCD1U10V2KX-5GP C
FILTER-4P-62-GP
TR3403 69.10080.021
1 2 2nd = 69.10103.061
A00 0618 A00 0618
4 3 [16] USB_PN0 USB20_DN0_C
[16] USB3_PTX_CRX_P1 1 2 USB30_TXDP1_R 1 R3415 2 USB30_TXDP1_C
FILTER-4P-62-GP
69.10080.021 C3409 0R0402-PAD-2-GP A00 0618
2nd = 69.10103.061 SCD1U10V2KX-5GP

[35] USB_PN1_R USB20_DN1_C

A00 0618 A00 0618
A00 0618
[16] USB3_PTX_CRX_P0 1 2 USB30_TXDP0_R 1 R3406 2 USB30_TXDP0_C [16] USB3_PRX_CTX_N1 1 R3424 2 USB30_RXDN1_C U3403 USB30_VCCB

C3402 0R0402-PAD-2-GP 0R0402-PAD-2-GP

SCD1U10V2KX-5GP USB20_DN0_C 1 8

A00 0618 USB20_DP0_C 2 7

[16] USB3_PRX_CTX_N0 1 R3405 2 USB30_RXDN0_C

U3401 USB30_VCCA A00 0618
0R0402-PAD-2-GP USB30_RXDP1_C 3 6 USB30_TXDN1_C

USB30_TXDP0_C 1 8
B USB30_RXDN1_C USB30_TXDP1_C B
4 5
USB30_TXDN0_C 2 7
A00 0618 A00 0618
AZ1065-06Q-GP
[16] USB3_PRX_CTX_P1 1 R3423 2 USB30_RXDP1_C
USB30_RXDP0_C 3 6 USB20_DP1_C 83.01065.0AJ
0R0402-PAD-2-GP

USB30_RXDN0_C 4 5 USB20_DN1_C
A00 0618
[16] USB3_PRX_CTX_P0 1 R3407 2 USB30_RXDP0_C AZ1065-06Q-GP

0R0402-PAD-2-GP 83.01065.0AJ

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0(1)
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 34 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = USB
5V_S5 USB30_VCCB
U3502

1 GND VOUT#8 8
2 7 C3507
VIN VOUT#7

SC1U6D3V2KX-GP
C3501 3 6
VIN VOUT#6

1
SC1U6D3V2KX-GP
4 5 USB_OC#0_1 [16] C3504 If MLCC is used as Main Source.
EN# OC#

1
D C3502 SC100U6D3V6MX-GP D
Inform Layout team to remark Pin 1 as positive.

SCD1U10V2KX-5GP

2
UP7534QRA8-15-GP
78.10710.52L In case MLCC shortage and other type of Cap With Polarity Is Used.

2
74.07534.C79
2nd = 74.06288.A79
3rd = 74.02000.B71

[24] USB_PW R_EN#

5V_S5 U3503

1 GND FLG1 8 USB_OC#2_3 [16]

2 IN OUT1 7 USB30_VCCC
SC1U6D3V2KX-GP
C3505

3 EN1# OUT2 6 USB30_VCCD

1

[24] USB_PW R_EN# 4 EN2# FLG2 5

2

AP2182SG-13-GP
74.02182.071

C 0319 modify USB Charger circuit C

A00 0618

[24] USBCHG_EN 1 R3505 2 5V_S5

0R0402-PAD-2-GP

1
R3501
A00 0618 U3501 100KR2J-1-GP
Q3502
0R0402-PAD-2-GP 9 1 USBCHG_EN_R G

2
GND INT
[24] USBCHARGER_CB0 1 R3502 2 SB# 8 SB/ D- 2 USB_PN1_R [34]
[16] USB_PN1 7 3 USB_PP1_R [34] D USBCHG_EN#
Y- D+ SEL
[16] USB_PP1 6 Y+ SEL 4
5 VDD S
5V_S5

PI5USB1458AZAEX-GP 5V_S5 2N7002K-2-GP

84.2N702.J31
74.51458.073 2ND = 84.2N702.031
1

1
C3510
SCD1U10V2KX-5GP

R3503
2

100KR2J-1-GP
2

B B
1

R3504
10KR2J-3-GP
DY
2

5V_S5 USB30_VCCA
U3504

1 GND VOUT#8 8
2 7 C3511 C3512
VIN VOUT#7
SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
C3503 3 6
VIN VOUT#6
1

1
SC1U6D3V2KX-GP

USBCHG_EN# 4 5 USB_OC#0_1 [16] C3506

EN# OC#
1

2 SC100U6D3V6MX-GP If MLCC is used as Main Source.

2
UP7534QRA8-15-GP
78.10710.52L Inform Layout team to remark Pin 1 as positive.
2

74.07534.C79 In case MLCC shortage and other type of Cap With Polarity Is Used.
2nd = 74.06288.A79
3rd = 74.02000.B71
USB Power SW (U3504)
A <Core Design> A

Vendor Vendor P/N Wistron P/N Priority

Wistron Corporation
Silergy SY6288DCAC 74.06288.A79 1ST 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DII (Diodes) AP2301MPG-13 74.02301.071 2ND Title

USB Power SW
GMT G547I2P81U 74.00547.F79 3RD Size Document Number Rev
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 35 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

D
Power Good D

3D3V_S0

1
A00 0618 R3601
1KR2J-1-GP

[49] 1D35V_VTT_PW RGD 2 R3610 1 0R0402-PAD-2-GP

2
[7,48] 1D05V_VTT_PW RGD 2 R3611 1 0R0402-PAD-2-GP ALL_SYS_PW RGD [24]

ROSA Run Power

C 3D3V_AUX_S5 C

1 2 PS_S3CNTRL
DY
R3607
100KR2J-1-GP
D G S
6

Q3603 5V_S5 5V_S5

DY 2N7002KDW -GP
84.2N702.A3F U3601 5V_S0
5V_S0
1

S G D
GND 15
A00 0618 1 VIN1#1 VOUT1#14 14 5V_S0 Comsumption

C3603
SC10U6D3V3MX-GP
2 13
VIN1#2 VOUT1#13 Peak current 4.033A

1
[17,24,48,49,51] PM_SLP_S3# 2 R3609 1 3V_5V_S0_EN 3 ON1 CT1 12 CT1
0R0402-PAD-2-GP 4 11 3D3V_S0
VBIAS GND CT2
5 10
[17,24,26] PCH_PW ROK
3D3V_S0

2
ON2 CT2
3D3V_S5 6 VIN2#6 VOUT2#9 9

C3604
SC10U6D3V3MX-GP
7 VIN2#7 VOUT2#8 8

1
C3601
SC470P50V2KX-3GP

C3602
SC470P50V2KX-3GP
3D3V_S0 Comsumption

1
TPS22966DPUR-GP Peak current 3A

2
74.22966.093

2
B B

D3602
BAS16-6-GP
2

3 PURE_HW _SHUTDOW N# [24,26,76]

[45] 3V_5V_EN 1
83.00016.K11
2ND = 83.00016.F11
1

1 2 S5_ENABLE [24]
R3602
200KR2J-L1-GP DY R3603
1KR2J-1-GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 36 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

D D

[5] +V_SM_VREF_CNT
Layout Note:
Place Close SO-DIMMA. Close to DIMM
0D675V_VTTREF 0R2J-2-GP 1D35V_S3
R3704 S3 Power Reduction Circuit PM_DRAM_PWRGD
1 2
DY

1
SA_DIMM_VREFDQ R3706
C 1K8R2F-GP C
SODIMM1

2
2R2F-GP
M_VREF_CA_DIMMA 1 R3708 2

1
C3701

1
SCD022U16V2JX-GP
R3703

2
1K8R2F-GP
+V_VREF_PATH3

1
2
R3707
24D9R2F-L-GP

2
1
R3705
0R0402-PAD-2-GP

B B

SB_DIMM_VREFDQ
SODIMM2

M_VREF_CA_DIMMB

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

S3 Power Reduction
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 37 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

D D

3D3V_S5 0R3J-0-U-GP 3D3V_S5_PCH

R3801
1 2
Non DS3

3D3V_S5

SCD47U16V2ZY-GP
C3801

1
3D3V_S5_PCH
DS3

2
U3801

C 1
DS3 8 C
GND OUT#8
2 IN#2 OUT#7 7
3 IN#3 OUT#6 6
[17,24] PM_SLP_SUS# 1 R3802 2 DS3_PW RCTL 4 EN/EN# OCB 5

SCD47U16V2ZY-GP
C3802

1
0R0402-PAD-2-GP
SY6288CCAC-GP DS3
A00 0618 74.06288.079

2
B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DSW
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 38 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 39 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 40 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 41 of 101
5 4 3 2 1
 5 4 3 2 1

5V_S5

SSID = PWR.Support

2
84.03904.L06

1
PR4202 2nd = 84.03904.P11 3D3V_S5
15KR2F-GP PR4203

2
10KR2J-3-GP

1
PQ3802_1 1 PMBS3904-1-GP 3D3V_S5

1
D
PQ4202 D

2
2

1
PR4211 PSID_DISABLE#_R_C
0103 Add EC4203 Layout Note: 100KR2J-1-GP PD4203 PR4206
ndde close to EL4202 PSID Layout width > 25mil BAV99-12-GP 2K2R2J-2-GP

G
1

3
A00 0618 PQ4201 75.00099.E7D

2
FDV301N-NL-GP 2nd = 75.03101.07D
0R0603-PAD-2-GP-U PR4207
PS_ID_R 1 PR4219 2 PS_ID_R2 D S PS_ID 1 2

D
JGND PSID_EC [24]
SCD1U50V5JX-1-GP 84.00301.A31 33R2J-2-GP
EC4203 2nd = 84.3K329.031
1 2
DY

1
PD4204 PR4208
DY PESD24VS2UT-GP 1 2
EL4202 DY
PAD-2P-4516-GP-U 33R2J-2-GP

3
DCIN1
6
2

NP1 1 AFTP4204
1

2 1 AFTP4203
3
4 +DC_IN AD+
C 5 A00 0619 PU4201 C

SC10U25V5KX-GP
NP2 +DC_IN_C 1 S D 8
S D

PC4205

PC4206
240KR3-GP
7 2 7

SC1U25V5KX-1GP

SCD01U50V2KX-1GP
1
SC10U25V5KX-GP

S D
EC4201

PC4201

PR4209
3 6

K
1

1
EC4202
SCD1U25V2KX-GP

ACES-CON5-27-GP 4 G D 5

1
PR4216 PD4201 PC4202
20.F2182.005 1SMB22AT3G-GP-U1 SCD1U25V3KX-GP SI7121DN-T1-GE3-GP
DY
2

2
AFTP4205 3K3R6J-GP 83.22R03.03G

2
A
EL4201

2
PAD-2P-4516-GP-U
PQ4206_3 PQ4205

1
R2
JGND JGND PQ4204 E Id=-9.6A
1

C AD_OFF_L B
PR4214 B R1 R1
C AD_OFF_R Qg=-25nC
1

100KR2J-1-GP 84.2N702.A3F E PR4210 Rdson=18~30mohm

2nd = 84.DM601.03F R2 PDTA124EU-1-GP 47KR3J-L-GP

2
3rd = 84.2N702.E3F PDTC124EU-1-GP 84.00124.K1K
2

PQ4206 4th = 84.2N702.F3F 84.00124.H1K 2nd = 84.05124.A11

EL4203 2nd = 84.05124.011
3 4
PAD-2P-4516-GP-U
AC_IN#_G 2 5 1 2
PR4212

PC4208
SC1U25V3KX-1-GP

1
1 6 1KR2J-1-GP

2N7002KDW -GP
DY PQ4208
PR4217

2
1

G PQ3808G1 DY 2
PR4215 3D3V_S5 1KR2J-1-GP
B 100KR2J-1-GP PQ3808D
DY B
D

1
S PC4209
2

PR4213 DY

SCD01U50V2KX-1GP
DY 10KR2J-3-GP

2
2N7002K-2-GP
DT MODE 84.2N702.J31
[24] AC_IN_KBC#

1
PW R_CHG_AD_OFF_R

[24] PW R_CHG_AD_OFF BAT_IN#

PQ4203
1 6
PR4218
2 DY 1 2 5 BAT_IN# [24,43,44]
100KR2J-1-GP
DY
3 4

[4,24,44,46] H_PROCHOT# 1DY 2 PQ3807D

DMN66D0LDW -7-GP

PC4207
SC1U6D3V2ZY-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

DCIN Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 42 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support

BT+
D D

Battery CONN

1
C4301 EC4304
SCD1U50V3KX-GP DY DY SC2200P50V2KX-2GP

2
BATT1
10
SRN100J-4-GP 8
RN4301 7
1 8 PBAT_SMBCLK1 6 AFTP4301 1 PBAT_PRES1#
[24,44,53] BAT_SCL
2 7 PBAT_SMBDAT1 5 AFTP4302 1 PBAT_SMBDAT1
[24,44,53] BAT_SDA
3 6 PBAT_PRES1# 4 AFTP4303 1 PBAT_SMBCLK1
[24,42,44] BAT_IN#
4 5 1 2 SYS_PRES1# 3 AFTP4304 1 BT+
R4303 2 AFTP4305 1 SYS_PRES1#
0R0402-PAD-2-GP
1
SC10P50V2JN-4GP
EC4303

EC4302
SC10P50V2JN-4GP

EC4301
SC10P50V2JN-4GP
2 9

1
DY DY DY SYN-CON8-28-GP
1

2
20.82045.008

C C

0109 DY PD4301~4303
BAT_IN# BAT_SDA BAT_SCL Layout Note:
Place near Battery CONN
3

3
PD4303 PD4302 PD4301
BAV99-12-GP BAV99-12-GP BAV99-12-GP
1

2
75.00099.E7D 75.00099.E7D 75.00099.E7D
2nd = 75.03101.07D 2nd = 75.03101.07D 2nd = 75.03101.07D

3D3V_AUX_KBC

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 43 of 101
5 4 3 2 1
 5 4 3 2 1

AD+ +SDC_IN CHARGER_SRC

PU4405
SSID = Charger 8 D
7 D
S
S
1
2
PR4426 1
D01R3721F-GP-U
2

6 D S 3
5 D G 4

1
PG4406 PG4402

PR4435
SI7121DN-T1-GE3-GP

100KR2J-1-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
84.06675.030
2nd = 84.07121.037

2
2
1
PR4418 AD+_G_2
3KR5J-GP PR4421 2 1 0R2J-2-GP
DY

10KR2F-2-GP
PC4428

PR4423
DC_IN_D
2 1

PWR_CHG_ACP
SCD1U25V2KX-GP
D PQ4407 D

1
AD+_G_1

SCD1U25V2KX-GP
3 4

PWR_CHG_ACN
2

SCD1U25V2KX-GP
PC4418

PC4416
ACAV_IN 2 5
AD+
DY

1
PD4405 1 6

1
A K PWR_CHG_1 1 2 PWR_CHG_VCC
PR4403 10R5J-GP 2N7002KDW-GP
PAD-2P-330056-GP PC4410 84.2N702.A3F BQ24715_AGND

1
PC4433 SC1U25V3KX-1-GP 2nd = 84.DM601.03F BQ24715_AGND
SCD1U25V2KX-GP 3rd = 84.2N702.E3F
4th = 84.2N702.F3F

2
BQ24715_AGND BQ24715_AGND CHARGER_SRC
AD+

PU4406 and PU4407:

PC4425
SC10U25V5KX-GP

PC4411
SC10U25V5KX-GP

PC4427
SC10U25V5KX-GP

PC4407
SC10U25V5KX-GP

PC4434
SC10U25V5KX-GP
main source: 84.03660.037

1
PC4413
SCD1U25V2KX-GP
VacDET=2.4V
PR4444
309KR2F-GP
Acok setting=2.4*((PR4444+PR4411)/PR4411) PU4406 PU4407

2
Setting=18.178v FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
2 2

2
3 3
BATDRV 1 4 1 4
10 10 DCBATOUT
PC4432
SCD01U50V2KX-1GP

PWR_CHG_REGN 9 9

1
SC1U25V3KX-1-GP DY 7 7
1

PC4430
SC10U25V5KX-GP
PR4411

PWR_CHG_ACP
PWR_CHG_ACN
KBC FOR DT MODE DY DY 8 6 8 6

1
PC4403
SC10U25V5KX-GP
47KR2F-GP PC4422 1 2 5 5

1
CHECK EE PULL HIGH
2

PR4409
4K02R2F-GP
PC4402

SC1U25V3KX-1-GP

2
1
+VCHGR
ZZ.00215.037
2

2
BQ24715_AGND ZZ.00215.037 PD4402
PL4401 1

A
COIL-2D2UH-11-GP
BQ24715_AGND BQ24715_AGND +SDC_IN PD4401 1 2 1 2 3

2
PU4404 1PS76SB40-GP-U 68.2R210.20C PR4443
3D3V_AUX_S5

PR4427

2D2R5F-2-GP
PWR_CHG_REGN BQ24717RGRR-GP 83.1PS76.01F D01R2512F-3-GP 2

1
BT+
150KR2F-L-GP

1 20

K
ACN VCC

2
3D3V_S5 3D3V_AUX_S5
PR4434

PR4439
4K02R2F-GP 11 PWR_CHG_BATDRV DY DY PC4420 V10P10-GP-U
BATDRV#
1

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
2 SC1U25V3KX-1-GP

1
ACP
1

PG4407

PG4403
C 16 PWR_CHG_REGN PU4403 C

2
REGN
PR4419
100KR2F-L1-GP

DY PR4449 PWR_CHG_CMSRC 3 PR4425 PC4421 1 S D 8

CMSRC
1

100KR2J-1-GP PWR_CHG_BTST 2PWR_CHG_BTST1 1 DCBATOUT_SNUB S D 7

DY 17 1 2 2

1
BTST

SC330P50V3KX-GP
PR4432 PR4414 4 0R3J-0-U-GP 3 S D 6
2

3K3R2J-3-GP 3K3R2J-3-GP ACDRV PWR_CHG_HIDRV SCD047U25V3KX-3-GP BATDRV G D 5

DY DY 18 4
2

HIDRV

1
PC4406
PWR_CHG_ACDET 6
ACDET
DY FDMC6675BZ-GP-U DY PC4424
2

CHARGER_CELL_PIN 10 84.06675.030

2
CELL

SCD01U25V2KX-3GP
19 PWR_CHG_PHASE 2nd = 84.07121.037
PHASE PC4429
1

15 PWR_CHG_LODRV 1 2
LODRV
PR4415
33KR2F-GP

PG4401 2 1 GAP-CLOSE-PWR-3-GP PWR_SDA 8

[24,43,53] BAT_SDA SDA

1
DY 14 PC4401 SCD1U25V2KX-GP PC4412
PG4408 2 GND
[24,43,53] BAT_SCL 1 GAP-CLOSE-PWR-3-GP PWR_SCL 9 SCD1U25V2KX-GP SCD1U25V2KX-GP
SCL PWR_CHG_SRP PR4438 1
13 2 0R0402-PAD-2-GP PWR_CHG_SRP_R
2

2
ACAV_IN PR4430 2 SRP
1 0R0402-PAD-2-GP PWR_CHG_ACOK 5
ACOK PWR_CHG_SRN PR4417 1
ACAV_IN 12 2 0R0402-PAD-2-GP PWR_CHG_SRN_R
SRN
H=ACIN PR4413 2 1BQ24715_IOUT_1 7 BQ24715_AGND BQ24715_AGND

GND
[24] AD_IA IOUT
L=UNAC 0R0402-PAD-2-GP
DIS_DTM:

21
PR4406 1 2 0R0402-PAD-2-GP
H= cell is plus to GND. (reset charger ic)

SC100P50V2JN-3GP
PC4423
L=nornal Follow custormer circuits 1
CHARGER_CELL_PIN BQ24715_AGND
1

PR4452 BQ24715_AGND PWR_CHG_CMPIN:

V-=3.3*(PR4402/(PR4428+PR4402))=1.1099V
2

Follow custormer circuits DY 100KR2J-1-GP 84.2N702.A3F

PQ4412
DY 2nd = 84.DM601.03F
3D3V_AUX_S5

150KR2F-L-GP
1 PR4454 2 3 4 5V_S5 3rd = 84.2N702.E3F
2

PR4428
[24] DIS_DTM 1DY 2 PQ4412_2 0R2J-2-GP 2 DY 5 PQ4413_2 1 DY2DIS_DTM_CELL Close PR4443 4th = 84.2N702.F3F PR4457

1
1 2

1
PC4409 1 6 CHARGER_CELL_PIN PC4431 PQ4413 0R0402-PAD-2-GP H_PROCHOT# [4,24,42,46]
SC1U25V3KX-1-GP SC1U25V3KX-1-GP PR4422 PR4437 2N7002KDW-GP
2N7002KDW-GP 1M8R2J-L-GP 100KR2J-1-GP PQ4413_3 PWR_CHG_REGN
1

84.2N702.A3F PR4436 4 3

2
3D3V_S5
PR4464
100KR2F-L1-GP

DCBATOUT

PWR_CHG_CMPIN
2nd = 84.DM601.03F

2
100KR2F-L1-GP

PWR_CHG_CMPOUT PQ4413_5
+VCHGR
3rd = 84.2N702.E3F DY 1 2
PWR_CHG_CMPOUT
1 2 5 2
4th = 84.2N702.F3F
1

1
PR4402 6 1
2

220KR2F-GP

1
5V_S5
PR4431

316KR2F-GP PR4410

SCD01U25V2KX-3GP
DY 3D3V_AUX_S5 100KR2J-1-GP

PC4419
PC4405
PWR_CHG_ACOK: BQ24715_IOUT_1 SCD01U50V3JX-1GP

2
2

1
PWR_CHG_REGN=6V
2

2
1
PG4404

PG4405
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

PC4426
PR4412 PWR_CHG_ACOK

SC100P50V2JN-3GP
V+=6*(PR4404/(PR4410+PR4404))=3.27V 100KR2F-L1-GP

2
BAT_IN# [24,42,43]

1
B B
CHECK PM BATTERY TYPE
1DCBATOUT_R 1

5
6
7
8
PR4404
1

120KR2J-GP

VCC
2IN+

2OUT
2IN-
CHECK CELL for DT mode

2
LM393PWR-GP
+VCHGR_R

PU4402
PC4414
CHECK EE DY SCD47U6D3V2KX-1-GP [24] AC_IN#
2

2
1OUT
GND
1IN+
1IN-
PQ4406_G
1

PR4446 PWR_CHG_REGN PWR_CHG_REGN

4
3
2
1
1

PQ4406 0R0402-PAD-2-GP PR4448 5V_S5 5V_S5

G

100KR2F-L1-GP

100KR2F-L1-GP

100KR2F-L1-GP

100KR2F-L1-GP
2N7002K-1-GP 10R2F-L-GP

DIS_DTM_CELL
84.2N702.031 DY PR4429 CHECK PM ADAPTER TYPE
2

1
[4,24,42,46] H_PROCHOT# 100KR2J-1-GP
DY
And setting adapter type
2

PR4461

PR4441

PR4453

PR4460
1 2
2

1 2 PQ4406_D D DY S PR4407 DY DY DY DY
PU4401_5

PR4456 BATTERY MON 6D8R2F-GP

2

2
0R2J-2-GP PU4402_1IN+
1 2
A00 0618
1

PR4424 PC4415 DCBATOUT BT+

84.2N702.A3F
1 2 BOOST_MON_1 1 2PU4401_6 SCD1U25V2KX-GP PR4440 2nd = 84.DM601.03F
AD+ [24] BOOST_MON
PR4465

PR4442
316KR2F-GP

412KR2F-GP
PR4445 PU4401_4 120KR2J-GP DY 357KR2F-GP
(AD_IA_HW) 3rd = 84.2N702.E3F
1

1
PC4417
SC1U25V3KX-1-GP

0R0402-PAD-2-GP 20KR2F-L-GP 4th = 84.2N702.F3F

PR4401 PQ4411
2
6
5
4

PWR_CHG_CMPIN 1 PQ4411_D1 3
100KR2J-1-GP

DY DY 2 4
2

PU4401

PU4402_1IN-
1

-
+
PR4416

INA199A1-GP 2 5
2

2
[24] AD_IA_HW2 AD_IA_HW [24]
1 6 PQ4411_D2 1 2 PWR_CHG_CMPIN
1
2
3

15V_S5
2N7002KDW-GP 147KR2F-GP
2

PR4420
DCBATOUT (AD_IA_HW_2)
1
PC4408
SC1U25V3KX-1-GP
2

DIS_DTM_HW: PR4447
1

PR4459 PR4433 180KR2F-GP

DY DY
PQ4408_E

1MR2J-1-GP PWR_CHG_REGN=6V
0R2J-2-GP DY ADAPTER TYPE AD_IA_HW AD_IA_HW_2 SETTING
H_PROCHOT# [4,24,42,46] V+=6*(PR4440/(PR4441+PR4440))=3.27V
2

Setting=3.27*((PR4442+PR4447)/PR4447)=9V
1

PD4403 PR4455 84.2N702.A3F

90W L L 1.099V
2

1N4148WS-7-F-GP 0R0402-PAD-2-GP 2nd = 84.DM601.03F

K APD4403_A 1 PQ4408 3rd = 84.2N702.E3F
PQ4405 4th = 84.2N702.F3F
1

PD4403_K PMBS3906-GP A00 0618

65W H L 0.862329V
3

A 84.03906.F11 PQ4405_3 3 4 A
2

A00 0618 PR4458 PQ4408_C 2 1 PQ4405_2 2 5 PQ4405_5

0R0402-PAD-2-GP PR4462
1
PC4404
SC1U25V3KX-1-GP

0R0402-PAD-2-GP 1 6
45W L H 0.659648V
1

2N7002KDW-GP
2

PR4451 PR4463
680KR2F-GP 0R2J-2-GPDY
DCBATOUT
PQ4405_6

<Core Design>
2

2
PWR_CHG_ACOK

PR4405 Wistron Corporation

100KR2F-L1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

PR4450
1

10KR2F-2-GP Title

CHECK EE CHARGE(BQ24715)
2

Size Document Number Rev

follow custormer circuits. 3D3V_S5
Custom
X02
Date: Friday, June 28, 2013 Sheet 44 of 101
5 4 3 2 1
 A B C D E

SSID = PWR.Plane.Regulator_5v3p3v
PWR_5V_VCLK

PC4526

SCD1U25V3KX-GP
3D3V_AUX_S5 PC4525
DY

1
DCBATOUT SC1KP50V2KX-1GP
PWR_DCBATOUT_5V DY DY PC4532

2
SCD1U25V3KX-GP

1
PG4502

2
BST15V_1

BST15V_2
PR4503 2 1
0R2J-2-GP DY
GAP-CLOSE-PWR-3-GP
4 PG4503 4

2
2 1 PD4503
PR4506 PR4502

3
BAT54S-7-F-GP PD4502
2 DY 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1 GAP-CLOSE-PWR-3-GP BAT54S-7-F-GP
DCBATOUT PWR_DCBATOUT_3D3V PG4505
75.00054.B7D
0R2J-2-GP
2nd = 75.00054.C7D DY 75.00054.B7D
0R0402-PAD-2-GP 2 1 3rd = 75.00054.M7D DY 2nd = 75.00054.C7D

2
PG4504 3rd = 75.00054.M7D
1 2 PR4504 GAP-CLOSE-PWR-3-GP 5V_PWR 15V_S5

2
0R0402-PAD-2-GP PG4506
PG4530
GAP-CLOSE-PWR-3-GP 2 1 GAP-CLOSE-PWR-3-GP
PR4505

1
PG4501 GAP-CLOSE-PWR-3-GP
BOOST_10V 15V_PWR 2 1
1 2 [36] 3V_5V_EN 1 2 PWR_3D3V_EN2 PG4508
2 1

K
1

1
GAP-CLOSE-PWR-3-GP 0R0402-PAD-2-GP PC4533
GAP-CLOSE-PWR-3-GP DY DY
PC4527 PC4534 SC1U25V3KX-1-GP DY PD4501
PG4507 PG4510
SCD1U25V3KX-GP SCD1U25V3KX-GP
DYBZT52C15S-GP

2
1 2 2 1

GAP-CLOSE-PWR-3-GP

A
GAP-CLOSE-PWR-3-GP
PG4511
1 2

GAP-CLOSE-PWR-3-GP

DCBATOUT
PWR_DCBATOUT_3D3V
PC4510 PC4511
PWR_DCBATOUT_5V

SC10U25V5KX-GP

SCD01U50V2KX-1GP
PC4507 PC4508 PC4509

1
1

1
SC10U25V5KX-GP

SCD1U25V2KX-GP

SC10U25V5KX-GP

3
DY 84.00412.037 PC4512 PC4513 PC4514
3

2
5V_PWR 5V_S5
D 84.00412.037
2

8
7
6
5

5
6
7
8

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
PG4512

D
D
D
D
D
D
D
D
D

PU4503 2 1
Design Current=3.34A PU4502 SIS412DN-T1-GE3-GP

12

2
SIS412DN-T1-GE3-GP PU4501 GAP-CLOSE-PWR-3-GP
5.28A<OCP<5.72AA PG4513

VIN
Design Current=8.48A 2 1

G
S
S
S
S
S
S
G

3D3V_S5 3D3V_PWR PC4515 PC4516 13.33A<OCP<15.76A

PR4507 TPS51225RUKR-GP PR4508 GAP-CLOSE-PWR-3-GP
G S
1
2
3
4

4
3
2
1
PG4514 1PWR_3D3V_VBST2_1 2 PWR_3D3V_VBST2 PWR_5V_VBST1 2PWR_5V_VBST1_1 2 PG4515
68.3R310.20A S G 2 1
1D5R3F-GP
9
VBST2 VBST1
17 1
1D5R3F-GP
1
2 1
3D3V_PWR 2nd = 68.3R31B.10U SCD1U25V3KX-GP PWR_3D3V_DRVH2 10 PWR_5V_DRVH1 SCD1U25V3KX-GP 5V_PWR
2 1
PL4503 16 PL4502
GAP-CLOSE-PWR-3-GP DRVH2 DRVH1 GAP-CLOSE-PWR-3-GP
PG4516 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 PG4517
SW2 SW1 IND-2D2UH-46-GP-U
2 1 2 1
1

IND-3D3UH-57GP PWR_3D3V_DRVL2 PWR_5V_DRVL1

D 11
DRVL2 DRVL1
15

1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PU4504 DPU4505
8
7
6
5

5
6
7
8
PG4518 A00 0618 PR4509 DY PR4510 PG4521 A00 0618 PG4522

D
D
D
D

PC4518
SCD1U10V2KX-5GP
D
D
D
D

2 1 PG4520 2D2R5F-2-GP SIS780DN-T1-GE3-GP

VO1
14 PWR_5V_VO1 DY 2D2R5F-2-GP 2 1
1

1
PC4517

SIS780DN-T1-GE3-GP

GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-5GP

1PWR_3D3V_SNUB 2
1

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP PT4502 PWR_3D3V_FB2 4 2 PWR_5V_FB1 DY PT4501 GAP-CLOSE-PWR-3-GP

2
VFB2 VFB1
SE220U6D3VM-28-GP-U

SE220U6D3VM-28-GP-U
PG4519 DY PG4523
2

2
G
2 1 4 4 2 1
G
2

2
S
S
S

1PWR_5V_SNUB
S
S
S

GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 PWR_5V_EN1 GAP-CLOSE-PWR-3-GP

6 20 G S
1
2
3

3
2
1
PG4524 EN2 EN1 PG4525
2 1
S G 2 1
PWR_3D3V_CS2 5 1 PWR_5V_CS1
GAP-CLOSE-PWR-3-GP CS2 CS1 GAP-CLOSE-PWR-3-GP
3V_FEEDBACK

1
PG4531 PG4526
2 1 DY PR4511 19 PWR_5V_VCLK PR4512 2 1
PC4519 57K6R2F-GP VCLK 143KR2F-GP PC4520
DY
2

GAP-CLOSE-PWR-3-GP SC330P50V3KX-GP SC560P50V-GP GAP-CLOSE-PWR-3-GP

2
2 2
PWR_5V3D3V_PGOOD 7 21 PG4527
2

2
PGOOD GND
2 1
VREG3

VREG5
GAP-CLOSE-PWR-3-GP
PG4528
1

1
2 1
3

13

PR4514 PR4515

1
PR4513 DY0R2J-2-GP 0R2J-2-GP DY GAP-CLOSE-PWR-3-GP
6K65R2F-GP 5V_PWR_2 PR4516
3D3V_AUX_S5 3D3V_PWR_2 15KR2F-GP
2

1 2

1 2
PWR_3D3V_FB2_R PG4529 PWR_5V_FB1_R
PC4521 1 2

2
DYSC18P50V2JN-1-GP PC4522 DY
GAP-CLOSE-PWR-3-GP SC18P50V2JN-1-GP
2

2
X01 change PR4120 to 9.76K to solve 5V
1

1
3D3V_S5 voltage fall issue while on heavy loading
PR4517 PR4518
1

10KR2F-2-GP PC4524 9K76R2F-1-GP

1

PC4523 SC1U6D3V3KX-2GP
DY PR4519 SC4D7U6D3V3KX-GP Close to VFB Pin (pin2)
2

2
100KR2J-1-GP

PR4520
2

[17] 3V_5V_POK 2 1
Close to VFB Pin (pin5)
0R0402-PAD-2-GP

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

3V/5V TPS51225
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 45 of 101
A B C D E
 5 4 3 2 1

SSID = CPU.Regulator
PW R_VCC_VREF

1
PR4603 PR4604 PR4605

1
D PR4602 DY 75R2F-2-GP 1MR2F-GP 8K87R2F-2-GP D

NTC-100K-10-GP

2
PC4602

2
1 2

1
PR4606 15KR2F-GP SC4700P50V2KX-1GP
1 2 PR4601 PR4607 PR4608
1 2 1 2 150KR2F-L-GP 150KR2F-L-GP 150KR2F-L-GP
PR4610
PC4603 422KR3F-GP PR4609

2
1 2 56KR2F-GP

SC1KP50V2KX-1GP

PR4611 1 DY 2 75R2F-2-GP PW R_VCC_B-RAMP

PW R_VCC_F-Imax
PR4612

PWR_VCC_THERM
PW R_VCC_O-USR

PWR_VCC_OCP-1
PWR_VCC_IMON
1 2PW R_VCC_SLEW A

39KR2F-GP

PR4613
DCBATOUT 1 2PW R_VCC_VBAT

10R3J-3-GP 3D3V_S0

16

15

14

13

12

11

10

9
C PU4601 C
IMVP_PW RGD PR4614 2 1 2KR2F-3-GP

THERM

IMON

O-USR
SLEWA

OCP-I

B-RAMP

F-IMAX
VBAT
17 8 IMVP_VRON PR4615 1 2 H_VR_ENABLE [7] EC4602
[47] PW R_VCC_CSP1 CSP1 VR_ON

SCD1U25V2KX-GP
0R0402-PAD-2-GP
0117 Add EC4602

1
[47] PW R_VCC_CSN1 18 CSN1 SKIP# 7 PW R_VCC_SKIP# [47]
19 6 PW R_VCC_PW M1 [47]
DY

2
CSN2 PWM1
3D3V_S5 20 CSP2 PWM2 5

21 4 NC#4 PR4626 1 DY 2
NC#21 MODE 0R2J-2-GP
22 3 PW R_PG PR4625 1 2 IMVP_PW RGD [7,24]
NC#22 PGOOD 0R0402-PAD-2-GP
PR4616 1 2 PW R_VCC_GFB 23 2 PW R_VCC_VDD PR4618 1 2 10R3J-3-GP 3D3V_S5
[9] VSS_SENSE 0R0402-PAD-2-GP GFB VDD 1D05S_VCCST

PC4601
SC1U6D3V2KX-GP
PR4617 1 2 PW R_VCC_VFB 24 1
[7] VCC_SENSE VFB VDIO

1
0R0402-PAD-2-GP SCD1U10V2KX-5GP PC4605
VR_HOT#
2 DY 1

ALERT#
DROOP

COMP

VREF

VCLK
H_CPU_SVIDDAT 130R2F-1-GP 1 2 PR4621
GND

GND

2
V5A

H_CPU_SVIDCLK 54D9R2F-L1-GP 1 2 PR4622

TPS51622RSMR-1-GP
25

26

27

28

29

30

31

32

33
VR_SVID_ALERT# 130R2F-1-GP 1 DY 2 PR4623

B B
PW R_VCC_DROOP

PC4604 H_CPU_SVIDDAT [7]

PWR_VCC_V5A

SC470P50V2JN-GP
VR_SVID_ALERT# [7]
28W 15W
2 DY 1 PW R_VCC_COMP

H_CPU_SVIDCLK [7] Fsw PR4604 392K 1M

H_PROCHOT# [4,24,42,44]
1 2 1 PR4620 2 PW R_VCC_VREF Fsw PR4607 75K 150K
PR4619
2

PR4624 1 2 10R3J-3-GP
SCD33U6D3V2KX-1-GP
PC4606

10KR2F-2-GP 3KR2F-GP OCP PR4609 150k 75K

5V_S5
1

PC4607
SC10U6D3V2MX-GP-U

IMON PR4610 680K 422K

1

PR4627
1 2 PC46081 2 Load line PR4620 2.8K 3K
2

5K76R2F-2-GP
SC1500P50V2KX-2GP
PWR_VCC_COMP_1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51622_CPUCORE(1/2)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 46 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator
PW R_DCBATOUT_VCCCORE1

DCBATOUT PW R_DCBATOUT_VCCCORE1 For acoustic noice

PG4702

1
1 2 PC4702 PC4703 PC4704 EC4701 PT4702

SE68U25VM-7-GP-U
DY

SCD1U50V3KX-GP
SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
D GAP-CLOSE-PW R-3-GP D

2
PG4703
1 2
DY
GAP-CLOSE-PW R-3-GP
PG4704
1 2

GAP-CLOSE-PW R-3-GP
PG4701
1 2 PW R_DCBATOUT_VCCCORE1

GAP-CLOSE-PW R-3-GP
PG4705
1 2

1
GAP-CLOSE-PW R-3-GP PC4708 PU4701 5V_S5
PG4706 SC1000P100V3KX-GP CSD97374Q4M-GP-U1 PC4705 SC2D2U10V3KX-1GP

2
1 2 5 VIN VDD 2 1 2

GAP-CLOSE-PW R-3-GP PC4706

PR4702 1 2PW R_VCC_SKIP#1 1 6 PW R_VCC_BOOTR11 2VCC_BOOTR1_R
[46] PW R_VCC_SKIP# SKIP# BOOT_R

2
0R0402-PAD-2-GP PR4703 2D2R3F-L-GP
SCD22U25V3KX-GP
8 7 PW R_VCC_BOOT1 VCC_CORE
[46] PW R_VCC_PW M1 PWM BOOT

PGND
3 4 PW R_VCC_VSW 1 PL4701 1 2 IND-D22UH-9-GP-U
PGND VSW
C C

1
A00 0621

1
PR4701

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
2D2R5F-2-GP DY PT4701

PG4707

PG4708
SE330U2D5VM-14-GP

2
79.3371V.6CL

2
VCC_CORE

VCC_VSW1_GP 1

1
VCC_VSW 1_R

1
PC4701
SC820P50V2KX-1GP
PC4729

PC4730

PC4731

PC4732

PC4733

PC4734

PC4725

PC4736

PC4737

PC4738
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

2
1

1
2

1
PR4704
2K21R2F-GP 28W 15W
DCR sensing PR4704 2.21K 2.21K

2
PR4705 DCR sensing PR4706 2.94K 2.94K
1 2
DCR sensing PR4705 60.4K 29.4K
PC4719

PC4720

PC4721

PC4722

PC4726

PC4709

PC4710

PC4711

PC4724

PC4735
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

PR4706 29K4R2F-GP
1

2K94R2F-GP PR4707
1 2VCC_CSN1_R 1 2
DY DY NTC-10K-26-GP
PW R_VCC_CSN1 [46]
2

B B

A00 0621 PC4707

0318 Add EC4702, need close to PC4741 1 2

SCD15U10V3KX-4-GP
SCD1U10V2KX-4GP
PC4714

PC4727

PC4728

PC4715

PC4739

PC4740

PC4716

PC4741

PC4742

PC4743

EC4702
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

PW R_VCC_CSP1 [46]
1

DY DY DY DY DY DY DY DY DY
2

28W CPU need stuff PC4743, PC4728, PC4739, PC4724, PC4735, PC4738

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51622_CPUCORE(2/2)
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 47 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v
1D05V_PWR 1D05V_S0

PG4802
1 2
Mode Fsw(KHz)
GAP-CLOSE-PW R-3-GP
PG4803
GND 400KHz 1 2
D [17,24,36,49,51] PM_SLP_S3# PR4801 2 1 0R0402-PAD-2-GP PW R_1D05_EN D
GAP-CLOSE-PW R-3-GP
Float 800KHz PG4804
Refer Intel CRB to use SLP_S3# control 1 2

1
PC4818 GAP-CLOSE-PW R-3-GP
SCD1U10V2KX-4GP DY PG4805

2
1 2

GAP-CLOSE-PW R-3-GP
PU4801 PW R_1D05_PGOOD PR4834 1 2 0R0402-PAD-2-GP 1D05V_VTT_PW RGD [7,36] PG4806
1 2
PW R_1D05_VRF_L PR4823 1 2 28 1 PR4835 1 2 10KR2F-2-GP
0R0402-PAD-2-GP EN PGOOD DY PCH_SLP_S0# [17]
GAP-CLOSE-PW R-3-GP
PG4807
PC4826
SCD22U6D3V2KX-1GP

27 2 PW R_1D05_LP# PR4819 1 2 10KR2F-2-GP 1 2

NU#27 NU#2 DY
1

PR4826
95K3R2F-GP 3 PW R_1D05_MODE 2 1 GAP-CLOSE-PW R-3-GP
PW R_1D05_VREF 26
MODE PR4824 DY 0R2J-2-GP PG4808
2

VREF
1 2
2

PW R_1D05_REFIN_1 PR4832 1 2 PW R_1D05_REFIN 25 4 GAP-CLOSE-PW R-3-GP

0R0402-PAD-2-GP REFIN NC#4 PR4830
5D1R3F-GP
1

24 5 PW R_1D05_BOOT 1 2 PW R_1D05_RC
PR4833 REFIN2 BST
105KR2F-1-GP
1 DY 2 PW R_1D05V_GSNS 23 6
GSNS SW#6
PC4821 SC10P50V2JN-4GP Design Current = 6.1A
2

SCD1U25V3KX-GP

1
C Panasonic ETQP3W1R0WFN C
1 DY 2 PW R_1D05V_VSNS 22 7 PC4823 9.57A<OCP<11.31A
SC10P50V2JN-4GP VSNS SW#7 7x7x3.
PC4833

2
Isat : 13 A , DCR 6.9+-15%mOhm 1D05V_PW R
1 2 PW R_1D05_SLEW 21 8
PC4834 SC2700P50V2KX-1-GP SLEW SW#8 PL4801

PR4828 1 2 PW R_1D05_TRIP 20 9 PW R_1D05_SW 1 2

0R0402-PAD-2-GP TRIP SW#9 COIL-1UH-61-GP
2

19 GND

GAP-CLOSE-PWR-3-GP
PR4821

1
PGND 10
DY 0R2J-2-GP PC4829 PC4822 PC4831 DYPC4830 DYPC4825 DYPC4832 PC4828

1
PG4820

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SCD1U10V2KX-5GP
TRIP OCL(A) PR4825

2
18 11
5V_S5 DY
1

V5 PGND 2D2R5F-2-GP

2
GND 8A 17 12

2
VIN PGND
5V_S5 Pin19 direct PG4821

1
GAP-CLOSE-PWR-3-GP
Reserve PR4821 TPS51363RVER-GP

1PWR_1D05_SUNB
5V 12A connect to 16 13
for OCP setting thermal pad PC4819
VIN PGND

2
SC2D2U10V3KX-1GP

PW R_1D05V_VSNS
1

15 VIN PGND 14

GND
PWR_1D05V_GSNS
2

29 PC4820
SC330P50V3KX-GP
DY

2
B B

DCBATOUT +PW R_SRC_1D05V

PG4813
+PW R_SRC_1D05V
1 2

GAP-CLOSE-PW R-3-GP
PC4817 PC4827 PC4835 PC4824
PG4812
SC10U25V5KX-GP
1

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP

1 2
1

GAP-CLOSE-PW R-3-GP DY REFIN Voltage (V) Output Voltage (V)

2

PG4814 GND 1.05V

1 2

GAP-CLOSE-PW R-3-GP FLOAT 1.2V

PG4815 Resistor Divider

1 2 Adjustable between 0.6V to 2.0V

GAP-CLOSE-PW R-3-GP

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Title
Inductor:CHIP CHOKE 1.0UH ETQP3W1R0WFN / Panasonic/ 6.9mOhm / Isat =13Arms/ 68.1R01D.20H
O/P cap:CHIP CAP C 22U 6.3V M0805 X5R /78.22610.51L TPS51363 1D05V
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 48 of 101

5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p35v0p675v www.qdzbwx.com DCBATOUT

PG4903
1
+PW R_SRC_1D35V

GAP-CLOSE-PW R-3-GP
PG4904
1 2
PR4907 1 2 PW R_1D35V_EN
[17,24] PM_SLP_S4# 0R0402-PAD-2-GP GAP-CLOSE-PW R-3-GP 1D35V_PW R 1D35V_S3
PG4905

1
PC4906 1 2
SCD1U10V2KX-5GP PG4908
D
DY GAP-CLOSE-PW R-3-GP 1 2
D

2
PG4906
1 2 GAP-CLOSE-PW R-3-GP
PG4909
GAP-CLOSE-PW R-3-GP 1 2
PR4909 1 2 PG4921
[12] DDR_VTT_PG_CTRL 0R0402-PAD-2-GP GAP-CLOSE-PW R-3-GP
1 2
PG4910
GAP-CLOSE-PW R-3-GP 1 2
PR4910 1 2 0R2J-2-GP 0D675V_EN +PW R_SRC_1D35V PG4920
[17,24,36,48,51] PM_SLP_S3# DY 1 2 GAP-CLOSE-PW R-3-GP
5V_S5 PG4911
GAP-CLOSE-PW R-3-GP 1 2

PC4909

PC4911

PC4912

PC4913

PC4914
SC1U10V2KX-1GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP

SC4D7U25V5KX-GP
GAP-CLOSE-PW R-3-GP

1
PG4912

PC4901
1 2

1
0117 Add EC4901

2
GAP-CLOSE-PW R-3-GP

5
6
7
8
SIR172ADP-T1-GE3-GP
PG4913
[36] 1D35V_VTT_PW RGD

D
D
D
D
PU4902
1 2
EC4901
1

SCD1U25V2KX-GP

GAP-CLOSE-PW R-3-GP
PG4914
PU4901

G
4 1 2
DY
2

PR4605_2

S
S
S
20 12 PC4919
PGOOD V5IN SCD1U25V3KX-GP Design Current=13.52A GAP-CLOSE-PW R-3-GP

3
2
1
0D675V_EN 17 PR4905 PG4915
C VTTEN
15 PW R_1D35V_VBST
1 2 1 2
21.25A<OCP>25.11A 1 2 C
PW R_1D35V_EN VBST
16 EN/PSV 2D2R3-1-U-GP GAP-CLOSE-PW R-3-GP
PW R_1D35V_VREF 6 14 PW R_1D35V_DRVH PG4916
VREF DRVH
1

PL4902 1D35V_PW R 1 2
PR4903
10KR2F-2-GP 13 PW R_1D35V_SW 1 2 GAP-CLOSE-PW R-3-GP
SW PG4917
IND-D68UH-51-GP-U A00 0621 1 2

SCD1U10V2KX-5GP
SC4D7U6D3V5KX-3GP
2

5
6
7
8
PW R_1D35V_REFIN 8 11 PW R_1D35V_DRVL

GAP-CLOSE-PWR-3-GP

PC4921
REFIN DRVL

1
D
D
D
D
SIRA12DP-T1-GE3-GP

PT4903
SE330U2D5VM-14-GP
GAP-CLOSE-PW R-3-GP

PU4903

PC4920
1

1
PG4919

PG4907
10
DY

SCD1U50V3KX-GP
SCD1U10V2KX-4GP

SCD01U16V2KX-3GP

PW R_1D35V_MODE 19 PGND PR4912 1 2

DY

2
MODE
1

2D2R5F-2-GP
PC4903

200KR2F-L-GP

2
GAP-CLOSE-PW R-3-GP

G
PC4902

EC4601
4

2
1 PR4908 2

S
S
S
PW R_1D35V_TRIP 18 9 PW R_1D35V_VDDQS PG4918
2

TRIP VDDQS

PWR_1D35V_VDDQS
1 2
29K4R2F-GP

68K1R2F-1-GP

3
2
1
1

2 +0D675V_DDR_P TPS51216_PHS_SET
VTTIN
1

PW R_1D35V_VTTREF GAP-CLOSE-PW R-3-GP

PR4906

5 VTTREF

1
PG4922
PR4902

3
VTT DY
1

PC4918 PC4922 79.3371V.6CL 1 2

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SCD22U10V2KX-1GP SC330P50V2KX-3GP
PC4915

1
2

2
PC4916

PC4917
VTTS
1

21 GND 1 GAP-CLOSE-PW R-3-GP

2

4 DY PG4923
VTTGND
7 1 2
2

GND
TPS51216RUKR-GP GAP-CLOSE-PW R-3-GP
74.51216.073 1D35V_PW R
B B

PC4904
SC1U6D3V2KX-GP
1
+0D675V_DDR_P 0D675V_S0
PG4901
1 2 A00 0618 0D675V_VTTREF

2
GAP-CLOSE-PW R-3-GP PW R_1D35V_VTTREF 1 PR4911 2
PG4902 0R0603-PAD-2-GP-U
1 2

GAP-CLOSE-PW R-3-GP

State S3 S5 VDDR VTTREF VTT

S0 Hi Hi On On On
S3 Lo Hi On On Off(Hi-Z)
S4/S5 Lo Lo Off Off Off I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M/ 3.3mohm/ Isat =28A rms /68.1R01C.10Q
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L
A MODE <Core Design> A
H/S: SIR172ADP-T1-GE3 / 8.5mohm/10.5mOhm@4.5Vgs/ 84.00172.A37
PR4608 Frequency Discharge Mode L/S: SIRA12DP-T1-GE3 / 4.4mohm/6mOhm@4.5Vgs/ 84.SRA12.037
200k ohm 400kHz Wistron Corporation
Tracking Discharge 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
100k ohm 300kHz Taipei Hsien 221, Taiwan, R.O.C.

68k ohm 300kHz Title

Non-tracking Discharge TPS51216_+1.35V_SUS
47k ohm 400kHz
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 49 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)TPS51312 1D8V
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 50 of 101

5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v

D 3D3V_S5
TLV70215DBVR for 1D5V_S0 D

PC5103
SC1U6D3V2KX-GP
1
Design Current = 15mA

2
PU5101 1D5V_PW R 1D5V_S0
PG5101
1 IN OUT 5 1 2
2 GND
PW R_1D5V_EN 3 4 GAP-CLOSE-PW R
EN NC#4

PC5104
SC1U6D3V2KX-GP
1
TLV70215DBVR-GP

2
C C

[17,24,36,48,49] PM_SLP_S3# 2 1 PR5108 PW R_1D5V_EN

0R0402-PAD-2-GP

1
PC5101
SCD1U10V2KX-5GP
DY2

0108 Reserve PC5101

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT9198-15PU5R_1D5V
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 51 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO X02 change CAM1 connector

CAM1
LCD1 LCDVDD
Pin eDP LVDS Pin eDP LVDS 15
31 1
1 1 LCDVDD LCDVDD 16 NC LVDS_DATA2# 2 USB_CAMERA

1
2 C5201 C5203 EC5201 2 LCDVDD LCDVDD 17 NC LVDS_DATA2 3 USB_CAMERA#

SCD1U25V2KX-GP
SC4D7U6D3V3KX-GP
3 4 EL5201
DY 3D3V_CAMERA_S0

SCD1U10V2KX-5GP
4 3 LCDVDD LCDVDD 18 GND GND 5 DMIC_CLK_C 1 2 DMIC_CLK [27]

2
5 EDP_HP/LVDS_3D3V_ROM 6 BLM15AG221SN-GP
6 LCD_TST_C 4 LCDVDD LCDVDD 19 NC LVDS_CLK#_R 7 DMIC_DATA [27]
7 EDP_AUX/LVDS_DDC_CLK 8 68.00094.991
D 8 EDP_AUX#/LVDS_DDC_DAT 5 EDP_HP 3D3V_ROM 20 NC LVDS_CLK_R 9 TPAN_VDD D
9 10
10 EDP_TX0/LVDS_DATA0# 6 LCD_TST_C LCD_TST_C 21 GND GND 11 USB_PN6_TPNL
11 EDP_TX0/LVDS_DATA0 12 USB_PP6_TPNL
12
EDP_TX1/LVDS_DATA1#
7 EDP_AUX LVDS_DDC_CLK 22 GND GND 13
13 14 TOUCH_PANEL_INTR# [24]
14 EDP_TX1/LVDS_DATA1 8 EDP_AUX# LVDS_DDC_DAT 23 GND GND 16
15 USB_CAMERA 1 AFTP5202
16 LVDS_DATA2#_R LVDS_DATA2#_R [53] 9 GND GND 24 DBC_EN DBC_EN ACES-CON14-9-GP USB_CAMERA# 1 AFTP5203
17 LVDS_DATA2_R LVDS_DATA2_R [53] DMIC_CLK 1 AFTP5204 A00 0618
18 10 EDP_TX0N LVDS_DATA0# 25 BRIGHTNESS BRIGHTNESS DMIC_DATA 1 AFTP5205
19 LVDS_CLK#_R LVDS_CLK#_R [53] 3D3V_CAMERA_S0 1 AFTP5206
20 LVDS_CLK_R LVDS_CLK_R [53] 11 EDP_TX0P LVDS_DATA0 26 BLON_OUT BLON_OUT 0R0603-PAD-2-GP-U
21 USB_CAMERA# 2 R5225 1 USB_PN4 [16]
22 A00 0618 12 GND GND 27 Color_Engine Color_Engine
23 0R0402-PAD-2-GP
24
25
DBC_EN_R
LCD_BRIGHTNESS
1 R5224 2 DBC_EN [20] 13 EDP_TX1N LVDS_DATA1# 28 NC NC Camera Power CAMERA
26 BLON_OUT_C 14 EDP_TX1P LVDS_DATA1 29 DCBATOUT_LCD DCBATOUT_LCD
27 COLOR_ENGINE_CONN 1 DY 2 COLOR_ENGINE [20]
28 15 GND GND 30 DCBATOUT_LCD DCBATOUT_LCD 3D3V_CAMERA_S0
29 R5228
30
DCBATOUT_LCD
0R2J-2-GP 3D3V_S0 303mA
32

STAR-CON30-4-GP R5214 1 2 0R3J-0-U-GP

EC5202
SC1U6D3V2KX-GP
F5204 USB_CAMERA 2 1 USB_PP4 [16]
R5221

C5207
SC10U6D3V3MX-GP
1 2
DY

1
0R0603-PAD-2-GP-U
POLYSW-D5A6V-1-GP
DY DY DY
LVDS / EDP Colay Page 53 69.50007.921

2
SC10P50V2JN-4GP SC10P50V2JN-4GP

1
A00 0618
EC5206 EC5205
0R0402-PAD-2-GP PL Page 53.
C 1 R5222 2 eDP_BKLT_CTRL [53] C

2
RN5201 RN5204
D5202 LCD_TST_C 1 8 BKLT_CTRL 1 8
BKLT_CTRL 1 2 EC_BRIGHTNESS [24]
LCD_BRIGHTNESS 2 7 BKLT_CTRL
LCD_TST [24]
BLON_OUT_C 2 7 need close to connector
BLON_OUT_C 3 6 EDP_HPD 3 6
BLON_OUT [24]
4 5 4 5
CH751H-40PT-GP
SRN100J-4-GP
83.R0304.A8F EC (BIST MODE) SRN100KJ-5-GP

eDP/ LVDS select circuit

[53] EDP_TX0_DN_CON_L C5215 eDP 2

1 SCD1U10V2KX-5GP EDP_TX0/LVDS_DATA0#
LCDVDD
C5216 2 SCD1U10V2KX-5GP EDP_TX0/LVDS_DATA0 LCD Power
[53] EDP_TX0_DP_CON_L 1
eDP INVERTER POWER R5207
2 3
[53] LVDSA_DATA0#
[53] LVDSA_DATA0 1 LVDS 4 DCBATOUT 800mA DCBATOUT_LCD 1 eDP 2
RN5206 SRN0J-6-GP [15] EDP_VDD_EN
F5201 0R2J-2-GP
POLYSW-1D1A24V-GP-U
1 2 R5208 D5201
[53] EDP_TX1_DN_CON_L C5218 eDP 2
1 SCD1U10V2KX-5GP EDP_TX1/LVDS_DATA1# 1 DY 2 LCDPWR_EN 1
[53] LVDS_VDD_EN
C5217 2 SCD1U10V2KX-5GP EDP_TX1/LVDS_DATA1
[53] EDP_TX1_DP_CON_L 1 69.50007.A31

1
C5202 0R2J-2-GP 3 EN_LCDPWR
eDP 2nd = 69.50007.D31 C5205 eDP
3rd = 69.50007.A41 DY

SC1KP50V2KX-1GP
2 3 SCD1U50V3KX-GP 2
[53] LVDSA_DATA1# LVDS [24] LCD_TST_EN 600mA

2
[53] LVDSA_DATA1 1 4

1
RN5207 SRN0J-6-GP BAT54CPT-2-GP
R5209 3D3V_S0
3D3V_S0 75.00054.K7D eDP 100KR2J-1-GP
B B

U5201
eDP 2

2
[53] EDP_AUX_DN_CON_L C5219 1 SCD1U10V2KX-5GP EDP_AUX#/LVDS_DDC_DAT R5201 1 LVDS 2 0R3J-0-U-GP LCDVDD
[53] EDP_AUX_DP_CON_L C5220 1 2 SCD1U10V2KX-5GP EDP_AUX/LVDS_DDC_CLK 1 5
F5202 FUSE-2A32V-16-GP EN VIN#5
1 2 2
eDP DY 3
GNDeDP 4
RN5208 1 VOUT VIN#4
[53] LVDS_DDC_DATA_R 4 SRN0J-6-GP

1
[53] LVDS_DDC_CLK_R 2 LVDS 3 R5203 2 eDP 1 100R2J-2-GP EDP_HP/LVDS_3D3V_ROM C5204
[15,53] EDP_HPD
RT9724GB-GP
eDPSC4D7U6D3V3KX-GP

2
Layout Note: 74.09724.09F
Trace width = 80mil
LCDVDD
Touch panel A00 0618 0307 modify LVDS_VDD_EN 1 R5211 2
0R0603-PAD-2-GP-U 0R3J-0-U-GP
X02 remove TPNL1 USB_PN6_TPNL 2 R5223 1 USB_PN6 [16] 2136_LCDVDD
Layout Note:

1
R5202
5V_S0 TPAN_VDD Trace width = 80mil 1 R5212 2 2136_LCDVDD

100KR2J-1-GP
0R3J-0-U-GP
0R3J-0-U-GP 2136_LCDVDD
R5229

2
A00 0618 1 2

F5203
1 2
DY
POLYSW-D5A6V-1-GP

USB_PP6_TPNL 2 1 USB_PP6 [16]

69.50007.921
A R5220 A
0R0603-PAD-2-GP-U

<Core Design>
1

DY DYEC5203 A00 0618

TPAN_VDD 1 AFTP5210 EC5204
USB_PN6_TPNL 1 AFTP5208 SC10P50V2JN-4GP SC10P50V2JN-4GP
Wistron Corporation
2

USB_PP6_TPNL 1 AFTP5209
TOUCH_PANEL_INTR# 1 AFTP5207 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
need close to connector Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD Connector
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 52 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
LVDS & EDP Colay Layout Note:
Place near U5301
LVDS
LVDS
[8] EDP_TX1_DN C5209 1 2 SCD1U10V2KX-5GP EDP_TX1_DN_RTS2136
[8] EDP_TX1_DP C5210 1 2 SCD1U10V2KX-5GP EDP_TX1_DP_RTS2136

2 3 EDP_TX1_DN_CON_L
1 eDP 4 EDP_TX1_DP_CON_L EDP_TX1_DN_CON_L [52]
D RN5303 SRN0J-6-GP EDP_TX1_DP_CON_L [52] D
LVDS
LVDS
[8] EDP_TX0_DN C5211 1 2 SCD1U10V2KX-5GP EDP_TX0_DN_RTS2136
[8] EDP_TX0_DP C5212 1 2 SCD1U10V2KX-5GP EDP_TX0_DP_RTS2136

2 3 EDP_TX0_DN_CON_L
1 eDP 4 EDP_TX0_DP_CON_L EDP_TX0_DN_CON_L [52]
RN5302 SRN0J-6-GP EDP_TX0_DP_CON_L [52]
LVDS
LVDS
[8] EDP_AUX_DN C5213 1 2 SCD1U10V2KX-5GP EDP_AUX_DN_RTS2136
[8] EDP_AUX_DP C5214 1 2 SCD1U10V2KX-5GP EDP_AUX_DP_RTS2136

RN5304 1 4 SRN0J-6-GP EDP_AUX_DN_CON_L

EDP_AUX_DP_CON_L EDP_AUX_DN_CON_L [52]
2 eDP 3 EDP_AUX_DP_CON_L [52]

Brightness
R5319 1 LVDS 2 0R2J-2-GP 2136_PWM_IN
[15] L_BKLT_CTRL
R5320 1 eDP 2 0R2J-2-GP eDP_BKLT_CTRL
eDP_BKLT_CTRL [52]

R5302
1KR2J-1-GP
1 LVDS 2 EDP_HPD_RTS2136
[15,52] EDP_HPD

3D3V_S0 DP_AVCC33
C L5301 C

1 LVDS 2
MPZ1608S600AT-GP
68.00212.011
C5301
SC10U6D3V3MX-GP

C5303
1

SCD1U10V2KX-5GP

C5312
SCD1U10V2KX-5GP

LVDS LVDS DY SWR_V12 SCD1U10V2KX-5GP

2

3D3V_S0
[24] LVDS_R2136_BKLT_EN C5311
LVDS_DDC_DATA_R
[52] LVDS_DDC_DATA_R
LVDS_DDC_CLK_R 1DY 2
[52] LVDS_DDC_CLK_R
EEPROM_SDA0 LVDSA_DATA0# [52]
EEPROM_SCL0 LVDSA_DATA0 [52] R5306 R5317

1
X02 change to 4P2R LVDSA_DATA1# [52]

4K7R2J-2-GP

4K7R2J-2-GP
LVDSA_DATA1 [52]
RN5306 LVDS_DATA2#_R [52] LVDS DY
1 4 TEST_MODE LVDS_DATA2_R [52]
2 LVDS 3 2136_PWM_IN

2
3D3V_S0 DP_DVCC33 EEPROM_SCL0
L5302
LVDS EEPROM_SDA0

49

48
47
46
45
44
43
42
41
40
39
38
37
1 2 SRN100KJ-6-GP U5301

1
MPZ1608S600AT-GP R5318 R5307

MIICSDA

VCCK
GND

BL_EN
MODE_CFG1
MODE_CFG0
MIICSCL

TXO0-
TXO0+
TXO1-
TXO1+
TXO2-
TXO2+
68.00212.011 LVDS
C5302

4K7R2J-2-GP

4K7R2J-2-GP
SC10U6D3V3MX-GP

DY
1

C5313
LVDS DY DY SCD1U10V2KX-5GP

2
C5317
2

2
SCD1U10V2KX-5GP

EDP_HPD_RTS2136 1 36 LVDS_CLK#_R [52]

TEST_MODE HPD TXOC-
2 35 LVDS_CLK_R [52]
EDP_AUX_DN_RTS2136 TEST TXOC+
3 34
EDP_AUX_DP_RTS2136 AUX_N TXO3-
4 33
DP_AVCC33 AUX_P TXO3+
5 32
DP_V33 TXE0-
6
DP_GND TXE0+
31 Operation Mode Table
EDP_TX0_DP_RTS2136 7 30
B
EDP_TX0_DN_RTS2136 LANE0_P TXE1- B

EDP_TX1_DP_RTS2136
8
LANE0_N LVDS TXE1+
29
9
LANE1_P TXE2-
28 PIN47
L5303 EDP_TX1_DN_RTS2136 10 27
IND-4D7UH-300-GP SWR_V12 LANE1_N TXE2+
11
DP_V12 TXEC-
26 0 1
SWR_LX 1 2 SWR_V12 Close to PIN5 DP_REXT 12 25
DP_REXT TXEC+
2136_SW 0 X EP Mode

PANEL_VCC
PIN48

SWR_VCCK
1

SWR_GND

PWM_OUT
C5305
SC10U6D3V3MX-GP

SWR_VDD
A00 0618 DP_AVCC33 C5310 1 ROM EEPOOM

SWR_LX
1

CIICSDA

PWM_IN
CIICSCL
SCD1U10V2KX-5GP

R5301

TXE3+
TXE3-
PVCC
0R0603-PAD-2-GP-U LVDS C5306 LVDS LVDS 12KR2F-L-GP
SCD1U10V2KX-5GP

1 R5314 2 LVDS
2

2
1

C5316 RTD2136R-CGT-GP
LVDSSCD1U10V2KX-5GP

13
14
15
16
17
18
19
20
21
22
23
24
71.02136.B03
2

DP_DVCC33
SWR_V12

CIICSCL1 SWR_LX
CIICSDA1

1
C5309
LVDSSCD1U10V2KX-5GP

2
[52] eDP_BKLT_CTRL
3D3V_S0 [52] LVDS_VDD_EN
RN5301
3D3V_S0 1 8 LVDS_DDC_DATA_R 2136_PWM_IN
2 7 LVDS_DDC_CLK_R
DP_DVCC33
3 LVDS 6
4 5

SRN4K7J-10-GP
1

RN5307 C5308 C5307

PCH
SC10U6D3V3MX-GP

A Q5301 A
1 4 SML0_DATA [18] LVDS LVDS
SCD1U10V2KX-5GP

CIICSDA1 CIICSDA DY
1 6 2 3 SML0_CLK [18]
PCH
2

LVDS Close to PIN13 <Core Design>

2 5 SRN0J-6-GP
RN5305
3 4 1 4 KBC
2N7002KDW-GP
2 LVDS 3
BAT_SDA [24,43,44]
BAT_SCL [24,43,44]
KBC Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SRN0J-6-GP Taipei Hsien 221, Taiwan, R.O.C.
84.2N702.A3F
2nd = 84.DM601.03F CIICSCL Title
3rd = 84.2N702.E3F
CIICSCL1 4th = 84.2N702.F3F LVDS_Switch
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 53 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
5V_S0 HDMI_CLK_R_C
0R3J-0-U-GP
R5401
1 2

HDMI_CLK_R_C_CON
www.qdzbwx.com HDMI_DATA2_R_C
0R3J-0-U-GP
R5405
1 2

HDMI_DATA2_R_C_CON

0307 change RN5401 RN5402 form A00 0619 A00 0619

1
5V_S0 5V_HDMI_S0 U5401
G
680 ohm to 470 ohm ER5401 ER5403
F5401 A00 0618 150R2J-L1-GP-U A00 0618 150R2J-L1-GP-U
1 2 D HDMI_PLL_GND
D D

2
S
POLYSW -1D1A8V-5-GP
2N7002K-2-GP
84.2N702.J31

1
2
3
4

1
2
3
4
HDMI_CLK_R_C# HDMI_CLK_R_C#_CON HDMI_DATA2_R_C# HDMI_DATA2_R_C#_CON
RN5402 RN5401
SRN470J-5-GP SRN470J-5-GP 1 2 1 2

R5402 R5406
0R3J-0-U-GP ER5401~04 change to 180R 0R3J-0-U-GP

8
7
6
5

8
7
6
5
0R3J-0-U-GP 0R3J-0-U-GP
R5403 R5407
C5401 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C# 1 2 1 2
[8] HDMI_CLK# C5402 SCD1U10V2KX-5GP HDMI_CLK_R_C
[8] HDMI_CLK 1 2
HDMI_DATA0_R_C HDMI_DATA0_R_C_CON HDMI_DATA1_R_C HDMI_DATA1_R_C_CON
C5403 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C#
[8] HDMI_DATA0# C5404 SCD1U10V2KX-5GP HDMI_DATA0_R_C
[8] HDMI_DATA0 1 2
A00 0619 A00 0619

1
ER5402 ER5404
A00 0618 150R2J-L1-GP-U A00 0618 150R2J-L1-GP-U
C5405 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C#
[8] HDMI_DATA1# C5406 SCD1U10V2KX-5GP HDMI_DATA1_R_C
1 2

2
[8] HDMI_DATA1
C5407 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C#
[8] HDMI_DATA2# C5408 SCD1U10V2KX-5GP HDMI_DATA2_R_C
[8] HDMI_DATA2 1 2
C C
HDMI_DATA0_R_C# HDMI_DATA0_R_C#_CON HDMI_DATA1_R_C# HDMI_DATA1_R_C#_CON

1 2 1 2

R5404 R5408
5V_HDMI_S0 0R3J-0-U-GP 0R3J-0-U-GP

3 D5401
BAW 56-11-GP
HDMI CONN
75.00056.B7D
2nd = 75.00056.A7D
2

HDMI1
D5102_2

D5102_1

22
20

HDMI_DATA2_R_C_CON 1
4
3

2
HDMI_DATA2_R_C#_CON 3
3D3V_S0 RN5203 HDMI_DATA1_R_C_CON 4
SRN2K2J-1-GP 5
HDMI_DATA1_R_C#_CON 6
HDMI_DATA0_R_C_CON 7
1
2

B B
8
HDMI_DATA0_R_C#_CON 9
[15] PCH_HDMI_CLK 4 3 DDC_CLK_HDMI HDMI_CLK_R_C_CON 10
11
5 2 HDMI_CLK_R_C#_CON 12
13
[15] PCH_HDMI_DATA 6 1 DDC_DATA_HDMI 14
DDC_CLK_HDMI 15
Q5401 5V_HDMI_S0 DDC_DATA_HDMI 16
2N7002KDW -GP 17
84.2N702.A3F AFTP5401 1 18
1 HPD_HDMI_CON 19

1
C5417 TP5411
SCD1U10V2KX-5GP 21
23

2
SKT-HDMI23-97-GP
3D3V_S0
22.10296.A31

PMBS3904-1-GP 1HDMI_HPD_B 1 R5411 2

Q5402
84.03904.L06 150KR2J-L1-GP
2

<Core Design>
A [15] HDMI_PCH_DET 1 2 HDMI_HPD_E A

1
R5413
1

0R0402-PAD-2-GP DY R5412
R5414 20KR2J-L2-GP Wistron Corporation
10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2
2

Title

HDMI Repeater/Connector
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 54 of 101

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Reserved Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 55 of 101
5 4 3 2 1
SSID = SATA

5V_S0

HDD CONN

SC10U6D3V3MX-GP
C5602
1

1
C5603
DY SCD1U10V2KX-5GP A00 0618 20.F2036.020

2
ACES-CON20-28-GP
0R0402-PAD-2-GP 24
[20] HDD_DEVSLP 1 R5602 2 HDD_DEVSLP_R 20
19 23
18
17
5V_S0 16
15
14
Need to check conn pin define 13
0R0402-PAD-2-GP 12
[67] FFS_INT2_Q 1 R5614 2 FFS_INT2_Q_R 11
10
9
8
7
SATA3_DRX_CTX_P0 C5601 1 2 SCD01U16V2KX-3GP SATA3_DRX_CTX_P0_C 6
SATA3_DRX_CTX_N0 C5604 1 2 SCD01U16V2KX-3GP SATA3_DRX_CTX_N0_C 5
4
SATA3_DTX_CRX_N0 C5606 2 1 SCD01U16V2KX-3GP SATA3_DTX_CRX_N0_C 3
SATA3_DTX_CRX_P0 C5605 2 1 SCD01U16V2KX-3GP SATA3_DTX_CRX_P0_C 2
22
1
21
Layout Note:
AC coupling Cap; HDD1
place near CONN(<100mils)

3D3V_S0
SC1U6D3V2KX-GP
C5613

SC1U6D3V2KX-GP
C5612

SC1U6D3V2KX-GP
C5611
1

HDD Re-driver
2

C5607 SCD01U16V2KX-3GP
1 2 SATA3_PRX_DTX_P0 [19]
C5609 SCD01U16V2KX-3GP U5601 1 2 SATA3_PRX_DTX_N0 [19]
[19] SATA3_PTX_DRX_P0 1 2 C5608 SCD01U16V2KX-3GP
[19] SATA3_PTX_DRX_N0 1 2 10 15 SATA3_DTX_CRX_P0
C5610 SCD01U16V2KX-3GP VCC TX1P SATA3_DTX_CRX_N0
20 VCC TX1N 14
3D3V_S0 5 SATA3_PRX_DTX_P0_L 3D3V_S0
TX2P SATA3_PRX_DTX_N0_L
TX2N 4
SATA3_PTX_DRX_P0_R 1 RX1P
1

1
SATA3_PTX_DRX_N0_R 2 17 SATA3_EQ1_HDD
R5601 SATA3_DRX_CTX_P0 RX1N EQ1 SATA3_EQ2_HDD R5603
11 RX2P EQ2 19
SATA3_DRX_CTX_N0 3D3V_S0
10KR2J-3-GP
DY 12 RX2N
7 3D3V_S0
DY 10KR2J-3-GP
EN
2

2
1
SATA3_DE1_HDD 9
SATA3_DE2_HDD DE1 R5604
8 DE2 GND 3
1

3D3V_S0
R5605 3D3V_S0 HDD_DEW 1 GND 13
DY 10KR2J-3-GP
DY 16 DEW1 GND 18

1
10KR2J-3-GP HDD_DEW 2 6 21

2
DEW2 GND
1

R5607
R5606
DY DY 10KR2J-3-GP
2

10KR2J-3-GP
R5611

2
4K7R2J-2-GP 3D3V_S0 SN75LVCP601RTJR-GP 1
DY
2

71.75601.003 R5608
DY 10KR2J-3-GP
2
1

R5609 R5613
1

4K7R2J-2-GP
10KR2J-3-GP
DY R5610 DY
4K7R2J-2-GP
2

2
2

R5612
4K7R2J-2-GP
2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
HDD
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 56 of 101
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 57 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless

D D

0311 modify power rail

3D3V_W LAN_AOAC

1
R5809
10KR2J-3-GP WLAN CONN
WLAN1

2
54
1.1A NP1
[24] W IFI_W AKE# 1
3D3V_S0 3D3V_W LAN_AOAC 2

3D3V_S5 TP5802 1 WLAN_ACT 3

R5806 4
0R3J-0-U-GP TP5803 1 BT_ACT 5
1 2 6
7
NON AOAC [18] CLK_PCIE_W LAN_REQ3#
8
2

C5804 9
SC1U6D3V2KX-GP

10
AOAC [18] CLK_PCIE_W LAN_N3 11
1

C 12 C
U5801 [18] CLK_PCIE_W LAN_P3 13
14
1 AOAC 8 15
GND OUT#8
2 IN#2 OUT#7 7 16
3 6 TP5801 1 E51_RxD_R 17
IN#3 OUT#6
[24] AOAC_W LAN_EN 4 EN/EN# OCB 5 18
R5803 1 2 0R2J-2-GP E51_TxD_R 19
1210 Low Active change to High Active
[24] E51_TxD
[24] W IFI_RF_EN
DY 20
1

SY6288CCAC-GP A00 0618 0R0402-PAD-2-GP 21

(Need to confirm with the SW)
100KR2J-1-GP
R5808

1 R5804 2 WLAN_22 22
DY 74.06288.079 [17,24,30,65,73] PLT_RST#
[16] PCIE_PRX_W LANTX_N3 23
24
[16] PCIE_PRX_W LANTX_P3 25
2

26
27
28
29
[12,13,18,62,67] PCH_SMBCLK 30
[16] PCIE_PTX_W LANRX_N3_C 31
[12,13,18,62,67] PCH_SMBDATA 32
[16] PCIE_PTX_W LANRX_P3_C 33
34
35
A00 0618 USB_PN5_R 36
USB_PN5_R R5801 1 2 0R0603-PAD-2-GP-U USB_PN5 [16] 37
3D3V_W LAN_AOAC USB_PP5_R 38
39
40
B B
41
42
43
SC10U6D3V3MX-GP
C5801

44
1

1
A00 0618 5V_S5 10KR2J-3-GP 45
C5806 C5805 R5807 46
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP 1 2 47
DY
2

2 48
49
50
A00 0618 [20] BLUETOOTH_EN 51
USB_PP5_R R5805 1 2 0R0603-PAD-2-GP-U USB_PP5 [16] 52
NP2
53

MINIPCI52P-8-GP-U1
62.10043.B91

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

WLAN/BT
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 58 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 59 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 60 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
PWRBTN CONN

PW BT1
5
D D
Battery LED1(Amber_LED) 3D3V_S5 1
RN6101
LOW actived from KBC GPIO 1 4 KBC_PW RBTN#_C 2
[24] KBC_PW RBTN#
[24] LID_CLOSE# 2 3 LID_CLOSE#_C 3
4
SRN100J-3-GP
6
5V_S5
Q6104 ACES-CON4-50-GP
R2
E
CHG_AMBER_LED#_R B R1
20.K0722.004
C LED_BAT 1 2 BAT_AMBER_LED_A

SC220P50V2KX-3GP
PDTA144VT-GP R6107

EC6104

1
84.00144.P11 680R2J-3-GP
2nd = 84.DT144.A11 DY

2
3D3V_S5 1 AFTP6101
KBC_PW RBTN#_C 1 AFTP6102
LID_CLOSE#_C 1 AFTP6107

Power & Battery LED2(White_LED)

LOW actived from KBC GPIO
C C

5V_S5
Q6103
R2
E
PW RLED#_R B R1
RN6102 C LED_BATCHG 1 2 BAT_W HITE_LED_A
0R8P4R-PAD-1-GP
RN PDTA144VT-GP R6106

SC220P50V2KX-3GP
1
CHG_AMBER_LED#_R 680R2J-3-GP

EC6103
[24] CHG_AMBER_LED# 1 8 84.00144.P11
2 7 PW RLED#_R 2nd = 84.DT144.A11
[24] PW RLED#
3 6 SATA_LED#_R DY LED board CONN

2
[19] SATA_LED#
4 5

LEDBD1
5

BAT_W HITE_LED_A 1

BAT_AMBER_LED_A 2
HDD_LED_A 3
4

6
SATA HDD LED
ACES-CON4-50-GP
B 20.K0722.004 B

5V_S0
Q6105
R2
E BAT_W HITE_LED_A 1 AFTP6103
SATA_LED#_R B BAT_AMBER_LED_A 1 AFTP6104
R1
C SATA_LED_R 1 2 HDD_LED_A GND 1 AFTP6105
HDD_LED_A 1 AFTP6106
1

PDTA144VT-GP R6108
EC6105
SC220P50V2KX-3GP

84.00144.P11 680R2J-3-GP
2nd = 84.DT144.A11 DY
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Bar/Power Button

Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 61 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = KBC SSID = Touch.Pad

Internal Keyboard Connector
3D3V_S0 X01 0321
TP_VDD
R6209
AFTP6201 1 KB1 1 2
D 31 D
[20] KB_DET# 1 0R0603-PAD-2-GP-U
AFTP6202 1 KROW 7 2
AFTP6203 1 KROW 6 3 Touch Pad Connector
AFTP6204 1 KROW 4 4
AFTP6205 1 KROW 2 5 TP_VDD
AFTP6206 1 KROW 5 6 TP_VDD
AFTP6207 1 KROW 1 7
AFTP6208 1 KROW 3 8

SCD1U10V2KX-5GP
[24] KROW [0..7]
AFTP6209 KROW 0

C6201
1 9
AFTP6210 1 KCOL5 10

1
[24] KCOL[0..16] AFTP6211 1 KCOL4 11

1
2
AFTP6212 1 KCOL7 12 RN6201
AFTP6213 1 KCOL6 13

2
AFTP6215 1 KCOL8 14 20.K0721.006
AFTP6216 1 KCOL3 15 ACES-CON6-52-GP
AFTP6217 1 KCOL1 16 SRN10KJ-5-GP
AFTP6218 1 KCOL2 17 8

4
3
AFTP6219 1 KCOL0 18
AFTP6220 1 KCOL12 19 SRN33J-5-GP-U 6
AFTP6221 1 KCOL16 20 [24] TPCLK 1 4 TPCLK_C 5
AFTP6222 1 KCOL15 21 [24] TPDATA 2 3 TPDATA_C 4
AFTP6223 1 KCOL13 22 3

EC6202
SC33P50V2JN-3GP
AFTP6225 1 KCOL14 23 RN6202 [12,13,18,58,67] PCH_SMBCLK 2

1
AFTP6224 1 KCOL9 24
AFTP6226 1 KCOL11 25 EC6201 1
AFTP6227 1 KCOL10 26 SC33P50V2JN-3GP DY DY [12,13,18,58,67] PCH_SMBDATA

2
CAP_LED CAP_LED 27 7
C AFTP6238 1 28 C
29 TP1
AFTP6228 1 30
32 AFTP6214 1

ACES-CON30-10-GP
20.K0592.030
CAP LED Control
LOW actived from KBC GPIO
5V_S0 CAP_LED
A00 0618 Q6201
R2
E TP_VDD 1 AFTP6229
[24] CAP_LED# 1 R6202 2 CAP_LED_R# B R1
R6201 TPCLK_C 1 AFTP6230
0R0402-PAD-2-GP C CAP_LED_Q 1 2 CAP_LED TPDATA_C 1 AFTP6231
PCH_SMBCLK 1 AFTP6232
PDTA144VT-GP 1KR2J-1-GP PCH_SMBDATA 1 AFTP6233
84.00144.P11
2nd = 84.DT144.A11

B 5V_S0 +5V_KB_BL B

F6201
1 2
DY
1

POLYSW -D5A6V-1-GP C6202

SCD1U10V2KX-5GP
69.50007.921
1 2
2

R6205 0R3J-0-U-GP KBLIT1

5

1
R6206
1 2 KB_LED_DET_C 2
[20] KB_LED_BL_DET
3
1

51KR2J-1-GP 4
1

C6203
KB_BL_CTRL#
SCD1U10V2KX-5GP

R6207 6
100KR2J-1-GP DY
2
2

ACES-CON4-50-GP 1
20.K0722.004 AFTP6234
D

Q6202
P8503BMG-GP
[24] KB_BL_CTRL G
A <Core Design> A
1

84.P8503.031
S

R6208 2nd = 84.03404.C31

DY 100KR2J-1-GP
+5V_KB_BL 1 Wistron Corporation
KB_LED_DET_C 1 AFTP6235 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

KB_BL_CTRL# 1 AFTP6236 Taipei Hsien 221, Taiwan, R.O.C.

AFTP6237
Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 62 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

A00 0618

USB30_VCCC USB30_VCCD 3D3V_S0

IOBD1
41 USB20_DN2_C USB_PN2 [16]

EC6301
SCD1U10V2KX-5GP

EC6302
SCD1U10V2KX-5GP

EC6303
SCD1U10V2KX-5GP
1 USB30_VCCC

1
2
3
DY DY DY

2
4
5 USB30_VCCD 1 2
6
7 4 3 69.10080.021
8 2nd = 69.10103.061
9 3D3V_S0 TR6301
C 10 FILTER-4P-62-GP C
11
12
13 USB20_DP2_C USB_PP2 [16]
14
15 USB20_DN3_C
16 USB20_DP3_C
17 A00 0618
18 USB20_DN2_C
19 USB20_DP2_C
20
21 USB3_PRX_DTX_N3 [16] USB20_DN3_C USB_PN3 [16]
22 USB3_PRX_DTX_P3 [16]
23
24 USB3_PTX_DRX_N3 [16]
25 USB3_PTX_DRX_P3 [16]
26
27 USB3_PRX_DTX_N2 [16]
28 USB3_PRX_DTX_P2 [16] 1 2
29
30 USB3_PTX_DRX_N2 [16] 4 3 69.10080.021
31 USB3_PTX_DRX_P2 [16] A00 0628 2nd = 69.10103.061
32 TR6302
33 SATA3_PTX_DRX_N1_R C6002 1 DY2 SCD01U16V2KX-3GP SATA3_PTX_DRX_N1 [19] FILTER-4P-62-GP
34 SATA3_PTX_DRX_P1_R 1
35 C6013 DY2 SCD01U16V2KX-3GP
SATA3_PTX_DRX_P1 [19]
36 SATA3_PRX_DTX_N1_R C6012 1 SCD01U16V2KX-3GP USB20_DP3_C
37 SATA3_PRX_DTX_P1_R 1
DY22 SATA3_PRX_DTX_N1 [19] USB_PP3 [16]

38 C6001 DY SCD01U16V2KX-3GP
SATA3_PRX_DTX_P1 [19]
MSATA_DEVSLP [20]
B B
39 MSATA_DET# [19]
40

42

ACES-CON40-18-GP
20.K0678.040

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

IO Board Connector Rev
A3 Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 63 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 64 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

Debug Connector
A00 0625
D D

Place near trace separated point 3D3V_S0

DB1
RN6501 11
LPC_AD[3..0] 0R8P4R-PAD-1-GP 1
[18,24] LPC_AD[3..0]
RN
LPC_AD0 1 8 LPC_LAD0_R 2
LPC_AD1 2 7 LPC_LAD1_R 3
LPC_AD2 3 6 LPC_LAD2_R 4
LPC
LPC_AD3 4 5 LPC_LAD3_R 5
LPC_FRAME#_DEBUG 6
0R0402-PAD-2-GP 1 R6501 2 PLT_RST#_DEBUG 7
[18,24] LPC_FRAME#
[17,24,30,58,73] PLT_RST# 0R0402-PAD-2-GP 1 R6502 2 8
[18] CLK_PCI_LPC 9
10
12

PAD-10P-177042-GP

ZZ.00PAD.Y41

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 65 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

B
(Blanking) B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 66 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

Note:
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
Free Fall Sensor A00 0618
3D3V_S0 - mount the sensor near the center of mass of the NB as possible as you can

0R0603-PAD-2-GP-U
3D3V_RUN_FFS 1 R6701 2
C C
U6701

C6703
SCD1U16V2KX-3GP

C6702
SCD1U16V2KX-3GP

C6701
SC10U6D3V3MX-GP
10 RES#10 VDD_IO 1

1
13 RES#13
15 RES#15 VDD 14 FFS FFS DY
16

2
RES#16 3D3V_S0
[12,13,18,58,62] PCH_SMBCLK 4 SCL/SPC INT1 11
6 9 HDD_FALL_INT
[12,13,18,58,62] PCH_SMBDATA SDA/SDI/SDO INT2 HDD_FALL_INT [15]

1
3D3V_RUN_FFS 7 8 R6703
SDO/SA0 CS 100KR2J-1-GP
Need to check GPIO FFS
FFS
5 2

2
GND NC#2 FALL_INT2
12 GND NC#3 3

LNG3DMTR-GP
Q6701
74.LNG3D.0BZ

1
2N7002KDW -GP
84.2N702.A3F
2nd = 84.DM601.03F FFS
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

6
B B

FFS_INT2
FFS_INT2_Q [56]

Note: Need to check conn pin define

(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom. FFS_INT2 [20]

Need to check GPIO

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

FFS
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 67 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 68 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 69 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 70 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 71 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 72 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO dGPU Reset

D7301
[17,24,30,58,65] PLT_RST# K OPS A VGA_RST# [76]
1SS400GPT-GP
83.00400.C1F 1D05V_VGA_S0

2ND = 83.27101.01F
3RD = 83.01426.01F
A00 0618 0R0402-PAD-2-GP
[15] DGPU_HOLD_RST# 1 R7304 2

D D

1
3D3V_VGA_S0 OPS OPS OPS OPS OPS
GPU1A 1 OF 17
OPS C7313OPS C7325

2
C7323 C7310 C7322 C7312 C7326
1/17 PCI_EXPRESS

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
2
GK107/GF108
Q7301
R7308 GK208/GF117

G OPS10KR2J-3-GP AJ11
PEX_WAKE# NC
AG19
VGA_RST# PEX_IOVDD_1
[18] PEG_CLKREQ# D AJ12 AG21

1
PEX_RST# PEX_IOVDD_2
PEX_IOVDD_3 AG22
OPS S GPU_CLKREQ# AK12 AG24
PEX_CLKREQ# PEX_IOVDD_4
AL13
PEX_IOVDD_5 AH21
AH25
1.05V +/- 30mV
2N7002K-2-GP [18] CLK_PCIE_VGA PEX_REFCLK PEX_IOVDD_6
84.2N702.J31 [18] CLK_PCIE_VGA# AK13 PEX_REFCLK# 3.3A
[16] CPU_RXP_C_dGPU_TXP0 C7301 1OPS2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP0 AK14
C7302 1OPS2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN0 PEX_TX0 1D05V_VGA_S0
[16] CPU_RXN_C_dGPU_TXN0 AJ14 PEX_TX0#
1 DY 2 [16] dGPU_RXP_C_CPU_TXP0 AN12 PEX_RX0
[16] dGPU_RXN_C_CPU_TXN0 AM12 PEX_RX0# PEX_IOVDDQ_1 AG13
R7305 AG15
0R2J-2-GP C7303 1OPS2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP1 PEX_IOVDDQ_2
[16] CPU_RXP_C_dGPU_TXP1 AH14 PEX_TX1 PEX_IOVDDQ_3 AG16
[16] CPU_RXN_C_dGPU_TXN1 C7304 1OPS2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN1 AG14 AG18
PEX_TX1# PEX_IOVDDQ_4
PEX_IOVDDQ_5 AG25

1
[16] dGPU_RXP_C_CPU_TXP1 AN14 PEX_RX1 PEX_IOVDDQ_6 AH15 OPS OPS OPS
[16] dGPU_RXN_C_CPU_TXN1 AM14 PEX_RX1# PEX_IOVDDQ_7 AH18 OPS OPS
AH26 OPS C7314OPS C7327

2
C7305 1OPS2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP2 PEX_IOVDDQ_8 C7320 C7321 C7309 C7311 C7328
[16] CPU_RXP_C_dGPU_TXP2 AK15 PEX_TX2 PEX_IOVDDQ_9 AH27

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP
[16] CPU_RXN_C_dGPU_TXN2 C7306 1OPS2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN2 AJ15 AJ27
PEX_TX2# PEX_IOVDDQ_10
PEX_IOVDDQ_11 AK27
[16] dGPU_RXP_C_CPU_TXP2 AP14 PEX_RX2 PEX_IOVDDQ_12 AL27
C [16] dGPU_RXN_C_CPU_TXN2 AP15 PEX_RX2# PEX_IOVDDQ_13 AM28 C
PEX_IOVDDQ_14 AN28
[16] CPU_RXP_C_dGPU_TXP3 C7307 1OPS2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP3 AL16
C7308 1OPS2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN3 PEX_TX3
[16] CPU_RXN_C_dGPU_TXN3 AK16 PEX_TX3#
[16] dGPU_RXP_C_CPU_TXP3 AN15 PEX_RX3
[16] dGPU_RXN_C_CPU_TXN3 AM15 PEX_RX3#
AK17
PEX_TX4
AJ17
PEX_TX4#
AN17
PEX_RX4
AM17
PEX_RX4#
AH17
3.3V +/- 5%
PEX_TX5 GF108 GK208/GK107/GF117
AG17
PEX_TX5#
AH12
210mA
NC PEX_PLL_HVDD 3D3V_VGA_S0
AP17
PEX_RX5
AP18 AG12
PEX_RX5# PEX_SVDD_3V3
AK18
PEX_TX6
AJ18
PEX_TX6#

1
C7316 C7315 C7324

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AN18
PEX_RX6 OPS OPS OPS
AM18

2
PEX_RX6#
AL19
PEX_TX7
AK19
PEX_TX7#
AN20
AM20
PEX_RX7
PEX_RX7#
X7R, Under GPU.
AK20
PEX_TX8
AJ20
PEX_TX8#
L4 VGA_SENSE [82]
B VDD_SENSE B
AP20
AP21
PEX_RX8
PEX_RX8#
POWER IC
L5 GND_SENSE [82]
GND_SENSE
AH20
PEX_TX9
AG20
PEX_TX9#
AN21
PEX_RX9
AM21
PEX_RX9#
AK21
PEX_TX10
AJ21
PEX_TX10#
P8
NC_3V3AUX
AN23
PEX_RX10
AM23
PEX_RX10#
AL22
PEX_TX11
AK22
PEX_TX11#
AP23 R7303
PEX_RX11 200R2F-L-GP
AP24
PEX_RX11#
AJ26 PEXTSTCLK_OUT 1 DY 2
1.05V +/- 30mV
PEX_TSTCLK_OUT
AK23 AK26 PEXTSTCLK_OUT# 150mA
PEX_TX12 PEX_TSTCLK_OUT#
AJ23
PEX_TX12#
PEX LANES 8 TO 15 NC FOR GF117/GK208

AN24
PEX_RX12 1D05V_VGA_S0
AM24
PEX_RX12#
AH23
PEX_TX13
AG23 AG26
PEX_TX13# PEX_PLLVDD
AN26
AM26
PEX_RX13
PEX_RX13#
0102 remove R7307

1
C7318 C7317 C7319

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP
AK24 R7302 OPS OPS
PEX_TX14
AJ24 AK11 TESTMODE 1 OPS 2
A
OPS A

2
PEX_TX14# TESTMODE 10KR2J-3-GP
AP26 PEX_RX14
AP27 PEX_RX14# <Core Design>

AL25 PEX_TX15
AK25 PEX_TX15# OPS R7301 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AN27 PEX_RX15 PEX_TERMP AP29 PEX_TERMP 1 OPS 2
2K49R2F-GP Taipei Hsien 221, Taiwan, R.O.C.
AM27 PEX_RX15#
Title
N14P-GS-A1-GP
71.0N14P.00U
GPU_PCIE/STRAPPING(1/5)
Size Document Number Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 73 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
GPU1J 10 OF 17
5/17 IFPAB GPU1K 11 OF 17
6/17 IFPC
ALL PINS NC FOR GF117

DP(GK208) LVDS ALL PINS NC FOR GF117

DPA_L3 IFPA_TXC# AN6
DPA_L3 IFPA_TXC AM6 AF8 IFPC_RSET
D AJ8 DVI/HDMI DP D
IFPAB_RSET

DPA_L2 IFPA_TXD0# AN3

AP3 TP7406 1 IFPC_PLLVDD AF7 I2CW_SDA AG2
DPA_L2 IFPA_TXD0 IFPC_PLLVDD IFPC_AUX_I2CW_SDA#
I2CW_SCL IFPC_AUX_I2CW_SCL AG3
TP7401 1 IFPAB_PLLVDD AH8
IFPAB_PLLVDD
DPA_L1 AM5
IFPA_TXD1#
DPA_L1 AN5 TXC AG4
IFPA_TXD1 IFPC_L3#
TXC AG5
IFPC_L3

DPA_L0 AK6 AH4

IFPA_TXD2# TXD0 IFPC_L2#
DPA_L0 IFPA_TXD2
AL6 IFPC TXD0 IFPC_L2
AH3

TXD1 IFPC_L1# AJ2

IFPA_TXD3# AH6 TXD1 IFPC_L1 AJ3
IFPA_TXD3 AJ6
TXD2 IFPC_L0# AJ1
TXD2 IFPC_L0 AK1
DPB_L3 IFPB_TXC# AH9
DPB_L3 IFPB_TXC AJ9

TP7402 1 IFPA_IOVDD AG8 TP7407 1 IFPC_IOVDD AF6 P2

IFPA_IOVDD IFPC_IOVDD GPIO15
DPB_L2 IFPB_TXD4# AP5
TP7403 1 IFPB_IOVDD AG9 DPB_L2 AP6
IFPB_IOVDD IFPB_TXD4 N14P-GS-A1-GP

DPB_L1 IFPB_TXD5# AL7 71.0N14P.00U

DPB_L1 IFPB_TXD5 AM7

OPS
DPB_L0 IFPB_TXD6# AM8
DPB_L0 IFPB_TXD6 AN8

C
IFPB_TXD7# AL8 C
IFPB_TXD7 AK8

GPU1M 13 OF 17
GPIO14 N4 8/17 IFPEF
IFPAB
N14P-GS-A1-GP ALL PINS NC FOR GF117

71.0N14P.00U DVI-DL DVI-SL/HDMI DP

OPS
I2CY_SDA I2CY_SDA AB4
IFPE_AUX_I2CY_SDA#
I2CY_SCL I2CY_SCL AB3
TP7408 IFPEF_PLLVDD IFPE_AUX_I2CY_SCL
1 AB8
IFPEF_PLLVDD

TXC TXC AC5

IFPE_L3#
AD6 AC4
IFPEF_RSET TXC TXC IFPE_L3
AC3
NC FOR GK208 TXD0 TXD0 IFPE_L2#
AC2
TXD0 TXD0 IFPE_L2

TXD1 TXD1 AC1

IFPE_L1#
AD1
IFPE TXD1 TXD1 IFPE_L1
AD3
TXD2 TXD2 IFPE_L0#
AD2
TXD2 TXD2 IFPE_L0

NC FOR GK208
GPU1L 12 OF 17
B B
7/17 IFPD
HPD_E HPD_E R1
GPIO18
ALL PINS NC FOR GF117

AN2
IFPD_RSET
DVI/HDMI DP

TP7404 1 IFPD_PLLVDD AG7 I2CX_SDA AK2 TP7409 1 IFPE_IOVDD AC7

IFPD_PLLVDD IFPD_AUX_I2CX_SDA# IFPE_IOVDD
I2CX_SCL AK3 I2CZ_SDA AF2
IFPD_AUX_I2CX_SCL IFPF_AUX_I2CZ_SDA#
I2CZ_SCL AF3
TP7410 IFPF_IOVDD IFPF_AUX_I2CZ_SCL
1 AC8
IFPF_IOVDD
TXC AK5
IFPD_L3#
TXC AK4 TXC AF1
IFPD_L3 NC FOR GK208 IFPF_L3#
TXC AG1
IFPF_L3
TXD0 AL4
IFPD_L2#
IFPD TXD0 IFPD_L2
AL3 TXD3 TXD0 IFPF_L2#
AD5
TXD3 TXD0 AD4
IFPF_L2
TXD1 AM4
IFPD_L1#
TXD1 AM3 TXD4 TXD1 AF5
IFPD_L1
IFPF TXD4 TXD1
IFPF_L1#
IFPF_L1
AF4
TXD2 AM2
IFPD_L0#
TXD2 AM1 TXD5 TXD2 AE4
IFPD_L0 IFPF_L0#
TXD5 TXD2 AE3
IFPF_L0

TP7405 IFPD_IOVDD NC FOR GK208

1 AG6 M6
IFPD_IOVDD GPIO17
HPD_F P3
N14P-GS-A1-GP GPIO19

71.0N14P.00U N14P-GS-A1-GP
A A

OPS 71.0N14P.00U
<Core Design>
OPS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 74 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO GPU1B 2 OF 17

A00 0618
GPU1C 3 OF 17
2/17 FBA 0R0402-PAD-2-GP 3/17 FBB
4 OF 17 1D35V_VGA_S0
1 R7506 2 EC_FB_CLAMP [24,76,83] GPU1D
14/17 FBVDDQ
[78] FBA_D[0..31] [80] FBB_D[0..31] ALL PINS NC FOR GF117/GK208

AA27
FBA_D0 FB_CLAM R7518 FBB_D0 FBVDDQ_1
L28 E1 1 2 10KR2J-3-GP G9 AA30
FBA_D1 FBA_D0 FB_CLAMP FBB_D1 FBB_D0 FBVDDQ_2
M29
FBA_D1
OPS E9
FBB_D1 FBVDDQ_3
AB27
FBA_D2 L29 FBB_D2 G8 AB33
FBA_D3 FBA_D2 FBB_D3 FBB_D2 FBVDDQ_4
M28 F9 AC27
FBA_D4 FBA_D3 FBB_D4 FBB_D3 FBVDDQ_5
N31 F11 AD27
FBA_D5 FBA_D4 FBA_PLL_AVDD FBB_D5 FBB_D4 FBVDDQ_6
P29 K27 G11 AE27
FBA_D6 FBA_D5 FB_DLL_AVDD FBB_D6 FBB_D5 FBVDDQ_7
R29 F12 AF27
FBA_D7 FBA_D6 FBB_D7 FBB_D6 FBVDDQ_8
P28 G12 AG27
FBA_D8 FBA_D7 FBB_D8 FBB_D7 FBVDDQ_9
D J28 G6 B13 D
FBA_D9 FBA_D8 C7509 FBB_D9 FBB_D8 FBVDDQ_10
H29 X7R F5 B16

1
FBA_D10 FBA_D9 FBB_D10 FBB_D9 FBVDDQ_11
J29 E6 B19

SCD1U10V2KX-5GP
FBA_D11 FBA_D10 FBB_D11 FBB_D10 FBVDDQ_12
H28
FBA_D11 OPS Layout note:FBA_PLL_AVDD=16mil F6
FBB_D11 FBVDDQ_13
E13
FBA_D12 G29 FBB_D12 F4 E16

2
FBA_D13 FBA_D12 FBB_D13 FBB_D12 FBVDDQ_14
E31
FBA_D13 Place close to Ball G4
FBB_D13 FBVDDQ_15
E19
FBA_D14 E32 FBB_D14 E2 H10
FBA_D15 FBA_D14 FBB_D15 FBB_D14 FBVDDQ_16
F30 F3 H11
FBA_D16 FBA_D15 FBB_D16 FBB_D15 FBVDDQ_17
C34 C2 H12
FBA_D17 FBA_D16 FBB_D17 FBB_D16 FBVDDQ_18
D32 D4 H13
FBA_D18 FBA_D17 FBB_D18 FBB_D17 FBVDDQ_19
B33 D3 H14
FBA_D19 FBA_D18 FBB_D19 FBB_D18 FBVDDQ_20
C33 C1 H15
FBA_D20 FBA_D19 FBB_D20 FBB_D19 FBVDDQ_21
F33
FBA_D20 0102 remove L7502 B3
FBB_D20 FBVDDQ_22
H16
FBA_D21 F32 FBB_D21 C4 H18
FBA_D22 H33
FBA_D21 change K27 pin net name FBB_D22 B5
FBB_D21 FBVDDQ_23
H19
FBA_D23 FBA_D22 FBB_D23 FBB_D22 FBVDDQ_24
H32 C5 H20
FBA_D24 FBA_D23 FBB_D24 FBB_D23 FBVDDQ_25
P34 A11 H21
FBA_D25 FBA_D24 FBB_D25 FBB_D24 FBVDDQ_26
P32 C11 H22
FBA_D26 FBA_D25 FBB_D26 FBB_D25 FBVDDQ_27
P31 D11 H23
FBA_D27 FBA_D26 FBB_D27 FBB_D26 FBVDDQ_28
P33 B11 H24
FBA_D28 FBA_D27 FBB_D28 FBB_D27 FBVDDQ_29
L31 D8 H8
FBA_D29 FBA_D28 FBB_D29 FBB_D28 FBVDDQ_30
L34 A8 H9
FBA_D30 FBA_D29 FBB_D30 FBB_D29 FBVDDQ_31
L32 C8 L27
FBA_D31 FBA_D30 FBB_D31 FBB_D30 FBVDDQ_32
[79] FBA_D[32..63] L33 [81] FBB_D[32..63] B8 M27
FBA_D32 FBA_D31 FBB_D32 FBB_D31 FBVDDQ_33
AG28 F24 N27
FBA_D33 FBA_D32 FBA_CMD0 FBB_D33 FBB_D32 FBB_CMD0 FBVDDQ_34
AF29 U30 FBA_CMD0 [78] G23 D13 FBB_CMD0 [80] P27
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 FBB_D34 FBB_D33 FBB_CMD0 FBB_CMD1 FBVDDQ_35
AG29 T31 FBA_CMD1 [78] E24 E14 FBB_CMD1 [80] R27
FBA_D35 FBA_D34 FBA_CMD1 FBA_CMD2 FBB_D35 FBB_D34 FBB_CMD1 FBB_CMD2 FBVDDQ_36
AF28 U29 FBA_CMD2 [78] G24 F14 FBB_CMD2 [80] T27
FBA_D36 FBA_D35 FBA_CMD2 FBA_CMD3 FBB_D36 FBB_D35 FBB_CMD2 FBB_CMD3 FBVDDQ_37
AD30 R34 FBA_CMD3 [78] D21 A12 FBB_CMD3 [80] T30
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD4 FBB_D37 FBB_D36 FBB_CMD3 FBB_CMD4 FBVDDQ_38
AD29 R33 FBA_CMD4 [78] E21 B12 FBB_CMD4 [80] T33
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD5 FBB_D38 FBB_D37 FBB_CMD4 FBB_CMD5 FBVDDQ_39
AC29 U32 FBA_CMD5 [78] G21 C14 FBB_CMD5 [80] V27
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD6 FBB_D39 FBB_D38 FBB_CMD5 FBB_CMD6 FBVDDQ_40
AD28 U33 FBA_CMD6 [78] F21 B14 FBB_CMD6 [80] W27
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD7 FBB_D40 FBB_D39 FBB_CMD6 FBB_CMD7 FBVDDQ_41
AJ29 U28 FBA_CMD7 [78] G27 G15 FBB_CMD7 [80] W30
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD8 FBB_D41 FBB_D40 FBB_CMD7 FBB_CMD8 FBVDDQ_42
AK29 V28 FBA_CMD8 [78] D27 F15 FBB_CMD8 [80] W33
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD9 FBB_D42 FBB_D41 FBB_CMD8 FBB_CMD9 FBVDDQ_43
AJ30 V29 FBA_CMD9 [78] G26 E15 FBB_CMD9 [80] Y27
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD10 FBB_D43 FBB_D42 FBB_CMD9 FBB_CMD10 FBVDDQ_44
AK28 V30 FBA_CMD10 [78] E27 D15 FBB_CMD10 [80]
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD11 FBB_D44 FBB_D43 FBB_CMD10 FBB_CMD11
AM29 U34 FBA_CMD11 [78] E29 A14 FBB_CMD11 [80]
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD12 FBB_D45 FBB_D44 FBB_CMD11 FBB_CMD12 TP7501 FBVDDQ_SENSE
AM31 U31 FBA_CMD12 [78] F29 D14 FBB_CMD12 [80] 1 F1
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD13 FBB_D46 FBB_D45 FBB_CMD12 FBB_CMD13 FB_VDDQ_SENSE
AN29 V34 FBA_CMD13 [78] E30 A15 FBB_CMD13 [80] 1D35V_VGA_S0
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD14 FBB_D47 FBB_D46 FBB_CMD13 FBB_CMD14
AM30 V33 FBA_CMD14 [78] D30 B15 FBB_CMD14 [80]
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD15 FBB_D48 FBB_D47 FBB_CMD14 FBB_CMD15 TP7502 FB_GND_SENSE
AN31 Y32 FBA_CMD15 [78] A32 C17 FBB_CMD15 [80] 1 F2
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16 FBB_D49 FBB_D48 FBB_CMD15 FBB_CMD16 FB_GND_SENSE
C AN32 AA31 FBA_CMD16 [79] C31 D18 FBB_CMD16 [81] C
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17 FBB_D50 FBB_D49 FBB_CMD16 FBB_CMD17 R7505
AP30 AA29 FBA_CMD17 [79] C32 E18 FBB_CMD17 [81]
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18 FBB_D51 FBB_D50 FBB_CMD17 FBB_CMD18 FB_CAL_PD_VDDQ
AP32
FBA_D51 FBA_CMD18
AA28 FBA_CMD18 [79] B32
FBB_D51 FBB_CMD18
F18 FBB_CMD18 [81] 2 OPS 1 J27
FB_CAL_PD_VDDQ
FBA_D52 AM33 AC34 FBA_CMD19 FBA_CMD19 [79] FBB_D52 D29 A20 FBB_CMD19 FBB_CMD19 [81]
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD20 FBB_D53 FBB_D52 FBB_CMD19 FBB_CMD20 40D2R2F-GP
AL31 AC33 FBA_CMD20 [79] A29 B20 FBB_CMD20 [81]
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD21 FBB_D54 FBB_D53 FBB_CMD20 FBB_CMD21 FB_CAL_PU_GND
AK33 AA32 FBA_CMD21 [79] C29 C18 FBB_CMD21 [81] H27
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD22 FBB_D55 FBB_D54 FBB_CMD21 FBB_CMD22 FB_CAL_PU_GND
AK32 AA33 FBA_CMD22 [79] B29 B18 FBB_CMD22 [81]
FBA_D56 FBA_D55 FBA_CMD22 FBA_CMD23 FBB_D56 FBB_D55 FBB_CMD22 FBB_CMD23
AD34 Y28 FBA_CMD23 [79] B21 G18 FBB_CMD23 [81]
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD24 FBB_D57 FBB_D56 FBB_CMD23 FBB_CMD24 FB_CAL_TERM_GND
AD32 Y29 FBA_CMD24 [79] C23 G17 FBB_CMD24 [81] H25
FBA_D58 FBA_D57 FBA_CMD24 FBA_CMD25 FBB_D58 FBB_D57 FBB_CMD24 FBB_CMD25 FB_CAL_TERM_GND
AC30 W31 FBA_CMD25 [79] A21 F17 FBB_CMD25 [81]
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD26 FBB_D59 FBB_D58 FBB_CMD25 FBB_CMD26
AD33 Y30 FBA_CMD26 [79] C21 D16 FBB_CMD26 [81]
FBA_D60 FBA_D59 FBA_CMD26 FBA_CMD27 FBB_D60 FBB_D59 FBB_CMD26 FBB_CMD27 N14P-GS-A1-GP
AF31 AA34 FBA_CMD27 [79] B24 A18 FBB_CMD27 [81]
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD28 FBB_D61 FBB_D60 FBB_CMD27 FBB_CMD28
AG34 Y31 FBA_CMD28 [79] C24 D17 FBB_CMD28 [81]
FBA_D62 FBA_D61 FBA_CMD28 FBA_CMD29 FBB_D62 FBB_D61 FBB_CMD28 FBB_CMD29
AG32 Y34 FBA_CMD29 [79] B26 A17 FBB_CMD29 [81] 71.0N14P.00U

1
FBA_D63 FBA_D62 FBA_CMD29 FBA_CMD30 FBB_D63 FBB_D62 FBB_CMD29 FBB_CMD30
AG33 Y33 FBA_CMD30 [79] C26 B17 FBB_CMD30 [81]
FBA_D63 FBA_CMD30 FBA_CMD31 FBB_D63 FBB_CMD30 FBB_CMD31 R7507 R7508
V31 FBA_CMD31 [79] E17 FBB_CMD31 [81]
FBA_CMD31 FBB_CMD31 OPS
OPS OPS

60D4R2F-GP
42D2R2F-GP
[78] FBA_DQM[0..3] [80] FBB_DQM[0..3]
FBA_DQM0 P30 NC R32 FBB_DQM0 E11 C12
FBA_DQM1 FBA_DQM0 FBA_CMD_RFU0 FBB_DQM1 FBB_DQM0 FBB_CMD_RFU0
F31 NC AC32 E3 C20

2
FBA_DQM2 FBA_DQM1 FBA_CMD_RFU1 1D35V_VGA_S0 FBB_DQM2 FBB_DQM1 FBB_CMD_RFU1 1D35V_VGA_S0
F34 A3
FBA_DQM3 FBA_DQM2 GF117/GK208 FBB_DQM3 FBB_DQM2
[79] FBA_DQM[4..7] M32 [81] FBB_DQM[4..7] C9
FBA_DQM4 FBA_DQM3 GK107/GF108 FBB_DQM4 FBB_DQM3
AD31
FBA_DQM4 DY F23
FBB_DQM4 DY
FBA_DQM5 AL29 1 2 FBB_DQM5 F27 1 2
FBA_DQM6 FBA_DQM5 R7501 60D4R2F-GP FBB_DQM6 FBB_DQM5 R7502 60D4R2F-GP
AM32 C30
FBA_DQM7 FBA_DQM6 FBA_DEBUG0 FBB_DQM7 FBB_DQM6 FBB_DEBUG0
AF34
FBA_DQM7 FBA_DEBUG0
R28 DY A24
FBB_DQM7 FBB_DEBUG0
G14 DY
AC28 FBA_DEBUG1 1 2 G20 FBB_DEBUG1 1 2
FBA_DEBUG1 R7503 60D4R2F-GP FBB_DEBUG1 R7504 60D4R2F-GP
[78] FBA_EDC[0..3] [80] FBB_EDC[0..3]
FBA_EDC0 M31 FBB_EDC0 D10
FBA_EDC1 FBA_DQS_WP0 FBB_EDC1 FBB_DQS_WP0
G31 D5
FBA_EDC2 FBA_DQS_WP1 FBA_CLK0P FBB_EDC2 FBB_DQS_WP1
E33 R30 FBA_CLK0P [78] C3 D12 FBB_CLK0P FBB_CLK0P [80]
FBA_EDC3 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0N FBB_EDC3 FBB_DQS_WP2 FBB_CLK0
[79] FBA_EDC[4..7] M33 R31 FBA_CLK0N [78] [81] FBB_EDC[4..7] B9 E12 FBB_CLK0N FBB_CLK0N [80]
FBA_EDC4 FBA_DQS_WP3 FBA_CLK0# FBA_CLK1P FBB_EDC4 FBB_DQS_WP3 FBB_CLK0#
AE31 AB31 E23 E20 FBB_CLK1P GPU FBVDDQ Decoupling
FBA_EDC5 AK30
FBA_DQS_WP4 FBA_CLK1
AC31 FBA_CLK1N
FBA_CLK1P [79]
FBA_CLK1N [79]
FBB_EDC5 E28
FBB_DQS_WP4 FBB_CLK1
F20 FBB_CLK1N
FBB_CLK1P [81]
FBB_CLK1N [81]
1.35V +/- 3%
FBA_EDC6 FBA_DQS_WP5 FBA_CLK1# FBB_EDC6 FBB_DQS_WP5 FBB_CLK1# 1D35V_VGA_S0
AN33
FBA_DQS_WP6
B30
FBB_DQS_WP6 4.88A PLACE CLOSE TO GPU BALLS
FBA_EDC7 AF33 FBB_EDC7 A23
FBA_DQS_WP7 FBB_DQS_WP7

M30 K31 FBA_WCK01 D9 F8 FBB_WCK01

FBA_DQS_RN0 FBA_WCK1 FBA_WCK01 [78] FBB_DQS_RN0 FBB_WCK1 FBB_WCK01 [80]
H30 L30 FBA_WCK01# E4 E8 FBB_WCK01#
FBA_DQS_RN1 FBA_WCK1# FBA_WCK01# [78] FBB_DQS_RN1 FBB_WCK1# FBB_WCK01# [80]
E34 H34 FBA_WCK23 B2 A5 FBB_WCK23
FBA_DQS_RN2 FBA_WCK23 FBA_WCK23 [78] FBB_DQS_RN2 FBB_WCK23 FBB_WCK23 [80]

1
M34 J34 FBA_WCK23# FBA_WCK23# [78] A9 A6 FBB_WCK23# FBB_WCK23# [80] C7501 C7502 C7525 C7507 C7508 C7524 C7522 C7513 C7514 C7517 C7520 C7521 C7528
FBA_DQS_RN3 FBA_WCK23# FBB_DQS_RN3 FBB_WCK23#

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
B FBA_WCK45 FBB_WCK45 OPS OPS OPS OPS DY DY OPS B
AF30 AG30 D22 D24 DY DY DY DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
FBA_DQS_RN4 FBA_WCK45 FBA_WCK45 [79] FBB_DQS_RN4 FBB_WCK45 FBB_WCK45 [81]
AK31 AG31 FBA_WCK45# D28 D25 FBB_WCK45#
FBA_WCK45# [79] FBB_WCK45# [81] DY DY

2
FBA_DQS_RN5 FBA_WCK45# FBA_WCK67 FBB_DQS_RN5 FBB_WCK45# FBB_WCK67
AM34 AJ34 FBA_WCK67 [79] A30 B27 FBB_WCK67 [81]
FBA_DQS_RN6 FBA_WCK67 FBA_WCK67# FBB_DQS_RN6 FBB_WCK67 FBB_WCK67#
AF32 AK34 FBA_WCK67# [79] B23 C27 FBB_WCK67# [81]
FBA_DQS_RN7 FBA_WCK67# FBB_DQS_RN7 FBB_WCK67#
J30 D6
FBA_WCKB1 FBB_WCKB1
THE FBA_WCKBxx J31 D7
FBA_WCKB1# DA-05691-001_V05 P7 THE FBB_WCKBxx FBB_WCKB1#
PINS ARE USED J32 C6
FBA_WCKB23 PINS ARE USED FBB_WCKB23
ONLY ON GK107 J33 B6
FBA_WCKB23# ONLY ON GK107 FBB_WCKB23#
THEY ARE NC AH31 F26
FBA_WCKB45 THEY ARE NC FBB_WCKB45
FOR GK208/GF108 AJ31 1D05V_VGA_S0 E26
FBA_WCKB45# FOR GF108 FBB_WCKB45#
/GF117 AJ32 A26
FBA_WCKB67 L7501 FBB_WCKB67
AJ33 A27 1D35V_VGA_S0
FBA_WCKB67# MHC1608S300QBP-GP FBB_WCKB67#
TP7503 1 FB_VREF H26 U27 FBA_PLL_AVDD 1 2 H17 FBA_PLL_AVDD
FB_VREF FBA_PLL_AVDD OPS NC FBB_PLL_AVDD
PLACE CLOSE TO GPU BALLS
30ohm@100MHz ESR=0.2 GF108 GK107
N14P-GS-A1-GP
68.00335.051 N14P-GS-A1-GP
1

OPS C7510 X7R

OPS

1
71.0N14P.00U 71.0N14P.00U

SCD1U10V2KX-5GP
C7505 OPS
2

1
C7506 C7503 C7504 C7526 C7511 C7512 C7527 C7523 C7515 C7516 C7519 C7518 C7529 C7530
SCD1U10V2KX-5GP

2
SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
OPS OPS OPS OPS DY OPS DY DY OPS DY DY DY DY
OPS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
DY

2
1D35V_VGA_S0 1D35V_VGA_S0
Place under GPU near

0102 remove L7503

2

2
R7516 R7524 change C7506 to 0603 package R7517 R7525
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
OPS OPS OPS OPS
1

FBA_CMD14 FBB_CMD14
FBA_CMD30 FBB_CMD30
A A
FBA_CMD29 FBB_CMD29
FBA_CMD13 FBB_CMD13
2

R7520 R7521 <Core Design>

OPS OPS R7522 R7523
10KR2J-3-GP

10KR2J-3-GP

OPS OPS
Wistron Corporation
10KR2J-3-GP

10KR2J-3-GP
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

Taipei Hsien 221, Taiwan, R.O.C.

Title
GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
A2
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 75 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO 1D05V_VGA_S0

30ohm@100MHz
DCR=0.04 ohm
3D3V_VGA_S0
Max current = 3000mA
L7601
GPU1N 14 OF 17 MHC1608S300QBP-GP
52mA
NV request to need to be keeped
4/17 DACA 1 OPS 2
GF108/GK107 GF108/GK107
GF117 GF117 GPU1O 15 OF 17
GK208 GK208
68.00335.051

1
AG10 DACA_VDD NC NC I2CA_SCL R4 I2CA_SCL 4 OPS 1 RN7603 C7606 11/17 XTAL_PLL
NC R5 I2CA_SDA 3 2 SRN2K2J-1-GP C7605 OPS OPSSC2D2U6D3V2MX-GP
I2CA_SDA SCD1U10V2KX-5GP
AP9 TSEN_VREF

2
DACA_VREF GPU_PLL_VDD AD8 PLLVDD
L7602 SP_PLLVDD
AP8 DACA_RSET NC NC
NC
DACA_HSYNC AM9
AN9 MCB1608S181FBP-GP 112mA AE8 SP_PLLVDD
DACA_VSYNC
1 OPS 2 AD7 VID_PLLVDD NC

D NC DACA_RED
AK9 68.00909.261 GF108/GK107 GF117 D
GK208
NC AL10 180ohm@100MHz C7601 C7603 C7604 C7602
DACA_GREEN

1
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
DCR=0.3 ohm

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
NC AL9 OPS OPS OPS OPS VIDEO_CLK_XTAL_SS H1 J4 N12P_XTAL_OUTBUFF
DACA_BLUE XTAL_SSIN XTAL_OUTBUFF
Max current = 300mA

2
N14P-GS-A1-GP
OPS
H3 XTAL_IN XTAL_OUT H2

1
71.0N14P.00U N14P-GS-A1-GP

1
71.0N14P.00U 20PF 5% 50V +/-0.25PF 0402 R7602
OPS10KR2J-3-GP
OPS OPS R7601 R7603
10KR2J-3-GP 1MR2J-1-GP

2
27MHZ_IN 1 DY 2 27MHZ_OUT

2
X7601 A00 0618

2
1 4 R7629
3D3V_VGA_S0 0R0402-PAD-2-GP
0102 remove 0R

1
2 3 27MHZ_OUT_R
3D3V_VGA_S0
OPS

4
3

1
XTAL-27MHZ-85-GP-U
RN7601 C7607 82.30034.641 C7608
SC15P50V2JN-2-GP
OPS SRN4K7J-8-GP OPS 2ND = 82.30034.651 OPS SC15P50V2JN-2-GP

2
3RD = 82.30034.681

1
2
Q7601
3 4 SMBD_THERM_NV
[18,24,26] SML1_DATA
2 5

1 6 2N7002KDW-GP
84.2N702.A3F
OPS 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
SMBC_THERM_NV

C
[18,24,26] SML1_CLK C

3D3V_VGA_S0

3D3V_VGA_S0

RN7606 Q7604
GPU1Q 17 OF 17 3D3V_VGA_S0 GPIO9_ALERT 2 3
10/19 MISC1 GPIO8_OVERT# 1 OPS 4 G
T4 SMBC_THERM_NV OPS
I2CS_SCL SMBD_THERM_NV
T3 SRN10KJ-5-GP D VIDEO_THERM_OVERT# [82]
I2CS_SDA
R2 I2CC_SCL 3 2 GPIO9_ALERT S
I2CC_SCL
R3 I2CC_SDA 4 1 SRN2K2J-1-GP GPIO10_FBVREF
I2CC_SDA OPS RN7604
2N7002K-2-GP

1
NC I2CB_SCL R7 I2CB_SCL 4 OPS 1 RN7605
1 P2800_VGA_DXN K4 NC R6 I2CB_SDA 3 2 SRN2K2J-1-GP R7610 84.2N702.J31
TP7603 THERMDN I2CB_SDA 100KR2J-1-GP
P2800_VGA_DXP
OPS 2ND = 84.2N702.031
1 K3 THERMDP GK107/GF108
TP7604 GF117

2
GK208

N12P_JTAG_TCK AM10 A00 0618

N12P_JTAG_TMS JTAG_TCK
1 AP11 1 2 VGA_RST# [73]
TP7602 N12P_JTAG_TDI JTAG_TMS R7604
1 AM11 JTAG_TDI VGA_RST#_R
TP7605 1 N12P_JTAG_TDO AP12 0R0402-PAD-2-GP
TP7601 N12P_JTAG_TRST JTAG_TDO FB_CLAMP_MON
AN11 JTAG_TRST# GPIO0 P6
GPIO1 M3 Q7602
GPIO2 L6
4
3

RN7602 P5 3D3V_VGA_S0 G
GPIO3
GPIO4 P7 OPS
GPIO5 L7 D PURE_HW_SHUTDOWN# [24,26,36] 3D3V_VGA_S0 3D3V_VGA_S0 3D3V_VGA_S0
OPS M7 FB_CLAMP_TGL_REQ#
GPIO6
1

SRN10KJ-5-GP GK208 N8 GPIO8_OVERT# S

GPIO7 GPIO8_OVERT# R7605
OVERT M1
1
2

GPIO8

1
M2 GPIO9_ALERT OPS 10KR2J-3-GP
GPIO9 GPIO10_FBVREF 2N7002K-2-GP R7608 R7611 R7612
GPIO10 L1 GPIO10_FBVREF [78,79,80,81]
M5 VGA_CORE_VID [82] D7601 84.2N702.J31 4K99R2F-L-GP OPS 10KR2J-3-GPDY 10KR2J-3-GPDY
2

GPIO11 PWR_LEVEL
GPIO12 N3 A DY K AC_PRESENT [17,24] 2ND = 84.2N702.031
M4 VGA_CORE_PSI [82]

2
GPIO13
GPIO16 NC GPIO16 R8 1SS400GPT-GP
GPIO16 ROM_SO ROM_SI ROM_SCLK
GPIO20 NC NC GPIO20 P4 83.00400.C1F
GPIO8 NC NC GPIO21 P1 2ND = 83.27101.01F

1
GK208 GF117 GK107 GF108 3RD = 83.01426.01F R7618
D7602 R7621 45K3R2F-L-GP R7617
B 15KR2F-GP B
DA-05691-001_V05 P15 A OPS K OVER_CURRENT_P8# [24] DY Samsung OPS 15KR2F-GP
GPIO20/21 NC : for ALL
1SS400GPT-GP

2
83.00400.C1F
N14P-GS-A1-GP
2ND = 83.27101.01F
71.0N14P.00U
3RD = 83.01426.01F
OPS
3D3V_VGA_S0 3D3V_VGA_S0 3D3V_VGA_S0 3D3V_VGA_S0 3D3V_VGA_S0

1
R7613 R7614 R7615 R7620 R7616
EA40-HW SC 10KR2J-3-GPDY 10KR2J-3-GPDY 10KR2J-3-GPDY 45K3R2F-L-GP DY 45K3R2F-L-GP OPS
3D3V_VGA_S0

2
GPU1P 16 OF 17
12/17 MISC2 STRAP4 STRAP3 STRAP2 STRAP1 STRAP0
2

3D3V_VGA_S0 3D3V_VGA_S0 3D3V_S0

1
R7626 3D3V_S0

1
DY 10KR2J-3-GP R7609 R7622

2
Q7603 45K3R2F-L-GP R7625 R7619 R7627 DY 15KR2F-GP
2

2
H6 ROM_CS# 2N7002KDW-GP R7648 OPS 4K99R2F-L-GP 24K9R2F-L-GP OPS 4K99R2F-L-GP
Q7606
1

ROM_CS# R7650 R7649 10KR2J-L-GP

84.2N702.A3F OPS OPS

2
H5 ROM_SI 2nd = 84.DM601.03F 10KR2J-L-GP 10KR2J-L-GP G OPS_GC6

2
ROM_SI ROM_SO
H7 3rd = 84.2N702.F3F OPS_GC6 OPS_GC6

1
STRAP0 ROM_SO ROM_SCLK
J2 H4 D
1

STRAP1 STRAP0 ROM_SCLK

J7 STRAP1
1 6
STRAP2 J6 FB_CLAMP_TGL_REQ# S OPS_GC6
STRAP3 STRAP2 FB_CLAMP_MON_S
J5 STRAP3 NC [24,75,83] EC_FB_CLAMP 2 5 EC_FB_CLAMP_TGL_REQ# [24]
STRAP4 J3 NC
STRAP4 3D3V_VGA_S0 2N7002K-2-GP
GK107/GF117 GF108
3 4
GK208
84.2N702.J31
R7628 2ND = 84.2N702.031
2

BUFRST# R7647
OPS_GC6
BUFRST# L2 2 OPS 1
10KR2J-L-GP
10KR2J-3-GP OPS_GC6
1

STRAP_REF0_GND_N9 J1 L3 FB_CLAMP_MON
MULTI_STRAP_REF CEC
N14P-GT
CEC IS NC FOR
A DA-05691-001_V05 P6 A
1

GK107/GK208/GF117

R7607
OPS NC : N13P-GS
40K2R2F-GP
N14P-GS-A1-GP
2

71.0N14P.00U
<Core Design>

OPS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Reserved Rev
Custom X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 76 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
VGA_CORE

GPU1F 6 OF 17 GPU1G 7 OF 17
GPU1H 8 OF 17 GPU1I 9 OF 17
Under GPU N14P-GT : 45A 13/17 NVVDD A2
15/17 GND_1/2
AM25
16/17 GND_2/2
9/17 XVDD
GND_1 GND_71
AA17 GND_5 GND_72 AN1 N19 GND_141 GND_170 T28
AA12 AA18 AN10 N2 T32 CONFIGURABLE
VDD_1 GND_6 GND_73 GND_142 GND_171
AA14 AA20 AN13 N21 T5 POWER
VDD_2 GND_7 GND_74 GND_143 GND_172
AA16 VDD_3 AA22 GND_8 GND_75 AN16 N23 GND_144 GND_173 T7 CHANNELS
C7709 C7708 C7702 C7701 AA19 AB12 AN19 N28 U12 U1
1 VDD_4 GND_9 GND_76 GND_145 GND_174 XVDD_1

1
D C7707 C7706 AA21 AB14 AN22 N30 U14 U2 D
VDD_5 GND_10 GND_77 GND_146 GND_175 XVDD_2
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
OPS OPS OPS OPS OPS OPS AA23 VDD_6 AB16 GND_11 GND_78 AN25 N32 GND_147 GND_176 U16 XVDD_3 U3
AB13 AB19 AN30 N33 U19 U4
2

2
VDD_7 GND_12 GND_79 GND_148 GND_177 XVDD_4
AB15 AB2 AN34 N5 U21 U5
VDD_8 GND_13 GND_80 GND_149 GND_178 XVDD_5
AB17 VDD_9 AB21 GND_14 GND_81 AN4 N7 GND_150 GND_179 U23 XVDD_6 U6
AB18 A33 AN7 P13 V12 U7
VDD_10 GND_2 GND_82 GND_151 GND_180 XVDD_7
AB20 AB23 AP2 P15 V14 U8
VDD_11 GND_15 GND_83 GND_152 GND_181 XVDD_8
AB22 AB28 AP33 P17 V16
VDD_12 GND_16 GND_84 GND_153 GND_182
AC12 AB30 B1 P18 V19
VDD_13 GND_17 GND_85 GND_154 GND_183
AC14 AB32 B10 P20 V21 V1
VDD_14 GND_18 GND_86 GND_155 GND_184 XVDD_9
AC16 AB5 B22 P22 V23 V2
VDD_15 GND_19 GND_87 GND_156 GND_185 XVDD_10
AC19 AB7 B25 R12 W13 V3
VDD_16 GND_20 GND_88 GND_157 GND_186 XVDD_11
AC21 VDD_17 AC13 GND_21 GND_89 B28 R14 GND_158 GND_187 W15 XVDD_12 V4
AC23 VDD_18 AC15 GND_22 GND_90 B31 R16 GND_159 GND_188 W17 XVDD_13 V5
M12 VDD_19 AC17 GND_23 GND_91 B34 R19 GND_160 GND_189 W18 XVDD_14 V6
C7722 C7723 C7724 C7721 C7720 C7719 M14 AC18 B4 R21 W20 V7
VDD_20 GND_24 GND_92 GND_161 GND_190 XVDD_15
1

1
C7725 M16 AA13 B7 R23 W22 V8
VDD_21 GND_3 GND_93 GND_162 GND_191 XVDD_16
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
OPS OPS OPS OPS OPS OPS OPS M19 VDD_22 AC20 GND_25 GND_94 C10 T13 GND_163 GND_192 W28
M21 AC22 C13 T15 Y12
2

2
VDD_23 GND_26 GND_95 GND_164 GND_193
M23 VDD_24 AE2 GND_27 GND_96 C19 T17 GND_165 GND_194 Y14 XVDD_17 W2
N13 VDD_25 AE28 GND_28 GND_97 C22 T18 GND_166 GND_195 Y16 XVDD_18 W3
N15 VDD_26 AE30 GND_29 GND_98 C25 T2 GND_167 GND_196 Y19 XVDD_19 W4
N17 VDD_27 AE32 GND_30 GND_99 C28 T20 GND_168 GND_197 Y21 XVDD_20 W5
N18 VDD_28 AE33 GND_31 GND_100 C7 T22 GND_169 GND_198 Y23 XVDD_21 W7
N20 VDD_29 AE5 GND_32 GND_101 D2 XVDD_22 W8
N22 VDD_30 AE7 GND_33 GND_102 D31
P12 VDD_31 AH10 GND_34 GND_103 D33
P14 VDD_32 AA15 GND_4 GND_104 E10
P16 VDD_33 AH13 GND_35 GND_105 E22
P19 VDD_34 AH16 GND_36 GND_106 E25 XVDD_23 Y1
P21 VDD_35 AH19 GND_37 GND_107 E5 AG11 GND_F GND_H AH11 XVDD_24 Y2
C7716 C7715 C7718 C7717 C7714 C7713 C7712 C7711 P23 AH2 E7 Y3
VDD_36 GND_38 GND_108 XVDD_25
1

R13 VDD_37 AH22 GND_39 GND_109 F28 XVDD_26 Y4

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

OPS OPS OPS OPS OPS OPS OPS OPS R15 VDD_38 AH24 GND_40 GND_110 F7 XVDD_27 Y5
C R17 AH28 G10 Y6 C
2

VDD_39 GND_41 GND_111 XVDD_28

R18 VDD_40 AH29 GND_42 GND_112 G13 XVDD_29 Y7
R20 VDD_41 AH30 GND_43 GND_113 G16 XVDD_30 Y8
R22 VDD_42 AH32 GND_44 GND_114 G19
T12 VDD_43 AH33 GND_45 GND_115 G2 GND_OPT_1 C16
T14 VDD_44 AH5 GND_46 GND_116 G22 GND_OPT_2 W32 XVDD_31 AA1
T16 VDD_45 AH7 GND_47 GND_117 G25 XVDD_32 AA2
T19 VDD_46 AJ7 GND_48 GND_118 G28 Optional CMD GNDs (2)
XVDD_33 AA3
T21 AK10 G3 NC for 4-Lyr cards AA4
VDD_47 GND_49 GND_119 XVDD_34
T23 AK7 G30 AA5
VDD_48 GND_50 GND_120 N14P-GS-A1-GP XVDD_35
U13 AL12 G32 AA6
VDD_49 GND_51 GND_121 XVDD_36
U15
VDD_50
AL14
GND_52 GND_122
G33 71.0N14P.00U XVDD_37
AA7
U17 AL15 G5 AA8
VDD_51 GND_53 GND_123 XVDD_38
U18 AL17 G7
NEAR TO GPU U20
VDD_52
AL18
GND_54 GND_124
K2 OPS N14P-GS-A1-GP
VDD_53 GND_55 GND_125
U22
VDD_54
AL2
GND_56 GND_126
K28 71.0N14P.00U
V13 AL20 K30
VDD_55 GND_57 GND_127
V15 AL21 K32
VDD_56 GND_58 GND_128
V17
VDD_57
AL23
GND_59 GND_129
K33 OPS
V18 AL24 K5
VDD_58 GND_60 GND_130
V20 AL26 K7
VDD_59 GND_61 GND_131
1

C7703 C7705 C7710 R7701 V22 AL28 M13

VDD_60 GND_62 GND_132
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

W12 AL30 M15

OPS OPS OPS VDD_61 GND_63 GND_133
0R3J-0-U-GP

UMA W14 AL32 M17

2

VDD_62 GND_64 GND_134

W16 AL33 M18
VDD_63 GND_65 GND_135
W19 AL5 M20
2

VDD_64 GND_66 GND_136

W21 AM13 M22
VDD_65 GND_67 GND_137
W23 AM16 N12
VDD_66 GND_68 GND_138
Y13 AM19 N14
VDD_67 GND_69 GND_139
Y15 AM22 N16
VDD_68 GND_70 GND_140
Y17
VDD_69
Y18
VDD_70
Y20
VDD_71 N14P-GS-A1-GP
Y22
VDD_72
B 71.0N14P.00U B

N14P-GS-A1-GP
71.0N14P.00U OPS

OPS

GPU1E 5 OF 17 DA-05691-001_V05 P20 3.3V +/- 5%

17/17 NC/VDD33 3V3MISC : N13P-GS 85mA 3D3V_VGA_S0
GK208
GK107
GF117
AJ28 3V3MISC J8
NC#AJ28 3V3MISC_1
C15 3V3MISC K8
NC#C15 3V3MISC_2
D19
NC#D19
D20 L8
NC#D20 VDD33_1
D23
NC#D23 VDD33_2
M8 X7R X7R
1

D26 C7704 C7729 C7727 C7728

NC#D26
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

H31
NC#H31 OPS OPS OPS OPS
V32
2

NC#V32
AC6
DNU#AC6 DO NOT
AJ4
DNU#AJ4 CONNECT
AJ5
DNU#AJ5 THESE
AL11
DNU#AL11 PINS
T8
DNU#T8

N14P-GS-A1-GP 0.1U Under GPU

A 71.0N14P.00U A
4.7U NEAR TO GPU
OPS <Core Design>
1U NEAR TO GPU
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_POWER(4/5)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 77 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

1D35V_VGA_S0 VRAM2A 1 OF 2 1D35V_VGA_S0 Place close VDD ball

1D35V_VGA_S0 VRAM1A 1 OF 2
Frame Buffer Patition A-Lower Half C5
VDD OPS VSS
B5
OPS OPS
C5 B5 C10 B10
VDD OPS VSS VDD VSS

ST330U2VDM-4-GP
C7827

C7804
SC10U6D3V3MX-GP

SC1U6D3V3KX-2GP
C7805

SC1U6D3V3KX-2GP
C7806

SC1U6D3V3KX-2GP
C7807

SC1U6D3V3KX-2GP
C7809
C10 B10 D11 D10
VDD VSS VDD VSS

1
D11 D10 1D35V_VGA_S0 G1 G5
VDD VSS VDD VSS
G1 G5 G4 G10
G4
VDD VSS
G10 G11
VDD VSS
H1 DY OPS
OPS

2
D VDD VSS VDD VSS D
G11 H1 G14 H14
VDD VSS VDD VSS

1
G14 H14 L1 K1
L1
VDD VSS
K1 R7806 R7805 L4
VDD VSS
K14
OPS
VDD VSS 549R2F-GP 549R2F-GP VDD VSS
L4 K14 L11 L5
VDD VSS VDD VSS
L11 L5 L14 L10
L14
VDD VSS
L10
OPS OPS P11
VDD VSS
P10

2
VDD VSS FBA_VREFC0 FBA_VREFD_L VDD VSS
P11 P10 R5 T5
R5
VDD VSS
T5 1D35V_VGA_S0 R10
VDD VSS
T10 1D35V_VGA_S0 Place close VDD ball
VDD VSS VDD VSS

1
1D35V_VGA_S0

SC820P50V2KX-1GP
C7803

1K33R2F-GP
R7807

931R2F-1-GP
R7804

931R2F-1-GP
R7803

1K33R2F-GP
R7809

SC820P50V2KX-1GP
C7802
R10 T10
VDD VSS

1
B1 A1
B1 A1 B3
VDDQ VSSQ
A3
OPS OPS OPS
VDDQ VSSQ OPS VDDQ VSSQ

SCD1U10V2KX-4GP
C7820

SCD1U10V2KX-4GP
C7821

SCD1U10V2KX-4GP
C7822

SCD1U10V2KX-4GP
C7823

SCD1U10V2KX-4GP
C7824

SCD1U10V2KX-4GP
C7825
B3 A3 B12 A12
OPS OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ

1
B12 A12 B14 A14

2
VDDQ VSSQ VDDQ VSSQ
B14 A14 D1 C1
D1
VDDQ VSSQ
C1 D3
VDDQ VSSQ
C3 OPS
DY

2
VDDQ VSSQ VDDQ VSSQ
D3 C3 D12 C4
VDDQ VSSQ FBA_VREF_FET_L VDDQ VSSQ
D12 C4 D14 C11
D14
VDDQ VSSQ
C11 E5
VDDQ VSSQ
C12
OPS
VDDQ VSSQ VDDQ VSSQ
E5 C12 E10 C14
VDDQ VSSQ VDDQ VSSQ
E10 C14 F1 E1

D
VDDQ VSSQ VDDQ VSSQ
F1 E1 F3 E3
F3
VDDQ VSSQ
E3 Q7801 F12
VDDQ VSSQ
E12 1D35V_VGA_S0 Place close VDDQ ball
VDDQ VSSQ VDDQ VSSQ
F12 E12 2N7002K-2-GP F14 E14
VDDQ VSSQ VDDQ VSSQ
F14 E14 84.2N702.J31 G2 F5
VDDQ VSSQ VDDQ VSSQ
G2 F5 G13 F10
VDDQ VSSQ OPS VDDQ VSSQ OPS OPS

SC10U6D3V3MX-GP
C7813

SC1U6D3V3KX-2GP
C7814

SC1U6D3V3KX-2GP
C7810

SC1U6D3V3KX-2GP
C7811

SC1U6D3V3KX-2GP
C7812
G13
VDDQ VSSQ
F10 2ND = 84.2N702.031 H3
VDDQ VSSQ
H2

1
H3 H2 H12 H13
VDDQ VSSQ VDDQ VSSQ
H12 H13 K3 K2
OPS

S
VDDQ VSSQ VDDQ VSSQ
K3 K2 Description K12 K13

2
VDDQ VSSQ VDDQ VSSQ
K12 K13 [76,79,80,81] GPIO10_FBVREF L2 M5
VDDQ VSSQ VDDQ VSSQ
L2 M5 L13 M10
L13
VDDQ VSSQ
M10 M1
VDDQ VSSQ
N1
OPS OPS
VDDQ VSSQ VDDQ VSSQ
M1 N1 M3 N3
VDDQ VSSQ VDDQ VSSQ
M3
VDDQ VSSQ
N3 FBVREF Termination M12
VDDQ VSSQ
N12
M12 N12 M14 N14
VDDQ VSSQ VDDQ VSSQ
M14 N14 N5 R1
N5
VDDQ VSSQ
R1 Type FBVREF% Voltage GPU_GPIO10 N10
VDDQ VSSQ
R3
Place close VDD ball Place close VDDQ ball
VDDQ VSSQ VDDQ VSSQ
C N10 R3 P1 R4 C
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0 1D35V_VGA_S0
P1 R4 P3 R11
VDDQ VSSQ VDDQ VSSQ
P3
VDDQ VSSQ
R11 Un-termination 50% 0.749V High P12
VDDQ VSSQ
R12
P12 R12 P14 R14
VDDQ VSSQ VDDQ VSSQ
P14 R14 T1 U1
VDDQ VSSQ VDDQ VSSQ
T1
VDDQ VSSQ
U1 Termination 70% 1.0617V Low T3
VDDQ VSSQ
U3
OPS OPS

C7808

C7815

C7816

C7817

C7818

C7819
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
T3 U3 T12 U12
VDDQ VSSQ VDDQ VSSQ

1
T12 U12 T14 U14
VDDQ VSSQ VDDQ VSSQ
T14 U14
VDDQ VSSQ FBA_VREFC0 J14 A5
OPS

2
FBA_VREFC0 VREFC VPP/NC#A5
J14 A5 U5
VREFC VPP/NC#A5 FBA_VREFD_L VPP/NC#U5
U5 A10
FBA_VREFD_L A10
VPP/NC#U5 VPP1 1 TP7801 TPAD14-OP-GP U10
VREFD TP_VPPNC3
1 TP7803 TPAD14-OP-GP OPS OPS
U10
VREFD VPP2 1 TP7802 TPAD14-OP-GP VREFD TP_VPPNC4
1 TP7804 TPAD14-OP-GP OPS
VREFD
C7826
SC820P50V2KX-1GP
1

H5GQ2H24AFR-T2C-GP
H5GQ2H24AFR-T2C-GP
OPS
2

[75] FBA_EDC[0..3] FBA_DQM[0..3] [75]

FBA_EDC0 FBA_DQM0
FBA_EDC1 FBA_DQM1
FBA_EDC2 FBA_DQM2
FBA_EDC3 FBA_DQM3

B B

Mirrored(MF=1)
Normal(MF=0) FBA_D[0..31] [75]
VRAM2B 2 OF 2
VRAM1B 2 OF 2
FBA_D[0..31] [75]
FBA_CMD10 K4 A4 FBA_D24
FBA_CMD6 K4 A4 FBA_D0
[75] FBA_CMD10
FBA_CMD7 H5
A8/A7 OPS DQ0
A2 FBA_D25
[75]
[75]
FBA_CMD6
FBA_CMD11 FBA_CMD11 H5
A8/A7 OPS DQ0
A2 FBA_D1
[75]
[75]
FBA_CMD7
FBA_CMD6 FBA_CMD6 H4
A9/A1 DQ1
B4 FBA_D26
FBA_CMD10 A9/A1 DQ1 FBA_D2 FBA_CMD11 A10/A0 DQ2 FBA_D27
[75] FBA_CMD10 H4 B4 [75] FBA_CMD11 K5 B2
FBA_CMD7 A10/A0 DQ2 FBA_D3 FBA_CMD9 A11/A6 DQ3 FBA_D28
[75] FBA_CMD7 K5 B2 [75] FBA_CMD9 J5 E4
FBA_CMD9 A11/A6 DQ3 FBA_D4 A12/RFU#J5/NC#J5 DQ4 FBA_D29
[75] FBA_CMD9 J5 E4 E2
A12/RFU#J5/NC#J5 DQ4 FBA_D5 FBA_CMD3 DQ5 FBA_D30
E2 [75] FBA_CMD3 H11 F4
FBA_CMD2 DQ5 FBA_D6 FBA_CMD1 BA0/A2 DQ6 FBA_D31
[75] FBA_CMD2 H11 F4 [75] FBA_CMD1 K10 F2
FBA_CMD4 BA0/A2 DQ6 FBA_D7 FBA_CMD2 BA1/A5 DQ7
[75] FBA_CMD4 K10 F2 [75] FBA_CMD2 K11 A11
FBA_CMD3 BA1/A5 DQ7 FBA_CMD4 BA2/A4 DQ8
[75] FBA_CMD3 K11 A11 [75] FBA_CMD4 H10 A13
FBA_CMD1 BA2/A4 DQ8 BA3/A3 DQ9
[75] FBA_CMD1 H10 A13 B11
BA3/A3 DQ9 FBA_CMD8 DQ10
B11 [75] FBA_CMD8 J4 B13
FBA_CMD8 DQ10 FBA_CMD15 ABI# DQ11
[75] FBA_CMD8 J4 B13 [75] FBA_CMD15 G3 E11
FBA_CMD12 ABI# DQ11 FBA_CMD5 RAS# DQ12
[75] FBA_CMD12 G3 E11 [75] FBA_CMD5 G12 E13 FBA_D[0..31] [75]
FBA_CMD0 RAS# DQ12 FBA_CMD12 CS# DQ13
[75] FBA_CMD0 G12 E13 FBA_D[0..31] [75] [75] FBA_CMD12 L3 F11
FBA_CMD15 CS# DQ13 FBA_CMD0 CAS# DQ14
[75] FBA_CMD15 L3 F11 [75] FBA_CMD0 L12 F13
FBA_CMD5 CAS# DQ14 WE# DQ15 FBA_D8
[75] FBA_CMD5 L12 F13 U11
WE# DQ15 FBA_D16 FBA_CLK0P DQ16 FBA_D9
U11 J12 U13
FBA_CLK0P DQ16 FBA_D17 FBA_CLK0N CK DQ17 FBA_D10
[75] FBA_CLK0P J12 U13 J11 T11
FBA_CLK0N CK DQ17 FBA_D18 FBA_CMD14 CK# DQ18 FBA_D11
[75] FBA_CLK0N J11 T11 [75] FBA_CMD14 J3 T13
CK# DQ18 CKE# DQ19
1

[75] FBA_CMD14 FBA_CMD14 J3 T13 FBA_D19 N11 FBA_D12

CKE# DQ19 FBA_D20 R7802 R7801 FBA_DQM3 DQ20 FBA_D13
N11 D2 N13
FBA_DQM0 DQ20 FBA_D21 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBA_D14
D2 N13 D13 M11
DBI0# DQ21 FBA_D22 FBA_DQM1 DBI1# DQ22 FBA_D15
D13 M11 P13 M13
FBA_DQM2 P13
DBI1# DQ22
M13 FBA_D23 OPS OPS P2
DBI2# DQ23
U4
2

DBI2# DQ23 FBA_CLK0_MIDPT DBI3# DQ24

P2 U4 U2
DBI3# DQ24 FBA_CMD13 DQ25
U2 [75] FBA_CMD13 J2 T4
DQ25 RESET# DQ26
2

[75] FBA_CMD13 FBA_CMD13 J2 T4 T2

RESET# DQ26 C7801 FBA_SEN0 DQ27
T2 J10 N4
A FBA_SEN0 J10
DQ27
N4 SCD01U16V2KX-3GP OPS FBA_ZQ1 J13
SEN DQ28
N2 A
1

FBA_ZQ0 SEN DQ28 FBA_MF2 ZQ DQ29

J13 N2 2 1 J1 M4
FBA_MF1 J1
ZQ DQ29
M4
1D35V_VGA_S0
R7812 OPS 1KR2J-1-GP MF DQ30
M2
MF DQ30 DQ31
2

1
R7810

R7813
1KR2J-1-GP

121R2F-GP

M2 FBA_WCK23 D4
DQ31 WCK01
1

2
R7808

R7811
121R2F-GP

1KR2J-1-GP

FBA_WCK01 D4 FBA_WCK23# D5 C2 FBA_EDC3

FBA_WCK01# WCK01 FBA_EDC0 WCK01# EDC0 <Core Design>
D5 C2 C13
WCK01# EDC0
C13 OPS OPS FBA_WCK01 P4
EDC1
R13 FBA_EDC1
OPS OPS FBA_WCK23 P4
EDC1
R13 FBA_EDC2 FBA_WCK01# P5
WCK23 EDC2
R2
Wistron Corporation
1

FBA_WCK23# WCK23 EDC2 WCK23# EDC3

P5 R2
2

WCK23# EDC3
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
[75] FBA_WCK23 H5GQ2H24AFR-T2C-GP Taipei Hsien 221, Taiwan, R.O.C.
H5GQ2H24AFR-T2C-GP [75] FBA_WCK23#
[75] FBA_WCK01 Title
[75] FBA_WCK01#
GPU-VRAM1,2 (1/4)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 78 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

1D35V_VGA_S0 VRAM3A 1 OF 2 1D35V_VGA_S0 VRAM4A 1 OF 2 1D35V_VGA_S0

Frame Buffer Patition A-Upper Half Place close VDD ball
C5 B5 C5 B5
C10
VDD OPS VSS
B10 C10
VDD OPS VSS
B10
VDD VSS 1D35V_VGA_S0 VDD VSS

SC10U6D3V3MX-GP
C7907
D11 D10 D11 D10
VDD VSS VDD VSS

1
D D

SC1U6D3V3KX-2GP
C7924

SC1U6D3V3KX-2GP
C7904

SC1U6D3V3KX-2GP
C7905

SC1U6D3V3KX-2GP
C7906
G1 G5 G1 G5
VDD VSS VDD VSS
G4 G10 G4 G10
G11
VDD VSS
H1 G11
VDD VSS
H1
OPS

2
VDD VSS VDD VSS

1
G14 H14 G14 H14
L1
VDD VSS
K1 R7903 R7907 L1
VDD VSS
K1 OPS OPS OPS OPS
VDD VSS 549R2F-GP 549R2F-GP VDD VSS
L4 K14 L4 K14
VDD VSS VDD VSS
L11 L5 L11 L5
L14
VDD VSS
L10
OPS OPS L14
VDD VSS
L10

2
VDD VSS FBA_VREFC1 FBA_VREFD_H VDD VSS
P11 P10 P11 P10
VDD VSS VDD VSS
R5 T5 R5 T5
VDD VSS VDD VSS

1
1D35V_VGA_S0 1D35V_VGA_S0 1D35V_VGA_S0

SC820P50V2KX-1GP
C7902

1K33R2F-GP
R7904

931R2F-1-GP
R7902

931R2F-1-GP
R7905

1K33R2F-GP
R7901

SC820P50V2KX-1GP
C7903
R10 T10 R10 T10
VDD VSS VDD VSS Place close VDD ball

1
B1 A1 B1 A1
B3
VDDQ VSSQ
A3 OPS B3
VDDQ VSSQ
A3
OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ

SCD1U10V2KX-4GP
C7911

SCD1U10V2KX-4GP
C7912

SCD1U10V2KX-4GP
C7913

SCD1U10V2KX-4GP
C7914

SCD1U10V2KX-4GP
C7920

SCD1U10V2KX-4GP
C7926
B12 A12 B12 A12
OPS

2
VDDQ VSSQ VDDQ VSSQ

1
B14 A14 B14 A14
VDDQ VSSQ VDDQ VSSQ
D1 C1 D1 C1
VDDQ VSSQ VDDQ VSSQ
D3 C3 D3 C3

2
VDDQ VSSQ FBA_VREF_FET_H VDDQ VSSQ
D12 C4 D12 C4
VDDQ VSSQ VDDQ VSSQ
D14 C11 D14 C11
E5
VDDQ VSSQ
C12 E5
VDDQ VSSQ
C12
OPS OPS OPS OPS OPS OPS
VDDQ VSSQ VDDQ VSSQ
E10 C14 E10 C14

D
VDDQ VSSQ VDDQ VSSQ
F1 E1 F1 E1
VDDQ VSSQ Q7901 VDDQ VSSQ
F3 E3 F3 E3
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0
F12 E12 F12 E12
F14
VDDQ VSSQ
E14
2N7002K-2-GP
F14
VDDQ VSSQ
E14
Place close VDDQ ball
VDDQ VSSQ 84.2N702.J31 VDDQ VSSQ
G2 F5 G2 F5
G13
VDDQ VSSQ
F10
OPS 2ND = 84.2N702.031 G13
VDDQ VSSQ
F10
VDDQ VSSQ VDDQ VSSQ

SC10U6D3V3MX-GP
C7918
H3 H2 H3 H2
VDDQ VSSQ VDDQ VSSQ

1
SC1U6D3V3KX-2GP
C7919

SC1U6D3V3KX-2GP
C7915

SC1U6D3V3KX-2GP
C7916

SC1U6D3V3KX-2GP
C7917
H12 H13 H12 H13

S
VDDQ VSSQ VDDQ VSSQ
K3 K2 K3 K2
K12
VDDQ VSSQ
K13 [76,78,80,81] GPIO10_FBVREF K12
VDDQ VSSQ
K13
OPS

2
VDDQ VSSQ VDDQ VSSQ
L2 M5 L2 M5
VDDQ VSSQ VDDQ VSSQ
L13 M10 L13 M10
M1
VDDQ VSSQ
N1 M1
VDDQ VSSQ
N1 OPS OPS OPS OPS
VDDQ VSSQ VDDQ VSSQ
M3 N3 M3 N3
VDDQ VSSQ VDDQ VSSQ
M12
VDDQ VSSQ
N12 FBVREF Termination M12
VDDQ VSSQ
N12
C M14 N14 M14 N14 C
VDDQ VSSQ VDDQ VSSQ
N5 R1 N5 R1
VDDQ VSSQ VDDQ VSSQ
N10
VDDQ VSSQ
R3 Type FBVREF% Voltage GPU_GPIO10 N10
VDDQ VSSQ
R3
Place close VDD ball Place close VDDQ ball
P1 R4 P1 R4
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0 1D35V_VGA_S0
P3 R11 P3 R11
VDDQ VSSQ VDDQ VSSQ
P12
VDDQ VSSQ
R12 Un-termination 50% 0.749V High P12
VDDQ VSSQ
R12
P14 R14 P14 R14
VDDQ VSSQ VDDQ VSSQ
T1 U1 T1 U1
VDDQ VSSQ VDDQ VSSQ
T3
VDDQ VSSQ
U3 Termination 70% 1.0617V Low T3
VDDQ VSSQ
U3

C7910

C7909

C7921

C7922

C7923

C7925
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
T12 U12 T12 U12
VDDQ VSSQ VDDQ VSSQ

1
T14 U14 T14 U14
VDDQ VSSQ VDDQ VSSQ
FBA_VREFC1 J14 A5 FBA_VREFC1 J14 A5 DY

2
VREFC VPP/NC#A5 VREFC VPP/NC#A5
U5 U5
FBA_VREFD_H A10
VPP/NC#U5 TP_VPPNC5 1 TP7901 TPAD14-OP-GP FBA_VREFD_H A10
VPP/NC#U5 OPS OPS OPS
VREFD VREFD OPS OPS
C7908
SC820P50V2KX-1GP

U10 TP_VPPNC6 1 TP7902 TPAD14-OP-GP U10

VREFD VREFD
1

H5GQ2H24AFR-T2C-GP H5GQ2H24AFR-T2C-GP TP_VPPNC7 1 TP7903 TPAD14-OP-GP

2

TP_VPPNC8 1 TP7904 TPAD14-OP-GP

OPS

[75] FBA_EDC[4..7] FBA_DQM[4..7] [75]

FBA_EDC4 FBA_DQM4
FBA_EDC5 FBA_DQM5
FBA_EDC6 FBA_DQM6
FBA_EDC7 FBA_DQM7

B B

Normal(MF=0) Mirrored(MF=1) FBA_D[32..63] [75]

VRAM3B 2 OF 2 VRAM4B 2 OF 2
FBA_D[32..63] [75]
FBA_CMD22 K4 A4 FBA_D32 FBA_CMD26 K4 A4 FBA_D56
[75]
[75]
FBA_CMD22
FBA_CMD27 FBA_CMD27 H5
A8/A7 OPS DQ0
A2 FBA_D33
[75]
[75]
FBA_CMD26
FBA_CMD23 FBA_CMD23 H5
A8/A7 DQ0
A2 FBA_D57
[75] FBA_CMD26 FBA_CMD26 H4
A9/A1 DQ1
B4 FBA_D34 [75] FBA_CMD22 FBA_CMD22 H4
A9/A1 OPS DQ1
B4 FBA_D58
FBA_CMD23 A10/A0 DQ2 FBA_D35 FBA_CMD27 A10/A0 DQ2 FBA_D59
[75] FBA_CMD23 K5 B2 [75] FBA_CMD27 K5 B2
FBA_CMD25 A11/A6 DQ3 FBA_D36 FBA_CMD25 A11/A6 DQ3 FBA_D60
[75] FBA_CMD25 J5 E4 [75] FBA_CMD25 J5 E4
A12/RFU#J5/NC#J5 DQ4 FBA_D37 A12/RFU#J5/NC#J5 DQ4 FBA_D61
E2 E2
FBA_CMD18 DQ5 FBA_D38 FBA_CMD19 DQ5 FBA_D62
[75] FBA_CMD18 H11 F4 [75] FBA_CMD19 H11 F4
FBA_CMD20 BA0/A2 DQ6 FBA_D39 FBA_CMD17 BA0/A2 DQ6 FBA_D63
[75] FBA_CMD20 K10 F2 [75] FBA_CMD17 K10 F2
FBA_CMD19 BA1/A5 DQ7 FBA_CMD18 BA1/A5 DQ7
[75] FBA_CMD19 K11 A11 [75] FBA_CMD18 K11 A11
FBA_CMD17 BA2/A4 DQ8 FBA_CMD20 BA2/A4 DQ8
[75] FBA_CMD17 H10 A13 [75] FBA_CMD20 H10 A13
BA3/A3 DQ9 BA3/A3 DQ9
B11 B11
FBA_CMD24 DQ10 FBA_CMD24 DQ10
[75] FBA_CMD24 J4 B13 [75] FBA_CMD24 J4 B13
FBA_CMD28 ABI# DQ11 FBA_CMD31 ABI# DQ11
[75] FBA_CMD28 G3 E11 [75] FBA_CMD31 G3 E11
FBA_CMD16 RAS# DQ12 FBA_CMD21 RAS# DQ12
[75] FBA_CMD16 G12 E13 [75] FBA_CMD21 G12 E13 FBA_D[32..63] [75]
FBA_CMD31 CS# DQ13 FBA_CMD28 CS# DQ13
[75] FBA_CMD31 L3 F11 FBA_D[32..63] [75] [75] FBA_CMD28 L3 F11
FBA_CMD21 CAS# DQ14 FBA_CMD16 CAS# DQ14
[75] FBA_CMD21 L12 F13 [75] FBA_CMD16 L12 F13
WE# DQ15 FBA_D48 WE# DQ15 FBA_D40
U11 U11
FBA_CLK1P DQ16 FBA_D49 FBA_CLK1P DQ16 FBA_D41
[75] FBA_CLK1P J12 U13 J12 U13
FBA_CLK1N CK DQ17 FBA_D50 FBA_CLK1N CK DQ17 FBA_D42
[75] FBA_CLK1N J11 T11 J11 T11
FBA_CMD30 CK# DQ18 FBA_D51 FBA_CMD30 CK# DQ18 FBA_D43
[75] FBA_CMD30 J3 T13 [75] FBA_CMD30 J3 T13
CKE# DQ19 CKE# DQ19
1

N11 FBA_D52 N11 FBA_D44

FBA_DQM4 DQ20 FBA_D53 R7906 FBA_DQM7 DQ20 FBA_D45
D2 N13 R7908 D2 N13
DBI0# DQ21 FBA_D54 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBA_D46
D13 M11 D13 M11
FBA_DQM6 DBI1# DQ22 FBA_D55 FBA_DQM5 DBI1# DQ22 FBA_D47
P13 M13 P13 M13
P2
DBI2# DQ23
U4 OPS OPS P2
DBI2# DQ23
U4
2

DBI3# DQ24 FBA_CLK1_MIDPT DBI3# DQ24

U2 U2
FBA_CMD29 DQ25 FBA_CMD29 DQ25
[75] FBA_CMD29 J2 T4 [75] FBA_CMD29 J2 T4
RESET# DQ26 RESET# DQ26
2

T2 T2
FBA_SEN2 DQ27 C7901 FBA_SEN2 DQ27
J10 N4 J10 N4
FBA_ZQ2 J13
SEN DQ28
N2 SCD01U16V2KX-3GP OPS FBA_ZQ3 J13
SEN DQ28
N2
1

FBA_MF3 ZQ DQ29 FBA_MF4 ZQ DQ29

J1 M4 2 1 J1 M4
MF DQ30
M2
1D35V_VGA_S0 OPS
R7910 1KR2J-1-GP MF DQ30
M2
DQ31 DQ31
1

1
R7912

R7911

R7909

R7913
121R2F-GP

1KR2J-1-GP

1KR2J-1-GP

121R2F-GP

FBA_WCK45 D4 FBA_WCK67 D4
A FBA_WCK45# WCK01 FBA_EDC4 FBA_WCK67# D5 WCK01 FBA_EDC7 A
D5 C2 C2
WCK01# EDC0 WCK01# EDC0
C13 C13
FBA_WCK67 P4
EDC1
R13 FBA_EDC6 OPS OPS FBA_WCK45 P4
EDC1
R13 FBA_EDC5
OPS OPS FBA_WCK67# P5
WCK23 EDC2
R2 FBA_WCK45# P5
WCK23 EDC2
R2
2

WCK23# EDC3 WCK23# EDC3

<Core Design>
H5GQ2H24AFR-T2C-GP [75] FBA_WCK67 H5GQ2H24AFR-T2C-GP
[75] FBA_WCK67#
[75] FBA_WCK45 Wistron Corporation
[75] FBA_WCK45# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 79 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
1D35V_VGA_S0
VRAM6A 1 OF 2 1D35V_VGA_S0
1D35V_VGA_S0 Place close VDD ball
VRAM5A 1 OF 2 C5 B5
Frame Buffer Patition B-Lower Half C10
VDD OPS VSS
B10
VDD VSS

SC10U6D3V3MX-GP
C8023
C5 B5 D11 D10
VDD OPS VSS VDD VSS

1
1D35V_VGA_S0

SC1U6D3V3KX-2GP
C8021

SC1U6D3V3KX-2GP
C8024

SC1U6D3V3KX-2GP
C8002

SC1U6D3V3KX-2GP
C8003
C10 B10 G1 G5
VDD VSS VDD VSS
D11 D10 G4 G10
G1
VDD VSS
G5 G11
VDD VSS
H1 OPS OPS OPS OPS OPS

2
D VDD VSS VDD VSS D
G4 G10 G14 H14
VDD VSS VDD VSS
G11 H1 L1 K1
VDD VSS VDD VSS
G14 H14 L4 K14
VDD VSS VDD VSS

1
L1 K1 L11 L5
VDD VSS R8005 R8004 VDD VSS
L4 K14 L14 L10
VDD VSS 549R2F-GP VDD VSS
L11
L14
VDD VSS
L5
L10
OPS OPS549R2F-GP P11
R5
VDD VSS
P10
T5
VDD VSS VDD VSS 1D35V_VGA_S0
P11 P10 R10 T10
Place close VDD ball

2
1D35V_VGA_S0 VDD VSS FBB_VREFC0 FBB_VREFD_L 1D35V_VGA_S0 VDD VSS
R5 T5
VDD VSS
R10 T10 B1 A1
VDD VSS VDDQ VSSQ

1
SC820P50V2KX-1GP
C8022

1K33R2F-GP
R8007

931R2F-1-GP
R8003

931R2F-1-GP
R8009

1K33R2F-GP
R8006

SC820P50V2KX-1GP
C8020
B3 A3
VDDQ VSSQ

SCD1U10V2KX-4GP
C8014

SCD1U10V2KX-4GP
C8015

SCD1U10V2KX-4GP
C8016

SCD1U10V2KX-4GP
C8017

SCD1U10V2KX-4GP
C8018

SCD1U10V2KX-4GP
C8019
B1 A1 B12 A12
VDDQ VSSQ VDDQ VSSQ

1
B3 A3 B14 A14
B12
VDDQ VSSQ
A12 OPS OPS OPS OPS OPS OPS D1
VDDQ VSSQ
C1
OPS OPS OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ
B14 A14 D3 C3

2
VDDQ VSSQ VDDQ VSSQ
D1 C1 D12 C4
VDDQ VSSQ VDDQ VSSQ
D3 C3 D14 C11
VDDQ VSSQ VDDQ VSSQ
D12 C4 E5 C12
VDDQ VSSQ FBB_VREF_FET_L VDDQ VSSQ
D14 C11 E10 C14
VDDQ VSSQ VDDQ VSSQ
E5 C12 F1 E1
VDDQ VSSQ VDDQ VSSQ
E10 C14 F3 E3
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0
F1 E1 F12 E12
Place close VDDQ ball

D
VDDQ VSSQ VDDQ VSSQ
F3 E3 F14 E14
VDDQ VSSQ Q8001 VDDQ VSSQ
F12 E12 G2 F5
VDDQ VSSQ VDDQ VSSQ
F14 E14 G13 F10
VDDQ VSSQ OPS 2N7002K-2-GP VDDQ VSSQ

SC10U6D3V3MX-GP
C8007
G2 F5 84.2N702.J31 H3 H2
VDDQ VSSQ VDDQ VSSQ

1
SC1U6D3V3KX-2GP
C8008

SC1U6D3V3KX-2GP
C8004

SC1U6D3V3KX-2GP
C8005

SC1U6D3V3KX-2GP
C8006
G13 F10 H12 H13
VDDQ VSSQ VDDQ VSSQ
H3
VDDQ VSSQ
H2 2ND = 84.2N702.031 K3
VDDQ VSSQ
K2
OPS OPS OPS OPS OPS
H12 H13 K12 K13

2
VDDQ VSSQ VDDQ VSSQ
K3 K2 L2 M5

S
VDDQ VSSQ VDDQ VSSQ
K12 K13 L13 M10
VDDQ VSSQ VDDQ VSSQ
L2 M5 [76,78,79,81] GPIO10_FBVREF M1 N1
VDDQ VSSQ VDDQ VSSQ
L13 M10 M3 N3
VDDQ VSSQ VDDQ VSSQ
M1 N1 M12 N12
VDDQ VSSQ VDDQ VSSQ
M3 N3 M14 N14
VDDQ VSSQ VDDQ VSSQ
M12
VDDQ VSSQ
N12 FBVREF Termination N5
VDDQ VSSQ
R1
M14 N14 N10 R3
N5
VDDQ VSSQ
R1 P1
VDDQ VSSQ
R4
Place close VDD ball Place close VDDQ ball
C VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0 1D35V_VGA_S0 C
N10
VDDQ VSSQ
R3 Type FBVREF% Voltage GPU_GPIO10 P3
VDDQ VSSQ
R11
P1 R4 P12 R12
VDDQ VSSQ VDDQ VSSQ
P3 R11 P14 R14
VDDQ VSSQ VDDQ VSSQ
P12
VDDQ VSSQ
R12 Un-termination 50% 0.749V High T1
VDDQ VSSQ
U1
P14 R14 T3 U3
VDDQ VSSQ VDDQ VSSQ

C8001

C8009

C8010

C8011

C8012

C8013
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
T1 U1 T12 U12
VDDQ VSSQ VDDQ VSSQ

1
T3
VDDQ VSSQ
U3 Termination 70% 1.0617V Low T14
VDDQ VSSQ
U14
T12 U12
T14
VDDQ VSSQ
U14 FBB_VREFC0 J14 A5
OPS OPS OPS OPS OPS OPS

2
VDDQ VSSQ VREFC VPP/NC#A5
U5
FBB_VREFC0 FBB_VREFD_L VPP/NC#U5 TP_VPPNC11 TP8003 TPAD14-OP-GP
J14 A5 A10 1
VREFC VPP/NC#A5 VREFD TP_VPPNC12 TP8004 TPAD14-OP-GP
U5 U10 1
FBB_VREFD_L VPP/NC#U5 TP_VPPNC9 TP8001 TPAD14-OP-GP VREFD
A10 1
VREFD TP_VPPNC10 TP8002 TPAD14-OP-GP
U10 1
VREFD
C8026
SC820P50V2KX-1GP

H5GQ2H24AFR-T2C-GP
1

H5GQ2H24AFR-T2C-GP
OPS
2

Normal(MF=0)

[75] FBB_EDC[0..3]
FBB_EDC0
FBB_DQM[0..3] [75]
FBB_EDC1 FBB_DQM0
FBB_EDC2 FBB_DQM1
FBB_EDC3 FBB_DQM2
FBB_DQM3

Mirrored(MF=1)
2 OF 2 FBB_D[0..31] [75]
B VRAM6B B
VRAM5B 2 OF 2
FBB_D[0..31] [75]
[75] FBB_CMD10 FBB_CMD10 K4 A4 FBB_D24
[75] FBB_CMD6 FBB_CMD6 K4 A4 FBB_D0 [75] FBB_CMD7 FBB_CMD7 H5
A8/A7 OPS DQ0
A2 FBB_D25
[75] FBB_CMD11 FBB_CMD11 H5
A8/A7 OPS DQ0
A2 FBB_D1 [75] FBB_CMD6 FBB_CMD6 H4
A9/A1 DQ1
B4 FBB_D26
FBB_CMD10 A9/A1 DQ1 FBB_D2 FBB_CMD11 A10/A0 DQ2 FBB_D27
[75] FBB_CMD10 H4 B4 [75] FBB_CMD11 K5 B2
FBB_CMD7 A10/A0 DQ2 FBB_D3 FBB_CMD9 A11/A6 DQ3 FBB_D28
[75] FBB_CMD7 K5 B2 [75] FBB_CMD9 J5 E4
FBB_CMD9 A11/A6 DQ3 FBB_D4 A12/RFU#J5/NC#J5 DQ4 FBB_D29
[75] FBB_CMD9 J5 E4 E2
A12/RFU#J5/NC#J5 DQ4 FBB_D5 FBB_CMD3 DQ5 FBB_D30
E2 [75] FBB_CMD3 H11 F4
FBB_CMD2 DQ5 FBB_D6 FBB_CMD1 BA0/A2 DQ6 FBB_D31
[75] FBB_CMD2 H11 F4 [75] FBB_CMD1 K10 F2
FBB_CMD4 BA0/A2 DQ6 FBB_D7 FBB_CMD2 BA1/A5 DQ7
[75] FBB_CMD4 K10 F2 [75] FBB_CMD2 K11 A11
FBB_CMD3 BA1/A5 DQ7 FBB_CMD4 BA2/A4 DQ8
[75] FBB_CMD3 K11 A11 [75] FBB_CMD4 H10 A13
FBB_CMD1 BA2/A4 DQ8 BA3/A3 DQ9
[75] FBB_CMD1 H10 A13 B11
BA3/A3 DQ9 FBB_CMD8 DQ10
B11 [75] FBB_CMD8 J4 B13
FBB_CMD8 DQ10 FBB_CMD15 ABI# DQ11
[75] FBB_CMD8 J4 B13 [75] FBB_CMD15 G3 E11
FBB_CMD12 ABI# DQ11 FBB_CMD5 RAS# DQ12
[75] FBB_CMD12 G3 E11 [75] FBB_CMD5 G12 E13 FBB_D[0..31] [75]
FBB_CMD0 RAS# DQ12 FBB_CMD12 CS# DQ13
[75] FBB_CMD0 G12 E13 FBB_D[0..31] [75] [75] FBB_CMD12 L3 F11
FBB_CMD15 CS# DQ13 FBB_CMD0 CAS# DQ14
[75] FBB_CMD15 L3 F11 [75] FBB_CMD0 L12 F13
FBB_CMD5 CAS# DQ14 WE# DQ15 FBB_D8
[75] FBB_CMD5 L12 F13 U11
WE# DQ15 FBB_D16 FBB_CLK0P DQ16 FBB_D9
U11 J12 U13
FBB_CLK0P DQ16 FBB_D17 FBB_CLK0N CK DQ17 FBB_D10
[75] FBB_CLK0P J12 U13 J11 T11
FBB_CLK0N CK DQ17 FBB_D18 FBB_CMD14 CK# DQ18 FBB_D11
[75] FBB_CLK0N J11 T11 [75] FBB_CMD14 J3 T13
CK# DQ18 CKE# DQ19
1

[75] FBB_CMD14 FBB_CMD14 J3 T13 FBB_D19 N11 FBB_D12

CKE# DQ19 FBB_D20 R8002 R8001 FBB_DQM3 DQ20 FBB_D13
N11 D2 N13
FBB_DQM0 DQ20 FBB_D21 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBB_D14
D2 N13 D13 M11
DBI0# DQ21 FBB_D22 FBB_DQM1 DBI1# DQ22 FBB_D15
D13 M11 P13 M13
FBB_DQM2 P13
DBI1# DQ22
M13 FBB_D23 OPS OPS P2
DBI2# DQ23
U4
2

DBI2# DQ23 DBI3# DQ24

P2 U4 U2
DBI3# DQ24 FBB_CLK0_MIDPT FBB_CMD13 DQ25
U2 [75] FBB_CMD13 J2 T4
FBB_CMD13 DQ25 RESET# DQ26
[75] FBB_CMD13 J2 T4 T2
RESET# DQ26 FBB_SEN0 DQ27
T2 J10 N4
DQ27 SEN DQ28
2

FBB_SEN0 J10 N4 FBB_ZQ1 J13 N2

FBB_ZQ0 J13
SEN DQ28
N2 C8025 OPS 1D35V_VGA_S0 2
OPS 1 FBB_MF2 J1
ZQ DQ29
M4
FBB_MFB ZQ DQ29 SCD01U16V2KX-3GP R8012 1KR2J-1-GP MF DQ30
J1 M4 M2
1

MF DQ30 DQ31
2

1
R8010

R8013
1KR2J-1-GP

121R2F-GP

M2 FBB_WCK23 D4
DQ31 WCK01
1

2
R8008

R8011
121R2F-GP

1KR2J-1-GP

FBB_WCK01 D4 FBB_WCK23# D5 C2 FBB_EDC3

FBB_WCK01# WCK01 WCK01# EDC0
D5 C2 FBB_EDC0 C13
WCK01# EDC0
C13
OPS OPS FBB_WCK01 P4
EDC1
R13 FBB_EDC1
A OPS OPS FBB_WCK23 P4
EDC1
R13 FBB_EDC2 FBB_WCK01# P5
WCK23 EDC2
R2 A
1

FBB_WCK23# WCK23 EDC2 WCK23# EDC3

P5 R2
2

WCK23# EDC3
[75] FBB_WCK23 H5GQ2H24AFR-T2C-GP
H5GQ2H24AFR-T2C-GP [75] FBB_WCK23# <Core Design>
[75] FBB_WCK01
[75] FBB_WCK01#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 80 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

1D35V_VGA_S0 VRAM8A 1 OF 2 1D35V_VGA_S0

1D35V_VGA_S0 VRAM7A 1 OF 2 Place close VDD ball
Frame Buffer Patition B-Upper Half C5
VDD OPS VSS
B5
C5 B5 C10 B10
VDD OPS VSS VDD VSS

SC10U6D3V3MX-GP
C8107
C10 B10 D11 D10
VDD VSS VDD VSS

1
1D35V_VGA_S0

SC1U6D3V3KX-2GP
C8124

SC1U6D3V3KX-2GP
C8104

SC1U6D3V3KX-2GP
C8105

SC1U6D3V3KX-2GP
C8106
D11 D10 G1 G5
VDD VSS VDD VSS
G1 G5 G4 G10
G4
VDD VSS
G10 G11
VDD VSS
H1 OPS OPS OPS OPS OPS

2
D VDD VSS VDD VSS D
G11 H1 G14 H14
VDD VSS VDD VSS

1
G14 H14 L1 K1
VDD VSS R8103 R8109 VDD VSS
L1 K1 L4 K14
VDD VSS 549R2F-GP 549R2F-GP VDD VSS
L4 K14 L11 L5
L11
VDD VSS
L5 OPS OPS L14
VDD VSS
L10
VDD VSS VDD VSS
L14 L10 P11 P10

2
VDD VSS FBB_VREFC1 FBB_VREFD_H VDD VSS
P11 P10 R5 T5
VDD VSS VDD VSS 1D35V_VGA_S0
R5 T5 R10 T10
VDD VSS VDD VSS Place close VDD ball

1
1D35V_VGA_S0 1D35V_VGA_S0

SC820P50V2KX-1GP
C8102

1K33R2F-GP
R8104

931R2F-1-GP
R8102

931R2F-1-GP
R8105

1K33R2F-GP
R8101

SC820P50V2KX-1GP
C8103
R10 T10
VDD VSS

1
B1 A1
VDDQ VSSQ
B1 A1 B3 A3
VDDQ VSSQ OPS OPS OPS OPS OPS OPS VDDQ VSSQ

SCD1U10V2KX-4GP
C8110

SCD1U10V2KX-4GP
C8111

SCD1U10V2KX-4GP
C8112

SCD1U10V2KX-4GP
C8113

SCD1U10V2KX-4GP
C8119

SCD1U10V2KX-4GP
C8121
B3 A3 B12 A12

2
VDDQ VSSQ VDDQ VSSQ

1
B12 A12 B14 A14

2
VDDQ VSSQ VDDQ VSSQ
B14 A14 D1 C1
D1
VDDQ VSSQ
C1 D3
VDDQ VSSQ
C3 OPS OPS OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ
D3 C3 D12 C4
VDDQ VSSQ FBB_VREF_FET_H VDDQ VSSQ
D12 C4 D14 C11
VDDQ VSSQ VDDQ VSSQ
D14 C11 E5 C12
VDDQ VSSQ VDDQ VSSQ
E5 C12 E10 C14

D
VDDQ VSSQ VDDQ VSSQ
E10 C14 F1 E1
VDDQ VSSQ Q8101 VDDQ VSSQ
F1 E1 F3 E3
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0
F3 E3 F12 E12
F12
VDDQ VSSQ
E12
OPS 2N7002K-2-GP
F14
VDDQ VSSQ
E14
Place close VDDQ ball
F14
VDDQ VSSQ
E14
84.2N702.J31 G2
VDDQ VSSQ
F5
VDDQ VSSQ VDDQ VSSQ
G2
VDDQ VSSQ
F5 2ND = 84.2N702.031 G13
VDDQ VSSQ
F10

SC10U6D3V3MX-GP
C8117
G13 F10 H3 H2
VDDQ VSSQ VDDQ VSSQ

1
SC1U6D3V3KX-2GP
C8118

SC1U6D3V3KX-2GP
C8114

SC1U6D3V3KX-2GP
C8115

SC1U6D3V3KX-2GP
C8116
H3 H2 H12 H13

S
VDDQ VSSQ VDDQ VSSQ
H12 H13 K3 K2
K3
VDDQ VSSQ
K2 [76,78,79,80] GPIO10_FBVREF K12
VDDQ VSSQ
K13 OPS OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ
K12 K13 L2 M5
VDDQ VSSQ VDDQ VSSQ
L2 M5 L13 M10
VDDQ VSSQ VDDQ VSSQ
L13 M10 M1 N1
VDDQ VSSQ VDDQ VSSQ
M1 N1 M3 N3
VDDQ VSSQ VDDQ VSSQ
M3
VDDQ VSSQ
N3 FBVREF Termination M12
VDDQ VSSQ
N12
M12 N12 M14 N14
VDDQ VSSQ VDDQ VSSQ
M14 N14 N5 R1
VDDQ VSSQ VDDQ VSSQ
N5
VDDQ VSSQ
R1 Type FBVREF% Voltage GPU_GPIO10 N10
VDDQ VSSQ
R3
Place close VDD ball Place close VDDQ ball
C N10 R3 P1 R4 C
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0 1D35V_VGA_S0
P1 R4 P3 R11
VDDQ VSSQ VDDQ VSSQ
P3
VDDQ VSSQ
R11 Un-termination 50% 0.749V High P12
VDDQ VSSQ
R12
P12 R12 P14 R14
VDDQ VSSQ VDDQ VSSQ
P14 R14 T1 U1
VDDQ VSSQ VDDQ VSSQ
T1
VDDQ VSSQ
U1 Termination 70% 1.0617V Low T3
VDDQ VSSQ
U3

C8109

C8108

C8120

C8122

C8123

C8125
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
T3 U3 T12 U12
VDDQ VSSQ VDDQ VSSQ

1
T12 U12 T14 U14
VDDQ VSSQ VDDQ VSSQ
T14 U14
VDDQ VSSQ FBB_VREFC1 J14 A5
DY OPS OPS OPS OPS OPS

2
FBB_VREFC1 VREFC VPP/NC#A5
J14 A5 U5
VREFC VPP/NC#A5 FBB_VREFD_H VPP/NC#U5
U5 A10
FBB_VREFD_H VPP/NC#U5 TP_VPPNC13 TP8101 TPAD14-OP-GP VREFD
A10 1 U10
VREFD TP_VPPNC14 TP8102 TPAD14-OP-GP VREFD
U10 1
VREFD
C8126
SC820P50V2KX-1GP
1

H5GQ2H24AFR-T2C-GP TP_VPPNC15
1 TP8103 TPAD14-OP-GP
H5GQ2H24AFR-T2C-GP TP_VPPNC16
1 TP8104 TPAD14-OP-GP
OPS
2

Mirrored(MF=1)
Normal(MF=0)

FBB_DQM[4..7] [75]
FBB_DQM4
[75] FBB_EDC[4..7]
FBB_EDC4 FBB_DQM5
FBB_EDC5 FBB_DQM6
B FBB_EDC6 FBB_DQM7 B
FBB_EDC7

2 OF 2 FBB_D[32..63] [75]
VRAM8B
VRAM7B 2 OF 2
FBB_D[32..63] [75]
[75] FBB_CMD26 FBB_CMD26 K4 A4 FBB_D56
FBB_CMD22 K4 A4 FBB_D32 FBB_CMD23 H5
A8/A7 OPS DQ0
A2 FBB_D57
[75]
[75]
FBB_CMD22
FBB_CMD27 FBB_CMD27 H5
A8/A7 OPS DQ0
A2 FBB_D33
[75]
[75]
FBB_CMD23
FBB_CMD22 FBB_CMD22 H4
A9/A1 DQ1
B4 FBB_D58
FBB_CMD26 A9/A1 DQ1 FBB_D34 FBB_CMD27 A10/A0 DQ2 FBB_D59
[75] FBB_CMD26 H4 B4 [75] FBB_CMD27 K5 B2
FBB_CMD23 A10/A0 DQ2 FBB_D35 FBB_CMD25 A11/A6 DQ3 FBB_D60
[75] FBB_CMD23 K5 B2 [75] FBB_CMD25 J5 E4
FBB_CMD25 A11/A6 DQ3 FBB_D36 A12/RFU#J5/NC#J5 DQ4 FBB_D61
[75] FBB_CMD25 J5 E4 E2
A12/RFU#J5/NC#J5 DQ4 FBB_D37 FBB_CMD19 DQ5 FBB_D62
E2 [75] FBB_CMD19 H11 F4
FBB_CMD18 DQ5 FBB_D38 FBB_CMD17 BA0/A2 DQ6 FBB_D63
[75] FBB_CMD18 H11 F4 [75] FBB_CMD17 K10 F2
FBB_CMD20 BA0/A2 DQ6 FBB_D39 FBB_CMD18 BA1/A5 DQ7
[75] FBB_CMD20 K10 F2 [75] FBB_CMD18 K11 A11
FBB_CMD19 BA1/A5 DQ7 FBB_CMD20 BA2/A4 DQ8
[75] FBB_CMD19 K11 A11 [75] FBB_CMD20 H10 A13
FBB_CMD17 BA2/A4 DQ8 BA3/A3 DQ9
[75] FBB_CMD17 H10 A13 B11
BA3/A3 DQ9 FBB_CMD24 DQ10
B11 [75] FBB_CMD24 J4 B13
FBB_CMD24 DQ10 FBB_CMD31 ABI# DQ11
[75] FBB_CMD24 J4 B13 [75] FBB_CMD31 G3 E11
FBB_CMD28 ABI# DQ11 FBB_CMD21 RAS# DQ12
[75] FBB_CMD28 G3 E11 [75] FBB_CMD21 G12 E13 FBB_D[32..63] [75]
FBB_CMD16 RAS# DQ12 FBB_CMD28 CS# DQ13
[75] FBB_CMD16 G12 E13 [75] FBB_CMD28 L3 F11
FBB_CMD31 CS# DQ13 FBB_CMD16 CAS# DQ14
[75] FBB_CMD31 L3 F11 FBB_D[32..63] [75] [75] FBB_CMD16 L12 F13
FBB_CMD21 CAS# DQ14 WE# DQ15 FBB_D40
[75] FBB_CMD21 L12 F13 U11
WE# DQ15 FBB_D48 FBB_CLK1P DQ16 FBB_D41
U11 J12 U13
FBB_CLK1P DQ16 FBB_D49 FBB_CLK1N CK DQ17 FBB_D42
[75] FBB_CLK1P J12 U13 J11 T11
FBB_CLK1N CK DQ17 FBB_D50 FBB_CMD30 CK# DQ18 FBB_D43
[75] FBB_CLK1N J11 T11 [75] FBB_CMD30 J3 T13
CK# DQ18 CKE# DQ19
1

[75] FBB_CMD30 FBB_CMD30 J3 T13 FBB_D51 N11 FBB_D44

CKE# DQ19 FBB_D52 R8108 R8110 FBB_DQM7 DQ20 FBB_D45
N11 D2 N13
FBB_DQM4 DQ20 FBB_D53 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBB_D46
D2 N13 D13 M11
DBI0# DQ21 FBB_D54 FBB_DQM5 DBI1# DQ22 FBB_D47
D13 M11 P13 M13
FBB_DQM6 P13
DBI1# DQ22
M13 FBB_D55 OPS OPS P2
DBI2# DQ23
U4
2

DBI2# DQ23 FBB_CLK1_MIDPT DBI3# DQ24

P2 U4 U2
DBI3# DQ24 FBB_CMD29 DQ25
U2 [75] FBB_CMD29 J2 T4
DQ25 RESET# DQ26
2

FBB_CMD29 J2 T4 T2
[75] FBB_CMD29 RESET# DQ26
T2 C8101 OPS FBB_SEN2 J10
DQ27
N4
FBB_SEN2 DQ27 SCD01U16V2KX-3GP FBB_ZQ3 SEN DQ28
J10 N4 J13 N2
1

A FBB_ZQ2 SEN DQ28 FBB_MF4 ZQ DQ29 A

J13 N2 2 1 J1 M4
FBB_MF3 J1
ZQ DQ29
M4
1D35V_VGA_S0
R8112 OPS
1KR2J-1-GP MF DQ30
M2
MF DQ30 DQ31
2

1
R8111

R8114
1KR2J-1-GP

121R2F-GP

M2 FBB_WCK67 D4
DQ31 WCK01
1

2
R8106

R8113
121R2F-GP

1KR2J-1-GP

FBB_WCK45 D4 FBB_WCK67# D5 C2 FBB_EDC7

FBB_WCK45# WCK01 FBB_EDC4 WCK01# EDC0
D5 C2 C13
WCK01# EDC0
C13 OPS OPS FBB_WCK45 P4
EDC1
R13 FBB_EDC5 <Core Design>
OPS OPS FBB_WCK67 P4
EDC1
R13 FBB_EDC6 FBB_WCK45# P5
WCK23 EDC2
R2
1

FBB_WCK67# WCK23 EDC2 WCK23# EDC3

P5 R2
Wistron Corporation
2

WCK23# EDC3
[75] FBB_WCK67 H5GQ2H24AFR-T2C-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
H5GQ2H24AFR-T2C-GP [75] FBB_WCK67# Taipei Hsien 221, Taiwan, R.O.C.
[75] FBB_WCK45
[75] FBB_WCK45# Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
Custom
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 81 of 101
5 4 3 2 1
 5 4 3 2 1

5V_S5

1
SSID = PWR.Plane.Regulator_vga_core OPS
PR8264
2D2R2J-GP

5V_S5

2
PWR_VGA_CORE_VCC PU8201
PC8212
EN

1
PC8211 15 21 1 2
3D3V_VGA_S0
OPS SC1U6D3V2KX-GP VCC PVCC OPS
SC4D7U6D3V2MX-GP-U

2
25 22
PR8263 1 PWR_VGA_CORE_EN GND PGND
2 10KR2J-3-GP
DY PR8225
PC8238
81172_AGND
81172_AGND
OPS 2 PWR_VGA_CORE_HG1 0R3J-0-U-GP PC8230 OPS
HG1

1
1 PWR_VGA_CORE_BST1 2 1PWR_VGA_CORE_BST1_R 1 2PWR_VGA_CORE_SW1
OPS [15,24,83] DGPU_PWROK BST1 OPS

SCD1U10V2KX-4GP
PWR_VGA_CORE_EN 3 24 PWR_VGA_CORE_SW1
PR8265 EN PH1
D OPS 10KR2J-3-GP PWR_VGA_CORE_PSI 4 23 PWR_VGA_CORE_LG1 SCD1U25V3KX-GP D

2
PR8213 PSI LG1
[15,83] DGPU_PWR_EN 1 2 3D3V_VGA_S0 1 2 16
PWR_VGA_CORE_TALERT# 14 PGOOD
1 OPS 2
0R2J-2-GP 1 PR8215 PR8216 21KR2F-GP
[76] VIDEO_THERM_OVERT# PR8214 1 DY 22 0R0402-PAD-2-GP PWR_VGA_CORE_VID 5
TALERT#
17 PWR_VGA_CORE_HG2 PC8237 OPS
10KR2J-3-GP [76] VGA_CORE_VID OPS VID HG2
18 PWR_VGA_CORE_BST2 2 1PWR_VGA_CORE_BST2_R 1 2PWR_VGA_CORE_SW2
OPS PWR_VGA_CORE_TSENSE 13
BST2
19 PWR_VGA_CORE_SW2 PR8230 OPS PR8228
TSNS PH2 PWR_VGA_CORE_LG2
0307 DY PR8263, POP PR8265 LG2
20 0R3J-0-U-GP SCD1U25V3KX-GP 0R0402-PAD-2-GP
PR8210
1
OPS 2

1
0521 change resistor value from 12K ohm to 10K PC8216 PWR_VGA_CORE_VREF 8 10R2J-2-GP

1
PR8268 SCD1U10V2KX-4GP PWR_VGA_CORE_REFIN VREF PWR_VGA_CORE_FBRTN
7 10 1
NTC-100K-10-GP PWR_VGA_CORE_VIDBUF 6 REFIN FBRTN
11 PWR_VGA_CORE_FB OPS2 GND_SENSE [73]
B=4250K OPS OPS R3 9
VIDBUF FB
12 PC8218 PR8206 OPS
OPS

1
FS
PWR_VGA_CORE_FS COMP
1 2 1 2
OPS 1 2 1 2 PC8215 1225 change P/N

2
3D3V_VGA_S0 PR8204 PR8207 PR8267 49D9R2F-GP SC47P50V2JN-3GP C8232
PSI NTC close Phase1 MOSFET
PR8202
3K92R2F-GP
OPS 2KR2F-3-GP 20KR2F-L-GP NCP81172MNTXG-1-GP-U 82KR2F-1-GP SC100P50V2JN-L-GP OPS SC1KP25V2JX-GP

2
1
PC8217
OPS OPS 74.81172.A73
1

R1 PR8208 PWR_VGA_CORE_COMP 2 1 OPS 1 2 1

OPS2

2
VGA_SENSE [73]
PR8258
VGA_R1R3
OPS 34KR2F-GP SC10P50V2JN-4GP PR8209
10KR2F-2-GP
OPS 10KR2J-3-GP 81172_AGND OPS PR8205
OPS PR8227

2
1 PR8211 2 0R0402-PAD-2-GP 1 2
OPS VGA_CORE
2

PR8257 R2 OPS
1 2 PWR_VGA_CORE_PSI 10R2J-2-GP
[76] VGA_CORE_PSI OPS 81172_AGND

1
0R0402-PAD-2-GP 20KR2F-L-GP
PR8212 1 2 0R0402-PAD-2-GP
PC8214 OPS PC8222 OPS

2
1

SCD01U50V2KX-1GP
PR8259
DY DY
SCD1U10V2KX-4GP

0R2J-2-GP 81172_AGND PWR_VGA_CORE_REFIN

2

C 81172_AGND

1
R4
2

PR8203
OPS

1
18KR2F-GP PC8219
OPS SC2700P50V2KX-1-GP N14P-GT iis ConfigB

2
VGA_R4R5

1
R5
PR8201
0R0402-PAD-2-GP
OPS
C 81172_AGND C

2
81172_AGND
VGA type Config Design EDP-peak OCP R1/PR8207 R2/PR8211 R3/PR8204 R4/PR8203 R5/PR8201 C/PC8219
Current
N14P-LP B 25A 35A 38.5A<OCP<45.5A 20K 20K 2K 18K 0 2.7nF

N14P-GE B 27A 40A 44A<OCP<52A 20K 20K 2K 18K 0 2.7nF

N14P-GS B 38A 60A 66A<OCP<78A 20K 20K 2K 18K 0 2.7nF

N14P-GT B 45A 75A 82.5A<OCP<97.5A 20K 20K 2K 18K 0 2.7nF

Phase2 N14P-GV B 24A 35A 38.5A<OCP<45.5A 20K 20K 2K 18K 0 2.7nF

DCBATOUT

N14P-GV2 B 32A 55A 60.5A<OCP<71.5A 20K 20K 2K 18K 0 2.7nF

OPS OPS OPS OPS OPS N14M-GS B 26A 45A 49.5A<OCP<58.5A 20K 20K 2K 18K 0 2.7nF
1

1
SC10U25V5KX-GP

PC8224 PC8223 PC8235

1
SC10U25V5KX-GP

SC10U25V5KX-GP
PC8234 PC8236 N14M-LP B 22A 35A 38.5A<OCP<45.5A 20K 20K 2K 18K 0 2.7nF

SC10U25V5KX-GP
SCD1U25V3KX-GP
2

2
5
6
7
8
SIRA14DP-T1-GE3-GP

N14M-GL C 24.33A 35.42A 38.96A<OCP<46.04A 39K 30K 3K 24K 3K 1.8nF

D
D
D
D

PU8205
OPS N14M-GE C 35A 40.89A 44.98A<OCP<53.16A 39K 30K 3K 24K 3K 1.8nF
G

4
S
S
S

N14E-GTX A 95A 125A 137.5A<OCP<162.5A 39K 39K 1.5K 30K 1.5K 1.5nF
3
2
1

B PWR_VGA_CORE_HG2 B
PWR_VGA_CORE_SW2 N14E-GS B 65.16A 87.87A 96.66A<OCP<114.2A 20K 20K 2K 18K 0 2.7nF
PWR_VGA_CORE_LG2 PL8202 VGA_CORE

1 OPS 2 N14E-GE-B B 65.37A 98.6A 108.5A<OCP<128.2A 20K 20K 2K 18K 0 2.7nF

COIL-D15UH-2-GP
2

PT8212 N14E-GE B 65.37A 98.6A 108.5A<OCP<128.2A 20K 20K 2K 18K 0 2.7nF

1
PR8229 SE470UF2VDM-GP
ESR=6mohm
Phase1 DY 2D2R5F-2-GP
OPS N14E-GL B 46.35A 71.83A 79.01A<OCP<93.98A 20K 20K 2K 18K 0 2.7nF

2
VGA_SNB2 1
5
6
7
8

5
6
7
8
SIRA12DP-T1-GE3-GP

SIRA12DP-T1-GE3-GP
D
D
D
D

D
D
D
D

PU8207 PU8209

DCBATOUT OPS OPS

G

4 4
1
S
S
S

S
S
S

PC8233
OPS OPS OPS OPS OPS DY
3
2
1

3
2
1

SC330P50V2KX-3GP
2
1

PC8220 PC8221 PC8229

1

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

PC8228 PC8227
SC10U25V5KX-GP

SCD1U25V3KX-GP
2

2
5
6
7
8
SIRA14DP-T1-GE3-GP

2
D
D
D
D

PU8202
OPS
G

4
S
S
S
3
2
1

PWR_VGA_CORE_HG1
PWR_VGA_CORE_SW1 VGA_CORE
PWR_VGA_CORE_LG1 PL8201

1 OPS 2 A00 0621

COIL-D15UH-2-GP
PT8210 PT8211
2

1
SE330U2D5VM-14-GP

SE330U2D5VM-14-GP
5
6
7
8

5
6
7
8

A A
SIRA12DP-T1-GE3-GP

SIRA12DP-T1-GE3-GP

PR8226
D
D
D
D

D
D
D
D

PU8206 PU8208 2D2R5F-2-GP OPS OPS

2

OPS OPS DY
1
G

VGA_SNB1

4 4
<Core Design>
S
S
S

S
S
S
3
2
1

3
2
1

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

PC8231 Inductor: CHIP IND 0.22UH M PCMC063T-R22MN/ 2.8mohm/ Isat =40A rms /68.R2210.10V Taipei Hsien 221, Taiwan, R.O.C.
SC330P50V2KX-3GP O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L
DY Title
2

H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037

L/S: SIRA12DP-T1-GE3 / 4.4mohm/6mOhm@4.5Vgs/ 84.SRA12.037
NCP81172_VGA_CORE
Size Document Number Rev
A2 Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 82 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_3p3v_vga, 1p35v_vga, 1p05v_vga

3D3V_VGA_S0
3D3V_S0 to 3D3V_VGA_S0
D
1D05V_VGA_S0 1D05V_S0 to 1D05V_VGA_S0
D

0307 Add Discharge Circuit

3D3V_VGA_S0 should ramp-up before VGA_Core
VGA_Core should ramp-up before 1D5V_VGA_S0
1D05V_S0 3D3V_S0
1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0 VGA_CORE
U8301 1D05V_VGA_S0
3D3V_AUX_S5

1
15 1D05V_VGA_S0
GND PG8313 DGPU_PWR_EN# PR8317
1 14 1
2
VIN1#1 VOUT1#14
13 1D05V_VGA_OUT2 1 2
OPS2 10R2J-2-GP
1D05V_VGA_EN 3
VIN1#2 VOUT1#13
12 VTT_CT_105VC_2 PR8313 D G S OPS
ON1 CT1 GAP-CLOSE-PWR 100KR2J-1-GP
5V_S0 4 11

2
VBIAS GND VTT_CT_3VC_1 3D3V_VGA_S0
[15,82] DGPU_PWR_EN 5 ON2 CT2 10

1
6 9 PG8312
VIN2#6 VOUT2#9 3D3V_VGA_OUT1 PG8314 PQ8305
R8314 7 VIN2#7 OPS VOUT2#8 8 1 2
OPS 10R2J-2-GP
1 2 2N7002KDW-GP
OPS

D
PR8316

C8305
SC220P50V2KX-3GP
1 2 1D05V_VGA_EN GAP-CLOSE-PWR
[15,24,82] DGPU_PWROK 84.2N702.A3F

C8309
SC1KP25V2JX-GP

SC10U6D3V3MX-GP
C8301
TPS22966DPUR-GP C8308 GAP-CLOSE-PWR PQ8307

2
1

2
C8304 2nd = 84.DM601.03F 2N7002K-2-GP
10KR2J-3-GP 74.22966.093

SC1U6D3V2KX-GP

SCD1U10V2KX-L1-GP
C8310 C8302 X01 0322 OPS S G D
OPS DY 3rd = 84.2N702.E3F 84.2N702.J31 OPS
2

1
SC1U6D3V2KX-GP PG8315
OPS

1
1
SCD1U10V2KX-L1-GP

OPS 1 2
C8306
OPS DY
1

SC10U6D3V3MX-GP
C8307

SCD1U10V2KX-L1-GP
GAP-CLOSE-PWR
DY

S
2

G
1

2
[15,82] DGPU_PWR_EN
DY

1
OPS DGPU_PWR_EN#
C C

1D35V_S3 3.3V +/- 5% 1D35V_VGA_S0

4.88A
1D35V_VGA_S0 AO4468, SO-8
Id=?A, Qg=9~12nC
8
7
D
D
PQ8308
OPS S 1
S 2
6 D S 3

1
Rdson=17.4~22m ohm 5 D PC8307

1
SC10U6D3V3MX-GP
PC8303 SIRA06DP-T1-GE3-GP G
OPS

2
SC10U6D3V3MX-GP
OPS
2 84.SRA06.037
B B

1D5V_ENABLE_RC 0319 modify Discharge Circuit

A00 0618
1 2
R8313 1D35V_VGA_S0
0R0402-PAD-2-GP
PC8302 1
3D3V_AUX_S5 SCD01U50V2KX-1GP
OPS

1
2

1 1D5V_VGA_EN#
OPS 2 10R2J-2-GP
PR8311 D G S OPS PR8315
100KR2J-1-GP

2
6

PQ8304 DCBATOUT 15V_S5

2N7002KDW-GP DIS_1D5V_VGA_S0
84.2N702.A3F

D
1

2nd = 84.DM601.03F
PR8312
330KR2J-L1-GP

100KR2J-1-GP

OPS GC6
PR8310

3rd = 84.2N702.E3F S G D PQ8306

D8301 OPS DY 2N7002K-2-GP
1
[24,75,76] EC_FB_CLAMP 84.2N702.J31 OPS
2

3 1D5V_VGA_EN

2
OPS 1D5V_ENABLE

S
G
[15,24,82] DGPU_PWROK
BAT54CPT-2-GP
75.00054.K7D
1

1D5V_VGA_EN#
R8312 PR8301
A
1 2
DY 10MR2J-L-GP
A

<Core Design>
0R2J-2-GP
2

Non-GC6
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DISCRETE VGA POWER
Size Document Number Rev
Custom Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 83 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 84 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 85 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

SO1 SO2 SO3

OPS OPS OPS S1 S2 S3 S4

D D
1

1
STF217R128H83-2-GP STF217R128H83-2-GP STF217R128H83-2-GP SPRING-52-GP SPRING-52-GP SPRING-52-GP SPRING-52-GP
34.4Y702.301 34.4Y702.301 34.4Y702.301 34.4T025.001 34.4T025.001 34.4T025.001 34.4T025.001

0116 Add RF CAP

C1 C2 C3
HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP
H2 H3 H4 DCBATOUT

1
1

EC8601

EC8602

EC8603

EC8604

EC8605
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
C C

1
HOLET256B315R111-GP HT85BE85R29-U-5-GP HOLET256B315R111-GP DY DY DY ZZ.00PAD.V71 ZZ.00PAD.V71 ZZ.00PAD.V71
2

2
ZZ.00PAD.M01 ZZ.00PAD.D41 ZZ.00PAD.M01

0528 Add NPTH hole

0117 Add EMC CAP
PAD1
1 3 DCBATOUT
2

PAD-3P-GP
EC8606

EC8607

EC8608

EC8609

EC8610

EC8611

EC8612
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
1

B B

DY DY DY DY DY
2

5V_S0 3D3V_S0 VGA_CORE 1D05V_S0

EC8613

EC8614

EC8615

EC8616

EC8620

EC8621

EC8622
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
1

DY DY DY DY DY DY DY
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 86 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 87 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Reserved Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 88 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 89 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 90 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 91 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 92 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A3 Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 93 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 94 of 101
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 95 of 101
5 4 3 2 1
 5 4 3 2 1

SSID = XDP

D D

CPU XDP
3D3V_S5

CFG[19:0]
[6] CFG[19:0]
XDP_BPM[7:0]
[4] XDP_BPM[7:0]
1
2

RN9602 CFG0 1 TP9624 CFG12 1 TP9635 XDP_PREQ# 1 TP9601

CFG1 TP9623 CFG13 TP9636 [4] XDP_PREQ#
SRN1KJ-11-GP-U 1 1
XDP [4] XDP_PRDY# XDP_PRDY# 1 TP9602
CFG2 1 TP9622 CFG14 1 TP9637
CFG3 1 TP9621 CFG15 1 TP9638
4
3

CFG4 1 TP9609 CFG17 1 TP9627

CFG5 1 TP9608 CFG16 1 TP9628
SYS_PW ROK [17,24] XDP_BPM0 TP9612
PM_PW RBTN# [17,24] 1
CFG6 1 TP9607 CFG19 1 TP9633 XDP_BPM1 1 TP9613
CFG7 1 TP9606 CFG18 1 TP9634 XDP_BPM2 1 TP9614
XDP_BPM3 1 TP9615
CFG8 1 TP9629 TP9639 1 PCIE_CLK_XDP_P PCIE_CLK_XDP_P [18] XDP_BPM4 1 TP9616
CFG9 1 TP9630 TP9640 1 PCIE_CLK_XDP_N PCIE_CLK_XDP_N [18] XDP_BPM5 1 TP9617
XDP_BPM6 1 TP9618
CFG10 1 TP9631 XDP_BPM7 1 TP9619
CFG11 1 TP9632

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU XDP
Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 96 of 101
5 4 3 2 1
 A
PCH Strapping B C
Processor Strapping D E
Name Schematics Notes Pin Name Strap Description (Default value for each bit is Default
1 unless specified otherwise) Value
C

4 4

Voltage Rails
POWER PLANE VOLTAGE DESCRIPTION
ACTIVE IN

3 3

2 2

SMBus ADDRESSES

PCIE Routing I 2 C / SMBus Addresses CHIEF RIVER ORB

Device Address Bus

LANE1 X
USB Table EC SMBus 1
Battery 0 0x16 BAT_SCL/BAT_SDA
CHARGER 0x12 BAT_SCL/BAT_SDA
PS8122(HDMI Switch) (Bottom Dock) 0x9E BAT_SCL/BAT_SDA
Pair Device USB3.0 redriver PS8710 (Bottom Dock) 0x40 BAT_SCL/BAT_SDA
LANE2 X SATA Table EC SMBus 2
USB port 1,with Power Share Battery 1 0x16 SML1_CLK/SML1_DATA
LANE3 Mini Card1(WLAN) SATA
0 PCH 0x96 & 0x94 SML1_CLK/SML1_DATA
1 USB 2.0 HDMI Discrete VGA Thermal 0x9C or 0x9E SML1_CLK/SML1_DATA
Pair Device PS8321 HDMI level shifter 0x96 & 0X97 SML1_CLK/SML1_DATA
LANE4 X 2 USB port2 (usb redriver) NCT7718W 0x98 or 0x99 SML1_CLK/SML1_DATA

1 LANE5 X 0 HDD1 3 X EC SMBus 3

NCT5605Y-0 0x30
SMB2_CLK/SMB2_DATA
SMB2_CLK/SMB2_DATA
<Core Design>
1
1 mSATA 4 Touch Panel NCT5605Y-1 0x32 SMB2_CLK/SMB2_DATA

LANE6 X Wistron Corporation

2 5 Card Reader PCH SMBus 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SO-DIMMA PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
BLUETOOTH SO-DIMMB PCH_SMBDATA/PCH_SMBCLK
LANE7 X 3 6 Intel LAN 82579 PCH_SMBDATA/PCH_SMBCLK Title
4 7 CAMERA G-Sensor PCH_SMBDATA/PCH_SMBCLK

LANE8 X MINI WWAN PCH_SMBDATA/PCH_SMBCLK Table of Content

5 INTEL LAN82579 PCH_SMBDATA/PCH_SMBCLK Size Document Number Rev
A3 X02
Hadley 15"
Date: Friday, June 28, 2013 Sheet 97 of 101
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 98 of 101
5 4 3 2 1
 5 4 3 2 1

Intel-Power Up Sequence

(AC mode) Red printings:KBC GPIO involved (DC mode) Red printings:KBC GPIO involved
D D

+RTC_VCC T1
+RTC_VCC T1 >9ms
RTC_RST# T2
RTC_RST#
DCBATOUT T3
DCBATOUT T2
3D3V_AUX_S5
3D3V_AUX_S5 T3
KBC GPIO34 control
S5_ENABLE T4

5V_S5 T5
T6
3D3V_S5 T7
KBC GPIO43 to PCH
PM_RSMRST# T8 >5ms

PCH_SUSCLK_KBC 0ms< T9 <90ms

KBC GPIO84 control
AC_PRESENT

KBC_PWRBTN# T4

S5_ENABLE T5

3D3V_S5 T6

5V_S5 T7

PM_PWRBTN# T8

PCH_RSMRST# T9 T10 >5ms

KBC_PWRBTN# PCH_SUSCLK_KBC
T10
PM_PWRBTN#
C
T11 C
PM_SLP_S4#
T12
1D35V_S3
T13
1.35V_VTT_PWRGD

PM_SLP_S3# T14 T15

1D5V_S0 T16
T11
1D05V_S0 T17 PM_SLP_S4#
T18 T12
1.05VTT_PWRGD / RUNPWROK +5V_RUN & +3.3V_RUN need meet 0.7V difference 1D35V_S3
T19
T13
5V_S0 1.35V_VTT_PWRGD
T20
3D3V_S0 T21 PM_SLP_S3# T14 T15

1D5V_S0 T16

1D05V_S0 T17
T18
1.05VTT_PWRGD / RUNPWROK +5V_RUN & +3.3V_RUN need meet 0.7V difference
T19
5V_S0
T20
DDR_VTT_PG_CTRL 3D3V_S0 T21
T22
0D675V_S0

DDR_VTT_PG_CTRL
T22
B B
RUNPWROK T23 0D675V_S0

H_VCCST_PWRGD

PM_SLP_S3#
T24
PCH_PWROK

H_VR_ENABLE T25
T26
VCC_CORE
T27 RUNPWROK T23
IMVP_PWRGD
H_VCCST_PWRGD
SYS_PWROK T28
PM_SLP_S3#
T24
H_CPU_SVIDDAT
PCH_PWROK
PLT_RST#
H_VR_ENABLE T25
T26
VCC_CORE
T27
IMVP_PWRGD

SYS_PWROK T28

H_CPU_SVIDDAT

PLT_RST#

A A
43

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev

Hadley 15" X02

Date: Friday, June 28, 2013 Sheet 99 of 101
5 4 3 2 1
 5 4 3 2 1

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

D DC 3 D
BT+ SWITCH
Battery PM_SLP_S4#
Page43 Page44

-7 -3 DCBATOUT
AC +DC_IN SWITCH DCBATOUT
Adapter in S5_ENABLE 3a
Page44 4a
Page42 VIN 1D35V_S3
SW
VIN 1D05V_S0
AD+ SW

4 TPS51367
-5 EN1 EN2 RUNPWROK
3D3V_S5 TPS51367 EN PGOOD
PM_SLP_S3# RUNPWROK Page48
Charger EN PGOOD
DCBATOUT TPS51225CRUKR Page48 4b
BQ24715 VIN
DC/DC -2 4b
(3.3V/5V) 5V_S5
ACOK Page44 1D35V_S3
Page41

3D3V_AUX_S5 RUNPWROK 5V_S0

4 SWITCH
Page36
DDR_VTT_PG_CTRL 0D675V_S0
-4 SWITCH TPS51206
Page24 Page46
RUNPWROK 3D3V_S0
-6 SWITCH
C 3D3V_AUX_KBC -3 4b Page36
5 C

AC_IN S5_ENABLE 7
PSL_IN1# GPIO34
DDR_PG_CTL RUNPWROK Level H_VCCST_PWRGD
1 H_VR_ENABLE Shifter
VR_EN
Page7
KBC_PWRBTN# -1
PSL_IN2# KBC DPWROK H_CPU_SVIDDAT
VIDSOUT
PM_SLP_S4#
NPCE985 GPIO43
RSMRST#_KBC
RSMRST# Haswell ULT CPU
GPIO8 PM_PWRBTN# 11
PM_SLP_S3#
GPIO01
GPIO20 PWRBTN#
with
3D3V_S5
GPIO80 2 Lynx Point PCH
Page24 12 4a
SLP_S3# de-assert, delay 20ms; APWROK PCI_PLTRST# 4 VIN 1D5V_S0
PCH_PWROK assert. PLTRST# VOUT
10 S0_PWR_GOOD
6 PCH_PWROK VCCST_PWRGD SYS_PWROK VR_READY PM_SLP_S3# TPS51312 RUNPWROK
SLP_S3# de-assert, delay 200ms; EN PGOOD
S0_PWR_GOOD assert. Page51

5 4b
PCH_PWROK H_VCCST_PWRGD

SYS_PWROK be asserted after S0_PWR_GOOD

B assertion and CPU core VR power good B
assertion.
11
S0_PWR_GOOD
H_CPU_SVIDDAT
VDIO

TPS51622 9
7 H_VR_ENABLE IMVP_PWRGD
VR_ON PGOOD

Page46

PWR_VCC_PWM1

DCBATOUT 8
CSD97374
VCC_CORE
VSW
Page47

A A

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 100 of 101
5 4 3 2 1
 A B C D E

1 1

PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5 3D3V_S0

3D3V_S0

SRN2K2J-1-GP ‧ SRN2K2J-1-GP

DIMM 1
‧ ‧
‧ ‧
SMBCLK SMB_CLK PCH_SMBCLK
SCL
3D3V_AUX_KBC
SMBDATA SMB_DATA PCH_SMBDATA

‧
SDA

‧
‧
2N7002SPT PCH_SMBCLK

PCH_SMBDATA
MSATA
SRN4K7J-10-GP

‧ BAT1 CONN
‧ ‧‧
PCH_SMBCLK
2 TouchPad 100R2J-2-GP 2

‧ ‧
PCH_SMBDATA GPIO17/SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB

GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16

3D3V_S5
Minicard 100R2J-2-GP

PCH_SMBCLK WLAN SCL

BQ24715
PCH_SMBDATA SMB_CLK
SRN2K2J-1-GP SDA SMBus address:12
SMB_DATA

SML0CLK SML0_CLK

SML0DATA SML0_DATA KBC 3D3V_S5

NPCE885
PCH PCH
SRN2K2J-1-GP

‧
‧
GPIO73/SCL2 SML1_CLK
3D3V_S5
GPIO74/SDA2 SML1_DATA

KBC
SRN2K2J-1-GP
NPCE985
‧ ‧
‧ ‧
SML1CLK SML1_CLK SCL2
3 SML1DATA SML1_DATA SDA2 3

3D3V_S0

SRN2K2J-1-GP Thermal
‧ NCT7718W
‧
THM_SML1_CLK SCL
switch THM_SML1_DATA SDA
SMBus address:XX

4 4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
Hadley 15" X02
Date: Friday, June 28, 2013 Sheet 101 of 101
A B C D E