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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 28-nm FD-SOI 115-fs Jitter PLL-Based

LO System for 24–30-GHz Sliding-IF
5G Transceivers
Staffan Ek, Tony Påhlsson , Christian Elgaard , Anders Carlsson , Member, IEEE, Andreas Axholt,
Anna-Karin Stenman , Member, IEEE, Lars Sundström , Member, IEEE,
and Henrik Sjöland , Senior Member, IEEE

Abstract— A system for local oscillator (LO) signal generation

in 5G millimeter-wave (mmW) multi-antenna transceivers is
presented. The system is modular with one phase locked loop
(PLL) per antenna element transceiver, and a test circuit imple-
mented in 28-nm fully depleted silicon on insulator (FD-SOI)
CMOS features two such PLLs and a 491.52 MHz crystal oscilla-
tor (XO) generating a common frequency reference. A fractional-
N architecture is employed to achieve high-frequency resolution,
and the quantization noise is reduced using a novel frequency
divider, which achieves full integer resolution while still using
a pre-scaler. The system covers the 3rd Generation Partnership
Project (3GPP) bands n257 and n258, achieved by a digital coarse
tuning of the voltage-controlled oscillator (VCO). The chip area
of each PLL is 0.11 mm2 , and 0.029 mm2 for the XO. The total
power consumption of the system is 35 mW, where each PLL
consumes 15.4 mW and the XO consumes 0.84 mW. The total rms
jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just
115 fs, corresponding to an FOM j of −244 dB, which is the best
reported figure for a fractional-N PLL above 15 GHz. The error-
vector magnitude (EVM) due to phase noise is −34.6 dBc using an
orthogonal frequency-division multiplexing (OFDM) signal with
120-kHz sub-carrier spacing, sufficient to support 256 QAM. Fig. 1. Different radio scenarios.
Index Terms— CMOS, crystal oscillator (XO), decorrela-
tion, delta–sigma modulator (DSM), fifth generation (5G), for mobile communication systems. In particular, 3GPP has
fractional-N, frequency synthesis, millimeter-wave (mmW), phase
noise, phase-locked loops (PLLs), radio transceivers. paid a substantial amount of attention to local oscillator (LO)
generation at mmW frequencies, as LO phase noise has been
anticipated to have a larger impact on performance than in
I. I NTRODUCTION present systems, operating in the low gigahertz regime. Using
orthogonal frequency-division multiplexing (OFDM), the sub-
A S CELLULAR communication now enters its fifth
generation (5G), it will, for the first time, support
millimeter-wave (mmW) frequencies. This has, to a large
carrier spacing, f sc , of the signal is a key parameter that
directly determines the impact of LO phase noise.
extent, been an uncharted territory for 3rd Generation Part- Consider the two radio scenarios in Fig. 1, an outdoor
nership Project (3GPP), the de facto standardization body and an indoor scenario. In the outdoor scenario, the channel
dispersion is large due to long distances between reflecting
Manuscript received December 6, 2017; revised February 16, 2018; accepted objects, with a spread in delay due to multi-path propagation
March 16, 2018. This paper was approved by Guest Editor Andrea Bevilacqua.
This work was supported by the European Commission in the frame- on the order of hundreds of nanoseconds. This means that
work of the H2020-ICT-2014-2 Project Flex5Gware under Grant 671563. consecutive OFDM symbols may overlap at the receiving end,
(Corresponding author: Lars Sundström.) leading to inter-symbol interference (ISI). This is managed
S. Ek was with Ericsson, 221 83 Lund, Sweden. He is now with Arm
Sweden, 223 69 Lund, Sweden. by extending each symbol by a so-called cyclic prefix (CP),
T. Påhlsson, A. Carlsson, A.-K. Stenman, and L. Sundström are with during which the overlap can be allowed. However, for a low
Ericsson, 221 83 Lund, Sweden (e-mail: lars.s.sundstrom@ericsson.com). system impact, the CP should only occupy a small fraction of
C. Elgaard and H. Sjöland are with Ericsson, 221 83 Lund, Sweden, and
also with the Department of Electrical and Information Technology, Lund each symbol; thus, the symbol duration should be long. Since
University, 221 00 Lund, Sweden. the duration of one OFDM symbol is the reciprocal of the sub-
A. Axholt is with Acconeer, 223 63 Lund, Sweden. carrier spacing, f sc should be small. The same reasoning of
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. course applies to the indoor scenario, but here the difference
Digital Object Identifier 10.1109/JSSC.2018.2820149 in delay between propagation paths is much smaller, on the
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 3. Transceiver array architecture.

FOM j of −244 dB in its frequency range, enabling a low

power consumption, a high level of integration, and a high-
Fig. 2. Phase noise and inter-carrier interference versus sub-carrier spectral efficiency in mmW 5G cellular systems. With a sub-
spacing f sc . carrier spacing of 120 kHz and a carrier frequency of 26 GHz,
the EVM due to phase noise is −34.6 dBc, with further reduc-
tion enabled by extending the distributed LO generation sys-
order of tens of nanoseconds or even less, thus allowing for tem to an antenna array system with tens of elements or more.
a much shorter CP and symbol duration compared with the This paper starts by discussing the architecture chosen for the
outdoor scenario. work in Section II, followed by the circuit design in Section III
Unfortunately, phase noise characteristics of LO genera- and measurements in Section IV. Finally, conclusions are
tion circuits lead to f sc requirements conflicting with those drawn in Section V.
imposed by the radio scenarios. In Fig. 2, the raster of
sub-carriers of the OFDM signal is exemplified for a low
II. A RCHITECTURE
and high f sc . In a transceiver, when the OFDM signal is
frequency-translated from baseband to RF or vice versa, each The LO generation is intended for a 5G mmW antenna
sub-carrier will be convolved with the LO phase noise and array system, featuring several transceivers, each supporting
thus interfere with neighboring sub-carriers, resulting in inter- one antenna element. The transceivers may be located on a
carrier interferene (ICI) leading to an equivalent error-vector single or on multiple chips. To obtain a flexible solution with
magnitude (EVM) contribution. Any given sub-carrier will a minimum amount of high-frequency routing, an architecture
also be affected by the phase noise component associated was chosen where the LO signals for each transceiver are gen-
with itself, but this contribution can be largely suppressed by erated locally by a separate high-frequency PLL (see Fig. 3).
common phase error (CPE) tracking [9]. In short, to calculate No global routing of LO signals is then needed, just the refer-
the EVM contribution from phase noise, a weighting function ence clock needs to be routed to all the PLLs to ensure that the
should be applied to the phase noise prior to integration [9]. LO signals generated are locked in phase and frequency. This
The frequency scale of the weighting function is proportional reduces both the power consumption of signal distribution and
to fsc , and as evident from Fig. 2, a high f sc is therefore design effort when changing the number of transceivers on a
favorable with regard to EVM. 5G mobile communication chip, as keeping the high-frequency signals localized at each
link level simulations suggest rather small f sc to achieve transceiver allows for a modular design [8].
high performance [3], and the first specification, 3GPP new To reduce the high-frequency generation and quadrature
radio (NR) release 15, stipulates the support of f sc of 60 and accuracy requirements of the LO system, a sliding IF archi-
120 kHz when operating at mmW frequencies. Using such tecture is adopted for the transceivers. The voltage-controlled
small sub-carrier spacings in mmW systems results in very oscillator (VCO) output frequency is then equal to two
stringent phase noise requirements. thirds (2/3) of the carrier frequency. In the receiver, the antenna
To support 256-QAM modulation (with unity code rate) of signal is frequency down-converted in a first mixer stage,
the OFDM sub-carriers, the EVM for the complete radio link clocked by the VCO output frequency, resulting in an IF
must be below −30 dBc. This budget is to be shared by many signal with a frequency equal to one third (1/3) of the carrier
contributors, but the larger part must be allocated to the RF frequency. The IF signal is down-converted to baseband by
power amplifier to maximize its power efficiency. Thus, means a quadrature mixer, clocked by quadrature signals from a
to reduce EVM contributions from other parts, and the LO divide-by-two circuit connected to the VCO output. In the
generation in particular, to say −36 dBc or lower is of great transmitter (TX), the signal takes the other direction, starting
importance. with baseband signals being up-converted to IF by quadrature
This paper presents a dual phase locked loop (PLL) dis- mixers clocked by signals from the divide-by-two circuit, and
tributed LO generation system for multi-antenna mmW trans- then the IF signal is up-converted to carrier frequency by a
ceivers [22]. Implemented in a 28-nm fully depleted silicon mixer clocked by the VCO output signal. Fig. 4 illustrates the
on insulator (FD-SOI) CMOS technology, it achieves a record LO generation system connected to this type of TX.
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EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 3

Fig. 4. LO generation system and sliding IF TX architecture.

A complication with generating the quadrature LO signal

using a frequency divider is that it has two different internal
states. Depending on in which state it starts, there will be a
180° difference in the output signal phase, and the probability
is about equal for the two states. This is not a concern in Fig. 5. Accumulated phase at VCO output for DSM sequences with varying
delays.
a single transceiver, but in an antenna array, the construc-
tive addition of signals in the beams will be ruined when
some transceivers operate in opposite phase. In this paper,
the quadrature divider is therefore part of the PLL feedback quantization of the  modulator thus becomes a single VCO
frequency divider, allowing the phase of the quadrature signal output cycle. To further suppress the quantization noise of
to be locked to the reference. the  modulators, they are de-correlated. This is achieved
The effective LO signal of the array transceiver system is the by using separate local modulators in the PLLs. Since all
combined signal of the individual LO generators. If the phase the modulators are made identical for modularity, starting
noise of the PLLs has equal magnitude and is uncorrelated, them simultaneously with the same state would result in fully
the phase noise of the combined signal is reduced by 3 dB correlated signals. For that reason, the modulators are time
for each doubling of the number of PLLs used. With a total delayed with respect to each other, such that the correlation
number of M PLLs, the phase noise is thus reduced by of their quantization noise becomes very low [7].
10 × log(M) dB compared with a single PLL. The noise When the different  sequences are delayed to achieve
will be reduced both in-band and out-of-band of the PLL. noise de-correlation, also the phase relation between the PLL
However, as uncorrelated noise is suppressed, the importance outputs will be affected. Fig. 5 is an illustration of the effect,
of correlated noise increases. Since all PLLs share the same showing three different  sequence time delays. The 
reference signal, its noise becomes correlated, and obtaining commanded phase positions versus time are marked by points
low reference noise becomes increasingly important. At the (◦, , and , for the different sequences, respectively). Note
VCO output, the phase noise of the reference is increased that the phase resolution is in single VCO periods. For the
due to frequency multiplication. The frequency multiplication purpose of illustration, the division ratio is in the range
factor of the PLL, equal to the VCO output frequency divided [−1 . . . + 2] instead of about [35 . . . 38]. The interesting part is
by the reference frequency, should thus be reduced. A high- the fractional periods, not the full periods, as the full periods
frequency crystal oscillator (XO) operating at 491.52 MHz will not affect the phase difference measured between PLL
was therefore used to generate the reference [5]. outputs. Due to the low-pass filter action of the PLLs, they
The fractional-N functionality is implemented completely will not follow the instant phase commands from the 
in the digital domain using  modulators controlling the modulator but will act to adjust a line with a minimum average
feedback division ratio. The PLL uses a well-established phase error from the commanded points, where the slope of the line
frequency detector (PFD) and charge-pump architecture with represents the frequency of the output signal. With identical,
an analog loop filter that together with the integrating action of but time delayed, sequences, the lines become identical but
the oscillator suppresses the high-frequency  quantization time delayed, i.e., they will have exactly the same slope. This
noise. To minimize the quantization noise, not only the order can be seen in Fig. 5, where the slope is the same in the
and clock rate of the  modulator are important but also the three cases, equal to 0.690, which is the fractional frequency.
time quantization (resolution). The use of fixed division ratio However, there is a horizontal offset between the lines, equal
pre-scalers is often required in high-frequency PLLs, which to the time delay between the sequences. This corresponds to
enables a high-frequency operation but limits the achievable a vertical offset between the lines, representing a phase differ-
time resolution. Having a pre-scaler division equal to four, ence, after the full periods have been subtracted. The relation
the feedback divider resolution typically becomes four VCO between the vertical and horizontal offsets is given by the slope
cycles. In the circuit presented, however, although a pre- of the lines. As can be seen in the legend of the figure, a delay
scaler division ratio of four is used, full integer resolution is of ten samples results in 7.52 − 0.62 = 6.9 periods of phase
achieved by using a novel rotating multi-modulus frequency retardation. This is the same as ten samples multiplied by
divider with multi-phase inputs after the pre-scaler. The time the fractional frequency (10 × 0.69 = 6.9), confirming that the
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

is used for a maximum high-frequency quality factor [23].

To ensure monotonicity, needed by the digital tuner, the two
most significant bits (MSBs) are thermometer-coded. In this
way, an oscillator tuning range exceeding 25% can be achieved
together with limited continuous tuning sensitivity (K VCO )
supporting a low PLL phase noise. To reduce flicker noise,
programmable resistors (R1 ) rather than transistors are used
to control the current in the oscillator. Furthermore, the core
transistors (N1, P1) have about twice the minimum length
(L NMOS = 60 nm and L PMOS = 50 nm).
The design of the on-chip inductor is a key to achieving high
oscillator performance. The process used offers ten copper
metal layers, and the two topmost are used in parallel in a
single turn differential inductor without center tap. The outer
dimensions are 96 × 96 μm2 and the track width is 12 μm.
The corners are cut to reduce losses but still provide a
close to square geometry for maximum area efficiency. The
geometry can be seen in the PLL layout and chip photo-
Fig. 6. VCO schematic.
graph in Fig. 17. According to electromagnetic simulations
in Momentum, the resulting differential inductance is 138 pH
phase difference in periods can simply be found by multiplying with a quality factor of 24 at 18 GHz. In circuit simulations,
the fractional frequency by the number of symbols of delay the oscillator consumes 2 mA from a 1.25-V supply, and
in the  sequence and taking the fractional part of the its phase noise at 10-MHz offset from an 18-GHz carrier is
result. This can be used to control the phase of the LO −124.5 dBc/Hz, corresponding to a phase noise figure of merit
signals in an LO-beamforming system, for instance in a hybrid (FoM) of 186 dB. The 1/ f 3 phase noise corner is 750 kHz.
beamforming system [26]. Note that the result follows from
using identical time delayed sequences, regardless of sequence
B. Frequency Divider
and modulator type.
Due to the high input frequency, the first two stages in the
III. C IRCUIT D ESIGN divider chain are divide-by-two circuits using current mode
logic (CML). The simplicity of the divide-by-two circuits,
A. Voltage Controlled Oscillator combined with the high-speed properties of CML and the
The VCO uses a cross-coupled LC NMOS–PMOS push– 28-nm SOI technology, allows robust operation at input fre-
pull topology (see Fig. 6). The push–pull structure limits the quencies exceeding 20 GHz. The first CML divide-by-two
voltage swing of the oscillator nodes between supply and circuit outputs a quadrature signal at half the VCO frequency.
ground, ensuring reliability of the thin oxide devices used This signal is also used as an LO for the mixers taking the
to achieve high transconductance and minimum capacitive baseband signals to IF (see Fig. 4). The dual use of the highest
parasitics. A drawback, however, is that the oscillator features frequency divider not only saves considerable power but it also
PMOS devices, which are larger than corresponding NMOS, allows control of the quadrature LO phase relation between
reducing the achievable frequency-tuning range. In our case, different PLLs.
the penalty was limited, as the width of the PMOS devices Using an integer resolution programmable divider after the
was not more than twice that of the NMOS, and in even more fixed divide-by-four circuit would yield a total division ratio
advanced technologies, there is a trend toward faster PMOS resolution equal to four. To obtain full integer resolution,
devices with performance on par with the NMOS, eliminating the programmable divider is therefore not using a single input
this drawback of push–pull oscillators. Still, even with 130- signal, but all the four quadrature signals are provided by
nm SOI technology, it is possible to reach 15% tuning range the second CML divide-by-two circuit. The time difference
at 40 GHz [28]. In our design, a combination of continuous between each input of the programmable divider is then
(analog) and switched (digital) frequency tuning is used. MOS- equal to one VCO cycle, enabling full integer resolution. The
varactors (N2 in Fig. 6) are used for the continuous tuning, schematic and simulated signals of this divider are shown
and to achieve a more constant tuning sensitivity over the in Fig. 7. The second divide-by-two circuit generating the four
control voltage range, each MOS varactor is split-up in four quadrature signals is also part of the schematic. A program-
parts, separately ac-coupled to the oscillator core. As can be mable true-single-phase clock (TSPC) divider with a division
seen in Fig. 6, four different dc-voltages are used for biasing, ratio P ∈ [1 . . . 31] is connected to one of the four quadrature
creating an effective tuning characteristic being the sum of signals. The output of this divider is re-sampled in TSPC flip-
four offset characteristics, reducing the maximum gain, and flops using the four quadrature signals as clocks. The result
widening the control voltage range. For the switched tuning, is four divided signals, time skewed with respect to each
a bank of metal-oxide-metal (MOM) capacitors (CBank ) is other by one VCO cycle. This can be seen in the simulated
used together with NMOS switches. A differential topology signals for a 20-GHz VCO frequency and a division ratio N
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EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 5

Fig. 7. Phase multiplexing divider. (a) Schematic. (b) Simulation result.

of 39 shown in Fig. 7. A multiplexer is then used to select noise source to a minimum, at the cost of some additional
which signal to use as output, providing a time resolution of power consumption, would be to re-clock the divider output
one VCO cycle. By changing the multiplexer from sample to with the VCO signal.
sample in a rotating pattern, non-integer division ratios can When increasing the resolution to below two VCO cycles
be realized in the latter part of the divider chain, creating using this technique, i.e., one VCO cycle, a problem occurs
overall integer resolution. When the rotation wraps around the with phase ambiguity in the quadrature LO signal, since one
multiplexer, a VCO cycle needs to be swallowed/injected by cycle resolution at the VCO output corresponds to 180° res-
increasing or decreasing P by one during one reference cycle. olution (half cycle) at the quadrature divider output. This
The following equations, implemented in the state-machine will require synchronization between the PLLs; otherwise,
of the divider control block, control the multiplexer and the the problem of some PLLs operating in anti-phase may occur
programmable divider: even though the divide-by-two circuit is inside the loop. Even
if the phase rotating divider local control units would be started
mux[n + 1] = (mux[n] + N mod 4) mod 4 (1)
fully synchronized, synchronization would be lost since they
P = N/4 + (mux[n] + N mod 4)/4 (2) are clocked by the divided signal from the VCOs, which are
where n is the number of the sample in the sequence, and not locked during calibration. Slight differences in frequency
N is the 7-bit total division ratio N ∈ [1 . . . 127] of the divider are therefore expected during calibration, depending on indi-
chain, supplied by the Digital Macro (see Fig. 4). vidual VCO characteristics, resulting in different numbers of
Unlike in the rotating divider in [24], here the multiplexing clock cycles being received by different control units. The
is performed on signals close in frequency to the reference, output phases then end up randomly in phase and in anti-
making the timing of the multiplexing relatively uncritical. phase. After PLL settling, this can be corrected by comparing
Both the multiplexer and its control are therefore realized in a the least significant bit of the multiplexer control signals.
standard CMOS logic. As can be seen in Fig. 7, the timing dif- If these have different values in different PLLs, the outputs will
ference between the four re-sampled signals is small compared be an odd number of VCO cycles apart, and the quadrature
with the period time, making it straightforward to perform outputs will be in anti-phase. The situation is rectified by
switching between any of the four signals while avoiding first assigning one of the PLLs of the array as the master.
glitches. This would not be the case if multiplexing was to be Then, the division ratio is increased by one during a single
performed on the incoming high-frequency quadrature signals. reference cycle for all PLLs of the array that have a multiplexer
Glitch-free phase switching at lower frequency can also be control signal LSB deviating from the master. After settling,
realized using a multi-phase divider tree [25] but with a higher the phases of these PLLs will be advanced by one VCO
circuit complexity. cycle, assuring constructive summation of signals in the beam
The switching between phases to improve divider resolu- direction.
tion comes at a cost, however, as the different phases will
deviate from their ideal values due to layout and device C.  modulator
mismatch. Depending on the division ratio, this mismatch will The  modulator has a signed 2-1 multi-stage noise-
cause reference sub-harmonic spurs in the integer-N mode. shaping (MASH) architecture with configurable modulus, con-
In fractional-N mode, on the other hand, the non-linearity of figurable self-dithering, state memory, and an output range
the frequency divider transfer due to phase mismatch folds of [−3 . . . 4]. The modulus of the error-feedback stages can
high-frequency delta–sigma modulator (DSM) quantization be set separately to either the power of two corresponding
noise to low frequencies. This can impact the PLL integrated to the word size, or the nearest lower prime number [6].
phase noise performance, but due to the random nature of Optional dithering noise is taken from the MSBs of the
the DSM, no sub-harmonic spurs are generated. Although not residual error [7]. The fractional resolution was chosen to be
employed in this paper, a technique to reduce this potential 19 bits to minimize the circuit size and power consumption.
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 8. DSM decorrelation principle.

At 491.52-MHz reference frequency, this corresponds to a

937.5-Hz PLL output frequency resolution.
The  modulator can save its state in internal memory, Fig. 9. Transient simulation of start-up including VCO calibration showing
VCO tune voltage and calibration word.
which can later be recalled, allowing the output sequence
to be restarted from a known state. Save and recall are
controlled by timers counting DSM clock cycles from reset division ratio, enabling a near mid-scale VCO control voltage
(see Fig. 8). This allows de-correlation of the DSM noise in after calibration and settling. The frequency measurement
the individual transceiver paths, by first saving the state at is performed by counting divider output periods during a
different times in the different modulators and then recalling measurement interval timed by the reference clock. Since
the states simultaneously. To support this, as can be seen the period is modulated, the measurement interval must be
in Fig. 8, individual timers (Ts,1 and Ts,2 ) are used for increased to obtain the average, as the modulation may cause
save and a common one (Tr ) for recall. The time offset a ±1 count error. The reference clock is also asynchronous
between two sequences, like those in Fig. 5, will then be to the measured signal, which means that the cycle count
equal to the difference between their save timer settings. has an additional error of up to one cycle. The counter is
The identical modulators make the system design modular gray-coded to address the asynchronous clock domains. The
and eliminate the risk for phase drift due to digital fre- minimum number of cycles that must be measured corresponds
quency differences between PLLs, as illustrated in Fig. 5. This to the desired precision times the maximum measurement
de-correlation method is supported by the results in [7], where error. For example, 6-bit resolution corresponds to one part in
it is demonstrated that the DSM sequence from an 18-bit, 26 = 64 precision. To measure the frequency with this
second-order H-K MASH has zero autocorrelation within precision, with a count error range of 4 ([−1, 0, 1, 2]), we must
shifts less than 65 521, despite the absence of dithering, measure across an interval corresponding to a count of
and that their self-dithering scheme completely eliminates 64 × 4 = 256 periods. At 491.52 MHz, this corresponds to
correlation for all shifts. An analysis of fractional-N DSM about half a microsecond. With each frequency measurement
is found in [29], showing that the quantization error of the taking 0.5 μs, the total time to find the six control-bit
MASH 1-1-1 and MASH 1-1-1-1 has zero autocorrelation, word becomes 3 μs. When a new PLL output frequency is
which is the property used in [7]. commanded, the digital tuner will then first be activated, and
when it is finished after 3 μs, the analog PLL settling can
D. Digital VCO Tuner start. A transient simulation of circuit start-up including VCO
The VCO has a digital frequency control word with six bits, calibration can be seen in Fig. 9.
which controls the switched tuning capacitors. Since this is the
coarse tuning of the frequency, the control word needs to be E. Crystal Oscillator
set before the analog PLL settling can be started. It should Since the reference is common to all PLLs, its phase noise
be set such that the analog control voltage will be close to contribution will be correlated between all transceivers, and
mid-scale after the PLL has locked. the requirement is thus stringent. By using a high reference
To find the proper digital setting, a successive approxi- frequency, the phase noise increase due to PLL frequency mul-
mation (binary search) algorithm is used. This is a well- tiplication will be less severe. For this reason, a 491.52-MHz
known technique used, e.g., in successive approximation regis- XO was used [5]. The crystal is a inverted-mesa research pro-
ter (SAR) analog-to-digital converters. The algorithm is easy totype crystal manufactured using a photolithographic process.
to implement and provides fast convergence, achieving one It has a Q value of 8500 at the fundamental resonance fre-
binary bit for each comparison made, so that six comparisons quency of 491.52 MHz and a maximum drive level of 300 μW.
are sufficient to find the full 6-bit binary control word. This It is housed in a 3.8 × 3.8 mm2 package and is mounted close
makes it the probably most commonly used VCO calibration to the chip on the printed circuit board (PCB) to minimize
algorithm [32]. The VCO must have a monotonic digital parasitics (see Fig. 10).
frequency tuning characteristic for this algorithm to work The topology of the oscillator is similar to that of the VCO,
properly, however, which was easily achieved for the 6-bit using a cross-coupled NMOS–PMOS push–pull architecture,
switched tuning by thermometer coding the two MSBs. but with a crystal replacing the LC resonator (see Fig. 11).
To measure the frequency of the VCO, the frequency of the Unlike the LC resonator, the crystal does not provide a
output from the frequency divider is measured, with fractional dc-path, which enables a low-frequency differential oscillation
 modulation active. The same  modulator configuration mode in the XO. To prevent this oscillation, its loop gain must
as during regular operation is used, providing the same average be kept well below unity. The low-frequency loop gain can be
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EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 7

Fig. 10. Packaged chip and crystal on PCB.

Fig. 12. Charge pump with phase control: schematic and signals.
Fig. 11. XO core schematic and crystal model.

allowing more linear operation reducing the level of harmonics

approximated by generated [5].
 2
Cf
Aloop ≈ R f gm , (3) F. Phase-Frequency Detector, Charge Pump, and Loop Filter
2C L + 2C0 + C f
The PFD uses a conventional architecture with two
where gm is the single-ended transconductance of the XO D-flip-flops, which is connected to the charge pump in Fig. 12.
core and C L is the total capacitive load across the core, To avoid the crossover non-linearity of the PFD, a small
excluding the crystal itself. The expression is derived as the dc-current is injected into the loop filter using NMOS current
gain of the current from one C f capacitor to the output sources (transistors N6–N8). Only the PMOS (charge-up)
current of the corresponding inverter, multiplied by the current transistor (P2) of the CP then needs to be active in steady-state
division between the capacitors at the output and the other C f conditions. However, the conventional PFD then still creates
capacitor. This is then squared, since the loop features two ultra-short pulses on the charge-down output to reset the flip-
cascaded stages. Setting the loop gain equal to one gives flops. These ultra-short pulses are not needed in this case
C L + C0 C L + C0 and are therefore eliminated using logic gates. This relaxes
Cf < 2 ≈2 . (4) the requirement of high-speed CP switching, enabling large
R f gm − 1 R f gm
transistors to be used for a higher CP output resistance and
Having selected C f according to the equation, variations less flicker noise. The linearity of the PFD and CP in steady
in the loop gain can be controlled by the programmable state is high as there are no crossover phenomena when only
resistors R f . one type of pulses (charge-up) is generated. This reduces the
There is also a risk for high-frequency self-oscillation, problem of non-linearity folding  quantization noise to
due to series inductance in the interconnect from the chip in-band frequencies [27].
to the crystal. The circuit was designed to handle parasitic The charge pump has a large degree of programmability;
inductances of two times 3 nH from PCB strip lines and its current is programmable with 5 bits from 96 to 847 μA;
package, requiring two on-chip series resistors of 20  each, the dc-current injected is programmable with 3 bits from
unfortunately reducing the quality factor of the resonator 1/48 to 7/48 of the charge pump current; and the phase can be
at 491.52 MHz by a factor 1.8. controlled with 5 bits and approximately 12° resolution. The
The oscillator has an amplitude control loop stabilizing the phase control is achieved by setting the dc-current injection
amplitude near the maximum drive level of the crystal and transistors N6–N8 to produce about five VCO cycles of phase
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 13. Loop filter schematic.

shift and then adjusting the charge-pump up-current. When the

charge-pump current is changed, to remain in a steady-state
condition, the loop must change the duration of the charge-
pump pulses (φ in Fig. 12), so that the charge in each pulse Fig. 14. Simulated phase noise and contributions for one PLL.
remains constant and still equals the charge injected by Idc
during one reference cycle. The relation between phase shift
and charge pump current thus becomes inversely proportional.
To realize a linear phase control without having to imple-
ment the 1/x function, a current mirror (P3–P9) was used
where the width of the diode connected input transistor was
made programmable with binary weighted devices. Its output
current is inversely proportional to the input transistor width,
which conveniently realizes the 1/x functionality. The output
of the current mirror provides the current ICHP of the charge-
pump pulses. While the phase control is not needed in a
full digital beamforming system, in a hybrid beamforming,
it can be very useful. The simplicity of implementing LO Fig. 15. Simulated phase noise and contributions when combining
eight PLLs.
beamforming is one of the benefits of local LO generation
using PLLs. The PLL phase control can then be realized using
accurate current injection in the loop filter [8], the proposed of eight LO signals, using the same settings as in the single
technique with CP current control, and/or by time offsetting PLL case in Fig. 14. In this case, the  quantization noise
the  sequences as described in Section II. is de-correlated by using time-offsets for the  modulators,
The loop filter is also highly reconfigurable. It is a as previously described. Their noise will then have the same
fourth-order filter (see schematic in Fig. 13), exploiting the relative impact as in the single PLL case. The reference noise,
high reference frequency to PLL bandwidth ratio to suppress however, is fully correlated, and its impact therefore increases
reference spurs. The fourth capacitor is the VCO tuning input when increasing the number of PLLs. This puts the focus
capacitance, which is fixed. All other filter components are on XO performance, motivating the use of a high-frequency
programmable in four linear steps, C1 from 2.5 to 10 pF, C2 491.51-MHz crystal. The multi-antenna system also moti-
from 40 to 160 pF, C3 from 0.5 to 2 pF, R2 from 1 to 4 k, vates the choice of a nominal PLL bandwidth of 1.48 MHz.
and R3 as well as R4 from 0.6 to 2.4 k. The loop filter Although for a single PLL, the VCO noise is dominant and
also has a pre-charge to set the control voltage during VCO a higher bandwidth would thus reduce the jitter; using a
calibration, when the PFD can also be disabled. large number of PLLs, the reference noise instead becomes
dominant making a lower bandwidth beneficial, suppressing
G. Full PLL Phase Noise Simulations high-frequency reference noise.
The phase noise corresponding to a 26-GHz carrier was
simulated, i.e., for a PLL output frequency of 2/3 × 26 GHz = IV. M EASUREMENTS
17.333 GHz. The total phase noise versus offset frequency, A 5.2-mm2chip featuring two TX channels was fabricated
and the contributions from the different parts, can be seen in the 28-nm FD-SOI technology. It was flip-chip mounted
in Fig. 14. The total rms jitter from 20 kHz to 500 MHz in a 6 × 6 mm2 FCBGA package with 0.5-mm ball pitch and
offset is 166 fs. As can be seen the VCO dominates the phase mounted on a PCB for measurements. The measurement setup
noise above 100 kHz and the reference below. An exception is shown in Fig. 16, where the parts inside the large rectangle
is a frequency range from 100 to 300 MHz, where the  are on-chip. As can be seen, there are two PLLs and one
quantization noise dominates, although with negligible jitter XO on the chip, and the purpose is to characterize these. The
impact. other parts of the chip are outside the scope of this paper.
In a multi-antenna system, the effective LO signal is a A partial chip photograph with the layout of the PLL is shown
combination of several PLL signals, where uncorrelated phase in Fig. 17. One PLL occupies a chip area of 0.11 mm2 and
noise will be reduced. For instance, combining signals from the XO occupies 0.029 mm2 .
eight PLLs reduces uncorrelated noise by 9 dB, whereas cor- In the measurement, the TX baseband inputs were connected
related noise remains the same. Fig. 15 shows the combination to dc voltages, so that each TX output signal was a tone at the
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EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 9

TABLE I
LO G ENERATION S YSTEM P OWER B REAKDOWN

Fig. 16. Measurement setup.

Fig. 17. Die photograph and layout of the active part of the PLL.
Fig. 18. Top: phase noise of XO and FoM versus offset frequency for
sample 2. Bottom: difference between measured and simulated phase noise
for respective sample.
LO frequency. The two PLLs were set to the same frequency,
and a combiner was used to add the two signals and then TABLE II
measured with a Keysight N9030A PXA signal analyzer with XO P ERFORMANCE S UMMARY AND C OMPARISON
phase noise option N9068A. By setting the PLLs to generate
signals in phase, the effect of phase noise correlation could be
investigated in the combined signal. In another setup, the com-
biner was removed and the phase relation between the two
TX output signals was investigated using a Keysight N5242A
PNA-X network analyzer. This was done to investigate the
time stability of the phase relation between the PLLs. The XO
signal was also measured separately using an Agilent E5052B
10-MHz–7-GHz signal source analyzer.
The entire LO generation system consumed in total
34.6 mW, with one PLL consuming 15.4 mW from a 1.2-V
supply, and the XO consuming 0.84 mW from a 1-V supply.
A simulated power consumption breakdown is shown
in Table I.
The phase noise of the XO is shown in Fig. 18. It is even in a 40-GHz system, the contribution is just −42.6 dBc.
−107 dBc/Hz at 1-kHz offset, and the peak FoM equals The performance of the XO is compared with state of the art
256.6 dB at about 8-kHz offset. More important, however, in Table II. As can be seen, increasing the crystal frequency
is the offset region between 20 kHz and the PLL bandwidth from below 100 to 491.52 MHz results in superior start-up
of 1.48 MHz, which will dominate the contribution to the time and EVM in a 5G OFDM system, still with a power
EVM in the 5G OFDM system. The EVM contribution of consumption that is lower than many of the other designs and
this XO phase noise to a 26-GHz system is −46.3 dBc, and that also represents a minor part of the total power of the
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 19. VCO frequency range using coarse and fine tuning.
Fig. 21. Measured phase noise of 26-GHz carrier: single instance and
combined.

signals combined corresponds to an EVM of −34.6 dBc, still

giving room for improvement by increasing the number of
PLLs, the limitation set by the correlated XO phase noise
at −46.3 dBc. A calculation based on these measurement
results indicates that an EVM of −43.6 dBc can be achieved
using 32 PLLs.
The effect of DSM noise correlation was investigated by
measuring the phase noise of the combined signal in two
different cases. In the first case, the two DSMs were operated
without time difference, producing the same division ratio
sequence at the same time. Their noise was then identical and
Fig. 20. Phase noise combining the two TX outputs constructively. hence fully correlated. In the other case, there was a time
difference between the two DSMs, such that the noise in the
two PLLs was different at different times, hence effectively
LO system presented in this paper. Given this, if a crystal with uncorrelated. As can be seen in Fig. 21, where also the
a higher maximum drive level would become available at this phase noise of a single instance is plotted as comparison, this
frequency, it would be beneficial to increase the XO power to de-correlation method works well. The noise in the
further reduce its noise contribution as the number of PLLs is de-correlated case is close to 3 dB less compared with the
increased. single instance case, also where the DSM noise shows up at an
The VCO frequency tuning was then characterized (Fig. 19), offset around 100 MHz. Without the de-correlation, the phase
showing a robust frequency overlap between the different noise rises with close to 3 dB, approaching the single instance
coarse tuning settings. The two targeted 3GPP bands, n257 and case at about 100-MHz offset. It does not reach all the way,
n258 [1], are also well covered. however, as there are also nondominant noise sources like the
The phase noise of a single PLL signal was measured, VCOs which are uncorrelated.
and the total rms jitter integrated from 20 kHz to 500 MHz In a beamforming transceiver, the stability of the phase
was below 160 fs for each output signal over the complete relations between the LO signals used for different antenna
tuning range in Fig. 19. The noise of the two combined PLLs elements is critical. If the phase drifts significantly over
was then measured (see Fig. 20). The carrier frequency was time, re-calibrations or corrections are necessary; otherwise,
25.954 GHz, corresponding to an overall PLL division ratio the antenna gain will drop as signals are no longer added con-
of 35.20 and a multi-modulus divider ratio of 35.20/4 = 8.8. structively. In systems where nulls are formed to avoid interfer-
It is expected to achieve 3 dB less noise when combining two ence from certain directions, the phase accuracy requirement is
un-correlated signals, and as can be seen, the integrated jitter further pronounced. Using the same DSM sequences, delayed
from 20 kHz to 500 MHz was just 115.6 fs, which agrees well by an integer number of reference cycles, ensures that the
with the theory. It should be noted that by combining more average frequencies of the two PLLs are identical. While this
than two PLLs, it is possible to achieve even lower values indicates that the digital part is free from phase drift, there
of jitter. In upcoming 5G systems, many antenna elements can still be errors due to the analog part and due to, for
will be used, and the power combination will then occur in instance, temperature differences between the PLLs. The phase
the air, so that constructive signal addition will be secured difference between the two LO signals was therefore measured
by the beamforming algorithms. The EVM due to phase using the network analyzer (see Fig. 22). It was measured over
noise was calculated by integrating the phase noise versus 10 ks, and as can be seen, there is a slow initial transient
offset frequency using a weighting function for the ICI ratio of about 4° phase shift, before reaching a steady state after
according to [9] for OFDM modulation with 120-kHz sub- roughly 4 ks. Beyond this point, the variation was within a
carrier spacing. The result is that the phase noise for two few degrees with a distribution shown to the right.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 11

TABLE III
C OMPARISON W ITH P UBLISHED F RACTIONAL -N PLL S FOR mmW

Fig. 22. Phase stability between the two PLLs over time and its distribution
(after t = 4000 s).

Fig. 23. Dominant spur levels versus fractional-N spur frequency f s .

Fig. 24. Wide spectrum measurement with 491-MHz offset reference spur Fig. 25. Jitter-power FoM comparison.
at −65.1 dBc.

Fractional-N-based PLLs are known to suffer from frac- EVM figures for the comparison, they have been calculated
tional spurs with levels typically increasing when the division from reported jitter values and normalized to the same carrier
ratio approaches integer values. Fig. 23 shows the measured frequency of 26 GHz. In case a reported jitter value is missing,
main fractional spur at offset fs when the division ratio is the EVM and jitter has instead been extracted from published
swept as N = 36 + f s / f reference . The levels of additional spurs phase noise plots. As can be seen, this paper has the lowest
appearing at fs /2 and f s /4 are also shown. Spur levels are EVM value and jitter, 0.6 dB better than [12], but with a
rather low except for main spur offsets | f s | < 10 MHz, power consumption of just 31 mW compared with 174 mW
corresponding to (|N − [N]| < 0.02). Fortunately, spurs at for [12]. Furthermore, together with [11], it has the lowest
such small offsets, well within the bandwidth of the desired power consumption but with an EVM that is 19 dB better
channel, will have much less impact on system performance than in [11]. The jitter performance and power consump-
compared with spurs at larger offsets. The latter leads to tion are also compared in Fig. 25, where more published
co-channel interference from reciprocal mixing between the fractional-N synthesizers above 10 gigahertz have been
spurs and strong interfering signals in adjacent channels. included [4], [10]–[14], [20], [21], [31]. This paper achieves
A wide spectrum measurement is shown in Fig. 24 to capture a record low FOM j of −244 dB for PLL frequencies above
the reference spur having a level of −65 dBc. 15 GHz. As can be seen, [31] has achieved an even lower
A comparison with published state-of-the-art mmW FOM j (−246.6 dB) but at 10.1–12.4 GHz. Still better values
fractional-N CMOS PLLs is found in Table III. To obtain have been achieved below 5 GHz [30], [33].
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

12 IEEE JOURNAL OF SOLID-STATE CIRCUITS

V. C ONCLUSION [8] A. Axholt and H. Sjöland, “A 60 GHz receiver front-end with PLL
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ACKNOWLEDGMENT
[19] M. M. Ghahramani, Y. Rajavi, A. Khalili, A. Kavousian, B. Kim, and
The authors would like to thank Seiko Epson Corporation M. P. Flynn, “A 192MHz differential XO based frequency quadrupler
for providing packaged crystal prototype samples and electri- with sub-picosecond jitter in 28nm CMOS,” in Proc. IEEE RFIC Symp.,
May 2015, pp. 59–62.
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“A 39.1-to-41.6GHz  fractional-N frequency synthesizer in 90nm
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[Online]. Available: http://www.3gpp.org/ftp/tsg_ran/WG4_Radio/ frequency dividers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55,
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Graz, Austria, Sep. 2015, pp. 76–79. phase-switching prescaler and loop capacitance multiplier,” IEEE
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EK et al.: 28-nm FD-SOI 115-fs JITTER PLL-BASED LO SYSTEM FOR 24–30-GHz SLIDING-IF 5G TRANSCEIVERS 13

[29] M. Kozak and I. Kale, “Rigorous analysis of delta-sigma modulators Andreas Axholt received the M.Sc. degree in
for fractional-N PLL frequency synthesis,” IEEE Trans. Circuits Syst. I, electronic engineering and the Ph.D. degree from
Reg. Papers, vol. 51, no. 6, pp. 1148–1162, Jun. 2004. Lund University, Lund, Sweden, in 2006 and 2011,
[30] X. Gao et al., “A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, respectively.
digital fractional-N sampling PLL in 28nm CMOS,” in IEEE Int. He has a background in the development of inte-
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, grated circuits for telecom applications at sub-3 GHz
pp. 174–175. and at mm-Waves. He is currently with Acconeer,
[31] N. Markulic et al., “A self-calibrated 10Mb/s phase modulator with Lund, as an Analog ASIC Architect developing fully
−37.4 dB EVM based on a 10.1-to-12.4GHz, −246.6 dB-FOM, integrated radar circuits with an antenna array in
fractional-N subsampling PLL,” in IEEE Int. Solid-State Circuits Conf. package. His current research interests include the
(ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, pp. 176–177. design and analysis of analog integrated circuits and
[32] J. Shin and H. Shin, “A fast and high-precision VCO frequency calibra- mm-wave CMOS for various applications.
tion technique for wideband  fractional-N frequency synthesizers,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582,
Jul. 2010.
[33] A. T. Narayanan et al., “A fractional-N sub-sampling PLL using a
pipelined phase-interpolator with an FoM of −250 dB,” IEEE J. Solid-
State Circuits, vol. 51, no. 7, pp. 1630–1640, Jul. 2016. Anna-Karin Stenman (M’18) received the
M.Sc.E.E. degree from the Department of Applied
Electronics, Lund University, Lund, Sweden,
Staffan Ek was born in Jönköping, Sweden, in 1978. in 1993, and the Lic.E.E. degree from the
He received the M.Sc. degree in electrical engineer- Department of Electroscience, Lund University,
ing from Lund University, Lund, Sweden, in 2002. in 2001.
Since 2002, he has been involved in CMOS From 1993 to 1997, she was with the RFIC
transceiver design, frequency synthesizers, and Department, Ericsson Mobile Communication,
analog/mixed-signal circuits. He has been with Lund. From 2002 to 2003, she was with Acreo/Via
Acreo, Lund; Infineon Austria, Villach, Austria; and Lund, Lund, Sweden, as an RFIC Engineer. From
Ericsson Research, Ericsson, Lund. Since 2017, he 2003 to 2008, she was an RF Engineer with Nokia,
has been a Staff Engineer with Arm Sweden, Lund. Copenhagen, Denmark. Since 2008, she has been an RFIC Engineer with
Ericsson, Lund.

Tony Påhlsson received the M.Sc. degree in electri-

cal engineering from Lund University, Lund, Swe-
den, in 2001.
From 2001 to 2005, he was with Acreo, Lund,
as an RF ASIC Designer. From 2005 to 2008, Lars Sundström (S’91–M’95) received the M.Sc.
he was with Altran Sweden as an RF Consultant degree in electrical engineering and the Ph.D. degree
at Ericsson, Lund. In 2008, he joined Ericsson as in applied electronics from Lund University, Lund,
an RF ASIC Designer. Since 2014, he has been Sweden, in 1989 and 1995, respectively.
with Ericsson Research, Ericsson, Lund, where he From 1995 to 2000, he was an Associate Professor
is currently a Senior Researcher. He holds 13 patent with the Competence Center for Circuit Design,
applications. His current research interests include Lund University, where he was involved in linear
CMOS transceiver and frequency synthesizer design. radio transmitters and RF integrated circuits design.
In 2000, he joined Ericsson Research, Ericsson,
Lund, where he is currently a Principal Researcher
Christian Elgaard received the M.Sc. degree in and is involved in mixed-signal and RF design,
engineering physics from Lund University, Lund, and radio architectures for mobile system transceivers. He has authored or
Sweden, in 2002, where he is currently pursuing the co-authored over 60 international peer-reviewed journal and conference
Industrial Ph.D. degree at the Department of Elec- papers. He holds over 50 granted patents on different inventions.
trical and Information Technology, Lund University, Dr. Sundström is a member of the Technical Program Committee of the
Lund. European Solid-State Circuits Conference.
From 2003 to 2014, he held different positions at
Ericsson, Lund; Nokia, Copenhagen, Denmark; and
Cambridge Silicon Radio (CSR), Lund. Since 2015,
he has been a Senior Researcher with the RF ASIC
Systems Group, Ericsson Research, Ericsson, Lund.
Over the years, he has designed various analog blocks aimed for 2G–5G radio Henrik Sjöland (M’98–SM’10) received the M.Sc.
systems, including low-noise amplifiers, mixers, voltage-controlled oscillators, degree in electrical engineering and the Ph.D. degree
crystal oscillator baseband filters, and power amplifiers ranging from low from Lund University, Lund, Sweden, in 1994 and
frequencies to the mm-wave domain. He has authored one international peer- 1997, respectively.
reviewed journal paper and one international peer-reviewed conference paper. In 1999, he held a post-doctoral position with
He holds nine patent applications. the University of California at Los Angeles, Los
Angeles, CA, USA, on a Fulbright Scholarship.
Anders Carlsson (M’03) received the M.S.E.E. He has been an Associate Professor with Lund Uni-
and Lic.E.E. degrees from Lund University, Lund, versity since 2000 and a Full Professor since 2008.
Sweden, in 1993 and 1998, respectively. Since 2002, he has also been part-time employed
From 1993 to 1998, he was a Research Assistant, with Ericsson Research, Ericsson, Lund, where he
conducting research studies at the Department of is currently a Research Fellow. He has successfully been the main supervisor
Industrial Electrical Engineering and Automation, of 13 Ph.D. students to receive their degrees. He has authored or co-authored
Lund University. From 1999 to 2007, he was a over170 international peer-reviewed journal and conference papers. He holds
Consultant and a Contractor at Enea, with customers patents on over 25 different inventions. His current research interests include
in the telecom and optical media businesses. Since the design of radio frequency, microwave, and mm-wave integrated circuits,
2007, he has been a Senior Researcher with Ericsson primarily in the CMOS technology.
Research, Ericsson, Lund. His current research inter- Dr. Sjöland has been a member of the Technical Program Committee of the
ests include real-time software, real-time operating systems, signal processing, European Solid-State Circuits Conference. He has been an Associate Editor of
hardware/software interfaces, and circuit design for measurement and control the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS II. He is currently an
systems. Associate Editor of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS I.