Arithmetic Logic Unit: School of Electronics Engineering

CSE 1003
Arithmetic Logic Unit
Dr. Shweta B. Thomas

School of Electronics Engineering
Dr. Shweta B. Thomas, VIT Vellore
Bus Organization
 The processor part of a computer CPU is sometimes referred to as the

data path of the CPU because the processor forms the paths for the data
transfers between the registers in the unit.
 When a large number of registers are included in a processor unit, it is
most efficient to connect them through common buses or arrange them
as a small memory having very fast access time.
 The registers communicate with each other not only for direct data
transfers, but also while performing various micro operations.

 Each register is connected to two multiplexers (MUX) to form input buses
A and B. The selection lines of each multiplexer select one register for
the particular bus.
 The A and B buses are applied to a common arithmetic logic unit. The
function selected in the ALU determines the particular operation that is
to be performed.
 The shift micro operations are implemented in the shifter. The result of
the micro operation goes through the output bus S into the inputs of all
registers.
 The destination register that receives the information from the output
bus is selected by a decoder. When enabled, this decoder activates one
of the register load inputs to provide a transfer path between the data
on the S bus and the inputs of the
Dr. Shweta selected
B. Thomas, destination register.
VIT Vellore
 The control unit that supervises the processor bus system directs the
information flow through the ALU by selecting the various components
in the unit. For example, to perform the micro operation: R1 ← R2 + R3
the control must provide binary selection variables to the following
selector inputs:
 MUX A selector: to place the contents of R2 onto bus A.
 MUX B selector: to place the contents of R3 onto bus B.
 ALU function selector: to provide the arithmetic operation A + B.
 Shift selector: for direct transfer from the output of the ALU onto
output bus S (no shift).
 Decoder destination selector: to transfer the contents of bus S into R 1

Arithmetic Logic Unit
 An arithmetic logic unit (ALU) is a multioperation, combinational-

logic digital function which can perform a set of basic arithmetic
operations and a set of logic operations.
 The ALU has a number of selection lines to select a particular
operation in the unit.
 The selection lines are decoded within the ALU so that k selection
variables can specify up to 2k distinct operations.

 The four data inputs from A are combined with the four inputs from B to
generate an operation at the F outputs.
 The mode-select input s2 distinguishes between arithmetic and logic
operations. The two function-select inputs s1 and s0 specify the
particular arithmetic or logic operation to be generated.
 With three selection variables, it is possible to specify four arithmetic
operations (with s2 in one state) and four logic operations (with s2 in the
other state).
 The input and output carries have meaning only during an arithmetic
operation. The input carry in the least significant position of an ALU is
quite often used as a fourth selection variable that can double the
number of arithmetic operations. In this way, it is possible to generate
four more operations, for Dr.
a Shweta
totalB.of eight
Thomas, arithmetic operations.
VIT Vellore
Design of Arithmetic Circuit
 The basic component of the arithmetic section of an ALU is a parallel

adder.
 By controlling the data inputs to the parallel adder, it is possible to obtain
different types of arithmetic operations.
 The number of bits in the parallel adder may be of any value. The input
carry Cin goes to the full-adder circuit in the least significant bit position.
The output carry Cout comes from the full-adder circuit in the most
significant bit position.
 The arithmetic addition is achieved when one set of inputs receives a
binary number A, the other set of inputs receives a binary number B, and
the input carry is maintained at 0.
Design of Logic Circuit
 The diagram shows one typical stage designated by subscript i. The

circuit must be repeated n times for an n-bit logic circuit. The Four gates
generate the four logic operations OR, XOR, AND, and NOT.
 The two selection variables in the multiplexer select one of the gates for
the output.
 The function table lists the output logic generated as a function of the
two selection variables.
 The logic circuit can be combined with the arithmetic circuit to produce
one arithmetic logic unit.
 Selection variables s1 and s0 can be made common to both sections
provided we use a third selection variable, s2, to differentiate between
the two. Dr. Shweta B. Thomas, VIT Vellore
Design of Shifter
 The shift unit attached to a processor transfers the output of the ALU
onto the output bus. The shifter may transfer the information directly
without a shift, or it may shift the information to the right or left.
 An obvious circuit for a shifter is a bidirectional shift-register with parallel
load. The information from the ALU can be transferred to the register in
parallel and then shifted to the right or left.
 A combinational-logic shifter can be constructed with multiplexers as
shown in Figure.

 The two selection variables, H1 and H0, applied to all four multiplexers
select the type of operation in the shifter.
 With H1H0 = 00, no shift is executed and the signals from F go directly to
the S lines. The next two selection variables cause a shift-right operation
and a shift-left operation.
 When H1H0 = 11, the multiplexers select the inputs attached to 0 and as
a consequence the S outputs are also equal to 0, blocking the transfer of
information from the ALU to the output bus.

Design of Accumulator


Arithmetic Logic Unit: School of Electronics Engineering

Uploaded by

Copyright:

Available Formats

Arithmetic Logic Unit: School of Electronics Engineering

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Arithmetic Logic Unit: School of Electronics Engineering

Uploaded by

Copyright:

Available Formats

CSE 1003

Arithmetic Logic Unit

Dr. Shweta B. Thomas

 The processor part of a computer CPU is sometimes referred to as the

Dr. Shweta B. Thomas, VIT Vellore

Dr. Shweta B. Thomas, VIT Vellore

 An arithmetic logic unit (ALU) is a multioperation, combinational-

Dr. Shweta B. Thomas, VIT Vellore

 The basic component of the arithmetic section of an ALU is a parallel

 The diagram shows one typical stage designated by subscript i. The

Dr. Shweta B. Thomas, VIT Vellore

Dr. Shweta B. Thomas, VIT Vellore

Dr. Shweta B. Thomas, VIT Vellore

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.