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LM833
SLOS481B – JULY 2010 – REVISED OCTOBER 2014

LM833 Dual High-Speed Audio Operational Amplifier

1 Features 3 Description
•
1 Dual-Supply Operation: ±5 V to ±18 V The LM833 device is a dual operational amplifier with
high-performance specifications for use in quality
• Low Noise Voltage: 4.5 nV/√Hz audio and data-signal applications. Dual amplifiers
• Low Input Offset Voltage: 0.15 mV are utilized widely in audio circuits optimized for all
• Low Total Harmonic Distortion: 0.002% preamp and high level stages in PCM and HiFi
• High Slew Rate: 7 V/μs systems. The LM833 device is pin-for-pin compatible
with industry-standard dual operation amplifiers. With
• High-Gain Bandwidth Product: 16 MHz addition of a preamplifier, the gain of the power stage
• High Open-Loop AC Gain: 800 at 20 kHz can be greatly reduced to improve performance.
• Large Output-Voltage Swing: –14.6 V to 14.1 V
Device Information
• Excellent Gain and Phase Margins
PART NUMBER PACKAGE BODY SIZE (NOM)
• Available in 8-Terminal MSOP Package
SOIC (8) 4.90 mm × 3.91 mm
(3.0 mm x 4.9 mm x 0.65 mm)
LM833 VSSOP (8) 3.00 mm × 3.00 mm
PDIP (8) 9.81 mm × 6.35 mm
2 Applications
• HiFi Audio System Equipment
• Preamplification and Filtering
• Set-Top Box
• Microphone Preamplifier Circuit
• General-Purpose Amplifier Applications

4 Typical Design Example Audio Pre-Amplifier

+VCC

750

47 µF 0.1 µF

1000
Audio
Input 1 µF 2.7 k 0.0022 µF

47 k
2.7 k OUT1 VCC+
IN1± OUT2
IN1+ IN2±
0.001 µF VCC± IN2+ 10 k

0.1 µF 47 µF

750

±VEE 12 V / 1 W

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM833
SLOS481B – JULY 2010 – REVISED OCTOBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 14
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 9 Application and Implementation ........................ 15
4 Typical Design Example Audio Pre-Amplifier..... 1 9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
5 Revision History..................................................... 2
9.3 Typical Application — Reducing Oscillation from
6 Pin Configuration and Functions ......................... 3 High-Capacitive Loads............................................. 18
7 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 20
7.1 Absolute Maximum Ratings ..................................... 4
11 Layout................................................................... 20
7.2 Handling Ratings....................................................... 4
11.1 Layout Guidelines ................................................. 20
7.3 Recommended Operating Conditions....................... 4
11.2 Layout Example .................................................... 20
7.4 Thermal Information .................................................. 4
12 Device and Documentation Support ................. 22
7.5 Electrical Characteristics........................................... 5
12.1 Trademarks ........................................................... 22
7.6 Operating Characteristics.......................................... 5
12.2 Electrostatic Discharge Caution ............................ 22
7.7 Typical Characteristics .............................................. 6
12.3 Glossary ................................................................ 22
8 Detailed Description ............................................ 13
13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 13
Information ........................................................... 23
8.2 Functional Block Diagram ....................................... 13

5 Revision History
Changes from Revision A (August 2010) to Revision B Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Deleted Ordering Information table. ....................................................................................................................................... 1
• Added Device Information table. ............................................................................................................................................ 1
• Added Pin Functions table. .................................................................................................................................................... 3
• Added Handling Ratings table. ............................................................................................................................................... 4
• Added Thermal Information table. .......................................................................................................................................... 4
• Added Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging,
and Orderable Information sections .................................................................................................................................... 20

Changes from Original (July 2010) to Revision A Page

• Changed data sheet status from Product Preview to Production Data. ................................................................................. 1

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6 Pin Configuration and Functions

D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE
(TOP VIEW)

OUT1 1 8 VCC+

IN1– 2 7 OUT2

IN1+ 3 6 IN2–

VCC– 4 5 IN2+

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
IN1+ 3 Input Noninverting input
IN1– 2 Input Inverting Input
IN2+ 5 Input Noninverting input
IN2- 6 Input Inverting Input
OUT1 1 Output Output 1
OUT2 7 Output Output 2
VCC+ 8 — Positive Supply
VCC– 4 — Negative Supply

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ Supply voltage (2) 18 V
(2)
VCC– Supply voltage –18 V
VCC+ – VCC– Supply voltage 36 V
Input voltage, either input (2) (3) VCC– VCC+ V
(4)
Input current ±10 mA
Duration of output short circuit (5) Unlimited
TJ Operating virtual junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
(3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
(4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
(5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.

7.2 Handling Ratings

PARAMETER DEFINITION MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human-Body Model (HBM) (1) 0 2.5
V(ESD) kV
Charged-Device Model (CDM) (2) 0 1.5

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC– –5 –18
Supply voltage V
VCC+ 5 18
TA Operating free-air temperature range –40 85 °C

7.4 Thermal Information

LM833
THERMAL METRIC (1) D DGK P UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance (2) (3) 97 172 85 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

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7.5 Electrical Characteristics

VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C 0.15 2
VIO Input offset voltage VO = 0, RS = 10 Ω, VCM = 0 mV
TA = –40°C to 85°C 3
Input offset voltage
αVIO VO = 0, RS = 10 Ω, VCM = 0 TA = –40°C to 85°C 2 μV/°C
temperature coefficient
TA = 25°C 300 750
IIB Input bias current VO = 0, VCM = 0 nA
TA = –40°C to 85°C 800
TA = 25°C 25 150
IIO Input offset current VO = 0, VCM = 0 nA
TA = –40°C to 85°C 175
Common-mode input voltage
VICR ΔVIO = 5 mV, VO = 0 ±13 ±14 V
range
Large-signal differential TA = 25°C 90 110
AVD RL ≥ 2 kΩ, VO = ±10 V dB
voltage amplification TA = –40°C to 85°C 85
VOM+ 10.7
RL = 600 Ω
VOM– –11.9
Maximum output voltage VOM+ 13.2 13.8
VOM VID = ±1 V RL = 2000 Ω V
swing VOM– –13.2 –13.7
VOM+ 13.5 14.1
RL = 10,000 Ω
VOM– –14 –14.6
CMMR Common-mode rejection ratio VIN = ±13 V 80 100 dB
kSVR (1) Supply-voltage rejection ratio VCC+ = 5 V to 15 V, VCC– = –5 V to –15 V 80 105 dB
Source current 15 29
IOS Output short-circuit current |VID| = 1 V, Output to GND mA
Sink current –20 –37
TA = 25°C 2.05 2.5
ICC Supply current (per channel) VO = 0 mA
TA = –40°C to 85°C 2.75

(1) Measured with VCC± differentially varied at the same time

7.6 Operating Characteristics

VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR Slew rate at unity gain AVD = 1, VIN = –10 V to 10 V, RL = 2 kΩ, CL = 100 pF 5 7 V/μs
GBW Gain bandwidth product f = 100 kHz 10 16 MHz
B1 Unity gain frequency Open loop 9 MHz
CL = 0 pF –11
Gm Gain margin RL = 2 kΩ dB
CL = 100 pF –6
CL = 0 pF 55
Φm Phase margin RL = 2 kΩ degrees
CL = 100 pF 40
Amp-to-amp isolation f = 20 Hz to 20 kHz –120 dB
Power bandwidth VO = 27 V(PP), RL = 2 kΩ, THD ≤ 1% 120 kHz
THD Total harmonic distortion VO = 3 Vrms, AVD = 1, RL = 2 kΩ, f = 20 Hz to 20 kHz 0.002%
zo Open-loop output impedance VO = 0, f = 9 MHz 37 Ω
rid Differential input resistance VCM = 0 175 kΩ
Cid Differential input capacitance VCM = 0 12 pF
Vn Equivalent input noise voltage f = 1 kHz, RS = 100 Ω 4.5 nV/√Hz
In Equivalent input noise current f = 1 kHz 0.5 pA/√Hz

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7.7 Typical Characteristics

0.1 µF

10 Ω 100 kΩ

2.0 kΩ
4.3 kΩ 22 µF
D.U.T. +
1/2 Scope
LM833
− x1
4.7 µF RIN = 1.0 MΩ

100 kΩ
Voltage Gain = 50,000 2.2 µF

24.3 kΩ 110 kΩ

0.1 µF

NOTE: All capacitors are non-polarized.

Figure 1. Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

600 600
VCC+ = 15 V VCM = 0 V
VCC– = –15 V TA = 25°C
500 500
TA = 25°C
IIB – Input Bias Current – nA
IIB – Input Bias Current – nA

400 400

300 300

200 200

100 100

0 0
-15 -10 -5 0 5 10 15 5 6 7 8 9 10 11 12 13 14 15 16 17 18

VCM – Common Mode Voltage – V VCC+/–VCC– – Supply Voltage – V

Figure 2. Input Bias Current vs Common-Mode Voltage Figure 3. Input Bias Current vs Supply Voltage

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Typical Characteristics (continued)

1000 2
VCC+ = 15 V VCC+ = 15 V
900 VCC– = –15 V 1.5 VCC– = –15 V
800 VCM = 0 V VCM = 0 V

VIO – Input Offset Voltage – mV

IIB – Input Bias Current – nA

1
700

600 0.5

500 0

400
-0.5
300
-1
200

100 -1.5

0 -2
-55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 125
TA – Temperature – °C TA – Temperature – °C

Figure 4. Input Bias Current vs Temperature Figure 5. Input Offset Voltage vs Temperature

1.4 0
VCC+ = 3 V to 15 V
1.2 -0.2 VCC– = -3 V to -15 V

Input Common-Mode Voltage High

Input Common-Mode Voltage Low

D VIO = 5 mV

1 VO = 0 V
Proximity to V CC– – V

-0.4

Proximity to V CC+ – V
0.8 -0.6

0.6 -0.8

VCC+ = 3 V to 15 V
0.4 -1
VCC– = -3 V to -15 V
D
è VIO = 5 mV
0.2 -1.2
VO = 0 V

0 -1.4
-55 -25 5 35 65 95 125 -55 -25 5 35 65 95 125
TA – Temperature – °C TA – Temperature – °C

Figure 6. Input Common-Mode Voltage Low Proximity Figure 7. Input Common-Mode Voltage High Proximity
to VCC– vs Temperature to VCC+ vs Temperature

0 10

-1 9
TA = 125°C
-2 8
Output Saturation Voltage

TA = 25°C
Output Saturation Voltage
Proximity to V CC+ – V

-3
Proximity to V CC– – V

TA = –55°C 7
-4
6
-5
5
TA = 125°C
-6
4
TA = 25°C
-7
3
TA = –55°C
-8
2
-9
1
-10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
kW
RL – Load Resistance – kh
kW
RL – Load Resistance – k@

Figure 8. Output Saturation Voltage Proximity to VCC+

Figure 9. Output Saturation Voltage Proximity to VCC–
vs Load Resistance
vs Load Resistance

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Typical Characteristics (continued)

70 10
VCC+ = 15 V
9 VCM = 0 V
IOS – Output Short-Circuit Current – mA

VCC– = –15 V
60 RL = High Impedance
VID = 1 V 8
VO = 0 V

ICC – Supply Current – mA

7
50
6
VCC± = ±15 V
40 5
Source
4
Sink
30
3 VCC± = ±10 V
VCC± = ±5 V
2
20
1

10 0
-55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 125
TA – Temperature – °C TA – Temperature – °C

Figure 10. Output Short-Circuit Current vs Temperature Figure 11. Supply Current vs Temperature

100 120
VCC+ = 15 V VCC+ = 15 V
90 VCC– = –15 V 110
VCC– = –15 V
VCM = 0 V 100 TA = 25°C
80 DVCM = ±1.5 V
TA = 25°C 90
70
80
60
CMMR – dB

PSRR – dB
70
T3P
50 60

40 50
T3N
40
30
30
20
20
10 10
0 0
100
1.0E+02 1k
1.0E+03 10k
1.0E+04 100k 1.0E+06
1.0E+05 1M 10M
1.0E+07 1.0E+02 1.0E+03 1.0E+04 1.0E+05
100 1k 10k 100k 1.0E+06
1M 1.0E+07
10M
f – Frequency – Hz f – Frequency – Hz

Figure 12. CMRR vs Frequency Figure 13. PSSR vs Frequency

30 30
GBW – Gaind Bandwidth Product – MHz

GBW – Gain Bandwidth Product – MHz

25 25

20 20

15 15

10 10

5 5

0 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 -55 -35 -15 5 25 45 65 85 105 125
VCC+/–VCC– – Supply Voltage – V TA – Temperature – °C

Figure 14. Gain Bandwidth Product vs Supply Voltage Figure 15. Gain Bandwidth Product vs Temperature

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Typical Characteristics (continued)

20 30
VCC+ = 15 V
VCC– = –15 V
15 RL = 2 kW
RL = 10 kW 25 AV = 1
10 THD < 1%
VO – Output Voltage – V

VO – Output Voltage – V
RL = 2 kW TA = 25°C
20
5

0 15

-5
RL = 10 kW 10
-10
RL = 2 kW
5
-15

-20 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k 1.E+06
1.E+05 1M 10M
1.E+07
VCC+/–VCC– – Supply Voltage – V f – Frequency – Hz

Figure 16. Output Voltage vs Supply Voltage Figure 17. Output Voltage vs Frequency

110 120
RL = 2 kW
f < 10 Hz
115
105 DVO = 2/3(VCC+ – VCC–)
TA = 25°C
AV – Open-Loop Gain – dB

AV – Open-Loop Gain – dB
110
100
105

95 100

95
90

RL = 2 kW 90
85 f < 10 Hz
DVO = 2/3(VCC+ – VCC–) 85
TA = 25°C
80 80
5 6 7 8 9 10 11 12 13 14 15 16 17 18 -55 -35 -15 5 25 45 65 85 105 125
VCC+/–VCC– – Supply Voltage – V TA – Temperature – °C

Figure 18. Open-Loop Gain vs Supply Voltage Figure 19. Open-Loop Gain vs Temperature

50 200
VCC+ = 15 V Drive Channel
45 190 VCC+ = 15 V
VCC– = –15 V
VCC– = –15 V
40 VO = 1 Vrms 180 RL = 2 kW
ZO – Output Impedance – W

TA = 25°C VO = 20 VPP
Crosstalk Rejection – dB

35 170 TA = 25°C

30 160

25 150

20 140

15 130
AV = 1000
10 120
AV = 100 AV = 10 AV = 1
5 110

0 100
1.0E+03
1k 1.0E+04
10k 1.0E+05
100k 1.0E+06
1M 1.0E+07
10M 1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k
f – Frequency – Hz f – Frequency – Hz

Figure 20. Output Impedance vs Frequency Figure 21. Crosstalk Rejection vs Frequency

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Typical Characteristics (continued)

1 1
VCC+ = 15 V
VCC– = –15 V
VO = 1 Vrms AV = 1000
THD – Total Harmonic Distortion – %

THD – Total Harmonic Distortion – %

AV = 1
0.1 RL = 2 kW 0.1
TA = 25°C
AV = 100

0.01 0.01

AV = 10

0.001 0.001
VCC+ = 15 V
AV = 1
VCC– = –15 V
f = 2 kHz
RL = 2 kW
TA = 25°C
0.0001 0.0001
10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 0 1 2 3 4 5 6 7 8 9
f – Frequency – Hz VO – Output Voltage – Vrms

Figure 22. Total Harmonic Distortion vs Frequency Figure 23. Total Harmonic Distortion vs Output Voltage

10 10

9 9

8 Falling Edge 8
Falling Edge
SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

7 7
Rising Edge Rising Edge
6 6

5 5
VCC+ = 15 V
4 DV = 2/3(V – V ) 4 VCC– = –15 V
IN CC+ CC–

AV = 1 DVIN = 20 V
3 RL = 2 kW AV = 1
3 RL = 2 kW
TA = 25°C
2 2
5 6 7 8 9 10 11 12 13 14 15 16 17 18 -55 -35 -15 5 25 45 65 85 105 125
VCC+/–VCC– – Supply Voltage – V TA – Temperature – °C

Figure 24. Slew Rate vs Supply Voltage Figure 25. Slew Rate vs Temperature

80 0 12 0
Phase Gain, TA = 125°C VCC+ = 15 V
VCC– = –15 V
70 VO = 0 V 10
Gain, TA = 25°C

60 -45 9 20
Phase Margin – deg

Gain Gain, TA = –55°C

Gain Margin – dB
Phase Shift – deg

50 30
Gain – dB

40 -90 6 40
Phase, TA = 125°C
30 50

20 -135 3 60
VCC+ = 15 V Phase, TA = 25°C
VCC– = –15 V
10 RL = 2 kW 70
Phase, TA = –55°C
TA = 25°C
0 -180 0 80
1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M 1.E+07
10M 1 10 100 1000

f – Frequency – Hz Cout – Output Load Capacitance – pF

Figure 26. Gain and Phase vs Frequency Figure 27. Gain and Phase Margin
vs Output Load Capacitance

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Typical Characteristics (continued)

100 100 10
VCC+ = 15 V VCC+ = 15 V
90
VCC– = –15 V VCC– = –15 V
80 VIN = 100 mVPP TA = 25°C

Input Voltage Noise – nV/rtHz

Input Current Noise – pA/rtHz

nV/ÖHz

pA/ÖHz
70
Overshoot – %

60

50 10 1

40 Input Voltage Noise

TA = 125°C
30

20 Input Current Noise

TA = 25°C
10
TA = –55°C
0 1 0.1
10 100 1000 10 100 1k
1000 10k
10000 100k
100000
Cout – Output Load Capacitance – pF f – Frequency – Hz

Figure 28. Overshoot vs Output Load Capacitance Figure 29. Input Voltage and Current Noise vs Frequency

1000 16 64
VCC+ = 15 V 60
VCC– = –15 V 14 56
Input Referred Noise Voltage – nV/rtHz
nV/ÖHz

f = 1 Hz 52
TA = 25°C 12 48
Phase Margin
44
100

Phase Margin – deg

Gain Margin – dB
10 40
Gain Margin 36
8 32
28
6 VCC+ = 15 V 24
10
VCC– = –15 V 20
4 AV = 100 16
VO = 0 V 12
2 TA = 25°C 8
4
1 0 0
1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M 00 1 10
10 100
10 0 101k
00 1010k
0 0 0 10100k
0000

RS – Source Resistance – W
è RSD – Differential Source Resistance – W
è

Figure 30. Input Referred Noise Voltage Figure 31. Gain and Phase Margin
vs Source Resistance vs Differential Source Resistance

Input Input
55 10 55 10

45 0 45 0
VO – Output Voltage – V

VO – Output Voltage – V
VI – Input Voltage – V

VI – Input Voltage – V

35 -10 35 -10
VCC+ = 15 V
VCC+ = 15 V VCC– = –15 V
25 VCC– = –15 V -20 25 AV = –1 -20
AV = 1 RL = 2 kW
RL = 2 kW CL = 100 pF
15 CL = 100 pF -30 15 TA = 25°C -30
Output Output
TA = 25°C
5 -40 5 -40

-5 -50 -5 -50

-15 -60 -15 -60

-2 2 6 10 14 18 22 -2 2 6 10 14 18 22
Time – µs Time – µs

Figure 32. Large Signal Transient Response (AV = 1) Figure 33. Large Signal Transient Response (AV = –1)

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Typical Characteristics (continued)

0.6 0.2 400

0.5 0.1 300

200
0.4 0.0

Input Voltage Noise – nV

VO – Output Voltage – V

VI – Input Voltage – V
Input 100
0.3 -0.1
VCC+ = 15 V 0
VCC– = –15 V
0.2 AV = 1 -0.2
-100
RL = 2 kW
0.1 CL = 100 pF -0.3 -200 T3
TA = 25°C
VCC+ = 15 V
0 -0.4 -300
VCC– = –15 V
Output BW = 0.1 Hz to 10 Hz
-0.1 -0.5 -400
TA = 25°C
-500
-0.2 -0.6 -5 -4 -3 -2 -1 0 1 2 3 4 5
-0.5 0.0 0.5 1.0 1.5
Time – s
Time – µs

Figure 35. Low-Frequency Noise

Figure 34. Small Signal Transient Response

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8 Detailed Description

8.1 Overview
The LM833 device is a dual operational amplifier with high-performance specifications for use in quality audio
and data-signal applications. This device operates over a wide range of single- and dual-supply voltage with low
noise, high-gain bandwidth, and high slew rate. Additional features include low total harmonic distortion, excellent
phase and gain margins, large output voltage swing with no deadband crossover distortions, and symmetrical
sink/source performance. The dual amplifiers are utilized widely in circuit of audio optimized for all preamp and
high-level stages in PCM and HiFi systems. The LM833 device is pin-for-pin compatible with industry-standard
dual operation amplifiers' pin assignments. With addition of a preamplifier, the gain of the power stage can be
greatly reduced to improve performance.

8.2 Functional Block Diagram

VCC

INí IN+

VOUT

VEE

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8.3 Feature Description

8.3.1 Operating Voltage
The LM833 operational amplifier is fully specified and ensured for operation from ±5 V to ±18 V. In addition,
many specifications apply from –40°C to 85°C. Parameters that vary significantly with operating voltages or
temperature are shown in Absolute Maximum Ratings .

8.3.2 High Gain Bandwidth Product

Gain bandwidth product is found by multiplying the measured bandwidth of an amplifier by the gain at which that
bandwidth was measured. The LM833 has a high gain bandwidth of 16 MHz which stays relatively stable over a
wide range of supply voltages. Parameters that vary significantly with temperature are shown in Figure 14.

8.3.3 Low Total Harmonic Distortion

Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The LM833
has a very low THD of 0.002% meaning that the LM833 will add little harmonic distortion when used in audio
signal applications. More specific characteristics are shown in Figure 22.

8.4 Device Functional Modes

The LM833 is powered on when the supply is connected. It can be operated as a single supply operational
amplifier or dual supply amplifier depending on the application.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

An application of the LM833 is the two stage RIAA Phono Preamplifier. A primary task of the phono preamplifier
is to provide gain (usually 30 to 40 dB at 1 kHz) and accurate amplitude and phase equalization to the signal
from a moving magnet or a moving coil cartridge. In addition to the amplification and equalization functions, the
phono preamp must not add significant noise or distortion to the signal from the cartridge. The circuit shown in
Figure 36 uses two amplifiers, fulfills these qualifications, and has greatly improved performance over a single-
amplifier design.

9.2 Typical Application

R3 C4 15 V
½ LM833
3 + 2.37 2 PF
VIN 1 5 + 8
47 k 2 7 VOUT
CP 4 6
R6
C3 54.9 k
-15 V ½ LM833
33 nF
R1 R2
80.6 k 8.45 k
R5
R4 4.3 k
2 k
C1
R0 39 nF
499

C0
200 PF

Figure 36. RIAA Phono Preamplifier

9.2.1 Design Requirements

• Supply Voltage = ±15 V
• Low-Frequency −3 dB corner of the first amplifier (f0) > 20 Hz (below audible range)
• Low-Frequency −3 dB corner of the second stage (fL) = 20.2 Hz

9.2.2 Detailed Design Procedure

9.2.2.1 Introduction to Design Method

Equation 1 through Equation 5 show the design equations for the preamplifier.
R1 = 8.058 R0A1
where
• A1 is the 1 kHz voltage gain of the first amplifier (1)

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Typical Application (continued)

3.18 ´10-3
C1 =
R1 (2)
R
R 2 = 1 - R0
9 (3)
-5
(R3 + R6 ) 7.5 ´10
C3 = 7.5 ´10-5 =
R3 R 6 RP (4)
1
C4 =
2 p f L (R3 + R6 )

where
• fL is the low-frequency −3 dB corner of the second stage (5)
For standard RIAA preamplifiers, fL should be kept well below the audible frequency range. If the preamplifier is
to follow the IEC recommendation (IEC Publication 98, Amendment #4), fL should equal 20.2 Hz.
R
A V2 = 1 + 5
R4
where
• AV2 is the voltage gain of the second amplifier (6)
1
C0 »
2 p f0 R0
where
• f0 is the low-frequency −3 dB corner of the first amplifier (7)
This should be kept well below the audible frequency range.
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Because 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.

9.2.2.2 RIAA Phono Preamplifier Design Procedure

A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Since 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.
Choose R0. R0 should be small for minimum noise contribution, but not so small that the feedback network
excessively loads the amplifier.
Example: Choose R0 = 500
Choose 1 kHz gain, AV1 of first amplifier. This will typically be around 20 dB to 30 dB.
Example: Choose AV1 = 26 dB = 20
Calculate R1 = 8.058 R0AV1
Example: R1 = 8.058 × 500 × 20 = 80.58 k
3.18 ´10-3
Calculate C1 =
R1 (8)
3.18 ´10-3
Example : C1 = = 0.03946 mF
8.058 ´104 (9)
If C1 is not a convenient value, choose the nearest convenient value and calculate a new R1 from Equation 10.

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Typical Application (continued)

3.18 ´10-3
R1 =
C1 (10)
Example: New C1 = 0.039 μF.
3.18 ´10-3
New R1 = = 81.54k
3.9 ´10-8

Use R1 = 80.6k (11)

Calculate a new value for R0 from Equation 12.
R1
R0 =
8.058 A V1 (12)
4
8.06 ´10
Example: New R0 = = 498.8
8.058 ´ 20 (13)
Use R0 = 499.
R1
Calculate R2 = - R0
9

8.06 ´104
Example : R2 = - 499 = 8456.56
9 (14)
Use R2 = 8.45 K.
Choose a convenient value for C3 in the range from 0.01 μF to 0.05 μF.
Example: C3 = 0.033 μF
7.5 ´10-5
Calculate RP =
C3

7.5 ´10-5
Example: RP = = 2.273k
3.3 ´10-8 (15)
Choose a standard value for R3 that is slightly larger than RP.
Example: R3 = 2.37 k
Calculate R6 from 1 / R6 = 1 / RP − 1 / R3
Example: R6 = 55.36 k
Use 54.9 k
Calculate C4 for low-frequency rolloff below 1 Hz from design Equation 5.
Example: C4 = 2 μF. Use a good quality mylar, polystyrene, or polypropylene.
Choose gain of second amplifier.
Example: The 1 kHz gain up to the input of the second amplifier is about 26 dB for this example. For an
overall 1 kHz gain equal to about 36 dB we choose:
AV2 = 10 dB = 3.16
Choose value for R4.
Example: R4 = 2 k
Calculate R5 = (AV2 − 1) R4
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Typical Application (continued)

Example: R5 = 4.32 k
Use R5 = 4.3 k
Calculate C0 for low-frequency rolloff below 1 Hz from design Equation 7.
Example: C0 = 200 μF

9.2.3 Application Curves for Output Characteristics

The maximum observed error for the prototype was 0.1 dB.

Figure 37. Deviation from Ideal RIAA Response for

Circuit of Figure 36 Using 1% Resistors

The lower curve is for an output level of 300 mVrms and the upper curve is for an output level of 1 Vrms.

Figure 38. THD of Circuit in Figure 36 as a Function of Frequency

9.3 Typical Application — Reducing Oscillation from High-Capacitive Loads

While all the previously stated operating characteristics are specified with 100-pF load capacitance, the LM833
device can drive higher-capacitance loads. However, as the load capacitance increases, the resulting response
pole occurs at lower frequencies, causing ringing, peaking, or oscillation. The value of the load capacitance at
which oscillation occurs varies from lot-to-lot. If an application appears to be sensitive to oscillation due to load
capacitance, adding a small resistance in series with the load should alleviate the problem (see Figure 39).

9.3.1 Test Schematic

15 V
RO
5V VO
–5 V
–15 V
CL RL = 2 kΩ

Figure 39. Capacitive Load Testing Circuit

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Typical Application — Reducing Oscillation from High-Capacitive Loads (continued)

9.3.2 Output Characteristics
Figure 40 through Figure 45 demonstrate the effect adding this small resistance has on the ringing in the output
signal.

Maximum capacitance Maximum capacitance

before oscillation = 380 pF before oscillation = 590 pF
0.25 V per Division

0.25 V per Division

250 ns per Division 250 ns per Division

Figure 40. Pulse Response Figure 41. Pulse Response

(RL = 600 Ω, CL = 380 pF) (RL = 2 kΩ, CL = 560 pF)

Maximum capacitance
before oscillation = 590 pF
0.25 V per Division

0.25 V per Division

250 ns per Division

250 ns per Division
Figure 42. Pulse Response
(RL = 10 kΩ, CL = 590 pF)
Figure 43. Pulse Response
(RO = 0 Ω, CO = 1000 pF,
RL = 2 kΩ)
0.25 V per Division
0.25 V per Division

250 ns per Division 250 ns per Division

Figure 44. Pulse Response

(RO = 4 Ω, CO = 1000 pF,
Figure 45. Pulse Response
RL = 2 kΩ)
(RO = 35 Ω, CO = 1000 pF,
RL = 2 kΩ)

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10 Power Supply Recommendations

The LM833 is specified for operation from 10 to 36 V (±5 to ±18 V); many specifications apply from –40°C to
85°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.

CAUTION
Supply voltages larger than 36 V can permanently damage the device (see Absolute
Maximum Ratings ).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 46. Operational Amplifier Schematic for Noninverting Configuration

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Layout Example (continued)

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
VS+
away from the supply lines
as possible RF
OUT1 VCC+
RG
GND IN1í OUT2

GND
VIN IN1+ IN2í
RIN
VCCí IN2+
Only needed for Use low-ESR, ceramic
dual-supply bypass capacitor
operation
GND VS-
(or GND for single supply) Ground (GND) plane on another layer

Figure 47. Operational Amplifier Board Layout for Noninverting Configuration

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12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: LM833
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM833D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LM833

LM833DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RSU

LM833DGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 RSU

LM833DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LM833

LM833P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 LM833P

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM833DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
LM833DGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
LM833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM833DGKR VSSOP DGK 8 2500 346.0 346.0 35.0
LM833DGKT VSSOP DGK 8 250 200.0 183.0 25.0
LM833DR SOIC D 8 2500 853.0 449.0 35.0
LM833DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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