EE Con-3
EE Con-3
Engineering Academy
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Electrical Engineering
ESE CONVENTIONAL TEST – III
Time Allowed: 3 Hours Maximum Marks: 200
INSTRUCTIONS
Please read each of the following instructions carefully before
attempting questions.
Candidates should attempt FIVE questions in all. Question No.1 is
compulsory. Out of the remaining SIX questions attempt any FOUR.
All questions carry equal marks.
The number of marks carried by a part of a question is indicated
against it.
Answers must be written in ENGLISH only.
Assume suitable data, if necessary and indicate the same clearly.
Unless otherwise mentioned, symbols and notations have their usual
standard meanings.
Neat sketches may be drawn, wherever required.
All parts and sub-parts of a question are to be attempted together in
the answer book.
Attempts of questions shall be counted in chronological order.
Unless struck off, attempt of a question shall be counted even if
attempted partly.
Any pages left blank in the answer book must be clearly struck out.
1
ESE – Conventional Offline Test-3
01. (a) The following data were obtained on a 20 kVA, 50Hz,
2000/200V distribution transformer:
Voltage Current
Power(W)
(V) (A)
OC test
with HV
200 4 120
open-
circuited
SC test
with LV
60 10 300
short-
circuited
2
Electrical Engineering
(e) A 2200/220 V, 1-phase transformer has maximum possible
voltage regulation of 6% and it occurs at a p.f. of 0.3. Find
the load voltage at full-load at p.f. of 0.8 lead. (4M)
(f) Clearly differentiate between combinational and sequential
circuits. (4M)
(g) Convert following Hex numbers into their equivalent
numbers in base-4 number system. (4M)
(i) 315 (ii) 9E
3
ESE – Conventional Offline Test-3
(j). An 8-bit DAC produces Vout = 0.05 V for a digital input of
00000001. What is the step size of the DAC? What is its
full scale output? What is the percentage resolution? What
is Vout for an input of 00101010? (4M)
(b) Specify the truth table for a half subtractor circuit and
realize the circuit using AND-OR gates. How two half
subtractors can be combined to obtain a full subtractor?
Using half subtractor and full subtractors draw and explain
the block schematic of a 4-bit parallel binary subtractor.
(15M)
(c) Explain the working of a R – 2R ladder DAC and show how
R – 2R DAC converts the binary word 1010101 to an
analog output. Find the magnitude of the output given
Vref = 10 V. (10M)
5
ESE – Conventional Offline Test-3
(c) A 5 kW, 400 V, 50 Hz, 4 pole delta connected 3 –phase
induction motor is supplied by a cable of negligible
inductance. On starting the motor using a star-delta starter,
it is found that the starting toque is same on star as well as
delta connection due to the voltage drop in the feeder
resistance. The equivalent circuit parameters of the motor
are as follows :
R1=1 ohms R2’=1.4 ohms X1=X2’=4.5 ohms
Determine feeder resistance
(i) 5.697 ohms (ii) 6.013 ohms
(iii) 4.981 ohms (iv) 5.378 ohms (12M)
6
Electrical Engineering
(ii) Write the simplified expression for F as a Sum of
products.
(iii)Write the simplified expression for F as a product of
Sums.
(iv)Draw a logic circuit implementation of F using the
minimum number of 2-input NAND gates only.
(10M)
(c) The notation x1x0 represents a two bit binary number that
can have any value (00, 01, 10, or 11); for example, when
x1 = 1 and x0 = 0, the binary number is 10, and so on.
Similarly, y1y0 represents another two bit binary number.
Design a logic circuit, using x1, x0, y1 and y0 inputs, whose
output will be HIGH only when the two binary numbers
x1x0 and y1y0 are equal. (15M)