DIGITAL COMMUNICATIONS LAB

Regulations : AR 17
Course Code : 171EC6L09

Semester : VI Sem
Name :
Roll No :
Section :

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

ADITYA ENGINEERING COLLEGE(A)
 Index
Marks
S. No Name of the Experiment Date and
Signature

1 Phase Shift Keying

2 Differential Phase Shift Keying

3 Frequency Shift Keying

4 Source Encoder and Decoder

5 Linear Block Code - Encoder and Decoder

6 Binary Cyclic Code Encoder and Decoder

Average Marks

Name of the Student :

Roll No :

Signature of the Faculty Signature of the HOD

Dept Seal:
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 1 Phase Shift Keying Date:________________

Aim of the Experiment: Verify the process of Phase shift keying modulation and
demodulation.
Apparatus Required: PSK Trainer Kit, Dural Channel CRO, Probes, Patch cords
Block/Circuit Diagram:

Procedure:
1. Switch ON the trainer and see that the supply LED glows.
2. Observe the carrier output at TP1.
3. Observe the data outputs (D1, D2, D3, D4).
4. Now, connect the carrier output TP1 to the carrier input of PSK modulator TP2 using patch
chord.
5. Connect the D1 to data input of PSK modulator TP3.
6. Observe the Phase shifted PSK output waveform on CRO on channel1 and corresponding
data output on channel 2.
7. Repeat the steps 4,5,6 for data outputs D2, D3, and D4 and observe the PSK outputs.
8. Connect the carrier output TP1 to the PSK input of demodulation TP4.
9. Connect the carrier output TP1 to the carrier input of PSK demodulation TP5.
10. Now, observe the PSK demodulated output at TP7 on CRO at channel1 and corresponding
data output on channel2.

Page 1 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Observations:
Amplitude Time Period Frequency Phase

Carrier Input

Data Input

Options:

D1

D2

D3

D4

PSK Output

For Logic 1

For Logic 0

Demodulated
Output

Result:

Note: Attach 1 graph sheet for this experiment

Page 2 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 2 Differential Phase Shift Keying Date:________________

Aim of the Experiment: Verify the operation of Differential phase shift keying Modulation
and Demodulation
Apparatus Required: DPSK Trainer Kit, Dural Channel CRO, Probes, Patch cords
Block/Circuit Diagram:

Procedure:
1. Connect clock output TP1 to the clock input of the DPSK modulator TP8.
2. Now Connect carrier output TP2 to the carrier input of the DPSK modulator TP10.
3. Observe the Differential Data output on the CRO at TP9 test point as shown on the front panel.
4. Observe the Phase shifted DPSK output waveform on the CRO corresponding to the differential
data output.
5. Connect DPSK MODULATOR output TP11 to the DPSK input of the DEMODULATOR
TP12.
6. Connect carrier output TP2 to the Carrier input of the DPSK Demodulator TP13.
7. Also connect clock output TP1 to the clock input of the DPSK demodulator TP14.
8. Now observe the DPSK demodulated output waveform TP15 on the CRO.

Page 3 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Observations:
Amplitude Time Period Frequency Phase

Carrier Input

Data Input

Options:

D1

D2

D3

D4

DPSK Output

Logic 0

Logic 1

Demodulation
Output

Result:

Note: Attach 1 graph sheet for this experiment

Page 4 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 3 Frequency Shift Keying Date:________________

Aim of the Experiment: Observe the process of Frequency shift keying modulation and
demodulation.
Apparatus Required: FSK Trainer Kit, Dual Channel DSO, Probes, Patch cords
Block/Circuit Diagram:
FSK Transmitter

FSK Receiver

Page 5 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Procedure:
1. Set the frequency of the message signal to 100 Hz or 200 Hz
2. Without applying the message signal find the VCO output (free running frequency) as a
carrier signal
3. Now apply the message signal to the input of the VCO (FSK modulator)
4. Find the high and low frequencies w.r.t. logic 1 and 0 of the message and identify the
frequency shift.
5. Now apply the FSK output to the FSK demodulator input, tune the demodulator in order to
achieve the demodulated signal similar to the message signal.
6. For the entire process use the DSO (Digital Storage Oscilloscope)

Observations:
Amplitude Time Period Frequency

Message Signal

Carrier Signal (VCO

Output without
message signal)
FSK Output

For Logic 1

For Logic 0

Frequency Shift

Demodulated Output

Result:

Note: Attach 1 graph sheet for this experiment

Page 6 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 4 Source Encoder and Decoder Date:________________

Aim of the Experiment: Minimize coding redundancy using Source Encoder and Decoder
Apparatus Required: Source Encoder Trainer Kit with power supply
Block/Circuit Diagram:

Procedure:
1. The five source symbols A B R D K are given with predefined probabilities
2. Find the code book for these source symbols without any source coding (normal mode)
3. Find the code book for these source symbols with source encoding (coding mode)
4. Note: the kind of source coding used: huffmen encoding
5. Find the average codeword length.
6. For the entire process use the following message
“A B R A K A D A B R A”

Page 7 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Observations:

Codeword without Code word with

Probability of the
Source Symbol coding source coding
source symbol
(Normal mode) (Code mode)

R
Average codeword
----
length

Perform Huffman coding here (Manually)

Result:

Page 8 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 5 Linear Block code- Encoder and Decoder Date:____________

Aim of the Experiment: Perform error detection and correction using Linear Block Code-
Encoder and Decoder
Apparatus Required: Linear Block Code Trainer Kit with power supply
Block/Circuit Diagram:

Procedure:
1. Generate a 4 bit message in normal mode, encode it and decode it without any error
2. Generate a 4 bit message in normal mode, encode it create a 1 bit or 2 bit error(s) decode the
message observe the decoded message at receiver w.r.t. message sent at the transmitter.
3. Generate a 4 bit message in code mode, encode it and decode it without any error, identify the
systematic block code word in terms of message and parity bits
4. Repeat the step no. 3 for a single bit error and observe that, the decoder is capable of
detecting and correcting 1 bit error
5. Repeat step no. 3 for two bit errors and observe that, the decoder is capable of detecting 2 bit
errors and but unable to correct the errors
6. Generate the code book for the all possible 4 bit messages

Page 9 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Observations:

Code word Error

Transmitted with and Received Decoded detecting and
Message
code word without codeword message correcting
errors capability
Normal
mode
without
error
Normal
mode with
1 bit error
Normal
mode with
2 bit errors
Code mode
without
error
Code mode
with
1 bit error
Code mode
with
2 bit erros

Code Book:

Message Code Word Message Code Word

0000 1000

0001 1001

0010 1010

0011 1011

0100 1100

0101 1101

0110 1110

0111 1111

Page 10 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Manual Calculations:
The Generator Matrix: (as per the kit design)
𝟎 𝟏 𝟏 𝟏 𝟎 𝟎 𝟎
𝟏 𝟎 𝟏 𝟎 𝟏 𝟎 𝟎
𝑮= [ ]
𝟏 𝟏 𝟎 𝟎 𝟎 𝟏 𝟎
𝟏 𝟏 𝟏 𝟎 𝟎 𝟎 𝟏

Result:

Page 11 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Experiment No: 5 Cyclic code- Encoder and Decoder Date:____________

Aim of the Experiment: Perform error detection and correction using Binary Cyclic Code –
Encoder and Decoder
Apparatus Required: Cyclic Code Trainer Kit with power supply
Block/Circuit Diagram:

Procedure:
1. Generate a 4 bit message in normal mode, encode it and decode it without any error
2. Generate a 4 bit message in normal mode, encode it create a 1 bit or 2 bit error(s) decode the
message observe the decoded message at receiver w.r.t. message sent at the transmitter.
3. Generate a 4 bit message in code mode, encode it and decode it without any error, identify the
systematic block code word in terms of message and parity bits
4. Repeat the step no. 3 for a single bit error and observe that, the decoder is capable of
detecting and correcting 1 bit error
5. Repeat step no. 3 for two bit errors and observe that, the decoder is capable of detecting 2 bit
errors and but unable to correct the errors
6. Generate the code book for the all possible 4 bit messages

Page 12 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Observations:

Code word Error

Transmitted with and Received Decoded detecting and
Message
code word without codeword message correcting
errors capability
Normal
mode
without
error
Normal
mode with
1 bit error
Normal
mode with
2 bit errors
Code mode
without
error
Code mode
with
1 bit error
Code mode
with
2 bit erros

Code Book:

Message Code Word Message Code Word

0000 1000

0001 1001

0010 1010

0011 1011

0100 1100

0101 1101

0110 1110

0111 1111

Page 13 of 14
Digital Communications Lab Dept. of ECE, Aditya Engineering College (A)

Manual Calculations:
The Generator Polynomial: (as per the kit design)
𝑮(𝒙) = 𝟏 + 𝒙 + 𝒙𝟑

Result:

Page 14 of 14