SMACD 2019, Lausanne, Switzerland EDA Competition

Automated Parameter Extraction and SPICE Model

Modification For Gate Enclosed MOSFETs
Simulation
Boris Contreras, Gladys Ducoudray, Rogelio Palomera, Carlos Bernal
Department of Electrical and Computer Engineering
University of Puerto Rico at Mayagüez
Mayagüez, Puerto Rico 00681
Email: boris.contreras@upr.edu

Abstract—This work focuses in using experimental measure- for circuit simulation, predict the I-V behavior of a system
ments to extract the aspect ratio (W/L) for Gate-Enclosed or before it enters the production cycle.
Annular MOSFETs. All measurements and calculations are
Transistor geometry aspect ratio (W/L) calculation or ex-
performed with an automated virtual instrumentation (VI)
environment developed in LabVIEW. The VI was capable of traction, is an important factor for MOS devices modeling,
extracting threshold voltage and low field mobility, needed for W/L since many electrical equations for MOSFETs depend on the
calculation. An extraction procedure for the body effect factor is W/L. This equations have been well developed and validated
also presented. For validation purposes, extracted parameters for traditional MOSFETs that have symmetric diffusion (drain
were compared with those provided by the foundry (MOSIS)
and source) areas. For MOSFETs with asymmetrical geometry,
using traditional rectangular transistors. The extracted W/L was
validated by comparing to Giraldo’s experimental method. The size effects on devices performance are not easily extracted.
SPICE BSIM 3 model parameters provided by the foundry An example of a non symmetrical geometry transistor is
is then modified using the extracted parameters including the the annular or gate-enclosed MOSFET. Figure 1 shows an
aspect ratio. With this modification better simulation results were annular MOSFET layout where the gate (G), drain (D), source
obtained. They were compared to the experimental measurements
(S), bulk (B) channel length (L) and inner width (W) are
for an annular MOSFET drain voltage vs drain current character-
istic curves at different gate voltages, showing an improvement of identified. These type of transistors are designed to increase
58% when compared to the original non modified SPICE model
parameters.
G
I. I NTRODUCTION
B
Computer aided design tools are indispensable for integrated
circuit (IC) design. Automation of post-fabrication processes L
D
is a strong determinant on the cost of IC design. These
processes have evolved substantially to reduce characterization Inner W

and simulation time [1]. S

Current and voltage (I-V) characteristics of devices are
important for an adequate model development. There are
three types of compact models for Metal-Oxide Semiconductor
Field-Effect Transistors (MOSFETs): Fig. 1. Annular/Gate Enclosed Transistor Layout Example
• Physical, based on device physics.
• Empirical which relies in curve fitting, with parameters performance in harsh environments due to their tolerance to
(coefficients, exponents used in the curve fitting with no radiation. Traditional MOSFETs radiation failure is observed
physical significance). at lower exposure due to trapped charges in the thin gate oxide,
• Tables with measured drain current values for different which can cause a leakage current increment [3] or threshold
bias voltages. This model is less time consuming since voltage shift. This type of radiation hardening technique shown
the values are stored in an array and the computer just in [4] shows greater Total Ionizing Dose (TID) tolerance of
looks for the value in a table. MRAD(SiO2 ) levels when compared to traditional transistors,
using commercial technologies.
Each model type mentioned before refers to the approach used
for calculating device parameters [2]. Compact models used Modeling the electrical response of annular MOSFETs
presents more challenges than traditional transistors due to
its asymmetric geometry [3]. For example when the drawn
c
978-1-7281-1201-5/19/$31.00 2019 IEEE layout is extracted in a simulator like Cadance Virtuosor , the

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Paper S105 SMACD 2019, Lausanne, Switzerland

equivalent transistor drain current compared with experimental current (ISpec ) are calculated as follow: The equilibrium
data is 3 to 4 times bigger. This shows the importance of a threshold voltage (VT 0 ) is the gate voltage VG where gm /ID
proper aspect ratio W/L calculation. Some analytical solutions is approximately 50% of its maximum value. This is for a
to calculate aspect ratio are presented in [5], [6], [7] and [8]. VDS ∼ =13mV, congruent to half thermal voltage (Vt ≈ 26mV,
This paper presents an automated experimental aspect ratio at 300K). Both parameters are extracted using this VDS value.
W/L calculation. Using low field mobility µ0 and threshold For VT H , a VDS of 50mV is used to guarantee triode region.
voltage (VT H ) extraction as key parameters to successfully Both VT 0 and VT H are extracted in the same manner. The
extract the W/L of annular or gate-enclosed transistor. The VT H is validated with the foundry provided for specific
Body Effect Factor (γ) was also extracted, in conjunction with Rectangular MOSFETs sizes.
the previous parameters including W/L, were then modified 2) µ0 Extraction: After successfully extracting VT H , Low
in the SPICE BSIM 3 model parameters provided by the Field Mobility (µ0 ) is calculated from a standard rectangular
foundry to enhance the simulated vs experimental comparison. transistor with known W/L using its transconductance in the
PMOS MOSFETs were not considered, because holes are less triode region and derived equations from [11].
mobile and the charge accumulated in the oxide will push
gm [1 + θ(VGS − VT H )2 ]L
the n-substrate or n-well into accumulation without danger µ0 = (2)
of inversion layer formation [9]. A detailed explanation of W Cox VDS
the parameters extraction is presented in section II. Hardware The mobility reduction factor θ was calculated as follows
setup and test automation using LabVIEWT M are shown in
[ gm (VGIS−V
D
− 1]
section III. Finally, results and conclusions are showed in IV θ= TH)
(3)
and V. (VGS − VT H )

II. E XPERIMENTAL PARAMETERS E XTRACTION B. Width over Length Calculation

There are several approaches to calculate W/L of gate With VT H and µ0 , the aspect ratio (W/L) of an annular
enclosed (GE) transistor as mentioned before. Giraldo et al. [8] MOSFET is obtained using ID equation for triode region.
compared gate-enclosed transistors and standard MOSFETs W
ID ≈ µef f Cox · (VGS − VT H )VDS (4)
using the same gate length, and assuming µCox to be equal for L
both devices. Standard and GE transistors transconductances Where
were calculated using measured drain current when transistor µ0
µef f = (5)
operates in triode region. The GE W/L was extracted using 1 + θ(VGS − VT H )
the following formula (1). Equation (4) is an approximation valid for VDS  2(VGS −
 enc  std enc VT H ) [12].
W W gm
= 1
(1) Solving (4) for W/L gives
L L std
ef f ef f gm
W ID
Using the same gate length could be a disadvantage, if there = (6)
L µef f Cox · (VGS − VT H )VDS
isn’t a standard MOSFET with this parameter to compare it to.
The length presents a challenge for annular or gate enclosed C. The Body Effect Factor (Gamma-γ)
transistors because in most asymmetric geometries L is not From the threshold voltage at equilibrium VT 0 and specific
constant and increasing the channel length increases its width current (ISpec ), a parameter called slope factor (n) (from EKV
and area. The proposed solution assumes µ0 is equal for model) can be extracted to determine body effect factor (γ)
annular and standard transistors. In this paper GE transistor and bulk Fermi potential (φF ) (calculation of n is shown in
W/L experimental extraction is independent of the standard [13]). The calculation of n needs a pinch-off voltage (VP )
MOSFET gate length for the µ0 extraction (any gate length can which is equal to source voltage (VS ) when the normalized
be used for the µ0 extraction). The Threshold Voltage (VT H ) forward current if = 3 in equation 7 [10]. The current ratio if
and Low Field Mobility (µ0 ) were needed to achieve the aspect = ID/ISP EC , also since if is greater than one, this guarantees
ratio calculation from experimental data. The extraction of the MOSFET operates in the saturation region, therefore the
these is described below. All the measurements were made slope factor will be greater than 1, as shown in equation 8.
with the transistors operating in the triode region.
VP − VS p p
A. Threshold Voltage (VT H ) and Low Field Mobility (µ0 ) = 1 + if − 2 + ln( 1 + if − 1) (7)
φt
Extraction
Since if = ID /ISpec , then ID needs to be three times ISpec to
1) VT H Extraction: For equilibrium threshold voltage meet the requirements for VP = VS .
(VT 0 ), transconductance to current ratio method (gm /ID ) is Equation 8 is used to calculate the slope factor n from
used to determine a set of first order DC Parameters for MOS experimental measurements of VP and VG .
Transistors as described in [10]. The VT H and the specific
1
1 enc
n= dVP
(8)
= annular/enclosed, std = Standard, eff= effective ( dV )
G

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SMACD 2019, Lausanne, Switzerland EDA Competition

VDD

3IS
A

USB
VD VG V
Ud

USB
2612A To 2612A
GPIB

VS
VG
GPIB GPIB

CHAN CHAN CHAN CHAN

BNC B A
BNC B
A
To To
SMA GATE SOURCE SMA
(a) (b) BODY
DRAIN

Fig. 2. Parameter Extraction Schematics: (a) VT H , VT 0 , ISpec µ0 and W/L

DUT
extraction DUT setup. (b) Slope Factor n, Body Effect Factor (γ) and Bulk
Fermi Potential (φF ) extraction DUT setup
Fig. 3. Parameter Extraction Setup and Test Board

The slope factor n can also be expressed as: Keithley Setup Vth Extraction

R e s e t K 1 (True) R e s e t K 2 (True)

γ True
K1
True
K2

(9)
GPIB0::28::INSTR GPIB0::29::INSTR

n=1+ √ Out Chan B (Gate) Out Chan A (Drain) Out Chan A (Source) Out Chan B (Bulk)

(2 2φF + VP )
ON ON
ON ON

Start 0 Drain Voltage 0.05

Solving equation 9 for γ and φF gives

Number of Runs
Gate Voltage 0.01 Source Voltage 0
Step Size 30

End 1.5 Run # Bulk Voltage 0

30

Drain Current (A) vs Gate Voltage (V)

1 4VP 8φF 4.5E-6

4.25E-6

= 2 + 2 (10) 4E-6

3.75E-6

(n − 1)2 γ γ
3.5E-6

3.25E-6

3E-6

2.75E-6

2.5E-6

From 10 and using a linear regression between 1

and
2.25E-6

2E-6

(n−1)2 1.75E-6

1.5E-6

VP , γ and 2φF can be calculated.

1.25E-6

1E-6

7.5E-7

5E-7

2.5E-7

III. H ARDWARE S ETUP AND L AB VIEW TM

AUTOMATION
0 2
VG (V)

A. Hardware Setup
The connections needed for parameter extraction are not Fig. 4. VT 0 , ISpec and µ0 and W/L extraction DUT setup.
complex as can be seen in Figures 2(a) and 2(b). The
schematic in Figure 2 was used to perform all the mea-
surements for VT H , µ0 and W/L extractions. Two Keithley IV. R ESULTS
SourceMetersr 2612A were selected to source voltage and The results obtained from experimental measurements with
measure current, controlled via GPIB with LabVIEWT M using LabVIEWT M parameter extraction were compared with MO-
a USB to GPIB adapter. SIS (VT H , µ0 and γ). The gm ratio [8] procedure (aspect ratio
A test board was designed using [14] guidelines to interface - W/L) was used to validate the aspect ratio solution presented
the Keithley SourceMetersr with the device under test (DUT). in this paper.
The MOSFETs or DUTs were fabricated by MOSIS in AMI
0.6µm process (6 rectangular and 4 annular MOSFETs) on
5 different ICs, for a total of 30 rectangular and 20 anular TABLE I
MOSFETs. Figure 3 shows the proposed setup for commu- T HRESHOLD VOLTAGE VT H AND G AMMA -γ(V 0.5 )
nication between test board, Keithley SourceMetersr and VT H
LabVIEWT M Automated Extraction
W/L MOSIS (Average of 30 Samples) Error
B. LabVIEWT M Automation 50µm/50µm 0.72 0.720072 0.010%
20µm/0.6µm 0.7 0.700054 0.008%
The time required for data manipulation in automated test γ
compared to a manual procedure is reduced. By implementing 50µm/50µm 0.47 0.467484333 0.535%
equations 2, 3, 5 and 6, 8 and 10 for VT 0 , ISpec , µ0 and W/L,
n, γ and φF extraction in LabVIEWT M , human intervention TABLE II 2
is minimized for a faster extraction [6]. This was made using L OW F IELD M OBILITY µ0 ( Vm·s )
MathScripts which can be interpreted as a basic MATLABr
Automated Extraction
compiler. Figure 4 shows an example of the graphical user MOSIS W/L (Average of 30 Samples) Error
interface (GUI) used to perform the automated parameter 0.045116292
50µm/50µm 0.042999745 4.691%
extractions. 20µm/0.6µm 0.042843005 5.039%

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Paper S105 SMACD 2019, Lausanne, Switzerland

TABLE III
Annular MOSFET Experimental vs Original Simulated
S TANDARD MOSFET S
SPICE Model and Modified Simulated SPICE Model
Drawn Ideal Experimental Percentage Characteristics Curves
W/L Aspect Ratio Calculation Error 0,003
50µm/50µm 1 1.029464743 2.946%
20µm/0.6µm 33.3 34.42445082 3.377% 0,0025
7.8µm/1.2µm 6.5 6.456807864 0.664% VG 1.8V E

Drain Current (A)

6.6µm/1.2µm 5.5 5.629206547 2.349% 0,002 VG 1.8V O
5.4µm/1.2µm 4.5 4.424032103 1.688% VG 1.8V M
4.2µm/1.2µm 3.5 3.156328468 9.819% 0,0015
VG 2.4V E
0,001 VG 2.4V O
TABLE IV VG 2.4V M
A NNULAR MOSFET A SPECT R ATIO E XTRACTION . 0,0005 VG 3V E
VG 3V O
gm R ATIO [8] VS . L AB VIEWT M E XPERIMENTAL E XTRACTION 0
VG 3V M

0
0,17
0,34
0,51
0,68
0,85
1,02
1,19
1,36
1,53
1,7
1,87
2,04
2,21
2,38
2,55
2,72
2,89
Drawn gm Experimental Percentage Drain Voltage (V)
Inner W/L Ratio Calculation Difference Inner W = 2.7µm L= 1.2µm
1.2µm/1.2µm 7.897002219 8.018019726 1.532%
2.7µm/1.2µm 14.48994568 15.23022938 5.109%
3.3µm/2.4µm 10.94207621 10.41770821 4.792% Fig. 5. Experimental and Simulated ID vsVD at Different VG Curves -
7.5µm/1.2µm 31.83949757 30.8897649 2.983% Annular MOSFET (Inner W 2.7µm L 1.2µm)

Table I and II show a comparison between MOSIS compared to the original provided SPICE model parameters,
(Foundry) and experimental parameter extraction using allowing further simulations using commercial software.
LabVIEWT M , with a VT H error < 0.1% and γ. For µ0 an
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