Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope using VDS Drain-source voltage 55 V
’trench’ technology. The device ID Drain current (DC) 64 A
features very low on-state resistance Ptot Total power dissipation 140 W
and has integral zener diodes giving Tj Junction temperature 175 ˚C
ESD protection up to 2kV. It is RDS(ON) Drain-source on-state 16 mΩ
intended for use in switched mode resistance VGS = 10 V
power supplies and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
d
tab
1 gate

2 drain
g
3 source

tab drain 1 23 s

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ - 55 V
±VGS Gate-source voltage - - 20 V
ID Drain current (DC) Tmb = 25 ˚C - 64 A
ID Drain current (DC) Tmb = 100 ˚C - 45 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 210 A
Ptot Total power dissipation Tmb = 25 ˚C - 140 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VC Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 1.1 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient

February 1999 1 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2 3.0 4.0 V
Tj = 175˚C 1 - - V
Tj = -55˚C - - 4.4 V
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - - 20 µA
±V(BR)GSS Gate-source breakdown IG = ±1 mA; 16 - - V
voltage
RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 12 16 mΩ
resistance Tj = 175˚C - - 30 mΩ

DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 25 A 8 39 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2200 2900 pF
Coss Output capacitance - 500 600 pF
Crss Feedback capacitance - 200 270 pF
Qg(tot) Total gate charge ID = 50 A; VDD = 44 V; VGS = 10 V - - 85 nC
Qgs Gate-source charge - - 19 nC
Qgd Gate-drain (Miller) charge - - 37 nC
td on Turn-on delay time VDD = 30 V; ID = 25 A; - 18 26 ns
tr Turn-on rise time VGS = 10 V; RG = 10 Ω - 35 85 ns
td off Turn-off delay time Resistive load - 45 60 ns
tf Turn-off fall time - 30 45 ns
Ld Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
Ld Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Ls Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad

February 1999 2 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - 64 A
current
IDRM Pulsed reverse drain current - - 210 A
VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 65 A; VGS = 0 V - 1.0 - V
trr Reverse recovery time IF = 65 A; -dIF/dt = 100 A/µs; - 57 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.14 - µC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 65 A; VDD ≤ 25 V; - - 200 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD% Normalised Power Derating ID% Normalised Current Derating

120 120
110 110
100 100
90 90
80 80
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
Tmb / C Tmb / C
Fig.1. Normalised power dissipation. Fig.2. Normalised continuous drain current.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V

February 1999 3 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

SOAX514 RDS(ON)/mOhm
1000 30
VGS/V = 6
6.5
ID / A 25
tp =
1 us 7
RDS(ON) = VDS/ID
100 10 us 20
8
100 us 9
15 10
DC 1 ms
10 10
10 ms
100 ms 5

1 0
1 10 55 100 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
VDS / V ID/A

Fig.3. Safe operating area. Tmb = 25 ˚C Fig.6. Typical on-state resistance, Tj = 25 ˚C.
ID & IDM = f(VDS); IDM single pulse; parameter tp RDS(ON) = f(ID); parameter VGS

BUKX514-55 100
Zth / (K/W)
1E+01
ID/A

80
1E+00
0.5
60
0.2
1E-01 0.1
0.05
tp 40
PD tp D=
0.02 T
1E-02 Tj/C = 175 25
0 T t 20

1E-03 0
1E-07 1E-05 1E-03 1E-01 1E+01 0 1 2 3 4 5 6 7 8 9
t/s VGS/V

Fig.4. Transient thermal impedance. Fig.7. Typical transfer characteristics.

Zth j-mb = f(t); parameter D = tp/T ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

100 40
16 8
ID/A gfs/S
10 7.5 VGS/V = 7 35
80
30
6.5
60 25

20
6
40
15
5.5
10
20
5
5
4.5
0 4 0
0 2 4 VDS/V 6 8 10 0 20 40 ID/A 60 80 100

Fig.5. Typical output characteristics, Tj = 25 ˚C. Fig.8. Typical transconductance, Tj = 25 ˚C.

ID = f(VDS); parameter VGS gfs = f(ID); conditions: VDS = 25 V

February 1999 4 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

BUK959-60 Rds(on) normlised to 25degC 4

a
2.5
3.5

3
2

Thousands (pF)
2.5

Ciss
1.5 2

1.5

1 1

5
Coss
0.5 Crss
-100 -50 0 50 100 150 200 0
0.01 0.1 1 VDS/V 10 100
Tmb / degC

Fig.9. Normalised drain-source on-state resistance. Fig.12. Typical capacitances, Ciss, Coss, Crss.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

VGS(TO) / V BUK759-60 12
5
VGS/V
max. 10
4 VDS = 14V
VDS = 44V
typ. 8
3
6
min.
2
4

1
2

0
-100 -50 0 50 100 150 200 0
Tj / C 0 10 20 30 QG/nC 40 50 60

Fig.10. Gate threshold voltage. Fig.13. Typical turn-on gate-charge characteristics.

VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS VGS = f(QG); conditions: ID = 50 A; parameter VDS

Sub-Threshold Conduction 100

1E-01
IF/A

80
1E-02

60
2% typ 98%
1E-03
Tj/C = 175 25
40
1E-04

20
1E-05

0
1E-06 0 0.2 0.4 0.6 0.8 1 1.2 1.4
0 1 2 3 4 5 VSDS/V

Fig.11. Sub-threshold drain current. Fig.14. Typical reverse diode current.

ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

February 1999 5 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

WDSS%
120
VDD
110 +
100 RD
90
80 VDS
70
VGS
-
60
50 RG
0 T.U.T.
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.17. Switching test circuit.
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A

VDD
+
L

VDS

VGS
-
-ID/100
0 T.U.T.

R 01
RGS
shunt

Fig.16. Avalanche energy test circuit.

WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )

February 1999 6 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

MECHANICAL DATA

Dimensions in mm
4,5
Net Mass: 2 g max
10,3
max
1,3
3,7

2,8 5,9
min

15,8
max

3,0 max
3,0
not tinned
13,5
min
1,3
max 1 2 3
(2x) 0,9 max (3x)
0,6
2,54 2,54 2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".

February 1999 7 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOSTM transistor

DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

February 1999 8 Rev 1.000